<s> bool spu_legitimate_constant_p ( machine_mode mode , rtx x ) { subrtx_iterator :: array_type array ; if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , <NUM_LIT> ) ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) if ( ea_symbol_ref_p ( * iter ) ) return <NUM_LIT> ; if ( ! flag_pic && mode == V4SImode && ( GET_CODE ( CONST_VECTOR_ELT ( x , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( CONST_VECTOR_ELT ( x , <NUM_LIT> ) ) == LABEL_REF || GET_CODE ( CONST_VECTOR_ELT ( x , <NUM_LIT> ) ) == CONST ) ) return const_vec_duplicate_p ( x ) ; if ( GET_CODE ( x ) == CONST_VECTOR && ! const_vector_immediate_p (


<s> if ( isDarwinABI || is<ISA_LIT>64 ) return <NUM_LIT> * ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; return


<s> unsigned getCurrGroupSize ( ) { return


<s> StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && Subtarget . hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; MachineMemOperand * MMO = nullptr ; for ( auto * I : MI . memoperands ( ) ) if ( I -> isStore ( ) ) { MMO = I ; break ; } BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . add ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB


<s> return sparc_function_value_1 ( valtype , TYPE_MODE ( valtype ) ,


<s> getTTypeGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { assert ( Encoding == DW_EH_PE_absptr && <STR_LIT>


<s> static bool is_fmul_op ( enum attr_type t ) { return ( t == TYPE_FMULS ) || ( t == TYPE_FMULD ) ||


<s> void addStringImm ( const StringRef & Str , IRBuilder < > & B , std :: vector < Value * > & Args ) { const size_t PaddedLen = getPaddedLen ( Str


<s> ValueVect BO ; BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ; for ( auto DTN : children < DomTreeNode * > ( DT -> getNode ( B ) )

) BO . push_back ( DTN -> getBlock ( ) ) ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool isMemImm8s4Offset ( ) const { if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment !=


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && Offs == <NUM_LIT> ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; } if ( Offs < <NUM_LIT> ) Offs


<s> rtx_insn * insn ; sparc_leaf_function_p = optimize > <NUM_LIT> && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > <NUM_LIT> ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == <NUM_LIT> ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7 ) ; } } if (


<s> static AddrMode DecodeSrcAddrModeII ( unsigned Insn ) { unsigned Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned As = fieldFromInstruction ( Insn , <NUM_LIT>


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; Len &= <NUM_LIT> ; Idx &= <NUM_LIT> ; if ( <NUM_LIT> != ( Len % EltSize ) || <NUM_LIT> != ( Idx % EltSize ) ) return ; if ( Len == <NUM_LIT> ) Len = <NUM_LIT> ; if ( ( Len + Idx ) > <NUM_LIT> ) { ShuffleMask . append ( NumElts , SM_SentinelUndef ) ; return ; } Len /= EltSize


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SVCR .


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += LaneSize ) { for ( unsigned i = <NUM_LIT> ; i != LaneSize ; ++ i ) { if ( ! isUndefOrInRange ( Mask [ i + l ] , l , l + LaneSize ) ) return false ; if ( NumElts != <NUM_LIT> || l == <NUM_LIT> ) continue ; if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Mask [ i + l ] , Mask [ i ] + l ) ) return false ; } } return


<s> unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( Size == <NUM_LIT> ) && ! Subtarget -> isMClass


<s> break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value : Op -> op_values ( ) ) { Entry . Node = Value ; Entry . Ty = Value . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsSExt = IsSigned ; Entry . IsZExt = ! IsSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ; SDLoc dl (


<s> if ( VT . getSizeInBits ( ) >= <NUM_LIT> ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } unsigned ScalarSize = Ld . getValueType ( ) . getSizeInBits ( ) ; bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) -> optForSize ( ) ; if ( ConstSplatVal && ( Subtarget . hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget . hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , Alignment ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; } } bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; if ( ! IsLoad && Subtarget . hasInt256 ( ) && ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; if ( ! IsLoad ) return SDValue ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( Subtarget . hasVLX ( ) && ScalarSize == <NUM_LIT>


<s> } else if ( ! ix86_contains_aligned_value_p ( type ) ) align = PARM_BOUNDARY ; if ( align < <NUM_LIT> ) align = PARM_BOUNDARY ; } if ( warn_psabi && ! warned && align != ix86_compat_function_arg_boundary ( mode , type , saved_align ) ) { warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , align / BITS_PER_UNIT ) ; } } return


<s> for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) Change |= HandleConstantPoolUser ( Fn , i ) ; DEBUG ( dumpBBs ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) Change |= FixUpImmediateBr ( Fn , ImmBranches [ i ] ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! Change ) break ; MadeChange = true ; } verify ( Fn ) ; if ( ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) && isThumb ) MadeChange |= UndoLRSpillRestore ( ) ; BBSizes . clear ( ) ; BBOffsets . clear (


<s> return MFI -> getShaderType ( ) != ShaderType :: COMPUTE && usesVertexCache ( MI ->


<s> if ( n >= <NUM_LIT> ) abort ( ) ; arg = default_conversion ( arg ) ; type = TREE_TYPE ( arg ) ; if ( POINTER_TYPE_P ( type ) && TREE_CODE ( arg ) == NOP_EXPR && lang_hooks . types_compatible_p ( TREE_TYPE ( arg ) , const_ptr_type_node ) && lang_hooks . types_compatible_p ( TREE_TYPE ( TREE_OPERAND ( arg , <NUM_LIT> ) ) , ptr_type_node ) ) { arg = TREE_OPERAND ( arg , <NUM_LIT> ) ; type = TREE_TYPE ( arg ) ; } if ( POINTER_TYPE_P ( decl_type ) && POINTER_TYPE_P ( type ) && TYPE_QUALS ( TREE_TYPE ( type ) ) != <NUM_LIT> ) { if ( TYPE_READONLY ( TREE_TYPE ( type ) ) && ! TYPE_READONLY ( TREE_TYPE ( decl_type ) ) ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , n + <NUM_LIT> , fndecl ) ; type = build_pointer_type ( build_qualified_type ( TREE_TYPE ( type ) , <NUM_LIT> ) ) ; arg = fold_convert ( type , arg ) ; } args [ n ] = arg ; types [ n ] = type ; } if ( ! VOID_TYPE_P ( TREE_VALUE ( fnargs


<s> if ( ix86_find_max_used_stack_alignment ( stack_alignment , stack_realign ) ) { stack_realign = incoming_stack_boundary < stack_alignment ; if ( ! stack_realign ) { crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> preferred_stack_boundary = incoming_stack_boundary ; } } else { if ( crtl -> drap_reg ) { basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; if ( ! REGNO_REG_SET_P ( DF_LR_IN ( bb ) , REGNO ( crtl -> drap_reg ) ) ) { crtl -> drap_reg = NULL_RTX ; crtl -> need_drap = false ; } } else cfun -> machine -> no_drap_save_restore = true ; frame_pointer_needed = false ; stack_realign = false ; crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> stack_alignment_estimated = incoming_stack_boundary ; if ( crtl -> preferred_stack_boundary > incoming_stack_boundary ) crtl -> preferred_stack_boundary = incoming_stack_boundary ; df_finish_pass ( true ) ; df_scan_alloc ( NULL ) ; df_scan_blocks ( ) ; df_compute_regs_ever_live ( true ) ; df_analyze ( ) ; if ( flag_var_tracking ) { df_ref ref , next ; for ( ref = DF_REG_USE_CHAIN ( HARD_FRAME_POINTER_REGNUM ) ; ref ; ref = next


<s> void <ISA_LIT>InstPrinter :: printAdrpLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { O << <STR_LIT> << ( Op . getImm ( )


<s> if ( ( GV -> hasSection ( ) && StringRef ( GV -> getSection ( ) ) . startswith ( <STR_LIT> ) ) || ( GVar && GVar -> isConstant ( ) && GV -> hasLocalLinkage ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA


<s> static bool isVInterp ( unsigned Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode


<s> } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget -> hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget -> hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops (


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> CLEAR_HARD_REG_SET ( full_reg_clobbers ) ; SET_HARD_REG_BIT ( full_reg_clobbers , R0_REGNUM ) ; SET_HARD_REG_BIT ( full_reg_clobbers , CC_REGNUM ) ; for ( int regno = P0_REGNUM ; regno <= P15_REGNUM ; ++ regno ) SET_HARD_REG_BIT ( full_reg_clobbers , regno ) ; tlsdesc_abi . initialize ( ARM_PCS_TLSDESC , full_reg_clobbers ) ; } return tlsdesc_abi . id (


<s> static void \ switch_to_section ( enum in_section section , tree decl ) \ { \ switch ( section ) \ { \ case in_text : text_section ( ) ; break ; \ case in_unlikely_executed_text : unlikely_text_section ( ) ; break ; \ case

in_data : data_section ( ) ; break ; \ case in_named : named_section ( decl , NULL , <NUM_LIT> ) ; break ; \ SUBTARGET_SWITCH_SECTIONS \ default : gcc_unreachable ( ) ; \ } \ }


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_AV_64 (


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return


<s> DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; NumBytes = ( NumBytes + <NUM_LIT> ) & ~ <NUM_LIT> ; MFI -> setStackSize ( NumBytes ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , - VARegSaveSize ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset


<s> OperandMatchResultTy parseGR128 ( OperandVector & Operands ) { return parseRegister ( Operands , RegGR , <STR_LIT> , GR128Reg


<s> B . setInstr ( MI ) ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( Src ) == S64 ) ; auto Trunc = B . buildIntrinsicTrunc ( S64 , Src ) ; const auto Zero = B . buildFConstant ( S64 , <NUM_LIT> ) ; const auto One = B . buildFConstant ( S64 , <NUM_LIT> ) ; auto Lt0 = B . buildFCmp ( CmpInst :: FCMP_OGT , S1 , Src , Zero ) ; auto NeTrunc = B . buildFCmp ( CmpInst :: FCMP_ONE , S1 , Src , Trunc ) ; auto And = B . buildAnd (


<s> void <ISA_LIT>BranchFixup :: dumpBBs ( ) { DEBUG ( { for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned

( BBI . Unalign ) << format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> return RegIdx . RegInfo -> getRegClass ( <STR_LIT> ) . getRegister (


<s> SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MaybeAlign InferredAlign = DAG . InferPtrAlign ( Ptr ) ; if ( ! InferredAlign || * InferredAlign < RequiredAlign ) { if ( MFI . isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI . setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign . value ( ) ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ int64_t ( RequiredAlign . value ( ) - <NUM_LIT> ) ; if ( StartOffset ) { SDLoc DL ( Ptr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset


<s> auto & RAB = static_cast < <ISA_LIT>AsmBackend & > ( Layout -> getAssembler ( ) . getBackend ( ) ) ; if ( RAB . willForceRelocations ( ) ) return false ; MCValue AUIPCLoc ; if ( ! getSubExpr ( ) -> evaluateAsValue ( AUIPCLoc , * Layout ) ) return false ; const MCSymbolRefExpr * AUIPCSRE = AUIPCLoc . getSymA ( ) ; if ( ! AUIPCSRE || findAssociatedFragment ( ) != AUIPCSRE -> findAssociatedFragment ( ) ) return false ; const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; if ( ! AUIPCSymbol ) return false ; const MCFixup * TargetFixup = getPCRelHiFixup ( ) ; if ( ! TargetFixup ) return false ; if ( ( unsigned ) TargetFixup -> getKind ( ) != <STR_LIT> ) return false ; MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ; Res = MCValue :: get ( Target . getSymA ( ) , nullptr , Target . getConstant ( ) + ( Fixup


<s> if ( EnableBranchCoalescing && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>BranchCoalescingPass ( ) ) ; TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( create<ISA_LIT>VSXSwapRemovalPass ( ) ) ; if ( ! DisableMIPeephole ) { addPass ( create<ISA_LIT>MIPeepholePass ( ) ) ; addPass ( &


<s> addend += pc_len ; avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; } while ( addend ++ < <NUM_LIT> ) avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; } else if ( addend > <NUM_LIT> ) { if ( flag_verbose_asm || flag_print_asm_name ) avr_asm_len ( ASM_COMMENT_START <STR_LIT> , op , plen , <NUM_LIT> ) ; while ( addend -- > <NUM_LIT> ) avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; } return <STR_LIT>


<s> uint64_t const F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII ,


<s> initialize<ISA_LIT>PromoteConstantPass ( * PassRegistry :: getPassRegistry ( )


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno += n_regs ) { n_regs = <NUM_LIT> ; if ( saved_regs & ( <NUM_LIT> << regno ) ) { if ( TARGET_H8300S ) { if ( ( ! TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; else if ( ( ! TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue (


<s> <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) MBB


<s> while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { OperandMode Mode = OperandMode_Default ; if ( IsMIMG && isGFX10 ( ) && Operands . size ( ) == <NUM_LIT> ) Mode = OperandMode_NSA ; OperandMatchResultTy Res = parseOperand ( Operands , Name , Mode ) ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; switch ( Res ) { case MatchOperand_Success : break ; case MatchOperand_ParseFail : Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { Parser . Lex ( ) ; } return true ; case MatchOperand_NoMatch : Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { Parser . Lex ( ) ; } return true ; } } return


<s> void printwordmem ( const MCInst * MI , unsigned


<s> gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = vinfo_for_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } } free ( bbs ) ; density_pct = ( vec_cost * <NUM_LIT> ) /


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext &


<s> case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : if ( ! hasV7Ops || ! hasMP ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } unsigned addrmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> ,


<s> if ( ! REG_P ( reg ) || insn == NULL ) return result ; for ( result . insn = insn ; result . insn != NULL ; result . insn = prev_nonnote_insn_bb ( result . insn ) ) { if ( BARRIER_P ( result . insn ) )


<s> SDValue RHSH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHSL , RHSL , Zero ) ; SDValue Carry ( Lo . getNode ( ) , <NUM_LIT> ) ; SDValue Hi = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHSH , RHSH , Carry ) ; SDValue Ignored ( Hi . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo


<s> bool <ISA_LIT>TargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind


<s> unsigned AccessSize ; return getBaseAndOffset ( MI , Value , AccessSize ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { Value = MI -> getOperand ( <NUM_LIT>


<s> static bool canTreatAsByteVector ( EVT VT ) { return VT . isVector ( ) && VT . getVectorElementType ( ) . getSizeInBits (


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Size ) ) ) ; return MCDisassembler ::


<s> if ( ! Subtarget . hasVInstructionsI64 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ; } if ( EltVT . getSizeInBits ( ) > Subtarget . getMaxELENForFixedLengthVectors ( ) ) return false ; unsigned LMul = divideCeil ( VT . getSizeInBits ( ) , MinVLen


<s> bool isSSrcOrLdsB32 ( ) const { return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) || isLiteralImm ( <STR_LIT> ) ||


<s> DebugLoc DL ; determineFrameLayout ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: makePreOp ( LPAC :: ADD ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm (

<NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) ,


<s> if ( auto Value = stripModuloOnShift ( * this , N ,


<s> const <ISA_LIT>Subtarget * getSubtargetImpl


<s> void <ISA_LIT>InstPrinter :: printPostIncOperand8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printPostIncOperand ( MI , OpNo , <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: abs ( PowDiff ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( std :: abs ( PowDiff ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( Src -> isIntOrIntVectorTy ( ) ) return <NUM_LIT> ; return std :: abs ( PowDiff ) ; } } return BaseT :: getCastInstrCost ( Opcode , Dst , Src , CCH , CostKind ,


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT>


<s> static int rs6000_compute_pressure_classes ( enum reg_class * pressure_classes ) { int n ; n = <NUM_LIT> ; pressure_classes [ n ++ ] = GENERAL_REGS ; if ( TARGET_VSX ) pressure_classes [ n ++


<s> void printImpl ( raw_ostream & OS , const MCAsmInfo * MAI )


<s> unsigned getReg ( ) const { assert ( isReg ( ) && <STR_LIT> ) ; return Contents


<s> return TargetIRAnalysis ( [ this ] ( Function


<s> inline vector signed int vec_msums ( vector signed short a1 , vector signed short a2 , vector signed int a3 ) { return ( vector signed int ) __builtin_altivec_vmsumshs ( ( vector signed short ) a1 , ( vector signed short


<s> if ( * name != '*' && * user_label_prefix && * stripped != FASTCALL_PREFIX

) stripped = ACONCAT ( ( user_label_prefix , stripped , NULL ) ) ;


<s> if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits , false ) ) return false ; for ( APInt Elt : EltBits ) RawMask . push_back ( Elt . getZExtValue ( ) ) ; return


<s> printOperand ( MI , Op , O ) ; O << <STR_LIT> ; O << markup ( <STR_LIT>


<s> assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << TRI -> getAsmName ( MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm ( ) ; if ( ShAmt ) { assert ( ShAmt <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> <<


<s> auto * RHSN1 = dyn_cast < ConstantSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! LHSN1 || LHSN1 != RHSN1 || ! RHSN1 -> isNullValue ( ) ) return SDValue ( ) ; SDValue Op1 = LHS -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = RHS -> getOperand ( <NUM_LIT> ) ; EVT OpVT1 = Op1 . getValueType ( ) ; EVT OpVT2 = Op2 . getValueType ( ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || OpVT1 != OpVT2 || Op2 . getOpcode ( ) != <STR_LIT> || OpVT1 . getVectorElementType ( ) != VT ) return SDValue ( ) ; SDValue Val1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Val2 = Op2 . getOperand


<s> if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) &


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { return ; } else if ( IS_VTX ( Desc ) ) { uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t InstWord2 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { InstWord2 |= <NUM_LIT> << <NUM_LIT> ; } Emit ( InstWord01 , OS ) ; Emit ( InstWord2 , OS ) ; Emit ( ( uint32_t ) <NUM_LIT> , OS ) ; } else if ( IS_TEX ( Desc ) ) { int64_t Sampler = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t SrcSelect [ <NUM_LIT> ] = { MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) } ; int64_t Offsets [ <NUM_LIT> ] = { MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> } ; uint64_t Word01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t Word2 = Sampler << <NUM_LIT> | SrcSelect [ ELEMENT_X ] << <NUM_LIT> | SrcSelect [ ELEMENT_Y ] << <NUM_LIT> | SrcSelect [ ELEMENT_Z ] << <NUM_LIT> | SrcSelect [ ELEMENT_W ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> ; Emit ( Word01 , OS ) ; Emit ( Word2 , OS ) ; Emit ( ( uint32_t ) <NUM_LIT> , OS ) ; } else { uint64_t Inst = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) && ( ( Desc . TSFlags & <STR_LIT> ) || Desc . TSFlags & <STR_LIT> ) ) { uint64_t ISAOpCode = Inst & ( <NUM_LIT>


<s> void <ISA_LIT>WholeQuadMode :: propagateBlock ( const MachineBasicBlock & MBB , std :: vector < WorkItem > & Worklist ) { BlockInfo BI = Blocks [ & MBB ] ; if ( ! MBB . empty ( ) ) { const MachineInstr * LastMI = & * MBB . rbegin ( ) ; InstrInfo & LastII = Instructions [ LastMI ] ; if ( ( LastII . OutNeeds | BI . OutNeeds ) != LastII . OutNeeds ) { LastII . OutNeeds |= BI


<s> MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB . getReg ( <NUM_LIT> ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB -> addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool NeedsDwarfCFI = ! IsWin64Prologue && MF . needsFrameMoves ( ) ; bool EmitCFI = ! TFL -> hasFP (


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( hasStackRealignment ( MF ) && MFI . hasVarSizedObjects ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>MCInstrInfo :: setMustExtend ( MCExpr const & Expr , bool Val ) { <ISA_LIT>MCExpr & HExpr = const_cast < <ISA_LIT>MCExpr & > ( cast


<s> const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdst ) ; unsigned NewOffset0 = CI . Offset ; unsigned NewOffset1 = Paired . Offset ; unsigned Opc = CI . UseST64 ? read2ST64Opcode ( CI . EltSize ) : read2Opcode ( CI . EltSize ) ; unsigned SubRegIdx0 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SubRegIdx1 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( NewOffset0 > NewOffset1 ) { std :: swap ( NewOffset0 , NewOffset1 ) ; std :: swap ( SubRegIdx0 , SubRegIdx1 ) ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( CI . EltSize == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; Register BaseReg = AddrReg -> getReg ( ) ; unsigned BaseSubReg = AddrReg -> getSubReg ( ) ; unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { Register ImmReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , Paired . I , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) . addImm ( <NUM_LIT> ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Read2 = BuildMI ( * MBB , Paired . I , DL , Read2Desc , DestReg ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * Paired . I } ) ; ( void ) Read2 ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1


<s> return ( poly64x2_t ) __builtin_neon_vdup_nv2di ( (


<s> static void rs6000_elf_asm_init_sections ( void ) { toc_section = get_unnamed_section ( <NUM_LIT> ,

rs6000_elf_output_toc_section_asm_op , NULL ) ;


<s> short <ISA_LIT>InstrInfo :: getBaseWithRegOffset ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode (


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> half_mode = HImode ; break ; case E_P2QImode : half_mode = QImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { if ( mem_op && rtx_equal_p ( op , mem_op ) ) { lo_half [ num ] = lo_half [ mem_num ] ; hi_half [ num ] = hi_half [ mem_num ] ; } else { mem_op = op ; mem_num = num ; lo_half [ num ] = adjust_address ( op , half_mode , <NUM_LIT> ) ; hi_half [ num ] = adjust_address ( op ,


<s> } else if ( STI . isTargetDarwin ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; } else if ( STI . isTargetWin32 ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetDragonFly ( ) ) { TlsReg = <STR_LIT> ; TlsOffset = <NUM_LIT> ; } else if ( STI . isTargetFreeBSD ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ; } if ( CompareStackPointer ) ScratchReg = <STR_LIT> ; else BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - StackSize ) . addReg ( <NUM_LIT> ) ; if ( STI . isTargetLinux ( ) || STI . isTargetWin32 ( ) || STI . isTargetWin64 ( ) || STI . isTargetDragonFly ( ) ) { BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) ; } else if ( STI . isTargetDarwin ( ) ) { unsigned ScratchReg2 ; bool SaveScratch2 ; if ( CompareStackPointer ) { ScratchReg2 = GetScratchRegister ( Is64Bit , IsLP64 , MF , true ) ; SaveScratch2 = false ; } else { ScratchReg2 = GetScratchRegister ( Is64Bit , IsLP64 , MF , false ) ; SaveScratch2 = MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) ; } assert ( ( ! MF . getRegInfo ( ) . isLiveIn ( ScratchReg2 ) || SaveScratch2 ) && <STR_LIT> ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg2 , RegState :: Kill ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) . addImm ( TlsOffset ) ; BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( ScratchReg2 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( TlsReg ) ; if ( SaveScratch2 ) BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) , ScratchReg2 ) ; } } BuildMI ( checkMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( & PrologueMBB ) ; if ( Is64Bit ) { const unsigned RegAX = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg10 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned Reg11 = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVrr = IsLP64 ? <STR_LIT> : <STR_LIT> ; const unsigned MOVri = IsLP64 ? <STR_LIT> :


<s> void <ISA_LIT>InstPrinter :: printBarrierOption ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Opcode = MI -> getOpcode ( ) ; bool Valid


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { if ( ! TheTriple . isOSBinFormatELF ( ) ) return None ; unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; if ( Type == - <NUM_LIT>


<s> if ( AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT ) { if ( AM . BaseOffs % <NUM_LIT> != <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( Ty -> isSized ( ) && DL . getTypeStoreSize ( Ty ) < <NUM_LIT> ) return isLegalGlobalAddressingMode ( AM ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; } else if ( AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { return isLegalMUBUFAddressingMode ( AM ) ; } else if ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . REGION_ADDRESS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( AM . Scale == <NUM_LIT> ) return


<s> return ( vector unsigned int ) __builtin_altivec_vmrglw ( ( vector signed int ) a1 , ( vector signed


<s> virtual void markPhysRegUsed ( unsigned PhysReg


<s> bool <ISA_LIT>AsmParser :: reportParseError ( StringRef ErrorMsg ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement


<s> vec_const_128bit_type vsx_const ; if ( TARGET_POWER10 && vec_const_128bit_to_bytes ( vec , mode , & vsx_const ) ) { unsigned imm = constant_generates_lxvkq ( & vsx_const ) ; if ( imm ) { operands [ <NUM_LIT> ] = GEN_INT ( imm ) ; return <STR_LIT> ; } imm = constant_generates_xxspltiw ( & vsx_const ) ; if ( imm ) { operands [ <NUM_LIT> ] = GEN_INT ( imm ) ; return <STR_LIT> ; } imm = constant_generates_xxspltidp ( & vsx_const ) ; if ( imm ) { operands [ <NUM_LIT> ] = GEN_INT ( imm ) ; return <STR_LIT> ; } } if ( TARGET_P9_VECTOR && xxspltib_constant_p ( vec , mode , & num_insns , & xxspltib_value ) ) { if ( num_insns == <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( xxspltib_value & <NUM_LIT> ) ; return <STR_LIT> ; } return <STR_LIT> ; } } if ( TARGET_ALTIVEC ) { rtx


<s> replaceb = int_rtx ; } else { offset_rtx = int_rtx ; replacea = NULL_RTX ; replaceb = NULL_RTX ; } reg = gen_rtx_REG ( mode , regno ) ; addr = gen_rtx_PLUS ( Pmode , frame_reg , offset_rtx ) ; mem = gen_rtx_MEM ( mode , addr ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ; insn = emit_move_insn ( mem ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIP ( SDValue Dest , SDValue & SRC1 ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initAsmInfo (


<s> EmitAlignment ( <NUM_LIT> ) ; printSuffixedName ( GV , <STR_LIT> , Prefix ) ; if ( Prefix ) O


<s> if ( startswith ( target_mcu , <STR_LIT> ) ) { snprintf ( mcu_name , sizeof ( mcu_name ) - <NUM_LIT> , <STR_LIT> , target_mcu + <NUM_LIT> ) ; start_upper = <NUM_LIT> ; } else { snprintf ( mcu_name , sizeof ( mcu_name ) - <NUM_LIT> , <STR_LIT> , target_mcu ) ; start_upper = <NUM_LIT> ; } end_upper = strlen ( mcu_name ) - <NUM_LIT> ; for ( i = start_upper ; i < end_upper ; i ++ )

mcu_name [ i ] = TOUPPER ( mcu_name [ i ] ) ;


<s> const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; if ( ! isPositionIndependent ( ) && STI . hasSym32 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF


<s> extern __inline __m512h __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_loadu_ph ( void const * __P ) { return * ( const __m512h_u *


<s> void onLShift ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : State = IES_LSHIFT


<s> unsigned CmpXchgNbWidth = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned OpWidth = MemType -> getPrimitiveSizeInBits ( ) ; if ( OpWidth == CmpXchgNbWidth ) return true ; return


<s> void <ISA_LIT>Shuffler :: restrictPreferSlot3 ( <ISA_LIT>PacketSummary const & Summary ) { const bool HasOnlySlot3 = llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { return ( I . Core . getUnits ( ) == Slot3Mask ) ; } ) ; const bool NeedsPrefSlot3Shuffle = ( Summary . branchInsts . size ( ) <= <NUM_LIT> && ! HasOnlySlot3 && Summary . pSlot3Cnt == <NUM_LIT> && Summary . PrefSlot3Inst ) ; if ( ! NeedsPrefSlot3Shuffle ) return ; <ISA_LIT>Instr * PrefSlot3Inst = * Summary . PrefSlot3Inst ; const unsigned saveUnits = PrefSlot3Inst -> Core . getUnits ( ) ; PrefSlot3Inst -> Core . setUnits ( saveUnits & Slot3Mask ) ; const bool HasShuffledPacket = tryAuction ( Summary ) . hasValue ( ) ; if ( HasShuffledPacket


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultTFE (


<s> case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_MCSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand (


<s> AU . addRequired < LiveIntervals > ( ) ; AU . setPreservesCFG (


<s> if ( Op0 -> isUndef ( ) && ! IsTop ) return Op1 ; if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1

-> getOpcode ( ) , SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue PerformBLENDICombine ( SDNode * N , SelectionDAG & DAG ) { SDValue V0 = N -> getOperand ( <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == V0 . getValueType ( ) && VT == V1 . getValueType ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> ) if ( auto * Mask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( Mask -> getZExtValue ( ) ==

<NUM_LIT> && ! isShuffleFoldableLoad ( V0 ) ) {


<s> if ( PointerType * PT = dyn_cast < PointerType > ( GType ) ) GType = PT -> getElementType ( ) ; if ( isa < ArrayType > ( GType ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StructType * ST = dyn_cast < StructType > ( GType ) ) { if ( ST -> isOpaque ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned Size = GVar -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( GType ) ; if ( Size == <NUM_LIT>


<s> if ( OverrideVectorInsertExtractBaseCost . getNumOccurrences ( ) > <NUM_LIT> ) return OverrideVectorInsertExtractBaseCost ; return


<s> gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; base = ( REGNO ( operands [ <NUM_LIT> ] ) - FIRST_VFP_REGNUM ) / <NUM_LIT> ; for ( i = <NUM_LIT> ; i < XVECLEN ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; i ++ ) { p += sprintf ( & pattern [ p ] , <STR_LIT> , base + i ) ; } strcpy ( & pattern [ p ] , <STR_LIT> ) ; output_asm_insn ( pattern


<s> S = MCDisassembler :: SoftFail ; } if ( mask == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( pred & <NUM_LIT> ) { unsigned LowBit = mask & - mask ; unsigned BitsAboveLowBit = <NUM_LIT> & ( - LowBit << <NUM_LIT> ) ; mask ^= BitsAboveLowBit


<s> protected : const <ISA_LIT>Subtarget * Subtarget ; protected : LEONMachineFunctionPass ( TargetMachine & tm , char


<s> if ( NoAliases || ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot


<s> HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; HasSHSTK = false ; HasIBT = false ; HasSGX = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastGather = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasMacroFusion = false ; HasERMSB = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; SlowTwoMemOps = false ; LEAUsesAG = false ; SlowLEA = false ; Slow3OpsLEA = false ; SlowIncDec = false ; stackAlignment = <NUM_LIT>


<s> <ISA_LIT>ScalarSink ( ) : MachineFunctionPass ( ID ) , MLI ( nullptr ) , TII


<s> SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; bool IsF128 = ( VT == <STR_LIT> ) ; assert ( VT . isFloatingPoint ( ) && VT != <STR_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && <STR_LIT> ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignMask ( EltBits ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl ,


<s> assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Register OldReg = SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MRI -> clearKillFlags ( OldReg ) ; MRI -> replaceRegWith ( OldReg , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg ) ; MIB . setMemRefs ( SetCCI


<s> bool isPostIdxImm8 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val


<s> unsigned Opcode = I -> getOpcode ( ) ; bool canUseShortMicro<ISA_LIT>CTI = false ; if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == Subtarget . getABI ( ) . GetZeroReg ( ) ) canUseShortMicro<ISA_LIT>CTI = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : canUseShortMicro<ISA_LIT>CTI = true ; break ; } } if ( Subtarget . has<ISA_LIT>32r6 ( ) && ( I -> getNumOperands ( ) > <NUM_LIT> ) && ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) ) return <NUM_LIT> ; if ( Subtarget . has<ISA_LIT>32r6 ( ) || canUseShortMicro<ISA_LIT>CTI ) { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT>


<s> unsigned NumArgs = Op . getNode ( ) -> getNumValues ( ) - <NUM_LIT> ; if ( ! NumArgs ) return false ; return cast < ARG_FLAGSSDNode > ( Op . getOperand ( <NUM_LIT> ) )


<s> __rv . __o = __builtin_neon_vld4v8bf ( ( const __builtin_neon_bf * ) __ptr ) ; return __rv .


<s> if ( const <ISA_LIT>MCExpr * S1 = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) { if ( const <ISA_LIT>MCExpr * S2 = dyn_cast < const <ISA_LIT>MCExpr > ( S1 -> getSubExpr ( ) ) ) { if ( S1 -> getKind ( ) == MEK_NEG && S2 ->


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { if ( RVFI -> getUsedSSR ( ) & ( <NUM_LIT> << n

) ) markSuperRegs ( Reserved , <STR_LIT> + n ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst &


<s> unsigned long off ; int i ; for ( i = <NUM_LIT> ; i < ( int ) sizeof ( save_order ) ; ++ i ) { reg = sr -> curr . reg + save_order [ i ] ; if ( reg -> where == UNW_WHERE_GR_SAVE ) { reg -> where = UNW_WHERE_GR ; reg -> val = sr -> gr_save_loc ++ ; } } if ( sr -> imask ) { static unsigned char const limit [ <NUM_LIT> ] = { UNW_REG_F31 , UNW_REG_R7 , UNW_REG_B5 } ; unsigned char kind , mask = <NUM_LIT> , * cp = sr -> imask ; int t ; struct unw_reg_info * ( regs [ <NUM_LIT> ] ) ; regs [ <NUM_LIT> ] = sr -> curr . reg + UNW_REG_F2 ; regs [ <NUM_LIT> ] = sr -> curr . reg + UNW_REG_R4 ; regs [ <NUM_LIT> ] = sr -> curr . reg + UNW_REG_B1 ; for ( t = <NUM_LIT> ; t < sr -> region_len ; ++ t ) { if ( ( t & <NUM_LIT> ) == <NUM_LIT> ) mask = * cp ++ ; kind = ( mask >> <NUM_LIT> * ( <NUM_LIT> - ( t & <NUM_LIT> ) ) ) & <NUM_LIT> ; if ( kind > <NUM_LIT> ) spill_next_when ( & regs [ kind - <NUM_LIT> ] , sr -> curr . reg + limit [ kind - <NUM_LIT> ] , sr -> region_start + t ) ; } } if ( sr -> any_spills ) { off = sr -> spill_offset ; alloc_spill_area ( & off , <NUM_LIT> , sr -> curr . reg + UNW_REG_F2 , sr -> curr . reg + UNW_REG_F31 ) ; alloc_spill_area ( & off , <NUM_LIT> , sr -> curr . reg +

UNW_REG_B1 , sr -> curr . reg + UNW_REG_B5 ) ;


default_function_abi . clobbers_full_reg_p ( regno ) ) ;


<s> EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( STI ) ) { if ( uint8_t REX = DetermineREXPrefix ( MI , TSFlags , MemOperand , Desc ) ) { EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; Ret = true ; } } switch ( TSFlags &


<s> break ; case MachineOperand :: MO_GlobalAddress : AddrSym = getSymbol ( Addr . getGlobal ( ) ) ; break ; } if ( ! isPositionIndependent ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } MCOperand RegPLT = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand cim24 = MCOperand :: createImm ( - <NUM_LIT> ) ; MCOperand loImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_LO32 , AddrSym , OutContext ) ; emitLEAzii ( * OutStreamer , cim24 , loImm , MCRegOP , STI ) ; MCOperand ci32 = MCOperand :: createImm ( <NUM_LIT> ) ; emitANDrm0 ( * OutStreamer , MCRegOP , ci32 , MCRegOP , STI ) ; emitSIC ( * OutStreamer , RegPLT , STI ) ; MCOperand hiImm = createGOTRelExprOp ( <ISA_LIT>MCExpr ::

VK_<ISA_LIT>_PLT_HI32 , AddrSym , OutContext ) ;


<s> OS << static_cast < uint8_t > ( ( Binary >> <NUM_LIT> ) & <NUM_LIT> ) ; OS << static_cast < uint8_t > ( ( Binary >> <NUM_LIT> ) & <NUM_LIT> ) ; OS << static_cast < uint8_t > ( ( Binary >> <NUM_LIT>


<s> unsigned short <ISA_LIT>MCInstrInfo :: getNewValueOp2 ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI


<s> if ( pool_size ) { fprintf ( asm_out_file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label ) ) ; output_asm_insn ( <STR_LIT> , & p -> value ) ; } pool_size =


<s> if ( ImmWithLSL . ShiftAmount >= RegWidth ) return false ; <ISA_LIT>MCExpr :: VariantKind Modifier ; if ( isNonConstantExpr ( ImmWithLSL . Val , Modifier ) ) { if ( ! ImmWithLSL . ImplicitAmount ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumModifiers ; ++ i ) if ( PermittedModifiers [ i ] == Modifier ) return true ; return false ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmWithLSL . Val ) ; return CE && CE -> getValue ( ) >= <NUM_LIT> && CE


<s> case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } DebugLoc DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( Orig -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; } else { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } MachineInstr * NewMI = std :: prev ( I ) ; NewMI -> substituteRegister ( Orig -> getOperand ( <NUM_LIT> ) . getReg (


<s> return ( Kind == k_Register ) && Reg . Kind


<s> size_t numParams ( ) const { return Params . size


<s> case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } SDValue result


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_SETJMP ( const


<s> } } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) && ( CompareVT == VT || VT == <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } if ( isZero ( LHS ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> CCSwapped = <STR_LIT> ( CCOpcode ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } else { <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT>


<s> if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { MVT CastVT = <STR_LIT> ( <STR_LIT> ( InVT . getScalarSizeInBits ( ) ) , InVT . getVectorNumElements ( ) ) ; In = DAG . getNode ( Op . getOpcode ( ) , dl , CastVT , In ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { unsigned CastOpc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT CastVT = VT . changeVectorElementTypeToInteger (


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator (


<s> <ISA_LIT>beTargetMachine :: <ISA_LIT>beTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU ,


<s> TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; DwarfRegNumForCFI = true ; Has<ISA_LIT>Expressions = true ; if ( TheTriple . getArch ( ) == Triple :: mips || TheTriple . getArch ( ) == Triple :: mipsel ) UseIntegratedAssembler = true ; if ( TheTriple . getEnvironment ( ) == Triple

:: GNUABI64 ) UseIntegratedAssembler = true ;


<s> if ( fndecl != NULL_TREE && TREE_CODE ( fndecl ) == FUNCTION_DECL ) call_abi = ix86_function_abi ( fndecl ) ; else call_abi = ix86_function_type_abi ( fndecl ) ; if ( TARGET_64BIT && call_abi == MS_ABI )


<s> if ( LI -> isAtomic ( ) ) return false ; const Value * SV = I -> getOperand ( <NUM_LIT> ) ; if ( TLI . supportSwiftError ( ) ) { if ( const Argument * Arg = dyn_cast < Argument > ( SV ) ) { if ( Arg -> hasSwiftErrorAttr ( ) ) return false ; } if ( const AllocaInst * Alloca = dyn_cast < AllocaInst > ( SV ) ) { if ( Alloca -> isSwiftError ( ) ) return false ; } } MVT VT ; if ( ! isTypeLegal ( LI -> getType ( ) , VT , true ) ) return false ; const Value * Ptr = LI -> getPointerOperand ( ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Ptr , AM ) ) return false ; unsigned ResultReg =


<s> Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = F . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask )


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx


<s> MCRegister <ISA_LIT>RegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC , const MachineFunction & MF ) const { for ( MCRegister Reg : * RC ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ; return MCRegister (


<s> mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_LINK ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } for ( regno = GPR_R0 ; regno <= GPR_LAST ; regno ++ ) { if ( ( reg_mask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , regno ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode ,


<s> MachineInstr * PseudoMI = MF -> CreateMachineInstr ( QII -> get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; bool CanReserve = ResourceTracker -> canReserveResources (


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> storeRegToStackSlotImpl ( MBB , MI , SrcReg , isKill , FrameIndex ,


<s> using namespace <STR_LIT> ; assert ( ( Val & IS_VGPR ) == <NUM_LIT> ) ; return decodeSrcOp ( OPW512 , Val


<s> unsigned CFIIndex = MMI -> addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DRegNum , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get (

TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( op0 == const0_rtx ) { addr = gen_rtx_MEM ( tmode , op1 ) ; } else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op0 , op1 ) ) ; } pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn (


<s> AntiDepBreakMode getAntiDepBreakMode ( ) const override { return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , DataLayout ( <STR_LIT> ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , JITInfo ( * this ) , Subtarget ( TT , FS ) , TLInfo ( * this ) { setRelocationModel ( Reloc ::


<s> } if ( ! riscv_v_ext_vector_mode_p ( mode ) && mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) . to_constant ( ) +


<s> if ( TheTriple . isOSWindows ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI (


<s> for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count = count > sub_count


<s> } RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , & SrcVal

, <NUM_LIT> , false , SDLoc ( Op ) ) . first ;


<s> static void InsertReturnAddressAuth ( MachineFunction & MF , MachineBasicBlock & MBB ) { if ( ! ShouldSignReturnAddress ( MF ) ) return ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB .


<s> for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugValue ( ) ) continue ; MI -> clearKillInfo ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; for ( MCSubRegIterator SR ( R , & TRI , true ) ; SR . isValid ( ) ; ++ SR ) Live . reset ( * SR ) ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; bool IsLive = false ; for ( MCRegAliasIterator AR ( R , & TRI , true ) ; AR . isValid ( ) ; ++ AR ) { if ( ! Live [ * AR ] ) continue ; IsLive =


<s> unsigned Opc ; const TargetRegisterClass * RC ; bool HasRepeatedOperand = false ; MachineFunction * F = BB -> getParent ( ) ; MachineRegisterInfo & RI = F -> getRegInfo ( ) ; const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; HasRepeatedOperand = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; HasRepeatedOperand = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor


<s> bool OptForMinSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ; if ( Subtarget . hasSSE41 ( ) && ( OptForMinSize || ! Subtarget . isPMULLDSlow ( ) ) ) return SDValue ( ) ; ShrinkMode Mode ; if ( ! canReduceVMulWidth ( N , DAG , Mode ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( ( NumElts % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; MVT OpsVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; if ( ExperimentalVectorWideningLegalization || NumElts >= OpsVT . getVectorNumElements ( ) ) { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) { return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; } else { MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast ( ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits


<s> PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopUnrollPass (


<s> return new <ISA_LIT>LowerEmscriptenEHSjLj ( EnableEmEH ,


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return


<s> expandLogicImm ( unsigned Op , Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo8 = Imm & <NUM_LIT> ; unsigned Hi8 = ( Imm >>


<s> break ; case AsmToken :: Identifier : do { if ( parseCnt ( CntVal ) ) return MatchOperand_ParseFail ; } while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) ; break ; } Operands . push_back ( AMDGPUOperand :: CreateImm ( CntVal ) ) ; return MatchOperand_Success


<s> unsigned CopyReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( CopyReg ) . addUse ( SrcReg ) ; unsigned SubRegCopy = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) ) . addDef ( SubRegCopy ) . addUse ( CopyReg , <NUM_LIT> , <STR_LIT> ) ; MachineOperand & RegOp = I .


<s> bool IsIRStructurizerEnabled ( ) const { return


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering


<s> FunctionPass * create<ISA_LIT>InstrCompress ( ) { return new <ISA_LIT>InstrCompress (


<s> unsigned getExpcntBitShift ( unsigned VersionMajor ) { return VersionMajor >= <NUM_LIT> ? <NUM_LIT> :


<s> else if ( M -> getModuleFlag ( <STR_LIT> ) ) { assert ( ! M -> getNamedMetadata ( <STR_LIT> ) ) ; emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } if ( HiddenArgNumBytes >= <NUM_LIT> ) { if ( Func . hasFnAttribute ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> bool <ISA_LIT>FastTileConfig :: isTileStore ( MachineInstr & MI ) { return MI . getOpcode (


<s> RegisterTarget < Triple :: sparc , true > X


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false


<s> void <ISA_LIT>MergeBaseOffsetOpt :: foldOffset ( MachineInstr & HiLUI , MachineInstr & LoADDI , MachineInstr & Tail , int64_t Offset ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; HiLUI . getOperand ( <NUM_LIT> ) . setOffset ( Offset ) ; LoADDI . getOperand ( <NUM_LIT> )


<s> MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> getOperand ( <NUM_LIT> ) . setIsKill


<s> } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) ,


<s> unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) .


<s> if ( ( flags & VEC_ANY_SVE ) && costs -> sve ) return costs -> sve ; return costs ->


<s> void <ISA_LIT>AsmInstCompress :: rmOpcodeFromBundle ( MCInst & MI , unsigned opcode ) const { for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MI ) ) { MCInst & BMI = const_cast < MCInst & > ( * I . getInst


<s> MachineBasicBlock :: iterator MBI = searchBackwards ( p , I , MFI ) ; if ( MBI ) { MachineInstr * NewMI = postRAConvertToLEA ( MFI , MBI ) ; if ( NewMI ) { ++ NumLEAs ; DEBUG ( dbgs ( ) << <STR_LIT> ; MBI -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ; ) ; MFI -> erase ( MBI


<s> return new <ISA_LIT>PassConfig ( this , PM


<s> maskcmp = true ; cmp_mode = nbits > <NUM_LIT> ? int_mode_for_size ( nbits , <NUM_LIT> ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest ; } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode ) { x = force_reg (


<s> LLVM_DEBUG ( if ( Collect ) { dbgs (


<s> if ( ST -> has16BitInsts ( ) && needsPromotionToI32 ( I . getType ( ) ) && DA -> isUniform ( & I ) && promoteUniformOpToI32 ( I ) ) return true ; bool Changed = false ; Instruction :: BinaryOps Opc = I . getOpcode ( ) ; Type * Ty = I . getType ( ) ; Value * NewDiv = nullptr ; if ( ( Opc == Instruction :: URem || Opc == Instruction :: UDiv || Opc == Instruction :: SRem || Opc == Instruction :: SDiv ) && Ty -> getScalarSizeInBits ( ) <= <NUM_LIT> ) { Value * Num = I . getOperand ( <NUM_LIT> ) ; Value * Den = I . getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( & I ) ; Builder . SetCurrentDebugLocation ( I . getDebugLoc (


<s> bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; <ISA_LIT>PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , & TPC ) ; return C . combineMachineInstrs (


<s> return const_cast < <ISA_LIT>AsmParser * > ( this )

-> getContext ( ) . getRegisterInfo ( ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; unsigned CC = StringSwitch < unsigned > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( <STR_LIT> ( CC ) , S ) ) ; return


<s> addPass ( new InstructionSelect ( ) ) ; return


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeImm6 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return encodeImmN ( MI , Op , Fixups , STI


<s> unsigned & CondReg = CondRegs [ Cond ] ; unsigned & InvCondReg = CondRegs [ <STR_LIT> ( Cond ) ] ; if ( ! CondReg && ! InvCondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc ,


<s> if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return get<ISA_LIT>RegClassName ( & <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) return


<s> void <ISA_LIT>ConstantIslands :: fixupBTI ( unsigned JTI , MachineBasicBlock & OldBB , MachineBasicBlock & NewBB ) { assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , NewBB . begin ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; const MachineJumpTableInfo & MJTI = * MF -> getJumpTableInfo ( ) ; const MachineJumpTableEntry & JTE = MJTI . getJumpTables ( ) [ JTI ] ; for ( const MachineBasicBlock * MBB : JTE . MBBs ) { if ( MBB != & OldBB ) continue ; -- BlockJumpTableRefCount [


<s> int <ISA_LIT>AsmParser :: tryParseShiftRegister ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShiftTy = StringSwitch < <STR_LIT> > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShiftTy == <STR_LIT> ) return <NUM_LIT> ; Parser . Lex ( ) ; std :: unique_ptr < <ISA_LIT>Operand > PrevOp ( ( <ISA_LIT>Operand * ) Operands . pop_back_val ( ) ) ; if ( ! PrevOp -> isReg ( ) ) return Error ( PrevOp -> getStartLoc ( ) , <STR_LIT> ) ; int SrcReg = PrevOp -> getReg ( ) ; SMLoc EndLoc ; int64_t Imm = <NUM_LIT> ; int ShiftReg = <NUM_LIT> ; if ( ShiftTy == <STR_LIT> ) { ShiftReg = SrcReg ; } else { if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { Parser . Lex ( ) ; SMLoc ImmLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftExpr = nullptr ; if ( getParser ( ) . parseExpression ( ShiftExpr , EndLoc ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return -


<s> case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_vsx_dform_quad ( mode ) ; break ; case E_V2SImode : case E_V2SFmode


<s> HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG =


<s> rtx addr ; if ( count != <NUM_LIT> ) { offset = - <NUM_LIT> ; addr = plus_constant ( Pmode , frameaddr , offset ) ; addr = memory_address ( Pmode , addr ) ; return gen_rtx_MEM ( Pmode , addr ) ; } return get_hard_reg_initial_val ( Pmode ,


<s> return create<ISA_LIT>ELFStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move ( Emitter ) , false , ( T . getArch ( ) == Triple :: thumb

|| T . getArch ( ) == Triple :: thumbeb ) ) ;


<s> void adjustBBSize ( MachineBasicBlock * MBB , int Size ) { BBInfo [ MBB -> getNumber (


<s> return isAmdCodeObjectV2 ( F ) ? <NUM_LIT>


<s> return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects (


<s> if ( ! skipToken ( AsmToken :: Comma , <STR_LIT> ) ) { return false ; } Loc = getLoc ( ) ; if ( ! parseExpr ( Op ) ) { return false ; } if ( Op < MinVal || Op > MaxVal


<s> bool hasV68Ops ( ) const { return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT>


<s> EVT VT = getPointerTy ( ) ; OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; return SDValue ( OutRetAddr . getNode ( )


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum +


<s> static SDValue combineSetCCAtomicArith ( SDValue Cmp , <STR_LIT> & CC , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! ( Cmp . getOpcode ( ) == <STR_LIT> || ( Cmp . getOpcode ( ) == <STR_LIT> && ! Cmp -> hasAnyUseOfValue ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; if ( ! Cmp . hasOneUse ( ) ) return SDValue ( ) ; SDValue CmpLHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue CmpRHS = Cmp . getOperand ( <NUM_LIT> ) ; if ( ! CmpLHS . hasOneUse ( ) ) return SDValue ( ) ; unsigned Opc = CmpLHS . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue OpRHS = CmpLHS . getOperand ( <NUM_LIT> ) ; auto * OpRHSC = dyn_cast < ConstantSDNode > ( OpRHS ) ; if ( ! OpRHSC ) return SDValue ( ) ; APInt Addend = OpRHSC -> getAPIntValue ( ) ; if ( Opc == <STR_LIT> ) Addend = - Addend ; auto * CmpRHSC = dyn_cast < ConstantSDNode > ( CmpRHS ) ; if ( ! CmpRHSC ) return SDValue ( ) ; APInt Comparison = CmpRHSC -> getAPIntValue ( ) ; if ( Comparison == - Addend ) { auto * AN = cast < AtomicSDNode > ( CmpLHS . getNode ( ) ) ; auto AtomicSub = DAG . getAtomic ( <STR_LIT> , SDLoc ( CmpLHS ) , CmpLHS . getValueType ( ) , CmpLHS . getOperand ( <NUM_LIT> ) , CmpLHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - Addend , SDLoc ( CmpRHS ) , CmpRHS . getValueType ( ) ) , AN -> getMemOperand ( ) ) ; bool NeedCF = false ; switch ( CC


<s> ClauseFile MakeFetchClause ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & I ) const { MachineBasicBlock :: iterator ClauseHead = I ; std :: vector < MachineInstr * > ClauseContent ; unsigned AluInstCount = <NUM_LIT> ; bool IsTex = TII -> usesTextureCache ( ClauseHead ) ; std :: set < unsigned > DstRegs ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ++ I ) { if ( IsTrivialInst ( I ) ) continue ; if ( AluInstCount >= MaxFetchInst ) break ; if ( ( IsTex && ! TII -> usesTextureCache ( I ) ) || ( ! IsTex && ! TII -> usesVertexCache ( I ) ) ) break ; if ( ! isCompatibleWithClause ( I , DstRegs ) ) break ; AluInstCount ++


<s> std :: vector < std :: string > & getSwitchNames ( ) { return


<s> MachineBasicBlock * MBB = OldMI -> getParent ( ) ; MachineInstr * NewMBB = MBB -> getParent ( ) -> CreateMachineInstr ( TII


<s> return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT>


<s> uint32_t getAddrMode2OpValue ( const MachineInstr & MI , unsigned OpIdx ) const { return <NUM_LIT>


<s> Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands , Name ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) .


<s> return false ; } if ( SU -> getInstr ( ) -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned imm = SU -> getInstr ( ) -> getOperand ( <NUM_LIT> ) .


<s> auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul , Flags ) ; auto Fma4 = B . buildFMA ( S32 , NegDivScale0 , Fma3 , NumeratorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( false , B , ST , Mode ) ; auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma1 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( NumeratorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; B . buildIntrinsic ( <STR_LIT> , Res , false ) . addUse ( Fmas . getReg ( <NUM_LIT> ) ) . addUse ( RHS ) . addUse ( LHS ) . setMIFlags ( Flags ) ; MI . eraseFromParent ( )


<s> rtx base = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; while ( GET_CODE ( base ) != REG ) base = XEXP ( base , <NUM_LIT> ) ; if ( REGNO ( base ) == REGNO ( operands [ <NUM_LIT> ] ) ) reversed = true ; if ( refers_to_regno_p ( REGNO ( operands [ <NUM_LIT> ] ) , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> , base , <NUM_LIT> ) ) dead = true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) reversed = true ; fixup [ <NUM_LIT> ] = ia64_split_tmode ( in , operands [ <NUM_LIT> ] , reversed , dead ) ; fixup [ <NUM_LIT> ] = ia64_split_tmode ( out , operands


<s> switch ( Op . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> getAPIntValue ( ) == <NUM_LIT> ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : { bool NonFlagUse = false ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( ) . getOperandNo ( ) ; User = * User -> use_begin ( ) ; } if ( User -> getOpcode ( ) != <STR_LIT> && User -> getOpcode ( ) != <STR_LIT> && ( User -> getOpcode ( ) != <STR_LIT> || UOpNo != <NUM_LIT> ) ) { NonFlagUse =


<s> int imm = Val & <NUM_LIT> ; if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( imm * <NUM_LIT> ) ) ; } return MCDisassembler ::


<s> fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } else { regs_off = <NUM_LIT> + <NUM_LIT> ; fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } this_cfa = ( int ) context -> cfa ; new_cfa = * ( int * ) ( ( context -> cfa ) + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ) ) ; fpu_save = * ( int * ) ( ( this_cfa ) + ( fpu_save_off ) ) ; fs -> cfa_how = CFA_REG_OFFSET ; fs -> cfa_reg = <NUM_LIT> ; fs -> cfa_offset = new_cfa - ( int ) context -> cfa ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) continue ; fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = this_cfa + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( i * <NUM_LIT> ) ) - new_cfa ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { fs -> regs . reg [ i + <NUM_LIT> ] .


<s> return ( __m512 ) __builtin_ia32_broadcastss512 ( __extension__ ( __v4sf ) { __A , } , (

__v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> void GCNHazardRecognizer :: Reset ( ) { EmittedInstrs . clear (


<s> const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) -> getParent ( ) ; unsigned char OpFlag = Subtarget . classifyGlobalReference ( nullptr , * Mod ) ; unsigned WrapperKind = <STR_LIT> ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( isPositionIndependent ( ) && ! Subtarget . is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc (


<s> void <ISA_LIT>Shuffler :: applySlotRestrictions ( )


<s> static inline bool isConv ( const MachineInstr * MI ) { return MI -> getDesc ( )


<s> return VectorType :: get ( B . getInt32Ty ( ) , cast < VectorType > ( T )


<s> int half_elts = GET_MODE_NUNITS ( GET_MODE ( XEXP ( sel , <NUM_LIT> ) ) ) >> <NUM_LIT> ; int lane = INTVAL ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) ; lane = lane >= half_elts ? lane - half_elts : lane + half_elts ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( lane ) ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID


<s> BBI . Size += TII -> getInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( )


<s> SDValue ExtLoad = DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , N0 . getValueType ( ) , LN0 -> getMemOperand ( ) ) ; DCI . CombineTo ( N , ExtLoad ) ; DCI . CombineTo ( N0 . getNode ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , ExtLoad , DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( N0 ) ) ) , ExtLoad .