<s> void <ISA_LIT>TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( ! Subtarget -> is64Bit ( ) ) return ; <ISA_LIT>MachineFunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setIsSplitCSR (


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Addr = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock ( true ) ; EmitMask ( Out , Addr , Mask ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine (


<s> LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; assert ( Load -> getAlignment ( ) >= MemVT . getStoreSize ( ) ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue Offset = Load -> getOffset ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> ,


<s> else { assert ( MI -> isSubregToReg ( ) && <STR_LIT> ) ; CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg ) ) { if ( ! isScalarVecReg ( CopySrcReg ) ) SwapVector [ VecIdx ] . MentionsPhysVR = <NUM_LIT> ; return CopySrcReg ; } return lookThruCopyLike ( CopySrcReg , VecIdx


<s> rtx expand ( function_expander & e ) const override { machine_mode mode = GET_MODE ( e . target ) ; rtx vlenb = gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ; emit_move_insn ( e . target , vlenb


<s> if ( ! IsSP ( MI -> getOperand ( <NUM_LIT>


<s> else if ( Reg == <STR_LIT> ) Comment << <STR_LIT> ; else Comment << printReg ( Reg , & TRI ) ; SmallString < <NUM_LIT> > Expr ; unsigned DwarfReg = TRI . getDwarfRegNum ( Reg , true ) ; Expr . push_back ( ( uint8_t ) ( dwarf :: DW_OP_breg0 + DwarfReg ) ) ; Expr . push_back ( <NUM_LIT> ) ; appendVGScaledOffsetExpr ( Expr , NumBytes , NumVGScaledBytes , TRI . getDwarfRegNum ( <STR_LIT> , true )


<s> fprintf ( file , <STR_LIT> , public ? ( int ) C_EXT : ( int )


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const


<s> getBDVAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction


<s> if ( mi_match ( Reg , MRI , m_GZExt ( m_Reg ( ZExtSrc ) ) ) ) return MRI . getType ( ZExtSrc ) == LLT :: scalar ( <NUM_LIT> ) ? ZExtSrc : Register ( ) ; const MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; if ( Def -> getOpcode ( ) != <STR_LIT> ) return false ; int64_t MergeRHS ; if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( MergeRHS ) ) && MergeRHS == <NUM_LIT> ) { return Def -> getOperand ( <NUM_LIT>


<s> Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) )


<s> BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI -> eraseFromParent ( ) ; return


<s> static inline unsigned getMsb ( uint32_t insn


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI -> getOperand


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * Blocks [ <NUM_LIT> ] ) ) ; for ( unsigned i = <NUM_LIT> , e = Blocks . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = Blocks [ i ] ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) , E = MBB -> end ( ) ; MII != E ; ++ MII ) { const MachineInstr * MI = & * MII ; if ( isInvalidLoopOperation ( MI


<s> bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR16 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success


<s> assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ; AddDefaultPred (


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) != REG ) operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , HImode , <NUM_LIT> ) ; if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( logval = exact_log2 ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) ) >= <NUM_LIT> && ( DATA_REG_P ( operands [ <NUM_LIT> ] ) || offsettable_memref_p ( operands [ <NUM_LIT> ] ) ) ) { if ( DATA_REG_P ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( logval ) ; else { operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> - ( logval / <NUM_LIT> ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( logval % <NUM_LIT> ) ; } return <STR_LIT> ; } if ( ! side_effects_p ( operands [ <NUM_LIT> ] ) ) flags_operand1 = operands [ <NUM_LIT> ] ; flags_valid = FLAGS_VALID_YES


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return - SEHFrameOffset ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI . getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { assert ( <NUM_LIT> && <STR_LIT> ) ; return false


<s> addPass ( new Legalizer ( ) ) ; return


<s> Register VReg1 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 ,


<s> machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; rtx perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) perm [ i ] = GEN_INT ( i * <NUM_LIT> ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode ,


<s> static enum arm_cond_code get_arm_condition_code ( rtx comparison ) { enum arm_cond_code code = maybe_get_arm_condition_code ( comparison )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Info . SwiftErrorVReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! mayTailCallThisCC ( CalleeCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Info . IsVarArg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( any_of ( CallerF . args ( ) , [ ] ( const Argument & A ) { return A . hasByValAttr ( ) || A .


<s> else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; Result . getNode ( ) -> setTrapInfo ( Op -> getTrapInfo ( ) ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } return Result


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI -> getOperand (


<s> Error ( L , <STR_LIT> ) ; return false ; } SMLoc FPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int FPReg = tryParseRegister ( ) ; if ( FPReg == - <NUM_LIT> ) { Error ( FPRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; SMLoc SPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int SPReg = tryParseRegister ( ) ; if ( SPReg == - <NUM_LIT> ) { Error ( SPRegLoc


<s> assert ( QII -> isPostIncrement ( MI ) && <STR_LIT> ) ; DenseMap < unsigned , unsigned > DefRegsSet ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isDef ( ) ) { DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] = <NUM_LIT> ; } for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isUse ( ) ) { if ( DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] ) { return MI -> getOperand ( opNum ) ; } } if ( MI -> getDesc ( ) .


<s> Triple TheTriple ( TT ) ; const uint8_t ABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT )


<s> if ( node_class ( N , EqRel ) ) continue ; NodeSet C ; for ( NodeSet :: iterator NJ = std :: next ( NI ) ; NJ != NE ; ++ NJ ) if ( node_eq ( N , * NJ , Eq , Ne ) ) C . insert ( * NJ ) ; if ( ! C . empty ( ) ) { C . insert ( N ) ; std :: pair < NodeSymRel :: iterator , bool > Ins = EqRel . insert ( C ) ; ( void ) Ins ; assert ( Ins . second && <STR_LIT> ) ; } } } DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( NodePairSet :: iterator I = Eq . begin ( ) , E = Eq . end ( ) ; I != E ; ++ I )

dbgs ( ) << <STR_LIT> << I -> first << <STR_LIT> << I -> second << <STR_LIT> ;


<s> return __builtin_aarch64_sminpv2sf ( a , b


<s> DINodeArray Elements = CTy -> getElements ( ) ; uint32_t VLen = Elements . size ( ) ; if ( VLen > <STR_LIT> ) return ; auto TypeEntry = llvm :: make_unique < BTFTypeEnum > ( CTy ,


<s> case MachO :: <ISA_LIT>_RELOC_BR24 : if ( ! S . isTemporary ( ) ) return true ; Value -= <NUM_LIT> ; Range = <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_THUMB_RELOC_BR22 : Value -= <NUM_LIT> ; Range = <NUM_LIT> ; } Value += Writer -> getSectionAddress ( & S . getSection ( ) ) ; Value -= Writer -> getSectionAddress ( Fragment . getParent ( ) ) ; if ( Value > Range || Value < - ( Range + <NUM_LIT> )


<s> uint8_t getInstSize ( uint64_t Inst ) const { return ( Inst >> <NUM_LIT> )


<s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg - <STR_LIT> + <STR_LIT>


<s> SMLoc <ISA_LIT>AsmParser :: getConstLoc ( const OperandVector & Operands ) const { auto Test = [ ] ( const <ISA_LIT>Operand & Op ) { return Op . isImmKindConst


<s> for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / <NUM_LIT> ) , PtrVT ) ) ; Loads . push_back ( DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , MachinePointerInfo ( Load -> getMemOperand ( ) -> getValue (

) ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ) ;


<s> bool <ISA_LIT>AsmParser :: emit ( MCInst & Inst , SMLoc const & Loc , MCStreamer & Out ) const { Inst . setLoc ( Loc ) ; Out . emitInstruction ( Inst ,


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID


<s> if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI ->


<s> rtx set = XVECEXP ( real , <NUM_LIT> , i ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return insn ; } if ( reg == reg2 ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; if ( reg == rreg ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; real = copy_rtx ( PATTERN ( insn ) ) ; if ( reg2 != NULL_RTX ) real = replace_rtx ( real , reg2 , rreg ) ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) gcc_checking_assert ( val == <NUM_LIT> ) ; else real = replace_rtx ( real , reg , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ) ; if ( GET_CODE ( real ) == SET ) { rtx set = real ; temp = simplify_rtx ( SET_SRC ( set


<s> bool llvm :: getReqNTIDy ( const Function & F , unsigned & y ) { return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [


<s> if ( ! Sym -> getType ( ) ) { const <ISA_LIT>TargetLowering & TLI = * Subtarget -> getTargetLowering ( ) ; SmallVector < MVT , <NUM_LIT> > VTs ; Type * GlobalVT = GV -> getValueType ( ) ; computeLegalValueVTs ( TLI , GV -> getParent ( ) -> getContext ( ) , GV -> getParent ( ) -> getDataLayout ( ) , GlobalVT , VTs ) ; <STR_LIT> ( Sym , GlobalVT , VTs ) ; } if ( Sym -> isTable


<s> TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableVectorCombine ) addPass

( create<ISA_LIT>VectorCombineLegacyPass ( ) ) ;


<s> _smpylh ( int src1 , int src2 ) { return __builtin_c6x_smpylh ( src1 ,


<s> TSTInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm ( ( int64_t ) <STR_LIT> ) ) ; TSTInst . addOperand ( MCOperand :: CreateImm


<s> static DecodeStatus DecodeThumbCmpBROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( Val << <NUM_LIT> ) ) ; return MCDisassembler ::


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> void <ISA_LIT>InstPrinter :: printUpdateExecMask ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return


<s> const SmallVector < int , <NUM_LIT> > & getLiveIn ( ) const { return


<s> __rv . __o = __builtin_neon_vld4v16qi ( ( const __builtin_neon_qi * ) __a ) ; return __rv .


<s> static void extractParts ( Register Reg , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , LLT Ty , int NumParts , SmallVectorImpl < Register > & VRegs ) { for ( int I = <NUM_LIT> ; I < NumParts ; ++ I ) VRegs . push_back ( MRI . createGenericVirtualRegister ( Ty ) ) ; MIRBuilder . buildUnmerge ( VRegs ,


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass


<s> std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; auto * Fn = MBB . getParent ( ) ; for ( MachineBasicBlock * Pred : SuccBB -> predecessors ( ) ) if ( ! examinePred ( * Pred , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * Fn ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo & MFI = Fn -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( & MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end ( ) , RegDU , *


<s> expandAlloca ( MI , HII , SP , MaxCF ) ; MI -> eraseFromParent ( ) ; } if ( ! hasFP ( MF ) ) return ; const unsigned int ALLOCFRAME_MAX = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; unsigned CallerSavedReg = HRI . getFirstCallerSavedNonParamReg ( ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , CallerSavedReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg (


<s> if ( Kind . isData ( ) && isGlobalInSmallSection ( GO , TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3Mods0Clamp ( SDValue In , SDValue & Src ,

SDValue & SrcMods , SDValue & Omod ) const {


<s> void setGPRSizeFromPredicates ( const PredicateLibrary


<s> vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; int cnt ; vec_uchar16 mask ; x . v = ( vec_uchar16 ) ( count ) ; x . i [ <NUM_LIT> ] = cnt = ( <NUM_LIT> - x . i [ <NUM_LIT> ] ) << <NUM_LIT> ; x . v = vec_splat ( x . v , <NUM_LIT> ) ; mask = ( cnt & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ; return ( ( qword ) ( vec_and ( vec_sro ( ( vec_uchar16 )


<s> SmallSet < unsigned , <NUM_LIT> > Defs ; for ( const MachineOperand & MO : CPSRDef -> operands ( ) ) { if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isUse ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> || Reg == <STR_LIT> ) continue ; Defs . insert ( Reg ) ; } for ( const MachineOperand & MO : Use -> operands (


<s> void ScheduleDAGPostRA :: observe ( MachineInstr * MI , unsigned


<s> unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( SrcReg == <STR_LIT> ||


<s> bool <ISA_LIT>SETargetLowering :: isEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>MachineFunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls )


<s> if ( visium_flags_exposed && gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) && ( gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) || ( mode ==

QImode && operands [ <NUM_LIT> ] == const0_rtx ) ) ) return false ;


<s> if ( LEGITIMATE_SMALL_DATA_ADDRESS_P ( x ) ) return true ; if ( GET_CODE ( x ) == CONST_INT && LARGE_INT ( INTVAL ( x ) ) ) return true ; if ( ! flag_pic && optimize_size && ! reload_completed && ( GET_CODE ( x ) == CONST ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && ! SYMBOL_REF_FUNCTION_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( CONST_INT_P ( addend ) ) ; HOST_WIDE_INT offset = INTVAL ( addend ) ; return ! ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; } if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) { if ( flag_pic ? arc_legitimate_pic_addr_p ( x ) : arc_legitimate_constant_p ( Pmode , x )


<s> void <ISA_LIT>InstPrinter :: printMovDGAll ( const MCInst * , unsigned , raw_ostream & O ) { O <<


<s> } if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } if ( DestReg == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } } if ( DestReg == <STR_LIT> && SrcReg == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestReg == <STR_LIT> && SrcReg == <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : { unsigned Rt = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = get<ISA_LIT>RegisterNumbering ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { unsigned lsb = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned widthm1 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( widthm1 >= <NUM_LIT> - lsb ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : { unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool hasWritebackToken = ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isToken ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) ; bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , Rn , <NUM_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> + hasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( ! listContainsBase && ! hasWritebackToken && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( listContainsBase && hasWritebackToken ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : { if ( listContainsReg ( Inst , <NUM_LIT> , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT>


<s> SDValue callFunction ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , const char * fnName , SDValue Dst , SDValue Src , SDValue Size ) { auto & Ctx = * DAG . getContext ( ) ; auto & STI = get<ISA_LIT>Subtarget ( DAG ) ; TargetLowering :: ArgListTy Args ; auto pushArg = [ & ] ( SDValue & Op ) { TargetLowering :: ArgListEntry Entry ; Entry . Node


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU , bool isLittle ) { switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = getMachOSubTypeFromArch ( TheTriple . getArchName ( ) ) ; return new <ISA_LIT>AsmBackendDarwin ( T , TheTriple , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( )


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> const BranchInst * BI = cast < BranchInst > ( I ) ; MachineBasicBlock * TrueMBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FalseMBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; <STR_LIT> CC ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( CI -> hasOneUse ( ) && CI -> getParent ( ) == I -> getParent ( ) ) { EVT VT = TLI . getValueType ( DL , CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; CmpInst :: Predicate Predicate = optimizeCmpPredicate ( CI ) ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_FALSE : fastEmitBranch ( FalseMBB , DbgLoc ) ; return true ; case CmpInst :: FCMP_TRUE : fastEmitBranch ( TrueMBB , DbgLoc ) ; return true ; } const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( Predicate == CmpInst :: FCMP_ORD || Predicate == CmpInst :: FCMP_UNO ) { const auto * CmpRHSC = dyn_cast < ConstantFP > ( CmpRHS ) ; if ( CmpRHSC && CmpRHSC -> isNullValue ( ) ) CmpRHS = CmpLHS ; } if ( FuncInfo . MBB -> isLayoutSuccessor ( TrueMBB ) ) { std :: swap ( TrueMBB , FalseMBB ) ; Predicate = CmpInst :: getInversePredicate ( Predicate ) ; } bool NeedExtraBranch = false ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : std :: swap ( TrueMBB , FalseMBB ) ; LLVM_FALLTHROUGH ; case CmpInst :: FCMP_UNE : NeedExtraBranch = true ; Predicate = CmpInst


<s> return __builtin_mve_vcaddq_rot90_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a ,


<s> void <ISA_LIT>AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand SourceReg = Inst . getOperand ( <NUM_LIT> ) ; unsigned SecondOpcode = SignExtend ? <STR_LIT> : <STR_LIT> ; int64_t ShAmt = ( isRV64 ( ) ? <NUM_LIT> : <NUM_LIT> ) - Width ; assert ( ShAmt > <NUM_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( DestReg ) .

addOperand ( SourceReg ) . addImm ( ShAmt ) ) ;


<s> SkippedVcc = false ; } if ( Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { switch ( BasicInstType ) { case <STR_LIT> : addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; if ( <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: omod ) != - <NUM_LIT> ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> , <NUM_LIT> ) ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstSel , SdwaSel :: DWORD ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstUnused , DstUnused :: UNUSED_PRESERVE ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , SdwaSel :: DWORD ) ; break ; case <STR_LIT> : addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; if ( <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: omod ) != - <NUM_LIT> ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> , <NUM_LIT> ) ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstSel , SdwaSel :: DWORD ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstUnused , DstUnused :: UNUSED_PRESERVE ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , SdwaSel :: DWORD ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc1Sel , SdwaSel :: DWORD ) ; break ; case <STR_LIT> : if ( <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: clamp ) != - <NUM_LIT> ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , SdwaSel :: DWORD ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc1Sel , SdwaSel :: DWORD ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> bool isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { return false


<s> bool constant_address_p ( rtx x ) { return CONSTANT_P ( x ) && ix86_legitimate_address_p ( Pmode


<s> Node -> setNodeId ( - <NUM_LIT> ) ; return nullptr ; } unsigned Opcode = Node -> getOpcode ( ) ; SDNode * ResNode = nullptr ; switch ( Opcode ) { case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ResNode = tryRxSBG ( Node , <STR_LIT> ) ; goto or_xor ; case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ResNode = tryRxSBG ( Node , <STR_LIT> ) ; or_xor : if ( ! ResNode && Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) if ( auto * Op1 = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Val = Op1 -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) ) Node = splitLargeImmediate ( Opcode , Node , Node -> getOperand ( <NUM_LIT> ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : if ( Node -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ResNode = tryRxSBG ( Node , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! ResNode ) ResNode = tryRISBGZero ( Node ) ; break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) Node = splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode (


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Align ( Size ) ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ; for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ; const Align RestAlign = std :: min ( Alignment , Align ( Size ) ) ; for ( auto & It : PendingMembers ) { It . convertToMem ( State . AllocateStack ( Size , Alignment ) ) ; State . addLoc


<s> AEABILibcall = AEABI_MEMMOVE ; break ; case RTLIB :: MEMSET : AEABILibcall = AEABI_MEMSET ; if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry )


<s> Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; return


<s> static bool iq2000_pass_by_reference ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int size ; if ( cum && targetm . calls . must_pass_in_stack ( mode , type ) ) { CUMULATIVE_ARGS temp ; temp = * cum


<s> inline bool mips_lo_sum_offset_hasher :: equal ( const value_type * entry ,


<s> mode = TYPE_MODE ( type ) ; if ( TARGET_AAPCS_BASED ) return aapcs_allocate_return_reg ( mode , type , func ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = arm_promote_function_mode ( type , mode , & unsignedp , func , <NUM_LIT> ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != <NUM_LIT>


_mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> dec = & MAP5_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case MAP6 : dec = & MAP6_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ; case MODRM_ONEENTRY : return modRMTable [ dec -> instructionIDs ] ; case MODRM_SPLITRM : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return modRMTable [ dec -> instructionIDs + <NUM_LIT> ] ; return modRMTable [ dec -> instructionIDs ] ; case MODRM_SPLITREG : if ( modFromModRM ( modRM ) == <NUM_LIT> ) return modRMTable [ dec -> instructionIDs + ( ( modRM & <NUM_LIT> ) >> <NUM_LIT> ) + <NUM_LIT> ] ; return modRMTable [ dec -> instructionIDs + ( ( modRM & <NUM_LIT> ) >>


<s> Offset += getOffsetOfLocalArea ( ) ; } if ( IsWin64Prologue ) { assert ( ! MFI . hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return StackOffset :: getFixed ( - SEHFrameOffset ) ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ; } else { assert ( isAligned ( MFI . getObjectAlign ( FI ) , - ( Offset + StackSize ) ) ) ; return StackOffset :: getFixed ( Offset + StackSize ) ; } } else if ( TRI -> hasStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ; } else


<s> gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( SUBREG_P ( mem ) ) mem = SUBREG_REG ( mem ) ; gcc_assert ( MEM_P ( mem ) ) ; return volatile_ok || ! MEM_VOLATILE_P


<s> MI . eraseFromParent ( ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: FLAT_ADDRESS ) { assert ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; auto SegmentNull = B . buildConstant ( DstTy , NullVal ) ; auto FlatNull = B . buildConstant ( SrcTy , <NUM_LIT> ) ; auto PtrLo32 = B . buildExtract ( DstTy , Src , <NUM_LIT> ) ; auto CmpRes = B . buildICmp ( CmpInst :: ICMP_NE , LLT :: scalar ( <NUM_LIT> ) , Src , FlatNull . getReg ( <NUM_LIT> ) ) ; B . buildSelect ( Dst , CmpRes , PtrLo32 , SegmentNull . getReg ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS != <ISA_LIT>AS :: LOCAL_ADDRESS && SrcAS != <ISA_LIT>AS :: PRIVATE_ADDRESS ) return false ; if ( ! ST . hasFlatAddressSpace ( ) ) return false ; auto SegmentNull = B . buildConstant ( SrcTy , TM .


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo


<s> int MaxValue = <ISA_LIT>MCInstrInfo :: getMaxValue ( MCII , MCI ) ; MCOperand const & MO = MCI . getOperand ( ExtOpNum ) ; if ( MO . isExpr ( ) ) return true ; assert ( MO . isImm (


<s> MI -> eraseFromParent ( ) ; } if ( ! hasFP ( MF ) ) return ; const unsigned int ALLOCFRAME_MAX = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; unsigned CallerSavedReg = HRI . getFirstCallerSavedNonParamReg ( ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , CallerSavedReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( CallerSavedReg ) ; } else { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( NumBytes ) . addMemOperand ( MMO ) ; } if ( AlignStack ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP


<s> if ( <STR_LIT> . contains ( SrcReg ) ) { assert ( Subtarget . hasBWI ( ) ) ; return <STR_LIT> ; } if ( <STR_LIT> . contains ( SrcReg ) ) return Subtarget . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> .


<s> bool SrcIsHigh = isHighReg ( SrcReg ) ; if ( ! DestIsHigh && ! SrcIsHigh ) MI -> setDesc ( get ( LowOpcodeK ) ) ; else { emitGRX32Move ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; MI -> setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { StackOffset Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI


<s> if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode )


<s> static void encode_pattern ( rtx x ) { patternp = pattern ; encode_pattern_1 ( x ) ; * patternp


<s> LowerGlobalTLSAddress ( SDValue Op ,


<s> return __builtin_mve_vcaddq_rot270_m_uv8hi ( __arm_vuninitializedq_u16 ( ) ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > (


<s> int reg = I -> getOperand ( opcount ) . getReg ( ) ; if ( isGPR ( reg ) && ! ( I -> mayLoad ( ) && ! opcount ) ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg ( reg ) ) ; MBB -> insert ( I , cmpInst ) ; MachineInstr * MItest = BuildMI ( MF , DL3 , TII -> get


<s> return ( int ) __builtin_c6x_sadd2 ( ( __v2hi ) src1 , ( __v2hi


<s> bool <ISA_LIT>TargetLowering :: shouldExpandBuildVectorWithShuffles ( EVT VT , unsigned DefinedValues ) const { if ( VT == <STR_LIT> ) return Subtarget . hasDirectMove


<s> static bool bfin_can_use_doloop_p ( const widest_int & , const widest_int & iterations_max , unsigned int , bool ) { if ( ! flag_unsafe_loop_optimizations && wi :: geu_p ( iterations_max , <NUM_LIT> ) ) return false ; return true


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegsV2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const uint16_t CalleeSavedRegsV3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( Subtarget . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V1


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo (


<s> nextMBB -> splice ( nextMBB -> begin ( ) , thisMBB , llvm :: next ( MachineBasicBlock :: iterator ( bInstr ) ) , thisMBB -> end ( ) ) ; nextMBB -> transferSuccessorsAndUpdatePHIs ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; assert ( bInstr -> getNumOperands ( ) < <STR_LIT> + <NUM_LIT> && <STR_LIT> ) ; DebugLoc dl = bInstr -> getDebugLoc ( ) ; MachineOperand & destOper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> + <STR_LIT> ] ; int numArgs = bInstr -> getNumOperands ( ) - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < numArgs ; ++ i ) argOpers [ i ] = & bInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <STR_LIT> - <NUM_LIT> ; int valArgIndx = lastAddrIndx + <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( newMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned tt = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( invSrc


<s> return ; } SDValue RC = DAG . getTargetConstant ( RegClass , <STR_LIT> ) ; SDNode * Node = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc

( ) , Operand . getValueType ( ) , Operand , RC ) ;


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( l + ( ( Imm >>


<s> <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo ,


<s> return ( vector signed int ) __builtin_altivec_vsum2sws ( ( vector signed int ) a1 , ( vector


<s> if ( StepSel ) { if ( ! MO . isImm ( ) ) return false ; return MO . getImm ( ) == Step . ImmVal ; } else { if ( ! MO . isReg ( ) ) return false ; return MO . getReg (


<s> return PairDRegs ( VT , N -> getOperand ( <NUM_LIT> ) , N ->


<s> } else if ( Op . isImm ( ) ) { O << formatImm ( ( int64_t ) Op . getImm ( ) ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr (


<s> static DecodeStatus DecodeVecShiftR32ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm


<s> return ( __m128i ) __builtin_ia32_pmovzxbd128_mask ( ( __v16qi ) __A , ( __v4si ) _mm_setzero_si128 ( ) , (


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIdx ) >= RC -> getSize ( ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >=

Alignment ) || RI . canRealignStack ( MF ) ;


<s> unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB


<s> } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasAES = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) ) ) { IsUAMemFast = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelAtom ; UseLeaForSP = true ; ToggleFeature ( <STR_LIT> ) ; } unsigned MaxExtLevel ; <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & MaxExtLevel , & EBX , & ECX , & EDX ) ; if ( MaxExtLevel >= <NUM_LIT>


<s> ConstantSDNode * CN = nullptr ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } } return false


<s> for ( MachineInstr :: const_mop_iterator Mop = Instr -> operands_begin ( ) ; Mop != Instr -> operands_end ( ) ; ++ Mop ) { if ( isSameOperand ( * Mop , *


<s> StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; Args . push_back ( getContext ( ) . getOrCreateSymbol ( Name ) ) ; if ( Idx + <NUM_LIT> == NbArgs ) break ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> + Twine ( IDVal ) + <STR_LIT> ) ) return true ; } if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> + Twine


<s> for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } unsigned NewSize ; MachineInstr & OldBranch = * I ; DebugLoc dl = OldBranch . getDebugLoc ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { NewSize = <NUM_LIT> ; } else { SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; TII -> ReverseBranchCondition ( Cond ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) ; NewSize = <NUM_LIT> ; } I = BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Dest ) ; OldBranch . eraseFromParent ( ) ; BlockSizes [ MBB . getNumber ( ) ] += NewSize - <NUM_LIT> ; MBBStartOffset += NewSize ; ++ NumExpanded ; MadeChange = true ; } } EverMadeChange |= MadeChange ; } BlockSizes . clear (


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; setAndEmitFunctionVirtualRegisters ( * MF ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; emitDemotedVars ( MF -> getFunction ( ) ,


<s> CombinerHelper Helper ( Observer , B , KB , MDT , LI ) ; return Generated . tryCombineAll ( Observer , MI , B


<s> if ( isToken ( AsmToken :: Identifier ) ) { Val = getTokenStr ( ) ; lex ( ) ; return true ; } else { if ( ! ErrMsg . empty ( ) )


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; return


<s> MVT ExtVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; if ( supportedVectorShiftWithBaseAmnt ( ExtVT , Subtarget , Opcode ) ) { unsigned LogicalOp = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned Logical<ISA_LIT>Op = getTargetVShiftUniformOpcode ( LogicalOp , false ) ; BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; SDValue BitMask = DAG . getConstant ( - <NUM_LIT> , dl , ExtVT ) ; BitMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , BaseShAmt , Subtarget , DAG ) ; if ( Opcode != <STR_LIT> ) BitMask = getTargetVShiftByConstNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , <NUM_LIT> , DAG ) ; BitMask = DAG . getBitcast ( VT , BitMask ) ; BitMask = DAG . getVectorShuffle ( VT , dl , BitMask , BitMask , SmallVector < int , <NUM_LIT> > ( NumElts , <NUM_LIT> ) ) ; SDValue Res = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , DAG . getBitcast ( ExtVT , R ) , BaseShAmt , Subtarget , DAG ) ; Res = DAG . getBitcast ( VT , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , BitMask ) ; if ( Opcode == <STR_LIT> ) { SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , ExtVT ) ; SignMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , SignMask , BaseShAmt , Subtarget , DAG ) ; SignMask = DAG . getBitcast ( VT , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; } return Res ; } } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = <NUM_LIT> / Amt . getScalarValueSizeInBits ( ) ; std :: vector < SDValue > Vals


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask


<s> if ( ! MO . isReg ( ) || Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; if ( MachineInstr * Def = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ) if ( Def -> getParent ( ) == & MBB ) MFI . unstackifyVReg ( MO . getReg ( ) ) ; } } for ( auto I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ) { MachineInstr & MI = * I ++ ; if ( ! <STR_LIT> ( MI . getOpcode ( ) ) ) continue ; Register TeeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( OpInfo . OperandType == MCOI :: OPERAND_IMMEDIATE ) return true ; if ( OpInfo . RegClass < <NUM_LIT> ) return false ; if ( MO . isImm ( ) && isInlineConstant ( MO , OpInfo ) ) return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ; return RI . opCanUseLiteralConstant (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> >

& Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , LocVT , LocInfo ) ) ; return


<s> FunctionPass * llvm :: create<ISA_LIT>SPReducePass (


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( IsExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( FirstTblReg + NumVecs ) ) ; Ops . push_back ( getAL ( CurDAG ) ) ; Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , Ops . data ( )


<s> unsigned <ISA_LIT>AsmBackend :: getNumFixupKinds ( )


<s> DebugLoc CurDL ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) EmitBasicBlockStart ( I ) ; for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { DebugLoc DL = II -> getDebugLoc ( ) ; if ( ! DL . isUnknown ( ) && DL


<s> unsigned <ISA_LIT>AsmParser :: matchRegister ( StringRef Name


<s> virtual const char * getPassName ( ) const { return


<s> SDValue <ISA_LIT>TargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { return makeAddress ( Op


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Enable<ISA_LIT>LongCalls ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg (


<s> if ( ! NewOpcode ) { uint64_t NumBytes = Offset - <NUM_LIT> ; emitIncrement ( MBB , MBBI , DL , MBBI -> getOperand ( AddrOpNo ) . getReg ( ) , NumBytes , ZII ) ; Offset -= NumBytes ; NewOpcode = ZII -> getOpcodeForOffset ( Opcode , Offset ) ; assert ( NewOpcode && <STR_LIT> ) ; } MBBI -> setDesc ( ZII -> get ( NewOpcode ) ) ; MBBI -> getOperand ( AddrOpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else if ( StackSize ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT>


<s> return new <ISA_LIT>PassConfig ( * this ,


<s> T V = Queue . front ( ) ; Queue . pop ( ) ; Set . erase (


<s> static MachineInstr * genFusedMultiplyIdxNeg ( MachineFunction & MF , MachineRegisterInfo & MRI , const TargetInstrInfo * TII , MachineInstr & Root , SmallVectorImpl < MachineInstr * > & InsInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg , unsigned IdxMulOpd , unsigned MaddOpc , unsigned MnegOpc , const TargetRegisterClass * RC ) { assert ( IdxMulOpd == <NUM_LIT> ) ; Register NewVR = genNeg ( MF , MRI , TII , Root , InsInstrs , InstrIdxForVirtReg , MnegOpc ,


<s> void <ISA_LIT>LowerControlFlowPass :: computeIndirectRegAndOffset ( unsigned VecReg , unsigned & Reg , int & Offset ) { unsigned SubReg = TRI -> getSubReg ( VecReg , <STR_LIT> ) ; if ( ! SubReg ) SubReg = VecReg ; const TargetRegisterClass * RC = TRI -> getPhysRegClass ( SubReg ) ; int RegIdx = TRI -> getHWRegIndex


<s> } assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; unsigned SubRegIdx0 , SubRegIdx1 ; std :: tie ( SubRegIdx0 , SubRegIdx1 ) = getSubRegIdxs ( CI , Paired ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> )


<s> if ( ST -> has16BitInsts ( ) && needsPromotionToI32 ( I . getType ( ) ) && DA -> isUniform ( & I ) ) Changed |= promoteUniformOpToI32 ( I ) ; return Changed


<s> assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind

== k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ) && <STR_LIT> ) ;


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName =


<s> <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , VecIns . back ( ) , CC , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ; return V ; } } if ( Op . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> BinOp ; if ( SDValue Match = DAG . matchBinOpReduction ( Op . getNode ( ) , BinOp , { <STR_LIT> } ) ) { <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , Match , CC , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL ,


<s> return SelectCode ( N ) ; } return nullptr ; } } unsigned Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget . hasHighWord ( ) ) { Opcode = <STR_LIT> ; OpcodeVT = <STR_LIT> ; RISBG . Start &= <NUM_LIT> ; RISBG . End &= <NUM_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { getUNDEF ( SDLoc ( N ) , OpcodeVT ) , convertTo ( SDLoc ( N ) , OpcodeVT , RISBG . Input ) , CurDAG -> getTargetConstant ( RISBG . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . End | <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , OpcodeVT ,


<s> assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Kind ) { case


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { bool isPtrReg = false ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) ) ; } else { O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op .


<s> O << '\n' ; if ( ! GVNonLazyPtrs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( StringMap < std :: string > :: iterator I = GVNonLazyPtrs . begin ( ) , E = GVNonLazyPtrs . end ( ) ; I != E ; ++ I ) { O << I -> second << <STR_LIT> ; O << <STR_LIT> << I -> getKeyData ( ) << <STR_LIT> ; O <<


<s> return CurDAG -> getTargetConstant (


<s> switch ( CalleeMO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : if ( CalleeMO . getImm ( ) ) CalleeMCOp = MCOperand :: createImm ( CalleeMO . getImm ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } unsigned ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; if ( <STR_LIT> ( ScratchReg ) ) EncodedBytes = <NUM_LIT> ; else EncodedBytes = <NUM_LIT> ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addOperand ( CalleeMCOp ) ) ; if ( Subtarget -> useRetpolineIndirectCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes && <STR_LIT> )


<s> static bool ft32_frame_pointer_required ( void ) { return cfun -> calls_alloca


<s> bool isImage ( const Value & val ) { return isImageReadOnly ( val ) || isImageWriteOnly ( val ) ||


<s> SDValue M0F = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Mask0F ) ; SmallVector < SDValue , <NUM_LIT> > Four ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FourV = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Four ) ; SDValue HighNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , FourV ) ; SDValue LowNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , M0F ) ; SDValue HighPopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , InRegLUT , HighNibbles ) ; SDValue LowPopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , InRegLUT , LowNibbles ) ; SDValue PopCnt = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , HighPopCnt , LowPopCnt ) ; if ( EltVT == <STR_LIT> ) return


<s> if ( ! llvm :: <STR_LIT> ( Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return GA -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS && ! shouldEmitGOTReloc ( GA -> getGlobal


<s> vld3q_dup_u16 ( const uint16_t * __a ) { uint16x8x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t


<s> static int mips_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { struct mips_arg_info


<s> return ( int16x8_t ) __builtin_neon_vmlalsv8qi ( __a ,


<s> const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <NUM_LIT> , false , false , MachinePointerInfo

( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> std :: vector < std :: string > app ( Ab c , SumBase base , bool sub_p0 ,

bool p0_align , bool sub_p1 , bool p1_align ) {


<s> bool hasRor ( ) const { return HasRor


<s> ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , BodyBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( BodyBB ) ; BodyBB -> addSuccessor ( LoopBB ) ; BodyBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , End , MBB . end ( ) ) ; BodyBB -> splice ( BodyBB -> begin ( ) , & MBB , Begin , MBB . end ( ) ) ; MBB . addSuccessor ( LoopBB ) ; if ( MDT ) { MDT -> addNewBlock ( LoopBB , & MBB ) ; MDT -> addNewBlock ( BodyBB , LoopBB ) ; MDT -> addNewBlock ( RemainderBB , BodyBB ) ; for ( auto & Succ : RemainderBB -> successors ( ) ) { if ( MDT -> properlyDominates ( & MBB , Succ ) ) { MDT -> changeImmediateDominator ( Succ , RemainderBB ) ; } } } emitLoadSRsrcFromVGPRLoop ( TII , MRI , MBB , * LoopBB , * BodyBB , DL , Rsrc ) ; MachineBasicBlock :: iterator First = RemainderBB -> begin ( ) ; BuildMI ( * RemainderBB , First , DL , TII . get ( MovExecOpc ) , Exec ) . addReg ( SaveExec ) ; return BodyBB


<s> SMLoc S = getLoc ( ) ; StringRef Value ; OperandMatchResultTy res ; SMLoc StringLoc ; res = parseStringWithPrefix ( Prefix , Value , StringLoc ) ; if ( res != MatchOperand_Success ) { return res ; } int64_t Int ; Int = StringSwitch < int64_t > ( Value ) . Case ( <STR_LIT> , SdwaSel :: BYTE_0 ) . Case ( <STR_LIT> , SdwaSel :: BYTE_1 ) . Case ( <STR_LIT> , SdwaSel :: BYTE_2 ) . Case ( <STR_LIT> , SdwaSel :: BYTE_3 ) . Case ( <STR_LIT> , SdwaSel :: WORD_0 ) . Case ( <STR_LIT> , SdwaSel :: WORD_1 ) . Case ( <STR_LIT> , SdwaSel :: DWORD ) . Default ( <NUM_LIT> ) ; if ( Int ==


<s> static bool needsFP ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF


<s> if ( MO . isExpr ( ) && MO . getExpr ( ) -> getKind ( ) == MCExpr :: SymbolRef ) return <NUM_LIT> ; llvm_unreachable (


<s> SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const char * <ISA_LIT>16HelperFunction = nullptr ; bool Need<ISA_LIT>16Helper = false ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = std :: lower_bound ( std :: begin ( <ISA_LIT>16IntrinsicHelper ) , std :: end ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . getArgs ( ) , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy ( DAG .


<s> return __builtin_mve_vrmlaldavhxq_sv4si ( __a ,


<s> } unsigned OpNo = <NUM_LIT> ; for ( unsigned e = MI . getNumOperands ( ) ; OpNo < e ; ++ OpNo ) { if ( & MO == & MI . getOperand ( OpNo ) ) break ; } const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( <STR_LIT> ( Desc , OpNo ) ) { uint32_t Enc = getLitEncoding ( MO , Desc . OpInfo [ OpNo ] , STI ) ; if ( Enc != ~ <NUM_LIT> && ( Enc != <NUM_LIT> || Desc . getSize ( ) == <NUM_LIT> ) ) return Enc ; } else if ( MO . isImm ( ) ) return MO . getImm ( ) ; llvm_unreachable ( <STR_LIT> ) ; return


<s> addPass ( create<ISA_LIT>OptimizePICCallPass ( get<ISA_LIT>TargetMachine (


<s> else if ( MASK_REGNO_P ( regno ) ) return HImode ; else if ( MMX_REGNO_P ( regno )


<s> if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , addV . getValueType (


<s> case <STR_LIT> ## SUFFIX : \ case <STR_LIT> ## SUFFIX : switch ( ReductionID ) { <ISA_LIT>C_VP_CASE ( add ) <ISA_LIT>C_VP_CASE ( and ) <ISA_LIT>C_VP_CASE ( or ) <ISA_LIT>C_VP_CASE ( xor )

<ISA_LIT>C_VP_CASE ( smax ) return true ;


<s> if ( min_offset < <NUM_LIT> || max_offset >= <NUM_LIT> ) return SImode ; else { if ( max_offset >=


<s> bool isImm0_508s4 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE ->


<s> delete DataSection ; delete BSSSection ; delete ReadOnlySection ; delete StaticCtorSection ; delete StaticDtorSection ; delete LSDASection ; delete EHFrameSection ; delete DwarfAbbrevSection


<s> if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( ! strict ) return true ; regno = reg_renumber [


<s> assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = getLoadRegOpcode ( DstReg , RC , TRI , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; <STR_LIT> ( BuildMI ( MBB , MI , DL , get ( Opc ) , DstReg


<s> const TargetRegisterInfo & getRegisterInfo ( ) const { return


<s> if ( get<ISA_LIT>Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { PM -> add ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint


<s> return { ST . getMinFlatWorkGroupSize ( ) , ST


<s> bool isu6_1Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false ,


<s> unsigned Other = MCELF :: getOther ( SymbolData ) << <NUM_LIT> ; Other &= ~ ELF :: STO_<ISA_LIT>64_LOCAL_MASK ; Other |= ( MCELF :: getOther ( Data ) << <NUM_LIT> ) & ELF :: STO_<ISA_LIT>64_LOCAL_MASK ; MCELF :: setOther ( SymbolData , Other >>


<s> bool <ISA_LIT>InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB

, unsigned NumCyles , BranchProbability Probability ) const {


<s> case Type :: PointerTyID : { const PointerType * PT = cast < PointerType > ( Ty ) ; const StructType * ST = dyn_cast < StructType > ( PT -> getElementType ( ) ) ; if ( ST && ST -> isOpaque ( ) ) { StringRef Name = ST -> getName ( ) ; if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { return <STR_LIT> ; } else if ( Name . startswith ( <STR_LIT> ) ) { return <STR_LIT> ; } else if ( Name == <STR_LIT> || Name == <STR_LIT> ) { const DataLayout & DL = getDataLayout ( ) ; return DL . getPointerSize ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> )


<s> else { rtx tmp = gen_rtx_REG ( Pmode , TEMP_REG_NUM ) ; emit_move_insn ( tmp , gen_int_mode ( sp_adjust , Pmode ) ) ; insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , tmp ) ) ; if ( ! epilogue_p ) note_kind = REG_FRAME_RELATED_EXPR ; } if ( epilogue_p ) note_kind = REG_CFA_ADJUST_CFA ; if ( note_kind != REG_NOTE_MAX ) { rtx cfa_adj = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , sp_adjust ) ) ; add_reg_note ( insn , note_kind


<s> if ( Producer >= <STR_LIT> && Producer <= <STR_LIT> ) if ( Consumer >= <STR_LIT> && Consumer <= <STR_LIT> ) return ( Consumer - <STR_LIT> ) & <NUM_LIT> ; if ( Producer2 != <STR_LIT> ) return Consumer == Producer ; return


<s> JCE . startGVStub ( GV , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) ptr ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) ptr ) >> <NUM_LIT> ) ) ; JCE . startGVStub ( GV , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) ptr ) ; return JCE . finishGVStub (


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitBPOSGE32 ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = llvm :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned VR1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Sink , Sink -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( )

) . addReg ( VR2 ) . addMBB ( FBB ) . addReg ( VR1 ) . addMBB ( TBB ) ;


<s> return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode1 , regno1 ) , GEN_INT ( offset1 ) ) ,

gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;


<s> if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( Subtarget . hasAVX2 ( )


<s> const SCEV * SCEVParser :: computeInit ( const SCEV * scev ) { while ( const SCEVAddRecExpr * temp = dyn_cast < SCEVAddRecExpr >

( scev ) ) scev = temp -> getStart ( ) ;


<s> const MCSection * <ISA_LIT>ELFMCAsmInfo :: getNonexecutableStackSection ( MCContext &


<s> case <STR_LIT> : addDSPCtrlRegOperands ( true , MI , MF ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> useOddSPReg ( ) ) { MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget -> isABI_FPXX ( ) && ! Subtarget -> hasMTHC1 ( ) ) MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isGlobal ( ) && MI . getOperand ( <NUM_LIT> )

. getGlobal ( ) -> getGlobalIdentifier ( ) == <STR_LIT> ) emitMCountABI ( MI , MBB , MF ) ;


<s> for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; i ++ ) { SDValue Op = BV -> getOperand ( i ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { std :: swap ( ExpectedOpcode , NextExpectedOpcode ) ; continue ; } if ( Opcode != ExpectedOpcode ) return SDValue ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return SDValue (


<s> int NumWideParts = ( ( WideBits % <NUM_LIT> ) ? ( ( WideBits / <NUM_LIT> ) + <NUM_LIT> ) : ( WideBits / <NUM_LIT> ) ) ; int NumElsPerVector = ( VecTy -> getVectorNumElements ( ) / NumWideParts ) ; int NumSrcParts = ( ( NumWideParts > NumElsPerVector ) ? NumElsPerVector : NumWideParts ) ; unsigned NumOperands = ( ( Opcode == Instruction :: Load ) ? Indices . size ( ) : Factor ) ; if ( NumSrcParts >


<s> bool is64Bit = Triple . getArch ( ) == Triple :: x86_64 ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString =


<s> SMLoc getStartLoc ( ) const override


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return


<s> void collectValueRotInfo ( ) { ValueRots . clear ( ) ; for ( auto & BG : BitGroups ) { unsigned RLAmtKey = BG . RLAmt + ( BG . Repl32 ? <NUM_LIT> : <NUM_LIT> ) ; ValueRotInfo & VRI = ValueRots [ std :: make_pair ( BG . V , RLAmtKey ) ] ; VRI . V = BG . V ; VRI . RLAmt = BG . RLAmt ; VRI . Repl32 =


<s> FunctionPass * llvm :: create<ISA_LIT>DelaySlotFillerPass ( <ISA_LIT>TargetMachine & tm


<s> for ( unsigned i = <NUM_LIT> , e = numOp ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Reg = MO . getReg ( )


<s> Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ ( RequiredAlign


<s> Register LowestAvailableVGPR , ReservedVGPR ; ArrayRef < MCPhysReg > AllVGPR32s = getAllVGPR32 ( ST , MF ) ; for ( MCPhysReg Reg : AllVGPR32s ) { if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) { LowestAvailableVGPR = Reg ; break ; } } if ( ! LowestAvailableVGPR ) return false ; ReservedVGPR = FuncInfo -> VGPRReservedForSGPRSpill ; const MCPhysReg * CSRegs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; int i = <NUM_LIT> ; for ( MachineBasicBlock & MBB : MF ) { for ( auto Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( Reg . VGPR == ReservedVGPR ) { MBB . removeLiveIn ( ReservedVGPR ) ; MBB . addLiveIn ( LowestAvailableVGPR ) ; Optional < int >


<s> return std :: find ( Exts . begin ( ) , Exts . end ( ) , E


<s> OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } else { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D1 ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D2 ) ; OutStreamer . AddComment (


<s> bool llvm :: getReqNTIDz ( const Function & F , unsigned & z ) { return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm ::


<s> bool Filler :: delayHasHazard ( MachineBasicBlock :: iterator candidate , bool & sawLoad , bool & sawStore , SmallSet < unsigned , <NUM_LIT> > & RegDefs , SmallSet < unsigned , <NUM_LIT> > & RegUses ) { if ( candidate -> isImplicitDef ( ) || candidate -> isKill ( ) ) return true ; if ( candidate -> mayLoad ( ) ) { if ( sawStore ) return true ; sawLoad = true ; } if ( candidate -> mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ; if ( sawLoad ) return true ; } assert ( ( ! candidate -> isCall ( ) && ! candidate -> isReturn ( ) ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( IsRegInSet ( RegDefs , Reg


<s> if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI , CurrentPredicate ) ; IsUse = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( IsDef && ! IsUse && VCTP && ! isVCTP ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) return true ; if ( ( Flags & <STR_LIT> ) == <NUM_LIT> && ! IsUse ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << *


<s> void AMDGPURegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , RegScavenger * RS ) const { assert ( ! <STR_LIT>


<s> gcc_assert ( CONST_INT_P ( op ) ) ; HOST_WIDE_INT opval = INTVAL ( op ) ; enum rtx_code scode = signed_condition ( code ) ; bool dec_p = ( scode == LT || scode == GE ) ; if ( code == EQ || code == NE ) { * alt_code = code ; * alt_op = op


<s> if ( ! MI ) return NULL ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } } return TargetInstrInfoImpl :: commuteInstruction (


<s> ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII

. get ( ADDriOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;


<s> Changed = true ; const TargetRegisterClass * SrcRC = IsVRReg ( SrcMO . getReg ( ) , MRI ) ? & <STR_LIT> : & <STR_LIT> ; assert ( ( IsF8Reg ( SrcMO . getReg ( ) , MRI ) || IsVRReg ( SrcMO . getReg ( ) , MRI ) || IsVSSReg ( SrcMO . getReg ( ) , MRI ) || IsVSFReg ( SrcMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . addOperand ( SrcMO ) . addImm ( IsVRReg ( SrcMO . getReg ( ) , MRI ) ? <STR_LIT> : <STR_LIT> ) ; SrcMO . setReg ( NewVReg ) ; } else if ( ! IsVSReg ( DstMO . getReg ( ) , MRI ) && IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * DstRC = IsVRReg ( DstMO . getReg ( ) , MRI ) ? & <STR_LIT> : & <STR_LIT>


<s> break ; case LT : libfunc = op_mode == DFmode ? ltdf_libfunc : ltsf_libfunc ; break ; case LE : libfunc = op_mode == DFmode ? ledf_libfunc : lesf_libfunc ; break ; default : gcc_unreachable ( ) ; } start_sequence ( ) ; cmp = emit_library_call_value ( libfunc , <NUM_LIT> , LCT_CONST , SImode , op0 , op_mode , op1 , op_mode ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) ; return gen_rtx_fmt_ee ( jump_code , mode , cmp


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodeFPR32RegisterClass ( Inst , Ry , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR32DecoderTable [ Ry + Imm5 ] ) ) ; return MCDisassembler ::


<s> const TargetRegisterClass * SuperRegClass = nullptr ; if ( ContiguousRegs && ( i < CSI . size ( ) - <NUM_LIT> ) ) { unsigned SuperRegNext = uniqueSuperReg ( CSI [ i + <NUM_LIT> ] . getReg ( ) , TRI ) ; SuperRegClass = TRI -> getMinimalPhysRegClass ( SuperReg ) ; CanUseDblStore = ( SuperRegNext == SuperReg ) ; } if ( CanUseDblStore ) { TII . storeRegToStackSlot ( MBB , MI , SuperReg , true , CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) , SuperRegClass , TRI ) ; MBB . addLiveIn ( SuperReg ) ; ++ i ; } else { ContiguousRegs = false ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; MBB . addLiveIn ( Reg )


<s> case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT>


<s> assert ( getGeneration ( ) <= NORTHERN_ISLANDS ) ; return CFALUBug


<s> getT2AddrModeImm8OpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = get<ISA_LIT>RegisterNumbering ( MO1 .


<s> static DecodeStatus DecodeThumbBROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const


<s> const MCExpr * getSubExpr ( ) const { return Expr


<s> SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; return SDValue ( N


<s> <ISA_LIT>LongBranch ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ) , LongBranchSeqSize ( ! IsPIC ? <NUM_LIT> : ( ABI == <ISA_LIT>Subtarget :: N64 ? <NUM_LIT> : ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( )


<s> num_bifs = <NUM_LIT> ; line = <NUM_LIT> ; if ( parse_bif ( ) == PC_PARSEFAIL ) { fprintf ( stderr , <STR_LIT> , bif_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } fclose ( bif_file ) ; create_bif_order ( ) ; fprintf ( stderr , <STR_LIT> ) ; rbt_dump ( & bif_rbt , bif_rbt . rbt_root ) ; fprintf ( stderr , <STR_LIT> ) ; num_ovld_stanzas = <NUM_LIT> ; num_ovlds = <NUM_LIT> ; line = <NUM_LIT> ; if ( parse_ovld ( ) == PC_PARSEFAIL ) { fprintf ( stderr , <STR_LIT> , ovld_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } fclose ( ovld_file ) ; fprintf ( stderr , <STR_LIT> ) ; rbt_dump ( & fntype_rbt , fntype_rbt . rbt_root ) ; fprintf ( stderr , <STR_LIT> ) ; if ( ! write_header_file ( ) ) { fprintf ( stderr , <STR_LIT> , header_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } if ( ! write_init_file ( ) ) { fprintf ( stderr , <STR_LIT> , init_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT> ) ; } if ( ! write_defines_file ( ) ) { fprintf ( stderr , <STR_LIT> , defines_path ) ; delete_output_files ( ) ; exit ( <NUM_LIT>


<s> SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackIndex ( ) , getPointerTy ( ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> )

, MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> opt_machine_mode arm_mode_to_pred_mode ( machine_mode mode ) { switch ( GET_MODE_NUNITS (


<s> void addRegShiftedImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegShiftedImm . SrcReg ) ) ; unsigned Imm = ( RegShiftedImm . ShiftImm == <NUM_LIT> ? <NUM_LIT> : RegShiftedImm . ShiftImm ) ; Inst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( RegShiftedImm . ShiftTy , Imm )


<s> const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateRotImm ( Val , S , EndLoc ) ) ; return MatchOperand_Success


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { return


<s> m_InputTLSGdSymbols . insert ( & pInfo ) ; m_MultipartList . back ( ) . m_TLSNum += <NUM_LIT> ; m_MultipartList . back ( ) . m_TLSDynNum += <NUM_LIT> ; return true


<s> static unsigned HOST_WIDE_INT mips_shift_truncation_mask ( machine_mode mode ) { if ( TARGET_LOONGSON_VECTORS && VECTOR_MODE_P ( mode ) ) return <NUM_LIT> ; return GET_MODE_BITSIZE ( mode )


<s> FunctionPass * llvm :: create<ISA_LIT>MIPeepholePass


<s> const MCExpr * getSubExpr ( ) const { return SubExpr


<s> int dst_regnum = xt_true_regnum ( operands [ <NUM_LIT> ] ) ; if ( dst_regnum == STACK_POINTER_REGNUM ) return ! TARGET_WINDOWED_ABI || ( mode == SImode && register_operand ( operands [ <NUM_LIT> ] , mode ) && ! ACC_REG_P ( xt_true_regnum ( operands [ <NUM_LIT> ] ) ) ) ; if ( ! ACC_REG_P ( dst_regnum ) ) return true ; } if ( register_operand ( operands [


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { assert ( ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumOperands ( ) || MII . get ( MI -> getOpcode ( ) ) . TSFlags == <NUM_LIT> ) && <STR_LIT> ) ; unsigned WAReg = Op . getReg ( ) ; if ( int ( WAReg ) >= <NUM_LIT> ) printRegName ( O , WAReg ) ; else if ( OpNo >= MII . get ( MI -> getOpcode ( ) ) . getNumDefs ( ) ) O << <STR_LIT> << ( WAReg & INT32_MAX ) ; else if ( WAReg != <ISA_LIT>FunctionInfo :: UnusedReg ) O << <STR_LIT> << ( WAReg & INT32_MAX ) ; else O << <STR_LIT> ; if ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumDefs ( ) ) O << '=' ; } else if ( Op . isImm ( ) ) { assert ( ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumOperands ( ) || ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) ) && <STR_LIT> <STR_LIT> ) ; O << Op . getImm ( ) ; } else if ( Op . isFPImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; assert ( OpNo < Desc . getNumOperands ( ) && <STR_LIT> ) ; assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ OpNo ] ; if ( Info . OperandType == <STR_LIT> ) { O << toString ( APFloat ( float ( Op . getFPImm ( ) ) ) ) ; } else { assert ( Info .


<s> unsigned NumBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList (


<s> __builtin_neon_vst3v8qi ( ( __builtin_neon_qi * ) __a ,