<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * LSBExpr ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( LSBExpr ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LSBExpr ) ; if ( ! CE ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t LSB = CE -> getValue ( ) ; if ( LSB < <NUM_LIT> || LSB > <NUM_LIT> ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * WidthExpr ; if ( getParser ( ) . ParseExpression ( WidthExpr ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CE = dyn_cast < MCConstantExpr > ( WidthExpr ) ; if ( ! CE ) { Error ( E ,


<s> } label = gen_label_rtx ( ) ; emit_label_after ( label , after ) ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( GET_CODE ( XEXP ( XEXP ( set , <NUM_LIT> ) , i ) ) == LABEL_REF ) { rtx ref = XEXP ( XEXP ( set , <NUM_LIT> ) , i ) ; if ( LABEL_NUSES ( XEXP ( ref , <NUM_LIT> ) ) == <NUM_LIT> ) delete_insn ( XEXP ( ref , <NUM_LIT> ) ) ; XEXP ( ref , <NUM_LIT> ) = label ; LABEL_NUSES ( label ) ++ ; JUMP_LABEL ( insn ) = label ; } INSN_CODE ( insn ) = -


<s> static DecodeStatus DecodeTAddrModeImm7 ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7 < shift > ( Inst , imm


<s> bool <ISA_LIT>InstrInfo :: isHVXVec ( const MachineInstr


<s> return ; } if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } const <STR_LIT> * Reg = <STR_LIT> ( Val ) ; if ( Reg && Reg -> Readable && Reg -> haveFeatures ( STI . getFeatureBits ( )


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI .


<s> const TypeSize & TySize = Ty -> getPrimitiveSizeInBits ( ) ; if ( TySize . isScalable ( ) && TySize . getKnownMinSize ( ) > <NUM_LIT> ) return true ; return false


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg )


<s> return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) )


<s> rtx set_src ( void ) const { return set_rtx == NULL_RTX ? NULL_RTX :


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; float FPImm = MO . isDFPImm ( ) ? bit_cast < double > ( MO .

getDFPImm ( ) ) : <STR_LIT> ( MO . getImm ( ) ) ;


<s> int nregs ; rtx result ; rtvec rtvec ; for ( nregs = <NUM_LIT> ; size > <NUM_LIT> ; size -= UNITS_PER_WORD ) { arg_regs [ nregs ] = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , reg ++ ) , GEN_INT ( nregs * UNITS_PER_WORD ) ) ; nregs ++ ; } assert ( ARRAY_SIZE ( arg_regs ) == <NUM_LIT>


<s> MachineBasicBlock :: iterator InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBB . findDebugLoc ( InsertPt ) ; if ( ! hasFP ( MF ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( unsigned NumBytes = MFI . getStackSize ( ) ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addImm ( NumBytes ) ; } return ; } MachineInstr * RetI = getReturn ( MBB ) ; unsigned RetOpc = RetI ? RetI -> getOpcode ( ) : <NUM_LIT> ; if ( RetOpc == <STR_LIT> ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( <STR_LIT> ) ; return ; } if ( RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> ) { MachineBasicBlock :: iterator It = RetI ; ++ It


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) || ! isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) || Op0 . getOperand ( <NUM_LIT> ) != Op1 . getOperand ( <NUM_LIT> ) ) return false ; unsigned I0 = cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( I0 != i ) return false ; if ( Opc [ i % <NUM_LIT> ] != <NUM_LIT> && Opc [ i % <NUM_LIT> ] != Opcode ) return false ; Opc [ i % <NUM_LIT> ] = Opcode ; if ( InVec0 . isUndef ( ) ) { InVec0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( InVec0 . getSimpleValueType ( ) !=


<s> if ( Subtarget . hasInt256 ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) return SDValue ( ) ; SDLoc DL ( N ) ; auto ExtendVecSize = [ & DAG ] ( const SDLoc & DL , SDValue N , unsigned Size ) { EVT InVT = N . getValueType ( ) ; EVT OutVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , Size / InVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / InVT . getSizeInBits ( ) , DAG . getUNDEF ( InVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } auto SplitAndExtendInReg = [ & ] (


<s> switch ( T . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops )


<s> int64_t Value = ConstExpr -> getValue ( ) ; return Value != <NUM_LIT> && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; return false


<s> } else if ( GET_CODE ( src ) == CONST_INT ) { int x , y ; if ( CONST_OK_FOR_I ( INTVAL ( src ) ) ) return <STR_LIT> ; else if ( CONST_OK_FOR_M ( INTVAL ( src ) ) ) return <STR_LIT> ; else if ( CONST_OK_FOR_N ( INTVAL ( src ) ) ) return <STR_LIT> ; else if ( try_constant_tricks ( INTVAL ( src ) , & x , & y ) ) return output_inline_const ( SImode , operands ) ; else return <STR_LIT> ; } else return <STR_LIT> ; } else if ( GET_CODE ( dst ) == MEM ) switch ( GET_MODE ( dst ) ) { case SImode : return <STR_LIT> ; case HImode : return <STR_LIT> ; case


<s> if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) > <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass


<s> Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get (

<STR_LIT> ) , Result ) . addReg ( Op ) ) ;


<s> inline AddrOpc getAM3Op ( unsigned AM3Opc


<s> int getVarArgsFrameOffset ( ) const { return VarArgsFrameOffset


<s> EVT ScalarVT = EVT :: getIntegerVT ( Ctx , <STR_LIT> / NumElts ) ; EVT MemVT = EVT :: getVectorVT ( Ctx , ScalarVT , NumElts , true ) ; return


<s> static void diagnose_openacc_conflict ( bool optval ,


<s> if ( AddrSpace == AS . GLOBAL_ADDRESS || AddrSpace == AS . CONSTANT_ADDRESS || AddrSpace == AS . CONSTANT_ADDRESS_32BIT || AddrSpace == AS . FLAT_ADDRESS ) return <NUM_LIT> ; if ( AddrSpace == AS . LOCAL_ADDRESS || AddrSpace == AS . REGION_ADDRESS ) return <NUM_LIT> ; if ( AddrSpace == AS . PRIVATE_ADDRESS ) return <NUM_LIT> * ST -> getMaxPrivateElementSize ( ) ; if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS && ( AddrSpace == AS . PARAM_D_ADDRESS || AddrSpace == AS . PARAM_I_ADDRESS || ( AddrSpace >= AS . CONSTANT_BUFFER_0 && AddrSpace <= AS . CONSTANT_BUFFER_15 ) ) ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT>


<s> if ( MO . isDef ( ) ) continue ; if ( MO . getReg ( ) == AMDGPU :: VCC ) return AMDGPU :: VCC ; if ( MO . getReg ( ) == AMDGPU :: FLAT_SCR ) return AMDGPU :: FLAT_SCR ; } unsigned UsedSGPRs [ <NUM_LIT> ] = { AMDGPU :: NoRegister } ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = OpIndices [ i ] ; if ( Idx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI -> getOperand ( Idx ) ; if ( RI . isSGPRClassID ( Desc . OpInfo [ Idx ] . RegClass ) ) SGPRReg = MO . getReg ( ) ; if ( MO . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) UsedSGPRs [ i ] = MO . getReg ( ) ; } if ( SGPRReg != AMDGPU :: NoRegister ) return SGPRReg ; if ( UsedSGPRs [ <NUM_LIT> ] != AMDGPU :: NoRegister ) { if ( UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] || UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] )


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) return false ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t FPOffset = Offset - <NUM_LIT> * <NUM_LIT> ; Offset += MFI -> getLocalFrameSize (


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OS , is64Bit ( )


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( needsStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; if ( AFI -> isThumbFunction ( ) && MFI -> hasVarSizedObjects ( ) ) { if ( AFI -> isThumb2Function ( ) && MFI -> getLocalFrameSize ( ) < <NUM_LIT> ) return false ; return true ; } return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; } uint64_t TSFlags = getInstDesc ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( TSFlags & <STR_LIT> ) && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) && ! hasEightFccRegisters ( ) ) return Match_NoFCCRegisterForCurrentISA ; return Match_Success


<s> else if ( ! TARGET_FPU && register_operand ( src , SFmode ) ) return <NUM_LIT> ; else if ( ! TARGET_FPU && TARGET_ARCH64 && register_operand ( src , DFmode ) ) return <NUM_LIT> ; else if ( return_p && TARGET_V9 && ! epilogue_renumber ( & pat , <NUM_LIT> ) && ( get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ) ) return <NUM_LIT> ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) && arith_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) ) return <NUM_LIT> ; else if ( GET_CODE ( src ) == PLUS && register_operand ( XEXP ( src , <NUM_LIT> ) , DImode ) && arith_double_operand ( XEXP ( src , <NUM_LIT> ) , DImode ) ) return <NUM_LIT> ; else if ( GET_CODE ( src ) == LO_SUM && ! TARGET_CM_MEDMID && ( ( register_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) && immediate_operand ( XEXP ( src , <NUM_LIT> ) , SImode ) ) || ( TARGET_ARCH64 && register_operand ( XEXP ( src

, <NUM_LIT> ) , DImode ) && immediate_operand ( XEXP ( src , <NUM_LIT> ) , DImode ) ) ) ) return <NUM_LIT> ;


<s> uint8_t OpFlagLo = IsPIC ? <STR_LIT> : <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> ,


<s> static void set_pic_reg_ever_live ( ) { if ( reload_in_progress ) df_set_regs_ever_live ( REGNO


<s> SmallVector < SDValue , <NUM_LIT> > Ops ( N -> op_begin ( ) , N -> op_end ( ) ) ; if ( SDValue R = combineConcatVectorOps ( SDLoc ( N ) , VT . getSimpleVT ( ) , Ops


<s> return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( )


<s> const int align = INTVAL ( align_rtx ) ; rtx dst_reg ; tree dst_expr ; if ( ! CONST_INT_P ( bytes_rtx ) || INTVAL ( bytes_rtx ) <= <NUM_LIT> ) return <NUM_LIT> ; dst_reg = copy_addr_to_reg ( XEXP ( dst , <NUM_LIT> ) ) ; if ( align >= <NUM_LIT> ) expand_block_set_4 ( dst , dst_reg


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val ) ) return C -> isAllOnesValue ( ) ; return


<s> if ( ! MI . hasOneMemOperand ( ) ) return false ; if ( mergedOpcode ( MI . getOpcode ( ) , false ) == <NUM_LIT> ) return false ; const MachineMemOperand * MemOperand = * MI . memoperands_begin ( ) ; if ( MemOperand -> isVolatile ( ) ) return false ; return true


<s> bool Modified = false ; MfIterator End = MF . end ( ) ; for ( MfIterator MFI = MF . begin ( ) ; MFI !=


<s> AVL = Op -> getOperand ( AVLIdx ) ; } else { AVL = CDAG . getConstant ( OpVecVT . getVectorNumElements ( ) , <STR_LIT> ) ; SDValue ConstTrue = CDAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Mask = CDAG . getBroadcast ( MaskVT , ConstTrue , AVL ) ; } if ( isVVPBinaryOp ( VVPOpcode ) ) { assert ( LegalVecVT . isSimple ( ) ) ; return CDAG . getNode ( VVPOpcode , LegalVecVT , { Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Mask , AVL } ) ; } if ( VVPOpcode == <STR_LIT> ) { auto Mask = Op -> getOperand ( <NUM_LIT> ) ; auto OnTrue = Op -> getOperand (


<s> return ! any_of ( M , [ & ] ( const Function & F ) { StringRef AttrVal = F . getFnAttribute ( Attr ) . getValueAsString ( ) ; return parseDenormalFPAttribute ( AttrVal


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return <NUM_LIT> - TFI ->


<s> frame_size_to_allocate = size ; gcc_assert ( ! ( size == <NUM_LIT> && gmask ) ) ; if ( frame -> pretend_size != <NUM_LIT> ) first_offset = - frame -> pretend_size ; if ( ARC_AUTO_IRQ_P ( fn_type ) && ! ARC_FAST_INTERRUPT_P ( fn_type ) ) { frame_stack_add ( first_offset ) ; first_offset = <NUM_LIT> ; arc_dwarf_emit_irq_save_regs ( ) ; } save_blink = arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) ; save_fp = arc_frame_pointer_needed ( ) && ! ARC_AUTOFP_IRQ_P ( fn_type ) ; if ( TARGET_CODE_DENSITY && TARGET_CODE_DENSITY_FRAME && ! ARC_AUTOFP_IRQ_P ( fn_type ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) && ! ARC_INTERRUPT_P ( fn_type ) && arc_enter_leave_p ( gmask ) ) frame_size_to_allocate -= arc_save_callee_enter ( gmask , save_blink , save_fp , first_offset ) ; else if ( frame -> millicode_end_reg > <NUM_LIT> ) frame_size_to_allocate -= arc_save_callee_milli ( gmask , save_blink , save_fp , first_offset , frame -> reg_size ) ; else frame_size_to_allocate -= arc_save_callee_saves ( gmask , save_blink , save_fp , first_offset ) ; if ( frame_size_to_allocate > <NUM_LIT> ) frame_stack_add ( ( HOST_WIDE_INT ) <NUM_LIT> - frame_size_to_allocate ) ; emit_insn ( gen_blockage


<s> if ( CONST_INT_P ( y ) ) y = GEN_INT ( INTVAL ( y ) & GET_MODE_MASK ( y_mode ) ) ; else { rtx t , cc_reg ; machine_mode cc_mode ; t = gen_rtx_ZERO_EXTEND ( SImode , y ) ; t = gen_rtx_COMPARE ( CC_SWPmode , t , x ) ; cc_mode = CC_SWPmode ; cc_reg = gen_rtx_REG ( cc_mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , t ) ; return cc_reg ; } } return aarch64_gen_compare_reg ( code , x ,


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( MI . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue


<s> if ( SDValue Flags = combineSetCCEFLAGS ( Cond , CC , DAG , Subtarget ) ) { if ( FalseOp . getValueType ( ) != <STR_LIT> || hasFPCMov ( CC ) ) { SDValue Ops [ ] = { FalseOp , TrueOp , DAG . getConstant ( CC , DL , <STR_LIT> ) , Flags } ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } } if ( ConstantSDNode * TrueC = dyn_cast < ConstantSDNode > ( TrueOp ) ) { if ( ConstantSDNode * FalseC = dyn_cast < ConstantSDNode > ( FalseOp ) ) { if ( TrueC -> getAPIntValue ( ) . ult ( FalseC -> getAPIntValue ( ) ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueC , FalseC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { Cond = getSETCC ( CC , Cond , DL , DAG ) ; Cond = DAG . getNode ( <STR_LIT> , DL , TrueC -> getValueType ( <NUM_LIT> ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , DL , <STR_LIT> ) ) ; return Cond ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { Cond = getSETCC ( CC , Cond , DL , DAG ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case


<s> static DecodeStatus DecodeThumbBLXOffset ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned S = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned J1 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned J2 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand (


<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && <ISA_LIT>SubTarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( FI ) ; SDValue Chain ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , array_lengthof ( Ops ) , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl

, Tmp , FIPtr , MPI , false , false , <NUM_LIT> ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; unsigned XorOp = MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MIB -> setDesc ( TII . get (


<s> MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator I = BB -> succ_begin ( ) , E = BB -> succ_end ( ) ; I != E ; ++ I ) { EM -> insert ( std :: make_pair ( * I , sinkMBB ) ) ; sinkMBB -> addSuccessor ( * I ) ; } while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr ( MI ) ; return BB ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineFunction * MF = BB -> getParent ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; bool SrcIsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( SrcReg != <STR_LIT> ) { const TargetRegisterClass * RC = MF -> getRegInfo ( ) . getRegClass ( SrcReg ) ; unsigned CopyOpc = ( RC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , dl , TII -> get ( CopyOpc ) , <STR_LIT>

) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT>


<s> int32_t V = cast < MCConstantExpr > ( HE -> getExpr ( ) ) -> getValue ( ) ; auto * NewCE = MCConstantExpr :: create ( V / int32_t ( VectorSize ) , Ctx ) ; auto * NewHE = <ISA_LIT>MCExpr :: create ( NewCE , Ctx ) ; T . addOperand ( MCOperand :: createExpr ( NewHE ) ) ; } return


<s> return findOneNVVMAnnotation ( & F , <STR_LIT>


<s> SDValue V1 = N -> getOperand ( i + <NUM_LIT> ) ; unsigned Reg0 = cast < RegisterSDNode > ( V0 ) -> getReg ( ) ; unsigned Reg1 = cast < RegisterSDNode > ( V1 ) -> getReg ( ) ; SDValue PairedReg ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( Kind == InlineAsm :: Kind_RegDef || Kind == InlineAsm :: Kind_RegDefEarlyClobber ) { unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , T0 , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , T1 , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , } ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR


<s> for ( auto & MI : MBB ) { MachineInstr * CurrInstr = & MI ; DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; if ( PrevInstr ) { DEBUG ( dbgs ( ) << <STR_LIT> << * PrevInstr << <STR_LIT> << * CurrInstr << <STR_LIT> << isFirstInstructionInSequence ( PrevInstr ) << <STR_LIT> << <STR_LIT> << isSecondInstructionInSequence ( CurrInstr ) << <STR_LIT> ) ; if ( isFirstInstructionInSequence ( PrevInstr ) && isSecondInstructionInSequence ( CurrInstr ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Idx << <STR_LIT> ) ; Sequences . push_back ( CurrInstr ) ; } } if ( ! CurrInstr -> isPseudo ( ) ) PrevInstr = CurrInstr ; ++


<s> EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal


<s> else if ( strcmp ( str , <STR_LIT> ) == <NUM_LIT> ) * val = indirect_branch_thunk_inline ; else if ( strcmp ( str , <STR_LIT> )

== <NUM_LIT> ) * val = indirect_branch_thunk_extern ;


<s> opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) { ix86_arch_mask = <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo


<s> return __builtin_mve_vcmpeqq_n_uv8hi ( __a ,


<s> emit_insn ( gen_rtx_SET ( VOIDmode , reg , gen_rtx_TRUNCATE ( int_mode , gen_rtx_LSHIFTRT ( TImode , src , GEN_INT ( int_mode == DImode ? <NUM_LIT> : <NUM_LIT> ) ) ) ) ) ; if ( int_mode !=


<s> const MachineOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; <STR_LIT> SOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned SBits = <NUM_LIT> ; unsigned Rs = MO1 . getReg ( ) ; if ( Rs ) { switch ( SOpc ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return


<s> EmitInstruction ( Out , MCInstBuilder


<s> explicit <ISA_LIT>MCAsmInfo ( const Triple & TT , const MCTargetOptions & Options ) { if ( TT . getArch ( ) == Triple :: bpfeb ) IsLittleEndian = false ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = true ; HasDotTypeDotSizeDirective = true ; SupportsDebugInformation =


<s> Register <ISA_LIT>GlobalRegistry :: buildConstantFP ( APFloat Val , MachineIRBuilder & MIRBuilder , <ISA_LIT>Type * SpvType ) { auto & MF = MIRBuilder . getMF ( ) ; Register Res ; const Type * LLVMFPTy ; if ( SpvType ) { LLVMFPTy = getTypeFor<ISA_LIT>Type ( SpvType ) ; assert ( LLVMFPTy -> isFloatingPointTy ( ) ) ; } else { LLVMFPTy = IntegerType :: getFloatTy ( MF . getFunction ( ) . getContext ( ) ) ; } const auto ConstFP = ConstantFP :: get ( LLVMFPTy -> getContext ( ) , Val ) ; if ( DT . find ( ConstFP , & MIRBuilder . getMF ( ) , Res ) == false ) { unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth ( SpvType ) : <NUM_LIT> ; Res = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: scalar ( BitWidth ) ) ; assignTypeToVReg ( LLVMFPTy , Res , MIRBuilder ) ; DT . add ( ConstFP , & MIRBuilder . getMF ( ) , Res ) ; MIRBuilder . buildFConstant ( Res , * ConstFP ) ; } return


<s> unsigned Opcode ; switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S32_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S64_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S128_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S256_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S512_RESTORE ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = MFI -> SpillTracker . getSpilledReg


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FrameReg =


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond ) -> get ( ) ; normalizeSetCC ( LHS , RHS , CC ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC


<s> const LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const LLT SrcTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( ! DstTy . isVector ( ) && ! SrcTy . isVector ( ) && <STR_LIT> ) ; if ( I . getNumOperands ( ) != <NUM_LIT> ) return false ; if ( DstTy . getSizeInBits ( ) != <NUM_LIT> || SrcTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; auto * DstRC = & <STR_LIT> ; Register SubToRegDef = MRI . createVirtualRegister ( DstRC ) ; MachineInstr & SubRegMI = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( SubToRegDef ) . addImm ( <NUM_LIT> ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; Register SubToRegDef2 = MRI . createVirtualRegister ( DstRC ) ; MachineInstr & SubRegMI2 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MachineInstr & BFM = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( SubToRegDef ) . addUse ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( SubRegMI , TII , TRI ,


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { if ( ST -> getCPUDirective ( ) == <STR_LIT> ) { UP . Partial = UP . Runtime =


<s> Name = ( Name [ <NUM_LIT> ] == 'r' ) ? Name . drop_front ( <NUM_LIT> ) : Name . drop_front ( ) ; switch ( Name . size ( ) ) { default : return - <NUM_LIT> ; case <NUM_LIT> : switch ( Name [ <NUM_LIT> ] ) { default : return - <NUM_LIT> ; case '0' : return <NUM_LIT> ; case '1' : return <NUM_LIT> ; case '2' : return <NUM_LIT> ; case '3' : return <NUM_LIT> ; case '4' : return <NUM_LIT> ; case '5' : return <NUM_LIT> ; case '6' : return <NUM_LIT> ; case '7' : return <NUM_LIT>


<s> if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( ! IsLittleEndian ) { FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ; assert ( ( Offset + FullSizeBytes ) <= DataSize && <STR_LIT> ) ; assert ( NumBytes <= FullSizeBytes && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( FullSizeBytes - <NUM_LIT> - i ) ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> (


<s> NumMemBound ++ ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; } if ( <STR_LIT> ( F . getCallingConv ( ) ) && needLimitWave ( * Info ) ) { LLVM_DEBUG ( dbgs ( ) << F . getName ( ) << <STR_LIT> ) ; NumLimitWave ++ ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; } return


<s> char ConstraintLetter = Constraint [ <NUM_LIT> ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode


<s> bool visitInstruction ( Instruction & )


<s> return ( crtl -> outgoing_args_size +


<s> bool <ISA_LIT>ELFObjectWriter :: needsRelocateWithSymbol ( unsigned Type ) const { switch ( Type ) { default : return true ; case ELF ::


<s> if ( SU -> getInstr ( ) != nullptr ) DAG -> dumpNode ( * SU ) ; else DAG -> dumpNodeName ( * SU


<s> int ok = <NUM_LIT> ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) <= MAX_LD_OFFSET ( GET_MODE ( x ) ) ) ) { rtx xx = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT>


<s> MVT ExtVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ( ExtVT != <STR_LIT> || Subtarget -> is64Bit ( ) ) && SrcOp . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == ExtVT ) { OpVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , SrcOp . getOperand ( <NUM_LIT> ) . getOperand


<s> getRegClassForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) != <NUM_LIT> ) return std :: vector < unsigned > ( ) ; switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : return make_vector < unsigned > ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> return get ( MI . getOpcode ( ) ) . TSFlags &


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect (


<s> SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget -> hasXMMInt ( ) , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or


<s> assert ( BasePtrVreg != - <NUM_LIT> && <STR_LIT>


<s> else { int rd ; uint32_t u = i ; for ( rd = <NUM_LIT> ; rd < <NUM_LIT> ; rd ++ ) { u = ( ( u >> <NUM_LIT> ) & <NUM_LIT> ) | ( u << <NUM_LIT> ) ; if ( ( - <NUM_LIT> <= ( int32_t ) u ) && ( ( int32_t ) u <= <NUM_LIT> ) ) { ft32_load_immediate ( dst , ( int32_t ) u ) ; sprintf ( pattern , <STR_LIT> , rd ) ; output_asm_insn ( pattern , & dst ) ; return <STR_LIT> ; } } ft32_load_immediate ( dst , i >> <NUM_LIT> ) ; sprintf ( pattern , <STR_LIT> , i & <NUM_LIT> ) ; output_asm_insn ( pattern , & dst


<s> AllAnalyzable &= Term . isBranch ( ) && ! Term . isIndirectBranch ( ) ; } assert ( ( AnyBarrier || AllAnalyzable ) && <STR_LIT> ) ; if ( AllAnalyzable ) MBB


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator Start = std :: begin ( ReduceTable ) ; llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator End = std :: end ( ReduceTable ) ; std :: pair < llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator , llvm :: SmallVector < ReduceEntry , <NUM_LIT> > :: const_iterator > Range = std :: equal_range (


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & Base = MI -> getOperand ( OpNo ) ; const MachineOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else llvm_unreachable ( <STR_LIT> ) ; if ( Offset . isImm ( ) ) { if ( Offset . getImm ( ) ) O << <STR_LIT> << Offset . getImm ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } return false


<s> unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) ,


<s> void <ISA_LIT>InstPrinter :: printSpecialCapRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; auto SpecialCapReg = <STR_LIT>


<s> break ; case llvm :: ELF :: R_HEX_GOT_11_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; result_u = GOT_S - GOT ; pReloc . target ( ) |= ApplyMask < uint32_t > ( bitMask , result_u ) ; return Relocator :: OK ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) { int32_t range = <NUM_LIT> << ( effectiveBits - <NUM_LIT> ) ; if ( ( result > range - <NUM_LIT> ) || ( result < - range ) ) return Relocator :: Overflow ; } pReloc . target ( ) |= ApplyMask < int32_t > ( bitMask ,


<s> unsigned Count ; if ( ! shouldInsertExtraNopBytesForCodeAlign ( AF , Count ) || ( Count == <NUM_LIT> ) ) return false ; MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue = <NUM_LIT>


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case FK_Data_4 :


<s> if ( ST . isThumb ( ) ) Ret += <STR_LIT> ; if ( ! ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; if ( ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . isThumb ( ) || ST . isAPCS_ABI ( ) ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else if ( ST . isAAPCS_ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return


<s> unsigned ExtraStepsF = <NUM_LIT> , ExtraStepsD = ExtraStepsF + <NUM_LIT> ; bool UseRsqrt = ST . useRSqrt ( ) ; TM . Options . Reciprocals . setDefaults ( <STR_LIT> , UseRsqrt , ExtraStepsF ) ; TM . Options . Reciprocals . setDefaults ( <STR_LIT> , UseRsqrt


<s> static <ISA_LIT>Operand * CreateMem ( <ISA_LIT>Operand * Base , const MCExpr * Off

, SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { if ( unsigned SubReg = MO . getSubReg ( ) ) { assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ; return RI . getNumChannelsFromSubReg ( SubReg ) * <NUM_LIT> ; } } return RI . getRegSizeInBits ( * getOpRegClass ( MI , OpNo )


<s> SDValue <ISA_LIT>TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL (


<s> if ( ! EHInfo ) report_fatal_error ( <STR_LIT> ) ; auto * FINode = dyn_cast < FrameIndexSDNode > ( RegNode ) ; if ( ! FINode ) report_fatal_error ( <STR_LIT> ) ; EHInfo -> EHRegNodeFrameIndex = FINode -> getIndex (


<s> printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; } if ( ! printAliasInstr ( MI , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode (


<s> <ISA_LIT>ModeRegisterDefaults Mode ; Mode . DX10Clamp = true ; Mode . IEEE = <STR_LIT> (


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned


<s> if ( region . readBytes ( address , <NUM_LIT> , ( uint8_t * ) Bytes , NULL ) == - <NUM_LIT> ) { size = <NUM_LIT> ; return MCDisassembler :: Fail ; } insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [


<s> for ( SmallVector < MachineInstr * , <NUM_LIT> > :: iterator II = DefSrcs . begin ( ) , EE = DefSrcs . end ( ) ; II != EE ; ++ II ) { MachineInstr * MI = * II ; if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; unsigned DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & I . getOperand ( ) ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVector < MachineOperand * , <NUM_LIT> > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I


<s> int <ISA_LIT>FrameLowering :: getSEHFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const auto * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF

. getSubtarget ( ) . getRegisterInfo ( ) ) ;


<s> static enum calling_abi ix86_function_abi ( const_tree fndecl ) { if ( ! fndecl


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked (


<s> fputs ( <STR_LIT> , file ) ; return ; } if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) && ! TARGET_SECURE_PLT && ( ! constant_pool_empty_p ( ) || crtl -> profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , * orig_name ; orig_name = ( * targetm . strip_name_encoding ) ( name ) ; desc_name = orig_name ; while ( * desc_name == '.' ) desc_name ++ ; if ( TREE_PUBLIC ( decl ) ) fprintf ( file ,


<s> qword q ; short s [ <NUM_LIT> ] ; } x ; x . q = q


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { if ( DarwinDirective == <STR_LIT> ) return false ; Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; if ( is<ISA_LIT>64 ( ) ) CriticalPathRCs . push_back


<s> if ( ! MEM_P ( mem ) ) return false ; if ( get_attr_indexed ( insn ) == INDEXED_YES || get_attr_update ( insn ) == UPDATE_YES ) return false ; machine_mode mem_mode = GET_MODE ( mem ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; enum non_prefixed_form non_prefixed = reg_to_non_prefixed ( reg , mem_mode ) ; if ( non_prefixed == NON_PREFIXED_X && is_lfs_stfs_insn ( insn ) ) return address_is_prefixed ( addr , mem_mode , NON_PREFIXED_DEFAULT ) ; else return address_is_prefixed ( addr , mem_mode , non_prefixed


<s> Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg

, RegState :: Kill ) . addImm ( ThisVal ) ) . setMIFlags ( MIFlags ) ;


<s> bool OptForSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) || MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; if ( ! OptForSize ) return false ; unsigned StackAlign = TFL -> getStackAlignment ( ) ; int64_t Advantage = <NUM_LIT> ; for ( auto CC : CallSeqMap ) { if ( CC . second . NoStackParams ) continue ; if ( ! CC . second . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( CC . second . ExpectedDist %


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: PIC_ ; return * RM


<s> bool <ISA_LIT>AsmPrinter :: isImageType ( Type * Ty ) { std :: map < Type * , std :: string > ::

iterator PI = TypeNameMap . find ( Ty ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { llvm_unreachable (


<s> OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegName ( RegShiftedReg . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegName ( RegShiftedReg . ShiftReg ) << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegName ( RegShiftedImm . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_ModifiedImmediate : OS << <STR_LIT> << ModImm . Bits << <STR_LIT> << ModImm . Rot << <STR_LIT> ; break ; case k_ConstantPoolImmediate : OS << <STR_LIT> << * getConstantPoolImm ( ) ; break ; case k_BitfieldDescriptor : OS << <STR_LIT> << <STR_LIT> << Bitfield . LSB << <STR_LIT> << Bitfield . Width << <STR_LIT> ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << RegName ( * I ) ; if ( ++ I < E ) OS << <STR_LIT> ; } OS << <STR_LIT> ; break ; } case k_VectorList : OS << <STR_LIT> << VectorList . Count << <STR_LIT> << RegName ( VectorList . RegNum ) << <STR_LIT> ; break ; case k_VectorListAllLanes


<s> case InlineAsm :: Constraint_m : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } SDLoc DL ( Op ) ; SDValue AluOp = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; ; OutOps . push_back ( Op0 ) ; OutOps . push_back (


<s> assert ( Kind == Register && <STR_LIT> ) ; return Reg


<s> } if ( ! FPIsUsed ) return false ; TII = MF . getTarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( df_ext_iterator < MachineBasicBlock * , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > > I = df_ext_begin ( Entry , Processed ) , E = df_ext_end ( Entry , Processed ) ; I != E ; ++ I ) Changed |= processBasicBlock ( MF , * * I ) ; if ( MF . size ( ) != Processed . size ( ) ) for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) if ( Processed . insert ( BB ) ) Changed |= processBasicBlock ( MF , * BB ) ; BlockBundle . clear


<s> if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: <ISA_LIT>_FastCall ) ; F -> addAttribute ( <NUM_LIT> , Attribute :: AttrKind :: InReg ) ; } return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple (


<s> case FrameHelperType :: Epilog : for ( auto NextMI = NextMBBI ; NextMI != MBB . end ( ) ; NextMI ++ ) { if ( NextMI -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } for ( const MachineBasicBlock * SuccMBB : MBB . successors ( ) ) { if ( SuccMBB -> isLiveIn ( <STR_LIT> ) || SuccMBB -> isLiveIn ( <STR_LIT> ) ) return false ; } break ; case FrameHelperType :: EpilogTail : { if ( NextMBBI == MBB .


<s> } MVT WideVT = ExtVT ; if ( ! ExtVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { NumElts *= <NUM_LIT> / ExtVT . getSizeInBits ( ) ; InVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; In = DAG . getNode ( <STR_LIT> , dl , InVT , DAG . getUNDEF ( InVT ) , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; WideVT = <STR_LIT> ( ExtVT . getVectorElementType ( ) , NumElts ) ; } SDValue V ; MVT WideEltVT = WideVT . getVectorElementType ( ) ; if ( ( Subtarget . hasDQI ( ) && WideEltVT . getSizeInBits ( ) >= <NUM_LIT> ) || ( Subtarget . hasBWI ( ) && WideEltVT . getSizeInBits ( ) <= <NUM_LIT> ) ) { V = DAG . getNode ( <STR_LIT> , dl , WideVT , In ) ; } else { SDValue NegOne = getOnesVector ( WideVT ,


<s> lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; new_optimize = build_optimization_node ( & func_options ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) << <STR_LIT> ) ; SmallVector < MachineInstr * , <NUM_LIT> > SplitPoints ; char State = BI . InitialState ; auto II = MBB . getFirstNonPHI ( ) , IE = MBB . end ( ) ; while ( II != IE ) { auto Next = std :: next ( II ) ; MachineInstr & MI = * II ; if ( StateTransition . count ( & MI ) ) State = StateTransition [ & MI ] ; MachineInstr * SplitPoint = nullptr ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : SplitPoint = lowerKillI1 ( MBB , MI , State == StateWQM ) ; break ; case <STR_LIT> : SplitPoint = lowerKillF32 ( MBB ,


<s> unsigned CCMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LivePhysRegs LiveRegs ( TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineBasicBlock * RestMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) RestMBB -> addLiveIn ( * I ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MoveMBB -> addLiveIn ( * I ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid ) . addMBB ( RestMBB ) ; MBB . addSuccessor ( RestMBB ) ; MBB . addSuccessor ( MoveMBB )


<s> MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , & BB , std :: next ( MachineBasicBlock :: iterator ( I ) ) , BB . end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( & BB ) ; BB . addSuccessor ( loop1MBB , BranchProbability :: getOne ( ) ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BuildMI ( loop1MBB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop1MBB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ; loop1MBB -> addLiveIn ( Ptr ) ; loop1MBB -> addLiveIn ( OldVal ) ; BuildMI ( loop2MBB , DL , TII -> get ( SC ) , NewVal ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop2MBB , DL , TII -> get ( BEQ ) ) . addReg ( NewVal , RegState :: Kill ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; loop2MBB -> addLiveIn ( Ptr ) ; loop2MBB -> addLiveIn ( NewVal ) ; addPostLoopLiveIns ( exitMBB ,


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT


<s> return ( GET_CODE ( op ) == MEM && inside_ba_p ( XEXP ( op , <NUM_LIT> ) , strict ) ) || ( reload_in_progress && GET_CODE ( op ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER ) || ( reload_in_progress && GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( XEXP ( op ,

<NUM_LIT> ) , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; } if ( Subtarget -> hasAVX ( ) ) { if ( ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) || ( ( VT == <STR_LIT> ) && ( OpVT == <STR_LIT> ) ) ) { SDValue ZeroVec = getZeroVector ( OpVT , Subtarget , DAG , dl ) ; SDValue OpLo = getTargetShuffleNode ( <STR_LIT> , dl , OpVT , N0 , ZeroVec , DAG ) ; SDValue OpHi = getTargetShuffleNode ( <STR_LIT> , dl , OpVT , N0 , ZeroVec , DAG ) ; EVT HVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType (

) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ;


<s> return ( uint32x4_t ) ( vabsq_f32 ( __a ) < vabsq_f32 ( __b ) ) ; return ( uint32x4_t ) __builtin_neon_vcagtv4sf (


<s> return TFI -> hasFP ( MF ) ? TFI -> getFPReg ( ) : TFI


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot ,

const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned adjustment = <NUM_LIT> ; if ( MF . protectReturnPtr ( ) && ! MF . getName ( ) . equals ( <STR_LIT> ) ) adjustment += RegInfo -> getSlotSize ( ) ; if ( hasFP ( MF ) && MF . protectFramePtr ( ) ) adjustment += RegInfo -> getSlotSize


<s> if ( ! fseek ( stream , <NUM_LIT> , SEEK_END ) ) { long s = ftell ( stream ) ; if ( s >= <NUM_LIT> ) alloc = s + <NUM_LIT> ; fseek ( stream , <NUM_LIT> , SEEK_SET ) ; } buffer = XNEWVEC ( char , alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , <NUM_LIT> , alloc - base - <NUM_LIT> , stream ) ; if ( ! n ) break ; base += n ; if ( base + <NUM_LIT> == alloc ) { alloc *= <NUM_LIT> ; buffer = XRESIZEVEC ( char , buffer ,


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildStore ( ExtReg , Addr ,


<s> if ( rclass == CCREGS ) return mode == BImode ; if ( mode == PDImode || mode == V2PDImode ) return regno == REG_A0 || regno == REG_A1 ; if ( mode == DImode )


<s> MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B ,


<s> void \ zbss_section ( ) \ { \ if ( in_section != in_zbss ) \ { \ fprintf ( asm_out_file , <STR_LIT> , ZBSS_SECTION_ASM_OP ) ; \ in_section = in_zbss


<s> static char buf [ <NUM_LIT> ] ; bool useskip ; int nullify = INSN_ANNULLED_BRANCH_P ( insn ) ; int length = get_attr_length ( insn ) ; int xdelay ; if ( branch_to_delay_slot_p ( insn ) ) return <STR_LIT> ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode && operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode && operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , <NUM_LIT> ) ; if ( length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = <NUM_LIT> ; if ( ! nullify && length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = forward_branch_p ( insn ) ; useskip = ( length == <NUM_LIT> && nullify ) ? use_skip_p ( insn ) : FALSE ; switch ( length ) { case <NUM_LIT> : if ( useskip ) strcpy ( buf , <STR_LIT> ) ; else strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( useskip ) strcat ( buf , <STR_LIT> ) ; else if ( nullify ) { if ( branch_needs_nop_p ( insn ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else strcat ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( dbr_sequence_length ( ) != <NUM_LIT> && ! forward_branch_p ( insn ) && nullify ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; strcat ( buf , <STR_LIT> ) ; } else if ( dbr_sequence_length ( ) == <NUM_LIT> && ! forward_branch_p ( insn ) && INSN_ADDRESSES_SET_P ( ) && VAL_14_BITS_P ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( insn ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) - <NUM_LIT> ) ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat (


<s> unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode (


<s> return ( __m256i ) __builtin_ia32_cvttpd2dq512_mask ( ( __v8df ) __A , ( __v8si ) _mm256_setzero_si256 ( ) ,


<s> if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ; else return <NUM_LIT> + ( regno - FIRST_VFP_REGNUM ) / <NUM_LIT> ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; switch ( OpTransfer ) { case OT_Operand2 : MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; break ; case OT_Operands02 : { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; break ; } case OT_OperandsXOR : { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } break ; } case OT_OperandsMovep : case OT_OperandsLwp : case OT_OperandsSwp : { if ( ConsecutiveForward ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( OpTransfer == OT_OperandsMovep ) MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; else MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; if ( OpTransfer == OT_OperandsMovep ) MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; else MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI2 << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; MBB . erase_instr ( MI2 ) ; return true ; } default : llvm_unreachable ( <STR_LIT> ) ; } MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; return true ; } return false


<s> bool explicit_type_suffix_p ( unsigned int i ) const override { return ( EXPLICIT_MASK >>


<s> MCSymbolRefExpr :: VariantKind <ISA_LIT>AsmParser :: getVariantKind ( StringRef Symbol ) { MCSymbolRefExpr :: VariantKind VK = StringSwitch < MCSymbolRefExpr :: VariantKind > ( Symbol ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) . Default ( MCSymbolRefExpr :: VK_None ) ; return VK


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { unsigned NumRet = Outs . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getFrameLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , <STR_LIT> ) ; SDValue BS = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue RetVal ; for ( unsigned i = <NUM_LIT> ; i < NumRet ; ++ i ) { RetVal = OutVals [ i ] ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , RetVal , ES , BS , DAG . getConstant ( i , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> SDLoc DL ( Op ) ; SDValue AluOp = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; ; OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ; return


<s> static DecodeStatus decodeU8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const


<s> unsigned Scratches = <NUM_LIT> ; for ( const SDep & Pred : SU -> Preds ) { if ( Pred . isCtrl ( ) ) continue ; Scratches ++


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else


<s> ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc


<s> TargetTransformInfo :: getAnalysisUsage (


<s> if ( ! StackSize ) return ; unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else


<s> int i ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( CONSTANT_P ( recog_data . operand [ i ] ) ) { enum attr_mode mode = get_attr_mode ( insn ) ; gcc_assert ( ! len ) ; if ( shortform && CONST_INT_P ( recog_data . operand [ i ] ) ) { HOST_WIDE_INT ival = INTVAL ( recog_data . operand [ i ] ) ; switch ( mode ) { case MODE_QI : len = <NUM_LIT> ; continue ; case MODE_HI : ival = trunc_int_for_mode ( ival , HImode ) ; break ; case MODE_SI : ival = trunc_int_for_mode ( ival , SImode ) ; break ; default : break ; } if ( IN_RANGE ( ival , - <NUM_LIT> , <NUM_LIT> ) ) { len =


<s> static void EmitIndirectGuardJmp ( const MCSubtargetInfo & STI , int I , MCInst Saved [ ] , MCStreamer & Out ) { assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm (


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction


<s> switch ( OldOpcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * LoopMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MF . insert ( It , LoopMBB ) ; MachineBasicBlock * DoneMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MF . insert ( It , DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; DoneMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopMBB ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; Register ReadAgainReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register LoReg = MI . getOperand ( <NUM_LIT> )


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> getCFIPersonalitySymbol ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI ) const { return Mang -> getSymbol ( GV )


<s> Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy


<s> const char * getPassName ( ) const override { return


<s> } } SDLoc DL ( Addr ) ; if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = Addr ; return true ; } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true


<s> DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB


<s> yaml :: MachineFunctionInfo * <ISA_LIT>TargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return new yaml :: <ISA_LIT>FunctionInfo ( * MFI


<s> unsigned OpNum = ( PFEntry >> <NUM_LIT> ) & <NUM_LIT> ; unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF )


<s> auto M = const_cast < Module * > ( DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ) ; auto GV = new GlobalVariable ( * M , T , true , GlobalVariable :: InternalLinkage , C , Twine ( DAG . getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( DAG . getMachineFunction ( ) . getFunctionNumber ( ) ) + <STR_LIT> + Twine ( AFI -> createPICLabelUId ( ) ) ) ; SDValue GA = DAG . getTargetGlobalAddress ( dyn_cast < GlobalValue > ( GV ) , dl , PtrVT ) ; return LowerGlobalAddress ( GA , DAG ) ; } if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlign ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlign ( ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt ; switch ( N -> getOpcode


<s> int i ; int count = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( x & ( ( unsigned short ) <NUM_LIT> << i ) ) count ++ ; return count


<s> unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MachineLocation DstML0 ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation DstML1 ( MachineLocation :: VirtualFP , Offset + <NUM_LIT> ) ; MachineLocation SrcML0 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; MachineLocation SrcML1 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; if ( ! STI . isLittle ( ) ) std :: swap ( SrcML0 ,


<s> TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) ,


<s> if ( ! insn_op -> predicate ( op [ arity ] , insn_op -> mode ) ) { error ( <STR_LIT> , arity + <NUM_LIT> , fndecl ) ; return const0_rtx ; } arity ++ ; } switch ( arity ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target ) ; break ; case <NUM_LIT> : if ( nonvoid ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( nonvoid ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( nonvoid ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( nonvoid ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( nonvoid ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( nonvoid ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable (


<s> assert ( isLegal ( MI , TII ) && <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) ) . add ( { MI -> getOperand ( <NUM_LIT> ) , MI -> getOperand ( SrcOpIdx ) } ) ; return


<s> I ++ ) { ( * I ) -> eraseFromParent ( ) ; } EraseSet . clear


<s> return ( __m64 ) __builtin_arm_wsubb ( ( __v8qi ) __m1 , (


<s> if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { llvm_unreachable ( <STR_LIT>


<s> if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( MBB , MI , DebugLoc ( ) , get ( <STR_LIT> ) , VirtReg ) . addImm ( <NUM_LIT> ) ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo


<s> unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * FR32 = & <STR_LIT> ; const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , FR32 , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else


<s> assert ( isBundle ( MCI ) ) ; int64_t Flags = MCI . getOperand ( <NUM_LIT> ) . getImm


<s> void <ISA_LIT>InstPrinter :: printMemExtend ( const MCInst * MI , unsigned OpNum , raw_ostream & O , char SrcRegKind , unsigned Width ) { bool SignExtend = MI -> getOperand ( OpNum ) . getImm ( ) ; bool DoShift = MI -> getOperand ( OpNum + <NUM_LIT> ) .


<s> Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext ( ) ,


<s> O << <STR_LIT> ; O . write_hex ( <STR_LIT> ( Val


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( )


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isAAPCS_ABI ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel


<s> if ( IsPS ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> :: ET_NULL ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( MBB , I , DL , TII -> get

( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; unsigned NumIterations = <NUM_LIT> ; while ( foldMachineFunction ( MF , MLI , MDT ) ) { modified = true ; NumIterations ++ ; assert ( NumIterations < <NUM_LIT> && <STR_LIT> ) ; } if ( modified )


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> } aa , bb ; aa . v = ( vector unsigned int ) ( a ) ; bb . v = ( vector unsigned int ) ( b ) ; if ( aa . i [ <NUM_LIT> ] > bb . i [ <NUM_LIT> ] )


<s> bool <ISA_LIT>LDBackend :: finalizeTargetSymbols ( ) { if ( config ( ) . codeGenType ( ) == LinkerConfig :: Object ) return true ; if ( m_psdabase ) m_psdabase -> setValue ( m_psdata -> addr ( ) ) ; ELFSegmentFactory :: const_iterator edata = elfSegmentTable ( ) . find ( llvm :: ELF :: PT_LOAD , llvm :: ELF :: PF_W , llvm :: ELF :: PF_X ) ; if ( elfSegmentTable ( ) . end ( ) != edata ) { if ( f_pEData != NULL && ResolveInfo :: ThreadLocal != f_pEData -> type ( ) ) { f_pEData -> setValue ( ( * edata ) -> vaddr ( ) + ( * edata ) -> filesz ( ) ) ; } if ( f_p_EData != NULL && ResolveInfo :: ThreadLocal != f_p_EData -> type ( ) ) { f_p_EData -> setValue ( ( * edata ) -> vaddr ( ) + ( *


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getSubArch ( ) == llvm :: Triple :: <ISA_LIT>SubArch_r6 ) { if ( TT . isMIPS32 ( ) ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ; } else if ( TT . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_cheri128 ) { CPU = <STR_LIT> ; } else if ( TT . getEnvironment ( ) == Triple :: CheriPurecap ) { CPU = <STR_LIT> ; } else { if ( TT . isMIPS32 ( ) ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ; } } return


<s> else if ( info . shift ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX <STR_LIT> , mnemonic , lane_count , element_char , UINTVAL ( info . value ) , shift_op , info . shift ) ; else snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_HEX , mnemonic , lane_count , element_char , UINTVAL ( info . value ) ) ; } else { mnemonic = info . insn == simd_immediate_info :: MVN ? <STR_LIT> : <STR_LIT> ; if ( info . shift ) snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , mnemonic , lane_count , element_char , UINTVAL ( info . value ) , <STR_LIT> , info . shift ) ; else snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , mnemonic , lane_count , element_char , UINTVAL ( info . value ) ) ; } return templ


<s> if ( ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State ,


<s> if ( Lane == <NUM_LIT> ) { unsigned Wt = Ws ; if ( ! Subtarget . useOddSPReg ( ) ) { Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } else { unsigned Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> )


<s> Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; if ( NewOp == <STR_LIT> ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ,


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM


<s> bool isu8Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ,


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry ( )


<s> Code16GCC = true ; if ( ! is16BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is32BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is64BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code64 ) ; } } else { Error ( L , <STR_LIT> + IDVal ) ; return


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { llvm_unreachable (


<s> if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; continue ; } assert ( TBB ) ; <STR_LIT> CC = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; assert ( FBB && <STR_LIT> ) ; if ( Dest != TBB && Dest != FBB ) { return true ; } if ( AllowModify ) { MachineBasicBlock :: iterator OldI = UnCondBrIter ; ++ OldI ; for ( ; OldI != I ; OldI ++ ) if ( OldI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( int ) CC ) break ; if ( OldI != I ) { OldI -> eraseFromParent (


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ]

|= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> if ( SrcVT == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) { return Op ; } return SDValue ( ) ; } assert ( SrcVT . getSimpleVT ( ) <= <STR_LIT> && SrcVT . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget -> is64Bit ( ) ) { return Op ; } DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) ->

CreateStackObject ( Size , Size , false ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { if ( HasPercentPrefix ) OS << <STR_LIT> ; OS << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { OS << formatHex ( Op . getImm


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( ! tryParseRelocExpression ( Operands ) ) return false ; if ( ( Parser . getTok ( ) . getKind ( ) == AsmToken :: Plus || Parser . getTok ( ) . getKind ( ) == AsmToken :: Minus ) && Parser . getLexer ( ) . peekTok ( ) . getKind ( ) == AsmToken :: Identifier ) { return true ; } MCExpr const * Expression ; if ( getParser ( ) . parseExpression ( Expression )