<s> MachineOperand FalseReg = MI -> getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( <STR_LIT> ( <STR_LIT> ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMI -> hasOptionalDef ( ) ) AddDefaultCC ( NewMI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert


<s> void WinEHStatePass :: addCXXStateStores ( Function & F , WinEHFuncInfo & FuncInfo ) { calculateWinCXXEHStateNumbers ( & F , FuncInfo ) ; addStateStoresToFunclet ( RegNode , FuncInfo , F , - <NUM_LIT> ) ; int RegNodeEscapeIndex = escapeRegNode (


<s> int Latency = <ISA_LIT>GenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; bool IsRegCR ; if ( TRI -> isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) ; } else { IsRegCR = <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode , * TII ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( std :: min ( CI . Offset , Paired . Offset ) ) . addImm ( CI . GLC ) . addImm ( CI . SLC ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; moveInstsAfter ( MIB


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateVectorIndex ( int Idx , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand >


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( Instruction * I ) { MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM , false ) ) return false ; return <ISA_LIT>FastEmitStore ( VT , I -> getOperand ( <NUM_LIT> )


<s> } else { auto C_P2HalfMemSize = MIRBuilder . buildConstant ( s32 , P2HalfMemSize ) ; auto Addr = MIRBuilder . buildPtrAdd ( PtrTy , BaseAddr , C_P2HalfMemSize ) ; auto Load_P2Half = MIRBuilder . buildLoad ( s32 , BaseAddr , * P2HalfMemOp ) ; auto Load_Rem = MIRBuilder . buildLoad ( s32 , Addr , * RemMemOp ) ; if ( Size == <NUM_LIT> ) MIRBuilder . buildMerge ( Val , { Load_P2Half , Load_Rem } ) ; else { auto Merge = MIRBuilder . buildMerge ( s64 , { Load_P2Half , Load_Rem } ) ; MIRBuilder . buildTrunc ( Val , Merge ) ; } } } MI . eraseFromParent ( ) ; break ; } case G_UITOFP : { Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src ) ; if ( SrcTy != s32 ) return false ; if ( DstTy != s32 && DstTy != s64 ) return false ; auto C_HiMask = MIRBuilder . buildConstant ( s32 , UINT32_C ( <NUM_LIT> ) ) ; auto Bitcast = MIRBuilder . buildMerge ( s64 , { Src , C_HiMask . getReg ( <NUM_LIT> ) } ) ; MachineInstrBuilder TwoP52FP = MIRBuilder . buildFConstant ( s64 , BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) ) ; if ( DstTy == s64 ) MIRBuilder . buildFSub (


<s> for ( unsigned i = <NUM_LIT> , e = MFI -> getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI -> getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI -> setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI -> getLocalFrameSize ( ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isObjectPreAllocated ( i ) && MFI -> getUseLocalStackAllocationBlock ( ) ) continue ; if ( MFI -> isDeadObjectIndex ( i ) ) continue ; AdjustStackOffset ( MFI , i , StackGrowsDown , Offset , MaxAlign ) ; } if ( ! TFI . targetHandlesStackFrameRounding ( ) ) { if ( MFI -> adjustsStack ( ) && TFI . hasReservedCallFrame ( Fn ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( Fn ) && MFI -> getObjectIndexEnd ( ) != <NUM_LIT> ) ) StackAlign = TFI . getStackAlignment ( ) ; else StackAlign = TFI .


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; bool CloseParen = false ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) O << <STR_LIT> << LowercaseString ( RI . get ( MO . getReg ( ) ) . AsmName ) ; else O << <STR_LIT> << MO . getReg ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB (


<s> void addRegCRRCOperands ( MCInst & Inst


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_PORTABLE_RUNTIME ) return


<s> assert ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; unsigned LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ; SDValue Lo = DAG . getCopyFromReg ( Chain , DL , LoVReg , <STR_LIT> ) ; SDValue Hi ; if ( VA . getLocReg ( ) == <STR_LIT> ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , <NUM_LIT> ,


<s> unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII ,


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; if ( ! LHSReg || !


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return make_unique < <ISA_LIT>Operand > ( Str


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return


<s> if ( CondCode != <STR_LIT> && ( ! OmitCC || ( CondCode != <STR_LIT> && CondCode != <STR_LIT> ) ) ) { StringRef SuffixStr = Name . substr ( Suffix ) ; Name = Name . slice ( <NUM_LIT> , Prefix ) ; Operands -> push_back ( <STR_LIT> ( Name , NameLoc ) ) ; SMLoc CondLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Prefix ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Suffix ) ; Operands -> push_back ( <STR_LIT> ( CondCode , CondLoc , SuffixLoc ) ) ; if ( ! SuffixStr . empty ( ) ) Operands -> push_back ( <STR_LIT> ( SuffixStr , SuffixLoc ) ) ; } else { Operands -> push_back ( <STR_LIT> ( Name , NameLoc ) ) ; } return Name


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> ) || ( Addr . getOpcode ( ) == <STR_LIT> ) ) { Base = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; Offset = Addr ; return true ; } } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( Addr . getOpcode ( )


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction &


<s> std :: vector < std :: string > max_gt ( Ax a , StepZIDS bs ) { return D ( <STR_LIT> , R ( a )


<s> void setVarArgsFrameIndex ( int Index


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl (


<s> unsigned <STR_LIT> ( Type * Ty , bool IsComplex ) const { unsigned NumVectorInstToHideOverhead =


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return Reserved


<s> return createELFStreamer ( Context , MAB , OS , Emitter


<s> void <ISA_LIT>ReduceCRLogicals :: initialize ( MachineFunction & MFParam ) { MF = & MFParam ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo (


<s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorELENMax )


<s> int i ; bool any_alg_usable_p = false ; * noalign = false ; * dynamic_check = - <NUM_LIT> ; if ( optimize_function_for_size_p ( cfun ) || ( optimize_insn_for_size_p ( ) && ( max_size < <NUM_LIT> || ( expected_size != - <NUM_LIT> && expected_size < <NUM_LIT> ) ) ) ) optimize_for_speed = false ; else optimize_for_speed = true ; cost = optimize_for_speed ? ix86_cost : & ix86_size_cost ; if ( memset ) algs = & cost -> memset [ TARGET_64BIT != <NUM_LIT> ] ; else algs = & cost -> memcpy [ TARGET_64BIT != <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < MAX_STRINGOP_ALGS ; i ++ ) { enum stringop_alg candidate = algs -> size [ i ] . alg ; bool usable = alg_usable_p ( candidate , memset , have_as ) ; any_alg_usable_p |= usable ; if ( candidate != libcall && candidate && usable ) max = algs -> size [ i ] . max ; } if ( ( ( max > <NUM_LIT> && ( unsigned HOST_WIDE_INT ) max >= max_size ) || max == - <NUM_LIT> ) && expected_size == - <NUM_LIT> ) expected_size = min_size / <NUM_LIT> + max_size / <NUM_LIT> ; if ( ix86_stringop_alg != no_stringop && alg_usable_p ( ix86_stringop_alg , memset , have_as ) ) return ix86_stringop_alg ; else if ( ! optimize_for_speed ) { * noalign = true ; if ( ! count || ( count & <NUM_LIT> ) || ( memset && ! zero_memset ) ) return alg_usable_p ( rep_prefix_1_byte , memset , have_as ) ? rep_prefix_1_byte : loop_1_byte ; else return alg_usable_p ( rep_prefix_4_byte , memset , have_as )


<s> dbgs ( ) << <STR_LIT> << PrintReg ( getBBSelectRegOut ( ) , TRI ) << <STR_LIT> ; dumpDepth ( depth ) ; if ( getSucc ( ) ) dbgs ( ) << <STR_LIT> << getSucc


<s> bool <ISA_LIT>RegisterInfo :: shouldRewriteCopySrc ( const TargetRegisterClass * DefRC , unsigned

DefSubReg , const TargetRegisterClass * SrcRC , unsigned SrcSubReg ) const {


<s> void printAS16Mem ( const MCInst * MI , int opNum , raw_ostream &


<s> for ( Idx = <NUM_LIT> ; Idx != array_lengthof ( LdStNInstInfo ) ; ++ Idx ) if ( LdStNInstInfo [ Idx ] . Opcode == Opcode ) return & LdStNInstInfo [ Idx ] ; return nullptr


<s> uint64_t TruncMask = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return false ; } return true


<s> rtx mmix_function_arg ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED , int incoming ) { if ( type == void_type_node ) return ( argsp -> regs < MMIX_MAX_ARGS_IN_REGS ) ? gen_rtx_REG ( mode ,

( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ) + argsp -> regs ) : NULL_RTX ;


<s> static SDValue LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG

. getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Src2Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned LaneImm = HasLane ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; unsigned NextOp = HasLane ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NextOp ) . getImm ( ) ; unsigned PredReg = MI -> getOperand ( ++ NextOp ) . getReg ( ) ; const TargetInstrDesc & TID1 = TII -> get ( MulOpc ) ; const TargetInstrDesc & TID2 = TII -> get ( AddSubOpc ) ; unsigned TmpReg = MRI -> createVirtualRegister ( TID1 . getRegClass ( <NUM_LIT> , TRI ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred ) . addReg ( PredReg ) ; MIB = BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TID2 ) . addReg ( DstReg , getDefRegState ( true ) | getDeadRegState ( DstDead ) ) ; if ( NegAcc ) { bool AccKill = MRI -> hasOneNonDBGUse ( AccReg ) ; MIB . addReg ( TmpReg , getKillRegState ( true ) ) . addReg ( AccReg , getKillRegState (


<s> void * _Unwind_GetLanguageSpecificData ( struct _Unwind_Context * context ) { return context ->


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( )


<s> if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return SDValue ( ) ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( N , <NUM_LIT> ) ; SDLoc DL ( N


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * CRImm = MCConstantExpr :: Create ( CRNum , getContext ( ) ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( CRImm , S , E ) ) ; return MatchOperand_Success


<s> rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( op0 == const0_rtx ) { addr = gen_rtx_MEM ( tmode , op1 ) ; } else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op0


<s> auto I = TargetRegisterInfo :: virtReg2Index ( VReg ) ; assert ( I < <ISA_LIT>Regs . size ( ) ) ; return <ISA_LIT>Regs [ I


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE -> getValue ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) .

getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;


<s> assert ( Section && <STR_LIT> ) ; if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) , <NUM_LIT> ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT>


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout &


<s> Arg = TruncInput . getOperand ( <NUM_LIT> ) ; continue ; } } break ; } int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode )


<s> rtx_insn * insn ; rtx_jump_insn * jump_insn ; shorten_branches ( get_insns ( ) ) ; something_changed = false ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( ( jump_insn = dyn_cast < rtx_jump_insn * > ( insn ) ) && get_attr_length ( jump_insn ) > <NUM_LIT> && ( any_condjump_p ( jump_insn ) || any_uncondjump_p ( jump_insn ) ) ) { rtx old_label , temp , saved_temp ; rtx_code_label * new_label ; rtx target ; rtx_insn * jump , * jump_sequence ; start_sequence ( ) ; saved_temp = gen_rtx_REG ( Pmode , AT_REGNUM ) ; temp = gen_rtx_REG ( Pmode , GP_REG_FIRST + <NUM_LIT> ) ; emit_move_insn ( saved_temp , temp ) ; old_label = JUMP_LABEL ( jump_insn ) ; target = gen_rtx_LABEL_REF ( Pmode , old_label ) ; mips16_load_branch_target ( temp , target ) ; jump = emit_jump_insn ( PMODE_INSN ( gen_indirect_jump_and_restore , ( temp , temp , saved_temp ) ) ) ; JUMP_LABEL ( jump )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return r


<s> MachineBasicBlock :: iterator Insert = SkipBB -> begin ( ) ; BuildMI ( * SkipBB , Insert , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) ; BuildMI ( * SkipBB , Insert , DL , TII -> get (


<s> int iq2000_reg_mode_ok_for_base_p ( rtx reg , machine_mode mode ATTRIBUTE_UNUSED


<s> { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , } ; static const uint16_t UCvtOpc [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; bool Is64Bit = SrcVT == <STR_LIT> ; if ( I -> getType ( ) -> isDoubleTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else return false ; MVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( DstVT ) ; Register ImplicitDefReg = createResultReg (


<s> OutStreamer . EmitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: Create ( GlobalEntryLabel , OutContext ) ; MCSymbol * TOCSymbol = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: CreateHa ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: CreateLo ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; MCSymbol * LocalEntryLabel = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: Create ( LocalEntryLabel , OutContext ) ; const MCExpr * LocalOffsetExp = MCBinaryExpr :: CreateSub ( LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer . getTargetStreamer ( ) ) ; if ( TS ) TS -> emitLocalEntry ( CurrentFnSym ,


<s> unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == ( unsigned ) Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ; } return Offset + <NUM_LIT>


<s> <ISA_LIT>Metadata . paramsNum = Func . getFunction ( ) . arg_size ( ) ; for ( int i = <NUM_LIT> ; i < numberOfLockRegister + <NUM_LIT> ; i ++ ) { if ( LockUnlockMismatchError && ( lockUnlock [ i ] . first ^ lockUnlock [ i ] . second ) ) { report_fatal_error (


<s> if ( TARGET_DEBUG ) fprintf ( stderr , <STR_LIT> , <NUM_LIT> * ( uses - <NUM_LIT> ) , uses , reg_names [ regno ] , IDENTIFIER_POINTER ( DECL_NAME ( current_function_decl ) ) , INSN_UID ( first_insn ) , INSN_UID ( last_insn ) ) ; if ( NOTE_P ( first_insn ) ) first_insn = next_nonnote_insn ( first_insn ) ; last_insn = next_nonnote_insn ( last_insn ) ; for ( insn = first_insn ; insn && insn != last_insn ; insn = NEXT_INSN ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { rtx pattern = single_set ( insn ) ; if ( pattern ) { rtx * p_mem ; int unsignedp = FALSE ; if ( GET_CODE ( SET_DEST ( pattern ) ) == MEM && GET_CODE ( SET_SRC ( pattern ) ) == MEM ) p_mem = ( rtx * ) <NUM_LIT> ; else if ( GET_CODE ( SET_DEST ( pattern ) ) == MEM ) p_mem = & SET_DEST ( pattern ) ; else if ( GET_CODE ( SET_SRC ( pattern ) ) == MEM ) p_mem = & SET_SRC ( pattern ) ; else if ( GET_CODE ( SET_SRC ( pattern ) ) == SIGN_EXTEND && GET_CODE ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ) == MEM ) p_mem = & XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ; else if ( GET_CODE ( SET_SRC ( pattern ) ) == ZERO_EXTEND && GET_CODE ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ) == MEM ) { p_mem = & XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ; unsignedp = TRUE ; } else p_mem = ( rtx


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget .


<s> static inline unsigned isImmPCRel ( uint64_t TSFlags ) { switch ( TSFlags & <STR_LIT> ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; auto opcode = MI -> getOpcode ( ) ; if ( Op . isReg ( ) ) { if ( ! ( ( isLoadInst ( opcode ) && OpNo == <NUM_LIT> ) || ( isStoreInst ( opcode ) && OpNo == <NUM_LIT> ) ) || Op . getReg ( ) != <STR_LIT> ) { printRegisterName ( Op . getReg ( ) , O ) ; } } else if ( Op . isImm ( ) ) { int64_t Value = Op . getImm ( ) ; bool IsShifted = false ; if ( PrintBytes == PrintAllAsBytes || ( PrintBytes == PrintCallAsBytes && opcode == <STR_LIT> ) ) { const MCInstrDesc & MID = MII . get ( opcode ) ; unsigned ImmShift = get<ISA_LIT>ImmediateShift ( MID . TSFlags ) ; Value <<= ImmShift ; IsShifted = true ; } if ( IsShifted && opcode == <STR_LIT> ) { O << format ( <STR_LIT> , Value ) ; } else { if ( ( isLoadInst ( opcode ) && OpNo == <NUM_LIT> ) || ( isStoreInst ( opcode ) && OpNo == <NUM_LIT> ) ) { const MCOperand & baseOp = MI -> getOperand ( OpNo - <NUM_LIT> ) ; if ( baseOp . getReg ( ) == <STR_LIT> ) { O << Value ; } else if ( Value != <NUM_LIT> ) { O << ( ( Value < <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) << std :: abs ( Value ) ; } } else


<s> SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; unsigned Align = Node -> getConstantOperandVal ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Node ) ; unsigned ArgSlotSizeInBytes = ( Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue VAListLoad = DAG . getLoad ( getPointerTy ( ) , DL , Chain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ; SDValue VAList = VAListLoad


<s> unsigned <ISA_LIT>TTIImpl :: getNumberOfRegisters ( bool Vec ) const { return <NUM_LIT>


<s> unsigned Align = TD -> getPreferredAlignmentLog ( GVar ) ; printVisibility ( name , GVar -> getVisibility ( ) ) ; SwitchToSection ( TAI -> SectionForGlobal ( GVar ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) ) { if ( ! GVar -> isThreadLocal ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> isWeakForLinker ( ) ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } else { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: CommonLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; case GlobalValue :: GhostLinkage : cerr << <STR_LIT> ; abort (


<s> if ( IN_RANGE ( cycles , <NUM_LIT> , <NUM_LIT> ) ) { loop_count = ( ( cycles - <NUM_LIT> ) / <NUM_LIT> ) + <NUM_LIT> ; cycles_used = ( ( loop_count - <NUM_LIT> ) * <NUM_LIT> ) + <NUM_LIT> ; emit_insn ( gen_delay_cycles_4 ( gen_int_mode ( loop_count , SImode ) , avr_mem_clobber ( ) ) ) ; cycles -= cycles_used ; } if ( IN_RANGE ( cycles , <NUM_LIT> , <NUM_LIT> ) ) { loop_count = ( ( cycles - <NUM_LIT> ) / <NUM_LIT> ) + <NUM_LIT> ; if ( loop_count > <NUM_LIT> ) loop_count = <NUM_LIT> ; cycles_used = ( ( loop_count - <NUM_LIT> ) * <NUM_LIT> ) + <NUM_LIT> ; emit_insn ( gen_delay_cycles_3 ( gen_int_mode ( loop_count , SImode ) , avr_mem_clobber ( ) ) ) ; cycles -= cycles_used ; } if ( IN_RANGE ( cycles , <NUM_LIT> , <NUM_LIT> ) ) { loop_count = ( ( cycles - <NUM_LIT> ) / <NUM_LIT> ) + <NUM_LIT> ; if ( loop_count > <NUM_LIT> ) loop_count = <NUM_LIT> ; cycles_used = ( ( loop_count - <NUM_LIT> ) * <NUM_LIT> ) + <NUM_LIT> ; emit_insn ( gen_delay_cycles_2 ( gen_int_mode ( loop_count , HImode ) , avr_mem_clobber ( ) ) ) ; cycles -= cycles_used ; } if ( IN_RANGE ( cycles , <NUM_LIT> ,


<s> const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: sdst ) ; BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( CI . I ) ; CI . I -> eraseFromParent (


<s> return decodeBDXAddr20Operand ( Inst , Field , <STR_LIT>


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op


<s> set_conv_libfunc ( sext_optab , mode , DDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , <STR_LIT> ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , <STR_LIT> ) ; } } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; if ( TARGET_PPC_GPOPT ) set_optab_libfunc ( sqrt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( eq_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ne_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , mode


<s> static const MCPhysReg ScratchRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT>


<s> return isInt < <NUM_LIT> > ( MFI . getMaxCallFrameSize ( ) ) &&


<s> RelocationType = MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT ; break ; case <STR_LIT> : RelocationType = MCSymbolRefExpr :: VK_TPREL ; break ; } ME = MCSymbolRefExpr :: create ( Symbol , RelocationType , MC ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , MC ) , MC ) ; ME = <ISA_LIT>MCExpr :: create ( ME , MC ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * ME , MustExtend ) ; return MCOperand :: createExpr ( ME


<s> for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = & <STR_LIT> ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin (


<s> <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; uint64_t Offset = MFI -> allocateKernArg ( LocVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return true


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<s> bool NextIsHash = Parser . getLexer ( ) . peekTok ( ) . is ( AsmToken :: Hash ) ; if ( ! Parser . getTok ( ) . getString ( ) . equals_insensitive ( <STR_LIT> ) || ! ( NextIsVL || NextIsHash ) ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; if ( NextIsVL ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; return false


<s> return new <ISA_LIT>LoadStoreReplace ( )


<s> const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getSubtarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs ) ; ++ NumCPEs ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } DEBUG ( BB -> dump (


<s> BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else if ( MFI -> hasVarSizedObjects ( ) ) { if ( CSSize ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = addLeaRegOffset ( BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; MBB . insert ( MBBI , MI ) ; } else BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else { if ( NumBytes ) emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; int MaxTCDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; int Offset = <NUM_LIT> ; assert ( MaxTCDelta <= <NUM_LIT> && <STR_LIT> ) ; Offset = StackAdj - MaxTCDelta ; assert ( Offset >= <NUM_LIT> && <STR_LIT> ) ; if ( Offset ) { Offset += mergeSPUpdates ( MBB , MBBI , StackPtr , true ) ; emitSPUpdate ( MBB , MBBI , StackPtr , Offset , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) ) ; else if ( RetOpcode == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII . get

( <STR_LIT> ) , JumpTarget . getReg ( ) ) ;


<s> <ISA_LIT>Type * SpirvType = getOrCreate<ISA_LIT>Type ( Type , MIRBuilder , AccessQual , EmitIR ) ; assign<ISA_LIT>TypeToVReg ( SpirvType , VReg , MIRBuilder . getMF ( ) ) ; return SpirvType


<s> if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ; APInt Mask = C -> getAPIntValue ( ) . trunc ( EltTy . getSizeInBits ( ) ) ; Dup = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Mask . zextOrTrunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , UnpkOp , Dup ) ; return DAG . getNode ( Opc , DL , N -> getValueType ( <NUM_LIT> ) , And ) ; } if ( ! EnableCombineMGatherIntrinsics ) return SDValue ( ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned RegType = ( RegNo >> <NUM_LIT> ) & <NUM_LIT> ; unsigned RegOffset = RegNo >> <NUM_LIT> ; OS << <STR_LIT> ; switch ( RegSpace ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : switch ( RegType ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OS << <STR_LIT> ; break ; case <STR_LIT> : OS << <STR_LIT> ; break ; case <STR_LIT> : OS << <STR_LIT> ; break ; case <STR_LIT>


<s> return ( __m64 ) __builtin_ia32_psrld ( ( __v2si ) __m , (


<s> return value == <NUM_LIT> ; case 'K' : return ( unsigned HOST_WIDE_INT ) ( value + <NUM_LIT> ) < <NUM_LIT> ; case 'L' : return ( ( value & <NUM_LIT> ) == <NUM_LIT> && ( ( value ) >> <NUM_LIT> == - <NUM_LIT> || value >> <NUM_LIT> == <NUM_LIT> ) ) ; case 'M' : return zap_mask ( value ) ; case 'N' : return ( unsigned HOST_WIDE_INT ) ( ~ value )


<s> unsigned ImmOp = Inst . getNumOperands ( ) - <NUM_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( ImmOp ) . isImm ( ) && ( ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Inst . getNumOperands


<s> EVT OVT = Op . getValueType ( ) ; MVT INTTY = <STR_LIT> ; if ( OVT == <STR_LIT> ) { INTTY = <STR_LIT> ; } else if ( OVT == <STR_LIT> ) { INTTY = <STR_LIT> ; } SDValue LHS = DAG . getSExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , INTTY ) ; SDValue RHS = DAG . getSExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , INTTY ) ; LHS = DAG . getNode ( <STR_LIT> , DL , INTTY


<s> Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDLoc ( Node ) ) ; SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * Subtarget -> getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = getPointerTy ( ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF


<s> unsigned int i = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_lookup_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_lookup_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_std_type ( SImode , qualifier_lane_pair_index


<s> SDValue Zero = BuildSplatI ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; SDValue Neg16 = BuildSplatI ( - <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DAG , dl ) ; SDValue RHSSwap = BuildIntrinsicOp ( <STR_LIT> , RHS , Neg16 , DAG , dl ) ; LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; RHSSwap = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHSSwap ) ; SDValue LoProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHS , DAG , dl , <STR_LIT> ) ; SDValue HiProd = BuildIntrinsicOp ( <STR_LIT> , LHS , RHSSwap , Zero , DAG , dl , <STR_LIT> ) ; HiProd = BuildIntrinsicOp ( <STR_LIT> , HiProd , Neg16 , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoProd , HiProd ) ; } else if ( Op . getValueType ( ) == <STR_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; bool isLittleEndian = Subtarget . isLittleEndian (


<s> SDValue XformMskToBitPosU4Imm ( uint16_t Imm


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , N0 ) ; SDValue Ops [ ] = { N0 , Neg , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Neg . getNode ( ) , <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSE41 ( ) ) { SDLoc DL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Src ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> unsigned opc1 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned cop = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; if ( Inst . getOpcode (


<s> } if ( RC == & <STR_LIT> && EnableGPRToVecSpills ) InflateGPRC ++ ; } if ( RC == & <STR_LIT> ) return & <STR_LIT> ; else if ( RC == & <STR_LIT> ) return & <STR_LIT> ; else if ( RC == & <STR_LIT> && Subtarget . hasP8Vector ( ) ) return & <STR_LIT> ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC


<s> MCCodeEmitter * llvm :: create<ISA_LIT>BEMCCodeEmitter ( const MCInstrInfo


<s> return insn1 -> compare_with ( insn2 ) <


<s> static void pdp11_option_override ( void ) { if (


<s> rtx par = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; rtx set = XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; rtx mem = SET_DEST ( set ) ; gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } return insn


<s> initialize<ISA_LIT>BranchExpansionPass ( * PassRegistry :: getPassRegistry


<s> bool <ISA_LIT>AsmPrinter :: printAsmRegInClass ( const MachineOperand & MO , const TargetRegisterClass * RC , bool isVector , raw_ostream & O ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; const <ISA_LIT>RegisterInfo * RI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo (


<s> Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) , Result ) ; } if ( isGlobalStubReference ( OpFlags ) ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result , DAG . getConstant ( Offset , getPointerTy ( ) ) ) ; return


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeFP ( const ConstantFP * CFP , MVT VT ) { const APFloat Val = CFP -> getValueAPF ( ) ; bool is64bit = VT == <STR_LIT> ; if ( TLI . isFPImmLegal ( Val , VT ) ) { int Imm ; unsigned Opc ; if ( is64bit ) { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } else { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } Register DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( Imm ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP )


<s> return TargetTriple . getEnvironment ( ) ==


<s> auto ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { } ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; if ( OpFlags & <STR_LIT> ) { ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MRI . setRegClass ( ADRP . getReg (


<s> createUnpackShuffleMask ( VT , Unpckh , false , false ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckl ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - DefaultSafety ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - DefaultSafety ; case <STR_LIT> : return <NUM_LIT> - DefaultSafety


<s> void printSymbolHi ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { printS16ImmOperand ( MI , OpNo , O ) ; } else { if ( Subtarget . isDarwin (


<s> if ( arg . aggregate_type_p ( ) ) return true ; HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size < <NUM_LIT>


<s> if ( ! MsgName . empty ( ) && isValidMsgOp ( MsgId , OpId , STI ) && isValidMsgStream ( MsgId , OpId , StreamId , STI ) ) { O << <STR_LIT> << MsgName ; if ( msgRequiresOp ( MsgId ) ) { O << <STR_LIT> << getMsgOpName ( MsgId , OpId ) ; if ( msgSupportsStream ( MsgId , OpId ) ) { O << <STR_LIT> << StreamId ; } } O << ')' ; } else if ( encodeMsg ( MsgId , OpId , StreamId ) == Imm16 ) { O << <STR_LIT> << MsgId << <STR_LIT> << OpId <<


<s> case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; default : break ; } if ( Dim <= <NUM_LIT> ) { unsigned ReqdSize = getReqdWorkGroupSize ( * Kernel , Dim ) ; if ( ReqdSize != std :: numeric_limits < unsigned > :: max ( ) ) MinSize = MaxSize = ReqdSize ; } } } if ( ! MaxSize ) return false ; if ( IdQuery ) MinSize = <NUM_LIT> ; else ++ MaxSize ; MDBuilder MDB ( I -> getContext ( ) ) ; MDNode * MaxWorkGroupSizeRange = MDB . createRange ( APInt ( <NUM_LIT> , MinSize ) , APInt ( <NUM_LIT> , MaxSize ) ) ; I -> setMetadata ( LLVMContext ::


<s> unsigned int abi_id = <NUM_LIT> ; rtx pat = PATTERN (


<s> assert ( m_pRelocator != NULL ) ; return


<s> DebugLoc dl = N . getDebugLoc ( ) ; if ( SelectAddressRegReg ( N , Disp , Base , DAG ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm & <NUM_LIT> ) == <NUM_LIT> ) { Disp = DAG . getTargetConstant ( ( ( int ) imm & <NUM_LIT> ) >> <NUM_LIT> , <STR_LIT> ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm &


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } const MCSymbol * Symbol ; unsigned Offset = <NUM_LIT> ; switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = Mang . getSymbol ( MO . getGlobal ( ) ) ; Offset = MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset = MO . getOffset ( ) ; break ; default : llvm_unreachable (


<s> unsigned CCReg = MI -> getOperand ( OpNo


<s> for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { MachineBasicBlock * MB = & * MBB ; PreviousRegSeq . clear ( ) ; PreviousRegSeqByReg . clear ( ) ; PreviousRegSeqByUndefCount . clear ( ) ; for ( MachineBasicBlock :: iterator MII = MB -> begin ( ) , MIIE = MB -> end ( ) ; MII != MIIE ; ++ MII ) { MachineInstr & MI = * MII ; if ( MI . getOpcode ( ) != <STR_LIT> ) { if ( TII -> get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ) { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: def_instr_iterator It = MRI -> def_instr_begin ( Reg ) , E = MRI -> def_instr_end ( ) ; It != E ; ++ It ) { RemoveMI ( & ( * It ) ) ; } } continue ; } RegSeqInfo R<ISA_LIT> ( * MRI , & MI ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! areAllUsesSwizzeable ( Reg ) ) continue ; DEBUG ( { dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; } ) ; RegSeqInfo CandidateR<ISA_LIT> ; std :: vector < std :: pair < unsigned , unsigned >> RemapChan ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( tryMergeUsingCommonSlot ( R<ISA_LIT> , CandidateR<ISA_LIT> , RemapChan ) ) { RemoveMI ( CandidateR<ISA_LIT> . Instr ) ; MII = RebuildVector ( & R<ISA_LIT> , & CandidateR<ISA_LIT> , RemapChan ) ; trackR<ISA_LIT> ( R<ISA_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; RemapChan . clear ( ) ; if ( tryMergeUsingFreeSlot ( R<ISA_LIT> , CandidateR<ISA_LIT> , RemapChan ) ) { RemoveMI ( CandidateR<ISA_LIT> . Instr ) ; MII = RebuildVector ( & R<ISA_LIT> , & CandidateR<ISA_LIT> , RemapChan ) ; trackR<ISA_LIT> ( R<ISA_LIT>


<s> LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printMBBReference ( * MB ) << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; RegisterSubReg UseR ( SO ) ; if ( ! Register :: isVirtualRegister ( UseR . Reg ) ) goto Bottomize ; if ( ! Cells . has ( UseR


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo .


<s> SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 < N >


<s> static bool isReachableFromPHI ( PHINode * Phi , BinaryOperator * BO ) { if ( ! Phi -> hasOneUse ( ) ) return false ; Instruction * U = cast < Instruction > ( * Phi -> user_begin (


<s> int <ISA_LIT>AsmParser :: getATReg (


<s> return ( ( Src << Shift ) & Mask ) | (


<s> if ( pass_by_reference_p ) type = build_pointer_type ( type ) ; size = int_size_in_bytes ( type ) ; rsize = ( ( size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) * UNITS_PER_WORD ; if ( TYPE_ALIGN ( type ) > PARM_BOUNDARY ) { gcc_assert ( STACK_BOUNDARY == PARM_BOUNDARY * <NUM_LIT> ) ; tmp = build2 ( BIT_AND_EXPR , sizetype , fold_convert ( sizetype , unshare_expr ( args ) ) , size_int ( PARM_BOUNDARY / <NUM_LIT> ) ) ; tmp = build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( args ) , tmp ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; } tmp = fold_build_pointer_plus_hwi ( unshare_expr ( args ) , rsize ) ; tmp = build2 ( TRUTH_AND_EXPR , boolean_type_node , build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( skip ) ) , build2 ( LE_EXPR , boolean_type_node , unshare_expr ( args ) , unshare_expr ( skip ) ) ) ; tmp = build3 ( COND_EXPR , ptr_type_node , tmp , build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( skip ) , size_int ( STACK_POINTER_OFFSET ) ) , unshare_expr ( args ) ) ; if ( BYTES_BIG_ENDIAN && rsize > size ) tmp = fold_build_pointer_plus_hwi ( tmp , rsize - size ) ; gimplify_assign ( addr , tmp , pre_p ) ; if ( BYTES_BIG_ENDIAN && rsize > size ) tmp = fold_build_pointer_plus_hwi ( addr , size ) ; else tmp = fold_build_pointer_plus_hwi ( addr , rsize ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( pass_by_reference_p ) addr = build_va_arg_indirect_ref ( addr ) ; return build_va_arg_indirect_ref ( addr


<s> const auto & FGR64RegClass = TRI -> getRegClass ( <STR_LIT> ) ; unsigned Fc2 = RegInfo . createVirtualRegister ( FGR64RegClass ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , Fc2 ) . addImm ( <NUM_LIT> ) . addReg ( Fc ) . addImm ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( Fc2


<s> bool <ISA_LIT>MCInstrInfo :: isPrefix ( MCInstrInfo const & MCII , MCInst const & MCI ) { return ( <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI )


<s> SDLoc dl ( Op ) ; const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S


<s> return D ( <STR_LIT> , MemARPSJ ( a , asj ) , R ( b ) , <STR_LIT> , MemARPSI ( a , asi


<s> assert ( Op . getValueType ( ) == <STR_LIT> && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Zero , Zero ,


<s> const char * RegName = <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; if ( ! Subtarget -> isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ! GV -> isStrongDefinitionForLinker ( ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage


<s> if ( type != <NUM_LIT> ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_pad_arg_upward ( mode


<s> MCInstLowering . Lower ( MI , TmpInst ) ; TmpInst . setOpcode ( <STR_LIT> ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; } else { OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> )


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RTB = DAG . getNode ( <STR_LIT> , dl , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RTB , RTB . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewInt ) ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getOperand ( N -> isStrictFPOpcode ( ) ? <NUM_LIT> : <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return ; Results . push_back ( LowerFP_TO_INT ( SDValue ( N , <NUM_LIT> ) , DAG , dl ) ) ; return ; case <STR_LIT> : { if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return ; SDValue Lowered = LowerTRUNCATEVector ( SDValue ( N , <NUM_LIT> ) , DAG ) ; if ( Lowered ) Results . push_back ( Lowered ) ; return ; } case <STR_LIT> : return ; case <STR_LIT> : SDValue Lowered = LowerFP_EXTEND ( SDValue ( N , <NUM_LIT> )


<s> if ( ! <ISA_LIT>SelectAddress ( LI -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; const <ISA_LIT>InstrInfo & XII = ( const <ISA_LIT>InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI ,


<s> return frameTriviallyRequiresSP ( MFI ) || MFI . isFrameAddressTaken ( ) || MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) -> hasStackRealignment ( MF ) || MF . getTarget ( ) . Options


<s> bool disablePostRAScheduler ( ) const { return DisablePostRAScheduler


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo


<s> bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; if ( ConstSplatVal && ( Subtarget -> hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget -> hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; } } bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; if ( ! IsLoad && Subtarget -> hasInt256 ( ) && ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; if ( ! IsLoad ) return SDValue ( ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( Subtarget -> hasVLX ( ) && ScalarSize == <NUM_LIT> ) ) return DAG . getNode (


<s> size_type edges_size ( ) const { return


<s> using namespace <STR_LIT> ; unsigned TTmpMin = ( isGFX9 ( ) || isGFX10

( ) ) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN ;


<s> rtx addend = NULL_RTX ; rtx reg_addend = NULL_RTX ; rtx const_addend = NULL_RTX ; rtx result = NULL_RTX ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == Pmode && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) { if ( base_term_p && MEM_P ( orig_x ) ) return orig_x ; rtx x2 = XVECEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; x = gen_rtx_PLUS ( Pmode , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , x2 ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_GOTPCREL || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) && ( MEM_P ( orig_x ) || XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PCREL ) ) { x = XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_MODE ( orig_x ) != GET_MODE ( x ) && MEM_P ( orig_x ) ) { x = lowpart_subreg ( GET_MODE ( orig_x ) , x , GET_MODE ( x ) ) ; if ( x == NULL_RTX ) return orig_x ; } return


<s> static void cris_file_start ( void ) { targetm . asm_file_start_app_off = ! (


<s> if ( TARGET_32BIT ) return ( TARGET_THUMB2 && ! speed_p ) ? <NUM_LIT> : <NUM_LIT> ; else return ( optimize > <NUM_LIT> ) ?


<s> Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ; return


<s> if ( LastInst -> isUnconditionalBranch ( ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } AnalyzeCondBr ( LastInst , LastOpc , TBB , Cond , I ) ; return false ; } if ( ++ I != REnd && isUnpredicatedTerminator ( * I ) ) return true ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastInst -> isUnconditionalBranch ( ) ) { if ( ! AllowModify ) { return true ; } TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back (


<s> FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) if ( MEM_P ( * iter ) && ( reg_mentioned_p ( stack_pointer_rtx , *

iter ) || reg_mentioned_p ( frame_pointer_rtx , * iter ) ) ) {


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures (


<s> static int getLoadStoreMultipleOpcode ( int Opcode ) { switch ( Opcode ) { case <STR_LIT> : ++ NumLDMGened ; return <STR_LIT> ; case <STR_LIT> : ++ NumSTMGened ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; return <STR_LIT> ; case <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: getIndexedAddressParts ( SDNode * Op , SDValue & Base , SDValue & Offset , SelectionDAG & DAG ) const { if ( Op -> getOpcode ( ) != <STR_LIT>


<s> AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ; LoadInst * LI = new LoadInst ( StructType , ArgInParam


<s> void emitARM64WinCFISaveLRPair ( unsigned Reg ,


<s> if ( AVR_HAVE_EIJMP_EICALL && xop [ <NUM_LIT> ] == all_regs_rtx [ <NUM_LIT> ] ) { sub_5 = xop [ <NUM_LIT> ] ; } if ( ! AVR_HAVE_EIJMP_EICALL && PLUS == GET_CODE ( xop [ <NUM_LIT> ] ) && LABEL_REF == GET_CODE ( XEXP ( xop [ <NUM_LIT> ] , <NUM_LIT> ) ) && rtx_equal_p ( xop [ <NUM_LIT> ] , XEXP ( XEXP ( xop [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) && xop [ <NUM_LIT> ] == const0_rtx ) { sub_5 = XEXP ( xop [ <NUM_LIT>


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_DATA ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REL_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REL_24 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_H ; case


<s> MBB . push_back ( Waitcnt ) ; return ; } MachineBasicBlock :: iterator It = MBB . end ( ) ; MachineInstr * MI = & * ( -- It ) ; if ( MI -> isBranch ( ) ) { MBB . insert ( It , Waitcnt ) ; } else


<s> if ( Cond . getOpcode ( ) != <STR_LIT> ) return Op ; return createCMovFP ( DAG , Cond , Op . getOperand ( <NUM_LIT> ) ,

Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) ) ;


<s> N -> getMask ( M ) ; return :: isUNPCKHMask ( M , N -> getValueType ( <NUM_LIT> ) ,


<s> SmallVector < const SUnit * , <NUM_LIT> > Worklist ( Set . begin ( ) , Set . end ( ) ) ; while ( ! Worklist . empty ( ) ) { auto SU = Worklist . pop_back_val ( ) ; assert ( ! SU -> isBoundaryNode ( ) ) ; for ( const auto & P : SU -> Preds ) { if ( ! P . getSUnit ( ) -> isBoundaryNode ( ) && ! isScheduled ( P . getSUnit ( ) ) && Set . insert ( P . getSUnit ( ) ) . second ) Worklist . push_back ( P . getSUnit ( ) ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << SchedSU -> NodeNum << <STR_LIT> << Priority << <STR_LIT> ) ; const auto SetEnd = Set . end ( ) ; for ( auto & C : RQ ) { if ( Set . find ( C . SU ) != SetEnd ) { C . Priority = Priority ; DEBUG ( dbgs ( ) << <STR_LIT> << C . SU -> NodeNum << ')'


<s> InstructionCost <ISA_LIT>TTIImpl :: getCFInstrCost ( unsigned Opcode , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT>


<s> virtual const Tile64Subtarget * getSubtargetImpl (


<s> return ( __m256 ) __builtin_ia32_rndscaleps_256_mask ( ( __v8sf ) __A , __imm , (

__v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( a >= - ( DFtype ) ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) return ( SItype ) ( a + ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - ( - ( ( SItype ) ( (

( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ;


<s> assert ( MI && <STR_LIT> ) ; int SaveOffset = Offset ; return is<ISA_LIT>FrameOffsetLegal ( * MI , SaveOffset )


<s> bool isFGRAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_FGR && RegIdx . Index


<s> else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LR_REGNO ; crtl -> uses_pic_offset_table = <NUM_LIT> ; if ( MACHOPIC_INDIRECT && crtl -> uses_pic_offset_table ) caller_addr_regno = <NUM_LIT> ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , gen_rtx_REG ( Pmode , caller_addr_regno


<s> bool demand_p ( enum demand_type type )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> if ( Conversion . XORValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . XORValue , DL , <STR_LIT> ) ) ; if ( Conversion . AddValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . AddValue , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . Bit , DL , <STR_LIT> ) ) ; if ( Conversion . Bit != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL ,


<s> if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) return CurDAG -> getTargetInsertSubreg ( <STR_LIT> , DL , VT , getUNDEF ( DL , <STR_LIT> ) , N ) ; if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) return CurDAG -> getTargetExtractSubreg ( <STR_LIT> , DL , VT , N ) ; assert ( N . getValueType ( ) == VT


<s> static DecodeStatus DecodeRegisterClassByID ( llvm :: MCInst & Inst , unsigned RegNo , unsigned RegID , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , RegID , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler ::


<NUM_LIT> ) | ( RangeLen - <NUM_LIT> ) ) ;


<s> } else { if ( global ) { fprintf ( file , <STR_LIT> ) ; assemble_name ( file , name ) ; fprintf ( file , <STR_LIT> ) ; } assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; ASM_OUTPUT_SKIP ( file , size


<s> } MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT> ) ; int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) , <STR_LIT> ) . addImm ( Amount ) ; } MBB . insert ( I


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineFrameInfo * MFrmInf = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = std :: prev ( MBB . end ( ) ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * MFuncInf = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; bool FP = hasFP ( MF ) ; int FrameSize = MFrmInf -> getStackSize ( ) ; if ( FrameSize ) { if ( FP ) { int FPSpillOffset = MFrmInf -> getObjectOffset ( MFuncInf -> getFPSpillSlot ( ) ) + FrameSize ; FPSpillOffset += Subtarget . hasSPBias ( ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FPSpillOffset ) ; } if ( MFuncInf -> getUsesLR ( ) ) { int LRSpillOffset = MFrmInf -> getObjectOffset ( MFuncInf -> getLRSpillSlot ( ) ) + FrameSize ; LRSpillOffset += Subtarget . hasSPBias (


<s> Value * <ISA_LIT>IREmitter :: visitVMOVRRD (


<s> int HalfIdx1 , HalfIdx2 ; SmallVector < int , <NUM_LIT> > HalfMask ( Mask . size ( ) / <NUM_LIT> ) ; if ( ! getHalfShuffleMask ( Mask , HalfMask , HalfIdx1 , HalfIdx2 ) || ( HalfIdx1 % <NUM_LIT> == <NUM_LIT> ) || ( HalfIdx2 % <NUM_LIT>


<s> switch ( Kind ) { case VK_<ISA_LIT>_LO : return Value & <NUM_LIT> ; case VK_<ISA_LIT>_HI : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHER : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHERA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHEST : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHESTA


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getStackSize ( ) && needsFP


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int Offset = MFI -> getObjectOffset ( FI ) + MFI -> getOffsetAdjustment ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( FI < <NUM_LIT> ) StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; Offset += StackSize - TFI . getOffsetOfLocalArea ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) Offset -= TFI .


<s> return ( int64x2_t ) __builtin_neon_vld1v2di ( ( const __builtin_neon_di *


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 (


<s> Register <ISA_LIT>RegisterInfo :: getBaseRegister ( ) const { return <STR_LIT>


<s> bool <ISA_LIT>ImmToReg :: processImmOperand ( MachineFunction & Func ) { for ( auto & MBB : Func ) { for ( auto & MI : MBB ) { collectImmUse ( & MI ) ; } } xformImmUse ( Func


<s> return __builtin_mve_vmulhq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCoprocNum ( unsigned CopVal , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CoprocNum ) ; Op -> Cop . Val = CopVal ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op


<s> <ISA_LIT>Gfx940CacheControl ( const GCNSubtarget & ST ) : <ISA_LIT>Gfx90ACacheControl (


<s> Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( Src0 ) == LLT


<s> unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; Type * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy -> getScalarSizeInBits ( ) ) return false ; unsigned NumDstEls = DstTyL . first * DstTyL . second . getVectorNumElements ( ) ; unsigned NumSrcEls = SrcTyL . first * SrcTyL . second


<s> __builtin_ia32_scatterpfqpd ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , (

long long const * ) addr , scale , hint ) ;


<s> SDLoc dl ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDNode * Result ; int32_t Val = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; if ( Val == - <NUM_LIT> ) { SDNode * IntRegTFR = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDNode * Pd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IntRegTFR , <NUM_LIT> ) ) ; SDNode * NotPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Pd , <NUM_LIT> ) ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Pd , <NUM_LIT> ) , SDValue ( NotPd , <NUM_LIT> ) ) ; ReplaceUses ( N , Result ) ; return Result ; } } return SelectCode ( N


<s> } ScheduleDAGMILive :: schedule ( ) ; Regions [ RegionIdx ] = std :: make_pair ( RegionBegin , RegionEnd ) ; if ( ! LIS ) return ; GCNMaxOccupancySchedStrategy & S = ( GCNMaxOccupancySchedStrategy & ) * SchedImpl ; auto PressureAfter = getRealRegPressure ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; PressureAfter . print ( dbgs ( ) ) ) ; if ( PressureAfter . getSGPRNum ( ) <= S . SGPRCriticalLimit && PressureAfter . getVGPRNum ( ) <= S . VGPRCriticalLimit ) { Pressure [ RegionIdx ] = PressureAfter ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } unsigned WavesAfter = getMaxWaves ( PressureAfter . getSGPRNum ( ) , PressureAfter . getVGPRNum ( ) , MF ) ; unsigned WavesBefore = getMaxWaves ( PressureBefore . getSGPRNum ( ) , PressureBefore . getVGPRNum ( ) , MF ) ; DEBUG ( dbgs ( ) << <STR_LIT> << WavesBefore << <STR_LIT> << WavesAfter << <STR_LIT> ) ; unsigned NewOccupancy = std :: max ( WavesAfter , WavesBefore ) ; if ( NewOccupancy < MinOccupancy ) { MinOccupancy = NewOccupancy ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> ExtendedInsts = false ; HWMultMode = NoHWMult ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget


<s> if ( MI -> isDebugInstr ( ) || MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) return ; auto RegOpcode = OutMI . getOpcode ( ) ; auto StackOpcode = regInstructionToStackInstruction ( RegOpcode ) ; OutMI . setOpcode ( StackOpcode ) ; for ( auto I = OutMI . getNumOperands ( ) ; I ; -- I ) { auto & MO = OutMI . getOperand ( I - <NUM_LIT> ) ; if ( MO . isReg ( ) ) { OutMI . erase ( & MO


<s> MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF )


<s> uint64_t Amount = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> )


<s> unsigned Start = Desc . getNumOperands ( ) ; unsigned NumVariadicDefs = <NUM_LIT> ; if ( Desc . variadicOpsAreDefs ( ) ) { NumVariadicDefs = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Start = <NUM_LIT> ; } bool NeedsComma = Desc . getNumOperands ( ) > <NUM_LIT> && ! Desc . variadicOpsAreDefs ( ) ; for ( auto I = Start , E = MI -> getNumOperands ( ) ; I < E ; ++ I ) { if ( MI -> getOpcode ( ) == <STR_LIT> && I - Start == NumVariadicDefs ) { ++ I ; continue ; } if ( NeedsComma ) OS << <STR_LIT> ; printOperand ( MI , I , OS , I - Start < NumVariadicDefs ) ; NeedsComma = true ; } } printAnnotation ( OS , Annot ) ; if ( CommentStream ) { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowCounter ) + ':' ) ; ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , true ) ) ; break ; case <STR_LIT> : case <STR_LIT> : ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , false ) ) ; break ; case <STR_LIT> : case <STR_LIT> : ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , false ) ) ; EHPadStack . push_back ( EHPadStackCounter ++ ) ; LastSeenEHInst = TRY ; break ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { ControlFlowStack . pop_back ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; LastSeenEHInst = END_TRY ; } break ; case <STR_LIT> : case <STR_LIT> : if ( EHPadStack . empty (


<s> __builtin_ia32_pmovqb256mem_mask ( ( __v16qi * ) __P , ( __v4di )


<s> SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , Offset ) ; SDValue NewStore = DAG . getTruncStore ( Store -> getChain ( ) , SL , Val , Ptr , SrcValue . getWithOffset ( i * EltSize ) , MemEltVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , MinAlign ( BaseAlign , i * EltSize ) ) ; Chains . push_back ( NewStore


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( ! Subtarget -> hasFP64 ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op


<s> emit_insn ( gen_cmpdf_lt_insn ( op0 , op1 ) ) ; break ; case GT : emit_insn ( gen_cmpdf_gt_insn ( op0 , op1 ) ) ; break ; case NE : case EQ : emit_insn ( gen_cmpdf_eq_insn ( op0 , op1 ) ) ; break ; default : gcc_unreachable ( ) ; } } else if ( GET_MODE ( v850_compare_op0 ) == SFmode ) { switch ( cond ) { case LE : emit_insn ( gen_cmpsf_le_insn ( op0 , op1 ) ) ; break ; case GE : emit_insn ( gen_cmpsf_ge_insn ( op0 , op1


<s> warnIfNoMacro ( IDLoc ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( OffsetImmOp . isImm ( ) && <STR_LIT> ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned SrcReg = SrcRegOp . getReg ( ) ; int64_t OffsetValue = OffsetImmOp . getImm ( ) ; unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; bool LoadedOffsetInAT = false ; if ( ! isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) || ! isInt < <NUM_LIT> > ( OffsetValue ) ) { LoadedOffsetInAT = true ; if ( loadImmediate ( OffsetValue , ATReg , <STR_LIT> , ! ABI . ArePtrs64bit ( ) , IDLoc , Instructions ) ) return true ; if ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> ) createAddu ( ATReg , ATReg , SrcReg , ABI . ArePtrs64bit ( ) , Instructions ) ; } unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg ; unsigned SecondLbuDstReg = LoadedOffsetInAT ? ATReg : DstReg ; unsigned LbuSrcReg = LoadedOffsetInAT ? ATReg : SrcReg ; int64_t FirstLbuOffset = <NUM_LIT> , SecondLbuOffset = <NUM_LIT> ; if ( isLittle ( ) ) { FirstLbuOffset = LoadedOffsetInAT ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; SecondLbuOffset = LoadedOffsetInAT ? <NUM_LIT> : OffsetValue ; } else { FirstLbuOffset = LoadedOffsetInAT ? <NUM_LIT> : OffsetValue ; SecondLbuOffset = LoadedOffsetInAT ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; } unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( FirstLbuDstReg ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( LbuSrcReg ) ) ; TmpInst . addOperand ( MCOperand :: createImm ( FirstLbuOffset ) ) ; Instructions . push_back ( TmpInst ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT>


getBuildVector ( <STR_LIT> , DL , VPermMask ) , V1 ) ;


<s> if ( <STR_LIT> ( GO ) && ! GO -> hasSection ( ) &&

Kind . isReadOnly ( ) ) return ProgmemDataSection ;


<s> -- I ; if ( ! ( isCondBranch ( I ) || isUncondBranch ( I ) ) ) return <NUM_LIT> ; DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( I -> dump ( ) ) ; I -> eraseFromParent ( ) ; return <NUM_LIT>


<s> } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; } if ( WavefrontSizeLog2 == <NUM_LIT> ) WavefrontSizeLog2 = <NUM_LIT> ; HasFminFmaxLegacy = getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; HasSMulHi = getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ; TargetID . setTargetIDFromFeaturesString ( FS ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TargetID . getXnackSetting ( ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TargetID .


<s> return ( ( vec_uchar16 ) ( si_cntb ( ( qword )


<s> return ( int32x4_t ) __builtin_neon_vqdmlslv4hi ( __a ,


<s> EmitRuntimeMetadata ( getRuntimeMDYAMLString ( Features , M )


<s> NumOpsAdded = <NUM_LIT> ; return true ; } switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } if ( Opcode == <STR_LIT> ) { NumOpsAdded = <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT>


<s> SE = & getAnalysis < ScalarEvolution > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; MadeChange |= runOnLoop ( L ) ; } return MadeChange


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties (


<s> if ( V . getValueSizeInBits ( ) == <NUM_LIT> ) return V ; assert ( V . getValueSizeInBits ( ) == <NUM_LIT> ) ; SDValue SubRegIdx = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , V , SubRegIdx ) , <NUM_LIT> ) ; return SubVal


<s> AddDefaultPred ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( QPR ? <STR_LIT> : <STR_LIT> ) , Out ) . addReg ( Reg ) . addImm ( Lane ) ) ; return Out


<s> Inst . addOperand ( MCOperand :: createImm ( EM ) ) ; } else if ( auto * CE = dyn_cast < Function > ( C ) ) { Register FuncReg = MAI -> getFuncReg ( CE -> getName ( ) . str ( ) ) ; assert ( FuncReg . isValid ( ) ) ; Inst . addOperand ( MCOperand ::


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ||

MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ;


<s> return ArgInfo . ImplicitBufferPtr . getRegister (


<s> bool <ISA_LIT>ElimCompare :: convertToBRCT ( MachineInstr & MI , MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned Opcode = MI . getOpcode ( ) ; unsigned BRCT ; if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else return false ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get


<s> } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = V . getConstantOperandVal ( <NUM_LIT> ) ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( ( ( Mask >> i ) & <NUM_LIT> ) == <NUM_LIT> ) Bits [ i ] = ( * LHSBits ) [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return std :: make_pair ( Interesting , & Bits ) ; } break ; case <STR_LIT> : { const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; const auto & RHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; bool AllDisjoint = true ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( LHSBits [ i ] . isZero ( ) ) Bits [ i ] = RHSBits [ i ] ; else if ( RHSBits [ i ] . isZero ( ) ) Bits [ i ] = LHSBits [ i ] ; else { AllDisjoint = false ; break ; } if ( ! AllDisjoint ) break ; return std :: make_pair ( Interesting = true , & Bits ) ; } case <STR_LIT> : { if ( V . getValueType ( ) != <STR_LIT> || V . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) break ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; const unsigned NumOperandBits = <NUM_LIT> ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumOperandBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperandBits ; ++ i ) Bits [ i ] = ( * LHSBits ) [ i ] ; for ( unsigned i = NumOperandBits ; i < NumBits ; ++ i ) Bits [ i ] = ValueBit ( ValueBit