<s> return ( int64x2_t ) __builtin_aarch64_sqaddv2di


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { return new <ISA_LIT>AsmBackend ( T , MRI , TT , CPU


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > (


<s> HOST_WIDE_INT offset ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? <NUM_LIT> : - info -> total_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { offset = info -> push_p ? <NUM_LIT> : - info -> total_size ; if ( FRAME_GROWS_DOWNWARD ) offset += info -> fixed_size + info -> vars_size + info -> parm_size ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = FRAME_GROWS_DOWNWARD ? info -> fixed_size + info -> vars_size + info -> parm_size : <NUM_LIT> ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = info -> total_size ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? info -> total_size : <NUM_LIT> ; else if ( from == RS6000_PIC_OFFSET_TABLE_REGNUM ) offset = <NUM_LIT> ; else gcc_unreachable ( ) ; return offset


<s> unsigned const ParseFieldOffset = <NUM_LIT> ; ParseField Field = HMI . isPacketEnd ( ) ?

ParseField :: end : ParseField :: last0 ;


<s> bool <ISA_LIT>TargetObjectFile :: shouldPutJumpTableInFunctionSection ( bool UsesLabelDifference , const Function &


<s> MachineInstr * OrSaveExec = BuildMI ( MBB , Start , DL , TII -> get ( <STR_LIT> ) , SaveReg ) . addReg ( CopyReg ) ; MachineBasicBlock * DestBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: iterator ElsePt ( MI ) ; if ( ExecModified ) { MachineInstr * And = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( <STR_LIT> ) . addReg ( SaveReg ) ; if ( LIS ) LIS -> InsertMachineInstrInMaps ( * And ) ; } MachineInstr * Xor = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( DstReg ) ; MachineInstr * Branch = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; if ( ! LIS ) { MI . eraseFromParent ( ) ; return ; } LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent ( ) ; LIS -> InsertMachineInstrInMaps (


<s> SDValue CmpLHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue CmpRHS = Cmp . getOperand ( <NUM_LIT> ) ; if ( ! CmpLHS . hasOneUse ( ) ) return SDValue ( ) ; auto * CmpRHSC = dyn_cast < ConstantSDNode > ( CmpRHS ) ; if ( ! CmpRHSC || CmpRHSC -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; const unsigned Opc = CmpLHS . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue OpRHS = CmpLHS . getOperand ( <NUM_LIT> ) ; auto * OpRHSC = dyn_cast < ConstantSDNode > ( OpRHS ) ; if ( ! OpRHSC ) return SDValue ( ) ; APInt Addend = OpRHSC -> getAPIntValue ( ) ; if ( Opc == <STR_LIT> ) Addend = - Addend ; if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == - <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == - <NUM_LIT> ) CC = <STR_LIT> ; else return SDValue


<s> void <ISA_LIT>TargetELFStreamer :: emitTextAttribute ( unsigned Attribute , StringRef


<s> else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , getRelocation ( MI , MO ) , true ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isCPI ( ) ) emitConstPoolAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , getRelocation ( MI , MO ) ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB (


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv4si (


<s> case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) { switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = true ; } else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) { switch ( IntrinsicID ) { case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) CompareOpc = <NUM_LIT> ; else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CompareOpc =


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return combineZERO_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineSIGN_EXTEND ( N , DCI ) ; case <STR_LIT> : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineMERGE ( N , DCI ) ; case <STR_LIT> : return combineSTORE ( N , DCI ) ; case <STR_LIT> : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case <STR_LIT> : return combineJOIN_DWORDS ( N , DCI ) ; case <STR_LIT> : return combineFP_ROUND ( N , DCI ) ; case <STR_LIT> : return combineBSWAP ( N , DCI ) ; case <STR_LIT> : return combineBR_CCMASK ( N ,


<s> int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = <NUM_LIT> ; if ( type && TREE_ADDRESSABLE ( type ) ) return - <NUM_LIT> ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != <NUM_LIT> ) return - <NUM_LIT> ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= <NUM_LIT> && ( slotno & <NUM_LIT> ) != <NUM_LIT> ) slotno ++ , * ppadding = <NUM_LIT> ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - <NUM_LIT> ; regno = SPARC_FP_ARG_FIRST + slotno * <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - <NUM_LIT> ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) == UNION_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - <NUM_LIT> ; regno = regbase + slotno ; } else { int intregs_p = <NUM_LIT> , fpregs_p = <NUM_LIT> , packed_p = <NUM_LIT> ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) fpregs_p = <NUM_LIT> ; else scan_record_type ( type , & intregs_p , & fpregs_p , & packed_p ) ; if ( packed_p || ! named ) fpregs_p = <NUM_LIT> , intregs_p


<s> Expected < uint64_t > FunctionSym :: getSectionOffset ( const HSACodeObject * CodeObject , const object :: ELF64LEObjectFile :: Elf_Shdr * Text ) const { assert ( Text ) ; auto AddressOr = getAddress ( CodeObject , Text ) ; if ( ! AddressOr ) return AddressOr . takeError ( ) ; return * AddressOr - Text


<s> unsigned MaskTZ = CountTrailingZeros_64 ( Mask ) ; unsigned AMShiftAmt = MaskTZ ; if ( AMShiftAmt <= <NUM_LIT> || AMShiftAmt > <NUM_LIT> ) return true ; if ( CountTrailingOnes_64 ( Mask >> MaskTZ ) + MaskTZ + MaskLZ != <NUM_LIT> ) return true ; MaskLZ -= ( <NUM_LIT> - X . getValueSizeInBits ( ) ) + ShiftAmt ; bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getValueSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getValueSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( X , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; EVT VT = N . getValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , X . getDebugLoc ( ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } DebugLoc DL = N . getDebugLoc ( ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X


<s> bool <ISA_LIT>BlockPlacement :: processPostOrderLoops ( MachineLoop * ML ) { bool Changed = false ; for ( auto * InnerML : * ML ) Changed |= processPostOrderLoops ( InnerML ) ; return Changed | fixBackwardsWLS


<s> int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT ) , Result ) ; } return


<s> if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo (


<s> return __builtin_aarch64_frecpsv2df ( __a ,


<s> return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> ,

FK_Data_4 ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ;


<s> if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return false ; Src = In


<s> case BUILT_IN_SQRT : if ( out_mode == DFmode && out_n == <NUM_LIT> && in_mode == DFmode && in_n == <NUM_LIT> ) return MIPS_GET_BUILTIN ( msa_fsqrt_d ) ; break ; case BUILT_IN_SQRTF : if ( out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode &&


<s> if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue Op = lowerShuffleWithSHUFPD ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Op ; if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2

, Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PointerSize ( computePointerSize ( TT ) ) , UsesLogicalAddressing ( TT . is<ISA_LIT>Logical ( ) ) , UsesVulkanEnv ( TT . isVulkanEnvironment ( ) ) , UsesOpenCLEnv ( TT . isOpenCLEnvironment ( ) ) , Target<ISA_LIT>Version ( <NUM_LIT> ) , TargetOpenCLVersion ( <NUM_LIT> ) , TargetVulkanVersion ( computeTargetVulkanVersion ( TT ) ) , OpenCLFullProfile ( computeOpenCLFullProfile ( TT ) ) , OpenCLImageSupport ( computeOpenCLImageSupport ( TT ) ) , InstrInfo ( ) , FrameLowering ( initSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) { initAvailableExtensions ( TT ) ; initAvailableExtInstSets ( TT ) ; initAvailableCapabilities ( TT ) ; GR = std :: make_unique < <ISA_LIT>GlobalRegistry > ( PointerSize ) ; CallLoweringInfo = std :: make_unique < <ISA_LIT>CallLowering > ( TLInfo , GR . get ( ) ) ; Legalizer = std :: make_unique < <ISA_LIT>LegalizerInfo > ( * this ) ; RegBankInfo = std :: make_unique < <ISA_LIT>RegisterBankInfo > ( ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( TM , * this , * RegBankInfo . get


<s> Op -> Expr . Val = Val ; Op -> Expr . CRVal = EvaluateCRExpr ( Val ) ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64 =


<s> else if ( findMaskedBFI ( N -> getOperand ( <NUM_LIT> ) , BFI , ExistingMask , Extended ) ) PossExtraMask = N -> getOperand ( <NUM_LIT> ) ; else return SDValue ( ) ; if ( PossExtraMask . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( PossExtraMask . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; uint64_t ExtraMask = PossExtraMask -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ExtraMask & ExistingMask ) return SDValue ( ) ; SDValue OldBFIVal = BFI . getOperand ( <NUM_LIT> ) ; SDValue NewBFIVal = BFI . getOperand ( <NUM_LIT> ) ; if ( Extended ) { assert ( VT == <STR_LIT> && BFI . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; OldBFIVal = DAG . getNode ( <STR_LIT> , DL , VT , OldBFIVal ) ; NewBFIVal = DAG . getNode ( <STR_LIT> , DL , VT , NewBFIVal ) ; } if ( PossExtraMask . getOperand ( <NUM_LIT> ) != OldBFIVal ) return SDValue ( ) ; BFI = DAG . getNode ( <STR_LIT> , DL , VT , OldBFIVal , NewBFIVal , BFI . getOperand ( <NUM_LIT> ) , BFI . getOperand ( <NUM_LIT> ) ) ; if ( ( ExtraMask | ExistingMask ) == ( - <NUM_LIT> >> ( <NUM_LIT> - VT . getSizeInBits ( ) ) ) ) return BFI ; return DAG . getNode ( <STR_LIT> , DL , VT , BFI , DAG . getConstant ( ExtraMask | ExistingMask , VT


<s> if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeSubeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAddSub = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAddSub = nullptr ; if ( ( AddeSubeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeSubeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAddSub = & AddeSubeOp1 ; else HiAddSub = & AddeSubeOp0 ; if ( AddcSubcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcSubcOp0 ; LowAddSub = & AddcSubcOp1 ; } if ( AddcSubcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcSubcOp1 ; LowAddSub = & AddcSubcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; if ( AddcSubcNode == HiAddSub -> getNode ( ) || AddcSubcNode -> isPredecessorOf ( HiAddSub -> getNode ( ) ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; if ( Subtarget -> hasV6Ops ( ) && Subtarget -> hasDSP ( ) && Subtarget -> useMulOps ( ) && FinalOpc == <STR_LIT> && ! AddeSubeNode -> hasAnyUseOfValue ( <NUM_LIT> ) && LowAddSub -> getNode ( ) -> getOpcode ( ) == <STR_LIT> && static_cast < ConstantSDNode * > ( LowAddSub -> getNode ( ) ) -> getZExtValue ( ) == <NUM_LIT> ) { Ops . push_back ( * HiAddSub ) ; if ( AddcSubcNode -> getOpcode ( ) == <STR_LIT> ) { FinalOpc = <STR_LIT> ; } else { FinalOpc = <STR_LIT> ; } SDValue NewNode = DAG . getNode ( FinalOpc , SDLoc ( AddcSubcNode ) , <STR_LIT> , Ops ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeSubeNode , <NUM_LIT> ) , NewNode ) ; return SDValue ( AddeSubeNode , <NUM_LIT> ) ; } else if ( AddcSubcNode -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; Ops . push_back ( * LowAddSub ) ; Ops . push_back ( * HiAddSub ) ; SDValue MLALNode = DAG . getNode ( FinalOpc , SDLoc ( AddcSubcNode ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue HiMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddeSubeNode , <NUM_LIT> ) , HiMLALResult ) ; SDValue LoMLALResult ( MLALNode . getNode ( ) , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( AddcSubcNode , <NUM_LIT> ) , LoMLALResult ) ; return SDValue ( AddeSubeNode


<s> uint32_t getISAExtensionValue ( ) { return ( uint32_t


<s> fputs ( <STR_LIT> , stream ) ; assemble_name ( stream , funname ) ; fputs ( <STR_LIT> , stream ) ; ASM_OUTPUT_LABEL ( stream , funname ) ; fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , funname ) ; fprintf ( stream , <STR_LIT> , alpha_procedure_type == PT_STACK ? <STR_LIT> : alpha_procedure_type == PT_REGISTER ? <STR_LIT> : <STR_LIT> ) ; if ( func


<s> if ( TREE_CODE ( arg0 ) == VECTOR_CST ) { tree inner_type = TREE_TYPE ( rtype ) ; unsigned i ; tree_vector_builder n_elts ( rtype , VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < VECTOR_CST_NELTS ( arg0 ) ; ++ i ) { unsigned HOST_WIDE_INT val = TREE_INT_CST_LOW ( VECTOR_CST_ELT ( arg0 , i ) ) ; n_elts . quick_push ( build_int_cst ( inner_type , val << <NUM_LIT> ) ) ; } return n_elts . build ( ) ; } break ; case SPARC_BUILTIN_FMUL8X16 : case SPARC_BUILTIN_FMUL8X16AU : case SPARC_BUILTIN_FMUL8X16AL : arg0 = args [ <NUM_LIT> ] ; arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree inner_type = TREE_TYPE ( rtype ) ; tree_vector_builder n_elts ( rtype , VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; sparc_handle_vis_mul8x16 ( & n_elts , code , inner_type , arg0 , arg1 ) ; return n_elts . build ( ) ; } break ; case SPARC_BUILTIN_FPMERGE : arg0 = args [ <NUM_LIT> ] ; arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree_vector_builder n_elts ( rtype , <NUM_LIT> * VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; unsigned i ; for ( i = <NUM_LIT> ; i < VECTOR_CST_NELTS ( arg0 ) ; ++ i ) { n_elts . quick_push ( VECTOR_CST_ELT ( arg0 , i ) ) ; n_elts . quick_push ( VECTOR_CST_ELT ( arg1 , i ) ) ; } return n_elts . build ( ) ; } break ; case SPARC_BUILTIN_PDIST : case SPARC_BUILTIN_PDISTN : arg0 = args [ <NUM_LIT> ] ; arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( code == SPARC_BUILTIN_PDIST ) { arg2 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg2 ) ; } else arg2


<s> return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( ( isJumpTableBranchOpcode ( SecondLastOpc ) || isIndirectBranchOpcode ( SecondLastOpc ) ) && isUncondBranchOpcode ( LastOpc ) ) { I =


<s> for ( size_t i = <NUM_LIT> ; i < pNum ; ++

i ) createEntry ( <NUM_LIT> , m_SectionData ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp , ArrayRef < Value * > Args ) { InstructionCost CostFactor = vectorCostAdjustmentFactor ( Instruction :: ShuffleVector , Tp


<s> addPass ( create<ISA_LIT>VSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass


<s> void <ISA_LIT>JITInfo :: relocate ( void * Function , MachineRelocation * MR , unsigned NumRelocs , unsigned char * GOTBase ) { for ( unsigned i = <NUM_LIT> ; i != NumRelocs ; ++ i , ++ MR ) { void * RelocPos = ( char * ) Function + MR -> getMachineCodeOffset ( ) ; intptr_t ResultPtr = ( intptr_t ) MR -> getResultPointer ( ) ; switch ( ( <STR_LIT> ) MR -> getRelocationType ( ) ) { case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> - MR -> getConstantVal ( ) ; * ( ( unsigned * ) RelocPos ) += ( unsigned ) ResultPtr ; break ; } case <STR_LIT>


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI


<s> MIB -> setDesc ( Desc ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; assert ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && MIB -> getOperand ( <NUM_LIT>


<s> unsigned long long d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> (


<s> bool <ISA_LIT>TargetLowering :: shouldSplitVectorElementType ( EVT


<s> rtx_code_label * label , * end_label ; end_label = gen_label_rtx ( ) ; cmp_result = gen_rtx_EQ ( VOIDmode , begin , end ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; inc = gen_reg_rtx ( Pmode ) ; emit_insn ( PMODE_INSN ( gen_rdhwr_synci_step , ( inc ) ) ) ; cmp_result = gen_rtx_EQ ( VOIDmode , inc , const0_rtx ) ; emit_jump_insn ( gen_condjump ( cmp_result , end_label ) ) ; mask = mips_force_unary ( Pmode , NEG , inc ) ; begin = mips_force_binary ( Pmode , AND , begin , mask ) ; length = mips_force_binary ( Pmode , MINUS , end , begin ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; emit_insn ( gen_synci ( begin


<s> AttributeList Attrs = CalleeFn -> getAttributes ( ) ; if ( Attrs . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: ReturnsTwice ) ) return true ; return


<s> MachineInstr & MI = * MBBI ; MachineBasicBlock * MBB = MI . getParent ( ) ; const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI . isPosition ( ) ) { if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Invisible ; return outliner :: InstrType :: Illegal ; } if ( MI . isInlineAsm ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isTerminator ( ) && ! MBB -> succ_empty ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isReturn ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; for ( const auto & MO : MI . operands ( ) ) if ( MO . isMBB ( ) || MO . isBlockAddress ( ) || MO . isCPI ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isMetaInstruction ( ) ) return outliner :: InstrType ::


<s> static void free_label_state ( struct unw_labeled_state * ls ) { labeled_state_alloced -- ; if ( PTR_IN ( emergency_labeled_state , ls ) ) atomic_free ( & emergency_labeled_state_free , emergency_labeled_state - ls ) ; else free ( ls


<s> ( strict ? GPR_P ( REGNO ( X ) ) : GPR_AP_OR_PSEUDO_P ( REGNO ( X ) ) ) if ( RTX_OK_FOR_BASE_P ( x ) ) return true ; if ( RTX_FRAME_OFFSET_P ( x ) ) return true ; if ( LEGITIMATE_OFFSET_ADDRESS_P ( mode , x ) ) return true ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> && GET_CODE ( x ) == PLUS && XEXP ( x , <NUM_LIT> ) == stack_pointer_rtx && ! ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= - <NUM_LIT> * <NUM_LIT> && INTVAL (

XEXP ( x , <NUM_LIT> ) ) <= <NUM_LIT> * <NUM_LIT> ) return true ;


<s> return Opc == <STR_LIT> || isT1i32Load ( Opc ) || isT2i32Load (


<s> bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < AllCRLogicalOps . size ( ) ;


<s> restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <NUM_LIT> ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( get ( <STR_LIT> ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; return


<s> switch ( OldOpcode ) { case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable (


<s> static bool isVTBLMask ( ArrayRef < int > M , EVT VT ) { return VT == <STR_LIT> && M . size (


<s> if ( Kind != InlineAsm :: Kind_RegUse && Kind != InlineAsm :: Kind_RegDef && Kind != InlineAsm :: Kind_RegDefEarlyClobber ) continue ; unsigned RC ; bool HasRC = InlineAsm :: hasRegClassConstraint ( Flag , RC ) ; if ( ( ! IsTiedToChangedOp && ( ! HasRC || RC != <STR_LIT> ) ) || NumRegs != <NUM_LIT> ) continue ; assert ( ( i + <NUM_LIT> < NumOps ) && <STR_LIT> ) ; SDValue V0 = N -> getOperand ( i + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( i + <NUM_LIT> ) ; unsigned Reg0 = cast < RegisterSDNode > ( V0 ) -> getReg ( ) ; unsigned Reg1 = cast < RegisterSDNode > ( V1 ) -> getReg ( ) ; SDValue PairedReg ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( Kind == InlineAsm :: Kind_RegDef || Kind == InlineAsm :: Kind_RegDefEarlyClobber ) { unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; GU = T1 . getNode ( ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; unsigned GPVR = MRI . createVirtualRegister


<s> static bool s390_match_ccmode_set ( rtx set , enum machine_mode req_mode ) { enum machine_mode set_mode ; gcc_assert ( GET_CODE ( set ) == SET ) ; if ( GET_CODE ( SET_DEST ( set ) ) != REG || ! CC_REGNO_P ( REGNO ( SET_DEST ( set ) ) ) ) return <NUM_LIT> ; set_mode = GET_MODE ( SET_DEST ( set ) ) ; switch ( set_mode ) { case CCSmode : case CCSRmode : case CCUmode : case CCURmode : case CCLmode : case CCL1mode : case CCL2mode : case CCL3mode : case CCT1mode : case CCT2mode


<s> RegisterTargetMachine < <ISA_LIT>32TargetMachine > A ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > B (


<s> unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 <<


<s> MemOpQueueEntry ( int o , int p , MachineBasicBlock :: iterator i ) : Offset ( o ) , Position ( p ) , MBBI ( i ) ,


<s> auto MOTW = llvm :: make_unique < <ISA_LIT>WinCOFFObjectWriter >


<s> if ( instr && ( isCondBranch ( instr ) ||


<s> unsigned RsReg = RsRegOp . getReg ( ) ; unsigned RtReg ; int64_t ImmValue ; const MCOperand & RtOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( RtOp . isReg ( ) || RtOp . isImm ( ) ) && <STR_LIT> ) ; if ( RtOp . isReg ( ) ) RtReg = RtOp . getReg ( ) ; else ImmValue = RtOp . getImm ( ) ; unsigned DivOp ; unsigned ZeroReg ; unsigned SubOp ; if ( Is<ISA_LIT>64 ) { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } else { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } bool UseTraps = useTraps ( ) ; unsigned Opcode = Inst . getOpcode ( ) ; bool isDiv = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isRem = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( RtOp . isImm ( ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( ImmValue == <NUM_LIT> ) { if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; else TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } if ( isRem && ( ImmValue == <NUM_LIT> || ( Signed && ( ImmValue == - <NUM_LIT> ) ) ) ) { TOut . emitRRR ( <STR_LIT> , RdReg , ZeroReg , ZeroReg , IDLoc , STI ) ; return false ; } else if ( isDiv && ImmValue == <NUM_LIT> ) { TOut . emitRRR ( <STR_LIT> , RdReg , RsReg , <STR_LIT> , IDLoc , STI ) ; return false ; } else if ( isDiv && Signed && ImmValue == - <NUM_LIT> ) { TOut . emitRRR ( SubOp , RdReg , ZeroReg , RsReg , IDLoc , STI ) ; return false ; } else { if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , Inst . getLoc ( ) , Out , STI ) ) return true ; TOut . emitRR ( DivOp , RsReg , ATReg , IDLoc , STI ) ; TOut . emitR ( isDiv ? <STR_LIT> : <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } return true ; } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; return false ; } TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num , SMLoc


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdiv8qi ( ( int8x8_t


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ ,

__artificial__ ) ) _readgsbase_u64 ( void ) {


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext


<s> assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( VecTy -> getScalarType ( ) ) == <NUM_LIT> ; if ( Factor <= TLI -> getMaxSupportedInterleaveFactor ( ) && ! EltIs64Bits ) { unsigned NumElts = VecTy -> getVectorNumElements ( ) ; Type * SubVecTy = VectorType :: get ( VecTy ->

getScalarType ( ) , NumElts / Factor ) ;


<s> return __aarch64_vset_lane_any ( * __src


<s> void <ISA_LIT>InstPrinter :: printU4ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O


<s> if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant (


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Extract128BitVector ( Op0 , <NUM_LIT> , DAG , DL ) ; SDValue RHS = Extract128BitVector ( Op0 , NumElems / <NUM_LIT> , DAG , DL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LowerVectorCTPOPInRegLUT ( LHS , DL ,

Subtarget , DAG ) , LowerVectorCTPOPInRegLUT ( RHS , DL , Subtarget , DAG ) ) ;


<s> bool arm_output_addr_const_extra ( FILE * fp , rtx x ) { if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) return arm_emit_tls_decoration ( fp , x ) ; else if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_LABEL ) { char label [ <NUM_LIT> ] ; int labelno = INTVAL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; ASM_GENERATE_INTERNAL_LABEL ( label , <STR_LIT> , labelno ) ; assemble_name_raw ( fp , label ) ; return TRUE


<s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( TM . getDataLayout ( ) ) ; emitHeader ( M ,


<s> } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , RI -> getDwarfRegNum ( Reg , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg , StackSize , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode ::


<s> <ISA_LIT>CustomBehaviour :: <ISA_LIT>CustomBehaviour ( const MCSubtargetInfo & STI , const mca :: SourceMgr & SrcMgr , const MCInstrInfo & MCII

) : CustomBehaviour ( STI , SrcMgr , MCII ) {


<s> static unsigned getAbsoluteReloc ( unsigned Kind ) { switch ( Kind


<s> if ( ElementWidth == <NUM_LIT> && Shift ) return Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; Inst . addOperand ( MCOperand :: createImm ( Shift ) ) ; return Success


<s> SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL ,


<s> REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; CurOp += <STR_LIT> ; REX |= isREXExtendedReg ( MI , CurOp ++ ) << <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : REX |= isREXExtendedReg ( MI , MemOperand + <STR_LIT> ) << <NUM_LIT> ; REX |= isREXExtendedReg ( MI , MemOperand +


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false ,


<s> return true ; case 'w' : Reg = getWRegFromXReg ( Reg ) ; break ; case 'x' : Reg = getXRegFromWReg


<s> MachineInstr * FixupBWInstPass :: tryReplaceLoad ( unsigned New32BitOpcode , MachineInstr * MI ) const { unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( New32BitOpcode ) , NewDestReg ) ; unsigned NumArgs = MI ->


<s> } if ( ! Found ) { std :: string name = PAN :: getUdataSectionName ( UDATASections_ . size ( ) ) ; Found = get<ISA_LIT>DataSection ( name . c_str ( ) , UDATA ) ; } Found -> Items . push_back ( GV ) ; Found -> setSize ( Found -> getSize ( )


<s> if ( const auto * BKey = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) return BKey -> getZExtValue ( ) ; return false ; } const StringRef Key = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; assert ( Key . equals_lower ( <STR_LIT> ) || Key . equals_lower ( <STR_LIT> ) ) ; return Key . equals_lower


<s> int <ISA_LIT>SchedStrategy :: pressureChange ( const SUnit * SU , bool isBotUp ) { PressureDiff & PD = DAG -> getPressureDiff ( SU ) ; for ( auto & P : PD ) { if ( ! P . isValid ( ) ) continue ; if ( HighPressureSets [ P . getPSet ( ) ] ) { return ( isBotUp ? P . getUnitInc ( ) : - P .


<s> MachineInstr * <ISA_LIT>CFGStructurizer :: insertInstrBefore ( MachineBasicBlock :: iterator I , int NewOpcode ) { MachineInstr * OldMI = & (


<s> bool <ISA_LIT>RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { llvm_unreachable (


<s> SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; SDValue TEB = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; Chain = TLSArray . getValue ( <NUM_LIT> ) ; SDValue TLSIndexHi = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; SDValue TLSIndexLo = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndexHi ) ; SDValue TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , TLSIndexLo ) ; TLSIndex = DAG . getLoad ( <STR_LIT> , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; Chain = TLSIndex . getValue ( <NUM_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; Chain = TLS . getValue ( <NUM_LIT> ) ; const GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue Addr = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TLS , TGAHi , DAG . getTargetConstant ( <NUM_LIT> , DL ,


<s> bool isVTypeI10 ( ) const { if ( Kind == KindTy :: Immediate


<s> assert ( StartIdx == StartIdx2 && <STR_LIT> ) ; } unsigned ScratchIdx = StartIdx , e = MI . getNumOperands ( ) ; while ( ScratchIdx < e && ! ( MI . getOperand ( ScratchIdx ) . isReg ( ) && MI . getOperand ( ScratchIdx ) . isDef ( ) && MI . getOperand ( ScratchIdx ) . isImplicit ( ) && MI . getOperand ( ScratchIdx ) . isEarlyClobber ( ) ) ) ++ ScratchIdx ; assert ( ScratchIdx != e && <STR_LIT> ) ; int64_t ID = MI . getOperand ( StartIdx ) . getImm ( ) ; assert ( ( int32_t ) ID == ID && <STR_LIT> ) ; bool isAnyRegCC = MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) == CallingConv :: AnyReg ; assert ( ( ( hasDef && isAnyRegCC ) || ! hasDef ) && <STR_LIT> ) ; int64_t StackMapIdx = isAnyRegCC ? StartIdx + <NUM_LIT> : StartIdx + <NUM_LIT> + MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) ; assert ( StackMapIdx <= MI . getNumOperands ( ) && <STR_LIT> ) ; SM . recordStackMap ( MI , ID , llvm :: next ( MI . operands_begin ( ) , StackMapIdx ) , getStackMapEndMOP ( MI . operands_begin ( ) , MI . operands_end ( ) ) , isAnyRegCC && hasDef ) ; unsigned EncodedBytes = <NUM_LIT> ; int64_t CallTarget = MI . getOperand ( StartIdx + <NUM_LIT>


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , ELFArch ( <NUM_LIT> ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_hasMemMappedGPR ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , CPU ,


<s> __builtin_ia32_pmovqd128mem_mask ( ( unsigned long long * ) __P


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( ) const { return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl (


<s> B . setInstr ( MI ) ; const bool IsRem = MI . getOpcode ( ) == <STR_LIT> ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Num = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Den = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; legalizeUDIV_UREM32Impl ( B , DstReg , Num , Den , IsRem ) ; MI . eraseFromParent (


<s> EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , SVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode (


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR (


<s> if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex (


<s> static void sparc32_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_shift ( RSHIFT_EXPR , SImode , cxt , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , <NUM_LIT> ) , expand_binop ( SImode , ior_optab , expand_and ( SImode , cxt , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , GEN_INT ( trunc_int_for_mode ( <NUM_LIT> , SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ) ; emit_insn ( gen_flushsi ( validize_mem ( adjust_address ( m_tramp , SImode , <NUM_LIT> )


<s> if ( addr > ( void * ) MIN_PATRANGE && addr < ( void * ) MAX_PATRANGE )


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get (


<s> rtx nvptx_expand_compare ( rtx compare ) { rtx pred = gen_reg_rtx ( BImode ) ; rtx cmp = gen_rtx_fmt_ee ( GET_CODE ( compare ) , BImode , XEXP ( compare , <NUM_LIT> ) , XEXP ( compare , <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( pred ,


<s> case GPRnopcRegClassID : case tGPR_and_tcGPRRegClassID : return getRegBank ( <STR_LIT> ) ; case SPR_8RegClassID : case SPRRegClassID : case DPR_8RegClassID : case DPRRegClassID : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT>


<s> MCB . clear ( ) ; MCB . addOperand ( MCOperand :: createImm ( BundleFlags ) ) ; for ( <ISA_LIT>Shuffler :: iterator I = begin ( ) ; I != end ( ) ; ++ I ) { MCInst const & MI = I -> getDesc ( ) ; MCInst const * Extender = I -> getExtender ( ) ; if ( Extender ) MCB . addOperand ( MCOperand :: createInst ( Extender ) ) ; MCB . addOperand ( MCOperand :: createInst (


<s> FunctionPass * create<ISA_LIT>InstrumentFunctionsPass (


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & OS ) { OS <<


<s> break ; case 'Z' : bitint = INTVAL ( x ) ; fprintf ( file , <STR_LIT> , bitint & <NUM_LIT> ) ; break ; case 'c' : switch ( GET_CODE ( x ) ) { case IOR : fprintf ( file , <STR_LIT> ) ; break ; case XOR : fprintf ( file , <STR_LIT> ) ; break ; case AND : fprintf ( file , <STR_LIT> ) ; break ; default : break ; } break ; case 'e' : switch ( GET_CODE ( x ) ) { case REG : if ( TARGET_H8300 ) fprintf ( file , <STR_LIT> , names_big [ REGNO ( x ) ] ) ; else fprintf ( file , <STR_LIT> , names_upper_extended [ REGNO ( x ) ] ) ; break ; case MEM : h8300_print_operand ( file , x , <NUM_LIT> ) ; break ; case CONST_INT : fprintf ( file , <STR_LIT> , ( ( INTVAL ( x ) >> <NUM_LIT> ) & <NUM_LIT> ) ) ; break ; case CONST_DOUBLE : { long val ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_SINGLE ( rv , val ) ; fprintf ( file , <STR_LIT> , ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ; break ; } default : gcc_unreachable ( ) ; break ; } break ; case 'f' : switch ( GET_CODE ( x ) ) { case REG : if ( TARGET_H8300 ) fprintf ( file , <STR_LIT> , names_big [ REGNO ( x ) + <NUM_LIT> ] ) ; else fprintf ( file , <STR_LIT> , names_big [ REGNO ( x ) ] ) ; break ; case MEM : x = adjust_address ( x , HImode , <NUM_LIT> ) ; h8300_print_operand ( file , x , <NUM_LIT> ) ; break ; case CONST_INT : fprintf ( file , <STR_LIT> , INTVAL ( x ) & <NUM_LIT> ) ; break ; case CONST_DOUBLE : { long val ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_SINGLE ( rv , val ) ; fprintf ( file , <STR_LIT> , ( val & <NUM_LIT> ) ) ; break ; } default : gcc_unreachable ( ) ; } break ; case 'j' : fputs ( cond_string ( GET_CODE ( x ) ) , file ) ; break ; case 'k' : fputs ( cond_string ( reverse_condition ( GET_CODE ( x ) ) ) , file ) ; break ; case 'm' : gcc_assert ( GET_CODE ( x ) == CONST_INT ) ; switch ( INTVAL ( x ) ) { case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; default : gcc_unreachable ( ) ; } break ; case 'o' : h8300_print_operand_address ( file


<s> const MTBUFInfo * Info = getMTBUFOpcodeHelper ( Opc


<s> void <ISA_LIT>AsmParser :: createCpRestoreMemOp ( bool IsLoad , int StackOffset , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; if ( IsLoad ) { TOut . emitLoadWithImmOffset ( <STR_LIT> , <STR_LIT> , <STR_LIT> , StackOffset , <STR_LIT>


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setShiftAmountType ( <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> return Subtarget . isTargetMachO ( ) && ! ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && Attrs . hasAttrSomewhere ( Attribute :: SwiftError ) ) && ! Attrs . hasAttrSomewhere ( Attribute :: SwiftAsync ) && MF . getFunction ( ) .

getCallingConv ( ) != CallingConv :: SwiftTail ;


<s> HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasMPX =


<s> auto * ECNode = CG . getExternalCallingNode ( ) ; for ( const auto & GI : * ECNode ) { auto * CGN = GI . second ; auto * F = CGN -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) || llvm ::


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI ->


<s> if ( ! IdxVal ) return true ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Vec = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ins = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT VecTy = MRI . getType ( Vec ) ; LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI .


<s> EVT ResVT = TLI -> getValueType ( DL , ResTy ) ; if ( ST -> hasMVEIntegerOps ( ) && ValVT . isSimple ( ) && ResVT . isSimple ( ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( ( LT . second == <STR_LIT> && ResVT . getSizeInBits ( ) <= <NUM_LIT> ) || ( LT . second == <STR_LIT> && ResVT . getSizeInBits ( ) <= ( IsMLA ? <NUM_LIT> :

<NUM_LIT> ) ) || ( LT . second == <STR_LIT> && ResVT . getSizeInBits ( ) <= <NUM_LIT> ) ) return ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ;


<s> else if ( cortexa7_younger ( file , verbose , insn ) && first_younger == - <NUM_LIT> ) first_younger = i ; } if ( first_younger == - <NUM_LIT> ) { if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; return ; } if ( first_older_only == - <NUM_LIT> ) { if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; return ; } if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ first_older_only ] ) , INSN_UID ( ready [ first_younger ] ) ) ; rtx_insn * first_older_only_insn = ready [


<s> return calculate_sew ( info1 . get_vlmul ( ) , info2 . get_ratio ( )


<s> if ( crtl -> calls_eh_return ) return true ; return false


<s> XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( SImode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - count * <NUM_LIT> ) ) ) ; pari = <NUM_LIT> ; for ( i = LAST_EXTENDED_REGNUM ; i >= <NUM_LIT> ; i -- ) if ( ( mask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) { rtx address = gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( - pari * <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , pari ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( SImode , address ) , gen_rtx_REG ( SImode , i ) ) ; pari += <NUM_LIT> ; } par = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( par )


<s> case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ; break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case fixup_<ISA_LIT>_32 : InstMask = <NUM_LIT> ; Reloc = Value ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ; DEBUG ( uint32_t OldData =


<s> case MEK_GOT_PAGE : OS << <STR_LIT> ; break ; case MEK_GOT_OFST : OS << <STR_LIT> ; break ; case MEK_GPREL : OS << <STR_LIT> ; break ; case MEK_HI : OS << <STR_LIT> ; break ; case MEK_HIGHER : OS << <STR_LIT> ; break ; case MEK_HIGHEST : OS << <STR_LIT> ; break ; case MEK_LO : OS << <STR_LIT> ; break ; case MEK_NEG : OS << <STR_LIT> ; break ; case MEK_PCREL_HI16 : OS << <STR_LIT> ; break ; case MEK_PCREL_LO16 : OS << <STR_LIT> ; break ; case MEK_TLSGD : OS << <STR_LIT>


<s> if ( <NUM_LIT> <= target_memregs && target_memregs <= <NUM_LIT> ) { for ( i = target_memregs / <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fixed_regs [ MEM0_REGNO + i ]


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return


<s> if ( ! VI . haveGVs ( ) || ! VI . getValue ( ) ) return getValueId ( VI .


<s> int FI = MFI . CreateFixedObject ( ValVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : case CCValAssign :: BCvt : ExtType = <STR_LIT> ; break ; } Val = DAG . getExtLoad ( ExtType , DL , LocVT , Chain , FIN , MachinePointerInfo :: getFixedStack (

DAG . getMachineFunction ( ) , FI ) , ValVT ) ;


<s> return ( __m64 ) __builtin_ia32_paddd ( ( __v2si ) __m1 ,


<s> sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ; return


<s> LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; DebugLoc dl = CP -> getDebugLoc ( ) ; EVT PtrVT = Op . getValueType ( ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) { Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; } else


<s> Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , Mask ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = ( SrcVector == V1 ) && ( Current . getConstantOperandVal ( <NUM_LIT> ) == i ) ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; unsigned ZMask = Zeroable . to_ulong ( ) ; unsigned InsertPSMask = EltMaskIdx << <NUM_LIT> | EltIdx


<s> void printOperand ( const MachineInstr * MI , unsigned OpNo ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { O << getRegisterName ( MO . getReg (


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; unsigned StackSlotsUsedByFunclet = <NUM_LIT> ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { StackSlotsUsedByFunclet = Last - <STR_LIT> ; AmountAboveFunclet += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { AmountAboveFunclet += <NUM_LIT> ; SavedBlink = true ; } if ( StackSize - AmountAboveFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - AmountAboveFunclet ) ; } if ( StackSlotsUsedByFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( load_funclet_name [ Last - <STR_LIT> ] )

. addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( )


<s> return MFI . getStackSize ( ) > RedZoneSize || MFI . hasCalls ( ) ||

MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ;


<s> bool doInitialization ( Module & ) override { if ( ! StatsFile . empty ( ) && ! AppendStatsFile && sys :: fs :: exists ( StatsFile ) ) { sys :: fs :: remove ( StatsFile . c_str ( ) ) ; } return


<s> if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits (


<s> Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpc ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case BND0_REG : case BND1_REG : return chkp_function_instrumented_p ( current_function_decl ) ; case ST0_REG : case ST1_REG


<s> return sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) || sparc_cannot_force_const_mem ( mode


<s> if ( Cursor -> getType ( ) == IVTy ) EarliestReplacement = Cursor ; auto * IntrinsicCursor = dyn_cast < IntrinsicInst > ( Cursor ) ; if ( ! IntrinsicCursor || ! ( IntrinsicCursor -> getIntrinsicID ( ) == <STR_LIT> || IntrinsicCursor -> getIntrinsicID ( ) == <STR_LIT> ) ) break ; CandidatesForRemoval . insert ( CandidatesForRemoval . begin ( ) , IntrinsicCursor ) ; Cursor = IntrinsicCursor -> getOperand


<s> if ( ! ( ( value >> i ) & <NUM_LIT> ) ) mask |= <NUM_LIT> ; } result = gen_int_mode ( mask , DImode


<s> SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr ,


<s> void emitLocalEntry ( MCSymbol * S ,


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> (


<s> if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ; return AsmPrinter :: GetCPISymbol ( CPID


<s> if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ; } if ( isV6M ( ) ) AllowsUnalignedMem = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options .

UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ;


<s> return ( __m64 ) __builtin_ia32_cvtps2pi ( ( __v4sf )


<s> } if ( MEM_P ( operands [ <NUM_LIT> ] ) && arc_is_aux_reg_p ( operands [ <NUM_LIT> ] ) ) { if ( arc_get_aux_arg ( operands [ <NUM_LIT> ] , & auxr ) ) { tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp , GEN_INT ( auxr ) ) ; } else { tmp = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( tmp ) == SYMBOL_REF ) ; } gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , tmp ) , VUNSPEC_ARC_LR ) ) ) ; return true ; } } if ( mode == SImode && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) { prepare_pic_move ( operands , SImode ) ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } } } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat )


<s> if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = FixedVectorType :: get ( SubVecTy -> getElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ; }


<s> MEM_COPY_ATTRIBUTES ( mem , orig_addr ) ; set_mem_size ( mem , GET_MODE_SIZE ( mode ) ) ; do_load_for_compare ( dest , mem


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue ReturnAddress ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddress = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } else { unsigned Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ; } SDNode * St ; if ( Subtarget -> hasPAuth ( ) ) { St = DAG . getMachineNode ( <STR_LIT> , DL , VT , ReturnAddress ) ; } else { SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , ReturnAddress ) ; St = DAG . getMachineNode ( <STR_LIT> , DL , VT , Chain ) ; } return SDValue ( St


<s> obstack_grow ( & m_string_obstack , name , strlen


<s> SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> / M_PI , DL , VT ) ) ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart ) ; default : llvm_unreachable ( <STR_LIT> )


<s> static unsigned getHashValue ( const CvtDirection & Val


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI


<s> printInstruction ( MI , O ) ; printAnnotation ( O , Annot


<s> if ( is64Bit ) PointerSize = <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; PCSymbol = <STR_LIT> ; SupportsDebugInformation = true ; DwarfUsesInlineInfoSection = true ; ExceptionsType = ExceptionHandling


<s> switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return <NUM_LIT> ; case FRAME_POINTER_REGNUM : return offsets -> soft_frame - offsets -> saved_args ; case ARM_HARD_FRAME_POINTER_REGNUM : if ( offsets -> frame == offsets -> saved_regs ) return <NUM_LIT> ; return ( frame_pointer_needed && cfun -> static_chain_decl != NULL && ! cfun -> machine -> uses_anonymous_args ) ? <NUM_LIT> : <NUM_LIT> ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - ( offsets -> saved_args + <NUM_LIT> ) ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; case FRAME_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return <NUM_LIT> ; case


<s> CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue (


<s> rtx tmp2 = * ( const rtx * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? <NUM_LIT> : - <NUM_LIT> ; return INSN_LUID ( tmp ) -


<s> if ( TLI . isTypeLegal ( VT ) ) if ( SDValue AddSub = combineShuffleToAddSubOrFMAddSub ( N , Subtarget , DAG ) ) return AddSub ; if ( SDValue LD = combineToConsecutiveLoads ( VT , SDValue ( N , <NUM_LIT> ) , dl , DAG , Subtarget , true ) ) return LD ; if ( SDValue ShufConcat = combineShuffleOfConcatUndef ( N , DAG , Subtarget ) ) return ShufConcat ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Shuffle = combineTargetShuffle ( Op , DAG , DCI , Subtarget ) ) return Shuffle ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; APInt KnownUndef , KnownZero ; APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( Op , DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; } return SDValue ( )


<s> if ( ItinUnits == <STR_LIT> || ItinUnits == <STR_LIT> ) return ( * Lanes = <NUM_LIT> , CVI_XLANE ) ; else if ( ItinUnits & <STR_LIT> && ItinUnits & <STR_LIT> ) return ( * Lanes = <NUM_LIT> , CVI_XLANE | CVI_MPY0 ) ; else if ( ItinUnits & <STR_LIT> ) return ( * Lanes = <NUM_LIT> , CVI_MPY0 ) ; else if ( ItinUnits & <STR_LIT> ) return ( * Lanes = <NUM_LIT> , CVI_XLANE ) ; else if ( ItinUnits & <STR_LIT> && ItinUnits & <STR_LIT> && ItinUnits & <STR_LIT> && ItinUnits & <STR_LIT> ) return ( * Lanes = <NUM_LIT> , CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 ) ; else if ( ItinUnits & <STR_LIT> && ItinUnits & <STR_LIT> ) return ( *

Lanes = <NUM_LIT> , CVI_XLANE | CVI_SHIFT ) ;


<s> } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ; if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) { return MatchOperand_ParseFail ; } const MCExpr * ModExpr = <ISA_LIT>MCExpr :: create ( SubExpr , VK , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( ModExpr , S , E , isRV64


<s> unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( )


<s> unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , FIOperandNum , this , MF


<s> assert ( ScheduledCycles . find ( BB ) == ScheduledCycles


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>V9Target (


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == SrcRC ) { unsigned Opc ; if ( DestRC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else { return false ; } BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; return true ; } return


<s> const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT . getSimpleVT ( ) ) ; Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return Val ; return convertLocVTToValVT ( DAG , Val , VA ,


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler (


<s> void emitFill ( const MCExpr & NumBytes , uint64_t


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS


<s> return ( uint8x16_t ) ( __a <= <NUM_LIT>


<s> count += get_attr_length ( from ) ; tmp = is_jump_table ( from ) ; if ( tmp != NULL ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next =


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ;


<s> bool <ISA_LIT>MCChecker :: checkRegistersReadOnly ( ) { for ( auto I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCB ) ) { MCInst const & Inst = * I . getInst ( ) ; unsigned Defs = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , Inst ) . getNumDefs ( ) ; for ( unsigned j = <NUM_LIT> ; j < Defs ; ++ j ) { MCOperand const & Operand = Inst . getOperand ( j ) ; assert ( Operand . isReg ( ) && <STR_LIT> ) ; unsigned Register = Operand . getReg ( ) ; if ( ReadOnly . find ( Register ) != ReadOnly . end ( ) ) { reportError ( Inst . getLoc ( ) , <STR_LIT> + Twine ( RI . getName ( Register ) ) + <STR_LIT> ) ; return false ; } } } return true


<s> break ; case <STR_LIT> : Pos = Lsb + <NUM_LIT> ; Size = Msbd + <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MI . setOpcode ( <STR_LIT> ) ; InsnType Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Pos ) ) ; MI . addOperand ( MCOperand :: createImm ( Size


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB ,

MachineBasicBlock :: iterator I ) const {


<s> if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( prev && ( CALL_P ( prev ) || ! insn_nothrow_p ( prev ) ) ) fputs ( <STR_LIT> , out_file ) ; fputs ( <STR_LIT> , out_file ) ; seh -> in_cold_section = true ; return ; } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( seh -> after_prologue ) return ; for ( note = REG_NOTES ( insn ) ; note ;


<s> else if ( idx < ( int ) NumElems ) Mask [ i ] = idx + NumElems ; else Mask [ i ] = idx


<s> if ( ! Store -> isSimple ( ) ) return SDValue ( ) ; EVT StoreVT = StoredVal . getValueType ( ) ; unsigned NumElems = StoreVT . getVectorNumElements ( ) ; unsigned HalfSize = StoredVal . getValueSizeInBits ( ) / <NUM_LIT> ; unsigned HalfAlign = ( <NUM_LIT> == HalfSize ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc DL ( Store ) ; SDValue Value0 = extractSubVector ( StoredVal , <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Value1 = extractSubVector ( StoredVal , NumElems / <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset ( HalfAlign ) , MinAlign ( Alignment , HalfAlign ) , Store ->


<s> } if ( matchADDRrr ( Addr , LHS , RHS ) ) { if ( dyn_cast < FrameIndexSDNode > ( RHS ) ) std :: swap ( LHS , RHS ) ; if ( matchADDRri ( RHS , Index , Offset ) ) { Base = LHS ; return true ; } if ( matchADDRri ( LHS , Base , Offset ) ) { Index = RHS ; return true ; } Base = LHS ; Index = RHS ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr


<s> void removeFromOwner ( NodeAddr < RefNode * > RA ) { NodeAddr < InstrNode * > IA = RA . Addr -> getOwner ( * this ) ; IA . Addr -> removeMember ( RA ,


<s> insn = emit_jump_insn ( insn ) ; add_int_reg_note ( insn , REG_BR_PROB ,


<s> if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , U . getMaxDisp ( ) + <NUM_LIT> , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; dumpBBs ( ) ; DEBUG ( MF -> dump ( ) ) ; llvm_unreachable ( <STR_LIT> )


<s> void <ISA_LIT>InstPrinter :: printZPRasFPR32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg (


<s> bool HasNoMicro<ISA_LIT>Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool softFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU


<s> bool getMAIIsDGEMM ( unsigned Opc ) { const MAIInstInfo * Info =


<s> Value * <ISA_LIT>IREmitter :: visitVFPEXT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> return <STR_LIT> ; } else { assert ( TT . isArch32Bit ( )


<s> if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! EmitLoad ( VT , ResultReg , Addr , cast < LoadInst > ( I ) ->


<s> tree fntype = TREE_TYPE ( current_function_decl ) ; tree result_type = TREE_TYPE ( fntype ) ; if ( TYPE_MODE ( result_type


<s> MI . eraseFromParent ( ) ; return ; } assert ( AMDGPU :: SReg_64RegClass . contains ( Save ) ) ; assert ( AMDGPU :: VReg_32RegClass . contains ( Idx ) ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_MOV_B64 ) , Save ) . addReg ( AMDGPU :: EXEC ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: V_READFIRSTLANE_B32_e32 ) , AMDGPU :: VCC ) . addReg ( Idx ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , AMDGPU :: M0 ) . addReg ( AMDGPU :: VCC ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: V_CMP_EQ_U32_e32 ) , AMDGPU :: VCC ) . addReg ( AMDGPU :: M0 ) . addReg ( Idx ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_AND_SAVEEXEC_B64 ) , AMDGPU :: VCC ) . addReg ( AMDGPU :: VCC ) ; MBB . insert ( I , MovRel ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_XOR_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) . addReg ( AMDGPU :: VCC ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_CBRANCH_EXECNZ ) ) . addImm ( - <NUM_LIT> )


<s> EVT PtrVT = getPointerTy ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , DAG .

getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeBitfieldExtract ( MachineInstr & MI , MachineRegisterInfo & MRI , LegalizerHelper & Helper ) const { return getIConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) && getIConstantVRegValWithLookThrough

( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;


<s> for ( i = <NUM_LIT> ; i < MAX_VECT_LEN ; ++ i ) XVECEXP ( x , <NUM_LIT> , i ) = const0_rtx ; x = gen_rtx_VEC_SELECT ( V2DFmode , gen_rtx_VEC_CONCAT ( V4DFmode , const0_rtx , const0_rtx ) , x ) ; x = gen_rtx_SET ( VOIDmode , const0_rtx ,


<s> return <STR_LIT> ; } if ( Subtarget . hasAltivec ( ) && Size >= <NUM_LIT> && ( ( ( ! SrcAlign || SrcAlign >= <NUM_LIT> ) && ( ! DstAlign || DstAlign >= <NUM_LIT> ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return <STR_LIT> ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT>


<s> MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: Create (


<s> const <ISA_LIT>TargetLowering * getTLI ( )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & MCSTI , MCContext


<s> if ( TARGET_64BIT ) { output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; ASM_OUTPUT_SKIP ( file , ( HOST_WIDE_INT ) ( TRAMPOLINE_SIZE - <NUM_LIT> ) ) ; } else { output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; output_asm_insn ( <STR_LIT> , op ) ; ASM_OUTPUT_SKIP ( file , ( HOST_WIDE_INT ) ( TRAMPOLINE_SIZE - <NUM_LIT>


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter > (


<s> if ( ! isHomogeneousAggregate ( AT -> getElementType ( ) , Base , SubMembers ) ) return false ; Members += SubMembers * AT -> getNumElements ( ) ; } else if ( Ty -> isFloatTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_FLOAT ) return false ; Members = <NUM_LIT> ; Base = HA_FLOAT ; } else if ( Ty -> isDoubleTy ( ) ) { if ( Base != HA_UNKNOWN && Base != HA_DOUBLE ) return false ; Members = <NUM_LIT> ; Base = HA_DOUBLE ; } else if ( auto * VT = dyn_cast < VectorType > ( Ty ) ) { Members = <NUM_LIT> ; switch ( Base ) { case HA_FLOAT : case HA_DOUBLE : return false ; case HA_VECT64


<s> static SDValue lowerVectorShuffleAsLanePermuteAndBlend ( SDLoc DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG ) { assert ( VT . is256BitVector ( ) && <STR_LIT> ) ; int LaneSize = Mask . size ( ) / <NUM_LIT> ; bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; if ( isSingleInputShuffleMask ( Mask ) ) { SmallVector < int , <NUM_LIT> > FlippedBlendMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) FlippedBlendMask . push_back ( Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] :

Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ) ;


<s> Op = parseRegister ( ) ; if ( ! Op ) { if ( ! Offset ) { if ( ( Op = parseImmediate ( ) ) && Lexer . is ( AsmToken :: RBrac ) ) { Parser . Lex ( ) ; if ( shouldBeSls ( * Op ) ) { Operands . push_back ( <STR_LIT> ( std :: move ( Op ) ) ) ; } else { if ( ! Op -> isLoImm16Signed ( ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , std :: move ( Op ) , LPAC :: ADD ) ) ; } return MatchOperand_Success ; } } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } BaseReg = Op -> getReg ( ) ; if ( ! PreOp ) PostOp = parsePrePost ( Type , & OffsetValue ) ; if ( Lexer . is ( AsmToken :: RBrac ) ) { Parser . Lex ( ) ; if ( ! Offset ) { SMLoc Start = Parser . getTok ( ) . getLoc ( ) ; SMLoc End = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCConstantExpr * OffsetConstExpr = MCConstantExpr :: create ( OffsetValue , getContext (


<s> bool <ISA_LIT>InstrInfo :: hasLoadFromStackSlot ( const MachineInstr * MI , const MachineMemOperand * &


<s> unsigned Opc = is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; if ( NumVecs <= <NUM_LIT> && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! IsImmUpdate ) Ops . push_back ( Inc ) ; else if ( NumVecs > <NUM_LIT> ) Ops . push_back ( Reg0 ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLdDup = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else if ( NumVecs == <NUM_LIT> ) { const SDValue OpsA [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; const SDValue OpsB [ ] = { MemAddr , Align , Pred , Reg0 , Chain } ; VLdDup = CurDAG -> getMachineNode ( QOpcodes1 [ OpcodeIndex ] , dl , ResTys , OpsB ) ; } else { SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTys , OpsA ) ; SDValue SuperReg = SDValue ( VLdA , <NUM_LIT> ) ; Chain = SDValue (


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> dbgs ( ) << <STR_LIT> ; for ( auto I : OG ) dbgs ( ) << <STR_LIT> << * I ; dbgs ( ) <<


<s> int NumV2Inputs = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , isV2 ) ; if ( NumV2Inputs == <NUM_LIT> ) return lowerV8I16SingleInputVectorShuffle ( DL , V1 , Mask , Subtarget , DAG ) ; assert ( NumV1Inputs > <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( Subtarget -> hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Rotate ; if ( NumV1Inputs + NumV2Inputs <= <NUM_LIT> ) return lowerV8I16BasicBlendVectorShuffle ( DL , V1 , V2 , Mask , Subtarget , DAG ) ; if ( shouldLowerAsInterleaving ( Mask ) ) { int EMask [ <NUM_LIT> ] , OMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { EMask [ i ] = Mask [ <NUM_LIT> * i ] ; OMask [ i ] = Mask [ <NUM_LIT> * i + <NUM_LIT> ] ; EMask [ i + <NUM_LIT> ] = - <NUM_LIT> ; OMask [ i + <NUM_LIT> ] = - <NUM_LIT> ; } SDValue Evens = DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , EMask ) ; SDValue Odds = DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , OMask ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Evens , Odds ) ; } int LoBlendMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiBlendMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { LoBlendMask [ i ] = Mask [ i ] ; HiBlendMask [ i ] = Mask [ i


<s> return ( vector signed char ) __builtin_altivec_lvxl ( a1 ,


<s> storeRegToStackSlotImpl ( MBB , MI , SrcReg , isKill


<s> if ( hasShortDelaySlot ) emitRR ( <STR_LIT> , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ; else emitRRI ( <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value

, const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const {


<s> Value * <ISA_LIT>IREmitter :: visitWrapperRIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , <NUM_LIT> , <NUM_LIT> ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( SImode , sp_reg , plus_constant ( SImode

, sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ;


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =