<s> unsigned StackReg = MF . getTarget ( ) . getRegisterInfo ( ) -> getFrameRegister ( MF ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( <NUM_LIT> ) ; std :: vector < SDValue > OutChains ; unsigned ArgRegEnd = <NUM_LIT> ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; SDValue StackPtr ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { MVT RegVT = VA . getLocVT ( ) ; ArgRegEnd = VA . getLocReg ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( ArgRegEnd , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned StackLoc = VA . getLocMemOffset ( ) + <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordLoadArgsFI ( FI , - StackLoc ) ; <ISA_LIT>FI -> recordLiveIn ( FI ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( ( isVarArg ) && ArgRegEnd ) { if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getRegister ( StackReg , getPointerTy ( ) ) ; const TargetRegisterClass *


<s> mode = TYPE_MODE ( valtype ) ; mode = promote_function_mode ( valtype , mode , & unsigned_p , func , <NUM_LIT> ) ; return handle_structs_in_regs ( mode , valtype ,


<s> bool hasIndexHalfRegs ( ) const { return HasIdxHalfRegs


<s> case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: <ISA_LIT>_AAPCS_VFP : case CallingConv :: <ISA_LIT>_AAPCS : case CallingConv :: <ISA_LIT>_APCS : break ; } unsigned Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > <NUM_LIT> ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = TLI . getRegClassFor ( <STR_LIT> ) ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; UpdateValueMap ( I , ResultReg ) ; } return true


<s> for ( size_t i = <NUM_LIT> ; i < strlen ( p ) ; ++ i ) if ( p


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : Changed |= enableGLCBit ( MI ) ; Changed |= enableDLCBit ( MI ) ; break ; case <STR_LIT> : if ( ! CuMode ) Changed |= enableGLCBit ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } return Changed


<s> double foo = __floatsidf ( l ) ; return foo


<s> MOpc = NVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; New = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , NVT , New ) , <NUM_LIT> ) ; if ( NVT == <STR_LIT> ) { New = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , New , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ) , <NUM_LIT> ) ; } } MachineSDNode * NewNode ; SDValue Input = N0 -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( tryFoldLoad ( Node , Input , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , New , Input . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( NVT , <STR_LIT> ) ; NewNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( N1 . getValue ( <NUM_LIT> ) , SDValue ( NewNode , <NUM_LIT> ) ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( Input ) ; if ( LoadNode ) { MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LoadNode -> getMemOperand ( ) ; NewNode -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; } } else { NewNode = CurDAG -> getMachineNode ( ROpc , dl , NVT , Input , New ) ; } ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( NewNode , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode (


<s> setAction ( { G_CONSTANT , S1 } , Legal ) ; setAction ( { G_CONSTANT , S32 } , Legal ) ; setAction ( { G_CONSTANT , S64 } , Legal ) ; setAction ( { G_FCONSTANT , S32 } , Legal ) ; setAction ( { G_FADD , S32 } , Legal ) ; setAction ( { G_FMUL , S32 } , Legal ) ; setAction ( { G_FPTOUI , S32 } , Legal ) ; setAction ( { G_FPTOUI , <NUM_LIT> , S32 } , Legal ) ; setAction ( { G_GEP , P1 } , Legal ) ; setAction ( { G_GEP , P2 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , S64 } , Legal ) ; setAction ( { G_ICMP , S1 } , Legal ) ; setAction ( { G_ICMP , <NUM_LIT> , S32 } , Legal ) ; setAction ( { G_LOAD , P1 } , Legal ) ; setAction ( { G_LOAD , P2 } , Legal ) ; setAction ( { G_LOAD , S32 } , Legal ) ; setAction ( { G_LOAD , <NUM_LIT> , P1 } , Legal ) ; setAction ( { G_LOAD , <NUM_LIT> , P2 } , Legal ) ; setAction ( { G_OR , S32 } , Legal ) ; setAction ( { G_SELECT , S32 } , Legal ) ; setAction ( { G_SELECT , <NUM_LIT> , S1 } , Legal ) ; setAction ( { G_SHL , S32


<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { if ( ! isEvaluated ( BE -> getLHS ( ) ) ) return false ; return isEvaluated ( BE -> getRHS ( ) ) ; } case MCExpr :: Unary : return isEvaluated ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr


<s> return ( __m128i ) __builtin_ia32_psubusb128 ( ( __v16qi )


<s> OutStreamer . SwitchSection ( getObjFileLowering ( ) . SectionForGlobal ( GVar , Mang , TM ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) ) { if ( ! GVar -> isThreadLocal ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> isWeakForLinker ( ) ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) O << <STR_LIT> << name << '\n' ; O << TAI -> getCOMMDirective ( ) << name << ',' << Size ; if ( TAI -> getCOMMDirectiveTakesAlignment ( ) ) O << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: CommonLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: PrivateLinkage : case GlobalValue :: LinkerPrivateLinkage : case GlobalValue :: InternalLinkage : if ( CVA && CVA -> isCString ( ) ) printSizeAndType = false ; break ; case GlobalValue :: GhostLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: DLLImportLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: DLLExportLinkage : llvm_unreachable ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } EmitAlignment ( Align , GVar ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) && printSizeAndType ) { O << <STR_LIT> << name << <STR_LIT> ; O << <STR_LIT> << name << ',' << Size << '\n' ; } O << name << <STR_LIT> ; EmitGlobalConstant (


<s> static bool InRange ( int64_t Value , unsigned short Shift , int LBound , int HBound ) { int64_t Value2 = Value >> Shift ; if ( ( Value2 << Shift ) == Value && ( Value2 >= LBound ) && ( Value2 < HBound ) ) return true ; return false


<s> SMLoc getStartLoc ( ) const { return


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateNumericReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { DEBUG ( dbgs ( ) << <STR_LIT> << Index << <STR_LIT> ) ; return CreateReg ( Index , RegKind_Numeric , RegInfo , S


<s> if ( Op . isImm ( ) ) { O << formatImm ( Op . getImm ( ) ) ; return ; } assert ( Op . isExpr (


<s> const FPMathOperator * FPOp = cast < const FPMathOperator > ( & FDiv ) ; float ULP = FPOp -> getFPAccuracy ( ) ; if ( ULP < <NUM_LIT> ) return false ; FastMathFlags FMF = FPOp -> getFastMathFlags ( ) ; bool UnsafeDiv = HasUnsafeFPMath || FMF . unsafeAlgebra ( ) || FMF . allowReciprocal ( ) ; if ( ST -> hasFP32Denormals ( ) && ! UnsafeDiv ) return false ; IRBuilder < > Builder ( FDiv . getParent ( ) , std :: next ( FDiv . getIterator ( ) ) , FPMath ) ; Builder . setFastMathFlags ( FMF ) ; Builder . SetCurrentDebugLocation ( FDiv . getDebugLoc ( ) ) ; const <ISA_LIT>IntrinsicInfo * II = TM -> getIntrinsicInfo ( ) ; Function * Decl = II -> getDeclaration ( Mod , <STR_LIT> , { } ) ; Value * Num = FDiv . getOperand ( <NUM_LIT> ) ; Value * Den = FDiv . getOperand ( <NUM_LIT> ) ; Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ; Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ; Value * NewElt ; if ( shouldKeepFDivF32 ( NumEltI , UnsafeDiv ) ) { NewElt = Builder . CreateFDiv ( NumEltI , DenEltI ) ; }


<s> EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; auto * MINode = cast < MemIntrinsicSDNode > ( N ) ; SDValue PassThru = DAG . getConstant ( <NUM_LIT> , DL , LoadVT ) ; SDValue L = DAG . getMaskedLoad ( LoadVT , DL , MINode -> getChain ( ) , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , PassThru , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , <STR_LIT> , false ) ; if ( VT . isFloatingPoint ( ) ) { SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , L ) , L . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } return L


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart (


<s> replaceCall ( opr0 ) ; return true ; } if ( ci_opr1 == <NUM_LIT> ) { std :: vector < const Type * > ParamsTys ; ParamsTys . push_back ( opr0 -> getType ( ) ) ; Module * M = CI -> getModule ( ) ; if ( FunctionCallee FPExpr = getFunction ( M , <ISA_LIT>LibFunc ( <ISA_LIT>LibFunc :: EI_SQRT , FInfo ) ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; Value * nval = CreateCallEx ( B , FPExpr , opr0 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; } } else if ( ci_opr1 == <NUM_LIT> ) { Module * M = CI -> getModule ( ) ; if ( FunctionCallee FPExpr = getFunction ( M , <ISA_LIT>LibFunc (

<ISA_LIT>LibFunc :: EI_CBRT , FInfo ) ) ) {


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { return AsmPrinter :: runOnMachineFunction


<s> static inline bool isSVECpyImmByte (


<s> SDLoc dl ( N ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ) ; } } if ( SDValue V = combineParity ( N , DAG , Subtarget ) ) return V ; if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps ) && SrcOps . size ( ) == <NUM_LIT> ) { SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { APInt AllBits = APInt :: getAllOnesValue ( NumElts ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , DAG . getConstant ( AllBits , dl , MaskVT ) , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits


<s> __o = __builtin_aarch64_ld3rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregcidi ( __o , <NUM_LIT> ) ; return ret


<s> return DAG . getTargetFrameIndex ( FI , Op . getValueType (


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned <ISA_LIT>Reg = <STR_LIT> ; SDValue <ISA_LIT> = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>Reg , <STR_LIT> ) ; SDValue New<ISA_LIT> = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT> , Size ) ; Chain = DAG . getCopyToReg ( <ISA_LIT> . getValue ( <NUM_LIT> ) , dl , <ISA_LIT>Reg , New<ISA_LIT> ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , New<ISA_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ops [ <NUM_LIT> ] = { NewVal , Chain } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , dl


<s> if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask :


<s> static inline bool isRVVWideningReduction ( uint64_t TSFlags ) { return TSFlags &


<s> StringRef getPassName ( ) const override { return


<s> const char * rs6000_xcoff_strip_dollar ( const char * name ) { char * strip , * p ; const char * q ; size_t len ; q = ( const char * ) strchr ( name , '$' ) ; if ( q == <NUM_LIT> || q == name


<s> assert ( Offset && <STR_LIT> ) ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } ZFI -> setLowSavedGPR ( LowGPR ) ; ZFI -> setHighSavedGPR ( HighGPR ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E


<s> if ( ! MDT -> dominates ( Def , Instr ) ) return false ; if ( UseToDefs . find ( Def ) == UseToDefs . end ( ) || UseToDefs . find ( Def ) -> second . empty ( ) ) return false ; Instr =


<s> ss = * sc ; memcpy ( prev_cycle_state , sc ->


<s> init_adjust_machine_modes ( ) ; init_derived_machine_modes ( ) ; reinit_regs ( ) ; init_optabs (


<s> if ( MO . isImm ( ) ) { O << ( unsigned int ) MO . getImm (


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm ( ) -


<s> for ( int regno = P4_REGNUM ; regno <= P15_REGNUM ; ++ regno ) CLEAR_HARD_REG_BIT ( full_reg_clobbers , regno ) ; sve_abi . initialize ( ARM_PCS_SVE ,


<s> unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; assert ( Offset1 <= Offset2 && <STR_LIT>


<s> static bool s390_safe_relative_long_p ( rtx_insn * insn ) { if ( recog_memoized ( insn ) >= <NUM_LIT> ) return get_attr_relative_long (


<s> void <ISA_LIT>AsmPrinter :: EmitFStart ( MCSymbol * SymStart , MCSymbol * SymEnd , Align Alignment ) { const MCExpr * SizeExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( SymEnd , OutContext ) , MCSymbolRefExpr :: create ( SymStart , OutContext ) , OutContext ) ; <ISA_LIT>TargetStreamer * PTS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode ::


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get (


<s> push_to_sequence2 ( after_md_seq , after_md_end ) ; emit_insn ( gen_fprx2_to_tf ( outputs [ i ] , fprx2 ) ) ; after_md_seq = get_insns ( ) ; after_md_end = get_last_insn ( ) ; end_sequence ( ) ; outputs [ i ] = fprx2 ; } for ( unsigned i = <NUM_LIT> ; i < ninputs ; i ++ ) { if ( GET_MODE ( inputs [ i ] ) != TFmode ) continue ; const char * constraint = constraints [ noutputs + i ] ; bool allows_mem , allows_reg ; bool ok = parse_input_constraint ( & constraint , i , ninputs , noutputs , <NUM_LIT> , constraints . address ( ) , & allows_mem , & allows_reg ) ; gcc_assert ( ok ) ; if ( ! f_constraint_p ( constraint ) ) continue ; gcc_assert ( allows_reg ) ; rtx fprx2 = gen_reg_rtx ( FPRX2mode ) ; emit_insn ( gen_tf_to_fprx2 ( fprx2 , inputs [ i ] ) ) ; inputs [ i ] = fprx2 ; input_modes [ i ] = FPRX2mode ; } return


<s> virtRegs . insert ( LR -> virtRegs . begin ( )


<s> fprintf ( stderr , <STR_LIT> , mode_name [ from ] , mode_name [ to ] , class_names [ rclass ] ) ; for ( rn = <NUM_LIT> ; rn < FIRST_PSEUDO_REGISTER ; rn ++ ) if ( class_contents [ rclass ] [ <NUM_LIT> ] & ( <NUM_LIT> << rn ) ) if ( ! m32c_hard_regno_ok ( rn , to ) ) return <NUM_LIT> ; if ( to == QImode ) return ( class_contents [ rclass ] [ <NUM_LIT> ] & <NUM_LIT> ) ; if ( class_contents [ rclass ] [ <NUM_LIT> ] & <NUM_LIT> && GET_MODE_SIZE ( from ) > <NUM_LIT> ) return <NUM_LIT> ; if ( GET_MODE_SIZE ( from ) > <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> const TargetRegisterInfo * TRI = BB -> getParent ( ) -> getTarget ( ) . getRegisterInfo ( ) ; if ( ! MI -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( MI , BB , TRI ) ) { copy0MBB -> addLiveIn ( <STR_LIT> ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; } sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; copy0MBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( )


<s> bool isDecl = GV -> isDeclaration ( ) && ! GV -> hasNotBeenReadFromBitcode ( ) ; if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ; return RelocM != Reloc :: Static && ( isDecl || GV


<s> static unsigned createLaneMaskReg ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget <


<s> continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = ( <ISA_LIT>TargetLowering * ) getTargetLowering ( ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT


<s> EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = <STR_LIT> ( EltTy ,


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; const SDValue Ops0 [ ] = { DAG . getTargetConstant ( AMDGPU :: SGPR_64RegClassID , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , <NUM_LIT> ) , DAG . getTargetConstant ( AMDGPU :: sub0 , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , TII -> getDefaultRsrcDataFormat ( ) >> <NUM_LIT> ) , DAG . getTargetConstant ( AMDGPU :: sub1 , <STR_LIT> ) } ; SDValue SubRegHi = SDValue ( DAG . getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , <STR_LIT> , Ops0 ) , <NUM_LIT> ) ; const SDValue Ops1 [ ] = { DAG . getTargetConstant ( AMDGPU :: SReg_128RegClassID , <STR_LIT> ) , Ptr , DAG . getTargetConstant ( AMDGPU :: sub0_sub1 , <STR_LIT> ) , SubRegHi , DAG . getTargetConstant ( AMDGPU :: sub2_sub3 , <STR_LIT> ) } ; return DAG . getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , <STR_LIT> , Ops1 ) ; const SDValue Ops [ ]


<s> static inline bool offset_9bit_signed_unscaled_p ( machine_mode mode ATTRIBUTE_UNUSED


<s> IV = getIsaVersion ( ST . getCPU ( )


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , TM . getPointerSize ( ) * <NUM_LIT> ) ; const LLT s1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) for ( auto Ty : { s8 , s16 , s32 , s64 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , s64 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , s1 } , WidenScalar ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } ,


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; a = arm_function_value ( TREE_TYPE ( exp ) , decl , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun


<s> DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << OffsetBits << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset

<< <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ;


<s> static SDValue LowerMEMBARRIER ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op5 = Op . getOperand ( <NUM_LIT> ) ; SDValue Res ; unsigned isDeviceBarrier = cast < ConstantSDNode > ( Op5 ) -> getZExtValue ( ) ; if ( isDeviceBarrier ) { if ( Subtarget -> hasV7Ops ( ) ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG .

getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> TargetIRAnalysis <ISA_LIT>BaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo (


<s> printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { O <<


<s> static void mmix_file_start ( void ) { default_file_start ( )


<s> } if ( ! DstReg ) return false ; for ( MachineRegisterInfo :: use_iterator U = MRI -> use_begin ( DstReg ) , E = MRI -> use_end ( ) ; U != E ; ) { MachineOperand & MO = * U ; unsigned OpNo = U . getOperandNo ( ) ; MachineInstr * MI = MO . getParent ( ) ; ++ U ; if ( MI -> isPHI ( ) || MI -> isRegTiedToDefOperand ( OpNo ) || MI -> isPseudo ( ) ) continue ; MO . setReg


<s> return parseRegister ( Operands , 'x' ,


<s> if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT>


<s> return ( ( qword ) ( vec_mulo ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) ( b


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName =


<s> if ( op && GET_CODE ( op ) == PLUS && CONST_SCALAR_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) { off = XEXP ( op , <NUM_LIT> ) ; op = XEXP ( op , <NUM_LIT> ) ; } while ( op && GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( op && GET_CODE ( op ) != REG ) return false ; if ( offset )


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isX18Reserved ( ) ) || ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isX20Reserved ( ) ) ) Reg = <NUM_LIT> ; if ( Reg ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT>


<s> case CCValAssign :: ZExtUpper : UseUpperBits = true ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == std :: numeric_limits < int32_t


<s> return BB ; case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } case <STR_LIT> : return splitKillBlock ( MI , BB ) ; default : return <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; } return


<s> MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; } return true ; } else if ( OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( Pred [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( MBB ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( MBB ) ; } else { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> )


<s> const auto SignBitMask = B . buildConstant ( S32 , UINT32_C ( <NUM_LIT> ) << <NUM_LIT> ) ; auto SignBit = B . buildAnd ( S32 , Hi , SignBitMask ) ; const auto FractMask = B . buildConstant ( S64 , ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> ) ; const auto Zero32 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto SignBit64 = B . buildMerge ( S64 , { Zero32 . getReg ( <NUM_LIT> ) , SignBit . getReg ( <NUM_LIT> ) } ) ; auto Shr = B . buildAShr ( S64 , FractMask , Exp ) ; auto Not = B . buildNot ( S64 , Shr ) ; auto Tmp0 = B . buildAnd (


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , IntPtrTy , DAG . getTargetExternalSymbol

( <STR_LIT> , getPointerTy ( ) ) , std :: move ( Args ) , <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>65816Target ( ) { RegisterTargetMachine < <ISA_LIT>65816TargetMachine > X (


<s> DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT>


<s> return ( int32x2_t ) __builtin_aarch64_subhnv2di


<s> if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) ; if ( StrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( - <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } Regs . clear


<s> tocrel_insn = DF_REF_INSN ( def_link -> ref ) ; break ; } gcc_assert ( tocrel_insn ) ; rtx base , offset ; rtx tocrel_expr = SET_SRC ( PATTERN ( tocrel_insn ) ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) gcc_unreachable ( ) ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; rtx const_vector = get_pool_constant ( base ) ; if ( GET_CODE ( const_vector ) == SYMBOL_REF ) const_vector = get_pool_constant ( const_vector ) ; gcc_assert ( GET_CODE ( const_vector ) == CONST_VECTOR ) ; unsigned int new_mask [ <NUM_LIT> ] , i , val ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { val = INTVAL ( XVECEXP ( const_vector , <NUM_LIT> , i ) ) ; if ( val < <NUM_LIT> ) new_mask [ i ] = ( val + <NUM_LIT> ) % <NUM_LIT> ; else new_mask [ i ] = ( ( val + <NUM_LIT> ) % <NUM_LIT> ) + <NUM_LIT> ; } rtx vals = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) XVECEXP ( vals , <NUM_LIT> , i ) = GEN_INT ( new_mask [ i ] ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( vals , <NUM_LIT> ) ) ; rtx new_mem = force_const_mem ( V16QImode , new_const_vector ) ; if ( ! REG_P ( XEXP ( new_mem , <NUM_LIT> ) ) ) { rtx base_reg = force_reg ( Pmode , XEXP ( new_mem , <NUM_LIT> ) ) ; XEXP ( new_mem , <NUM_LIT> ) = base_reg ; rtx_insn * force_insn = get_last_insn ( ) ; remove_insn ( force_insn ) ; rtx_insn * before_load_insn = PREV_INSN


<s> static int mips_issue_rate ( void ) { switch ( mips_tune ) { case PROCESSOR_74KC : case PROCESSOR_74KF2_1 : case PROCESSOR_74KF1_1 : case PROCESSOR_74KF3_2 : case PROCESSOR_R10000 : return <NUM_LIT> ; case PROCESSOR_20KC : case PROCESSOR_R4130 : case PROCESSOR_R5400 : case PROCESSOR_R5500 : case PROCESSOR_R5900 : case PROCESSOR_R7000 : case PROCESSOR_R9000 : case PROCESSOR_OCTEON : case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : case PROCESSOR_I6400 : return <NUM_LIT> ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return <NUM_LIT> ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_LOONGSON_3A : case PROCESSOR_P5600


<s> SDValue L1 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp1 ) ; SDValue HRes = DAG . getNode ( Opcode , DL , <STR_LIT> , H0 , H1 ) ; SDValue LRes = DAG . getNode ( Opcode , DL , <STR_LIT> , L0 , L1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , HRes , LRes ) ; } return DAG . getNode ( Opcode , DL ,


<s> break ; case LABEL_REF : x = XEXP ( x , <NUM_LIT> ) ; case CODE_LABEL : ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , CODE_LABEL_NUMBER ( x ) ) ; assemble_name ( asm_out_file , buf ) ; break ; case CONST_INT : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( x ) ) ; break ; case CONST : output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode ) { if ( CONST_DOUBLE_HIGH ( x ) || CONST_DOUBLE_LOW ( x ) < <NUM_LIT> ) fprintf ( file , <STR_LIT> , ( unsigned long ) CONST_DOUBLE_HIGH ( x ) , ( unsigned long ) CONST_DOUBLE_LOW ( x ) ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , CONST_DOUBLE_LOW ( x ) ) ; } else output_operand_lossage ( <STR_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else { gcc_assert ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '+' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } break ; case MINUS : if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; putc ( '-' , file ) ; output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; if ( ! TARGET_MACHO ) putc ( ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']' , file ) ; break ; case UNSPEC : gcc_assert ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) ; output_pic_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , code ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTPCREL : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_TPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_NTPOFF : if ( TARGET_64BIT ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_DTPOFF : fputs ( <STR_LIT> , file ) ; break ; case UNSPEC_GOTNTPOFF : if ( TARGET_64BIT ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT>


<s> Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto CC = static_cast < <STR_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; SmallVector < MachineInstr * , <NUM_LIT> > SelectDebugValues ; SmallSet < Register , <NUM_LIT> > SelectDests ; SelectDests . insert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * LastSelectPseudo = & MI ; for ( auto E = BB -> end ( ) , SequenceMBBI = MachineBasicBlock :: iterator ( MI ) ; SequenceMBBI != E ; ++ SequenceMBBI ) { if ( SequenceMBBI -> isDebugInstr ( ) ) continue ; else if ( isSelectPseudo ( * SequenceMBBI ) ) { if ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != LHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != RHS || SequenceMBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) != CC || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || SelectDests . count ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) break ; LastSelectPseudo = & * SequenceMBBI ; SequenceMBBI -> collectDebugValues ( SelectDebugValues


<s> CurrGroupSize = Incoming -> CurrGroupSize ; DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ; GrpCount = Incoming ->


<s> if ( SDValue Result = AddCombineToVPADD ( N , N0 , N1 , DCI , Subtarget ) ) return Result ; if ( SDValue Result = AddCombineVUZPToVPADDL ( N , N0 , N1 , DCI , Subtarget


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool DumpAsm , JITCodeEmitter & JCE ) { if ( DefRelocModel == Reloc :: Default ) setRelocationModel ( Reloc :: Static ) ; PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) ,


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT>


<s> if ( i == <NUM_LIT> ) { Rv ( StackFixup :: pushI ( j ) ) ; } else { XchgPairCorrector Correct ( <NUM_LIT> , i ) ; Correct ( j ) ; Rv ( StackFixup :: xcpu ( i ,


<s> SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( ! SelectAddr ( Node , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) return NULL ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node


<s> if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler ::


<s> return ( __mmask8 ) __builtin_ia32_cvtq2mask128 ( ( __v2di


<s> if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerVectorShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerVectorShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Unpack ; if ( ! IsBlendSupported && Subtarget . hasSSSE3 ( ) ) { bool V1InUse , V2InUse


<s> <ISA_LIT>MCCodeEmitter ( TargetMachine & tm , MCContext & ctx , bool is64Bit ) : TM ( tm ) , TII (

* TM . getInstrInfo ( ) ) , Ctx ( ctx ) {


<s> int Offset = <NUM_LIT> + mergeSPUpdates ( MBB , MBBI , true ) ; emitSPUpdate ( MBB , MBBI , DL , Offset , true ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , MachineFramePtr ) . addUse ( MachineFramePtr ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } if ( NeedsDwarfCFI ) { unsigned DwarfStackPtr = TRI -> getDwarfRegNum ( Is64Bit ? <STR_LIT> : <STR_LIT> , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: cfiDefCfa ( nullptr , DwarfStackPtr , SlotSize ) ) ; if ( ! MBB . succ_empty ( ) && ! MBB . isReturnBlock ( ) ) { unsigned DwarfFramePtr = TRI -> getDwarfRegNum ( MachineFramePtr , true ) ; BuildCFI ( MBB , AfterPop , DL , MCCFIInstruction :: createRestore ( nullptr , DwarfFramePtr ) ) ; -- MBBI ; -- AfterPop ; } -- MBBI ; } } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( ( TRI -> hasStackRealignment ( MF ) ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> hasStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) LEAAmount -= <NUM_LIT> ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' : case


<s> if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = <NUM_LIT> ; i != Ins . size ( ) ; i ++ ) { <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return


<s> if ( getFrameLowering ( MF ) -> hasFP ( MF ) ) return <STR_LIT> ; return <STR_LIT>


<s> EVT SplitVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorElementCount ( ) . divideCoefficientBy ( N ) ) ; assert ( isTypeLegal ( SplitVT ) ) ; SmallVector < EVT , <NUM_LIT> > VTs ( N , SplitVT ) ; VTs . push_back ( <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( VTs ) ; SDValue PseudoLoad = DAG . getNode ( Opcode , DL , NodeTys , LoadOps


<s> for ( Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; unsigned Size = DL . getTypeSizeInBits ( ArgTy ) ; unsigned AllocSize = DL . getTypeAllocSize ( ArgTy ) ; uint64_t EltOffset = alignTo ( ExplicitArgOffset , ABITypeAlign ) + BaseOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , ABITypeAlign ) + AllocSize ; if ( Arg . use_empty ( ) ) continue ; if ( PointerType * PT = dyn_cast < PointerType > ( ArgTy ) ) { if ( ( PT -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || PT -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ) && ! ST . hasUsableDSOffset ( ) ) continue ; if ( Arg . hasNoAliasAttr ( ) ) continue ; } auto * VT = dyn_cast < FixedVectorType > ( ArgTy ) ; bool IsV3 = VT && VT -> getNumElements ( ) == <NUM_LIT> ; bool DoShiftOpt = Size < <NUM_LIT> && ! ArgTy -> isAggregateType ( ) ; VectorType * V4Ty = nullptr ; int64_t AlignDownOffset = alignDown ( EltOffset , <NUM_LIT> ) ; int64_t OffsetDiff = EltOffset - AlignDownOffset ; Align AdjustedAlign = commonAlignment ( KernArgBaseAlign , DoShiftOpt ? AlignDownOffset : EltOffset ) ; Value * ArgPtr ; Type * AdjustedArgTy ; if ( DoShiftOpt ) { ArgPtr = Builder . CreateConstInBoundsGEP1_64 ( Builder . getInt8Ty ( ) , KernArgSegment , AlignDownOffset , Arg . getName ( ) + <STR_LIT> ) ; AdjustedArgTy = Builder . getInt32Ty ( ) ; } else { ArgPtr = Builder . CreateConstInBoundsGEP1_64 ( Builder . getInt8Ty ( ) , KernArgSegment , EltOffset , Arg . getName ( ) + <STR_LIT> ) ; AdjustedArgTy = ArgTy ; } if ( IsV3 && Size >= <NUM_LIT> ) { V4Ty = FixedVectorType :: get ( VT -> getElementType ( ) , <NUM_LIT> ) ; AdjustedArgTy = V4Ty ; } ArgPtr = Builder . CreateBitCast ( ArgPtr , AdjustedArgTy -> getPointerTo ( AS ) , ArgPtr -> getName ( ) + <STR_LIT> ) ; LoadInst * Load = Builder . CreateAlignedLoad ( AdjustedArgTy , ArgPtr , AdjustedAlign ) ; Load -> setMetadata ( LLVMContext :: MD_invariant_load , MDNode :: get ( Ctx , { } ) ) ; MDBuilder MDB ( Ctx ) ; if ( isa < PointerType > ( ArgTy ) ) { if ( Arg . hasNonNullAttr ( ) ) Load -> setMetadata ( LLVMContext :: MD_nonnull , MDNode :: get ( Ctx , { } ) ) ; uint64_t DerefBytes = Arg . getDereferenceableBytes ( ) ; if ( DerefBytes != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_dereferenceable , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , DerefBytes ) ) ) ) ; } uint64_t DerefOrNullBytes = Arg . getDereferenceableOrNullBytes ( ) ; if ( DerefOrNullBytes != <NUM_LIT> )


<s> DItype __fixsfdi ( SFtype a ) { if ( a < <NUM_LIT> ) return -


<s> Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; MVT SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , dl ) ; } else { SDValue Flag ; const unsigned Reg = ( Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned SPReg = RegInfo ->


<s> SDValue Value = StoreNode -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; if ( VT . isVector ( ) ) { unsigned AS = StoreNode -> getAddressSpace ( ) ; unsigned Align = StoreNode -> getAlignment ( ) ; if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return


<s> FunctionPass * llvm :: createAMDGPUCFGPreparationPass ( TargetMachine & tm ) { return new AMDGPUCFGPrepare


<s> unsigned <ISA_LIT>TargetLowering :: getByValTypeAlignment ( Type * Ty ) const { if ( <ISA_LIT>SubTarget . isDarwin (


<s> const char * pass_name = current_pass -> name ; if ( pass_name && ( ( strcmp ( pass_name , <STR_LIT> ) == <NUM_LIT> ) || ( strcmp ( pass_name , <STR_LIT> ) == <NUM_LIT> ) ) ) return ! satisfies_constraint_Da ( mem ) || MEM_VOLATILE_P ( mem ) ; return


<s> unsigned char VEX_B = <NUM_LIT> ; unsigned char VEX_W = <NUM_LIT> ; unsigned char XOP = <NUM_LIT> ; unsigned char VEX_5M = <NUM_LIT> ; unsigned char VEX_4V = <NUM_LIT> ; unsigned char VEX_L = <NUM_LIT> ; unsigned char VEX_PP = <NUM_LIT> ; if ( TSFlags & <STR_LIT> ) VEX_PP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_W = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) XOP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_L = <NUM_LIT> ; switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <NUM_LIT> : break ; } unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF .


<s> mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = gen_reg_rtx ( mode ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , force_reg ( mode , operand1 ) , mask ) ; emit_label (


<s> vrev64_u32 ( uint32x2_t a ) { return __builtin_shuffle ( a , ( uint32x2_t )


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( ) ; return false


<s> LabelPHI -> addIncoming ( Label , EndBB ) ; LabelPHI -> addIncoming ( IRB . getInt32 ( - <NUM_LIT> ) , Entry ) ; SwitchInst * SI = IRB . CreateSwitch ( LabelPHI , OrigEntry , SetjmpRetPHIs . size ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < SetjmpRetPHIs . size ( ) ; I ++ ) { SI -> addCase ( IRB . getInt32 ( I + <NUM_LIT> ) , SetjmpRetPHIs [ I ] -> getParent ( ) ) ; SetjmpRetPHIs [ I ] -> addIncoming ( Val , SetjmpDispatchBB ) ; } SmallVector < Instruction * , <NUM_LIT> > ToErase ; for ( auto * BB = & * F . begin ( ) ; BB ; BB = BB -> getNextNode ( ) ) { for ( Instruction & I : * BB ) { auto * CI = dyn_cast < CallInst > ( & I ) ; if ( ! CI ) continue ; const Value * Callee = CI -> getCalledOperand ( ) ; if ( ! canLongjmp ( Callee ) ) continue ; if ( isEmAsmCall ( Callee ) ) report_fatal_error ( <STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> , false ) ; if ( CI == WasmLongjmpCI ) continue ; ToErase . push_back ( CI ) ; CI -> removeFnAttr ( Attribute :: NoUnwind ) ; if ( Function * CalleeF = CI -> getCalledFunction ( ) ) { CalleeF -> removeFnAttr ( Attribute :: NoUnwind ) ; } IRB . SetInsertPoint ( CI ) ; BasicBlock * Tail = SplitBlock ( BB , CI -> getNextNode ( ) ) ; ToErase . push_back ( BB -> getTerminator ( ) ) ; SmallVector < Value * , <NUM_LIT> > Args ( CI -> args ( ) ) ; InvokeInst * II = IRB . CreateInvoke ( CI -> getFunctionType ( ) , CI -> getCalledOperand ( ) , Tail , CatchSwitchBB , Args ) ; II -> takeName ( CI ) ; II -> setDebugLoc ( CI -> getDebugLoc ( ) ) ; II -> setAttributes ( CI ->


<s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , & TM ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames


<s> static void computeKnownBitsBinOp ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth , unsigned OpNo ) { APInt Src0DemE = getDemandedSrcElements ( Op , DemandedElts , OpNo ) ; APInt Src1DemE = getDemandedSrcElements ( Op , DemandedElts


<s> rtx addr , mem ; addr = gen_rtx_PLUS ( Pmode , frame_reg , GEN_INT ( offset ) ) ; mem = gen_frame_mem ( GET_MODE ( reg ) ,


<s> SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ElemSize , dl , <STR_LIT> ) ) ; SDValue EXT = DAG . getNode ( <STR_LIT> , dl , ByteVT , Op0 , Op1


<s> static int mep_multiple_address_regions ( tree list , bool check_section_attr ) { tree a ; int count_sections = <NUM_LIT> ; int section_attr_count = <NUM_LIT> ; for ( a = list ; a ; a


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI


<s> static bool isZIPMask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned NumElts = VT . getVectorNumElements ( ) ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i !=


<s> static inline uint64_t le_short ( const MemoryObject & region , uint64_t address ) { uint8_t bytes [ <NUM_LIT> ] ; int ret = region . readBytes ( address , <NUM_LIT> , ( uint8_t * ) bytes ,


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI


<s> bool isImplicitlyTypedVectorList ( ) const { return Kind == k_VectorList && VectorList . Count == NumRegs && VectorList .

NumElements == <NUM_LIT> && VectorList . RegisterKind == VectorKind ;


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get


<s> if ( ! DisableHardwareLoops ) { addPass ( create<ISA_LIT>HardwareLoops (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSPE2DisEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; uint32_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm ( ) ) ; uint32_t Imm = getMachineOpValue ( MI , MO ,


<s> assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ; return <NUM_LIT> >> get<ISA_LIT>RegisterNumbering ( MO


<s> else { assert ( NextVA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ; MemOpChains . push_back ( LowerMemOpCallTo ( Chain , StackPtr , fmrrd . getValue

( <NUM_LIT> ) , dl , DAG , NextVA , Flags ) ) ;


<s> bool <ISA_LIT>ConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return true


<s> GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx !=


<s> case 'r' : case 'f' : case 'q' : case 'v' : if ( RegName [ <NUM_LIT> ] == 's' ) return RegName + <NUM_LIT> ; return RegName


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> int64_t Result ; if ( <ISA_LIT>Z80Expr -> evaluateAsConstant ( Result ) ) { return Result ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( <ISA_LIT>Z80Expr -> getFixupKind ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , <ISA_LIT>Z80Expr , FixupKind ) ) ; return <NUM_LIT>


<s> return __builtin_arm_crypto_sha256h2 ( __hash_abcd ,


<s> OS << '$' << StringRef ( getRegisterName ( RegNo ) )


<s> HOST_WIDE_INT scale ; addr_space_t seg ; if ( ix86_decompose_address ( addr , & parts ) == <NUM_LIT> ) return false ; base = parts . base ; index = parts . index ; disp = parts . disp ; scale = parts . scale ; seg = parts . seg ; if ( base ) { rtx reg = ix86_validate_address_register ( base ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_BASE_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_BASE_NONSTRICT_P ( reg ) ) ) return false ; } if ( index ) { rtx reg = ix86_validate_address_register ( index ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_INDEX_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P ( reg ) ) ) return false ; } if ( base && index && GET_MODE ( base ) != GET_MODE ( index ) ) return false ; if ( seg != ADDR_SPACE_GENERIC && ( ( base && GET_MODE ( base ) != word_mode ) || ( index && GET_MODE ( index ) != word_mode ) ) ) return false ; if ( scale != <NUM_LIT> ) { if ( ! index ) return false ; if ( scale != <NUM_LIT> && scale != <NUM_LIT> && scale != <NUM_LIT> ) return false ; } if ( disp ) { if ( ix86_endbr_immediate_operand ( disp , VOIDmode ) ) return false ; if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) != UNSPEC_MACHOPIC_OFFSET ) switch ( XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ) { case UNSPEC_GOT : if ( ! TARGET_64BIT && ix86_force_load_from_GOT_p ( XVECEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) ) goto is_legitimate_pic ; case


<s> insn = emit_move_insn ( dest , tempLR ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; } else if ( TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; rtx tempLR = ( fromprolog ? gen_rtx_REG ( Pmode , LINK_REGISTER_REGNUM ) : gen_reg_rtx ( Pmode ) ) ; rtx temp0 = ( fromprolog ? gen_rtx_REG ( Pmode , <NUM_LIT> ) : gen_reg_rtx ( Pmode ) ) ; if ( fromprolog ) { rtx symF , symL ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symF = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symL = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; rs6000_maybe_dead ( emit_insn ( gen_load_toc_v4_PIC_1 ( tempLR , symF ) ) ) ; rs6000_maybe_dead ( emit_move_insn ( dest , tempLR ) ) ; rs6000_maybe_dead ( emit_insn ( gen_load_toc_v4_PIC_2 ( temp0 , dest , symL , symF ) ) ) ; } else { rtx tocsym ; tocsym = gen_rtx_SYMBOL_REF ( Pmode , toc_label_name ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( tempLR , tocsym ) ) ; emit_move_insn ( dest , tempLR ) ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , dest ) ) ; } insn = emit_insn ( gen_addsi3 ( dest , temp0 , dest ) ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; } else if ( TARGET_ELF && ! TARGET_AIX && flag_pic == <NUM_LIT> && TARGET_MINIMAL_TOC ) { char buf [ <NUM_LIT> ] ; rtx realsym ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , <NUM_LIT> ) ; realsym = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; insn = emit_insn ( gen_elf_high ( dest , realsym ) ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; insn = emit_insn ( gen_elf_low ( dest , dest , realsym ) ) ; if ( fromprolog ) rs6000_maybe_dead ( insn ) ; } else { gcc_assert ( DEFAULT_ABI == ABI_AIX ) ; if ( TARGET_32BIT ) insn = emit_insn


<s> SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return


<s> if ( <STR_LIT> . contains ( Reg ) ) { MachineLocation DstML0 ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation DstML1 ( MachineLocation :: VirtualFP , Offset + <NUM_LIT> ) ; MachineLocation SrcML0 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; MachineLocation SrcML1 ( RegInfo -> getSubReg ( Reg , <STR_LIT> ) ) ; if ( ! STI . isLittle ( ) ) std :: swap ( SrcML0 , SrcML1 ) ; Moves . push_back ( MachineMove ( CSLabel , DstML0 , SrcML0 ) ) ; Moves . push_back ( MachineMove ( CSLabel , DstML1 , SrcML1 ) ) ; } else { DstML = MachineLocation ( MachineLocation :: VirtualFP , Offset ) ; SrcML = MachineLocation ( Reg ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; } } } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { if ( ! MBB . isLiveIn ( ehDataReg ( I ) ) ) MBB . addLiveIn ( ehDataReg ( I ) ) ; TII . storeRegToStackSlot ( MBB , MBBI , ehDataReg ( I ) , false , <ISA_LIT>FI -> getEhDataRegFI ( I ) , RC , RegInfo ) ; } MCSymbol * CSLabel2 = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel2 ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( <ISA_LIT>FI -> getEhDataRegFI ( I ) ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP , Offset ) ; SrcML = MachineLocation ( ehDataReg ( I ) ) ; Moves . push_back ( MachineMove ( CSLabel2 , DstML , SrcML ) ) ; } } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( ADDu ) , FP ) . addReg ( SP ) . addReg ( ZERO ) ; MCSymbol * SetFPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( SetFPLabel ) ; DstML = MachineLocation ( FP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP ) ; Moves . push_back ( MachineMove ( SetFPLabel , DstML , SrcML )


<s> auto Rdx = DAG . getNode ( Op , DL , VecOp . getSimpleValueType ( ) , VecOp ) ; return DAG . getNode ( <STR_LIT> , DL , ScalarOp . getValueType ( )

, Rdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> bool isMemOffs16 ( ) const { return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT>

&& ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , DB ? DB -> Name : <STR_LIT> , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! DB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Mnemonic == <STR_LIT> && DB -> Encoding != <STR_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( DB -> Encoding , Tok .

getString ( ) , getLoc ( ) , getContext ( ) ) ) ;


<s> for ( const char * Name = V -> getNameStart ( ) , * E = Name + V -> getNameLen ( ) ; Name != E ; ++ Name ) if ( isprint ( * Name ) ) OS <<


<s> addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_128RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_32RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_32RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: SReg_64RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: SCCRegRegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VCCRegRegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: SReg_128RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: SReg_256RegClass ) ; computeRegisterProperties ( ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> static Align getPrefTypeAlign ( EVT VT , SelectionDAG &


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ) ; if ( ! IsConstantImm


<s> case <STR_LIT> : if ( TLSBaseAddrReg ) I = ReplaceTLSBaseAddrCall ( * I , TLSBaseAddrReg ) ; else I = SetRegister ( * I , & TLSBaseAddrReg ) ; Changed = true ; break ; default : break ; } } for ( auto I = Node -> begin ( ) , E = Node -> end ( ) ; I != E ; ++ I ) { Changed |= VisitNode ( *


<s> static SDValue LowerToTLSGeneralDynamicModel32 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const MVT PtrVT ) { SDValue InFlag ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , InFlag ) ; InFlag = Chain . getValue


<s> BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumBlocks ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes ( MI ) ; ++ MI ; } skipNonTerminators ( Position , Block ) ; while ( MI != End ) { if ( ! MI -> isDebugValue ( ) ) { assert ( MI -> isTerminator ( ) && <STR_LIT> ) ; Terminators . push_back ( describeTerminator ( MI ) ) ; skipTerminator ( Position , Terminators . back (


<s> bool GCNTTIImpl :: isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned


<s> default : return false ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> , true ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> , true ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> , true ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert16i16to16ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert32i32to32ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : return convert64i32to64ri8 ( Inst , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( <STR_LIT> ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) || ! <STR_LIT> ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; unsigned NewOpc ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ;


<s> LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN

-> getMemOperand ( ) -> getFlags ( ) ) ;


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_int4 ) ( a ) , vec_splat ( ( vec_int4 ) ( si_from_int


<s> SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant (


<s> if ( ! new_tree && old_tree ) new_tree = target_option_default_node ; if ( old_tree == new_tree ) return ; aarch64_previous_fndecl = fndecl ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION (


<s> std :: string HexString = utohexstr ( AI . getLimitedValue ( ) , true ) ; unsigned Size = HexString . size


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) , Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue MaskedShamt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeftLo2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , MaskedShamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo2 , Or ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , DL


<s> bool isVecListTwoDByteIndexed ( ) const { if ( ! isSingleSpacedVectorIndexed ( )


<s> if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; FastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; FastEmitBranch ( Target ,


<s> if ( KillsOp0 ) { moveToTop ( Op0 , I ) ; TOS = Op0 ; } else if ( KillsOp1 ) { moveToTop ( Op1 , I ) ; TOS = Op1 ; } else { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } } else if ( ! KillsOp0 && ! KillsOp1 ) { duplicateToTop ( Op0 , Dest , I ) ; Op0 = TOS = Dest ; KillsOp0 = true ; } assert ( ( TOS == Op0 || TOS == Op1 ) && ( KillsOp0 || KillsOp1 ) && <STR_LIT> ) ; ArrayRef < TableEntry > InstTable ; bool isForward = TOS == Op0 ; bool updateST0 = ( TOS == Op0 && ! KillsOp1 ) || ( TOS == Op1 && ! KillsOp0 ) ; if ( updateST0 ) { if ( isForward ) InstTable = ForwardST0Table ; else InstTable = ReverseST0Table ; } else { if ( isForward ) InstTable = ForwardSTiTable


<s> <STR_LIT> ExtraCC ; changeFPCCTo<ISA_LIT>CC ( CC , OutCC , ExtraCC ) ; if ( ExtraCC != <STR_LIT> ) { SDValue ExtraCmp ; if ( ! CCOp . getNode ( ) ) ExtraCmp = emitComparison ( LHS , RHS , CC , DL , DAG ) ; else { SDValue ConditionOp = DAG . getConstant ( Condition , DL , MVT_CC ) ; unsigned NZCV = <STR_LIT> ( ExtraCC ) ; ExtraCmp = emitConditionalComparison ( LHS , RHS , CC , CCOp , ConditionOp , NZCV , DL , DAG ) ; } CCOp = ExtraCmp ; Condition = <STR_LIT> ( ExtraCC ) ; OutCC = <STR_LIT> ( OutCC ) ; } } if ( ! CCOp . getNode ( ) ) return emitComparison ( LHS , RHS , CC , DL , DAG ) ; SDValue ConditionOp = DAG . getConstant ( Condition , DL , MVT_CC ) ; <STR_LIT> InvOutCC = <STR_LIT> ( OutCC ) ; unsigned NZCV = <STR_LIT> ( InvOutCC ) ; return emitConditionalComparison ( LHS , RHS , CC , CCOp , ConditionOp , NZCV , DL , DAG ) ; } SDValue LHS = Val -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; bool isOr = Val -> getOpcode ( ) == <STR_LIT> ; assert ( ( isOr || Val -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; Negate ^= isOr


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl (


<s> return ( ( GET_CODE ( x ) == LABEL_REF ) || ( GET_CODE ( x ) == SYMBOL_REF ) || GET_CODE ( x ) == CONST_INT || ( GET_CODE ( x ) ==

CONST && ! ( flag_pic && pic_address_needs_scratch ( x ) ) ) ) ;


<s> return ( __mmask64 ) __builtin_ia32_ucmpb512_mask ( ( __v64qi ) __X , ( __v64qi )


<s> const char * rwro = ( flags & SECTION_WRITE ) ? <STR_LIT> : <STR_LIT> ; const char * insdat = ( flags & SECTION_CODE ) ? <STR_LIT> : <STR_LIT> ; gcc_assert ( TARGET_DEC_ASM ) ; fprintf ( asm_out_file , <STR_LIT> , name , insdat , rwro


<s> unsigned getCurrGroupSize ( ) { return CurrGroupSize


<s> unsigned Res0 = MRI -> createVirtualRegister ( RC ) ; unsigned Res1 = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( AddOpc ) , Res0 ) . addReg ( Op1 , <NUM_LIT> , <STR_LIT> ) . addReg ( Op2 , <NUM_LIT> , <STR_LIT> ) . addImm ( Type ) . addImm ( <NUM_LIT> ) . addReg ( Res0 , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( AddOpc ) , Res1 ) . addReg ( Op1 , <NUM_LIT> , <STR_LIT> ) . addReg ( Op2 , <NUM_LIT> , <STR_LIT> ) . addImm ( Type ) . addImm ( <NUM_LIT> ) . addReg ( Res1 , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , Res ) . addReg ( Res0 ) . addImm ( <STR_LIT> ) . addReg


<s> virtual unsigned getFunctionAlignment ( const Function *


<s> Target & llvm :: getThe<ISA_LIT>Target (


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1

, ArrayRef < MachineOperand > Pred2 ) const {


<s> bool <ISA_LIT>DAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) { auto * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C && ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) || C -> getSExtValue ( ) == <STR_LIT> ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; else VL = N ; return true


( BUFFER_LOAD_FORMAT ) case <STR_LIT> : break ;


<s> if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; ++ OpIdx ; return


<s> SDValue <ISA_LIT>TargetLowering :: lowerSin ( SDValue Op , SelectionDAG & DAG ) const { return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , Op , DAG


<s> void abort_with_error ( const char * reason ) { error ( reason


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo ) const { const MCOperand & RegMO = MI . getOperand ( OpNo ) . isReg ( ) ? MI . getOperand ( OpNo ) : MI . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand & OffsetMO = MI . getOperand ( OpNo ) . isImm ( ) ? MI . getOperand (


<s> unsigned <ISA_LIT>InstrInfo :: getMachineOutlinerMBBFlags ( MachineBasicBlock & MBB ) const { unsigned Flags = <NUM_LIT> ; if ( std :: any_of ( MBB . begin ( ) , MBB . end ( ) , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) Flags |= MachineOutlinerMBBFlags :: HasCalls ; LiveRegUnits LRU ( getRegisterInfo ( )


<s> inline bool isImmUnsignedi4Value ( uint64_t Value ) { return isUInt < <NUM_LIT> > ( Value


<s> void <ISA_LIT>DbgInfo :: EmitFileDirective ( Module & M ) { GlobalVariable * CU = M . getNamedGlobal ( <STR_LIT> ) ; if ( CU ) { DICompileUnit DIUnit ( CU ) ; std :: string Dir , FN ; O << <STR_LIT> << DIUnit . getDirectory ( Dir ) << <STR_LIT> << DIUnit .


<s> void <ISA_LIT>CodeEmitter :: emitExternalSymbolAddress ( const char * ES , unsigned Reloc ) { MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc ,


<s> RestMBB -> transferSuccessors ( & MBB ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) RestMBB -> addLiveIn ( * I ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MoveMBB -> addLiveIn ( * I ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid ) . addMBB ( RestMBB ) ; MBB . addSuccessor ( RestMBB


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm (


<s> case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT>


<s> const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB -> getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { if ( auto Imm = getFoldableImm ( Src2 ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( auto Imm = getFoldableImm ( Src1 ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; } if ( auto Imm =


<s> int size ; char * buf ; if ( symtab -> state != PARSING ) return ; size = strlen ( string ) + <NUM_LIT> ; if ( size <= microblaze_section_threshold ) section_asm_op = SDATA2_SECTION_ASM_OP ; else section_asm_op = READONLY_DATA_SECTION_ASM_OP ; buf = ACONCAT ( ( section_asm_op , <STR_LIT> , string , <STR_LIT> ,


<s> if ( Op0 . isUndef ( ) && Op1 . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; if ( Op0 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; else if ( Op1 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL ,


<s> AggBuffer ( unsigned _size , raw_ostream & _O , <ISA_LIT>AsmPrinter & _AP ) : size ( _size ) , buffer ( _size ) ,


<s> if ( OpSize == <NUM_LIT> ) { switch ( GenericOpc ) { case TargetOpcode :: G_SHL : return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; default : return GenericOpc ; } } else if ( OpSize == <NUM_LIT> ) { switch ( GenericOpc ) { case TargetOpcode :: G_GEP : return <STR_LIT> ; case TargetOpcode :: G_SHL : return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; default : return GenericOpc ; } } case <STR_LIT> : switch ( OpSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT>


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign ( DirectiveID .


<s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF & Mask , TF


<s> return ( __m256d ) __builtin_ia32_blendpd256 ( ( __v4df ) __X ,


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>_32TargetMachine > X ( The<ISA_LIT>_32Target ) ; RegisterTargetMachine < <ISA_LIT>_64TargetMachine > Y ( The<ISA_LIT>_64Target ) ; RegisterAsmInfoFn A ( The<ISA_LIT>_32Target , createTargetAsmInfo ) ; RegisterAsmInfoFn B ( The<ISA_LIT>_64Target ,


<s> StringRef getPassName ( ) const override { return


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target (


<s> return ( ST == <STR_LIT> || ST == <STR_LIT> || ST == <STR_LIT> ) && getShiftExtendAmount (


<s> EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { if ( V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V2 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( V2 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( SVOp -> getMaskElt ( i + NumElems / <NUM_LIT> ) , NumElems ) ) return SDValue ( ) ; if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> )


<s> } MachineBasicBlock * Dispatch = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , Dispatch ) ; Blocks . insert ( Dispatch ) ; const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( Dispatch , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( Reg ) ; DenseMap < MachineBasicBlock * , unsigned > Indices ; for ( auto * Entry : SortedEntries ) { auto Pair = Indices . insert ( std :: make_pair ( Entry , <NUM_LIT> ) ) ; assert ( Pair . second ) ; unsigned Index = MIB . getInstr ( ) -> getNumExplicitOperands ( ) - <NUM_LIT> ; Pair . first -> second = Index ; MIB . addMBB ( Entry ) ; Dispatch -> addSuccessor ( Entry ) ; } BlockVector AllPreds ; for ( auto * Entry : SortedEntries ) { for ( auto * Pred : Entry -> predecessors ( ) ) { if ( Pred != Dispatch ) { AllPreds . push_back ( Pred ) ; } } } DenseSet < MachineBasicBlock * > InLoop ; for ( auto * Pred : AllPreds ) { for ( auto * Entry : Pred -> successors ( ) ) { if ( ! Entries . count ( Entry ) ) continue ; if ( Graph . canReach ( Entry , Pred ) ) { InLoop . insert ( Pred ) ; break ; } } } DenseMap < PointerIntPair < MachineBasicBlock * , <NUM_LIT> , bool > , MachineBasicBlock * > EntryToLayoutPred ; for ( auto * Pred : AllPreds ) { bool PredInLoop = InLoop . count ( Pred ) ; for ( auto * Entry : Pred -> successors ( ) ) if ( Entries . count ( Entry ) && Pred -> isLayoutSuccessor ( Entry ) ) EntryToLayoutPred [ { Entry , PredInLoop } ] = Pred ; } DenseMap < PointerIntPair < MachineBasicBlock * , <NUM_LIT> , bool > , MachineBasicBlock * > Map ; for ( auto * Pred : AllPreds ) { bool PredInLoop = InLoop . count ( Pred ) ; for ( auto * Entry : Pred -> successors ( ) ) { if ( ! Entries . count ( Entry ) || Map . count ( { Entry , PredInLoop } ) ) continue ; if ( auto * OtherPred = EntryToLayoutPred . lookup ( { Entry , PredInLoop } ) ) if ( OtherPred != Pred ) continue ; MachineBasicBlock * Routing = MF . CreateMachineBasicBlock ( ) ; MF . insert ( Pred -> isLayoutSuccessor ( Entry ) ? MachineFunction :: iterator ( Entry ) : MF . end ( ) , Routing ) ; Blocks . insert (


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const { return new <ISA_LIT>LinuxTargetAsmInfo ( * this


<s> if ( DL . isFatPointer ( PointerTy ) && ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) && ( isa < AtomicRMWInst > ( AI ) || isa < AtomicCmpXchgInst > (


<s> static DecodeStatus DecodeBlezGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { llvm_unreachable ( <STR_LIT> ) ; return MCDisassembler :: Success


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) .


<s> static ALFWriter * createALFWriter ( const MCInstrInfo * mii , const MCRegisterInfo * mri ) { return new <ISA_LIT>ALFWriter ( mii


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressBase ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base . Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT>


<s> bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc


<s> if ( ! ( MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) ) return None ; if ( MI -> getNumMemOperands ( ) == <NUM_LIT> ) return <ISA_LIT>MemOpInfo ( SyncScope :: System , AtomicOrdering :: SequentiallyConsistent ) ; return <ISA_LIT>MemOpInfo :: constructFromMIWithMMO ( MI