<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { StringRef lookahead = getLexer ( ) . getTok ( ) . getString ( ) ; if ( ! lookahead . equals_lower ( <STR_LIT> ) ) { return MatchOperand_NoMatch ; } if ( MaxBits != <NUM_LIT> || OpIsVector ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getLexer ( ) . Lex ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: LParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getLexer ( ) . Lex ( ) ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: RParen ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getLexer ( ) . Lex ( ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * SymExpr = MCSymbolRefExpr :: create ( Sym , getContext ( ) ) ; Offset = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT , SymExpr , getContext ( ) ) ; } else if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: Plus ) ) { if ( Parser . parseExpression ( Offset ) ) return MatchOperand_ParseFail ; int MaxVal = <NUM_LIT> >> ( <NUM_LIT> - MaxBits ) ; int MinVal = <NUM_LIT> << ( MaxBits - <NUM_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Offset ) ; if ( ! CE || CE -> getValue ( ) > MaxVal || CE -> getValue ( ) < MinVal ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } if ( ! getLexer ( ) . is ( AsmToken :: LParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getLexer ( ) . Lex ( ) ; unsigned RegNo ; SMLoc _S , _E


<s> bool isMemMode5 ( ) const { if ( ! isMemory ( ) || Mem . OffsetIsReg || Mem . OffsetRegShifted || Mem . Writeback || Mem . Negative ) return false ; if ( ! Mem . Offset ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem


<s> int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } } return Changed


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat


<s> if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; unsigned char GVFlags = <ISA_LIT>SubTarget -> classifyGlobalReference


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget * Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto * Regs = Subtarget -> getSpecialRegisters ( ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error (


<s> SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; unsigned DWordOffset0 = C1 -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isDSOffsetLegal ( N0 , DWordOffset1 , <NUM_LIT> ) ) { Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned DWordOffset0 = C -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isUInt < <NUM_LIT> > ( DWordOffset0 ) ) { SDLoc DL ( Addr ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , DWordOffset1 , <NUM_LIT> ) ) { MachineSDNode * MachineSub = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { unsigned DWordOffset0 = CAddr -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; assert ( <NUM_LIT> * DWordOffset0 == CAddr -> getZExtValue ( ) ) ; if ( isUInt < <NUM_LIT> > ( DWordOffset0 ) && isUInt < <NUM_LIT> > ( DWordOffset1 ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; } } Base = Addr ; Offset0 = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return


<s> void setFeatures ( const FeatureBitset &


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> ,


<s> for ( size_t I = <NUM_LIT> , E = SortedIntervals . size ( ) ; I < E ; ++ I ) { LiveInterval * LI = SortedIntervals [ I ] ; unsigned Old = LI -> reg ; size_t Color = I ; const TargetRegisterClass * RC = MRI -> getRegClass ( Old ) ; if ( ! MRI -> isLiveIn ( Old ) ) for ( unsigned C : UsedColors . set_bits ( ) ) { if ( MRI -> getRegClass ( SortedIntervals [ C ] -> reg ) != RC ) continue ; for ( LiveInterval * OtherLI : Assignments [ C ] ) if ( ! OtherLI -> empty ( ) && OtherLI -> overlaps ( * LI ) ) goto continue_outer ; Color = C ; break ; continue_outer : ; } unsigned New = SortedIntervals [ Color ] -> reg ; SlotMapping [ I ] = New ; Changed |= Old != New ; UsedColors . set ( Color ) ; Assignments [ Color ] . push_back ( LI ) ; if ( Old != New && MFI . isFrameBaseVirtual ( ) && MFI . getFrameBaseVreg ( ) == Old ) MFI . setFrameBaseVreg ( New ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Register :: virtReg2Index ( LI -> reg ) << <STR_LIT> << Register ::


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> if ( ! lra_in_progress && ! reload_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < <NUM_LIT> || regno >= FIRST_PSEUDO_REGISTER ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= <NUM_LIT> ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ ( int ) rclass


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t


<s> HOST_WIDE_INT mask = GET_MODE_MASK ( mode ) ; HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( VOIDmode , dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == <NUM_LIT> ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET (


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; AlignmentIsInBytes = false ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; DwarfRegNumForCFI = true ; ExceptionsType = ExceptionHandling ::


<s> if ( Size >= Bytes . size ( ) ) return - <NUM_LIT> ; auto V = Bytes [ Size


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( need_to_save ( i * <NUM_LIT> ) || need_to_save ( i * <NUM_LIT> + <NUM_LIT> ) ) { cfun -> machine -> need_to_push [ i ] = <NUM_LIT> ; cfun -> machine -> framesize_regs += <NUM_LIT> ; } else cfun -> machine -> need_to_push [ i ] =


<s> static bool jumpTableFollowsTB ( MachineInstr * JTMI , MachineInstr * CPEMI ) { MachineFunction :: iterator MBB = JTMI -> getParent ( ) -> getIterator ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; ++ MBB ; return MBB != MF -> end ( ) && MBB -> begin ( ) != MBB -> end


<s> return expandUnalignedStore ( Store , DAG ) ; } unsigned AS = Store -> getAddressSpace ( ) ; if ( Subtarget -> hasLDSMisalignedBug ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS && Store -> getAlignment ( ) < VT . getStoreSize ( ) && VT . getSizeInBits ( ) > <NUM_LIT> ) { return SplitVectorStore ( Op , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS && ! Subtarget -> hasMultiDwordFlatScratchAddressing ( ) ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> || NumElements == <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue (


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> MF = & Func ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; SubregInstrs . clear


<s> getParser ( ) . getStreamer ( ) . emitTPRel64Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer (


<s> <STR_LIT> llvm :: getVPTInstrPredicate ( const MachineInstr & MI , Register & PredReg ) { int PIdx = findFirstVPTPredOperandIdx ( MI ) ; if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; } PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> ) MI . getOperand ( PIdx ) .


<s> if ( UA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) return false ; NodeAddr < RefNode * > AA = LV -> getNearestAliasedRef ( OffsetRR , IA ) ; if ( ( DFG -> IsDef ( AA ) && AA . Id != OffsetRegRD ) || AA . Addr -> getReachingDef ( ) != OffsetRegRD ) return false ; MachineInstr & UseMI = * NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; NodeAddr < DefNode * > OffsetRegDN = DFG -> addr < DefNode * > ( OffsetRegRD ) ; if ( ( OffsetRegDN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && MI . getParent ( ) != UseMI . getParent ( ) ) return false ; const MCInstrDesc & UseMID = UseMI .


<s> section = buf ; } switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( TARGET_RELOCATABLE ) { fputs ( <STR_LIT> ,


<s> unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent


<s> const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { ClauseInfo CI ; for ( auto & MI : MBB ) { HardClauseType Type = getHardClauseType ( MI ) ; int64_t Dummy1 ; bool Dummy2 ; SmallVector < const MachineOperand * , <NUM_LIT> > BaseOps ; if ( Type <= LAST_REAL_HARDCLAUSE_TYPE ) { if ( ! <ISA_LIT>I -> getMemOperandsWithOffset ( MI , BaseOps , Dummy1 , Dummy2 , TRI ) ) { Type = HARDCLAUSE_ILLEGAL ; } } if ( CI . Length == <NUM_LIT> || ( CI . Length && Type != HARDCLAUSE_INTERNAL && ( Type != CI . Type || ! <ISA_LIT>I -> shouldClusterMemOps ( CI . BaseOps , BaseOps , <NUM_LIT> ) ) ) ) { Changed |= emitClause ( CI , <ISA_LIT>I ) ; CI = ClauseInfo ( ) ; } if ( CI . Length ) { ++ CI . Length ; if ( Type != HARDCLAUSE_INTERNAL ) { CI . Last = & MI ; CI . BaseOps = std :: move (


<s> uint8_t get_ratio ( ) const { return m_ratio


<s> auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg


<s> ( isThumb1 && Offset < <NUM_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> && Base != <STR_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; } if ( ! TL -> isLegalAddImmediate ( Offset ) ) return nullptr ; bool KillOldBase = BaseKill && ( ! isi32Store ( Opcode ) || ! ContainsReg ( Regs , Base ) ) ; if ( isThumb1 ) { if ( Base != NewBase && ( BaseOpc == <STR_LIT> || BaseOpc == <STR_LIT> ) ) { if ( is<ISA_LIT>LowRegister ( NewBase ) && is<ISA_LIT>LowRegister ( Base ) && ! STI -> hasV6Ops ( ) ) { if ( Pred != <STR_LIT> ) return nullptr ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) ; } else BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . add ( predOps ( Pred , PredReg ) ) ; Base = NewBase ; KillOldBase = true ; } if ( BaseOpc == <STR_LIT> ) { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset / <NUM_LIT> ) . add ( predOps ( Pred , PredReg ) ) ; } else BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . add ( t1CondCodeOp ( true ) ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . add ( predOps ( Pred , PredReg ) ) ; } else { BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) ; } Base = NewBase ; BaseKill = true ; } bool isDef = isLoadSingle ( Opcode ) ; Opcode = getLoadStoreMultipleOpcode ( Opcode , Mode ) ; if ( ! Opcode ) return nullptr ; if ( isThumb1 && ! SafeToClobberCPSR && Writeback && ! BaseKill ) return nullptr ; MachineInstrBuilder MIB ; if ( Writeback ) { assert ( isThumb1 && <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { assert ( ! ( ContainsReg ( Regs , Base ) ) && <STR_LIT> ) ; Opcode = <STR_LIT> ; } MIB = BuildMI ( MBB , InsertBefore , DL , TII ->


<s> if ( src_code == CONST_INT ) { if ( SMALL_OPERAND ( INTVAL ( src ) ) || LUI_OPERAND ( INTVAL ( src ) ) ) return <STR_LIT> ; if ( TARGET_ZBS && SINGLE_BIT_MASK_OPERAND ( INTVAL ( src ) ) ) return <STR_LIT> ; abort ( ) ; } if ( src_code == HIGH ) return <STR_LIT> ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return <STR_LIT> ; case SYMBOL_ABSOLUTE : return <STR_LIT> ; case SYMBOL_PCREL : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> :


<s> bool supportsEfficientVectorElementLoadStore ( ) { return


<s> EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; EVT PtrVT = <STR_LIT> ( DAG . getDataLayout ( ) . getPointerSizeInBits ( <NUM_LIT> ) ) ; uint64_t SlotSize = ValVT . getSizeInBits ( ) / MF . getDataLayout ( ) . getBitsPerMemoryUnit ( ) ; int FI = MFI . CreateFixedObject ( SlotSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign ::


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned inc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder


<s> if ( CM == CodeModel :: JITDefault ) RM = Reloc :: Static ; else if ( RM == Reloc :: Default ) RM = Reloc :: PIC_ ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X


<s> return GV != <NUM_LIT> || CP != <NUM_LIT> || ES != <NUM_LIT> || JT !=


<s> if ( GET_CODE ( val ) != REG && GET_CODE ( val ) != CONST_INT ) val = copy_to_mode_reg ( QImode , val ) ; if ( GET_CODE ( out ) != REG ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , <NUM_LIT> ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , <NUM_LIT> ) ; if ( GET_CODE ( val ) != CONST_INT ) val = simplify_gen_subreg ( HImode , val , QImode , <NUM_LIT> ) ; emit_insn ( gen_andhi3 ( outsub , in , val ) ) ; if ( out != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [


<s> return ( __m256d ) __builtin_ia32_loadupd256_mask ( ( const double * ) __P , ( __v4df ) __W ,


<s> static bool classof ( const PseudoSourceValue * V


<s> addPass ( & EarlyIfConverterID ) ; return


<s> first_v = node_v ; while ( first_v -> prev != NULL ) first_v = first_v -> prev ; default_version_info = first_v ; while ( default_version_info != NULL ) { if ( is_function_default_version ( default_version_info -> this_node -> decl ) ) break ; default_version_info = default_version_info -> next ; } if ( default_version_info == NULL ) return NULL ; if ( first_v != default_version_info ) { default_version_info -> prev -> next = default_version_info -> next ; if ( default_version_info -> next ) default_version_info -> next -> prev = default_version_info -> prev ; first_v -> prev = default_version_info ; default_version_info -> next = first_v ; default_version_info -> prev = NULL ; } default_node = default_version_info -> this_node ; if ( targetm . has_ifunc_p ( ) ) { struct cgraph_function_version_info * it_v = NULL ; struct cgraph_node * dispatcher_node = NULL ; struct cgraph_function_version_info * dispatcher_version_info = NULL ; dispatch_decl = make_dispatcher_decl ( default_node -> decl ) ; dispatcher_node = cgraph_node :: get_create ( dispatch_decl ) ; gcc_assert ( dispatcher_node != NULL ) ; dispatcher_node -> dispatcher_function = <NUM_LIT> ; dispatcher_version_info = dispatcher_node -> insert_new_function_version ( ) ; dispatcher_version_info -> next =


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> if ( pred == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode


<s> TotalPackets ++ ; return false ; } if ( ! isResourceAvailable ( SU ) ) { ResourcesModel -> clearResources ( ) ; savePacket ( ) ; Packet . clear ( ) ; TotalPackets ++ ; startNewCycle = true ; } if ( ! SU -> getInstr ( ) -> isPseudo ( ) ) { ResourcesModel -> reserveResources ( * SU -> getInstr ( ) ) ; Packet . push_back ( SU ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalPackets << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << Packet [ i


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBitfieldInvertedMaskOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = countTrailingZeros ( v ) ; uint32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; assert ( v != <NUM_LIT> && lsb < <NUM_LIT>


<s> BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Idx ) ; } MBB . insert ( I , MovRel ) ; } else { assert ( <STR_LIT> . contains ( Save ) ) ; assert ( <STR_LIT> . contains ( Idx ) ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Save ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Idx ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Idx ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; if ( Offset ) { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Offset ) ; } MBB . insert ( I , MovRel ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) .

addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( TargetRegisterClass :: iterator I = <STR_LIT> . begin ( ) , E = <STR_LIT> . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } TII -> reserveIndirectRegisters ( Reserved ,


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * PtrAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Root . getReg ( ) , MRI ) ; if ( ! PtrAdd || ! isWorthFoldingIntoExtendedReg ( * PtrAdd , MRI ) ) return None ; MachineOperand & LHS = PtrAdd -> getOperand ( <NUM_LIT> ) ; MachineOperand & RHS = PtrAdd -> getOperand ( <NUM_LIT> ) ; MachineInstr * OffsetInst = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ; auto ExtendedShl = selectExtendedSHL ( Root , LHS , OffsetInst

-> getOperand ( <NUM_LIT> ) , SizeInBytes , true ) ;


<s> SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue Div = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , VT ) , Quotient , Quotient_A_One , <STR_LIT> ) ; Div = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , VT ) , Quotient_S_One , Div , <STR_LIT> ) ; SDValue Remainder_S_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Remainder_A_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Rem = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , VT ) , Remainder , Remainder_S_Den , <STR_LIT> ) ; Rem = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , VT ) , Remainder_A_Den , Rem , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] ; Ops [ <NUM_LIT> ] = Div ; Ops [ <NUM_LIT> ]


<s> if ( SelectBrevLdIntrinsic ( N ) ) return ; if ( SelectNewCircIntrinsic ( N ) ) return ; unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { SelectV65Gather ( N ) ; return ; } if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { SelectV65GatherPred ( N


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isN64 ( ) ) return DecodeGPR64RegisterClass ( Inst , RegNo


<s> } else if ( Fixup . getKind ( ) == MCFixupKind ( <STR_LIT> ) ) { assert ( Value != <NUM_LIT> && <STR_LIT> ) ; if ( ( Value & <NUM_LIT> ) != Value ) { report_fatal_error ( <STR_LIT> ) ; } unsigned InstrSize = <ISA_LIT>II :: InstructionSize ; int RelOffset = ( Value & <NUM_LIT> ) - <ISA_LIT>II :: InstructionSize / <NUM_LIT> ; LLVM_DEBUG ( fprintf ( stderr , <STR_LIT> , Offset , RelOffset , ( Data [ Offset ] & <NUM_LIT> ) ) ; ) ; APInt Instruction ( <ISA_LIT>II :: InstructionSize , ArrayRef < uint64_t > ( ( uint64_t * ) ( & Data [ Offset ] ) , <ISA_LIT>II :: InstructionSize / <NUM_LIT> ) ) ; APInt ImmSlot ( <ISA_LIT>II :: ImmSize , RelOffset ) ; Instruction |= ImmSlot . zext ( <ISA_LIT>II :: InstructionSize ) . shl ( <ISA_LIT>II :: LoopOffsetStart ) ; const char * RawInstrucion = ( const char * ) Instruction . getRawData ( ) ; for ( unsigned i = <NUM_LIT> ; i < InstrSize / <NUM_LIT>


<s> return PR_REGNUM_P ( regno ) || regno == FFR_REGNUM || regno ==


<s> bool andOp = false ; if ( base -> getOpcode ( ) == Instruction :: Shl ) { shift = dyn_cast < Constant > ( base -> getOperand ( <NUM_LIT> ) ) ; } else if ( base -> getOpcode ( ) == Instruction :: And ) { mask = dyn_cast < Constant > ( base -> getOperand ( <NUM_LIT> ) ) ; andOp = true ; } else { if ( mDebug ) { dbgs ( ) << <STR_LIT> ; } return false ; } src = dyn_cast < Instruction > ( base -> getOperand ( <NUM_LIT> ) ) ; if ( ! src ) { if ( mDebug ) { dbgs ( ) << <STR_LIT> ; } return false ; } if ( andOp


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit ) , TT , CPU , FS , Options

, Reloc :: PIC_ , CM , OL ) , is64bit ( is64bit ) , TLOF ( llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> static bool isMOVLHPSMask ( ArrayRef < int > Mask , EVT VT ) { if ( ! VT . is128BitVector ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if (

! isUndefOrEqual ( Mask [ i + e ] , i + NumElems ) ) return false ;


<s> if ( Imm & ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) ) Imm |= ~ ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> SetCC = Intr ; Intr = SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ; } else { BR = findUser ( BRCOND , <STR_LIT> ) ; Target = BR -> getOperand ( <NUM_LIT> ) ; } unsigned CFNode = isCFIntrinsic ( Intr ) ; if ( CFNode == <NUM_LIT> ) { return BRCOND ; } bool HaveChain = Intr -> getOpcode ( ) == <STR_LIT> || Intr -> getOpcode ( ) == <STR_LIT> ; assert ( ! SetCC || ( SetCC -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && cast < CondCodeSDNode > ( SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> get ( ) == <STR_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HaveChain ) Ops . push_back ( BRCOND . getOperand ( <NUM_LIT> ) ) ; Ops . append ( Intr -> op_begin ( ) + ( HaveChain ? <NUM_LIT> : <NUM_LIT> ) , Intr -> op_end ( ) ) ; Ops . push_back ( Target ) ; ArrayRef < EVT > Res ( Intr -> value_begin ( ) + <NUM_LIT> , Intr -> value_end ( ) ) ; SDNode * Result = DAG . getNode ( CFNode , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( ! HaveChain ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; Result = DAG . getMergeValues ( Ops , DL ) . getNode ( ) ; } if ( BR )


<s> MCSymbol * OffsetSym = MF . getMMI ( ) . getContext ( ) . getOrCreateParentFrameOffsetSymbol ( GlobalValue :: dropLLVMManglingEscape ( Fn -> getName ( ) ) ) ; SDValue OffsetSymVal = DAG . getMCSymbol ( OffsetSym , PtrVT ) ; SDValue ParentFrameOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , OffsetSymVal ) ; const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , ParentFrameOffset ) ; int RegNodeSize = getSEHRegistrationNodeSize ( Fn ) ; SDValue RegNodeBase = DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , DAG . getConstant ( RegNodeSize , dl , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl ,

PtrVT , RegNodeBase , ParentFrameOffset ) ;


<s> bool isReg ( ) const { return Kind == k_Register


<s> if ( ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail || getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return ResTy ; bool Negate = false , Abs = false ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { Parser . Lex ( ) ; Negate = true ; } if ( getLexer ( ) . getKind ( ) == AsmToken :: Pipe ) { Parser . Lex ( ) ; Abs = true ; } switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Integer : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) ) return MatchOperand_ParseFail ; APInt IntVal32 ( <NUM_LIT> , IntVal ) ; if ( IntVal32 . getSExtValue ( ) != IntVal ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } IntVal = IntVal32 . getSExtValue ( ) ; if ( Negate ) IntVal *= - <NUM_LIT> ; Operands . push_back ( AMDGPUOperand :: CreateImm ( IntVal , S ) ) ; return MatchOperand_Success ; } case AsmToken :: Real : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) ) return MatchOperand_ParseFail ; APFloat F ( ( float ) BitsToDouble ( IntVal ) ) ; if ( Negate ) F . changeSign ( ) ; Operands . push_back ( AMDGPUOperand :: CreateImm ( F . bitcastToAPInt ( ) . getZExtValue ( ) , S ) ) ; return MatchOperand_Success ; } case AsmToken :: Identifier : { SMLoc S , E ; unsigned RegNo ; if ( ! ParseRegister ( RegNo ,


<s> return __builtin_aarch64_sqrtv2df ( a


<s> static InstrUID decode ( OpcodeType type , InstructionContext insnContext , uint8_t opcode , uint8_t modRM ) { struct ModRMDecision * dec ; switch ( type ) { default : unreachable ( <STR_LIT> ) ; case ONEBYTE : dec = & ONEBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case TWOBYTE : dec = & TWOBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : unreachable ( <STR_LIT> ) ; case MODRM_ONEENTRY


<s> return FI <= InArgFIRange . first && FI >=


<s> if ( auto USatVal = detectUSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( ( VT . getScalarType ( ) == <STR_LIT> && InVT . getScalarType ( ) == <STR_LIT> ) || ( VT . getScalarType ( ) == <STR_LIT> && InVT . getScalarType ( ) == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( Subtarget . hasSSE41 ( ) || VT . getScalarType ( ) == <STR_LIT> ) if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL


<s> const unsigned Mask = <STR_LIT> ; return std :: make_pair ( TF & Mask , TF & ~


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO : return ELF :: R_<ISA_LIT>_GOTPCREL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI : return ELF :: R_<ISA_LIT>_GOTPCREL32_HI ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO : return ELF :: R_<ISA_LIT>_REL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_HI : return ELF :: R_<ISA_LIT>_REL32_HI ; } switch ( Fixup . getKind ( ) ) { default : break ; case FK_PCRel_4 : return ELF ::


<s> emitFrameDirective ( ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask (


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { SDValue V = PerformSHLCombine ( N , DAG ) ; if ( V . getNode ( ) ) return V ; } return SDValue (


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ClearMask . push_back ( i == IdxVal ? i + NumElts : i ) ; SDValue ZeroVector = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getVectorShuffle ( VT , dl , N0 , ZeroVector , ClearMask ) ; } if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget . hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget . hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumEltsIn128 ) ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Opc ; if ( VT == <STR_LIT> ) { Opc =


<s> StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) .


<s> SDValue <ISA_LIT>TargetLowering :: expandIndirectJTBranch ( const SDLoc & dl , SDValue Value , SDValue Addr , SelectionDAG & DAG ) const { const Module * M = DAG . getMachineFunction ( ) . getMMI ( ) . getModule ( ) ; Metadata * IsCFProtectionSupported = M -> getModuleFlag ( <STR_LIT> ) ; if ( IsCFProtectionSupported ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , Addr ) ; } return TargetLowering :: expandIndirectJTBranch ( dl , Value ,


<s> char loop_lab [ <NUM_LIT> ] , end_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ) ; ASM_GENERATE_INTERNAL_LABEL ( end_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = reg2 ; xops [ <NUM_LIT> ] = gen_rtx_REG ( BImode


<s> SDLoc DL ( Op ) ; auto Pg = getPredicateForVector ( DAG , DL , VT ) ; if ( useSVEForFixedLengthVectorVT ( VT , OverrideNEON ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { if ( isa < CondCodeSDNode > ( V ) ) { Operands . push_back ( V ) ; continue ; } if ( const VTSDNode * VTNode = dyn_cast < VTSDNode > ( V ) ) { EVT VTArg = VTNode -> getVT ( ) . getVectorElementType ( ) ; EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( useSVEForFixedLengthVectorVT ( V . getValueType ( ) , OverrideNEON ) && <STR_LIT> ) ; Operands . push_back ( convertToScalableVector ( DAG , ContainerVT , V ) ) ; } if ( isMergePassthruOpcode ( NewOp ) ) Operands . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ( ! V . getValueType ( ) . isVector ( ) ||

V . getValueType ( ) . isScalableVector ( ) ) && <STR_LIT> ) ;


<s> MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister


<s> tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args


__artificial__ ) ) _mm256_bcstnebf16_ps ( const void * __P ) {


<s> void addModImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx


<s> O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ; O << <STR_LIT> << getFunctionNumber (


<s> Range = <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_THUMB_RELOC_BR22 : Value -= <NUM_LIT> ; Range = <NUM_LIT> ; } const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Value += Writer -> getSectionAddress ( & SymSD ) ; Value -= Writer -> getSectionAddress (


<s> unsigned n = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( n ) ) ; status = DecodeOperandRegister ( Inst , s2 ,


<s> static void PrepareTailCall ( SelectionDAG & DAG , SDValue & InFlag , SDValue & Chain , const SDLoc & dl , bool is<ISA_LIT>64 , int SPDiff , unsigned NumBytes , SDValue LROp , SDValue FPOp , bool isDarwinABI , SmallVectorImpl < TailCallArgumentInfo > & TailCallArguments ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < SDValue , <NUM_LIT> > MemOpChains2 ; InFlag = SDValue ( ) ; StoreTailCallArgumentsToStackSlot ( DAG , Chain ,

TailCallArguments , MemOpChains2 , dl ) ;


<s> SMLoc getStartLoc ( ) const override { return StartLoc


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! requiresRegisterScavenging ( MF ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isDarwinABI ( )


<s> unsigned Scale ; int GEPElemSize = BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) ; int ResultElemSize = Ty -> getScalarSizeInBits ( ) ; if ( GEPElemSize == <NUM_LIT> && ResultElemSize == <NUM_LIT> ) { Scale = <NUM_LIT> ; } else if ( GEPElemSize == <NUM_LIT> && ResultElemSize == <NUM_LIT> ) { Scale = <NUM_LIT> ; } else if ( GEPElemSize == <NUM_LIT> ) { Scale = <NUM_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , BasePtr -> getType ( ) , Offsets -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( Ty -> getScalarSizeInBits ( ) )

, Builder . getInt32 ( Scale ) , Builder . getInt32 ( <NUM_LIT> ) , Mask } ) ;


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size ,

Alignment . value ( ) , RTLIB :: MEMMOVE ) ;


<s> if ( cfun -> machine -> is_naked ) { fputs ( <STR_LIT> , file ) ; } else { if ( cfun -> machine -> is_interrupt ) { fputs ( <STR_LIT> , file ) ; } else if ( cfun -> machine -> is_signal ) { fputs ( <STR_LIT> , file ) ; } else fputs ( <STR_LIT> , file ) ; } if ( ACCUMULATE_OUTGOING_ARGS ) fprintf ( file , <STR_LIT> , avr_outgoing_args_size ( ) ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , get_frame_size ( ) ) ; fprintf ( file , <STR_LIT> , cfun -> machine -> stack_usage ) ; fprintf ( file , <STR_LIT> , cfun -> machine ->


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT


<s> unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; assert ( ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) && <STR_LIT> ) ; O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; if ( MO . getOffset ( ) != <NUM_LIT> ) { O << <STR_LIT> ; O << MO . getOffset (


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag )


<s> if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) + INTVAL ( XEXP ( x , <NUM_LIT> ) ) / <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) + ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) - <NUM_LIT> ) / <NUM_LIT> ; } else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ! ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) > <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) <= <NUM_LIT> ) ) { * total = COSTS_N_INSNS ( TARGET_COLDFIRE ? <NUM_LIT> : <NUM_LIT> ) ; return true ; } return false ; case MULT : if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND ) && GET_MODE ( x ) == SImode ) * total = COSTS_N_INSNS ( MULW_COST ) ; else if ( GET_MODE ( x ) == QImode || GET_MODE ( x ) == HImode ) * total = COSTS_N_INSNS ( MULW_COST ) ; else * total = COSTS_N_INSNS ( MULL_COST ) ; return true ; case DIV : case UDIV : case MOD : case UMOD : if ( GET_MODE ( x ) == QImode || GET_MODE ( x ) == HImode ) * total = COSTS_N_INSNS ( DIVW_COST ) ; else if ( TARGET_CF_HWDIV ) * total = COSTS_N_INSNS (


<s> const unsigned FunctionCallDivCost = <NUM_LIT> ; const unsigned ReciprocalDivCost = <NUM_LIT> ; static const CostTblEntry CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; if ( ST -> hasNEON ( )


<s> if ( ( CSKY_TARGET_ARCH ( CK801 ) || CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK803 ) ) && reg > <NUM_LIT> ) break ; if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) save = true ; else if ( frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM ) save = true ; else if ( crtl -> calls_eh_return && reg


<s> if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) return new TargetLoweringObjectFileCOFF ( ) ; llvm_unreachable ( <STR_LIT>


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target )


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = ParseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT>


<s> return ( uint16x8_t ) __builtin_neon_vcgtzv8hf


<s> if ( auto Value = combineADDToADDZE ( N ,

DCI . DAG , Subtarget ) ) return Value ;


<s> if ( cfun -> is_thunk ) return ; fputs ( <STR_LIT> , f


<s> const auto Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; if ( IsMachO ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: EndOfStatement ) ) { if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken :: String ) ) { Error ( L , <STR_LIT> ) ; return false ; } MCSymbol * Func = getParser ( ) . getContext ( ) . GetOrCreateSymbol ( Tok . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Func ) ; Parser . Lex ( ) ; return false ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false


<s> Value * EFLAGSDef = computeEFLAGSForDef ( LastEFLAGSChangingDef , getRegNoCallback ( RegNo ) ) ; setRegValWithName ( RegNo ,


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT>


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_PLT , <STR_LIT> } , { MO_PIC_FLAG , <STR_LIT> } , { MO_NLP_FLAG , <STR_LIT> } , { MO_NLP_HIDDEN_FLAG , <STR_LIT> } } ; return makeArrayRef (


<s> SDValue Data = Op . getOperand ( <NUM_LIT> ) ; VTSDNode * BaseType = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT DVT = Data . getValueType ( ) ; EVT BVT = BaseType -> getVT ( ) ; unsigned baseBits = BVT . getScalarType ( ) . getSizeInBits ( ) ; unsigned srcBits = DVT . isSimple ( ) ? DVT . getScalarType ( ) . getSizeInBits ( ) : <NUM_LIT> ; unsigned shiftBits = srcBits - baseBits ; if ( srcBits < <NUM_LIT> ) { EVT IVT = genIntType ( <NUM_LIT> , DVT . isVector ( ) ? DVT . getVectorNumElements ( ) : <NUM_LIT> ) ; Data = DAG . getNode ( <STR_LIT> , DL , IVT , Data ) ; shiftBits = <NUM_LIT> - baseBits ; DVT = IVT


<s> unsigned SubLo ; const TargetRegisterClass * SuperRC = nullptr ; if ( <STR_LIT> . contains ( LoRegDef ) ) { SuperRC = & <STR_LIT> ; SubLo = <STR_LIT> ; } else if ( <STR_LIT> . contains ( LoRegDef ) ) { assert ( ST -> useHVXOps ( ) ) ; SuperRC = & <STR_LIT> ; SubLo = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , SubLo , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( )


<s> if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ; } if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF


<s> return ( __m128i ) __builtin_ia32_vplzcntd_128_mask ( ( __v4si ) __A , ( __v4si ) _mm_setzero_si128 ( ) ,


<s> CCValAssign & VA = ArgLocs [ I ] ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; Register Reg = VA . getLocReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT>


<s> static SDValue LowerVAARG ( SDValue Op , SelectionDAG & DAG ) { SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = VAListPtr . getValueType ( ) ; const Value * SV = cast < SrcValueSDNode > ( Node

-> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> void <ISA_LIT>SPReduce :: mergeMBBs ( MachineFunction & MF ) { DEBUG ( dbgs ( ) << <STR_LIT> ; MF . dump ( ) ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; RootScope -> dump ( dbgs ( ) , <NUM_LIT> , true ) ; } ) ; std :: vector < MachineBasicBlock * > order ; for ( df_iterator < MachineBasicBlock * > I = df_begin ( & MF . front ( ) ) , E = df_end ( & MF . front ( ) ) ; I != E ; ++ I ) { order . push_back ( * I ) ; } std :: vector < MachineBasicBlock * > :: iterator I = order . begin ( ) , E = order . end ( ) ; MachineBasicBlock * BaseMBB = * I ; auto BaseBlock = RootScope -> findBlockOf ( BaseMBB ) ; DEBUG_TRACE ( dbgs ( ) << <STR_LIT> << BaseMBB -> getNumber ( ) << <STR_LIT> ) ; while ( ++ I != E ) { MachineBasicBlock * MBB = * I ; if ( MBB -> pred_size ( ) == <NUM_LIT> ) { DEBUG_TRACE ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ) ; BaseMBB -> splice ( BaseMBB -> end ( ) , MBB , MBB -> begin ( ) , MBB -> end ( ) ) ; BaseMBB -> removeSuccessor ( MBB ) ; BaseMBB -> transferSuccessors ( MBB ) ; MF . erase ( MBB ) ; auto MBBBlock = RootScope -> findBlockOf ( MBB


<s> if ( c < <NUM_LIT> ) { error ( <STR_LIT> ) ; return NULL_RTX ; } emit_insn ( gen_delay_cycles_start ( arg ) ) ; if ( c > <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) { n = ( c - <NUM_LIT> ) / <NUM_LIT> ; c -= ( n * <NUM_LIT> ) + <NUM_LIT> ; if ( ( unsigned long long ) n > <NUM_LIT> ) { error ( <STR_LIT> ) ; return NULL_RTX ; } emit_insn ( gen_delay_cycles_2x_plus2_si ( GEN_INT ( n ) ) ) ; } if ( c > <NUM_LIT> ) { n = ( c - <NUM_LIT> ) / <NUM_LIT> ; c -= ( n * <NUM_LIT> ) +


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Token . getIntVal ( ) , getContext ( ) . getRegisterInfo ( ) , S , Token . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } DEBUG ( dbgs ( ) << Parser . getTok ( ) . getKind


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << getRegisterName ( MO2 .


<s> DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getValueType ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , GetGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( Op , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo ::

getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> return __builtin_aarch64_reduc_plus_scal_v2sf (


<s> MachineInstr & MovY = * YTop . getParent ( ) ; if ( ( MovY . getOpcode ( ) != <STR_LIT> && MovY . getOpcode ( ) != <STR_LIT> ) || MovY . getOperand ( <NUM_LIT> ) . getSubReg ( ) != Tsub ) continue ; Register Y = MovY . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ysub = MovY . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( ! TRI . isVGPR ( MRI , Y ) || MovT . getParent ( ) != MovY . getParent ( ) ) continue ; MachineInstr * MovX = nullptr ; auto I = std :: next ( MovT . getIterator ( ) ) , E = MovT . getParent ( ) -> instr_end ( ) ; for ( auto IY = MovY . getIterator ( ) ; I != E && I != IY ; ++ I ) { if ( instReadsReg ( & * I , X , Xsub , TRI ) || instModifiesReg ( & * I , Y , Ysub , TRI ) || instModifiesReg ( & * I , T , Tsub , TRI ) || ( MovX && instModifiesReg ( & * I , X , Xsub , TRI ) ) ) { MovX = nullptr ; break ; } if ( ! instReadsReg ( & * I , Y , Ysub , TRI ) ) { if ( ! MovX && instModifiesReg ( & * I , X , Xsub , TRI ) ) { MovX = nullptr ; break ; } continue ; } if ( MovX || ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) || I -> getOperand ( <NUM_LIT> ) . getReg ( ) != X || I -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != Xsub ) { MovX = nullptr ; break ; } MovX = & *


<s> Value = ( ( Value & <NUM_LIT> ) << <NUM_LIT>


<s> static DecodeStatus DecodeThumbTableBranch ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { const FeatureBitset & FeatureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) <= <STR_LIT> ) { addPass ( createAMDGPUIndirectAddressingPass ( * TM ) ) ; } return


<s> if ( regno <= PC_REGNUM ) return CEIL ( GET_MODE_SIZE


<s> return V -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) && V -> getConstantOperandVal ( <NUM_LIT> ) == Lane + <NUM_LIT> ; } ) ; if ( OtherIt == Op0 -> uses ( ) . end ( ) ) return SDValue ( ) ; SDValue OtherExt ( * OtherIt , <NUM_LIT> ) ; if ( OtherExt . getValueType ( ) != <STR_LIT> ) { if ( OtherExt -> use_size ( ) != <NUM_LIT> || OtherExt -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> || OtherExt -> use_begin ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; OtherExt = SDValue ( * OtherExt -> use_begin ( ) , <NUM_LIT> ) ; } SDValue F64 = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DCI . DAG . getConstant ( Ext . getConstantOperandVal ( <NUM_LIT> ) / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VMOVRRD = DCI . DAG . getNode ( <STR_LIT> , dl , {


<s> SPCallSpillOffset = SinglePathFIs . size (


<s> if ( GET_CODE ( op ) == REG ) regno = REGNO ( op ) ; else if ( GET_CODE ( op ) == SUBREG && GET_CODE ( SUBREG_REG ( op ) ) == REG ) { if ( REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) regno = subreg_regno ( op ) ; else regno = REGNO ( SUBREG_REG ( op )


<s> unsigned getLgkmcntBitMask ( const IsaVersion


<s> void <ISA_LIT>MCAsmStreamer :: reset ( ) { LabelToEmit . clear ( ) ; ExplicitCommentToEmit . clear ( ) ; CommentToEmit . clear ( ) ; Symbols . clear ( ) ; CurrentAlignmentToValue =


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) )


<s> } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBasePtrTy = SubVecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { Type * VecTran = VectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) -> getPointerTo ( ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecTran ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; i ++ ) { Value * NewBasePtr = Builder . CreateGEP ( VecBasePtr , Builder . getInt32 ( i ) ) ; Instruction * NewLoad = Builder . CreateAlignedLoad ( NewBasePtr , LI


<s> unsigned getTileConfigSize ( ) const


<s> void addT2SOImmNegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> InstructionCost <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , CmpInst :: Predicate VecPred , TTI :: TargetCostKind CostKind , const Instruction * I ) { InstructionCost Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind , I ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost ; return vectorCostAdjustment ( Cost , Opcode ,


<s> if ( ! context ) return false ; auto * STy = dyn_cast < StructType > ( PTy -> getElementType ( ) ) ; const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : <STR_LIT> ; for ( int i = <NUM_LIT> , e = array_lengthof ( specialTypes ) ; i != e ; ++ i ) if ( TypeName ==


<s> virtual const char * getPassName ( ) const LLVM_OVERRIDE { return <STR_LIT>


<s> static DecodeStatus DecodeMRSSystemRegister ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Address , const void * Decoder ) { Imm |= <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; bool ValidNamed ; ( void ) <STR_LIT> ( ) . toString


<s> return false ; } if ( ! Mem . WithPostInc ) { return false ; } return isOff3 ( getMemSrcImm


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredWinAlloca ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( ! Subtarget -> isTargetMachO ( ) ) ; <ISA_LIT>FrameLowering :: emitStackProbeCall ( * BB -> getParent ( ) , * BB , MI , DL ) ; MI -> eraseFromParent ( ) ; return


<s> if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) ,


<s> bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; CInst . setLoc ( Inst . getLoc ( ) ) ; S . EmitInstruction ( ( Res ? CInst : Inst ) ,


<s> const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = & * MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue &


<s> EVT VT = Op . getValueType ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; MVT IntVT = <STR_LIT> ; MVT FltVT = <STR_LIT> ; unsigned LHSSignBits = DAG . ComputeNumSignBits ( LHS ) ; if ( LHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned RHSSignBits = DAG . ComputeNumSignBits ( RHS ) ; if ( RHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned BitSize = VT . getSizeInBits ( ) ; unsigned SignBits = std :: min ( LHSSignBits , RHSSignBits ) ; unsigned DivBits = BitSize - SignBits ; if ( Sign ) ++ DivBits ; <STR_LIT> ToFp = Sign ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ToInt = Sign ? <STR_LIT> : <STR_LIT> ; SDValue jq = DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ; if ( Sign ) { jq = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( BitSize - <NUM_LIT> , DL , VT ) ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } SDValue ia = LHS ; SDValue ib = RHS ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; unsigned OpCode = MFI -> getMode ( ) . allFP32Denormals ( ) ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL


<s> return ( __m128i ) __builtin_ia32_cvtps2uqq128_mask ( ( __v4sf ) __A , ( __v2di )

_mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSPE4DisEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; uint32_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm ( ) ) ; uint32_t Imm = getMachineOpValue ( MI , MO , Fixups , STI ) >> <NUM_LIT> ; return reverseBits ( Imm | RegBits


<s> add_vector_labels ( file , <STR_LIT> ) ; if ( is_fast_interrupt_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT> ) ; if ( is_interrupt_func ( NULL_TREE ) )


<s> OperandMatchResultTy parseAR32 ( OperandVector & Operands ) { return parseRegister ( Operands ,


<s> auto FuncReg = FuncNameMap . find ( FuncName ) ; assert ( FuncReg != FuncNameMap . end (


<s> void <ISA_LIT>AnnotateControlFlow :: eraseIfUnused ( PHINode * Phi ) { if ( RecursivelyDeleteDeadPHINode ( Phi


<s> int NumElems = VT . getVectorNumElements ( ) ; assert ( NumElems == <NUM_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; int HalfSize = NumElems / <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != NumElems ; ++ i ) { if ( SVOp -> getMaskElt ( i ) < <NUM_LIT> ) continue ; unsigned Shamt = ( i % HalfSize ) * <NUM_LIT> ; unsigned Elt = SVOp -> getMaskElt ( i ) % HalfSize ; Mask |= Elt


<s> std :: string Ret = <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset0 , Offset1 , Base ; if ( ! SelectAddr ( N , N2 , Offset0 , Base ) || N1 . getValueType ( ) != <STR_LIT> || N2 . getValueType ( ) != <STR_LIT> ) return NULL ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue FPOdd = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; SDValue FPEven = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Offset0 ) ) Offset1 = CurDAG -> getTargetConstant ( C -> getSExtValue ( ) + <NUM_LIT> , <STR_LIT> ) ; else return NULL ; if ( TM . getTargetData ( ) -> isBigEndian ( ) ) std :: swap ( Offset0 , Offset1 ) ; SDValue Ops0 [ ] = { FPEven , Offset0 , Base , Chain } ; Chain = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops0 , <NUM_LIT> ) , <NUM_LIT> ) ; cast < MachineSDNode > ( Chain . getNode ( ) ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; SDValue Ops1 [ ] = { FPOdd , Offset1 , Base , Chain } ; Chain = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops1 , <NUM_LIT> ) , <NUM_LIT> ) ; cast < MachineSDNode > ( Chain . getNode ( ) ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Chain ) ; return Chain . getNode


<s> from_type = reg_class_to_reg_type [ ( int ) from_class ] ; to_type = reg_class_to_reg_type [ ( int ) to_class ] ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , ( secondary_reload_info * ) <NUM_LIT> , altivec_p ) ) return false ; if ( IS_FP_VECT_REG_TYPE ( from_type ) || IS_FP_VECT_REG_TYPE ( to_type ) ) return true ; return false


<s> return TypeSize :: getFixed ( ST -> getXLen ( ) ) ; case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( ST -> hasStdExtV ( ) ? ST

-> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ;


<s> const TargetRegisterClass * RC ; std :: string Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; assert ( Prefix == <STR_LIT> ) ; RC = getRegClassFor ( ( VT == <STR_LIT> ) ? <STR_LIT> : VT ) ; assert ( Reg < RC -> getNumRegs ( ) ) ; return std :: make_pair ( * ( RC -> begin ( ) + Reg )


<s> bool Was16 = isCode16 ( StartInfo . getTargetTriple ( ) ) ; if ( ! EndInfo || Was16 != isCode16 ( EndInfo


<s> return ( __m128i ) __builtin_ia32_vpcomfalseuq ( ( __v2di ) __A ,


<s> NPEngineTargetMachine & getNPEngineTargetMachine ( )


<s> bool mayNeedRelaxation ( const MCInst & ) const override { return


<s> cfun -> machine -> next_fcc += - cfun -> machine -> next_fcc & ( count - <NUM_LIT> ) ; if ( cfun -> machine -> next_fcc > FCC_REG_LAST - FCC_REG_FIRST ) cfun -> machine -> next_fcc = <NUM_LIT> ; regno = FCC_REG_FIRST + cfun -> machine -> next_fcc ; cfun -> machine -> next_fcc


<s> InstrExec . insert ( & MI ) ; visitNonBranch ( MI )


<s> assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems > <NUM_LIT> || ( NumElems == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) ) return splitVectorIntUnary ( Op , DAG ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; assert ( ( NewVT . is256BitVector ( ) || NewVT . is512BitVector ( ) ) && <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl ,

NewVT , Op . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! SMALL_OPERAND ( step1 ) ) { emit_move_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , adjust ) ; adjust = MIPS_EPILOGUE_TEMP ( Pmode ) ; } if ( ! TARGET_MIPS16 ) target = stack_pointer_rtx ; emit_insn ( gen_add3_insn ( target , base , adjust ) ) ; } if ( target != stack_pointer_rtx ) emit_move_insn ( stack_pointer_rtx , target ) ; if ( TARGET_ABICALLS && TARGET_NEWABI && ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_blockage ( ) ) ; mips_for_each_saved_reg ( cfun -> machine -> frame . total_size - step2 , mips_restore_reg ) ; if ( step2 > <NUM_LIT> ) emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( step2 ) ) ) ; if ( current_function_calls_eh_return ) { if ( TARGET_MIPS16 ) { emit_move_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , stack_pointer_rtx ) ; emit_insn ( gen_add3_insn ( MIPS_EPILOGUE_TEMP ( Pmode ) , MIPS_EPILOGUE_TEMP ( Pmode ) , EH_RETURN_STACKADJ_RTX ) ) ; emit_move_insn ( stack_pointer_rtx , MIPS_EPILOGUE_TEMP ( Pmode ) ) ; } else emit_insn ( gen_add3_insn ( stack_pointer_rtx ,

stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ;


<s> unsigned <ISA_LIT>Subtarget :: getMinSVEVectorSizeInBits ( ) const { assert ( HasSVE && <STR_LIT> ) ; assert ( SVEVectorBitsMin % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( ( SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == <NUM_LIT> ) && <STR_LIT> ) ; if ( SVEVectorBitsMax == <NUM_LIT> ) return ( SVEVectorBitsMin / <NUM_LIT> )


<s> MachineBasicBlock * <ISA_LIT>CFGStructurizer :: normalizeInfiniteLoopExit ( MachineLoop * LoopRep ) { MachineBasicBlock * LoopHeader = LoopRep -> getHeader ( ) ; MachineBasicBlock * LoopLatch = LoopRep -> getLoopLatch ( ) ; if ( ! LoopHeader || ! LoopLatch ) return nullptr ; MachineInstr * BranchMI = getLoopendBlockBranchInstr ( LoopLatch ) ; if ( ! BranchMI || ! isUncondBranch (


<s> DiagnosticPredicate isSVEPreferredLogicalImm ( ) const { if ( isLogicalImm < T > ( ) && ! isSVECpyImm < T > ( ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy ::


<s> s = ggc_alloc < stack_local_entry > ( ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE ( mode )


<s> int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> ,


<s> return MCID . TSFlags & <STR_LIT> || MCID . TSFlags & <STR_LIT> ||


<s> case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return LowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return ExpandADDSUB ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op ,


<s> for ( InputIt I = First ; I != Last ; ++ I ) { unsigned Matched = Predicate ( * I ) ; if ( Matched != FindBest_NoMatch ) { DEBUG ( dbgs ( ) << std :: distance ( First , I ) << <STR_LIT> ; I -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ) ; if ( Best == Last || BetterThan ( * I , * Best ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Best = I ; } } if ( Matched ==


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return & *


<s> const MCOperand MO1 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) ; if ( MO1 . isImm


<s> static bool alpha_cannot_copy_insn_p ( rtx insn ) { if ( ! reload_completed || !


<s> void <ISA_LIT>AtomicOptimizer :: visitAtomicRMWInst ( AtomicRMWInst & I ) { switch ( I . getPointerAddressSpace ( ) ) { default : return ; case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: LOCAL_ADDRESS : break ; } AtomicRMWInst :: BinOp Op = I . getOperation ( ) ; switch ( Op ) { default : return ; case AtomicRMWInst :: Add : case AtomicRMWInst :: Sub : case AtomicRMWInst :: And : case AtomicRMWInst :: Or : case AtomicRMWInst :: Xor : case AtomicRMWInst :: Max : case AtomicRMWInst :: Min : case AtomicRMWInst :: UMax : case AtomicRMWInst :: UMin : break ; } const unsigned PtrIdx = <NUM_LIT> ; const unsigned ValIdx = <NUM_LIT> ; if ( DA -> isDivergent ( I .


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU ,


<s> void printARI16Mem ( const MCInst * MI , unsigned opNum ,


<s> opts -> x_unaligned_access = ( TARGET_32BIT_P ( opts -> x_target_flags ) && arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ; } else if ( opts -> x_unaligned_access == <NUM_LIT> && ! ( arm_arch6 && ( arm_arch_notm || arm_arch7 ) ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; opts -> x_unaligned_access = <NUM_LIT> ; } if ( TARGET_THUMB1_P ( opts -> x_target_flags ) ) opts -> x_flag_schedule_insns = <NUM_LIT> ; else opts -> x_flag_schedule_insns = to -> x_flag_schedule_insns ; if ( optimize_function_for_size_p ( cfun ) && TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_flag_shrink_wrap = false ; else opts -> x_flag_shrink_wrap = to -> x_flag_shrink_wrap ; if ( TARGET_THUMB1_P ( opts -> x_target_flags ) ) opts -> x_flag_ipa_ra = <NUM_LIT> ; else opts -> x_flag_ipa_ra = to -> x_flag_ipa_ra ; if ( TARGET_THUMB2_P ( opts -> x_target_flags ) ) opts -> x_inline_asm_unified = true ; if ( arm_stack_protector_guard == SSP_GLOBAL &&

opts -> x_arm_stack_protector_guard_offset_str ) {


<s> { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! INT16_P ( INTVAL ( high ) ) + ! INT16_P ( INTVAL ( low ) ) ) ; return true ; } case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case DIV : case UDIV : case


<s> TypeNo = TypeNo << <STR_LIT> ; if ( Ty . getTag ( ) == dwarf :: DW_TAG_structure_type ) TypeNo = TypeNo | <STR_LIT> ; else TypeNo = TypeNo | <STR_LIT> ; CTy . getName ( TagName ) ; std :: string UniqueSuffix = <STR_LIT> + Ty . getGV ( ) -> getNameStr ( ) . substr ( <NUM_LIT> ) ; TagName += UniqueSuffix


<s> llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , Kind , Ctx ) ; if ( MO . getOffset ( ) != <NUM_LIT> ) { const auto * WasmSym = cast < MCSymbolWasm > ( Sym ) ; if ( TargetFlags == <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( WasmSym -> isFunction ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( WasmSym -> isGlobal ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( WasmSym -> isTag ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( WasmSym -> isTable ( ) ) report_fatal_error ( <STR_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; } return MCOperand :: createExpr ( Expr


<s> M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext

( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) , nullptr ) ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model >


<s> rtx call , use = NULL ; if ( flag_pic && GET_CODE ( XEXP ( fnaddr , <NUM_LIT> ) ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( XEXP ( fnaddr , <NUM_LIT> ) ) ) { crtl -> uses_pic_offset_table = <NUM_LIT> ; rtx hard_pic = gen_rtx_REG ( Pmode , REAL_PIC_OFFSET_TABLE_REGNUM ) ; emit_move_insn ( hard_pic , pic_offset_table_rtx ) ; use_reg ( & use , hard_pic ) ; } if ( ! call_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , Pmode ) ) { fnaddr = copy_to_mode_reg ( Pmode , XEXP ( fnaddr , <NUM_LIT> ) ) ; fnaddr = gen_rtx_MEM ( SImode , fnaddr ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) call = gen_rtx_SET ( retval , call ) ; if ( ! sibcall ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , call , clob ) ) ; } call = emit_call_insn ( call


<s> SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++


<s> static SDValue RewriteAsNarrowerShuffle ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG , DebugLoc dl ) { EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned NewWidth = ( NumElems == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT NewVT ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; } int Scale =


<s> Locals . resize ( NumLocals , <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode >


<s> rtx fpu_insn ; rtx reg , mem ; unsigned int regno = cfun -> machine -> callee_saved_first_fpr_regno ; unsigned int last_fpr = cfun -> machine -> callee_saved_last_fpr_regno ; while ( regno <= last_fpr ) { reg = gen_rtx_REG ( DFmode , regno ) ; mem = gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , base_offset ) ) ; base_offset += <NUM_LIT> ; regno += <NUM_LIT> ; fpu_insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( fpu_insn


<s> if ( ! VecTy -> isVectorTy ( ) || isa < ScalableVectorType > ( VecTy ) ) return false ; if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT Ty = EVT :: getEVT ( VecTy , false ) ; if ( ! Ty . isSimple ( ) || Ty . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( isHVXVectorType ( Ty . getSimpleVT ( ) , IncludeBool ) ) return true ; auto Action = getTargetLowering ( ) -> getPreferredVectorAction ( Ty . getSimpleVT ( ) ) ; return Action == TargetLoweringBase


<s> if ( ! isMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType != <STR_LIT> ) return false ; if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm )


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > <NUM_LIT> ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; return ( Subtarget -> hasLSE ( ) && Size < <NUM_LIT> ) ?

AtomicExpansionKind :: None : AtomicExpansionKind :: LLSC ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , const <ISA_LIT>Subtarget & st ) : Ctx ( ctx ) , ST ( st


<s> if ( imm == <NUM_LIT> && ! add ) imm = INT32_MIN ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( Rn == <NUM_LIT> ) tryAddingPcLoadReferenceComment ( Address , Address + imm + <NUM_LIT> , Decoder ) ; return S


<s> setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , F . getCallingConv ( ) ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( RetCC_<ISA_LIT> ) ; <ISA_LIT>OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitRetInfos , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; } MIRBuilder . insertInstr ( MIB ) ; return


<s> Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> || LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; return false ; } else if ( LastInst -> getOpcode ( ) == <STR_LIT> || LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB (


<s> uint64_t encoding ; const MCOperand op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( op1 . isReg ( ) && <STR_LIT> ) ; encoding = get<ISA_LIT>RegisterNumbering ( op1 . getReg ( ) ) ; encoding <<= <NUM_LIT> ; MCOperand op2 = MI . getOperand ( <NUM_LIT> ) ; assert ( op2 . isImm ( ) && <STR_LIT> ) ; encoding |= op2 . getImm ( ) &


<s> unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += InstrOffs * Scale


<s> unsigned <ISA_LIT>ParamManager :: addCallArgParam ( Type * Ty , const StringRef ParamName ) { return addParam ( <ISA_LIT>_PARAM_TYPE_CALL_PARAM , Ty , ParamName


<s> auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlignment ( RetTy ) : <NUM_LIT> ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op =


<s> if ( FP_REG_P ( src ) || FP_REG_P ( dst ) || VECTOR_REG_P ( src ) || VECTOR_REG_P ( dst ) ) return false ; if ( s_operand ( src , mode ) || s_operand ( dst , mode ) ) return false ; if ( ( GET_CODE ( src ) == MEM && ! offsettable_memref_p ( src ) ) || ( GET_CODE ( dst ) == MEM && ! offsettable_memref_p ( dst ) ) ) return false ; if ( register_operand ( dst , mode ) ) { rtx subreg = operand_subword ( dst , first_subword , <NUM_LIT> , mode ) ; if ( reg_overlap_mentioned_p ( subreg , src ) ) return false ; } return true


<s> return CU :: UNWIND_ARM64_MODE_DWARF ; case MCCFIInstruction :: OpDefCfa : { unsigned XReg = getXRegFromWReg ( * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ) ; if ( XReg != <STR_LIT> ) return CU :: UNWIND_ARM64_MODE_DWARF ; assert ( XReg == <STR_LIT> && <STR_LIT> ) ; assert ( i + <NUM_LIT> < e && <STR_LIT> ) ; const MCCFIInstruction & LRPush = Instrs [ ++ i ] ; assert ( LRPush . getOperation ( ) == MCCFIInstruction :: OpOffset && <STR_LIT> ) ; const MCCFIInstruction & FPPush = Instrs [ ++ i ] ; assert ( FPPush . getOperation ( ) == MCCFIInstruction :: OpOffset && <STR_LIT> ) ; unsigned LRReg = * MRI . getLLVMRegNum ( LRPush . getRegister ( ) , true ) ; unsigned FPReg = * MRI . getLLVMRegNum ( FPPush . getRegister ( ) , true ) ; LRReg = getXRegFromWReg ( LRReg ) ; FPReg = getXRegFromWReg ( FPReg ) ; assert ( LRReg == <STR_LIT> && FPReg == <STR_LIT> && <STR_LIT> ) ; CompactUnwindEncoding |= CU :: UNWIND_ARM64_MODE_FRAME ; HasFP = true ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { assert ( StackSize == <NUM_LIT> && <STR_LIT> ) ; StackSize = std :: abs ( Inst . getOffset ( ) ) ; break ; } case MCCFIInstruction :: OpOffset : { unsigned Reg1 = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; if ( i + <NUM_LIT> == e ) return CU :: UNWIND_ARM64_MODE_DWARF ; const MCCFIInstruction & Inst2 = Instrs [ ++ i ] ; if ( Inst2 . getOperation ( ) != MCCFIInstruction :: OpOffset ) return CU :: UNWIND_ARM64_MODE_DWARF ; unsigned Reg2 = * MRI . getLLVMRegNum ( Inst2 . getRegister ( ) , true ) ; Reg1 = getXRegFromWReg ( Reg1 ) ; Reg2 = getXRegFromWReg


<s> if ( MBB . isLayoutSuccessor ( TBB ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; } continue ; } unsigned Opcode = I -> getOpcode ( ) ; switch ( Opcode ) { default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ; } if ( Cond . empty ( ) ) { unsigned condReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { Opcode = GetOppositeBranchOpcode ( Opcode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addReg ( condReg ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Opcode ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( condReg , false ) ) ; continue ; } FBB = TBB ; TBB = TargetBB


<s> int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( BitExtMI ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoadI -> eraseFromParent ( ) ; return NextI


<s> SmallVector < int , <NUM_LIT> > Mask ( S0 -> getMask ( ) . begin ( ) , S0 -> getMask ( ) . end ( ) ) ; Mask . append ( S1 -> getMask ( ) . begin ( ) , S1 -> getMask ( ) . end ( ) ) ; if ( isVMOVNTruncMask ( Mask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( isVMOVNTruncMask ( Mask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , S0 -> getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } } if ( all_of ( N -> ops ( ) , [ ] ( SDValue Op ) { return Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; } ) ) { SmallVector < SDValue , <NUM_LIT> > Extracts ; for ( unsigned Op = <NUM_LIT> ; Op < N -> getNumOperands ( ) ; Op ++ ) { SDValue O = N -> getOperand ( Op ) ; for ( unsigned i = <NUM_LIT> ; i < O . getValueType ( ) . getVectorNumElements ( ) ; i ++ ) { SDValue Ext = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , O , DAG . getConstant ( i , DL , <STR_LIT> ) ) ; Extracts . push_back ( Ext ) ; } } return DAG . getBuildVector ( VT , DL , Extracts ) ; } if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( TypeSize :: Fixed ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ; int NumIns = N ->