<s> if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; int NumElems = VT . getVectorNumElements ( ) ; EVT CanonVT = VT . getSizeInBits ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( int i = <NUM_LIT> ; i < NumElems ; ++ i ) Mask . push_back ( EltNo ) ; V1 = DAG . getNode ( <STR_LIT> , dl , CanonVT , V1 ) ; return DAG . getNode ( <STR_LIT> , dl , NVT , DAG . getVectorShuffle ( CanonVT , dl , V1 , DAG .

getUNDEF ( CanonVT ) , & Mask [ <NUM_LIT> ] ) ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) &&


<s> DiagnosticInfoUnsupported NoTrap ( * MF . getFunction ( ) , <STR_LIT> , Op . getDebugLoc ( ) , DS_Warning ) ; DAG . getContext ( ) -> diagnose (


<s> case <STR_LIT> : { SDNode * Node = LowerLOAD ( SDValue ( N , <NUM_LIT> ) , DAG ) . getNode ( ) ; Results . push_back ( SDValue ( Node , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( Node , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) ) ; return ; } case <STR_LIT>


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; HazardRec -> dumpSU ( * Available . begin ( ) , dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; ) ; return * Available . begin ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ; Available . dump ( * HazardRec ) ; ) ; Candidate Best ; for ( auto * SU : Available ) { Candidate c ( SU , * HazardRec ) ; if ( Best . SU == nullptr || c < Best ) { Best = c ; DEBUG ( dbgs (


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ <NUM_LIT> ] + <NUM_LIT> ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = <NUM_LIT> ; i < nelt ; next ++ , i ++ ) { if ( next == <NUM_LIT> * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == <NUM_LIT> ) && ( d -> vmode != V2DImode ) ) return false ; else next = <NUM_LIT> ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ <NUM_LIT> ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT


<s> static DecodeStatus DecodeADRFRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { bool VPUEncoding = Inst . getFlags ( ) != FlagSPU ; unsigned Register ; if ( VPUEncoding ) { if ( RegNo > <NUM_LIT> || RegNo < <NUM_LIT> ) return MCDisassembler :: Fail ; Register = RegisterTableVPU [ RegNo ] ; } else { if ( RegNo >= <NUM_LIT> || RegNo < <NUM_LIT> ) return MCDisassembler :: Fail ; Register = RegisterTableSPU [ RegNo


<s> return isLD<ISA_LIT>nstr ( Opcode ) && getOperandIdx ( Opcode , <STR_LIT>


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const { if ( OSType == Triple :: OSType


<s> static inline float getFPImmFloat ( unsigned Imm ) { union { uint32_t I ; float F ; } FPUnion ; uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( Exp & <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= Mantissa <<


<s> { MO_ABSOLUTE_ADDRESS , <STR_LIT> } , { MO_PC_RELATIVE_ADDRESS , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_GOTOFF , <STR_LIT> } , { MO_GOTPCREL , <STR_LIT> } , { MO_PLT , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> BasicBlock * NewBB = NewPt -> getParent ( ) ; for ( InsertionPoints :: iterator IPI = InsertPts . begin ( ) , EndIPI = InsertPts . end ( ) ; IPI != EndIPI ; ++ IPI ) { BasicBlock * CurBB = IPI -> first -> getParent ( ) ; if ( NewBB == CurBB ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; appendAndTransferDominatedUses ( NewPt , UseIt , IPI , InsertPts ) ; return true ; } BasicBlock * CommonDominator = DT . findNearestCommonDominator ( NewBB ,


<s> void <ISA_LIT>64GNULDBackend :: initTargetSections ( Module & pModule , ObjectBuilder & pBuilder ) { <ISA_LIT>GNULDBackend :: initTargetSections ( pModule , pBuilder ) ; if ( LinkerConfig :: Object == config ( ) . codeGenType ( ) ) return ; ELFFileFormat * fileFormat = getOutputFormat ( ) ; LDSection & got = fileFormat -> getGOT ( ) ; m_pGOT = new <ISA_LIT>64GOT ( got ) ; LDSection & gotplt = fileFormat -> getGOTPLT ( ) ; m_pGOTPLT = new <ISA_LIT>GOTPLT ( gotplt ) ; LDSection & plt = fileFormat -> getPLT ( ) ; m_pPLT = new <ISA_LIT>PLT


<s> EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { if ( Op -> isImm ( ) ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) . addImm ( Op -> getImm ( ) ) ) ; else if ( Op -> isReg ( ) ) { if ( Op -> getReg ( ) != UsedRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) .


<s> case E_V8QImode : emit_insn ( gen_loongson_vec_init1_v8qi ( t1 , elt ) ) ; break ; case E_V4HImode : emit_insn ( gen_loongson_vec_init1_v4hi ( t1 , elt ) ) ; break ; default : gcc_unreachable ( ) ; } memset ( & d , <NUM_LIT> , sizeof ( d ) ) ; d . target = target ; d . op0


<s> void <ISA_LIT>PassConfig :: addCodeGenPrepare ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createTypePromotionPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare


<s> IsaVersion ISA = getIsaVersion ( Features ) ; memset ( & Header , <NUM_LIT> , sizeof ( Header ) ) ; Header . amd_kernel_code_version_major = <NUM_LIT> ; Header . amd_kernel_code_version_minor = <NUM_LIT> ; Header . amd_machine_kind = <NUM_LIT> ; Header . amd_machine_version_major = ISA .


<s> if ( TyA != DestTy || TyB != SrcTy ) return false ; } else if ( auto * PHI = dyn_cast < PHINode > ( V ) ) { if ( OldPhiNodes . count ( PHI ) == <NUM_LIT> ) return false ; } else return false ; } } SmallDenseMap < PHINode * , PHINode * > NewPNodes ; for ( auto * OldPN : OldPhiNodes ) { Builder . SetInsertPoint ( OldPN ) ; PHINode * NewPN = Builder . CreatePHI ( DestTy , OldPN -> getNumOperands ( ) ) ; NewPNodes [ OldPN ] = NewPN ; } for ( auto * OldPN : OldPhiNodes ) { PHINode * NewPN = NewPNodes [ OldPN ] ; for ( unsigned j = <NUM_LIT> , e = OldPN -> getNumOperands ( ) ; j != e ; ++ j ) { Value * V = OldPN -> getOperand ( j ) ; Value * NewV = nullptr ; Instruction * ACI = dyn_cast < Instruction > ( V ) ; if ( ACI && isAMXCast ( ACI ) ) NewV = ACI -> getOperand ( <NUM_LIT> ) ; else if ( auto * PrevPN = dyn_cast < PHINode > ( V ) ) NewV = NewPNodes [ PrevPN ] ; assert ( NewV )


<s> MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } } if ( Subtarget . hasVLX ( ) ) { if ( WidenedMask [ <NUM_LIT> ] < <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> ) { unsigned PermMask = ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) | ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( PermMask , DL , <STR_LIT> ) ) ; } } } assert ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask


<s> if ( GET_CODE ( sym ) == MEM ) sym =


<s> if ( fitsRegularPattern < int > ( Begin + <NUM_LIT> , <NUM_LIT> , End , <NUM_LIT> , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ; else if ( fitsRegularPattern < int > ( Begin + <NUM_LIT> , <NUM_LIT> , End , Indices . size ( ) , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ; else return SDValue


<s> return DAG . getNode ( <STR_LIT> , DL , VT , NewLD ) ; } if ( Load -> getAddressSpace ( ) == <STR_LIT> && isa < GlobalVariable > ( GetUnderlyingObject ( Load -> getMemOperand ( ) -> getValue ( ) ) ) ) { SDValue Ptr = DAG . getZExtOrTrunc ( Load -> getBasePtr ( ) , DL , getPointerTy ( <STR_LIT> ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } if ( Load -> getAddressSpace ( ) != <STR_LIT> || ExtType == <STR_LIT> || Load -> getMemoryVT ( ) . bitsGE ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType == <STR_LIT> ) { SDValue MemEltVTNode = DAG . getValueType ( MemEltVT ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , MemEltVTNode ) ; } return DAG . getZeroExtendInReg ( Ret , DL


<s> [ [ noreturn ] ] inline void Assert ( const char * expression , const char * file , int line ) { std :: fprintf ( stderr , <STR_LIT> , expression , file , line ) ; std :: abort (


<s> static DecodeStatus DecodeGRRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder


<s> } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count = count > sub_count ? count :


<s> } } APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { int Idx = SHFIndices [ i ] ; if ( Idx == - <NUM_LIT> ) Idx = <NUM_LIT> ; Imm <<= <NUM_LIT> ; Imm |= Idx & <NUM_LIT> ; } SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy , DAG . getTargetConstant ( Imm ,

DL , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) ) ;


<s> const MCExpr * EVal ; AsmToken :: TokenKind kind = getLexer ( ) . getKind ( ) ; switch ( kind ) { default : return true ; case AsmToken :: Minus : case AsmToken :: Integer : if ( getParser ( ) . parseExpression ( EVal ) ) return true ; Operands . push_back ( <STR_LIT> ( EVal , S , E ) ) ; return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; const auto * CD = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; int CondCode = CD -> getSExtValue ( ) ; if ( CondCode < FCmpInst :: Predicate :: FIRST_FCMP_PREDICATE || CondCode > FCmpInst :: Predicate :: LAST_FCMP_PREDICATE ) { return DAG . getUNDEF ( VT ) ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; EVT CmpVT = Src0 . getValueType ( ) ; SDLoc SL ( N ) ; if ( CmpVT == <STR_LIT> && ! TLI . isTypeLegal ( CmpVT ) ) { Src0 = DAG . getNode ( <STR_LIT> ,


<s> Inst . Op = FPOInstruction :: StackAlloc ; Inst . RegOrOffset = StackAlloc ; CurFPOData -> Instructions . push_back ( Inst


<s> LLT Ty = MRI . getType ( Dst ) ; assert ( ! Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; const Register ZeroReg = <STR_LIT> ; auto EmitCSet = [ & ] ( Register CsetDst , <STR_LIT> CC ) { auto CSet = MIRBuilder . buildInstr ( <STR_LIT> , { CsetDst } , { ZeroReg , ZeroReg } ) . addImm ( getInvertedCondCode ( CC ) ) ; constrainSelectedInstRegOperands ( * CSet , TII , TRI , RBI ) ; return & * CSet ; } ; <STR_LIT> CC1 , CC2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) return EmitCSet ( Dst , CC1 ) ; const TargetRegisterClass * RC = & <STR_LIT> ; Register Def1Reg = MRI . createVirtualRegister ( RC ) ; Register Def2Reg = MRI . createVirtualRegister ( RC ) ; EmitCSet ( Def1Reg ,


<s> unsigned Mask3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp2Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp3Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned Tmp4Reg = RegInfo . createVirtualRegister ( RC ) ; unsigned TmpDestReg = RegInfo . createVirtualRegister ( RC ) ; unsigned Ptr1Reg ; unsigned TmpReg = ( ! BinOpcode ) ? Incr2Reg : RegInfo . createVirtualRegister ( RC ) ; BB -> addSuccessor ( loopMBB ) ; if ( ptrA != ZeroReg ) { Ptr1Reg = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Ptr1Reg ) . addReg ( ptrA ) . addReg ( ptrB ) ; } else { Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg


<s> bool isRegOrImmWithInt16InputMods ( )


<s> __arm_vldrhq_s16 ( int16_t const * __base ) { return __builtin_mve_vldrhq_sv8hi ( ( __builtin_neon_hi *


<s> const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee


<s> rtx regbuf ; ns = cfun -> machine -> arg_regs_to_save ; if ( TARGET_IVC2 ) { bufsize = <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) + <NUM_LIT> * ns ; regbuf = assign_stack_local ( SImode , bufsize , <NUM_LIT> ) ; } else { bufsize = ns * <NUM_LIT> ; regbuf = assign_stack_local ( SImode , bufsize , <NUM_LIT> ) ; } move_block_from_reg ( <NUM_LIT> - ns , regbuf , ns ) ; if ( TARGET_IVC2 ) { rtx tmp = gen_rtx_MEM ( DImode , XEXP ( regbuf , <NUM_LIT> ) ) ; int ofs = <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < ns ; i ++ ) { int rn = ( <NUM_LIT> - ns ) + i + <NUM_LIT> ; rtx ptr ; ptr = offset_address ( tmp , GEN_INT ( ofs ) , <NUM_LIT> ) ; emit_move_insn ( ptr , gen_rtx_REG ( DImode , rn ) ) ; ofs +=


<s> return ( __m256i ) __builtin_ia32_cvtps2dq256_mask ( ( __v8sf ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , (


<s> LPR . stepForward ( * R , Clobbers ) ; for ( auto & C : Clobbers ) if ( C . second -> isReg ( ) && C . second -> isDead ( ) ) LPR . removeReg ( C . first ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; const auto & RC = ! Is128B ? <STR_LIT> : <STR_LIT> ; unsigned Size = HRI . getSpillSize ( RC ) ; unsigned NeedAlign = HRI . getSpillAlignment ( RC ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI


<s> while ( true ) { unsigned Mode = <NUM_LIT> ; SMLoc S = getLoc ( ) ; for ( unsigned ModeId = ID_MIN ; ModeId <= ID_MAX ; ++ ModeId ) { if ( trySkipId ( IdSymbolic [ ModeId ] ) ) { Mode = <NUM_LIT> << ModeId ; break ; } } if ( Mode == <NUM_LIT> ) { Error ( S , ( Imm == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; return


<s> if ( Preheader == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ; MachineBasicBlock * LastMBB = L -> getExitingBlock ( ) ; if ( LastMBB == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ; MachineBasicBlock * LoopStart = L -> getTopBlock ( ) ; if ( L -> getLoopLatch ( ) != LastMBB ) { LoopStart = L -> getLoopLatch ( ) ; if ( ! LastMBB -> isSuccessor ( LoopStart ) ) { return false ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; if ( TripCount -> isReg ( ) ) { MachineFunction * MF = LastMBB -> getParent ( ) ; const TargetRegisterClass * RC = MF -> getRegInfo ( ) . getRegClass ( TripCount -> getReg ( ) ) ; unsigned CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) ) ; if ( TripCount -> isNeg ( ) ) { unsigned CountReg1 = CountReg ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CountReg ) . addReg ( CountReg1 ) ; } BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; } else { assert ( TripCount -> isImm ( ) && <STR_LIT> ) ; int64_t CountImm = TripCount -> getImm ( ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ; } LoopStart -> setHasAddressTaken ( ) ; BlockAddress :: get ( const_cast < BasicBlock * > ( LoopStart -> getBasicBlock ( ) ) ) ; DebugLoc dl = LastI -> getDebugLoc ( ) ; BuildMI ( * LastMBB , LastI , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopStart ) ; if ( LastI -> getOpcode ( ) == <STR_LIT> || LastI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * BranchTarget = LastI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastI = LastMBB -> erase ( LastI ) ; if ( ! L -> contains ( BranchTarget ) ) { if ( LastI != LastMBB -> end (


<s> for ( b_arg_chain = TYPE_ARG_TYPES ( TREE_TYPE ( fndecl ) ) ; ! VOID_TYPE_P ( TREE_VALUE ( b_arg_chain ) ) ; b_arg_chain = TREE_CHAIN ( b_arg_chain ) ) { int tmp_n_elem ; if ( TREE_CODE ( TREE_VALUE ( b_arg_chain ) ) != VECTOR_TYPE ) continue ; tmp_n_elem = TYPE_VECTOR_SUBPARTS ( TREE_VALUE ( b_arg_chain ) ) ; if ( n_elem != - <NUM_LIT> && n_elem != tmp_n_elem ) return - <NUM_LIT> ; n_elem =


<s> Zero = TBB ; break ; case <STR_LIT> : Nonzero = TBB ; Zero = FBB ; break ; default : return Optional < BlockBRNZ > ( ) ; } MachineBasicBlock :: const_reverse_instr_iterator MI = MBB . instr_rbegin ( ) ; while ( MI != MBB . instr_rend ( ) && MI -> isUnconditionalBranch ( ) ) ++ MI ; if ( MI == MBB . instr_rend ( ) || ! MI -> isConditionalBranch ( ) ) return Optional < BlockBRNZ > ( ) ; BlockBRNZ Desc ; Desc . Zero = Zero ; Desc . Nonzero = Nonzero ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & op = MI -> getOperand ( <NUM_LIT> ) ; if ( op . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return Optional < BlockBRNZ > ( ) ; Desc . IsKill = op . isKill ( ) ; Desc . Regs . push_back ( op . getReg ( ) ) ; break ; } if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return Optional < BlockBRNZ > ( ) ; } if ( Desc . Regs . size ( ) != <NUM_LIT> ) { return Optional < BlockBRNZ > ( ) ; } const Register & Reg0 = Desc . Regs [ <NUM_LIT> ] ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> isPHI ( ) ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg0 ) { unsigned NumOperands = MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOperands ; I += <NUM_LIT> ) { Desc . Regs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; } } return Desc ; } if ( MI -> modifiesRegister ( Reg0 , TRI ) ) return Optional < BlockBRNZ > ( ) ; if ( MI -> readsRegister ( Reg0 , TRI ) ) Desc . IsKill = false ; } return Desc


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target ,


<s> static inline bool isAdvSIMDModImmType7 ( uint64_t Imm ) { return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) &&


<s> Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Neg = MIB . buildInstr ( NegOpc ,


<s> static rtx aarch64_gen_unspec_cond ( rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtvec vec = gen_rtvec ( <NUM_LIT> , pred , op0 , op1 ) ; return gen_rtx_UNSPEC ( pred_mode , vec , aarch64_unspec_cond_code ( code


<s> if ( arg . end_marker_p ( ) ) return NULL ; return loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named


<s> LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( LHS , DAG ) , Mask ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , bitcastf32Toi32 ( RHS , DAG ) , Mask ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } SDValue LHS1 , LHS2 ; SDValue RHS1 , RHS2 ; expandf64Toi32 ( LHS , DAG , LHS1 , LHS2 ) ; expandf64Toi32 ( RHS , DAG , RHS1 , RHS2 ) ; LHS2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS2 , Mask


<s> auto * Icmp1 = dyn_cast < ICmpInst > ( I . getOperand ( <NUM_LIT> ) ) ; if ( ! Icmp1 ) return false ; auto * Icmp2 = dyn_cast < ICmpInst > ( I . getOperand ( <NUM_LIT> ) ) ; if ( ! Icmp2 ) return false ; Value * Icmp1Op0 = Icmp1 -> getOperand ( <NUM_LIT> ) ; Value * Icmp2Op0 = Icmp2 -> getOperand ( <NUM_LIT> ) ; if ( Icmp1Op0 != Icmp2Op0 ) return false ; PassThroughInfo Info ( Icmp1 , & I , <NUM_LIT> ) ; PassThroughs . push_back ( Info


<s> const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) { llvm_unreachable ( <STR_LIT> ) ; } switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstant ( CE , getDataLayout ( ) ) ) if ( C && C != CE ) return lowerConstantForGV ( C , ProcessingGeneric ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? <NUM_LIT> : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = getDataLayout ( ) ; Constant * Op = CE -> getOperand


<s> MachineBasicBlock :: iterator I = MBB . begin ( ) ; DebugLoc DL ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned WorkGroupIDSGPR = MFI -> getWorkGroupIDSGPR ( i ) ; MF . getRegInfo ( ) . addLiveIn ( WorkGroupIDSGPR ) ; MBB . addLiveIn ( WorkGroupIDSGPR ) ; unsigned WorkGroupIDVGPR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , WorkGroupIDVGPR ) . addReg ( WorkGroupIDSGPR ) ; int WorkGroupIDObjectIdx = MFI -> getDebuggerWorkGroupIDStackObjectIndex ( i ) ; TII -> storeRegToStackSlot ( MBB , I , WorkGroupIDVGPR , false , WorkGroupIDObjectIdx , & <STR_LIT> , TRI ) ; unsigned WorkItemIDVGPR = MFI -> getWorkItemIDVGPR ( i ) ; MF . getRegInfo ( ) . addLiveIn ( WorkItemIDVGPR ) ; MBB . addLiveIn ( WorkItemIDVGPR


<s> unsigned AssignmentState :: getXccVReg ( unsigned reg , const TargetRegisterClass * RC ) const { int side = - <NUM_LIT> ; if ( RC == ARegsRegisterClass ) side = <NUM_LIT> ; else if ( RC == BRegsRegisterClass ) side = <NUM_LIT> ; assert ( side >= <NUM_LIT> )


<s> else if ( num_regs == <NUM_LIT> ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << PC_REGNUM


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: Cmp ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: AddSub ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> int EHRegSize = MFI -> getObjectSize ( FI ) ; int EndOffset = - EHRegOffset - EHRegSize ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; if ( UsedReg == FramePtr ) { assert ( UsedReg == FramePtr ) ; unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } else { assert ( UsedReg == BasePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , BasePtr ) , FramePtr , false , EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; assert ( <ISA_LIT>FI -> getHasSEHFramePtrSave ( ) ) ; int Offset = getFrameIndexReference ( MF , <ISA_LIT>FI

-> getSEHFramePtrSaveIndex ( ) , UsedReg ) ;


<s> uint32_t Major ; uint32_t Minor ; if ( ParseDirectiveMajorMinor ( Major , Minor ) ) return true ; getTargetStreamer ( ) . EmitDirectiveHSACodeObjectVersion ( Major , Minor ) ; return false


<s> MachineOperand Dest ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Src ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Suppress ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand Mode ( MI . getOperand ( <NUM_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( Opcode ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , & MI ) . add ( Dest ) . add ( Mode ) . add ( Src ) . add ( Suppress ) ; return true ; } return false


<s> assert ( ConstOp . isCImm ( ) && <STR_LIT> ) ; Opcode = ConstOp . getCImm ( ) -> getValue ( ) . getZExtValue ( ) ? <STR_LIT> : <STR_LIT> ; } auto MIB = MIRBuilder . buildInstr ( Opcode ) . addDef ( ResVReg ) . addUse ( GR -> get<ISA_LIT>TypeID ( ResType ) ) ; if ( ! IsBool ) { if ( Const -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ) addNumImm ( ConstOp . getCImm ( ) -> getValue ( ) , MIB ) ; else addNumImm ( ConstOp . getFPImm ( ) -> getValueAPF (


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder ,


<s> return TargetTransformInfo ( GCNTTIImpl ( this


<s> bool DeadCodeElimination :: runOnNode ( MachineDomTreeNode * N ) { bool Changed = false ; for ( auto * DTN : children < MachineDomTreeNode * > ( N ) ) Changed |= runOnNode ( DTN ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) ) continue ; if ( ! MI -> isPHI ( ) && ! MI ->

isSafeToMove ( nullptr , Store ) ) continue ;


<s> Type * <ISA_LIT>TargetLowering :: shouldConvertSplatType ( ShuffleVectorInst * SVI ) const { if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return nullptr ; Type * SVIType = SVI -> getType ( ) ; Type * ScalarType = SVIType -> getScalarType ( ) ; if ( ScalarType -> isFloatTy ( ) ) return Type :: getInt32Ty


<s> int BaseRegNum = Op -> getReg ( ) ; bool Preindexed = false ; bool Postindexed = false ; bool OffsetIsReg = false ; bool Negative = false ; bool Writeback = false ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Preindexed = true ; Parser . Lex ( ) ; int OffsetRegNum ; bool OffsetRegShifted ; enum ShiftType ShiftType ; const MCExpr * ShiftAmount ; const MCExpr * Offset ; if ( ParseMemoryOffsetReg ( Negative , OffsetRegShifted , ShiftType , ShiftAmount , Offset , OffsetIsReg , OffsetRegNum , E ) ) return true ; const AsmToken & RBracTok = Parser . getTok ( ) ; if ( RBracTok . isNot ( AsmToken :: RBrac ) ) return Error ( RBracTok . getLoc ( ) , <STR_LIT> ) ; E = RBracTok . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { E = ExclaimTok . getLoc ( ) ; Writeback = true ; Parser . Lex ( ) ; } <ISA_LIT>Operand :: CreateMem ( Op , BaseRegNum , OffsetIsReg , Offset , OffsetRegNum , OffsetRegShifted , ShiftType , ShiftAmount , Preindexed , Postindexed , Negative


<s> SDVTList VTList = DAG . getVTList ( EquivLoadVT , <STR_LIT> ) ; SDValue Res ; SDLoc DL ( Op ) ; MemSDNode * M = cast < MemSDNode > ( Op ) ; unsigned IID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; Chain = Res . getValue ( <NUM_LIT> ) ; return adjustLoadValueType ( Res , LoadVT , DL , DAG , Unpacked ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; Chain = Res . getValue ( <NUM_LIT> ) ; return adjustLoadValueType ( Res , LoadVT , DL , DAG , Unpacked ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; unsigned Opc = getImageOpcode ( IID ) ; Res = DAG . getMemIntrinsicNode ( Opc , DL , VTList , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; Chain = Res . getValue ( <NUM_LIT> ) ; return adjustLoadValueType ( Res , LoadVT , DL , DAG , Unpacked ) ; } case <STR_LIT> : case


<s> tree perm_type = build_vector_type ( ssizetype , nelts ) ; return gimple_build_assign ( f . lhs , VEC_PERM_EXPR , gimple_call_arg ( f . call , <NUM_LIT> ) , gimple_call_arg ( f . call , nargs - <NUM_LIT> )

, vec_perm_indices_to_tree ( perm_type , indices ) ) ;


<s> bool isNEONi32splatNot ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE ->


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel (


<s> static LegalityPredicate isSmallOddVector ( unsigned TypeIdx ) { return [ = ] ( const LegalityQuery & Query ) { const LLT Ty = Query .


<s> Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; if ( ! isLoadStoreTypeLegal ( Op0 -> getType ( ) , VT ) || cast < StoreInst > ( I )


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return


<s> if ( ! REG_P ( x ) ) return <NUM_LIT> ; regno = REGNO ( x ) ; if ( strict_p ) return THUMB1_REGNO_MODE_OK_FOR_BASE_P


<s> if ( ( Addr . getOffset ( ) < <NUM_LIT> ) || ( Addr . getOffset ( ) & ( ScaleFactor - <NUM_LIT> ) ) ) { UseScaled = false ; ScaleFactor = <NUM_LIT> ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return


<s> if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( isFP64bit ( ) && ! has<ISA_LIT>64 ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( inAbs2008Mode ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; assert ( inAbs2008Mode ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && !