<s> if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } C = ConstantVector :: get ( CV ) ; CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask2 = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Mask2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val


<s> numRegs = MFI -> getNumRegistersForClass ( <STR_LIT> ) ; if ( numRegs > <NUM_LIT> ) { regDefs += <STR_LIT> ; regDefs += utostr ( numRegs ) ; regDefs += <STR_LIT> ; } for ( <ISA_LIT>ParamManager :: param_iterator i = PM . local_begin ( ) , e = PM . local_end ( ) ; i != e ; ++ i ) { regDefs += <STR_LIT> ; regDefs += utostr ( PM . getParamSize ( * i ) ) ; regDefs += <STR_LIT> ; regDefs += PM . getParamName ( * i ) ; regDefs += <STR_LIT> ; } OutStreamer . EmitRawText ( Twine ( regDefs ) ) ; const MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FrameInfo -> getNumObjects ( ) << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = FrameInfo -> getNumObjects ( ) ; i != e ; ++ i ) { DEBUG ( dbgs ( ) << <STR_LIT> << FrameInfo -> getObjectSize ( i ) << <STR_LIT> ) ; if ( FrameInfo -> getObjectSize ( i ) > <NUM_LIT> ) { std :: string def = <STR_LIT> ; def += utostr ( FrameInfo -> getObjectAlignment ( i ) ) ; def += <STR_LIT> ; def += <STR_LIT> ; def += utostr ( i ) ; def += <STR_LIT> ; def += utostr ( FrameInfo -> getObjectSize ( i ) ) ; def += <STR_LIT> ; def += <STR_LIT> ; OutStreamer . EmitRawText ( Twine ( def )


<s> return ( __m128d ) __builtin_ia32_vfmsubpd ( ( __v2df ) __A , (


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { getTargetStreamer ( ) . emitCCTopFunction ( CurrentFnSym -> getName ( ) ) ; OutStreamer -> EmitLabel


<s> OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText


<s> return <NUM_LIT> ; } if ( AddrSpace == <ISA_LIT>AS :: PRIVATE_ADDRESS ) return <NUM_LIT> * ST -> getMaxPrivateElementSize ( ) ; return <NUM_LIT>


<s> bool UsedStack = false ; unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; <STR_LIT> ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , <NUM_LIT> , <NUM_LIT> , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UsedStack && Parts == <NUM_LIT> &&


<s> tree fndecl = add_builtin_function ( d -> name , nios2_ftype ( d -> ftype ) , i , BUILT_IN_MD , NULL , NULL ) ; nios2_register_builtin_fndecl ( i , fndecl ) ; } nios2_fpu_builtin_base = ARRAY_SIZE ( nios2_builtins


<s> bool supportsMultiplication ( ) const


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> return DAG . getMergeValues ( { Lo , Hi } ,


<s> if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> ) O << <STR_LIT> << Imm ; else O << getRegisterName ( Reg ) ; } else assert ( <NUM_LIT> && <STR_LIT>


<s> unsigned Slot = getSlot ( RegNo ) ; return Slot < StackTop && Stack [ Slot ]


<s> if ( ! is<ISA_LIT>64 ( ) ) return MatchOperand_NoMatch ; return parseRegs ( Operands , ( int ) <STR_LIT>


<s> ArgInfo . ImplicitBufferPtr = ArgDescriptor :: createRegister ( TRI . getMatchingSuperReg ( getNextUserSGPR ( ) , <STR_LIT> , & <STR_LIT> ) ) ; NumUserSGPRs +=


<s> SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op .

getOperand ( <NUM_LIT> ) , FIdx , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> if ( ! N0 -> hasOneUse ( ) || N0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * N0C = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; auto * N1C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! N0C || ! N1C ) return SDValue ( ) ; int64_t C0 = N0C -> getSExtValue ( ) ; int64_t C1 = N1C -> getSExtValue ( ) ; int64_t CA , CB ; if ( C0 == - <NUM_LIT> || C0 == <NUM_LIT> || C0 == <NUM_LIT> || isInt < <NUM_LIT> > ( C1 ) ) return SDValue ( ) ; if ( ( C1 / C0 ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 ) && isInt < <NUM_LIT> > ( C1 % C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 ) ) ) { CA = C1 / C0 ; CB = C1 % C0 ; } else if ( ( C1 / C0 + <NUM_LIT> ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 + <NUM_LIT> ) && isInt < <NUM_LIT> > ( C1 % C0 - C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 + <NUM_LIT> ) ) ) { CA = C1 / C0 + <NUM_LIT> ; CB = C1 % C0 - C0 ; } else if ( ( C1 / C0 - <NUM_LIT> ) != <NUM_LIT> && isInt < <NUM_LIT> > ( C1 / C0 - <NUM_LIT> ) && isInt < <NUM_LIT> > ( C1 % C0 + C0 ) && ! isInt < <NUM_LIT> > ( C0 * ( C1 / C0 - <NUM_LIT> ) ) ) { CA = C1 / C0 - <NUM_LIT> ; CB = C1 % C0 + C0 ; } else return SDValue ( ) ; SDLoc DL ( N


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { MachineFunction * MF = BB -> getParent ( ) ; unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy (


<s> if ( TARGET_P9_VECTOR ) return <NUM_LIT> ; if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return <NUM_LIT> ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , bool little , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>Default ) , IsLittle ( little ) , IsSoftFloat ( false ) , IsSingleFloat ( false ) , IsFPXX ( false ) , NoABICalls ( false ) , IsFP64bit ( false ) , UseOddSPReg ( true ) , IsNaN2008bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , HasCn<ISA_LIT> ( false ) , Has<ISA_LIT>3_32 ( false ) , Has<ISA_LIT>3_32r2 ( false ) , Has<ISA_LIT>4_32 ( false ) , Has<ISA_LIT>4_32r2 ( false ) , Has<ISA_LIT>5_32r2 ( false ) , In<ISA_LIT>16Mode ( false ) , In<ISA_LIT>16HardFloat ( <ISA_LIT>16HardFloat ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , HasDSPR3 ( false ) , AllowMixed16_32 ( Mixed16_32 | <ISA_LIT>_Os16 ) , Os16 ( <ISA_LIT>_Os16 ) , HasMSA ( false ) , UseTCCInDIV ( false ) , HasSym32 ( false ) , HasEVA ( false ) , DisableMadd4 ( false ) , HasMT ( false ) , StackAlignOverride ( StackAlignOverride ) , TM ( TM ) , TargetTriple ( TT ) , TSInfo ( ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( initializeSubtargetDependencies ( CPU , FS , TM ) ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( TM , * this ) ) { if ( <ISA_LIT>ArchVersion == <ISA_LIT>Default ) <ISA_LIT>ArchVersion = <ISA_LIT>32 ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 )

report_fatal_error ( <STR_LIT> , false ) ;


<s> if ( isa < MCSymbolRefExpr > ( Imm . Val ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ; if ( ! CE ) return false ; Val = CE -> getValue ( ) ; } else if ( isGPRMem ( ) ) { if ( ! Memory . OffsetImm || Memory .


<s> void setStackModelSourceRegs ( const MachineInstr * Target , const std :: vector < unsigned > &


<s> case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; const MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op2 = MI . getOperand ( <NUM_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( Op2 . isReg ( ) && ( Op2 . getReg ( ) == <STR_LIT> || Register :: isPhysicalRegister ( Op2 . getReg ( ) ) ) ) ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Ops ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) ) { Op = & Op1 ; } else if ( Op1 . isFI ( ) ) Op = & Op1 ; if ( Op && Op -> isReg ( ) && Op -> getReg ( ) == Op2 . getReg ( ) && Coef > <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( Coef + <NUM_LIT> ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; } else { if ( Op && Op2 . getReg ( ) != <STR_LIT> ) { int dwarfReg = TRI -> getDwarfRegNum ( Op2 . getReg ( ) , false ) ; if ( dwarfReg <


<s> bool <ISA_LIT>TargetLowering :: hasPairedLoad ( EVT LoadedType , unsigned & RequiredAligment ) const { if ( ! LoadedType . isSimple ( ) || ( ! LoadedType . isInteger ( ) && ! LoadedType . isFloatingPoint ( ) ) ) return false ; RequiredAligment = <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : Cond = Cond . getNode ( ) -> getOperand ( <NUM_LIT> ) ; addTest = false ; break ; } } } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; addTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , <STR_LIT> ) ; SDValue User = SDValue ( * Op . getNode ( ) -> use_begin ( ) , <NUM_LIT> ) ; if ( User . getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User . getOperand ( <NUM_LIT> ) ; SDValue NewBR = DAG . UpdateNodeOperands ( User , User . getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; Dest = FalseBB ; Chain = DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT>


<s> void <ISA_LIT>TargetLowering :: copyByValRegs ( SDValue Chain , SDLoc DL , std :: vector < SDValue > & OutChains , SelectionDAG & DAG , const <STR_LIT> & Flags , SmallVectorImpl < SDValue > & InVals , const Argument * FuncArg , unsigned FirstReg , unsigned LastReg , const CCValAssign & VA , <ISA_LIT>CCState & State ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned GPRSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; unsigned NumRegs = LastReg - FirstReg ; unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs ) return ; MVT RegTy = <STR_LIT> ( GPRSizeInBytes * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) { unsigned ArgReg = ByValArgRegs [ FirstReg + I


<s> case <NUM_LIT> : case <NUM_LIT> : { int ext = kind & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int shift2 = size - ext ; if ( ! currently_expanding_to_rtl && ! reload_in_progress && ! reload_completed ) { emit_insn ( gen_shl_sext_ext ( dest , source , left_rtx , size_rtx ) ) ; emit_insn ( gen_movsi ( dest , source ) ) ; break ; } if ( dest != source ) emit_insn ( gen_movsi ( dest , source ) ) ; operands [ <NUM_LIT> ] = dest ; if ( ext - insize ) { operands [ <NUM_LIT> ] = GEN_INT ( ext - insize ) ; gen_shifty_hi_op ( ASHIFT , operands ) ; } emit_insn ( kind & <NUM_LIT> ? gen_extendqisi2 ( dest , gen_lowpart ( QImode , dest ) ) : gen_extendhisi2 ( dest , gen_lowpart ( HImode , dest ) ) ) ; if ( kind <= <NUM_LIT> ) { if ( shift2 ) { operands [ <NUM_LIT> ] = GEN_INT ( shift2 ) ; gen_shifty_op ( ASHIFT , operands ) ; } } else { if ( shift2 > <NUM_LIT> ) { if ( EXT_SHIFT_SIGNED ( shift2 ) ) { operands [ <NUM_LIT> ] = GEN_INT ( shift2 + <NUM_LIT> ) ; gen_shifty_op ( ASHIFT , operands ) ; operands [ <NUM_LIT> ] = const1_rtx ; gen_shifty_op ( ASHIFTRT , operands ) ; break ; } operands [ <NUM_LIT> ] = GEN_INT ( shift2 ) ; gen_shifty_hi_op ( ASHIFT , operands ) ; } else if ( shift2 ) { operands [ <NUM_LIT> ] = GEN_INT ( - shift2 ) ; gen_shifty_hi_op ( LSHIFTRT , operands ) ; } emit_insn ( size <= <NUM_LIT> ? gen_extendqisi2 ( dest , gen_lowpart ( QImode , dest ) ) : gen_extendhisi2 ( dest , gen_lowpart ( HImode , dest ) ) ) ; } break ; } case <NUM_LIT> : { int i = <NUM_LIT> - size ; if ( ! currently_expanding_to_rtl && ! reload_in_progress && ! reload_completed ) emit_insn ( gen_shl_sext_ext


<s> void <ISA_LIT>BitcodeWriter :: writeDITemplateTypeParameter ( const DITemplateTypeParameter * N , SmallVectorImpl < uint64_t > & Record , unsigned Abbrev ) { Record . push_back ( N -> isDistinct ( ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getRawName ( ) ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getType ( )


<s> static void aarch64_emit_sve_invert_fp_cond ( rtx target , rtx_code code , rtx pred , bool known_ptrue_p , rtx op0 , rtx op1 ) { machine_mode pred_mode = GET_MODE ( pred ) ; rtx tmp = gen_reg_rtx


<s> arm_simd_polyTI_type_node = build_distinct_type_copy ( unsigned_intTI_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( arm_simd_polyTI_type_node , <STR_LIT> ) ; arm_simd_types [ Int8x8_t ] . eltype = intQI_type_node ; arm_simd_types [ Int8x16_t ] . eltype = intQI_type_node ; arm_simd_types [ Int16x4_t ] . eltype = intHI_type_node ; arm_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; arm_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; arm_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; arm_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; arm_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype


<s> return ( __m128 ) __builtin_ia32_maxps ( ( __v4sf )


<s> AU . addPreserved < PostDominatorTree > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage (


<s> ResNode = SelectLoad ( N ) ; break ; case <STR_LIT> : ResNode = SelectStore ( N ) ; break ; } if ( ResNode ) return ResNode ; return SelectCode (


<s> int Opc = Inst . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return true ; const MCRegisterInfo * MRI = getMRI ( ) ; const MCRegisterClass & VGRP32 = MRI -> getRegClass ( <STR_LIT> ) ; int Data0Pos = <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: data0 ) ; assert ( Data0Pos != - <NUM_LIT> ) ; auto Reg = Inst . getOperand ( Data0Pos ) .


<s> char * after ; unsigned fint = strtol ( rest + <NUM_LIT> , & after , <NUM_LIT> ) ; if ( after == rest + <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } TypeSize ScaleValue ( <NUM_LIT> , false ) ; unsigned Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = ScaleValue . isScalable ( ) ; unsigned Scale = ScaleValue . getKnownMinSize ( ) ; int64_t Offset = IsMulVL ? SOffset . getScalable ( ) : SOffset . getFixed ( ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , ScaleValue , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; Scale = ScaleValue . getKnownMinSize ( ) ; assert ( IsMulVL == ScaleValue . isScalable ( ) && <STR_LIT>


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> return StringRef ( Tok . Data , Tok .


<s> FunctionType * AsmFTy = FunctionType :: get ( Type :: getVoidTy ( C ) , AsmArgTypes , false ) ; InlineAsm * IA = InlineAsm :: get ( AsmFTy , AsmText , <STR_LIT> , true , false , InlineAsm :: AD_ATT ) ; CallInst :: Create ( IA , AsmArgs , <STR_LIT>


<s> } else { SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> mayStore ( ) ) { assert ( DstReg == <STR_LIT> && <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) RegList . push_back ( MI -> getOperand ( i ) . getReg ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm


<s> void ix86_split_xorsign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ <NUM_LIT> ] ; op0 = operands [ <NUM_LIT>


<s> assert ( ( Kind == k_Immediate ) && <STR_LIT> ) ; return Imm .


<s> StringRef storeName ( StringRef Name ) { std :: unique_ptr < std :: string > N = std :: make_unique < std :: string > ( Name ) ; Names . push_back ( std :: move ( N ) ) ; return * Names . back


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> auto * Op0 = dyn_cast < ConstantInt > ( CS . getArgument ( <NUM_LIT> ) ) ; if ( ! Op0 ) return CanCombine :: No ; auto * Op2 = dyn_cast < ConstantInt > ( CS . getArgument ( <NUM_LIT> ) ) ; if ( ! Op2 )


<s> if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) -> setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! IsPatchPoint ) { if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) ->


<s> break ; case SH_EXTRACT : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_INSERT : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_NOSWAP_LD : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_NOSWAP_ST : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_SPLAT : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_XXPERMDI : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_COPYWIDEN : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; } } if ( SwapVector [ EntryIdx ] . WebRejected ) DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SwapVector [ EntryIdx ] . WillRemove ) DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( )


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeCallTarget ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { MCFixupKind FixupKind = static_cast < MCFixupKind > ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return


<s> case ISA_EXT_FPU64 : return set1 -> fpu == ISA_EXT_FPU64 ; case ISA_EXT_FPU32 : return set1 -> fpu == ISA_EXT_FPU32 || set1 -> fpu == ISA_EXT_FPU64 ; case


<s> unsigned RetOpcode = MBBI -> getOpcode ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; switch ( RetOpcode ) { case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - <NUM_LIT> ; NumBytes = FrameSize - CSSize ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } else NumBytes = StackSize - CSSize ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI ->


<s> auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto & CondMI = * BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; ++ Count ; if ( FBB


<s> IRBuilder :: CreateSectionData ( * m_pscommon_1 ) ; m_pscommon_2 = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_PROGBITS , llvm :: ELF :: SHF_ALLOC | llvm :: ELF :: SHF_WRITE , <NUM_LIT> ) ; IRBuilder :: CreateSectionData ( * m_pscommon_2 ) ; m_pscommon_4 = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_PROGBITS , llvm :: ELF :: SHF_ALLOC | llvm :: ELF :: SHF_WRITE , <NUM_LIT> ) ; IRBuilder :: CreateSectionData ( * m_pscommon_4 ) ; m_pscommon_8 = pBuilder . CreateSection ( <STR_LIT> , LDFileFormat :: Target , llvm :: ELF :: SHT_PROGBITS , llvm :: ELF :: SHF_ALLOC | llvm :: ELF :: SHF_WRITE , <NUM_LIT> ) ; IRBuilder :: CreateSectionData ( *


<s> DIDescriptor Element = Elements . getElement ( i ) ; if ( Element . getTag ( ) == dwarf :: DW_TAG_subrange_type ) { TypeNo = TypeNo << <STR_LIT> ; TypeNo = TypeNo | <STR_LIT> ; DISubrange SubRange = DISubrange ( Element . getNode ( ) ) ; Dimension [ i ] = SubRange . getHi ( ) - SubRange . getLo ( ) + <NUM_LIT> ; Aux [ <NUM_LIT> + i * <NUM_LIT> + <NUM_LIT> ] = Dimension [ i ] ; Aux [ <NUM_LIT> + i * <NUM_LIT> + <NUM_LIT> ] = Dimension [ i ] >> <NUM_LIT> ; size = size * Dimension [ i ] ; } } HasAux = true ; Aux [ <NUM_LIT> ] = size & <NUM_LIT> ; Aux [ <NUM_LIT> ] =


<s> bool <ISA_LIT>Gfx10CacheControl :: enableNonTemporal ( const MachineBasicBlock


<s> static uint16_t set_kind ( uint16_t A , uint16_t K ) { return ( A & ~ KindMask


<s> ScheduleDAGMILive ( C , std :: move ( S ) ) , ST ( MF . getSubtarget < GCNSubtarget > ( ) ) , MFI ( * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ) , StartingOccupancy ( MFI . getOccupancy ( ) ) , MinOccupancy ( StartingOccupancy ) , Stage ( <NUM_LIT>


<s> rtx legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , enum machine_mode mode ) { rtx orig_x = x ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) , XEXP ( x , <NUM_LIT> ) ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ) ; if ( x != orig_x && legitimate_address_p ( mode , x , FALSE ) ) return x ; if ( SPARC_SYMBOL_REF_TLS_P ( x ) )


<s> return ; } if ( code == SMAX || code == SMIN ) c = GE ; else c = GEU ; if ( code == SMAX || code == UMAX ) target = emit_conditional_move ( dest , { c , op0 , op1 , mode } , op0 , op1 , mode , <NUM_LIT> ) ; else target = emit_conditional_move ( dest , { c , op0 , op1 , mode } , op1 , op0 , mode , <NUM_LIT> ) ; gcc_assert ( target ) ; if ( target != dest ) emit_move_insn ( dest ,


<s> void PHILinearize :: phiInfoElementSetDef ( PHIInfoElementT * Info , unsigned NewDef ) { Info -> DestReg =


<s> void decodeDfmtNfmt ( unsigned Format , unsigned & Dfmt , unsigned & Nfmt ) { Dfmt = ( Format >> DFMT_SHIFT ) & DFMT_MASK ; Nfmt = ( Format >> NFMT_SHIFT


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo


<s> HOST_WIDE_INT offset ; char buf [ <NUM_LIT> ] ; int i ; switch ( store_multiple_sequence ( operands , nops , regs , & base_reg , & offset ) ) { case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : strcpy ( buf , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } sprintf ( buf + strlen ( buf ) , <STR_LIT> , REGISTER_PREFIX , reg_names [ base_reg ] , REGISTER_PREFIX , reg_names [ regs [


<s> MachineRegisterInfo & getRegInfo ( Block & MBB ) { return MBB . getParent ( ) ->


<s> if ( * cum < <NUM_LIT> && <NUM_LIT> < * cum + ALPHA_ARG_SIZE ( mode , type , named ) ) words = <NUM_LIT> - * cum ; return words * UNITS_PER_WORD


<s> static SmallVector < int , <NUM_LIT> > getPSHUFShuffleMask ( SDValue N ) { MVT VT = N . getSimpleValueType ( ) ; SmallVector < int , <NUM_LIT> > Mask ; bool IsUnary ; bool HaveMask = getTargetShuffleMask ( N . getNode ( ) , VT , Mask , IsUnary ) ; ( void ) HaveMask ; assert ( HaveMask ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int LaneElts = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N . getOpcode ( ) ) { case <STR_LIT> : return Mask ; case <STR_LIT> : Mask . resize ( <NUM_LIT> ) ; return Mask ; case <STR_LIT> : Mask . erase ( Mask . begin ( ) , Mask . begin


<s> void printi8mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo ,


<s> auto BHR = TargetInstrInfo :: CreateTargetMIHazardRecognizer ( II , DAG ) ; MHR -> AddHazardRecognizer ( std :: unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ; return MHR


<s> rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; return gw_consumed_by_ex_dep_p ( consumer


<s> SDValue SizeNode = DAG . getIntPtrConstant ( Flags . getByValSize ( ) , dl ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign (

) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; if ( TLI . getNegatibleCost ( N2 , DAG , LegalOperations , CodeSize ) != TargetLowering :: NegatibleCost :: Cheaper ) return SDValue ( ) ; SDValue NegN2 = TLI . getNegatedExpression ( N2 , DAG


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) return DW_EH_PE_indirect | DW_EH_PE_pcrel | ( Model == CodeModel :: Small || Model == CodeModel :: Medium ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8 ) ; if ( Model == CodeModel :: Small || Model == CodeModel :: Medium ) return DW_EH_PE_udata4 ; return


( __v8si ) __C , ( unsigned char ) __imm , ( __mmask8 ) __U ) ;


<s> case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; return true ; case MachineOperand :: MO_BlockAddress : OutMO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; return true ; case MachineOperand ::


<s> static bool or1k_function_value_regno_p ( const unsigned int


<s> if ( ! IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) || TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA ) return ; auto & Streamer = getTargetStreamer ( ) -> getStreamer ( ) ; auto & Context = Streamer . getContext ( ) ; auto & ObjectFileInfo = * Context . getObjectFileInfo ( ) ; auto & ReadOnlySection = * ObjectFileInfo . getReadOnlySection ( ) ; Streamer . PushSection ( ) ; Streamer . SwitchSection ( & ReadOnlySection ) ; Streamer . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( ReadOnlySection . getAlignment ( ) < <NUM_LIT> ) ReadOnlySection . setAlignment ( <NUM_LIT> ) ; const MCSubtargetInfo & STI = MF -> getSubtarget ( ) ; SmallString < <NUM_LIT> > KernelName ; getNameWithPrefix ( KernelName , & MF ->


<s> bool has ( unsigned R ) const { unsigned Idx = v2x ( R ) ; if ( Idx >= Bits . size ( ) ) return false ; return Bits . test ( Idx


<s> uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> )


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool IsVolatile , bool AlwaysInline , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { auto & ST = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasBulkMemory ( ) )


<s> if ( ! Subtarget . isTargetLinux ( ) )

return TargetLowering :: useLoadStackGuardNode ( ) ;


<s> return ( __m128d ) __builtin_ia32_addsd ( ( __v2df )


<s> static DecodeStatus decodeBDXAddr64Disp12Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const MCDisassembler * Decoder ) { return decodeBDXAddr12Operand ( Inst , Field


<s> if ( ! getCell ( R1 , Inputs , LS1 ) || ! getCell ( R2 , Inputs , LS2 ) ) return false ; if ( LS1 . isProperty ( ) ) { if ( LS1 . properties ( ) & ConstantProperties :: Zero ) return ! ( Result = LS2 ) . isBottom ( ) ; return false ; } if ( LS2 . isProperty ( ) ) { if ( LS2 . properties ( ) & ConstantProperties :: Zero ) return ! ( Result = LS1 ) . isBottom ( ) ; return false


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveRegX ( unsigned Reg , int Offset ) { EmitARM64WinUnwindCode ( Win64EH :: UOP_SaveRegX


<s> static MCDisassembler * createThumbDisassembler ( const Target & T , const MCSubtargetInfo & STI


<s> if ( ( <STR_LIT> ) <STR_LIT> != getIntrinsicForGCCBuiltin ( <STR_LIT> , str . data ( ) ) ) return true ; return str . startswith (


<s> for ( ls = sr -> labeled_states ; ls ; ls = ls -> next ) { if ( ls -> label == label ) { free_state_stack ( & sr -> curr ) ; memcpy ( & sr -> curr , & ls -> saved_state , sizeof


<s> return & InstrInfo . getRegisterInfo


<s> EVT WidenedVT ; if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDLoc dl ( Op ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ResultLo = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0Lo , Op1Lo ) ; SDValue ResultHi = DAG . getNode ( Op . getOpcode ( ) , dl


<s> if ( Data != std :: end ( IntrinsicsWithChain ) && Data -> Id ==


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , VTs ,


<s> PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; return Return


<s> if ( nregs == <NUM_LIT> && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) { if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return mode ; else return SImode ; } else return choose_hard_reg_mode ( regno , nregs ,


<s> return Subtarget . is64Bit ( ) ? <STR_LIT>


<s> DiagnosticPredicate Res = DiagnosticPredicateTy :: NoMatch ; if ( ( Res = isExactFPImm < ImmA > ( ) ) ) return DiagnosticPredicateTy :: Match ; if ( ( Res = isExactFPImm < ImmB > ( ) )


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( mask ) > <NUM_LIT> && UINTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( UINTVAL ( mask ) >> UINTVAL ( shft_amnt ) ) + <NUM_LIT> ) >= <NUM_LIT> && ( UINTVAL ( mask ) & (

( HOST_WIDE_INT_1U << UINTVAL ( shft_amnt ) ) - <NUM_LIT> ) ) == <NUM_LIT> ;


<s> void arm_reload_in_hi ( rtx * operands ) { rtx ref = operands [ <NUM_LIT> ] ; rtx base , scratch ; HOST_WIDE_INT offset = <NUM_LIT> ; if ( SUBREG_P ( ref ) ) { offset = SUBREG_BYTE ( ref ) ; ref = SUBREG_REG ( ref ) ; } if ( REG_P ( ref ) ) { if ( reg_equiv_mem ( REGNO ( ref ) ) ) { ref = reg_equiv_mem ( REGNO ( ref ) ) ; base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; } else base = reg_equiv_address ( REGNO ( ref ) ) ; if ( base == NULL ) { gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movsi ( gen_rtx_SUBREG ( SImode , operands [ <NUM_LIT> ] , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , ref , <NUM_LIT> ) ) ) ; return ; } } else base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; if ( GET_CODE ( base ) == MINUS || ( GET_CODE ( base ) == PLUS && ! CONST_INT_P ( XEXP ( base , <NUM_LIT> ) ) ) ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; emit_set_insn ( base_plus , base ) ; base = base_plus ; } else if ( GET_CODE ( base ) == PLUS ) { HOST_WIDE_INT hi , lo ; offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; base = XEXP ( base , <NUM_LIT> ) ; lo = ( offset >= <NUM_LIT> ? ( offset & <NUM_LIT> ) : - ( ( - offset ) & <NUM_LIT> ) ) ; if ( lo == <NUM_LIT> ) lo &= <NUM_LIT> ; hi = ( ( ( ( offset - lo ) & ( HOST_WIDE_INT ) <NUM_LIT> ) ^ ( HOST_WIDE_INT ) <NUM_LIT> ) - ( HOST_WIDE_INT ) <NUM_LIT> ) ; gcc_assert ( hi + lo == offset ) ; if ( hi != <NUM_LIT> ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; emit_insn ( gen_addsi3 ( base_plus , base , GEN_INT ( hi ) ) ) ; base = base_plus ; offset = lo ; } } if ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) scratch = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ]


<s> return ( __m256 ) __builtin_ia32_expandloadsf256_maskz ( ( __v8sf * ) __P , (


<s> static bool aarch64_reads_global_state_p ( aarch64_simd_builtin_datum * d ) { unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_READ_FPCR ) return true ; return flags &


<s> return __aarch64_vset_lane_any ( __elem ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; BI -> dump ( ) ; ) ; if ( BI -> getOpcode ( ) == <STR_LIT> ) { MI = BI ; continue ; } if ( MI ) { for ( auto & MO : BI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } } if ( ! MI ) return ; MI -> setDesc ( HII -> get


<s> Out . EmitCodeAlignment ( kNaCl<ISA_LIT>InstructionBundleSize ) ; Out . EmitLabel ( RetTarget ) ; } else { Out . EmitBundleLock ( true ) ; MCInst CALLInst ; CALLInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; CALLInst . addOperand ( Op ) ; Out . EmitInstruction ( CALLInst , STI ) ; Out . EmitBundleUnlock


<s> static __inline unsigned long long sh_media_MSUB_W ( unsigned long long mm , unsigned long long mn ) { typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_subv4hi3 ( ( v4hi ) mm , ( v4hi )


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT


<s> if ( TII -> isDS ( Inst ) && TII -> usesLGKM_CNT ( Inst ) ) { if ( TII -> isAlwaysGDS ( Inst . getOpcode ( ) ) || TII -> hasModifiersSet ( Inst , <STR_LIT> :: gds ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_ACCESS , Inst ) ; ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_GPR_LOCK , Inst ) ; } else { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; } } else if ( TII -> isFLAT ( Inst ) ) { assert ( Inst . mayLoadOrStore ( ) ) ; int FlatASCount = <NUM_LIT> ; if ( mayAccessVMEMThroughFlat ( Inst ) ) { ++ FlatASCount ; if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( Inst . mayLoad ( ) && ! <ISA_LIT>InstrInfo :: isAtomicNoRet ( Inst ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; } if ( mayAccessLDSThroughFlat ( Inst ) ) { ++ FlatASCount ; ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; } assert ( FlatASCount ) ; if ( FlatASCount > <NUM_LIT> ) ScoreBrackets ->


<s> return decodeRegisterClass ( Inst , RegNo ,


<s> assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT>


<s> Inst . addOperand ( MCOperand :: CreateReg ( Mem . Base ) ) ; addExpr ( Inst , Mem . Disp


<s> initialize<ISA_LIT>CTRLoopsVerifyPass ( * PassRegistry :: getPassRegistry


<s> bool requiresRegisterScavenging ( const MachineFunction &


<s> AsmToken :: TokenKind kind = getLexer ( ) . getKind ( ) ; switch ( kind ) { default : return true ; case AsmToken :: Minus : case AsmToken :: Integer : if ( getParser ( ) . parseExpression (


<s> const Function & F = MF -> getFunction ( ) ; for ( Function :: const_arg_iterator I = F . arg_begin ( ) , E = F . arg_end ( ) ; I != E ; I


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getConstant ( CC , DL , <STR_LIT> ) , LHS , RHS , Dest ) ; return Cmp


<s> SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; SmallVector < const GlobalVariable * , <NUM_LIT> > Globals ; DenseSet < const GlobalVariable * > GVVisited ; DenseSet < const GlobalVariable * > GVVisiting ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E =


<s> virtual BitVector getReservedRegs ( const MachineFunction &


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const DataLayout DL = DAG . getDataLayout ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL )


<s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const auto * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; return RegInfo -> needsStackRealignment ( MF


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; unsigned FramePtrReg = FuncInfo -> getFrameOffsetReg ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL ; bool NeedFP = hasFP ( MF ) ; if ( NeedFP ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( StackPtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } uint32_t NumBytes = MFI . getStackSize ( ) ; if ( NumBytes != <NUM_LIT> && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( NumBytes * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const <ISA_LIT>MachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg . VGPR , true , Reg . FI . getValue ( )

, & <STR_LIT> , & TII -> getRegisterInfo ( ) ) ;


<s> static bool isImageOrSamplerVal ( const Value * arg , const Module * context ) { static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Type * Ty = arg -> getType ( ) ; auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy ) return false ; if ( ! context ) return false ; auto * STy = dyn_cast < StructType >


<s> int size = bytesize ( type , BLKmode ) ; if ( TARGET_IVC2 && VECTOR_TYPE_P ( type ) ) return size


<s> } Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: Address P = pReloc . place ( ) ; if ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) S = helper_get_PLT_address ( * pReloc . symInfo ( ) , pParent ) ; Relocator :: DWord X =


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups


<s> if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { switch ( op ) { case EQ : case NE : case UNORDERED : case ORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : return CCFPmode ; case LT : case LE : case GT : case GE : case LTGT : return CCFPEmode ; default : gcc_unreachable ( ) ; } } else if ( ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == NEG || GET_CODE ( x ) == ASHIFT ) && y == const0_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXNZmode ; else return CCNZmode ; } else { if ( GET_CODE ( x ) == NOT && y == constm1_rtx ) { if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXCmode ; else return CCCmode ; } if ( ! TARGET_ARCH64 && GET_MODE ( x ) == DImode ) { if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , <NUM_LIT> ) == UNSPEC_ADDV || XINT ( y , <NUM_LIT> ) == UNSPEC_SUBV || XINT ( y ,

<NUM_LIT> ) == UNSPEC_NEGV ) ) return CCVmode ;


<s> if ( ! getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz


<s> unsigned getRegisterBitWidth ( bool Vector )


<s> if ( aarch64_bitmask_imm ( val_in , mode ) ) return false ; if ( aarch64_move_imm ( val_in , mode ) ) return


<s> void addFPImmf64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( Kind == Float ) Inst . addOperand ( MCOperand :: createDFPImm ( bit_cast < uint64_t > ( Flt .


<s> MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getSubtarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align )


<s> bool <ISA_LIT>InstrInfo :: isIndirectL4Return ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> if ( & vStream == & nulls ( ) ) loggerFn = <NUM_LIT> ; int ret = decodeInstruction ( & internalInstr , regionReader , ( const void * ) & region , loggerFn , ( void * ) & vStream , ( const void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; } else { size = internalInstr . length ; return ( ! translateInstruction ( instr , internalInstr , this )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned


<s> return getStandardCSEConfigForOpt ( TM -> getOptLevel


<s> bool <ISA_LIT>DAGToDAGISel :: SelectLogicalImm ( SDValue N , SDValue & Imm ) { uint32_t Bits ; uint32_t RegWidth = N . getValueType ( ) . getSizeInBits ( ) ; ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ; if ( ! CN ) return false ; if ( ! A64Imms :: isLogicalImm ( RegWidth , CN -> getZExtValue ( ) , Bits ) ) return false ; Imm = CurDAG -> getTargetConstant ( Bits , <STR_LIT>


<s> } if ( ! GVar ) { llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; } const Type * Ty = cast < PointerType > ( GV -> getType ( ) ) -> getElementType ( ) ; if ( ! Ty -> isSized ( ) || isZeroLengthArray ( Ty ) ) { errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } SDValue base = getGlobalAddressWrapper ( GA , GV , DAG ) ; const TargetData * TD = TM . getTargetData ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; SDValue offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BuildGetId ( DAG , dl )

, DAG . getConstant ( Size , <STR_LIT> ) ) ;


<s> unsigned Shift = getShiftExtendAmount ( ) ; return getShiftExtendType ( ) == <STR_LIT> && ( Shift == <NUM_LIT> || Shift == <NUM_LIT> || Shift == <NUM_LIT> ||


<s> addPass ( & PostRAHazardRecognizerID ) ; addPass ( create<ISA_LIT>InsertWaitsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( create<ISA_LIT>LowerControlFlowPass (


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Subtarget . hasMSA ( ) || ! ResTy . is128BitVector ( ) ) return SDValue ( ) ; if ( Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) && SplatBitSize <= <NUM_LIT> ) { if ( SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> && SplatBitSize != <NUM_LIT> ) return SDValue ( ) ; if ( ResTy . isInteger ( ) && ! HasAnyUndefs && SplatValue . isSignedIntN ( <NUM_LIT> ) ) return Op ; EVT ViaVecTy ; switch ( SplatBitSize ) { default : return SDValue ( ) ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : return SDValue ( ) ; } SDValue Result = DAG . getConstant ( SplatValue , DL , ViaVecTy ) ; if ( ViaVecTy != ResTy ) Result = DAG . getNode ( <STR_LIT> , SDLoc ( Node ) , ResTy , Result ) ; return Result ; } else if ( isSplatVector ( Node ) ) return Op ; else if ( ! isConstantOrUndefBUILD_VECTOR ( Node ) ) { EVT ResTy = Node -> getValueType (


<s> bool LookupPresent = false ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineBasicBlock :: iterator mi = MBB . begin ( ) , me = MBB . end ( ) ; mi != me ; mi ++ ) { LookupPresent |= ( <ISA_LIT>II :: isLookup ( ( * mi ) . getDesc ( ) ) || <ISA_LIT>II :: isLookupC ( ( * mi ) . getDesc ( ) ) ) ; } } if ( ! LookupPresent ) { auto firstInst = MF -> getBlockNumbered ( <NUM_LIT> ) -> instr_begin ( ) ; MachineInstr * cacheIns = MF -> CreateMachineInstr ( TII -> get ( <STR_LIT> ) , firstInst -> getDebugLoc ( ) , true ) ; cacheIns -> addOperand ( * MF , MachineOperand :: CreateImm (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> VectorType * VTy = cast < VectorType > ( II . getType ( ) ) ; auto * DupXIntrI = dyn_cast < IntrinsicInst > ( OpIndices ) ; if ( ! DupXIntrI || DupXIntrI -> getIntrinsicID ( ) != <STR_LIT> ) return None ; auto * SplatValue = dyn_cast < ConstantInt > ( DupXIntrI -> getOperand ( <NUM_LIT> ) ) ; if ( ! SplatValue || SplatValue -> getValue ( ) . uge ( VTy -> getElementCount ( ) . getKnownMinValue ( ) ) ) return None ; IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; auto * Extract = Builder . CreateExtractElement ( OpVal , SplatValue ) ; auto * VectorSplat = Builder . CreateVectorSplat ( VTy -> getElementCount (


<s> TII -> legalizeOperandsVOP3 ( MRI , MI ) ; if ( const MCOperandInfo * OpInfo = MI . getDesc ( ) . OpInfo ) { unsigned Opc = MI . getOpcode ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; for ( auto I : { <STR_LIT> ( Opc , <STR_LIT> :: src0 ) , <STR_LIT> ( Opc , <STR_LIT> :: src1 ) } ) { if ( I == - <NUM_LIT> ) break ; MachineOperand & Op = MI . getOperand ( I ) ; if ( ( OpInfo [ I ] . RegClass != llvm :: <STR_LIT> && OpInfo [ I ] . RegClass != llvm :: <STR_LIT> ) || ! Register :: isVirtualRegister ( Op . getReg ( ) ) || ! TRI -> isAGPR ( MRI , Op . getReg ( ) ) ) continue ; auto * Src = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Src || ! Src -> isCopy ( ) || ! TRI -> isSGPRReg ( MRI , Src -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; auto * RC = TRI -> getRegClassForReg ( MRI , Op . getReg ( ) ) ; auto * NewRC = TRI -> getEquivalentVGPRClass ( RC ) ; MRI . setRegClass ( Op . getReg ( ) , NewRC ) ; } } return ; } int NoRetAtomicOp = <STR_LIT> ( MI . getOpcode (


<s> MCSubtargetInfo & STI = copySTI ( ) ; std :: vector < std :: string > ArchFeatures ( <ISA_LIT>Features . begin ( ) , <ISA_LIT>Features . end ( ) ) ; STI . setDefaultFeatures ( <STR_LIT> , <STR_LIT> , join ( ArchFeatures . begin ( ) , ArchFeatures . end ( ) , <STR_LIT> ) ) ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; ExpandCryptoAEK ( ID , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name !=


<s> break ; case <STR_LIT> : Type = <STR_LIT> ; break ; default : return false ; } unsigned FusedOpcode = TII -> getFusedCompare ( Compare . getOpcode ( ) , Type , & Compare ) ; if ( ! FusedOpcode ) return false ; Register SrcReg = Compare . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg2 = Compare . getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare . getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( ( Type == <STR_LIT> || Type == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> ) SrcNOps = <NUM_LIT> ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; for ( unsigned I = <NUM_LIT> ; I < SrcNOps ; I ++ ) MIB . add ( Compare . getOperand ( I ) ) ; MIB . add ( CCMask ) ; if ( Type == <STR_LIT> ) { MIB . add ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } if ( Type == <STR_LIT> ) { MIB . add ( Target ) ; MIB . addRegMask ( RegMask ) ; } MBBI = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) { MBBI -> clearRegisterKills ( SrcReg , TRI ) ; if ( SrcReg2 ) MBBI -> clearRegisterKills ( SrcReg2 , TRI ) ; } FusedComparisons += <NUM_LIT> ; return


<s> MI . setDesc ( get ( IsHigh ? HighOpcode : LowOpcode ) ) ; if ( IsHigh && ConvertHigh ) MI . getOperand ( <NUM_LIT> ) . setImm ( uint32_t ( MI . getOperand ( <NUM_LIT> ) . getImm


<s> rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; num_use_regs = Re - Rb + <NUM_LIT> + <NUM_LIT> ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + <NUM_LIT> ) ) ; par_index = <NUM_LIT> ; offset = - ( num_use_regs * <NUM_LIT> ) ; for ( regno = Rb ; regno <= Re ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( mem , reg ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) =


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_nested_too_deep ( void * const TM_buff ) { texasru_t texasru = * _TEXASRU_PTR (


<s> MCTargetStreamer * llvm :: create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S , OS


<s> TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |=


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else llvm_unreachable (


<s> for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ; dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned ( BBI . Unalign ) << <STR_LIT> <<

unsigned ( BBI . PostAlign ) << format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> EmitAllAutos ( M ) ; printLibcallDecls ( ) ; DbgInfo . EndModule


<s> } else { assert ( MO . isExpr ( ) && <STR_LIT> ) ; MO . getExpr ( ) -> print ( O ,


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT>


<s> const SetOfInstructions & getLOHRelated


<s> static void x86_print_call_or_nop ( FILE * file


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { assert ( MI . getDesc ( ) . isBranch (


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Val = - CE ->


<s> case IC_MINUS : Val = Op1 . second - Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_MULTIPLY : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = Op1 . second * Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_DIVIDE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; assert ( Op2 . second != <NUM_LIT> && <STR_LIT> ) ; Val = Op1 . second / Op2 . second ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; } } } assert ( OperandStack . size ( ) == <NUM_LIT> && <STR_LIT> ) ; return OperandStack . pop_back_val (


<s> unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op


<s> MachineInstr * DefMI = getForwardingDefMI ( MI , ForwardingOperand , SeenIntermediateUse ) ; if ( ! DefMI ) return false ; assert ( ForwardingOperand < MI . getNumOperands ( ) && <STR_LIT> ) ; bool IsForwardingOperandKilled = MI . getOperand ( ForwardingOperand ) . isKill ( ) ; bool KillFwdDefMI = ! SeenIntermediateUse && IsForwardingOperandKilled ; if ( KilledDef && KillFwdDefMI ) * KilledDef = DefMI ; if ( RI . getMappedIdxOpcForImmOpc ( MI . getOpcode ( ) ) != <STR_LIT> && transformToNewImmFormFedByAdd ( MI , * DefMI , ForwardingOperand ) ) return true ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; bool HasImmForm = instrHasImmForm ( MI . getOpcode ( ) , IsVFReg , III ,


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( RC -> hasType ( <STR_LIT> ) && <STR_LIT> ) ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) { setUsesTOCBasePtr ( * MBB -> getParent ( ) ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } unsigned BaseReg ; if ( MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; else BaseReg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( BaseReg ) . addImm ( BPOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin


<s> if ( auto * A = dyn_cast < const Argument > ( V ) ) return IsKernelFn && A -> onlyReadsMemory ( ) && A -> hasNoAliasAttr ( ) ; if ( auto * GV = dyn_cast < const GlobalVariable > (


<s> for ( i = <NUM_LIT> ; i < last_alg ; i ++ ) if ( ( stringop_alg ) i != rep_prefix_8_byte || TARGET_64BIT ) candidates . safe_push ( stringop_alg_names [ i ] ) ; char * s ; const char * hint = candidates_list_and_hint ( alg_name , s , candidates ) ; if ( hint ) inform ( input_location , <STR_LIT> , opt , s , hint ) ; else inform ( input_location , <STR_LIT> , opt , s ) ; XDELETEVEC ( s ) ; return ; } if ( ( stringop_alg ) i == rep_prefix_8_byte && ! TARGET_64BIT ) { error ( <STR_LIT> <STR_LIT> , alg_name , opt ) ; return ; } input_ranges [ n ] . max = maxs ; input_ranges [ n ] . alg = ( stringop_alg ) i ; if ( ! strcmp ( align , <STR_LIT> ) ) input_ranges [ n ] . noalign = false ; else if ( ! strcmp ( align , <STR_LIT> ) ) input_ranges [ n ] . noalign = true ; else { error ( <STR_LIT> , align , opt ) ; return ; } n ++ ; curr_range_str = next_range_str ; } while ( curr_range_str ) ; if ( input_ranges [ n - <NUM_LIT> ]


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: EXEC ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; Reserved . set ( AMDGPU :: FLAT_SCR ) ; return


<s> assert ( ( Val & IS_VGPR ) == <NUM_LIT> ) ; return decodeSrcOp ( OPW128 , Val |


<s> return <STR_LIT> ; case NE : return <STR_LIT> ; case GT : return <STR_LIT> ; case GTU : return <STR_LIT> ; case LT : return <STR_LIT> ; case LTU : return <STR_LIT> ; case GE : return <STR_LIT> ; case GEU : return <STR_LIT> ; case LE : return <STR_LIT> ; case LEU : return <STR_LIT> ; case PLUS : return <STR_LIT> ; case MINUS : return


<s> AM . Base . Reg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , N -> getDebugLoc ( ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , <NUM_LIT> ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable (


<s> return std :: make_pair ( <NUM_LIT> , & AMDGPU :: SGPR_32RegClass ) ; } } if ( Constraint . size ( ) > <NUM_LIT> ) { const TargetRegisterClass * RC = nullptr ; if ( Constraint [ <NUM_LIT> ] == 'v' ) { RC = & AMDGPU :: VGPR_32RegClass ; } else if ( Constraint [ <NUM_LIT> ] == 's' ) { RC = & AMDGPU ::


<s> uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true ; } ; for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; return false ; } } Predicated . insert ( MI ) ; } SmallSet < Register , <NUM_LIT> > LiveOuts ; SmallVector < MachineBasicBlock * , <NUM_LIT> > ExitBlocks ; ML . getExitBlocks ( ExitBlocks ) ; for ( auto * MBB : ExitBlocks ) for ( const MachineBasicBlock :: RegisterMaskPair & RegMask : MBB -> liveins ( ) ) if ( QPRs -> contains ( RegMask . PhysReg ) ) LiveOuts . insert ( RegMask . PhysReg ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveMIs ; assert ( ML . getNumBlocks ( ) == <NUM_LIT> &&


<s> return instAccessReg ( MI -> defs ( ) ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg


<s> std :: set < unsigned > SeenColors ; if ( DAGSize <= <NUM_LIT> ) return ; PreviousColor = CurrentColoring [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { SUnit * SU = & DAG -> SUnits [ i ] ; unsigned CurrentColor = CurrentColoring [ i ] ; unsigned PreviousColorSave = PreviousColor ; assert ( i == SU -> NodeNum ) ; if ( CurrentColor != PreviousColor ) SeenColors . insert ( PreviousColor ) ; PreviousColor =


<s> RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; } } } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ; } <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT>


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return &


<s> unsigned int old = * mask , ret , new ; while ( <NUM_LIT> ) { if ( old == <NUM_LIT> ) return - <NUM_LIT> ; ret = old & - old ; new = old & ~ ret ; new = __sync_val_compare_and_swap ( mask , old , new ) ; if ( old == new ) break


<s> return <STR_LIT> ( ( Imm >> <NUM_LIT> ) & <NUM_LIT>


<s> ReverseIter End = MBB -> rend ( ) ; ReverseIter Br = getNonDebugInstr ( MBB -> rbegin ( ) , End ) ; auto it = MBB -> begin ( ) ; for ( ; it != MBB -> end ( ) ; ++ it ) { if ( & * it == & * Br ) break ; } if ( ( Br != End ) && ! Br -> isIndirectBranch ( ) && ( Br -> isConditionalBranch ( ) ||

( Br -> isUnconditionalBranch ( ) && IsPIC ) ) ) MBBInfos [ I ] . Br = & * it ;


<s> unsigned ValueEnumerator :: getInstructionID ( const Instruction * Inst ) const { InstructionMapType :: const_iterator I = InstructionMap . find ( Inst ) ; assert ( I != InstructionMap . end ( ) && <STR_LIT> ) ; return I ->


<s> case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , static_cast < EVT > ( <STR_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo


<s> bool isMemImm0_1020s4Offset ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue (


<s> if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return Match_rGPR ; case MCK_GPRPair : if ( Op . isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) . contains ( Op . getReg ( ) ) ) return Match_Success ; break ; } return Match_InvalidOperand


<s> auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; assert ( TPC && <STR_LIT> ) ; auto & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; if ( EnableEH && TM . Options . ExceptionModel == ExceptionHandling :: Wasm ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; ThrewGV = getGlobalVariable ( M , getAddrIntType ( & M ) , TM , <STR_LIT> ) ; ThrewValueGV = getGlobalVariable ( M , IRB . getInt32Ty ( ) , TM , <STR_LIT> ) ; GetTempRet0Func = getEmscriptenFunction ( FunctionType :: get ( IRB . getInt32Ty ( ) , false ) , <STR_LIT> , & M ) ; SetTempRet0Func = getEmscriptenFunction ( FunctionType :: get ( IRB . getVoidTy ( ) , IRB . getInt32Ty ( ) , false ) , <STR_LIT> , & M ) ; GetTempRet0Func -> setDoesNotThrow ( ) ; SetTempRet0Func -> setDoesNotThrow ( ) ; bool Changed = false ; if ( EnableEH ) { FunctionType * ResumeFTy = FunctionType :: get ( IRB . getVoidTy ( ) , IRB . getInt8PtrTy ( ) , false ) ; ResumeF = getEmscriptenFunction ( ResumeFTy , <STR_LIT> , & M ) ; FunctionType * EHTypeIDTy = FunctionType :: get ( IRB . getInt32Ty ( ) , IRB . getInt8PtrTy ( ) , false ) ; EHTypeIDF = getEmscriptenFunction ( EHTypeIDTy , <STR_LIT> , & M ) ; } if ( DoSjLj ) { FunctionType * FTy = FunctionType :: get ( IRB . getVoidTy ( ) , { getAddrIntType ( & M ) , IRB . getInt32Ty ( ) } , false ) ; EmLongjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ; if ( SetjmpF ) { FunctionType * SetjmpFTy = SetjmpF -> getFunctionType ( ) ; FTy = FunctionType :: get ( Type :: getInt32PtrTy ( C ) , { SetjmpFTy -> getParamType ( <NUM_LIT> ) , IRB . getInt32Ty ( ) , Type ::

getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } , false ) ;


<s> OSABI ( OSABI ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>XCOFFObjectWriter ( bool Is64Bit ) { return std :: make_unique < <ISA_LIT>XCOFFObjectWriter


<s> FunctionPass * llvm :: create<ISA_LIT>CollectLOHPass


<s> case <NUM_LIT> : break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset (


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS ,


<s> TTI :: MemCmpExpansionOptions Options ; Options . LoadSizes = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Options . MaxNumLoads = TLI -> getMaxExpandSizeMemcmp ( OptSize ) ; return Options


<s> static machine_mode counter_mode ( rtx count_exp ) { if ( GET_MODE ( count_exp ) != VOIDmode ) return GET_MODE ( count_exp ) ; if ( ! CONST_INT_P ( count_exp ) ) return Pmode ; if ( TARGET_64BIT && ( INTVAL ( count_exp ) &


<s> void <ISA_LIT>InstPrinter :: printRegisterName ( unsigned RegNo , raw_ostream & O ) { O << <STR_LIT> ; O << getRegisterName (


<s> DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT , DAG . getRegister ( is64Bit ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Base , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; unsigned char OperandFlags = <NUM_LIT> ; unsigned WrapperKind = <STR_LIT> ; if ( model == TLSModel :: LocalExec ) { OperandFlags = is64Bit ? <STR_LIT> : <STR_LIT> ; } else if ( is64Bit ) { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else { assert ( model == TLSModel :: InitialExec ) ; OperandFlags = <STR_LIT> ; } SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; SDValue Offset = DAG . getNode ( WrapperKind , dl , PtrVT , TGA ) ; if ( model == TLSModel :: InitialExec ) Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Offset , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false ,


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> <STR_LIT> :: IsaVersion ISA = <STR_LIT> :: getIsaVersion ( getFeatureBits ( ) ) ; getTargetStreamer ( ) . EmitDirectiveHSACodeObjectISA ( ISA . Major , ISA . Minor , ISA . Stepping , <STR_LIT> , <STR_LIT> ) ; return false ; } if ( ParseDirectiveMajorMinor ( Major , Minor ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( ParseAsAbsoluteExpression ( Stepping ) ) return TokError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: String ) ) return TokError ( <STR_LIT> ) ; VendorName = getLexer ( ) . getTok ( ) . getStringContents ( ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma )


<s> adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> <<


<s> void WaitcntBrackets :: setExpScore ( const MachineInstr * MI , const <ISA_LIT>InstrInfo * TII , const <ISA_LIT>RegisterInfo * TRI , const MachineRegisterInfo * MRI , unsigned OpNo , unsigned Val ) { RegInterval Interval = getRegInterval ( MI , TII , MRI , TRI ,


<s> bool hasDot4Insts ( ) const { return HasDot4Insts


<s> if ( checkForImmediate ( * InitVal , Imm ) ) return ( EndVal -> getImm ( ) == Imm ) ; Register Reg = InitVal -> getReg ( ) ; if ( ! Reg . isVirtual ( ) ) return true ; MachineInstr * Def = MRI -> getVRegDef ( Reg ) ; if ( ! Def ) return true ; if ( Def -> isPHI ( ) && ! phiMayWrapOrUnderflow ( Def , EndVal , Def -> getParent ( ) , L , LoopFeederPhi ) ) return false ; if ( Def -> isCopy ( ) && ! loopCountMayWrapOrUnderFlow ( & ( Def -> getOperand ( <NUM_LIT> ) ) , EndVal , Def -> getParent ( ) , L , LoopFeederPhi ) ) return false ; for ( MachineRegisterInfo :: use_instr_nodbg_iterator I = MRI -> use_instr_nodbg_begin ( Reg ) , E = MRI -> use_instr_nodbg_end ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; Register CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int CmpMask = <NUM_LIT> , CmpValue


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO .


<s> else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> gcc_assert ( ok ) ; if ( parts . base && GET_CODE ( parts . base ) == SUBREG ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && GET_CODE ( parts . index ) == SUBREG ) parts . index = SUBREG_REG ( parts . index ) ; base = parts . base ; index = parts . index ; disp = parts . disp ; len = <NUM_LIT> ; if ( base && ! index && ! disp ) { if ( addr == stack_pointer_rtx || addr == arg_pointer_rtx || addr == frame_pointer_rtx || addr == hard_frame_pointer_rtx ) len = <NUM_LIT> ; } else if ( disp && ! base && ! index ) len = <NUM_LIT> ; else { if ( disp ) { if ( GET_CODE ( disp ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL

( disp ) , 'K' ) && base ) len = <NUM_LIT> ;


<s> bool <ISA_LIT>TargetELFStreamer :: EmitCodeEnd ( ) { const uint32_t Encoded_s_code_end = <NUM_LIT> ; MCStreamer & OS = getStreamer ( ) ; OS . PushSection ( ) ; OS . emitValueToAlignment ( <NUM_LIT> , Encoded_s_code_end , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) OS .


<s> Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length =


<s> std :: tie ( CC , SwapArgs ) = <STR_LIT> ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; unsigned LHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; unsigned OpCmp ; LLT Ty = MRI . getType ( LHS ) ; switch ( Ty . getSizeInBits ( ) ) { default : return false ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF )


<s> Error ( FnStartLoc , <STR_LIT> ) ; return true ; } FnStartLoc = L ; getTargetStreamer ( ) . emitFnStart ( ) ; return false


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { print<ISA_LIT>Operands ( Operands ) ; MCInst Inst ; unsigned MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( MatchResult ) { default : break ; case Match_Success : { Inst . setLoc ( IDLoc ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT>


<s> static bool isCalleeSavedRegister ( unsigned Reg , const MCPhysReg * CSRegs ) { for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) if ( Reg == CSRegs [ i ] ) return true ; return


<s> Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : case <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr =


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction


<s> bool <ISA_LIT>Operand :: isGPRIdxMode


<s> auto Instr = Builder . buildInstr ( <STR_LIT> , { MI . getOperand ( <NUM_LIT> ) , & <STR_LIT> } , { } ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Instr , TII , TRI , RBI ) ) return false ; MI . eraseFromParent


<s> unsigned int calculate_ratio ( unsigned int sew , enum vlmul_type vlmul ) { unsigned int ratio ; switch ( vlmul ) { case LMUL_1 : ratio = sew ; break ; case LMUL_2 : ratio = sew / <NUM_LIT> ; break ; case


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( )


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) ,


<s> void <ISA_LIT>BaseRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx

) . addImm ( <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> int64_t v = Op2 . getImm ( ) ; bool Valid = false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Valid = ( isUInt < <NUM_LIT> > ( v ) || v == - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Valid = isUInt < <NUM_LIT> > ( v ) ; break ; case <STR_LIT> : case <STR_LIT> : Valid = ( v == <NUM_LIT> ) ; break ; } if ( ! Valid ) return false ; } unsigned cmpReg1 , cmpOp2 = <NUM_LIT> ; cmpReg1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( secondReg ) { cmpOp2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( cmpReg1 == cmpOp2 ) return false ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! Register :: isPhysicalRegister ( cmpOp2 ) ) { MachineInstr * def = MRI . getVRegDef ( cmpOp2 ) ; if ( def -> getOpcode ( ) == TargetOpcode :: COPY ) return false ; } } ++ II ; for ( MachineBasicBlock :: iterator localII = II ; localII != end ; ++ localII ) { if ( localII -> isDebugInstr ( ) ) continue ; if ( ! commonChecksToProhibitNewValueJump ( optLocation , localII ) ) return false ; if ( localII -> modifiesRegister ( pReg , TRI ) || localII -> readsRegister ( pReg , TRI ) ) return false ; if ( localII -> modifiesRegister ( cmpReg1 , TRI ) || ( secondReg && localII -> modifiesRegister ( cmpOp2 , TRI ) ) ) return false ; } return


<s>
bool
<ISA_LIT>AsmParser
::
MatchAndEmitATTInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
assert
(
!
Operands
.
empty
(
)
&&
<STR_LIT>
)
;
<ISA_LIT>Operand
&
Op
=
static_cast
<
<ISA_LIT>Operand
&
>
(
*
Operands
[
<NUM_LIT>
]
)
;
assert
(
Op
.
isToken
(
)
&&
<STR_LIT>
)
;
SMRange
EmptyRange
=
;
MatchFPUWaitAlias
(
IDLoc
,
Op
,
Operands
,
Out
,
MatchingInlineAsm
)
;
bool
WasOriginallyInvalidOperand
=
false
;
MCInst
Inst
;
switch
(
MatchInstruction
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
,
isParsingIntelSyntax
(
)
)
)
{
default
:
llvm_unreachable
(
<STR_LIT>
)
;
case
Match_Success
:
if
(
!
MatchingInlineAsm
)
while
(
processInstruction
(
Inst
,
Operands
)
)
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
!
MatchingInlineAsm
)
EmitInstruction
(
Inst
,
Operands
,
Out
)
;
Opcode
=
Inst
.
getOpcode
(
)
;
return
false
;
case
Match_MissingFeature
:
return
ErrorMissingFeature
(
IDLoc
,
ErrorInfo
,
MatchingInlineAsm
)
;
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
.
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
.
setTokenValue
(
Tmp
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
uint64_t
ErrorInfoIgnore
;
uint64_t
ErrorInfoMissingFeature
=
<NUM_LIT>
;
unsigned
Match
[
<NUM_LIT>
]
;
for
(
unsigned
I
=
<NUM_LIT>
,
E
=
array_lengthof
(
Match
)
;
I
!=
E
;
++
I
)
{
Tmp
.
back
(
)
=
Suffixes
[
I
]
;
Match
[
I
]
=
MatchInstruction
(
Operands
,
Inst

, ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; auto & MDT = getAnalysis <


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { return


<s> Parser . Lex ( ) ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Plus ) ) { Parser . Lex ( ) ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Real ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } APFloat RealVal ( APFloat :: IEEEdouble , Parser . getTok ( ) . getString ( ) ) ; if ( Negative ) RealVal . changeSign ( ) ; double DblVal = RealVal . convertToDouble ( ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( DblVal , S , E


<s> if ( ! ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && ! usePrecSqrtF32 ( ) ) ) ) return SDValue ( ) ; if ( ExtraSteps == ReciprocalEstimate :: Unspecified ) ExtraSteps = <NUM_LIT> ; SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; bool Ftz = useF32FTZ ( DAG . getMachineFunction ( ) ) ; auto MakeIntrinsicCall = [ & ] ( <STR_LIT>


<s> static MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) { MCContext & Ctx = AP . OutContext ; const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr (


<s> static SDValue performST1Combine ( SDNode * N , SelectionDAG & DAG ) { SDLoc DL ( N ) ; SDValue Data = N -> getOperand ( <NUM_LIT> ) ; EVT DataVT = Data . getValueType ( ) ; EVT HwSrcVt = getSVEContainerType ( DataVT ) ; SDValue InputVT = DAG . getValueType ( DataVT ) ; if ( DataVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDValue SrcNew


<s> long double __extenddfxf2 ( double d ) { register union double_long dl ; register union long_double_long ldl ; register long exp ; dl . d = d ; if ( ! dl . l . upper && ! dl . l


<s> static bool isInlineValue ( unsigned Reg ) { switch ( Reg ) { case


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_GPR ) && <STR_LIT> ) ; AsmParser . warnIfAssemblerTemporary ( RegIdx . Index ,


<s> <ISA_LIT>GenInstrInfo :: MachineOutlinerInfo <ISA_LIT>InstrInfo :: getOutlininingCandidateInfo ( std :: vector < std :: pair < MachineBasicBlock :: iterator , MachineBasicBlock :: iterator >> & RepeatedSequenceLocs ) const { unsigned CallID = MachineOutlinerDefault ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumInstrsForCall = <NUM_LIT> ; unsigned NumInstrsToCreateFrame = <NUM_LIT> ; auto DoesntNeedLRSave = [ this ] ( std :: pair < MachineBasicBlock :: iterator , MachineBasicBlock :: iterator > & I ) { return canOutlineWithoutLRSave ( I . second ) ; } ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isTerminator ( ) ) { CallID = MachineOutlinerTailCall ; FrameID = MachineOutlinerTailCall ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT> ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , DoesntNeedLRSave ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT> ; } return MachineOutlinerInfo ( NumInstrsForCall , NumInstrsToCreateFrame , CallID


<s> void <ISA_LIT>MCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M


<s> if ( MRI . hasOneNonDBGUse ( DefReg ) || MI . getParent ( ) -> getParent ( ) -> getFunction ( ) . hasOptSize ( ) ) return true ; if ( ! STI . hasLSLFast


<s> } else if ( CSKY_TARGET_ARCH ( CK801 ) ) { sorry ( <STR_LIT> ) ; } else { fprintf ( f , <STR_LIT> , reg_names [ CSKY_T1_REGNUM ] ) ; fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ; fprintf ( f , <STR_LIT> , reg_names [ CSKY_T1_REGNUM ] ) ; fprintf ( f , <STR_LIT> ) ; } fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f


<s> if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == <STR_LIT> ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) return true ; return ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || ( ! MO . isImplicit ( ) && ( <STR_LIT> .

contains ( MO . getReg ( ) ) || <STR_LIT> . contains ( MO . getReg ( ) ) ) ) ) ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < LiveVariables > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachineLoopInfo >


<s> unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . InRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . ResultReg = ResultReg ; CLI . NumResultRegs = <NUM_LIT> ; } return true


<s> const <ISA_LIT>Subtarget & getSubtarget ( ) const { return *


<s> P . Addr -> init ( ) ; P . Addr -> setAttrs


<s> type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node )