<s> if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask ( RepeatedMask ) ) { SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue CastV2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; SDValue ShufPS = lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , CastV1 , CastV2 , DAG ) ; return DAG . getBitcast ( <STR_LIT> , ShufPS ) ; } if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2

, Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable (


<s> for ( regno = <NUM_LIT> ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! TARGET_NEON ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= <NUM_LIT> ; rshift /= <NUM_LIT> ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = <NUM_LIT> ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM +


<s> if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next , & load_mem ) && is_store_insn ( insn , & str_mem ) && DEP_TYPE ( dep ) == REG_DEP_TRUE && mem_locations_overlap ( str_mem , load_mem ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false


<s> if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF


<s> arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return


<s> <ISA_LIT>AssemblerImpl :: ~ <ISA_LIT>AssemblerImpl (


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( __A , <NUM_LIT> ) ; b = vec_splat ( __B , <NUM_LIT> ) ; c = a /


<s> virtual const <ISA_LIT>ompactSubtarget * getSubtargetImpl ( ) const { return & Subtarget


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ; PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ; initializeScalarToIRFPassPass ( Registry ) ; initializeGlobalResolverPass ( Registry


<s> if ( isGFX10Plus ( * STI ) && STI -> getFeatureBits ( ) . test ( FeatureCuMode ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( MemOpndSlot + i ) , LabelOffset ) ; else MIB . add ( MI . getOperand ( MemOpndSlot + i ) ) ; } if ( ! UseImmLabel ) MIB . addReg ( LabelReg ) ; else MIB . addMBB ( restoreMBB ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; MIB . addRegMask ( RegInfo -> getNoPreservedMask ( ) ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( restoreMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , mainDstReg ) ; mainMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( mainDstReg ) . addMBB ( mainMBB ) . addReg ( restoreDstReg ) . addMBB ( restoreMBB ) ; if ( RegInfo -> hasBasePointer ( * MF ) ) { const bool Uses64BitFramePtr = Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FI -> setRestoreBasePointer ( MF ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * MF ) ; unsigned BasePtr = RegInfo -> getBaseRegister ( ) ; unsigned Opm = Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( restoreMBB , DL , TII -> get ( Opm ) , BasePtr ) , FramePtr , true , <ISA_LIT>FI -> getRestoreBasePointerOffset ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } BuildMI ( restoreMBB , DL , TII -> get ( <STR_LIT> ) , restoreDstReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( restoreMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB


<s> static unsigned Get<ISA_LIT>RegNum ( const


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { APInt SubMask = APInt :: getSplat ( VWidth , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; APInt AddMask = APInt :: getSplat ( VWidth , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; bool IsSubOnly = DemandedElts . isSubsetOf ( SubMask ) ; bool IsAddOnly = DemandedElts . isSubsetOf ( AddMask ) ; if ( IsSubOnly || IsAddOnly ) { assert ( ( IsSubOnly ^ IsAddOnly ) && <STR_LIT> ) ; IRBuilderBase :: InsertPointGuard Guard ( IC . Builder ) ; IC . Builder . SetInsertPoint ( & II ) ; Value * Arg0 = II . getArgOperand ( <NUM_LIT> ) , * Arg1 = II . getArgOperand ( <NUM_LIT> ) ; return IC . Builder . CreateBinOp ( IsSubOnly ? Instruction :: FSub : Instruction :: FAdd , Arg0 , Arg1 ) ; } simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; UndefElts &= UndefElts2 ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto * Ty0 = II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; unsigned InnerVWidth = cast < FixedVectorType > ( Ty0 ) -> getNumElements ( ) ; assert ( VWidth == ( InnerVWidth * <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = Ty0 -> getPrimitiveSizeInBits ( ) / <NUM_LIT> ; unsigned VWidthPerLane = VWidth / NumLanes ; unsigned InnerVWidthPerLane = InnerVWidth / NumLanes ; for ( int OpNum = <NUM_LIT> ; OpNum != <NUM_LIT> ; ++ OpNum ) { APInt OpDemandedElts ( InnerVWidth , <NUM_LIT> ) ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { unsigned LaneIdx = Lane * VWidthPerLane ; for ( unsigned Elt = <NUM_LIT> ; Elt != InnerVWidthPerLane ; ++ Elt ) { unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum ; if ( DemandedElts [ Idx ] ) OpDemandedElts . setBit ( ( Lane * InnerVWidthPerLane ) + Elt ) ; } } APInt OpUndefElts ( InnerVWidth , <NUM_LIT> ) ; simplifyAndSetOp ( & II , OpNum , OpDemandedElts , OpUndefElts ) ; OpUndefElts = OpUndefElts . zext ( VWidth ) ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { APInt LaneElts = OpUndefElts . lshr ( InnerVWidthPerLane * Lane ) ; LaneElts = LaneElts . getLoBits ( InnerVWidthPerLane ) ; LaneElts <<= InnerVWidthPerLane * ( <NUM_LIT> * Lane + OpNum ) ; UndefElts |= LaneElts ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> NewSense NS = { PR , false , false , True } ; return


<s> bool <ISA_LIT>ExpandSDMA :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB (


<s> while ( TmpReg <= RegNo ) { if ( ( ( ( TmpReg < <STR_LIT> ) || ( TmpReg > <STR_LIT> ) ) && ! isGP64bit ( ) ) || ( ( ( TmpReg < <STR_LIT> ) || ( TmpReg > <STR_LIT> ) ) && isGP64bit ( ) ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } PrevReg = TmpReg ; Regs . push_back ( TmpReg ++ ) ; } } RegRange = false ; } else { if ( ( PrevReg == <STR_LIT> ) && ( ( isGP64bit ( ) && ( RegNo != <STR_LIT> ) && ( RegNo != <STR_LIT> ) ) || ( ! isGP64bit ( ) && ( RegNo != <STR_LIT> ) && ( RegNo != <STR_LIT> ) ) ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( ! ( ( ( RegNo == <STR_LIT> || RegNo == <STR_LIT> || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) && ! isGP64bit ( ) ) || ( ( RegNo == <STR_LIT> || RegNo == <STR_LIT> || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) && isGP64bit ( ) ) ) ) { Error ( E ,


<s> if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Function * Caller = CI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( TM , * Caller ) ; Changed |= ST . makeLIDRangeMetadata ( CI ) ; } return Changed


<s> MachineBasicBlock * MBB = nullptr ; if ( Stage > InitialSchedule ) { if ( ! LIS ) break ; if ( Stage == UnclusteredReschedule ) { if ( RescheduleRegions . none ( ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } if ( Stage == ClusteredLowOccupancyReschedule ) { if ( StartingOccupancy <= MinOccupancy ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MinOccupancy << <STR_LIT> ) ; S . setTargetOccupancy ( MinOccupancy ) ; } } if ( Stage == UnclusteredReschedule ) SavedMutations . swap ( Mutations ) ; for ( auto Region : Regions ) { if ( Stage == UnclusteredReschedule && ! RescheduleRegions [ RegionIdx ] ) { ++ RegionIdx ; continue ; } RegionBegin = Region . first ; RegionEnd = Region . second ; if ( RegionBegin -> getParent ( ) != MBB ) { if ( MBB ) finishBlock ( ) ; MBB = RegionBegin -> getParent ( ) ; startBlock ( MBB ) ; if ( Stage == InitialSchedule ) computeBlockPressure ( MBB ) ; } unsigned NumRegionInstrs = std :: distance ( begin ( ) , end ( ) ) ; enterRegion ( MBB , begin ( ) , end ( ) , NumRegionInstrs ) ; if ( begin ( ) == end ( ) || begin ( ) == std :: prev ( end ( ) ) ) { exitRegion ( ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MF . getName ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> << * begin ( ) << <STR_LIT> ; if ( RegionEnd != MBB -> end ( ) ) dbgs ( ) << * RegionEnd ; else dbgs ( ) << <STR_LIT>


<s> if ( CondReg == <NUM_LIT> ) return false ; unsigned TrueReg = getRegForValue ( Select -> getTrueValue ( ) ) ; if ( TrueReg == <NUM_LIT> ) return false ; unsigned FalseReg = getRegForValue ( Select -> getFalseValue ( ) ) ; if ( FalseReg == <NUM_LIT> ) return false ; if ( Not ) std :: swap ( TrueReg , FalseReg ) ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( Select -> getType ( ) ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT>


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & FS , bool is64Bit ) : IsV9 ( false ) , V8DeprecatedInsts ( false ) , IsVIS ( false ) , Is64Bit ( is64Bit ) { const char * CPU = <STR_LIT> ; if ( is64Bit ) { CPU = <STR_LIT>


<s> static unsigned int riscv_min_arithmetic_precision


<s> void addRegOperands ( MCInst & Inst , unsigned N


<s> } seq = emit_insn ( seq ) ; } else { seq = emit_insn ( seq ) ; RTX_FRAME_RELATED_P ( seq ) = <NUM_LIT> ; } return seq


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDValue N , SDValue & Base , SDValue & Disp ) { <ISA_LIT>ISelAddressMode AM ; if ( MatchAddress ( N , AM ) ) return false ; EVT VT = N . getValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , N -> getDebugLoc ( ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> ,


<s> TrapInfo TI = cast < GlobalAddressSDNode > ( Op ) -> getTrapInfo ( ) ; return LowerGlobalAddress ( GV , SDLoc ( Op )


<s> <ISA_LIT>Instr PI ( MCII , STI , & ID ,


<s> if ( ! TARGET_FPRS || ! TARGET_HARD_FLOAT ) return false ; if ( TARGET_SINGLE_FLOAT && mode == SFmode ) return true ; if ( TARGET_DOUBLE_FLOAT && mode == DFmode ) return true ; if ( is_complex_IBM_long_double ( mode ) )


<s> unsigned Reg ; const <ISA_LIT>Subtarget & Subtarget = State . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isTargetELF ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else if ( Subtarget . isTargetXPLINK64 ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Offset = Reg ? <NUM_LIT> : State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; for ( auto & It : PendingMembers ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( Offset ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true


<s> } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { MachineInstr * Cmp ; CmpInst :: Predicate Pred ; std :: tie ( Cmp , Pred ) = emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; if ( ! Cmp ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; } else { <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; unsigned CmpOpc = selectFCMPOpc ( * CondDef , MRI ) ; if ( ! CmpOpc ) return false ; auto Cmp = MIB . buildInstr ( CmpOpc , { } , { CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; if ( CmpOpc != <STR_LIT> && CmpOpc != <STR_LIT> ) Cmp . addUse ( CondDef -> getOperand ( <NUM_LIT> ) . getReg


<s> DOUT << <STR_LIT> << idx ; idx = ( idx - GOToffset ) * <NUM_LIT> ; DOUT << <STR_LIT> << idx << <STR_LIT> ; break ; case <STR_LIT> : idx = ( unsigned char * ) MR -> getResultPointer ( ) - & GOTBase [ GOToffset * <NUM_LIT> ] ; idx = getLower16 ( idx ) ; DOUT << <STR_LIT> << idx << <STR_LIT> ; DOUT << <STR_LIT> << ( void * ) MR -> getResultPointer ( ) << <STR_LIT> << ( void * ) & GOTBase [ GOToffset * <NUM_LIT> ] << <STR_LIT> ; break ; case <STR_LIT> : idx = ( unsigned char * ) MR -> getResultPointer ( ) - & GOTBase [ GOToffset * <NUM_LIT> ] ; idx = getUpper16 ( idx ) ; DOUT << <STR_LIT> << idx << <STR_LIT> ; DOUT << <STR_LIT> << ( void * ) MR -> getResultPointer ( ) << <STR_LIT> << ( void * ) & GOTBase [ GOToffset * <NUM_LIT> ] << <STR_LIT> ; break ; case <STR_LIT> : switch ( * RelocPos >>


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue Target = N -> getOperand ( <NUM_LIT> ) ; EVT CompareTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDVTList CompareVT = CurDAG -> getVTList ( CompareTys


<s> break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: Alloca : { const AllocaInst * A = cast < AllocaInst > ( V ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( A ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Disp ) ) { AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; Disp += SL -> getElementOffset ( cast < ConstantInt > ( Op ) -> getZExtValue ( ) ) ; continue ; } uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) . first ; if ( IndexReg == <NUM_LIT> ) return


<s> SDValue Cvt = DAG . getNode ( Opcode , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; return ; } } break ; } case <STR_LIT> : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( <STR_LIT> ) ) { LHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; SelectVT = <STR_LIT> ; } SDValue NewSelect = DAG . getNode ( <STR_LIT> , SL , SelectVT , N -> getOperand ( <NUM_LIT> ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( <STR_LIT> , SL , NewVT , NewSelect ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , VT , NewSelect


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL


<s> unsigned <ISA_LIT>InstrInfo :: loadImmediate ( unsigned FrameReg , int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II

, const DebugLoc & DL , unsigned & NewImm ) const {


<s> bool <ISA_LIT>AsmParser :: reportParseError ( SMLoc Loc , Twine


<s> AsmToken <ISA_LIT>AsmParser :: peekToken ( ) { return isToken ( AsmToken :: EndOfStatement ) ? getToken (


<s> if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return false ; if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return true ; assert ( false && <STR_LIT> ) ; return


<s> TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target (


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { return VRegs . empty


<s> if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) .

end ( ) ) ( * annotationCache ) [ m ] [ gv ] = tmp ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , * Ctx . getRegisterInfo


<s> e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; if ( fkind != SUBROUTINE ) return <NUM_LIT> ; if ( TARGET_OMIT_LEAF_FRAME_POINTER && ! current_function_is_leaf ) return <NUM_LIT> ; return <NUM_LIT>


<s> unsigned s3 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned const9 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const9


<s> unsigned NumElts = InVT . getVectorNumElements ( ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl ( Op )


<s> return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_SaveList


<s> enum attr_type insn_type , dep_insn_type ; int dep_insn_code_number ; if ( REG_NOTE_KIND ( link ) != <NUM_LIT> ) return <NUM_LIT> ; dep_insn_code_number = recog_memoized ( dep_insn ) ; if ( dep_insn_code_number < <NUM_LIT> || recog_memoized ( insn ) < <NUM_LIT> ) return cost ; insn_type = get_attr_type ( insn ) ; dep_insn_type = get_attr_type ( dep_insn ) ; if ( dep_insn_type == TYPE_MOVE || dep_insn_type


<s> MachineFunctionInfo ( ) , ShaderType ( ShaderType :: COMPUTE ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT> ) , IsKernel


<s> __v2df result = ( __v2df ) __A ; double db = __B ; result [ <NUM_LIT> ]


<s> unsigned last_fixed_arg = ArgLocs . size ( ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ArgLocs . size ( ) ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT ObjectVT = VA . getValVT ( ) ; switch ( ObjectVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Ins [ i ] . Used && ( ! isVarArg || i != last_fixed_arg ) ) { if ( arg_idx < <NUM_LIT> ) arg_idx ++ ; else stack_offset += <NUM_LIT> ; InVals . push_back ( DAG . getUNDEF ( ObjectVT ) ) ; } else if ( arg_idx < <NUM_LIT> && ( ! isVarArg || i != last_fixed_arg ) ) { unsigned arg_reg = VA . getLocReg ( ) ; reg = RegInfo . createVirtualRegister ( & GPRegsRegClass ) ; MF . getRegInfo ( ) . addLiveIn ( arg_reg , reg ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , dl , reg , <STR_LIT> ) ; if ( ObjectVT != <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg ,


<s> Parser . Lex ( ) ; MCSymbol * Func = getParser ( ) . getContext ( ) . GetOrCreateSymbol ( Name ) ; getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Func ) ; return false


<s> using namespace <ISA_LIT> ; static const MCPhysReg GuestReg64DecoderTable [ ] = { G1_0 , <NUM_LIT> , G3_2 , <NUM_LIT> , G5_4 , <NUM_LIT> , G7_6 , <NUM_LIT> , G9_8 , <NUM_LIT> , G11_10 , <NUM_LIT> , G13_12 , <NUM_LIT> , G15_14 , <NUM_LIT> , G17_16 , <NUM_LIT> , G19_18 , <NUM_LIT> , G21_20 , <NUM_LIT> , G23_22 , <NUM_LIT> , G25_24 , <NUM_LIT> , G27_26 , <NUM_LIT> , G29_28 , <NUM_LIT> , G31_30 , <NUM_LIT> } ; if ( RegNo >= array_lengthof ( GuestReg64DecoderTable ) ) return MCDisassembler :: Fail ; if ( GuestReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GuestReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg


<s> SDValue NewSP = Op . getOperand ( <NUM_LIT> ) ; SDValue Backchain ; SDLoc DL ( Op ) ; if ( StoreBackchain ) { SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , Regs -> getStackPointerRegister ( ) , <STR_LIT> ) ; Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP , DAG ) , MachinePointerInfo ( ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , Regs -> getStackPointerRegister ( ) , NewSP ) ; if ( StoreBackchain ) Chain = DAG . getStore ( Chain , DL , Backchain , getBackchainAddress ( NewSP , DAG ) , MachinePointerInfo ( ) ) ; return Chain


<s> unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> && RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return false ; if ( Count == <NUM_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; if ( RISBG . Rotate == <NUM_LIT> ) { bool PreferAnd = false ; if ( VT == <STR_LIT> ) PreferAnd = true ; else if ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) PreferAnd = true ; else if ( auto * Load = dyn_cast < LoadSDNode > ( RISBG . Input ) ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ; N = New .


<s> Register PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT>


<s> Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; return true ; case <STR_LIT> : if ( ! areOperandsOfVmullHighP64 ( II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ) return false ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 -> getOperand ( <NUM_LIT> ) , Ext2 -> getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I ->


<s> DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeBitpOperand ( Inst , Op2 , Address , Decoder ) ; return S


<s> assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT ElVT = VT . getVectorElementType ( ) ; int Factor = VT . getSizeInBits ( ) / <NUM_LIT> ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT ) ; if ( isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > (


<s> int const_uint32_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= <NUM_LIT> && INTVAL ( op


<s> int fma_forest :: get_target_parity ( ) { return this ->


<s> if ( CInfo . Kind == <ISA_LIT>PreserveFieldInfoAI ) VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; else VarType = Type :: getInt64Ty ( BB -> getContext ( ) ) ; GV = new GlobalVariable ( M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , AccessKey ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , TypeMeta ) ; GEPGlobals [ AccessKey ] = GV ; } else { GV = GEPGlobals [ AccessKey ] ; } if ( CInfo . Kind == <ISA_LIT>PreserveFieldInfoAI ) { auto * LDInst = new LoadInst ( Type :: getInt32Ty ( BB -> getContext ( ) ) , GV ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , LDInst ) ; Call -> replaceAllUsesWith ( LDInst ) ; Call -> eraseFromParent ( ) ; return true ; } auto * LDInst = new LoadInst ( Type :: getInt64Ty (


<s> break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr = gen_rtx_MEM ( mode , addr ) ; if ( pm == PM_read ) res = gen_rtx_SET ( addr , reg ) ; else if ( pm == PM_write ) res = gen_rtx_SET ( reg , addr ) ; else gcc_unreachable ( ) ; if ( data -> ptr ) { start_sequence ( ) ; emit_insn ( res ) ; emit_insn ( gen_adddi3 ( data -> ptr , data -> ptr , GEN_INT ( GET_MODE_SIZE ( GET_MODE ( reg )


<s> static int completed = <NUM_LIT> ; if ( completed ) return ; if ( __deregister_frame_info ) __deregister_frame_info ( __EH_FRAME_BEGIN__


<s> Inst . addOperand ( MCOperand :: CreateReg ( XRegs [ getReg


<s> return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant ( IID ,


<s> MCRegister getSCSPReg ( ) { return <STR_LIT>


<s> initialize_trampoline ( TRAMP , FNADDR , CXT ) { { ARG_POINTER_REGNUM , STACK_POINTER_REGNUM } , \ { ARG_POINTER_REGNUM , FRAME_POINTER_REGNUM

} , \ { FRAME_POINTER_REGNUM , STACK_POINTER_REGNUM } }


<s> rtx aarch64_simd_vect_par_cnst_half ( machine_mode mode , bool high ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits / <NUM_LIT> ) ; int high_base = nunits / <NUM_LIT> ; int low_base = <NUM_LIT> ; int base ; rtx t1 ; int i ; if ( BYTES_BIG_ENDIAN ) base = high ? low_base


<s> for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( R -> getOperandUse ( <NUM_LIT> ) , PromotablePHINodes , Bool2IntMap ) ; if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return


<s> Lex ( ) ; int NbArgs = MCLOHIdToNbArgs ( Kind ) ; assert ( NbArgs != - <NUM_LIT> && <STR_LIT> ) ; SmallVector < MCSymbol * , <NUM_LIT> > Args ; for ( int Idx = <NUM_LIT> ; Idx < NbArgs ; ++ Idx ) { StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; Args . push_back ( getContext ( ) . GetOrCreateSymbol ( Name ) ) ; if ( Idx + <NUM_LIT> == NbArgs ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> + Twine ( IDVal ) + <STR_LIT> ) ; Lex ( ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> + Twine ( IDVal ) + <STR_LIT> ) ; getStreamer ( ) . EmitLOHDirective ( ( MCLOHType ) Kind , Args


<s> if ( Minimal ) return false ; if ( producesStall ( MI ) ) return false ; auto & HST = MI . getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( HST . isTinyCoreWithDuplex ( ) && CurrentPacketMIs . size ( ) > <NUM_LIT> && ! PacketHasDuplex ) { for ( auto & MJ : CurrentPacketMIs ) PacketHasSLOT0OnlyInsn |= HII -> isPureSlot0 ( * MJ ) ; int Opcode = HII -> getDuplexOpcode ( MI , false ) ; if ( Opcode >= <NUM_LIT>


<s> SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Zero , Zero , Zero , Zero } ; return CurDAG -> SelectNodeTo ( N , Opc ,


<s> const VOPInfo * Info = getVOP1OpcodeHelper ( Opc ) ; return Info ? Info -> IsSingle


<s> return getSTI ( ) . getFeatureBits ( ) [


<s> bool <ISA_LIT>Operand :: isSDWAInt16Operand ( ) const { return isSDWAOperand ( <STR_LIT>


<s> MachineOperand * MO = getCallTargetRegOpnd ( MI ) ; if ( ! MO ) return false ; Reg = MO -> getReg ( ) ; Val = <NUM_LIT> ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * DefMI = MRI . getVRegDef ( Reg ) ; assert ( DefMI ) ; if ( ! DefMI -> mayLoad ( ) || DefMI -> getNumOperands ( ) < <NUM_LIT> ) return true ; unsigned Flags = DefMI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( Flags != <STR_LIT> && Flags != <STR_LIT> ) return true ; assert ( DefMI -> hasOneMemOperand ( ) ) ; Val = ( * DefMI -> memoperands_begin (


<s> ASM_OUTPUT_ALIGN ( asm_out_file , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; } for ( i = <NUM_LIT> ; i < n_deferred_plabels ; i ++ ) { targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER

( deferred_plabels [ i ] . internal_label ) ) ;


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_SReg_128 ( unsigned Val ) const { return decodeSrcOp ( OPW128 , Val )


<s> else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 ) && <STR_LIT> ) ; else assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 ) && <STR_LIT> ) ; } bool CloseParen = <ISA_LIT>MCExpr :: printVariantKind ( O , TF ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm8OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT>


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> return ( __m64 ) __builtin_ia32_punpckldq ( ( __v2si ) __m1 , (


<s> bool OffsetIsScalable ; if ( ! MI . mayLoadOrStore ( ) || ! getMemOperandWithOffsetWidth ( MI , Base , Offset , OffsetIsScalable , Width , & RI ) || ( Base -> isReg ( ) && Base -> getReg ( ) != <STR_LIT> ) ) continue ; TypeSize Scale ( <NUM_LIT> , false ) ; int64_t Dummy1 , Dummy2 ; MachineOperand & StackOffsetOperand = getMemOpBaseRegImmOfsOffsetOperand ( MI ) ; assert ( StackOffsetOperand . isImm ( ) && <STR_LIT> ) ; getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ; assert ( Scale != <NUM_LIT> && <STR_LIT> ) ; assert ( ! OffsetIsScalable


<s> bool processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( auto & MI : MBB ) { if ( ! hasTOCLoReloc ( MI


<s> const MachineOperand & BaseReg = MI -> getOperand ( Op ) ; const MachineOperand & IndexReg = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; bool HasParenPart = IndexReg . getReg ( ) || HasBaseReg ; if ( DispSpec . isImm ( ) ) { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ! HasParenPart ) O << DispVal ; } else { assert ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) ; printSymbolOperand ( MI -> getOperand ( Op + <NUM_LIT> ) ) ; } if ( HasParenPart ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; O << '(' ; if ( HasBaseReg ) printOperand ( MI , Op , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ; printOperand ( MI , Op + <NUM_LIT> , Modifier ) ; unsigned ScaleVal = MI -> getOperand ( Op + <NUM_LIT> ) . getImm ( ) ; if ( ScaleVal != <NUM_LIT> ) O << ',' << ScaleVal ; } O << ')'


<s> ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI -> mayLoadOrStore ( ) && <STR_LIT> ) ; unsigned MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) continue ; MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg


<s> unsigned Opc = N -> getMachineOpcode ( ) ; switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++


<s> __builtin_ia32_storedqusi512_mask ( ( int * ) __P , ( __v16si ) __A ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = getFMA3Group ( MI . getOpcode ( ) , MI . getDesc ( ) . TSFlags ) ; if ( FMA3Group ) return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , FMA3Group -> isIntrinsic ( ) ) ; if ( <STR_LIT> ( Desc . TSFlags ) ) { unsigned CommutableOpIdx1 = Desc . getNumDefs ( ) + <NUM_LIT> ; unsigned CommutableOpIdx2 = Desc . getNumDefs ( ) + <NUM_LIT> ; if ( ( MI . getDesc ( ) . getOperandConstraint ( Desc . getNumDefs ( ) , MCOI :: TIED_TO ) != - <NUM_LIT> ) ) { if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } else { -- CommutableOpIdx1 ; } } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; if ( ! MI . getOperand ( SrcOpIdx1 ) . isReg ( ) || ! MI . getOperand ( SrcOpIdx2 ) . isReg ( ) ) return false ; return true ; } return TargetInstrInfo :: findCommutedOpIndices ( MI ,


<s> msgpack :: DocNode & getRootMetadata ( StringRef Key ) { return HSAMetadataDoc -> getRoot ( ) . getMap


<s> auto MBBStart = MBB -> instr_rend ( ) ; for ( int i = <NUM_LIT> ; ( i < SearchBound ) && ( MI != MBBStart ) ; ++ i , ++ MI ) for ( auto & Op : MI -> implicit_operands ( ) ) if ( ( Op . getReg ( ) == <STR_LIT> ) && ( Op . isDef ( ) ) ) return & * MI ; return nullptr


<s> else if ( Opcode == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else return false ; if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } EvenReg = Op0 -> getOperand ( <NUM_LIT>


<s> void <ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & IsResolved ) { IsResolved =


<s> if ( isSMRD ( * FirstLdSt ) && isSMRD ( * SecondLdSt ) ) return true ; return ( isMUBUF ( * FirstLdSt ) || isMTBUF ( * FirstLdSt ) ) && ( isMUBUF ( * SecondLdSt ) || isMTBUF (


<s> bool hasStdExtZhinx ( ) const { return


<s> if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , Hi ) ; } Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasLazyResolverStub ( GV , TM ) ) return Lo ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Lo , NULL , <NUM_LIT> , false ,


<s> machine_mode mode ; gcc_assert ( TARGET_SSE ) ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || const0_operand ( x , mode ) ) { switch ( get_attr_mode ( insn ) ) { case MODE_XI : return <STR_LIT> ; case MODE_OI : return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; case MODE_TI : return ( TARGET_AVX512VL ? <STR_LIT> : <STR_LIT> ) ; case MODE_V8DF : return ( TARGET_AVX512DQ ? <STR_LIT> : <STR_LIT> ) ; case MODE_V4DF : return <STR_LIT> ; case MODE_V2DF : return <STR_LIT> ; case MODE_V16SF : return ( TARGET_AVX512DQ ? <STR_LIT> : <STR_LIT> ) ; case MODE_V8SF : return <STR_LIT> ; case MODE_V4SF : return <STR_LIT> ; default : gcc_unreachable ( ) ; } } else if ( x == constm1_rtx || vector_all_ones_operand ( x , mode ) ) { enum attr_mode insn_mode = get_attr_mode ( insn ) ; switch ( insn_mode ) { case MODE_XI : case MODE_V8DF


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _fxsave ( void * __P ) { return __builtin_ia32_fxsave (


<s> uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups , <STR_LIT> ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isInt < <NUM_LIT> > ( Disp ) ) ; return ( Base << <NUM_LIT> ) | ( ( Disp & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Disp & <NUM_LIT> )


<s> SDValue ImpDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , SDLoc ( N ) , <STR_LIT> ) , <NUM_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , SDLoc ( N ) , <STR_LIT> , ImpDef , N , SubReg ) ; return SDValue ( Node ,


<s> addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr , op [ <NUM_LIT> ] ) ; if ( pat ) emit_insn ( pat ) ; } else { if ( ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( op [ <NUM_LIT> ] , smode ) ) op [ <NUM_LIT> ] = copy_to_mode_reg ( smode , op [ <NUM_LIT> ] ) ; rtx addr ; if ( op [ <NUM_LIT> ] == const0_rtx ) addr = gen_rtx_MEM ( tmode , op [ <NUM_LIT> ] ) ; else { op [ <NUM_LIT> ] = copy_to_mode_reg ( Pmode , op [ <NUM_LIT> ] ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ) ; } rtx pat = GEN_FCN ( icode ) ( addr


<s> bool <ISA_LIT>RegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; else TS . emitDirectiveSetNoMicro<ISA_LIT>


<s> unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; if ( SpillToVGPR ) { for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool UseKill = IsKill && i == NumSubRegs - <NUM_LIT> ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( UseKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; if ( i == <NUM_LIT> && NumSubRegs > <NUM_LIT> ) { MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ; } if ( NumSubRegs > <NUM_LIT> ) MIB . addReg ( SuperReg , getKillRegState ( UseKill ) | RegState :: Implicit ) ; } } else { Register TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpVGPR ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; unsigned PerVGPR = <NUM_LIT> ; unsigned NumVGPRs = ( NumSubRegs + ( PerVGPR - <NUM_LIT> ) ) / PerVGPR ; int64_t VGPRLanes = ( <NUM_LIT> << std :: min ( PerVGPR , NumSubRegs ) ) - <NUM_LIT> ; for ( unsigned Offset = <NUM_LIT> ; Offset < NumVGPRs ; ++ Offset ) { unsigned TmpVGPRFlags = RegState :: Undef ; for ( unsigned i = Offset * PerVGPR , e = std :: min ( ( Offset + <NUM_LIT> ) * PerVGPR , NumSubRegs ) ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; MachineInstrBuilder WriteLane = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , TmpVGPR ) . addReg ( SubReg , SubKillState ) . addImm ( i % PerVGPR ) . addReg ( TmpVGPR , TmpVGPRFlags ) ; TmpVGPRFlags = <NUM_LIT> ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == NumSubRegs ) SuperKillState |= getKillRegState ( IsKill ) ; WriteLane . addReg ( SuperReg , RegState :: Implicit | SuperKillState


<s> const TargetFrameLowering * getFrameLowering ( )


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass

< <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ;


<s> if ( As == <NUM_LIT> ) return amConstant ; if ( As == <NUM_LIT> ) return amConstant ; break ; case <NUM_LIT> : return amConstant ; default : break ; } switch ( As ) { case <NUM_LIT> : return amRegister ; case <NUM_LIT> : return amIndexed ; case <NUM_LIT> : return amIndirect ; case <NUM_LIT> : return amIndirectPost ; default : llvm_unreachable ( <STR_LIT>


<s> if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) return inner_mode == DFmode ? cost -> divsd : cost -> divss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fdiv ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> divsd : cost -> divss ) ; else return cost -> divide [ MODE_INDEX ( mode )


<s> if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; return combineSetCCAtomicArith ( EFLAGS ,


<s> Kind = improveShuffleKindFromMask ( Kind , Mask ) ; if ( ST -> hasVOP3PInsts ( ) ) { if ( cast < FixedVectorType > ( VT ) -> getNumElements ( ) == <NUM_LIT> && DL . getTypeSizeInBits ( VT -> getElementType ( ) ) == <NUM_LIT> ) { switch ( Kind ) { case TTI :: SK_Broadcast : case TTI :: SK_Reverse : case TTI :: SK_PermuteSingleSrc : return <NUM_LIT> ; default : break ; } } } return BaseT :: getShuffleCost ( Kind , VT


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM .


<s> * num = <NUM_LIT> ; if ( ! ( flags & SECTION_DEBUG ) ) * num |= <NUM_LIT> ; if ( flags & SECTION_EXCLUDE ) * num |= <NUM_LIT> ; if ( flags & SECTION_WRITE ) * num |= <NUM_LIT> ; if ( flags & SECTION_CODE ) * num |= <NUM_LIT> ; if ( flags & SECTION_MERGE ) * num |= <NUM_LIT> ; if ( flags & SECTION_STRINGS ) * num |= <NUM_LIT> ; if ( flags & SECTION_TLS ) * num |= <NUM_LIT> ; if ( HAVE_COMDAT_GROUP && ( flags & SECTION_LINKONCE ) ) *


<s> if ( isFloat ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; unsigned MovCCOpc = isThumb ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = TargetMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) ; UpdateValueMap ( I ,


<s> static bool IsCallReturnTwice ( llvm :: MachineOperand & MOp ) { if ( ! MOp . isGlobal ( ) ) return false ; auto * CalleeFn = dyn_cast < Function > ( MOp . getGlobal ( ) ) ; if ( ! CalleeFn ) return false ; AttributeList Attrs = CalleeFn -> getAttributes ( ) ; return Attrs . hasFnAttribute ( Attribute


begin ( ) , * e = ConstantCasts . end ( ) ;


<s> assert ( ( MaskEltTy == <STR_LIT> || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( MaskEltTy , NumEltsInWideVec ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; if ( MaskEltTy != <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) , Mask ) ; SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , Src0 , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Exract = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Exract , NewLoad


<s> } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) .


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; for ( const TargetRegisterClass * BaseClass : BaseClasses ) { if ( BaseClass -> contains ( Reg ) ) { return BaseClass ; } } return nullptr


<s> if ( GVar -> use_empty ( ) ) return ; } const Function * demotedFunc = nullptr ; if ( ! processDemoted && canDemoteGlobalVar ( GVar , demotedFunc ) ) { O << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ; if ( localDecls . find ( demotedFunc ) != localDecls . end ( ) ) localDecls [ demotedFunc ] . push_back ( GVar ) ; else { std :: vector < const GlobalVariable * > temp ; temp . push_back ( GVar ) ; localDecls [ demotedFunc ] = temp ; } return ; } O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( isManaged ( * GVar ) ) { O << <STR_LIT> ; } if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; if ( ETy -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( ETy , false ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; if ( GVar -> hasInitializer ( ) ) { if ( ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GLOBAL ) || ( PTy -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_CONST ) ) { const Constant * Initializer = GVar -> getInitializer ( ) ; if ( ! Initializer -> isNullValue ( ) && ! isa < UndefValue > ( Initializer ) ) { O << <STR_LIT> ; printScalarConstant ( Initializer , O ) ; } } else { if ( ! GVar -> getInitializer ( ) -> isNullValue ( ) ) { std :: string warnMsg = ( <STR_LIT> + GVar -> getName ( ) + <STR_LIT> + Twine ( llvm :: utostr_32 ( PTy -> getAddressSpace ( ) ) ) + <STR_LIT> ) . str ( ) ; report_fatal_error ( warnMsg . c_str ( ) ) ; } } } } else { unsigned int ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize (


<s> assert ( ! IsKernel || ( Info -> hasWorkGroupIDX ( ) && Info -> hasWorkItemIDX ( ) ) ) ; } if ( IsEntryFunc ) { allocateSpecialInputVGPRs ( CCInfo , MF , * TRI , * Info ) ; allocateHSAUserSGPRs ( CCInfo , MF , * TRI , * Info ) ; } if ( IsKernel ) { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } else { CCAssignFn * AssignFn = CCAssignFnForCall ( CallConv , isVarArg ) ; CCInfo . AnalyzeFormalArguments ( Splits , AssignFn ) ; } SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped [ i ] ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; MVT VT = VA . getLocVT ( ) ; if ( IsEntryFunc && VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = VA . getLocVT ( ) ; const uint64_t Offset = Subtarget -> getExplicitKernelArgOffset ( MF ) + VA . getLocMemOffset ( ) ; Info -> setABIArgOffset ( Offset + MemVT . getStoreSize ( ) ) ; SDValue Arg = lowerKernargMemParameter ( DAG , VT , MemVT , DL , Chain , Offset , Ins [ i ] . Flags . isSExt ( ) , & Ins [ i ] ) ; Chains . push_back ( Arg . getValue ( <NUM_LIT> ) ) ; auto * ParamTy = dyn_cast < PointerType > ( FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && ParamTy && ParamTy -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ) { Arg = DAG . getNode ( <STR_LIT> , DL , Arg . getValueType ( ) , Arg , DAG . getValueType ( <STR_LIT> ) ) ; } InVals . push_back ( Arg ) ; continue ; } if ( VA . isMemLoc ( ) ) report_fatal_error ( <STR_LIT> ) ; assert ( VA . isRegLoc (


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerAndToBT ( Op0 , CC , dl , DAG ) ) return NewSetCC ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerVectorAllZeroTest ( Op0 , CC , Subtarget , DAG ) ) return NewSetCC ; } if ( SDValue NewSetCC = EmitKTEST ( Op0 , Op1 , CC , dl , DAG , Subtarget ) ) return NewSetCC ; if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return getSETCC ( CCode , Op0 . getOperand ( <NUM_LIT> ) , dl


<s> const <ISA_LIT>FrameLowering * llvm :: create<ISA_LIT>SEFrameLowering


<s> SDValue <ISA_LIT>TargetLowering :: loadStackInputValue ( SelectionDAG & DAG , EVT VT , const SDLoc & SL , int64_t Offset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = getOrCreateFixedStackObject ( MFI , VT . getStoreSize


<s> void addSImm19Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerADDROFRETURNADDR ( SDValue Op , SelectionDAG &


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS ,

MCCodeEmitter * Emitter , bool RelaxAll ) {


<s> bool isu16_2Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , true


<s> } for ( Value :: const_use_iterator iter = F -> use_begin ( ) , iterEnd = F -> use_end ( ) ; iter != iterEnd ; ++ iter ) { if ( const Constant * C = dyn_cast < Constant > ( * iter ) ) { if ( usedInGlobalVarDef ( C ) ) { CurrentFnSym = Mang -> getSymbol ( F ) ; emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { CurrentFnSym = Mang -> getSymbol ( F ) ; emitDeclaration ( F , O )


<s> for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MBB -> addLiveIn (


, _mm512_setzero_ph ( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } FrameInfo . setStackID ( FrameIndex , <STR_LIT> ) ; MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( )


<s> const char * Sym = N -> getSymbol ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue GALo = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , GAHi ) , <NUM_LIT> ) ; SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , GALo ) , <NUM_LIT> ) ; return


<s> if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) && ValTy -> getVectorElementType ( ) -> isIntegerTy ( ) ) return <NUM_LIT> ; return BaseT :: getVectorInstrCost ( Opcode ,


<s> for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isRegOrImmWithInputMods ( ) ) { Op . addRegOrImmWithInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { return ; } if ( IsVOP1 ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstSel , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstUnused , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , <NUM_LIT> ) ; }


<s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [


<s> unsigned SrcSelect [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned CT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Value * Offset [ <NUM_LIT> ] = { I . getArgOperand ( <NUM_LIT> ) , I . getArgOperand ( <NUM_LIT> ) , I . getArgOperand ( <NUM_LIT> ) , } ; bool useShadowVariant ; getAdjustmentFromTextureTarget ( TextureType , false , SrcSelect , CT , useShadowVariant


<s> unsigned <ISA_LIT>TTIImpl :: getStoreVectorFactor ( unsigned VF , unsigned StoreSize , unsigned ChainSizeInBytes , VectorType * VecTy ) const { unsigned VecRegBitWidth = VF * StoreSize ; if ( VecRegBitWidth > <NUM_LIT> ) return


<s> unsigned int getRemainingOccupancy (


<s> return ( uint16x4_t ) __builtin_neon_vcvtuv4hf (


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( DataTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( DataTy , Align ( Alignment ) ) ) ) return BaseT


<s> MI -> getOperand ( getOperandIdx ( * MI , <STR_LIT> :: pred_sel_W ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI -> getOperand ( PIdx ) ; PMO . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) ,


<s> const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MI -> getMF ( ) -> getSubtarget ( ) ) ; if ( MMO -> getSize ( ) == <NUM_LIT> && ( ! STI . systemSupportsUnalignedAccess ( ) && MMO ->

getAlign ( ) < MMO -> getSize ( ) ) ) return true ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateToken ( StringRef Str , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S


<s> return NumElem * Cost + SplitCost ; } } if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT>

&& ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ;


<s> auto BuildPtr = B . buildMerge ( DstTy , { SrcAsInt , ApertureReg } ) ; if ( isKnownNonNull ( Src , MRI , TM , SrcAS ) ) { B . buildCopy ( Dst , BuildPtr ) ; MI . eraseFromParent ( ) ; return true ; } auto SegmentNull = B . buildConstant ( SrcTy , TM . getNullPointerValue ( SrcAS ) ) ; auto FlatNull = B . buildConstant ( DstTy , TM . getNullPointerValue ( DestAS ) ) ; auto CmpRes = B . buildICmp ( CmpInst :: ICMP_NE , LLT :: scalar ( <NUM_LIT> ) , Src , SegmentNull . getReg ( <NUM_LIT> ) ) ; B . buildSelect ( Dst , CmpRes , BuildPtr , FlatNull ) ; MI . eraseFromParent ( ) ; return true ; } if ( DestAS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT && SrcTy . getSizeInBits ( ) == <NUM_LIT> ) { B . buildExtract ( Dst , Src , <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT && DstTy . getSizeInBits ( ) == <NUM_LIT> ) { const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; uint32_t AddrHiVal = Info -> get32BitAddressHighBits ( ) ; auto HighAddr = B . buildConstant ( LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT , <NUM_LIT> ) , AddrHiVal ) ; B . buildMerge ( Dst , { Src , HighAddr }


<s> if ( skipFunction ( mf . getFunction ( ) ) ) return false ; MRI = & mf . getRegInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo


<s> __asm__ volatile ( <STR_LIT> : [ val ] <STR_LIT> ( __rdtime . value ) , [ tid ] <STR_LIT> ( __rdtime . timeid ) : ) ; return


<s> <STR_LIT> expandPredBlockMask ( <STR_LIT> BlockMask , <STR_LIT> Kind ) { using PredBlockMask = <STR_LIT> ; assert ( Kind != <STR_LIT> && <STR_LIT> ) ; assert ( countTrailingZeros ( ( unsigned ) BlockMask ) != <NUM_LIT> && <STR_LIT> ) ; auto ChooseMask = [ & ] ( PredBlockMask AddedThen , PredBlockMask AddedElse ) { return Kind == <STR_LIT> ? AddedThen : AddedElse ; } ; switch ( BlockMask ) { case PredBlockMask :: T : return ChooseMask ( PredBlockMask :: TT , PredBlockMask ::


<s> <ISA_LIT>RDFOpt ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>RDFOptPass ( * PassRegistry ::


<s> if ( ScalarType . isFloatingPoint ( ) ) { unsigned ScalarSize = ScalarType . getSizeInBits ( ) ; assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned MaskVal = ( ScalarSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Mask = DAG . getConstant ( MaskVal , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec256 , Mask ) ; } const <ISA_LIT>Subtarget & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; MVT CastVT = Subtarget . hasAVX2 (


<s> const MachineInstr & PI = * PacketSU -> getInstr ( ) ; if ( PI . isInlineAsm ( ) ) return false ; if ( PI . isImplicitDef ( ) ) return false ; if ( isImplicitDependency ( PI , DepReg ) ) return false ; const MCInstrDesc & MCID = PI . getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) if ( HII -> isCondInst ( MI ) || HII -> isJumpR ( MI ) ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI )


<s> static unsigned int h8300_length_from_table ( rtx op1 , rtx op2 , const h8300_length_table * table ) { enum h8300_operand_class op1_class , op2_class ; unsigned int size , immediate_length ; size = GET_MODE_SIZE ( GET_MODE


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc & Loc = MI .


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) && Reciprocal ) || ( VT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Reciprocal ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) || ( VT == <STR_LIT> && Subtarget . useAVX512Regs ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; UseOneConstNR = false ; unsigned Opcode = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Estimate = DAG . getNode ( Opcode , DL , VT , Op ) ; if ( RefinementSteps == <NUM_LIT> && ! Reciprocal ) Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Op , Estimate ) ; return Estimate ; } if ( VT . getScalarType ( ) == <STR_LIT> && isTypeLegal ( VT ) && Subtarget . hasFP16 ( ) ) { assert ( Reciprocal && <STR_LIT> ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; if ( VT == <STR_LIT> ) { SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ; SDValue Undef = DAG . getUNDEF ( <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Undef , Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; if ( ! GlobalsEmitted ) { emitGlobals ( * MF -> getFunction ( ) -> getParent ( ) ) ; GlobalsEmitted = true ; } MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; } O << * CurrentFnSym ; emitFunctionParamList ( * MF , O ) ; if ( llvm :: isKernelFunction ( * F ) ) emitKernelFunctionDirectives ( * F , O ) ; OutStreamer . EmitRawText ( O . str (


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( CoprocReg ) ; Op -> Cop . Val = CopVal ; Op -> StartLoc =


<s> int avr_progmem_p ( tree decl , tree attributes ) { tree a ; if ( TREE_CODE ( decl ) != VAR_DECL ) return <NUM_LIT> ; if ( avr_decl_memx_p ( decl ) ) return <NUM_LIT> ; if ( avr_decl_flash_p ( decl ) ) return <NUM_LIT> ; if ( NULL_TREE != lookup_attribute ( <STR_LIT> , attributes ) ) return - <NUM_LIT> ; a = decl ; do a = TREE_TYPE


<s> unsigned NumBytes = alignTo ( Info . TargetSize , <NUM_LIT> ) / <NUM_LIT> ; if ( Value == <NUM_LIT> ) return ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( )


<s> Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; } SDValue GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , HiFixup ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , LoFixup ) , DAG . getConstant ( Alignment , <STR_LIT> ) ) ; if ( UseGOT ) { GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getEntryNode ( ) ,


<s> SDValue R600TargetLowering :: LowerSRXParts ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shift = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; const bool SRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue Width = DAG . getConstant ( VT . getSizeInBits ( ) , DL , VT ) ; SDValue Width1 = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , DL , VT ) ; SDValue BigShift = DAG . getNode ( <STR_LIT> , DL , VT , Shift , Width ) ; SDValue CompShift = DAG . getNode ( <STR_LIT> , DL , VT , Width1 , Shift ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Hi , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( SRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , Shift ) ; SDValue LoSmall = DAG . getNode ( <STR_LIT> , DL ,


<s> if ( MC . isReg ( ) ) O << getRegisterName ( MC . getReg ( ) ) ; else if ( MC . isImm ( ) ) O << MC . getImm ( ) ; else if ( MC . isExpr ( ) ) MC . getExpr ( ) -> print (


<s> return ( uint16x8_t ) __builtin_neon_vcaltv8hf ( __a ,


<s> switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } case <STR_LIT> : ++ NumVLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } case <STR_LIT> : ++


<s> if ( val >= <NUM_LIT> && val <= <NUM_LIT> ) return SPU_ILA ; if ( ( val & <NUM_LIT> ) == ( ( val >>

<NUM_LIT> ) & <NUM_LIT> ) ) return SPU_ILH ;


<s> case FCOND_F : case FCOND_T : return <STR_LIT> ; case FCOND_UN : case FCOND_OR : return <STR_LIT> ; case FCOND_EQ : case FCOND_NEQ : return <STR_LIT> ; case FCOND_UEQ : case FCOND_OGL : return <STR_LIT> ; case FCOND_OLT : case FCOND_UGE : return <STR_LIT> ; case FCOND_ULT : case FCOND_OGE : return <STR_LIT> ; case FCOND_OLE : case FCOND_UGT : return <STR_LIT> ; case FCOND_ULE : case FCOND_OGT : return <STR_LIT> ; case FCOND_SF


<s> Register CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI . eraseFromParent ( ) ; return


<s> AU . addRequired < TargetTransformInfoWrapperPass


<s> static void emit_save_or_restore_local_in_regs ( rtx base , int offset , sorr_act_t action ) { if ( offset < - <NUM_LIT> || offset + <NUM_LIT> * UNITS_PER_WORD > <NUM_LIT> ) { base = emit_adjust_base_to_offset ( base , offset ) ; offset = <NUM_LIT>


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool isImmutable = ! ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt && ( CallConv == CallingConv :: Fast ) ) ; unsigned PtrByteSize = <NUM_LIT> ; unsigned ArgOffset = <ISA_LIT>FrameLowering :: getLinkageSize ( true , true ) ; unsigned MinReservedArea = ArgOffset ; static const uint16_t GPR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const uint16_t * FPR = GetFPR ( ) ; static const uint16_t VR [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned Num_GPR_Regs = array_lengthof ( GPR ) ; const unsigned Num_FPR_Regs = <NUM_LIT> ; const unsigned Num_VR_Regs = array_lengthof ( VR ) ; unsigned GPR_idx = <NUM_LIT> , FPR_idx = <NUM_LIT> , VR_idx = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > MemOps ; unsigned nAltivecParamsAtEnd = <NUM_LIT> ; Function :: const_arg_iterator FuncArg = MF . getFunction ( ) -> arg_begin ( ) ; unsigned CurArgIdx = <NUM_LIT> ; for ( unsigned ArgNo = <NUM_LIT> , e = Ins . size ( ) ; ArgNo != e ; ++ ArgNo ) { SDValue ArgVal ; bool needsLoad = false ; EVT ObjectVT = Ins [ ArgNo ] . VT ; unsigned ObjSize = ObjectVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned ArgSize = ObjSize ; <STR_LIT> Flags = Ins [ ArgNo ] . Flags ; std :: advance ( FuncArg , Ins [ ArgNo ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ ArgNo ] . OrigArgIndex ; unsigned CurArgOffset = ArgOffset ; if ( ObjectVT == <STR_LIT> || ObjectVT == <STR_LIT> || ObjectVT == <STR_LIT> || ObjectVT == <STR_LIT> ) { if ( isVarArg ) { MinReservedArea = ( ( MinReservedArea + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; MinReservedArea += CalculateStackSlotSize ( ObjectVT , Flags , PtrByteSize ) ; } else nAltivecParamsAtEnd ++ ; } else MinReservedArea += CalculateStackSlotSize ( Ins [ ArgNo ] . VT , Flags , PtrByteSize ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; ArgSize = ( ( ObjSize + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ; if ( ! ObjSize ) { int FI = MFI -> CreateFixedObject ( PtrByteSize , ArgOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; continue ; } unsigned BVAlign = Flags . getByValAlign ( ) ; if ( BVAlign > <NUM_LIT> ) { ArgOffset = ( ( ArgOffset + BVAlign - <NUM_LIT> ) / BVAlign ) * BVAlign ; CurArgOffset = ArgOffset ; } if ( ObjSize < PtrByteSize ) CurArgOffset = CurArgOffset + ( PtrByteSize - ObjSize


<s> auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) { RTS . emitDirectiveOptionPop ( ) ; } AsmPrinter :: emitBasicBlockEnd


<s> if ( ! Op . isReg ( ) ) return false ; auto Reg = Op . getReg ( ) ; if ( Reg . isPhysical ( ) ) return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ; const TargetRegisterClass * TRC = :: getRegClass ( MI , Reg ) ; return TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> || TRC == & <STR_LIT> ; } ; return llvm :: any_of ( MI . operands (


<s> dbgs ( ) << <STR_LIT> ; } } MCGNodeUInt Spilling ; for ( MCGSCANodeMap :: const_iterator i ( nodes . begin ( ) ) , ie ( nodes . end ( ) ) ; i != ie ; i ++ ) { if ( i -> second -> isVisible ( ) ) { PrunedSCAGraphSize ++ ; Spilling [ i -> first . first ] = std :: max ( Spilling [ i -> first . first ] , i -> second -> getSpillCost ( ) ) ; } } <ISA_LIT>StackCacheAnalysisInfo * info = & getAnalysis < <ISA_LIT>StackCacheAnalysisInfo > ( ) ; for ( MCGNodes :: const_iterator i ( G . getNodes ( ) . begin ( ) ) , ie ( G . getNodes ( ) . end ( ) ) ; i != ie ; i ++ ) { unsigned int reserved = getBytesReserved ( * i ) ; if ( ! ( * i ) -> isDead ( ) ) { Functions ++ ; if ( reserved != <NUM_LIT> ) { unsigned int tmp = Spilling [ * i ] ; if ( tmp == <NUM_LIT> ) NonSpillingSRES ++ ; else { SpillingSRES ++ ; if ( tmp == reserved ) FullySpillingSRES ++ ; } MachineBasicBlock & MBB = ( * i ) -> getMF ( ) ->


<s> rtx braf_base_lab = NULL_RTX ; const char * jump ; int far ; int offset = branch_dest ( insn ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ; rtx prev ; this . lab = gen_label_rtx ( ) ; if ( TARGET_SH2 && offset >= - <NUM_LIT> && offset - get_attr_length ( insn ) <= <NUM_LIT> ) { far = <NUM_LIT> ; jump = <STR_LIT> ; } else { far = <NUM_LIT> ; if ( flag_pic ) { if ( TARGET_SH2 ) jump = <STR_LIT> ; else jump = <STR_LIT> ; } else jump = <STR_LIT> ; } if ( GET_CODE ( ( prev = prev_nonnote_insn ( insn ) ) ) == INSN && INSN_CODE ( prev ) == CODE_FOR_indirect_jump_scratch ) { this . reg = SET_DEST ( XVECEXP ( PATTERN ( prev ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( REGNO ( this . reg ) == R0_REG && flag_pic && ! TARGET_SH2 ) jump = <STR_LIT> ; output_asm_insn ( jump , & this . lab ) ; if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; this . reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( jump , & this . lab ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } if ( far && flag_pic && TARGET_SH2 ) { braf_base_lab = gen_label_rtx ( ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( braf_base_lab ) ) ; } if ( far ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file

, <STR_LIT> , CODE_LABEL_NUMBER ( this . lab ) ) ;


<s> <ISA_LIT>ConditionalCompares ( ) : MachineFunctionPass


<s> int maximum_bytes ; if ( TARGET_REDUCED_REGS ) maximum_bytes = <NUM_LIT> ; else maximum_bytes = <NUM_LIT> ; if ( GET_CODE ( total_bytes ) != CONST_INT || GET_CODE ( alignment ) != CONST_INT || INTVAL ( total_bytes ) > maximum_bytes || INTVAL ( total_bytes ) & <NUM_LIT> || INTVAL ( alignment ) & <NUM_LIT> ) return <NUM_LIT> ; dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( SImode , XEXP ( srcmem , <NUM_LIT> ) ) ; out_words = in_words = INTVAL (


<s> static bool castRequiresQueuePtr ( const AddrSpaceCastInst * ASC ) { unsigned SrcAS = ASC -> getSrcAddressSpace ( )


<s> rtx op [ <NUM_LIT> ] ; machine_mode mode [ <NUM_LIT> ] ; int i ; mode [ <NUM_LIT> ] = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; for ( i = <NUM_LIT> ; i < argcount ; i ++ ) { arg [ i ] = CALL_EXPR_ARG ( exp , i ) ; op [ i ] = expand_normal ( arg [ i ] ) ; mode [ i ] = insn_data [ icode ] . operand [ i ] . mode ; if ( code [ i ] == CONST_INT && GET_CODE ( op [ i ] ) != CONST_INT ) error ( <STR_LIT> , i + <NUM_LIT> ) ; if ( code [ i ] == REG && ! ( * insn_data [ icode ] . operand [ i ] . predicate ) ( op [ i ] , mode [ i ] ) ) op [ i ] = copy_to_mode_reg ( mode [ i ] , op [ i ] ) ; } if ( insn_data [ icode ] . operand [ <NUM_LIT> ] . constraint [ <NUM_LIT> ] == '=' ) { if ( target == <NUM_LIT> || GET_MODE ( target ) != mode [ <NUM_LIT> ] || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , mode [ <NUM_LIT> ] ) ) target = gen_reg_rtx ( mode [ <NUM_LIT> ] ) ; } else target = <NUM_LIT> ; switch ( argcount ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; else pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : if ( target ) pat = GEN_FCN ( icode ) ( target , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ]


<s> if ( TREE_CODE ( func ) != FUNCTION_DECL ) return <NUM_LIT> ; a = lookup_attribute ( <STR_LIT> ,


<s> __vector unsigned long long __a = ( __vector unsigned long long


<s> if ( model != TLSModel :: LocalExec ) llvm_unreachable ( <STR_LIT> ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create (


<s> static bool removeTerminatorBit ( const <ISA_LIT>InstrInfo & TII , MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { bool RegSrc = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ; MI . setDesc ( TII . get ( RegSrc ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { bool RegSrc = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ; MI . setDesc ( TII . get ( RegSrc ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { MI . setDesc ( TII .


<s> return gen_rtx_REG ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) ? SImode : TYPE_MODE ( valtype ) , outgoing ? GP_OUTGOING_RETURN


<s> BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb2 ) { BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( StSize ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addReg ( <NUM_LIT> ) . addImm ( StSize ) . add


<s> static DecodeStatus DecodeVecShiftR16ImmNarrow ( MCInst & Inst , unsigned Imm

, uint64_t Addr , const void * Decoder ) {


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>WinCOFFObjectWriter ( OS


<s> case <STR_LIT> : BuildMI ( * MBB , Inst , Inst . getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { movePackToVALU ( Worklist , MRI , Inst ) ; Inst . eraseFromParent ( ) ; continue ; } } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst . setDesc ( NewDesc ) ; for ( unsigned i = Inst . getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst . getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) { Inst . RemoveOperand ( i ) ; addSCCDefUsersToVALUWorklist ( Inst , Worklist ) ; } } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst . addImplicitDefUseOperands ( * Inst . getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } bool HasDst = Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isDef ( ) ; unsigned NewDstReg = <STR_LIT> ; if ( HasDst ) { unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg


<s> unsigned Opc = <NUM_LIT> ; bool NeedTrunc = false ; uint64_t Mask = <NUM_LIT> ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) { Op0Reg = emitIntExt ( RetVT , Op0Reg , <STR_LIT> , false ) ; Op1Reg = emitAnd_ri ( <STR_LIT> ,


<s> assert ( ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements


<s> if ( pro_x == NULL ) return <NUM_LIT> ; con_mem_read = sched_get_mem_operand ( con , true , false ) ; gcc_assert ( con_mem_read != NULL


<s> if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( EnableBranchTargets ) addPass ( create<ISA_LIT>BranchTargetsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO

( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> SDValue Build = ST -> getValue ( ) ; if ( MemVT != <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> ; I < MemVT . getVectorNumElements ( ) ; I ++ ) { unsigned Elt = DAG . getDataLayout ( ) . isBigEndian ( ) ? MemVT . getVectorNumElements ( ) - I - <NUM_LIT> : I ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Build , DAG . getConstant ( Elt , dl , <STR_LIT> ) ) ) ; } for ( unsigned I = MemVT . getVectorNumElements ( ) ; I < <NUM_LIT> ; I ++ ) Ops . push_back (


<s> static rtx arc_dwarf_register_span ( rtx rtl ) { machine_mode mode = GET_MODE ( rtl ) ; unsigned regno ; rtx p ; if ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; regno = REGNO ( rtl


<s> ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasXMM ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue ( <NUM_LIT>


<s> assert ( MCID . hasOptionalDef ( ) && <STR_LIT> ) ; assert ( MCID . NumOperands == Inst . getNumOperands ( ) && <STR_LIT> ) ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_RequiresFlagSetting ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; } else if ( isThumbOne ( ) ) { if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } for ( unsigned I = <NUM_LIT> ; I < MCID . NumOperands ; ++ I ) if ( MCID . OpInfo [ I ] . RegClass == <STR_LIT> ) { if ( ( Inst . getOperand ( I ) . getReg ( ) ==

<STR_LIT> ) && ! hasV8Ops ( ) ) return Match_RequiresV8 ;


<s> SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( ) ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy , NULL ) ; TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , RetTy , false , false , false , false , <NUM_LIT> , CallingConv ::

C , false , false , true , Callee , Args , DAG , dl ) ;


<s> create_input_operand ( & m_ops [ m_opno ++ ] ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int VaArgOffset ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = alignTo ( State . getNextStackOffset ( ) , RegSizeInBytes ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset +=


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - <NUM_LIT> ; NumBytes = FrameSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg (