<s> bool HasFP = hasFP ( MF ) ; DebugLoc DL ; if ( ForceStackAlign ) { if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ; else if ( MaxAlign < SlotSize ) MaxAlign = SlotSize ; } int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) <ISA_LIT>FI -> setCalleeSavedFrameSize ( <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) - TailCallReturnAddrDelta ) ; if ( Is64Bit && ! Fn -> hasFnAttr ( Attribute :: NoRedZone ) && ! needsStackRealignment ( MF ) && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! Subtarget -> isTargetWin64 ( ) ) { uint64_t MinSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; if ( HasFP ) MinSize += SlotSize ; StackSize = std :: max ( MinSize , StackSize > <NUM_LIT> ? StackSize - <NUM_LIT> : <NUM_LIT> ) ; MFI -> setStackSize ( StackSize ) ; } else if ( Subtarget -> isTargetWin64 ( ) ) { StackSize += <NUM_LIT> ; MFI -> setStackSize ( StackSize ) ; } if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( getSUBriOpcode ( Is64Bit , - TailCallReturnAddrDelta ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( - TailCallReturnAddrDelta ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const TargetData * TD = MF . getTarget ( ) . getTargetData ( ) ; uint64_t NumBytes = <NUM_LIT> ; int stackGrowth = - TD -> getPointerSize ( ) ; if ( HasFP ) { uint64_t FrameSize = StackSize - SlotSize ; if ( needsStackRealignment ( MF ) ) FrameSize = ( FrameSize + MaxAlign - <NUM_LIT> ) / MaxAlign * MaxAlign ; NumBytes = FrameSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FramePtr , RegState :: Kill ) ; if ( needsFrameMoves ) { MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; if ( StackSize ) { MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , <NUM_LIT> * stackGrowth ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; } else { MachineLocation SPDst ( StackPtr ) ; MachineLocation SPSrc ( StackPtr , stackGrowth ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst ,


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ^ Cond [ <NUM_LIT> ] . getImm ( ) ) ; return


<s> static __inline qword si_ahi ( qword a , short b ) { return ( ( qword ) ( vec_add ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) , <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) EmitAlignment ( <NUM_LIT> ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI


<s> static bool is_interrupt_func ( tree decl = current_function_decl ) { return has_attr ( ATTR_INTR ,


<s> Invert = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { assert ( IsFP && <STR_LIT> ) ; SDValue LT = getVectorCmp ( DAG , <STR_LIT> , DL , VT , CmpOp1 , CmpOp0 ) ; SDValue GT = getVectorCmp ( DAG , <STR_LIT> , DL , VT , CmpOp0 , CmpOp1 ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , VT , LT , GT ) ; break ; } default : if ( unsigned Opcode = getVectorComparisonOrInvert ( CC , IsFP , Invert ) ) Cmp = getVectorCmp ( DAG , Opcode , DL , VT , CmpOp0 , CmpOp1 ) ; else { CC = <STR_LIT> ( CC ) ; if ( unsigned Opcode = getVectorComparisonOrInvert ( CC , IsFP , Invert ) ) Cmp = getVectorCmp ( DAG , Opcode , DL


<s> bool hasDot7Insts ( ) const { return HasDot7Insts


<s> else if ( TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE ( mode ) ) return true ; else return false


<s> func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; if ( abi_reg ) { rtvec v = gen_rtvec ( <NUM_LIT> , func , func_desc , tlsarg ) ; rtx mark_func = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( <NUM_LIT> , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , func ) ; } else func_addr =


<s> aarch64_print_operand_address ( STREAM , X ) { \ rtx fun , lr ; \ lr = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; \ fun

= gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_NAME ) ; \ emit_library_call ( fun , LCT_NORMAL , VOIDmode , <NUM_LIT> , lr , Pmode ) ; \ }


<s> static SDValue concat128BitVectors ( SDValue V1 , SDValue V2 , EVT VT , unsigned NumElems , SelectionDAG & DAG , SDLoc dl ) { SDValue V = insert128BitVector ( DAG . getUNDEF ( VT ) , V1


<s> unsigned Size = Ty -> getScalarSizeInBits ( ) ; if ( Size <= <NUM_LIT> && ST -> has16BitInsts ( ) ) return false ; if ( DA -> isUniform ( & I ) ) return false ; Value * LHS = I . getOperand ( <NUM_LIT> ) ; Value * RHS = I . getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( & I ) ; Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; <STR_LIT> IntrID = <STR_LIT> ; if ( ST -> hasMulU24 ( ) && isU24 ( LHS , Size ) && isU24 ( RHS , Size ) ) { IntrID = <STR_LIT> ; } else if ( ST -> hasMulI24 ( ) && isI24 ( LHS , Size ) && isI24 ( RHS , Size ) ) { IntrID = <STR_LIT> ; } else return false ; SmallVector < Value * , <NUM_LIT> > LHSVals ; SmallVector < Value * , <NUM_LIT> > RHSVals ; SmallVector < Value * , <NUM_LIT> > ResultVals ; extractValues ( Builder , LHSVals , LHS ) ; extractValues ( Builder , RHSVals , RHS ) ; IntegerType * I32Ty = Builder . getInt32Ty ( ) ; FunctionCallee Intrin = <STR_LIT> ( Mod , IntrID ) ; for ( int I = <NUM_LIT> , E = LHSVals . size ( ) ; I != E ; ++ I ) { Value * LHS , * RHS ; if ( IntrID == <STR_LIT> ) { LHS = Builder . CreateZExtOrTrunc ( LHSVals [ I ] , I32Ty ) ; RHS = Builder . CreateZExtOrTrunc ( RHSVals [ I ] , I32Ty ) ; } else { LHS = Builder . CreateSExtOrTrunc ( LHSVals [ I ] , I32Ty ) ; RHS = Builder . CreateSExtOrTrunc ( RHSVals [ I ] , I32Ty ) ; } Value * Result = Builder . CreateCall ( Intrin , { LHS , RHS } ) ; if ( IntrID == <STR_LIT> ) { ResultVals . push_back ( Builder . CreateZExtOrTrunc ( Result , LHSVals [ I ] -> getType ( ) ) ) ; } else { ResultVals . push_back ( Builder . CreateSExtOrTrunc ( Result , LHSVals [ I ] -> getType (


<s> else return ~ <NUM_LIT> ; if ( Imm . I >= <NUM_LIT> && Imm . I <= <NUM_LIT> ) return <NUM_LIT> + Imm . I ; if ( Imm . I >= - <NUM_LIT> && Imm . I <= - <NUM_LIT> ) return <NUM_LIT> + abs ( Imm . I ) ; if ( Imm . F == <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == - <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == - <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == - <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == <NUM_LIT> ) return <NUM_LIT> ; if ( Imm . F == - <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> unsigned getValueBit ( int64_t Val , unsigned bit


<s> const auto & Operand = OperandPair . second ; MachineInstr * PotentialMI = Operand -> potentialToConvert ( TII ) ; if ( PotentialMI && isConvertibleToSDWA ( * PotentialMI , ST ) ) { PotentialMatches [ PotentialMI ] . push_back ( Operand . get ( ) ) ; } } for ( auto & PotentialPair : PotentialMatches ) { MachineInstr & PotentialMI = * PotentialPair . first ; convertToSDWA ( PotentialMI , PotentialPair . second ) ; } PotentialMatches . clear


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand


<s> auto VRegAndVal = getIConstantVRegValWithLookThrough ( IdxReg , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value . getSExtValue ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; if ( VecSize < <NUM_LIT> ) { MachineInstr * ScalarToVec = emitScalarToVector ( VecSize , & <STR_LIT> , SrcReg , MIB ) ; if ( ! ScalarToVec ) return false ; SrcReg = ScalarToVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineInstr * InsMI = emitLaneInsert ( None , SrcReg , EltReg , LaneIdx , EltRB , MIB ) ; if ( VecSize < <NUM_LIT> ) { Register DemoteVec = InsMI -> getOperand ( <NUM_LIT> ) . getReg (


<s> static <ISA_LIT>Operand * CreateFPImm ( double Val , SMLoc S , SMLoc E


<s> MO . setIsKill ( true ) ; } else if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg ,


<s> static SExpr * t_addrmode_rr_customALF ( const MachineInstr & MI , ALFStatementGroup & alfbb , ALFContext * ctx , string label ) { const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string Reg = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; string RegOff = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * offset = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , RegOff ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * bytes_to_bits = ctx -> select ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ctx -> u_mul ( <NUM_LIT> , <NUM_LIT> , ctx -> load ( <NUM_LIT> , Reg ) , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; SExpr * add = ctx -> add ( <NUM_LIT> , bytes_to_bits , offset , <NUM_LIT> ) ; return ctx -> list ( <STR_LIT> ) -> append ( <NUM_LIT> ) -> append ( ctx -> fref (


<s> static SDValue LowerF128_FPROUND ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return Op ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F64 ) , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F32 ) , <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; return SDValue ( )


<s> return DAG . getLoad ( getPointerTy ( ) , op . getDebugLoc ( ) , DAG .

getEntryNode ( ) , retaddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> DEBUG_FUNCTION void rs6000_debug_print_mode ( ssize_t m ) { ssize_t rc ; int spaces = <NUM_LIT> ; bool fuse_extra_p ; fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( m ) ) ; for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) fprintf ( stderr , <STR_LIT> , reload_reg_map [ rc ] . name , rs6000_debug_addr_mask ( reg_addr [ m ] . addr_mask [ rc ] , true ) ) ; if ( ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) || ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) ) fprintf ( stderr , <STR_LIT> , ( reg_addr [ m ] . reload_store != CODE_FOR_nothing ) ? 's' : '*' , ( reg_addr [ m ] . reload_load != CODE_FOR_nothing ) ? 'l' : '*' ) ; else spaces += sizeof ( <STR_LIT> ) - <NUM_LIT> ; if ( reg_addr [ m ] . scalar_in_vmx_p ) { fprintf ( stderr , <STR_LIT> , spaces , <STR_LIT> ) ; spaces = <NUM_LIT> ; } else spaces += sizeof ( <STR_LIT> ) - <NUM_LIT> ; fuse_extra_p = ( ( reg_addr [ m ] . fusion_gpr_ld != CODE_FOR_nothing ) || reg_addr [ m ] . fused_toc ) ; if ( ! fuse_extra_p ) { for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) { if ( rc != RELOAD_REG_ANY ) { if ( reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addi_st [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addis_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addis_st [ rc ] != CODE_FOR_nothing ) { fuse_extra_p = true ; break ; } } } } if ( fuse_extra_p ) { fprintf ( stderr , <STR_LIT> , spaces , <STR_LIT> ) ; spaces = <NUM_LIT> ; for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) { if ( rc != RELOAD_REG_ANY ) { char load , store ; if ( reg_addr [ m ] . fusion_addis_ld [ rc ] != CODE_FOR_nothing ) load = 'l' ; else if ( reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing ) load = 'L' ; else load =


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const


<s> OS << <STR_LIT> << Opcode << <STR_LIT> << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return true ; } if ( isPostIncrementForm ( MI , AddOffset ) ) { OS << <STR_LIT> << Opcode << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return true ; } return false


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags =


<s> auto CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , getBrCond ( CC ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB ) return <NUM_LIT> ; MachineInstr & MI = * BuildMI ( & MBB , DL ,


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { for ( MCRegAliasIterator AI ( Reg , TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet


<s> return ( __m128d ) vec_mergeh ( ( __v2df ) __A ,


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandSpecialInstrsPass (


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return


<s> if ( GET_CODE ( x ) == LO_SUM && ( mode != BLKmode && GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) && m32r_rtx_ok_for_base_p ( XEXP ( x ,

<NUM_LIT> ) , strict ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) return true ;


<s> case TargetOpcode :: G_ADD : case TargetOpcode :: G_OR : { assert ( ( OpdMapper . getInstrMapping ( ) . getID ( ) == <NUM_LIT> || OpdMapper . getInstrMapping ( ) . getID ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return applyDefaultMapping ( OpdMapper )


<s> return Kind == k_Register && Reg . Kind == RegKind :: SVEVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT>


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = <NUM_LIT> ; if ( sh_pass_in_reg_p ( * cum , mode , type ) && ! TARGET_FPU_DOUBLE && ( sh_round_reg ( * cum , mode ) + ( mode != BLKmode ? CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) :

CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) ) > NPARM_REGS ( mode ) ) ) words = NPARM_REGS ( mode ) - sh_round_reg ( * cum , mode ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: EmitStartOfAsmFile ( ) { OS << <STR_LIT> ; OS << <ISA_LIT>_SV_REGISTER_DECL ; OS << <ISA_LIT>_MEM_DECL ; OS <<


<s> fputs ( <STR_LIT> , file ) ; switch ( size ) { case <NUM_LIT> : break ; case <NUM_LIT>


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } if ( OpIdx >= NumOps ) return false ; assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; assert ( ( ! isPrePost || ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx + <NUM_LIT> >= NumOps ) return false ; assert ( ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && ( OpInfo [ OpIdx + <NUM_LIT> ] . RegClass == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; if ( getIBit ( insn ) == <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT>


<s> if ( ! <ISA_LIT>FI -> getLOHRelated ( ) . empty ( ) )


<s> bool isMemImm7ShiftedOffset ( ) const { if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> || ! <ISA_LIT>MCRegisterClasses [ RegClassID ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE


<s> RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> && ! isDarwin ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ; } switch ( access ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createLo ( Expr , isDarwin , Ctx ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createHa ( Expr , isDarwin , Ctx ) ; break ; } return MCOperand :: createExpr (


<s> F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return


<s> RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget -> hasSSE1 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : return false ; } ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return


<s> bool <ISA_LIT>AsmParser :: parseDirectiveRegSave ( SMLoc L , bool IsVector ) { if ( ! UC . hasFnStart ( ) ) return Error ( L , <STR_LIT> ) ; if ( UC . hasHandlerData ( ) ) return Error ( L , <STR_LIT> ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; if ( parseRegisterList ( Operands ) || parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; <ISA_LIT>Operand & Op = ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ; if ( ! IsVector && ! Op . isRegList ( ) ) return Error ( L , <STR_LIT> ) ; if ( IsVector && ! Op . isDPRRegList ( ) ) return Error ( L , <STR_LIT> ) ; getTargetStreamer ( ) . emitRegSave ( Op .


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & OS ) { LPCC :: CondCode CC = static_cast < LPCC :: CondCode > ( MI ->


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl

, VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ;


<s> OperandMatchResultTy parseGRH32 ( OperandVector & Operands ) { return parseRegister ( Operands


<s> static void frv_io_handle_use ( rtx * x


<s> void <ISA_LIT>InstructionSelector :: renderSetGLC ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( OpIdx >= <NUM_LIT> &&


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue >


<s> const <ISA_LIT>RegisterInfo * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; assert ( ! RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; FrameReg = RegInfo -> getStackRegister ( ) ; return getFrameIndexOffsetFromSP ( MF ,


<s> return ( CachePolicy >> <NUM_LIT> ) &


<s> return new Dcpu16PassConfig ( this ,


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else


<s> Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; std :: vector < CalleeSavedInfo > & CSI = MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ; if ( std :: none_of ( CSI . begin ( ) , CSI . end ( ) , [ & ] ( CalleeSavedInfo & CSR ) { return CSR . getReg ( ) == RAReg ; } ) ) return ; Register SCSPReg = <STR_LIT> ( ) ; auto & Ctx = MF . getFunction ( ) . getContext ( ) ; if ( ! STI . isRegisterReservedByUser ( SCSPReg ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( RVFI -> useSaveRestoreLibCalls ( MF ) ) { Ctx . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; return ; } const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo (


<s> static bool canMoveInstsAcrossMemOp ( MachineInstr & MemOp , ArrayRef < MachineInstr * > InstsToMove , AliasAnalysis * AA ) { assert ( MemOp . mayLoadOrStore ( ) ) ; for ( MachineInstr * InstToMove : InstsToMove ) { if ( ! InstToMove -> mayLoadOrStore ( ) ) continue ; if ( ! memAccessesCanBeReordered ( MemOp , * InstToMove , AA ) ) return false ; } return true


<s> createUnpackShuffleMask ( <STR_LIT> , Unpckhwd , false , false ) ; bool IsUnpackwdMask = ( isTargetShuffleEquivalent ( Mask , Unpcklwd ) || isTargetShuffleEquivalent ( Mask , Unpckhwd


<s> SMLoc getEndLoc ( ) const override { return


<s> emit_insn ( GEN_FCN ( CODE_FOR_tcommit ) ( ) ) ; break ; case AARCH64_TME_BUILTIN_TCANCEL : { tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; if ( CONST_INT_P ( op0 ) && UINTVAL ( op0 ) <= <NUM_LIT> ) emit_insn ( GEN_FCN ( CODE_FOR_tcancel ) ( op0 ) ) ; else { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> ) ; return const0_rtx ; } } break ; default : gcc_unreachable (


<s> bool HasAnyUndefs ; if ( ! Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) ) return false ; Imm = SplatValue ; return true


<s> for ( size_t i = <NUM_LIT> , e = RTLIB :: UNKNOWN_LIBCALL ; i < e ; ++ i ) if ( RuntimeLibcallNames [ i ] && strcmp ( RuntimeLibcallNames [ i ] , Name ) == <NUM_LIT> ) return GetSignature ( Subtarget , RTLIB


<s> if ( Subtarget -> hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( DAG . getMachineFunction ( ) , & Mask ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> ,

PtrVT , Chain . getValue ( <NUM_LIT> ) ) ;


<s> default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , <STR_LIT> ) ; break ; case ABI_ELFv2 : case ABI_V4 : case ABI_DARWIN : break ; } } RS6000_OUTPUT_BASENAME ( file


<s> static struct machine_function * mips_init_machine_status ( void


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx +


<s> SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , N0 ) ; SDValue Ops [ ] = { N0 , Neg , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Neg . getNode ( ) , <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSE41 ( ) ) { SDLoc DL ( Op )


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW ,


<s> int long_immediate_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : return <NUM_LIT> ; case CONST_INT : return ! SMALL_INT ( INTVAL ( op ) ) ; case CONST_DOUBLE : return <NUM_LIT>


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return


<s> bool <ISA_LIT>InstrInfo :: isOperandLegal ( const MachineInstr * MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx


<s> unsigned NextBlockOffset , NextBlockAlignment ; MachineFunction :: const_iterator NextBlock = Water -> getIterator ( ) ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( )


<s> assert ( ( Kind == k_Register || Kind == k_Memri ) && <STR_LIT> ) ; return RegImm .


<s> static MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S


<s> if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64


<s> InsertedThunks = true ; return true ; } if ( Is64Bit ) { assert ( MF . getName ( ) == <STR_LIT> && <STR_LIT> ) ; populateThunk ( MF , <STR_LIT> ) ; } else { if ( MF . getName ( ) == EAXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == ECXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDXThunkName ) populateThunk ( MF , <STR_LIT> ) ; else if ( MF . getName ( ) == EDIThunkName ) populateThunk ( MF , <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; } return true


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT VT = Op . getValueType ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; std :: vector < EVT > NodeTys ; SDValue MFFSreg , InFlag ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant (


<s> const MachineOperand & AddrReg0 = I -> getOperand ( AddrIdx ) ; const MachineOperand & AddrReg1 = MBBI -> getOperand ( AddrIdx ) ; if ( AddrReg0 . getReg ( ) == AddrReg1 . getReg ( ) && AddrReg0 . getSubReg ( ) == AddrReg1 . getSubReg ( ) ) { int OffsetIdx = <STR_LIT> ( I -> getOpcode ( ) , <STR_LIT> :: offset ) ; unsigned Offset0 = I -> getOperand ( OffsetIdx ) . getImm ( ) & <NUM_LIT> ; unsigned Offset1 = MBBI -> getOperand ( OffsetIdx ) . getImm (


<s> static rtx xstormy16_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode


<s> if ( BaseReg ) { static const unsigned R16Table [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned RMfield = R16Table [ BaseRegNo ] ; assert ( RMfield && <STR_LIT> ) ; if ( IndexReg . getReg ( ) ) { unsigned IndexReg16 = R16Table [ get<ISA_LIT>RegNum ( IndexReg ) ] ; assert ( IndexReg16 && <STR_LIT> ) ; assert ( ( ( IndexReg16 ^ RMfield ) & <NUM_LIT> ) && <STR_LIT> ) ; assert ( Scale . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( IndexReg16 & <NUM_LIT> ) RMfield = ( RMfield & <NUM_LIT> ) | ( ( <NUM_LIT> - IndexReg16 ) << <NUM_LIT> ) ; else RMfield = ( IndexReg16 & <NUM_LIT> ) | ( ( <NUM_LIT> - RMfield ) << <NUM_LIT> ) ; } if ( Disp . isImm ( ) && isInt < <NUM_LIT> > ( Disp . getImm ( ) ) ) { if ( Disp . getImm ( ) == <NUM_LIT> && RMfield != <NUM_LIT> ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; return ; } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , StartByte , OS , Fixups ) ; return ; } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , RMfield ) , OS ) ; } else { assert ( IndexReg . getReg ( ) == <NUM_LIT> && <STR_LIT> ) ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; } emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_2 , StartByte , OS , Fixups ) ; return ; } bool UseDisp8 = MI . getFlags ( ) & <STR_LIT> ; bool UseDisp32 = MI . getFlags ( ) & <STR_LIT> ; bool AllowNoDisp = ! UseDisp8 && ! UseDisp32 ; bool AllowDisp8 = ! UseDisp32 ; if ( ! ForceSIB && IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! STI . hasFeature ( <STR_LIT> ) || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_4 , StartByte , OS , Fixups ) ; return ; } if ( BaseRegNo != N86 :: EBP ) { if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && AllowNoDisp ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } if ( Disp . isExpr ( ) ) { auto * Sym = dyn_cast < MCSymbolRefExpr > ( Disp . getExpr ( ) ) ; if ( Sym && Sym -> getKind

( ) == MCSymbolRefExpr :: VK_TLSCALL ) {


<s> FunctionPass * llvm :: create<ISA_LIT>OptAddrMode ( ) { return new <ISA_LIT>OptAddrMode


<s> SDNode * IsIntrinsic = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( IsIntrinsic -> getOpcode ( ) == <STR_LIT> ) ) { unsigned ID = cast < ConstantSDNode > ( IsIntrinsic -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( doesIntrinsicReturnPredicate ( ID ) ) { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> )


<s> seen_vector_jump = true ; vector_neutered = true ; } else if ( insn == worker_label ) { seen_worker_label = true ; gcc_assert ( worker_neutered ) ; worker_neutered = false ; } else if ( insn == vector_label ) { seen_vector_label = true ; gcc_assert ( vector_neutered ) ; vector_neutered = false ; } else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_barsync : gcc_assert ( ! vector_neutered && ! worker_neutered ) ; break ; default : break ; } if ( insn != BB_END ( bb ) ) insn = NEXT_INSN ( insn ) ; else if ( JUMP_P ( insn ) && single_succ_p ( bb ) && ! seen_vector_jump && ! seen_worker_jump ) { bb = single_succ ( bb ) ; insn = BB_HEAD ( bb ) ; } else break ; } gcc_assert ( ! ( vector_jump && ! seen_vector_jump ) ) ; gcc_assert ( ! ( worker_jump && ! seen_worker_jump ) ) ; if ( seen_vector_label || seen_worker_label ) { gcc_assert ( ! ( vector_label &&


<s> <STR_LIT> BranchCode = GetCondFromBranchOpc ( LastInst -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; <STR_LIT> BranchCode = GetCondFromBranchOpc ( SecondLastOpc ) ; if ( BranchCode != <STR_LIT> && IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( IsBRU ( SecondLastInst -> getOpcode ( ) ) && IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } return


<s> tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( pc_rtx


<s> if ( ! isa < ConstantSDNode > ( K1 ) || ! isa < ConstantSDNode > ( K2 ) ) return false ; int64_t Val1 = cast < ConstantSDNode > ( K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; int64_t NegVal = std :: min ( Val1 , Val2 ) ; if ( ! ( ( Val1 > Val2 && isLTorLE ( CC1 ) ) || ( Val1 < Val2 && isLTorLE ( CC2 ) ) ) || ! isPowerOf2_64 ( PosVal + <NUM_LIT> ) ) return false ; if ( Val1 == ~ Val2 ) Usat = false ; else if ( NegVal == <NUM_LIT> ) Usat = true ; else return false ; V = V2Tmp ; K = ( uint64_t )


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr &


<s> if ( ! MaskedImm ) return ; if ( RemSize <= <NUM_LIT> ) { AddInstr ( SeqLs , Inst ( ADDiu , MaskedImm ) ) ; return ; } if ( ! ( Imm & <NUM_LIT> ) ) { GetInstSeqLsSHL ( Imm , RemSize , SeqLs ) ; return ; } GetInstSeqLsADDiu ( Imm , RemSize , SeqLs ) ; if ( Imm & <NUM_LIT> ) { InstSeqLs SeqLsORi ; GetInstSeqLsORi ( Imm ,


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT ElemVT = VT . getScalarType ( ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( useSVEForFixedLengthVectorVT ( VT ) ) return LowerToScalableOp ( Op , DAG ) ; switch ( ElemVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { if ( auto * ConstVal = dyn_cast < ConstantSDNode > ( SplatVal ) ) { if ( ConstVal -> isZero ( ) ) return SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , VT ) , <NUM_LIT> ) ; if ( ConstVal -> isOne ( ) ) return getPTrue ( DAG , dl , VT , <STR_LIT> ) ; } SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : report_fatal_error ( <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , VT ,


<s> if ( MFI . getStackSize ( ) > <NUM_LIT> ) { const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . Options . DisableFramePointerElim ( MF ) || ! EliminateFramePointer ) return true ; if ( EnableStackOVFSanitizer ) return true ; } const auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo


<s> if ( ! ST . hasLOB ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( ST . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( MF ) ) ; MF . RenumberBlocks (


<s> return ( __m64 ) __builtin_arm_waddbhusm ( ( __v4hi )


<s> if ( WithPreDec ) { O << '-' ; } if ( Base . getReg ( ) ) { printRegister ( Base . getReg ( ) , O ) ; } if ( WithPostInc ) { O << '+' ; } O << <STR_LIT> ; if ( Offset . isImm ( ) ) { O << Offset . getImm ( ) ; } else if ( Offset . isExpr ( ) ) { O << * Offset . getExpr ( ) ; } else


<s> const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; EmitLinkage ( GV , EmittedInitSym ) ; EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; OutStreamer -> EmitLabel ( EmittedInitSym ) ; EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout (


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE , bool RelaxAll ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; return S


<s> return isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) && isIntRegForSubInst ( HRI . getSubReg


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return true ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Identifier ) ) { HwReg . IsSymbolic = true ; HwReg . Id = ID_UNKNOWN_ ; const StringRef tok = Parser . getTok ( ) . getString ( ) ; for ( int i = ID_SYMBOLIC_FIRST_ ; i < ID_SYMBOLIC_LAST_ ; ++ i ) { if ( tok == IdSymbolic [ i ] ) { HwReg . Id = i ; break ; } } Parser . Lex ( ) ; } else { HwReg . IsSymbolic = false ; if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return true ; if ( getParser ( ) . parseAbsoluteExpression (


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: EXECNZ : { Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; Register SReg2 = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: EXECZ : { Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; Register SReg2 = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; llvm_unreachable ( <STR_LIT> ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } } else { llvm_unreachable ( <STR_LIT> )


<s> if ( Ptr -> getOpcode ( ) != <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; if ( VT == <STR_LIT> || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isSEXTLoad ) ) { Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } } isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; return


<s> bool isAISrcB16 ( ) const { return isRegOrInlineNoMods ( <STR_LIT>


<s> return getMCOpcodeGen ( Opcode , ( enum Subtarget


<s> const unsigned ProdPairIndex = IsReverseVecRegPair ( Producer ) ? Producer - <STR_LIT> : Producer - <STR_LIT> ; const unsigned ConsumerSingleIndex = ( Consumer - <STR_LIT> ) >> <NUM_LIT> ; return ConsumerSingleIndex ==


<s> static bool rs6000_can_eliminate ( const int from , const int to


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg (


<s> ( void ) IsOP3 ; switch ( SrcIdx ) { case <NUM_LIT> : FlagIndex = getOperandIdx ( * MI , <STR_LIT> ) ; break ; case <NUM_LIT> : FlagIndex = getOperandIdx ( * MI , <STR_LIT> ) ; break ; } break ; default : FlagIndex = - <NUM_LIT> ; break ; } assert ( FlagIndex != - <NUM_LIT> && <STR_LIT> ) ; } else { FlagIndex = GET_FLAG_OPERAND_IDX ( TargetFlags ) ; assert ( FlagIndex != <NUM_LIT> && <STR_LIT> ) ; } MachineOperand & FlagOp = MI ->


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } }


<s> lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Instruction * Load = tryCreateIncrementingGatScat ( I , Ptr , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru ,


<s> return <STR_LIT> :: getTotalNumSGPRs ( MCSubtargetInfo


<s> bool num ( ) const { return Type == Zero || Type


<s> SDValue <ISA_LIT>TargetLowering :: performStoreCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; StoreSDNode * SN = cast < StoreSDNode > ( N ) ; if ( ! SN -> isSimple ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; Align Alignment = SN -> getAlign ( ) ; if ( Alignment < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return SplitVectorStore ( SDValue ( SN , <NUM_LIT> ) , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) )


<s> gcc_assert ( GET_CODE ( x ) == MEM ) ; x = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; fnname = XSTR ( x , <NUM_LIT> ) ; len = strlen ( fnname ) ; if ( len + SSIB_PREFIX_LEN > <NUM_LIT>


<s> } } SmallVector < MachineInstr * , <NUM_LIT> > worklist ; for ( auto MBBI = Func . begin ( ) , MBBE = Func . end ( ) ; MBBI != MBBE ; MBBI ++ ) { for ( auto MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; MI ++ ) if ( MI -> isCall ( ) ) worklist . push_back ( MI ) ; } while ( ! worklist . empty ( ) ) { MachineInstr * mi = worklist . pop_back_val ( ) ; modified |= handleCallInst ( mi )


<s> Inst . addOperand ( MCOperand :: createReg ( getGPRMM16Reg (


<s> memset ( Outputs , <NUM_LIT> , sizeof ( Outputs


<s> int FI ; if ( ( VA . isRegLoc ( ) && ! Flags . isByVal ( ) ) || ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) > <NUM_LIT> ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; } StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; FI = MFI -> CreateFixedObject ( ObjSize , StackLocation , true


<s> static std :: string computeFSAdditions ( StringRef FS , CodeGenOpt :: Level OL , const Triple & TT ) { std :: string FullFS = std :: string ( FS ) ; if ( TT . getArch ( ) == Triple :: ppc64 || TT .


<s> switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; case CallingConv :: <ISA_LIT>_INTR : report_fatal_error (


<s> bool evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const override { return


<s> const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( hasConsumedDollar ) { hasConsumedDollar = false ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return false ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) .


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) return true ; bool IsInRange = isRV64 ( ) ? true : isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ; return IsConstantImm && IsInRange && VK == <ISA_LIT>MCExpr ::


<s> static SDValue performXorCombine ( SDNode * N , SelectionDAG & DAG ,

TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) {


<s> static void riscv_file_start ( void ) { default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT>


<s> if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { if ( DefInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { I1Defs . push_back ( Dst . getReg ( ) ) ; int64_t Val = DefInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Val == <NUM_LIT> || Val == - <NUM_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . add ( Dst ) . addImm ( Val ) ; MI . eraseFromParent ( ) ; continue ; } } unsigned int TmpSrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , TmpSrc ) . add ( Src ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . add ( Dst ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( TmpSrc ) ; MI . eraseFromParent ( ) ; } else if ( TRI -> getCommonSubClass ( DstRC , & <STR_LIT> ) && SrcRC == & <STR_LIT> ) { if ( DefInst -> getOpcode ( ) == <STR_LIT> && DefInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && DefInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && DefInst -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && DefInst -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> && DefInst -> getOperand ( <NUM_LIT> ) . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( DefInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && TRI -> getCommonSubClass ( MRI . getRegClass ( DefInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) , & <STR_LIT> ) && <STR_LIT> ( DefInst -> getParent ( ) , & MBB ) ) { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . add ( Dst ) . addReg ( <STR_LIT> ) . add ( DefInst -> getOperand ( <NUM_LIT> ) ) ; } else


<s> void <ISA_LIT>InstPrinter :: printUnsignedImm ( const MCInst * MI , int OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) O << ( unsigned short int ) MO . getImm ( ) ; else printOperand ( MI , OpNum


<s> new GOTPLTEntry ( <NUM_LIT> , m_SectionData ) ; new GOTPLTEntry ( <NUM_LIT> , m_SectionData


<s> bool isSupportedTgtId ( unsigned Id , const MCSubtargetInfo &


<s> auto Mul1 = B . buildFMul ( S32 , Rcp , B . buildFConstant ( S32 , BitsToFloat ( <NUM_LIT> ) ) ) ; auto Mul2 = B . buildFMul ( S32 , Mul1 , B . buildFConstant ( S32 , BitsToFloat ( <NUM_LIT> ) ) ) ; auto Trunc = B . buildIntrinsicTrunc ( S32 , Mul2 ) ; auto Mad2 = B . buildFMAD ( S32 , Trunc , B . buildFConstant ( S32 , BitsToFloat ( <NUM_LIT> ) ) , Mul1 ) ; auto ResultLo = B . buildFPTOUI ( S32 , Mad2 ) ; auto ResultHi = B . buildFPTOUI ( S32 , Trunc ) ; return { ResultLo . getReg ( <NUM_LIT> )


<s> bool <ISA_LIT>TargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const { return VT . isScalarInteger ( )


<s> virtual const <ISA_LIT>FrameInfo * getFrameInfo ( )


<s> assert ( Extended . isExpr ( ) ) ; int64_t Value ; if ( ! Extended . getExpr ( ) -> evaluateAsAbsolute (


<s> return bitc :: BINOP_ADD ; case Instruction :: Sub : case Instruction :: FSub : return bitc :: BINOP_SUB ; case Instruction :: Mul : case Instruction :: FMul : return bitc :: BINOP_MUL ; case Instruction :: UDiv : return bitc :: BINOP_UDIV ; case Instruction :: FDiv : case Instruction :: SDiv : return bitc


<s> bool Changed = false ; if ( MOI . isAtomic ( ) ) { if ( MOI . getOrdering ( ) == AtomicOrdering :: Release || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Changed |= CC -> insertRelease ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: BEFORE ) ; return Changed ; } if ( MOI . isNonTemporal


<s> unsigned ADDu = <STR_LIT> ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < ABI . EhDataRegSize ( )


<s> unsigned <ISA_LIT>ABIInfo :: GetFramePtr ( ) const { return <STR_LIT>


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill


<s> if ( VF == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT>


<s> return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; Disp += SL -> getElementOffset ( cast < ConstantInt > ( Op ) -> getZExtValue ( ) ) ; continue ; } uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) . first ; if ( IndexReg == <NUM_LIT> ) return false ; break ; } goto unsupported_gep ; } } if ( ! isInt < <NUM_LIT> > ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; GEPs . push_back ( V ) ; if ( const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( U -> getOperand ( <NUM_LIT> ) ) ) { V = GEP ; goto redo_gep ; } else if ( <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ) { return true ; } AM = SavedAM ; for ( SmallVectorImpl < const Value * > :: reverse_iterator I = GEPs . rbegin ( ) , E = GEPs . rend ( ) ; I != E ; ++ I ) if ( handleConstantAddresses ( * I , AM ) ) return true ; return false


<s> neg = <NUM_LIT> ; } if ( b < <NUM_LIT> ) b = - b ; res = udivmodsi4 ( a , b , <NUM_LIT> ) ; if ( neg ) res


<s> } assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; std :: string name = GV -> getName ( ) ; if ( PAN :: isLocalName ( name ) ) return getSectionForAuto ( GV ) ; if ( GV -> hasExternalLinkage ( ) || GV -> hasCommonLinkage ( ) ) ExternalVarDefs -> Items . push_back ( GV ) ; const Constant * C = GV -> getInitializer ( ) ; if ( C -> isNullValue ( ) )


<s> assert ( TID . getNumDefs ( ) == <NUM_LIT> && NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; ElemSize esize = Opcode == <STR_LIT> ? ESize8 : ( Opcode == <STR_LIT> ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd


<s> assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) )


<s> gcc_assert ( ! ! start == ! ! end ) ; if ( ! const_vec_duplicate_p ( op , & elt ) || ! CONST_INT_P ( elt ) ) return false ; size = GET_MODE_UNIT_BITSIZE ( GET_MODE ( op ) ) ; if ( size > <NUM_LIT> ) return false ; mask = UINTVAL (


<s> if ( GET_CODE ( x ) != CONST_INT ) { fatal_insn ( <STR_LIT> , x ) ; } fprintf ( stream , <STR_LIT> PRId64 , ( int64_t ) ( mmix_intval ( x ) - <NUM_LIT> ) ) ; return ; case 'p' : fprintf ( stream , <STR_LIT> , cfun -> machine -> highest_saved_stack_register + <NUM_LIT> ) ; return ; case 'r' : if ( ! REG_P ( x ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_destination_register = MMIX_OUTPUT_REGNO ( regno ) ; return ; case 'I' : if ( GET_CODE ( x ) != CONST_INT && ( GET_CODE ( x ) != CONST_DOUBLE || ( GET_MODE ( x ) != VOIDmode && GET_MODE ( x ) != DFmode && GET_MODE ( x ) != SFmode ) ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_register_setting ( stream , mmix_output_destination_register , mmix_intval ( x ) , <NUM_LIT> ) ; return ; case 'U' : if ( TARGET_ZERO_EXTEND ) putc ( 'U' , stream ) ; return ; case 'v' : mmix_output_shifted_value ( stream , ( int64_t ) mmix_intval ( x ) ) ; return ; case 'V' : mmix_output_shifted_value ( stream , ( int64_t ) ~ mmix_intval ( x ) ) ; return ; case 'W' : if ( GET_CODE ( x ) != CONST_INT ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( x ) & <NUM_LIT> ) ) ; return ; case <NUM_LIT> : break ; default : internal_error ( <STR_LIT> , code ) ; } switch ( GET_CODE ( modified_x ) ) { case REG : regno = REGNO ( modified_x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) internal_error ( <STR_LIT> , regno ) ; fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( regno ) ] ) ; return ; case MEM : output_address ( GET_MODE ( modified_x ) , XEXP ( modified_x , <NUM_LIT> ) ) ; return ; case CONST_INT


<s> Value * <ISA_LIT>IREmitter :: visitATOMUMIN64_DAG ( const SDNode *


<s>
unsigned
PairedReg
=
<STR_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
PairedReg
=
CSRegs
[
i
^
<NUM_LIT>
]
;
if
(
!
RegUsed
)
{
if
(
<STR_LIT>
.
contains
(
Reg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
Reg
)
)
{
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
producePairRegisters
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
if
(
MF
.
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
&&
!
Subtarget
.
isTargetWindows
(
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
}
unsigned
CSStackSize
=
<NUM_LIT>
;
unsigned
SVECSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
{
auto
RegSize
=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
SVECSStackSize
+=
RegSize
;
else
CSStackSize
+=
RegSize
;
}
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
uint64_t
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
int64_t
SVEStackSize
=
alignTo
(
SVECSStackSize
+
estimateSVEStackObjectOffsets
(
MFI
)
,
<NUM_LIT>
)
;
bool
CanEliminateFrame
=
(
SavedRegs
.
count
(
)
==
<NUM_LIT>
)
&&
!
SVEStackSize
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
SVEStackSize
||
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo


<s> if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) && ! aarch64_vect_struct_mode_p ( mode ) ) return <NUM_LIT> ; if ( FP_REGNUM_P ( regno ) ) { if ( aarch64_vect_struct_mode_p ( mode ) ) return ( regno + aarch64_hard_regno_nregs ( regno , mode ) - <NUM_LIT> ) <= V31_REGNUM ; else return <NUM_LIT> ; } return <NUM_LIT>


<s> CONST_VECTOR_ELT ( op , i + half_units ) = temp ; } } else { int j ; const char * fmt = GET_RTX_FORMAT ( code ) ; for ( i = <NUM_LIT> ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) swap_const_vector_halves ( XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = <NUM_LIT> ; j < XVECLEN ( op ,

i ) ; ++ j ) swap_const_vector_halves ( XVECEXP ( op , i , j ) ) ;


<s> extract_base_offset_in_addr ( mem_3 , & base_3 , & offset_3 ) ; if ( base_3 == NULL_RTX || offset_3 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_4 , & base_4 , & offset_4 ) ; if ( base_4 == NULL_RTX || offset_4 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) || ! rtx_equal_p ( base_2 , base_3 ) || ! rtx_equal_p ( base_3 , base_4 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; offval_3 = INTVAL ( offset_3 ) ; offval_4 = INTVAL ( offset_4 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( ( offval_1 != ( offval_2 + msize ) || offval_1 != ( offval_3 + msize * <NUM_LIT> ) || offval_1 != ( offval_4 + msize * <NUM_LIT> ) ) && ( offval_4 != ( offval_3 + msize ) || offval_4 != ( offval_2 + msize * <NUM_LIT> ) || offval_4 != ( offval_1 + msize * <NUM_LIT> ) ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) || reg_mentioned_p ( reg_2 , mem_2 ) || reg_mentioned_p ( reg_3 , mem_3 )


<s> const auto * C = dyn_cast < MCConstantExpr > ( MO . getExpr ( ) ) ; if ( ! C ) return <NUM_LIT> ; Imm = C -> getValue ( ) ; } else { assert ( ! MO . isFPImm ( ) ) ; if ( ! MO . isImm ( ) ) return ~ <NUM_LIT> ; Imm = MO . getImm ( ) ; } switch ( OpInfo . OperandType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getLit32Encoding ( static_cast < uint32_t > ( Imm ) , STI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getLit64Encoding ( static_cast < uint64_t > ( Imm ) , STI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getLit16Encoding ( static_cast < uint16_t > ( Imm ) , STI ) ; case <STR_LIT> : case <STR_LIT> : { uint16_t Lo16 = static_cast < uint16_t >


<s> void <ISA_LIT>HazardRecognizer :: EmitNoop ( ) { AdvanceCycle ( )


<s> unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc ,

i ) ) . second ) llvm_unreachable ( <STR_LIT> ) ;


<s> VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( Align . value ( ) - <NUM_LIT> , DL , VAList . getValueType ( ) ) ) ; VAList = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( - ( int64_t ) Align . value ( ) , DL , VAList . getValueType ( ) ) ) ; } auto & TD = DAG . getDataLayout ( ) ; unsigned ArgSizeInBytes = TD . getTypeAllocSize ( VT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , DL , VAList . getValueType ( ) , VAList , DAG . getConstant ( alignTo ( ArgSizeInBytes , ArgSlotSizeInBytes ) , DL , VAList . getValueType ( ) ) ) ; Chain = DAG . getStore ( VAListLoad . getValue ( <NUM_LIT> ) , DL , Tmp3 , VAListPtr , MachinePointerInfo ( SV ) ) ; if ( ! Subtarget . isLittle (

) && ArgSizeInBytes < ArgSlotSizeInBytes ) {


<s> case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( immediate ) ; case <STR_LIT>


<s> switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : break ; case <STR_LIT> : \ return <STR_LIT> #


<s> if ( cfun -> machine -> current_frame_size <= <NUM_LIT> ) offset = cfun -> machine -> current_frame_size ; else offset = cfun -> machine -> callee_save_size ; if ( offset ) xtensa_emit_adjust_stack_ptr ( offset , ADJUST_SP_NONE ) ; } else xtensa_emit_adjust_stack_ptr ( cfun -> machine -> current_frame_size , ADJUST_SP_NONE ) ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } cfun -> machine -> epilogue_done = true ; if ( sibcall_p ) emit_use ( gen_rtx_REG ( SImode , A0_REG ) ) ; else emit_jump_insn ( gen_return ( )


<s> void GCNMaxOccupancySchedStrategy :: initialize ( ScheduleDAGMI * DAG ) { GenericScheduler :: initialize ( DAG ) ; MF = & DAG -> MF ; const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; const unsigned ErrorMargin = <NUM_LIT> ; SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo & MFI = * MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; TargetOccupancy = MFI . getOccupancy ( ) ; SGPRCriticalLimit = std :: min ( ST . getMaxNumSGPRs ( TargetOccupancy , true ) , SGPRExcessLimit ) ; VGPRCriticalLimit = std :: min ( ST . getMaxNumVGPRs ( TargetOccupancy ) ,


<s> typename __altivec_bool_ret < vec_step ( T ) > :: __ret \ NAME ( T


<s> if ( GET_CODE ( x ) != TRUNCATE ) return <NUM_LIT> ; reg = XEXP ( x , <NUM_LIT> ) ; if ( GET_MODE_SIZE ( GET_MODE ( reg ) ) > <NUM_LIT> && GET_CODE (


<s> void printMemspi ( const MCInst * MI ,


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __bextr_u64 ( unsigned long long __X


<s> SDValue V0 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3


<s> SDValue <ISA_LIT>TargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const { SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , Shamt


<s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module &


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM


<s> if ( SrcReg != <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else { NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( RC == <STR_LIT> ) { if ( ( Enable<ISA_LIT>32RS && ! TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ) || ( Enable<ISA_LIT>64RS && TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else { NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned ShiftBits = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( SrcReg ) * <NUM_LIT> ; NewMIs . push_back ( BuildMI ( MF , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ShiftBits ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; } NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } } else if ( RC == <STR_LIT> ) { unsigned Reg = <NUM_LIT> ; if ( SrcReg >= <STR_LIT> || SrcReg <= <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg >= <STR_LIT> || SrcReg <= <STR_LIT> ) Reg = <STR_LIT> ; else if ( SrcReg >= <STR_LIT> || SrcReg <=


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: lowerEH_RETURN ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>FI -> setCallsEhReturn ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = IsN64 ?


<s> Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt


<s> int words ; unsigned int size = ( ( ( mode == BLKmode && type ) ? ( unsigned int ) int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( * cum >= M32R_MAX_PARM_REGS ) words = <NUM_LIT> ; else if ( * cum + size > M32R_MAX_PARM_REGS ) words = ( * cum + size ) - M32R_MAX_PARM_REGS ; else words = <NUM_LIT> ; return words *


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst


<s> } for ( const User * U : C -> users ( ) ) if ( const Constant * C = dyn_cast < Constant > ( U )

) if ( usedInGlobalVarDef ( C ) ) return true ;


<s> switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : return MCDisassembler :: Fail ; default : align = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn )


<s> if ( isPredicated ( MI ) ) return true ; MachineBasicBlock :: const_iterator Next = & MI ; ++ Next ; Register SrcReg , SrcReg2 ; int CmpMask , CmpValue ; bool


<s> if ( TheTriple . isOSBinFormatMachO ( ) && TheTriple . getArch ( ) == Triple :: x86_64 ) return create<ISA_LIT>_64MachORelocationInfo ( Ctx ) ; else if ( TheTriple . isOSBinFormatELF ( ) ) return

create<ISA_LIT>_64ELFRelocationInfo ( Ctx ) ;


<s> DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT>


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { llvm_unreachable (


<s> return Kind == k_Register && ! Reg . isVector && <ISA_LIT>MCRegisterClasses

[ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> unsigned Opc = MI -> getOpcode ( ) ; int EnIdx = <STR_LIT> ( Opc , <STR_LIT> :: en ) ; unsigned En = MI -> getOperand ( EnIdx ) . getImm ( ) ; int ComprIdx = <STR_LIT> ( Opc , <STR_LIT> :: compr ) ; if ( MI -> getOperand ( ComprIdx ) . getImm ( ) ) OpNo = OpNo - N + N / <NUM_LIT> ; if ( En & ( <NUM_LIT> << N ) ) printRegOperand ( MI -> getOperand ( OpNo


<s> char * q ; while ( ( q = strtok ( p , <STR_LIT> ) ) != NULL ) { bool error_p = false ; bool not_valid_p = false ; const char * cpu_opt = NULL ; p = NULL ; if ( strncmp ( q , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { int cpu_index = rs6000_cpu_name_lookup ( q + <NUM_LIT> ) ; if ( cpu_index >= <NUM_LIT> ) rs6000_cpu_index = cpu_index ; else { error_p = true ; cpu_opt = q + <NUM_LIT> ; } } else if ( strncmp ( q , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { int tune_index = rs6000_cpu_name_lookup ( q + <NUM_LIT> ) ; if ( tune_index >= <NUM_LIT> ) rs6000_tune_index = tune_index ; else { error_p = true ; cpu_opt = q + <NUM_LIT> ; } } else { size_t i ; bool invert = false ; char * r = q ; error_p = true ; if ( strncmp ( r , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { invert = true ; r += <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( rs6000_opt_masks ) ; i ++ ) if ( strcmp ( r , rs6000_opt_masks [ i ] . name ) == <NUM_LIT> ) { HOST_WIDE_INT mask = rs6000_opt_masks [ i ] . mask ; if ( ! rs6000_opt_masks [ i ] . valid_target ) not_valid_p = true ; else { error_p = false ; rs6000_isa_flags_explicit |= mask ; if ( mask == OPTION_MASK_VSX && ! invert ) mask |= OPTION_MASK_ALTIVEC ; if ( rs6000_opt_masks [ i ] . invert ) invert = ! invert ; if ( invert ) rs6000_isa_flags &= ~ mask ; else rs6000_isa_flags |= mask


<s> bool <ISA_LIT>InstrInfo :: isCompoundBranchInstr ( const MachineInstr & MI ) const { return ( getType ( MI ) == <STR_LIT> &&


<s> static const uint16_t CtrlReg64DecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] ==

<STR_LIT> ) return MCDisassembler :: Fail ;


<s> return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: IndirectBr : return SelectIndirectBr ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return SelectCmp ( I ) ; case Instruction :: Select : return SelectSelect ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: FPToSI : return SelectFPToInt ( I , true ) ; case Instruction :: FPToUI : return SelectFPToInt ( I , false ) ; case Instruction :: SIToFP : return SelectIntToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIntToFP ( I , false ) ; case Instruction :: SRem : return SelectRem ( I , <STR_LIT> ) ; case Instruction :: URem : return SelectRem ( I , <STR_LIT>


<s> else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT>


<s> return ( __m256i ) __builtin_ia32_permvarhi256_mask ( ( __v16hi ) __B , ( __v16hi ) __A , (


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI , getSubtargetInfo ( ) ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel ( PICBase ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( DotExpr ) ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; case <STR_LIT> : EmitToStreamer ( OutStreamer , MCInstBuilder ( getRetOpcode ( * Subtarget


<s> if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else { if ( UseInfo -> RegClass != <STR_LIT> && UseInfo -> RegClass != <STR_LIT> ) return false ; } if ( UseInfo -> Constraints != <NUM_LIT> ) return false ; unsigned ZeroReg ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; ZeroReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; } else { ZeroReg = UseInfo -> RegClass == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI -> getOperand ( UseIdx ) . setReg ( ZeroReg


<s> if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; bool NeedsAligna = needsAligna ( MF ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken ) { return


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : return make_vector < unsigned > ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( ) const { return &


<s> return isMem256 ( ) && isMemIndexReg ( <STR_LIT> ,


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return MFI -> getShaderType ( ) != ShaderType :: COMPUTE

&& usesVertexCache ( MI -> getOpcode ( ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { LastIssued . Array [ i ] += Increment . Array [ i ] ; if ( Increment . Array [ i ] ) Limit . Array [ i ] = LastIssued . Array [ i ] ; Sum += Increment . Array [ i ] ; } if ( Sum == <NUM_LIT> ) { LastOpcodeType = OTHER ; return ; } if ( MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( LastOpcodeType == VMEM && Increment . Named . VM ) { BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; LastInstWritesM0 = false ; } if ( TII -> isSMRD ( * I ) ) LastOpcodeType = SMEM ; else if ( Increment . Named . VM ) LastOpcodeType = VMEM ; } if ( Increment . Named . EXP ) { ExpInstrTypesSeen |= I -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = I -> getOperand ( i ) ; if ( ! isOpRelevant (


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { unsigned OffHi = ( unsigned ) Offset >> <NUM_LIT> ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister


<s> } const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP ) continue ; unsigned AS = GEP -> getAddressSpace ( ) ; unsigned Threshold = <NUM_LIT> ; if ( AS == ASST . PRIVATE_ADDRESS ) Threshold = ThresholdPrivate ; else if ( AS == ASST . LOCAL_ADDRESS ) Threshold = ThresholdLocal ; else continue ; if ( UP . Threshold >= Threshold ) continue ; if ( AS == ASST . PRIVATE_ADDRESS ) { const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr , DL ) ) ; if ( ! Alloca || ! Alloca -> isStaticAlloca ( ) ) continue ; Type * Ty = Alloca -> getAllocatedType ( ) ; unsigned AllocaSize = Ty -> isSized ( ) ? DL . getTypeAllocSize ( Ty ) : <NUM_LIT> ; if ( AllocaSize > MaxAlloca ) continue ; } else if ( AS == ASST . LOCAL_ADDRESS ) { LocalGEPsSeen ++ ; if ( LocalGEPsSeen > <NUM_LIT> || L -> getLoopDepth ( ) > <NUM_LIT> || ( ! isa < GlobalVariable > ( GEP -> getPointerOperand ( ) ) && ! isa < Argument > ( GEP -> getPointerOperand ( ) ) ) ) continue ; } bool HasLoopDef = false ; for ( const Value * Op : GEP -> operands ( ) ) { const Instruction * Inst = dyn_cast < Instruction > ( Op ) ; if ( ! Inst || L -> isLoopInvariant ( Op ) ) continue ; if ( llvm :: any_of ( L -> getSubLoops ( ) , [ Inst ] ( const Loop * SubLoop ) { return SubLoop -> contains ( Inst ) ; } ) ) continue ; HasLoopDef = true ; break ; } if ( ! HasLoopDef ) continue ; UP . Threshold


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , DAG . getConstant (

<NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , TmpExec ) ; BuildMI ( MBB , I , DL , TII -> get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; MachineBasicBlock * LoopBB ; MachineBasicBlock * RemainderBB ; std :: tie ( LoopBB , RemainderBB ) = splitBlockForLoop ( MI , MBB , false ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; auto InsPt = emitLoadM0FromVGPRLoop ( TII , MRI , MBB , * LoopBB , DL , * Idx , InitResultReg , DstReg , PhiReg , TmpExec , Offset , UseGPRIdxMode , IsIndirectSrc ) ; MachineBasicBlock :: iterator First =


<s> for ( const avr_mcu_t * mcu = avr_mcu_types ; ; mcu ++ ) { if ( mcu -> name == NULL ) { error ( <STR_LIT> , avr_mmcu , <STR_LIT> ) ; avr_inform_core_architectures ( ) ; break ; } else if ( strcmp ( mcu -> name , avr_mmcu ) == <NUM_LIT> && mcu -> macro == NULL ) { avr_arch = & avr_arch_types [ mcu -> arch_id ] ; if ( avr_n_flash < <NUM_LIT> ) avr_n_flash = <NUM_LIT> + ( mcu -> flash_size - <NUM_LIT> ) / <NUM_LIT> ; return true


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld

:: The<ISA_LIT>_64Target , mcld :: create<ISA_LIT>DiagLineInfo ) ;


<s> static StackOffset getStackOffset ( const MachineFunction & MF , int64_t ObjectOffset ) { const auto & MFI = MF . getFrameInfo ( ) ; return { ObjectOffset + ( int64_t ) MFI .


<s> MachineBasicBlock * <ISA_LIT>MachineCFGStructurizer :: splitEntry ( LinearizedRegion * LRegion ) { MachineBasicBlock * Entry = LRegion -> getEntry ( ) ; MachineBasicBlock * EntrySucc = split ( Entry -> getFirstNonPHI ( ) ) ; MachineBasicBlock * Exit = LRegion -> getExit ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * Entry ) << <STR_LIT> << printMBBReference

( * Entry ) << <STR_LIT> << printMBBReference ( * EntrySucc ) << <STR_LIT> ) ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return &


<s> void <ISA_LIT>SpeculationHardening :: insertSPToRegTaintPropagation ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { if ( UseControlFlowSpeculationBarrier ) { insertFullSpeculationBarrier ( MBB , MBBI , DebugLoc ( ) ) ; return ; } BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse ( <STR_LIT> )

. addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> if ( TARGET_64BIT && TARGET_LONG64 ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; strcpy ( tmp , <STR_LIT> ) ; output_asm_insn ( strcat ( tmp , & loop_lab [ <NUM_LIT> ] ) , xops ) ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops


<s> if ( ! LateCFGStructurize ) { addPass ( createStructurizeCFGPass ( true ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( create<ISA_LIT>AnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( create<ISA_LIT>AnnotateControlFlowPass (


<s> SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftLeftHi1 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , One ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi1 , XLenMinus1Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRightLo , ShiftLeftHi ) ; SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusXLen ) ; SDValue HiFalse = IsSRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , XLenMinus1 ) : Zero ; SDValue CC = DAG . getSetCC ( DL , VT , ShamtMinusXLen , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , LoFalse ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC , HiTrue , HiFalse ) ; SDValue Parts [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Parts ,


<s> MCCodeEmitter * llvm :: create<ISA_LIT>BEMCCodeEmitter ( const MCInstrInfo & MCII , MCContext &


<s> MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt = C -> getAPIntValue ( ) ; Ops . push_back ( DAG . getConstant ( CInt . zextOrTrunc (


<s> if ( auto * GV = dyn_cast < GlobalVariable > ( LdInst -> getOperand ( <NUM_LIT> ) ) ) { if ( GV -> hasAttribute ( <STR_LIT> ) || GV -> hasAttribute ( <STR_LIT> ) ) return false ; } } if ( ! isa < LoadInst > ( & I ) && ! isa < CallInst > ( & I ) ) return false ; bool isCandidate = false ; SmallVector < PassThroughInfo , <NUM_LIT> > Candidates ; for ( User * U : I . users ( ) ) { Instruction * Inst = dyn_cast < Instruction > ( U ) ; if ( ! Inst ) continue ; if ( auto * Icmp1 = dyn_cast < ICmpInst > ( Inst ) ) { Value * Icmp1Op1 = Icmp1 -> getOperand ( <NUM_LIT> ) ; if ( ! isa < Constant > ( Icmp1Op1 ) ) return false ; isCandidate = true ; continue ; } if ( Inst -> getParent ( ) == I . getParent ( ) ) continue ; for ( auto & I2 : * Inst -> getParent ( ) ) { if ( dyn_cast < CallInst > ( & I2 ) ) return false ; if ( dyn_cast < LoadInst > ( & I2 ) || dyn_cast < StoreInst > ( & I2 ) ) return false ; if ( & I2 == Inst ) break ; } if ( Inst -> getOpcode ( ) == Instruction :: ZExt || Inst -> getOpcode ( ) == Instruction :: SExt ) { PassThroughInfo Info ( & I , Inst , <NUM_LIT> ) ; Candidates . push_back ( Info ) ; } else if ( auto * GI = dyn_cast < GetElementPtrInst > ( Inst ) ) { unsigned i , e ; for ( i = <NUM_LIT> , e = GI -> getNumOperands ( ) ; i != e ; ++ i ) { Value * V = GI -> getOperand ( i ) ; if ( V == & I ) break ; } if ( i == e ) continue ; PassThroughInfo Info ( & I , GI , i ) ; Candidates . push_back ( Info ) ; } } if ( ! isCandidate || Candidates . empty ( ) ) return false ; llvm :: append_range ( PassThroughs ,


<s> if ( TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> , get_decl_name ( decl1 ) , get_decl_name ( decl2 ) , ret ) ; return ret


<s> void Emitter < CodeEmitter > :: emitExternalSymbolAddress ( const char * ES


<s> if ( arch -> common . extensions == NULL ) continue ; arm_initialize_isa ( target_isa , arch -> common . isa_bits ) ; for ( ext1 = arch -> common . extensions ; ext1 -> name != NULL ; ++ ext1 ) { if ( ext1 -> alias ) continue ; arm_initialize_isa ( isa1 , ext1 -> isa_bits ) ; for ( ext2 = ext1 + <NUM_LIT> ; ext2 -> name != NULL ; ++ ext2 ) { if ( ext2 -> alias || ext1 -> remove != ext2 -> remove ) continue ; arm_initialize_isa ( isa2 , ext2 -> isa_bits ) ; ASSERT_TRUE ( ! bitmap_subset_p ( isa2 , isa1 ) ) ; ASSERT_TRUE ( ! bitmap_intersect_p ( isa2 , target_isa ) ) ; } } } for ( cpu = all_cores ; cpu -> common .


<s> const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned WorkGroupSize = MFI -> getMaxFlatWorkGroupSize ( ) ; unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( &


<s> return hasSGPRs ( RC ) && ! hasVGPRs ( RC ) && ! hasAGPRs