<s> else if ( ( C = dyn_cast < ConstantSDNode > ( Op2 ) ) ) SetCC = Op1 ; else return SDValue ( ) ; if ( C -> getZExtValue ( ) == <NUM_LIT> ) { needOppositeCond = ! needOppositeCond ; checkAgainstTrue = true ; } else if ( C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; bool truncatedToBoolWithAnd = false ; while ( SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> || SetCC . getOpcode ( ) == <STR_LIT> ) { if ( SetCC . getOpcode ( ) == <STR_LIT> ) { int OpIdx = - <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand ( <NUM_LIT> ) ) ) OpIdx = <NUM_LIT> ; if ( isOneConstant ( SetCC . getOperand ( <NUM_LIT> ) ) ) OpIdx = <NUM_LIT> ; if ( OpIdx == - <NUM_LIT> ) break ; SetCC = SetCC . getOperand ( OpIdx ) ; truncatedToBoolWithAnd = true ; } else SetCC = SetCC . getOperand ( <NUM_LIT> ) ; } switch ( SetCC . getOpcode ( ) ) { case <STR_LIT> : if ( checkAgainstTrue && ! truncatedToBoolWithAnd ) break ; assert ( <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && <STR_LIT> ) ; case <STR_LIT> : CC = <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) ; if ( needOppositeCond ) CC = <STR_LIT> ( CC ) ; return SetCC . getOperand ( <NUM_LIT> ) ; case <STR_LIT> : { ConstantSDNode * FVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * TVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; if ( ! TVal ) return SDValue ( ) ; if ( ! FVal ) { SDValue Op = SetCC . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || Op . getResNo ( ) != <NUM_LIT> ) return SDValue ( ) ; } bool FValIsFalse = true ; if ( FVal && FVal -> getZExtValue ( ) != <NUM_LIT> ) { if ( FVal -> getZExtValue ( ) != <NUM_LIT> )


<s> DebugLoc DL = GSDN -> getDebugLoc ( ) ; const GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag , GV ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOHiFlag ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GSDN -> getOffset ( ) , MOLoFlag ) ; SDValue Ptr = LowerLabelRef ( GAHi , GALo , isPIC ,


<s> if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return <NUM_LIT>


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( ! ( GV = GA -> getBaseObject ( ) ) ) return false ; if ( const auto * V = dyn_cast < GlobalVariable > (


<s> bool <ISA_LIT>DagToDagISel :: SelectAddr ( SDNode * Parent , SDValue Addr , SDValue & Base , SDValue & Offset ) { return true


<s> do { Stage ++ ; RegionIdx = <NUM_LIT> ; MachineBasicBlock * MBB = nullptr ; if ( Stage > <NUM_LIT> ) { if ( ! LIS || StartingOccupancy <= MinOccupancy ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MinOccupancy << <STR_LIT> ) ; S . setTargetOccupancy ( MinOccupancy ) ; } for ( auto Region : Regions ) { RegionBegin = Region . first ; RegionEnd = Region . second ; if ( RegionBegin -> getParent ( ) != MBB ) { if ( MBB ) finishBlock ( ) ; MBB = RegionBegin -> getParent ( ) ; startBlock ( MBB ) ; if ( Stage == <NUM_LIT> ) computeBlockPressure ( MBB ) ; } unsigned NumRegionInstrs = std :: distance ( begin ( ) , end ( ) ) ; enterRegion ( MBB , begin ( ) , end ( ) , NumRegionInstrs ) ; if ( begin ( ) == end ( ) || begin ( ) == std :: prev ( end ( ) ) ) { exitRegion ( ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << MF . getName ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> <<

MBB -> getName ( ) << <STR_LIT> << * begin ( ) << <STR_LIT> ;


<s> if ( Opcode == TargetOpcode :: COPY_TO_REGCLASS ) return ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<= <NUM_LIT> ; } ++ MCNumEmitted


<s> if ( ! hasFP ( MF ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator LastFrameDestroy = MBBI ; size_t CalleeSavedSize = getCalleeSavedSize ( MFI . getCalleeSavedInfo ( ) , MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; std :: advance ( LastFrameDestroy , - CalleeSavedSize ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - StackSize , MachineInstr :: FrameDestroy ) ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg ,


<s> EVT <ISA_LIT>TargetLowering :: getEquivalentBitType ( LLVMContext & Ctx , EVT VT ) { unsigned StoreSize = VT .


<s> if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) -> getVectorElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ; if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment )


<s> bool has<ISA_LIT>r2 ( ) const { return <ISA_LIT>ArchVersion >=


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( auto Reg : <STR_LIT> ) { Reserved . set ( getSubReg ( Reg , <STR_LIT> ) ) ; Register Low = getSubReg ( Reg , <STR_LIT> ) ; if ( ! <STR_LIT> . contains ( Low ) ) Reserved . set ( Low ) ; } for ( auto Reg : <STR_LIT> ) { Reserved . set ( getSubReg ( Reg , <STR_LIT> ) ) ; } if ( ! ST . hasMAIInsts ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MaxNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo


<s> if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; if ( MO . getReg ( ) != <STR_LIT> ) continue ; assert ( LiveCPSR


<s> bool <ISA_LIT>DAGToDAGISel :: isPointer ( ) { return ptyType


<s> MachineInstr * RootI = getDefIgnoringCopies ( Root , MRI ) ; if ( RootI -> getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return { Root , <NUM_LIT> } ; MachineOperand & RHS = RootI -> getOperand ( <NUM_LIT> ) ; Optional < ValueAndVReg > MaybeOffset = getConstantVRegValWithLookThrough ( RHS . getReg (


<s> AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; FunctionPass :: getAnalysisUsage


<s> AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( Ty && Ty -> getBitWidth ( ) == <NUM_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; } return


<s> bool <ISA_LIT>ShortenInst :: runOnMachineFunction ( MachineFunction & F ) { const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed


<s> return visium_data_alignment ( TREE_TYPE ( exp


<s> } } if ( ldm_p ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ldm_regs ) ) ; int regno , slot ; for ( regno = sreg , slot = <NUM_LIT> ; regno <= ereg ; regno ++ , slot ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , slot * <NUM_LIT> ) ; rtx set = gen_rtx_SET ( reg , gen_frame_mem ( SImode , addr ) ) ; XVECEXP ( par , <NUM_LIT> , slot ) = set ; } insn = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; for ( regno = sreg ; regno <= ereg ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } } } expand_csky_stack_adjust ( adjust ) ; if ( crtl -> calls_eh_return ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx


<s> OperandMatchResultTy parseBDVAddr64 ( OperandVector


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { SMLoc CurLoc = getLoc ( ) ; StringRef CPU , ExtensionString ; std :: tie ( CPU , ExtensionString ) = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) . split ( '+' ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return true ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( CurLoc , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( CPU , CPU , <STR_LIT> ) ; CurLoc = incrementLoc ( CurLoc , CPU . size ( ) ) ; ExpandCryptoAEK ( llvm :: <STR_LIT> ( CPU ) , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { CurLoc = incrementLoc ( CurLoc , <NUM_LIT> ) ; bool EnableFeature = true ; if ( Name . startswith_insensitive ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } bool FoundExtension = false ; for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension . Features ) ; FeatureBitset Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; FoundExtension = true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> + HasVEX_4V + HasEVEX_K ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( __m256i ) __builtin_ia32_psadbw256 ( ( __v32qi )


<s> const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OrigSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Flags = MI . getFlags ( ) ; assert ( ST . hasFractBug ( ) && MRI . getType ( Dst ) == S64 && <STR_LIT> ) ; auto Fract = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( OrigSrc ) . setMIFlags ( Flags ) ; Register ModSrc = stripAnySourceMods ( OrigSrc , MRI ) ; auto Const = B . buildFConstant ( S64 , BitsToDouble ( <NUM_LIT> ) ) ; Register Min = MRI . createGenericVirtualRegister ( S64 ) ; const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getMode ( ) . IEEE ) B . buildFMinNumIEEE ( Min , Fract , Const , Flags ) ; else B . buildFMinNum ( Min , Fract , Const , Flags ) ; Register CorrectedFract = Min ; if ( ! MI . getFlag ( MachineInstr :: FmNoNans ) ) { auto IsNan = B . buildFCmp ( CmpInst :: FCMP_ORD , S1 , ModSrc , ModSrc , Flags ) ; CorrectedFract = B . buildSelect ( S64 , IsNan , ModSrc , Min , Flags ) . getReg ( <NUM_LIT> ) ; } auto NegFract = B . buildFNeg ( S64 , CorrectedFract , Flags ) ; B . buildFAdd ( Dst , OrigSrc , NegFract , Flags ) ; MI . eraseFromParent ( ) ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT>


<s> const TargetRegisterClass * RC ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) RC = MRI . getRegClass ( Reg ) ; else RC = getPhysRegClass ( Reg ) ; return hasVGPRs ( RC )


<s> std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; if ( ST . isTarget64BitILP32 ( ) || ! ST . is64Bit ( ) ) Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isOSWindows ( ) || ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT>


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned


<s> DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( spOffset < <NUM_LIT> ) ? ( stackSize - spOffset ) : ( spOffset + <NUM_LIT> ) ; Offset += MI . getOperand ( oi ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( oi ) . ChangeToImmediate ( Offset ) ; MI . getOperand ( i ) . ChangeToRegister


<s> if ( SPRegClass . contains ( RegNo ) ) return


<s> SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel


<s> if ( ( ( I + <NUM_LIT> ) >= EndIdx ) || ( ( NumGradients / <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> && ( I == DimIdx + ( NumGradients / <NUM_LIT> ) - <NUM_LIT> || I == DimIdx + NumGradients - <NUM_LIT> ) ) ) { if ( Addr . getValueType ( ) != <STR_LIT> ) Addr = DAG . getBitcast ( <STR_LIT> , Addr ) ; Addr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Addr ) ; } else { Addr = DAG . getBuildVector ( PackVectorVT , DL , { Addr , Op . getOperand ( I + <NUM_LIT> ) } ) ; I ++ ; } Addr = DAG . getBitcast ( <STR_LIT> ,


<s> vec_uint4 bsel = ( vec_uint4 ) vec_sra ( ( vec_int4 ) ( b ) , ( vec_uint4 ) vec_splat ( ( ( vec_uint4 ) si_from_int ( <NUM_LIT> ) ) , <NUM_LIT> ) ) ; bsel = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) bsel , ( vec_uchar16 ) bsel , splat_hi ) ; vec_uint4 abor = vec_subc ( ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) , aabs ) ; vec_uchar16 pat = vec_sel ( ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , vec_sr ( borrow_shuffle , vec_splat_u8 ( <NUM_LIT> ) ) , vec_sra ( borrow_shuffle , vec_splat_u8 ( <NUM_LIT> ) ) ) ; abor = ( vec_uint4 ) ( vec_perm ( vec_perm ( ( vec_uchar16 ) abor , ( vec_uchar16 ) abor , borrow_shuffle ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , pat ) ) ; vec_uint4 aneg = vec_add ( vec_add ( vec_splat_u32 ( <NUM_LIT> ) , vec_nor ( aabs , aabs ) ) , vec_and ( abor , vec_splat_u32 ( <NUM_LIT> ) ) ) ; vec_int4 aval = ( vec_int4 ) vec_sel ( ( vec_uchar16 ) aabs , ( vec_uchar16 ) aneg , ( vec_uchar16 ) asel ) ; vec_uint4 bbor = vec_subc ( ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) , babs ) ; bbor = ( vec_uint4 ) ( vec_perm ( vec_perm ( ( vec_uchar16 ) bbor , ( vec_uchar16 ) bbor , borrow_shuffle ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , pat ) ) ; vec_uint4 bneg = vec_add ( vec_nor ( babs , babs ) , vec_and ( bbor , vec_splat_u32 ( <NUM_LIT> ) ) ) ; vec_int4 bval = ( vec_int4 ) vec_sel ( ( vec_uchar16 ) babs , ( vec_uchar16 ) bneg , ( vec_uchar16 ) bsel ) ; vec_uint4 gt_hi = ( vec_uint4 ) vec_cmpgt ( aval , bval ) ; vec_uint4 gt_lo = ( vec_uint4 ) vec_cmpgt ( ( vec_uint4 ) aval , ( vec_uint4 ) bval ) ; vec_uint4 eq = ( vec_uint4 ) vec_cmpeq ( aval , bval ) ; vec_uint4 eqgt = vec_and ( eq , vec_slo ( gt_lo


<s> BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) , NewSrcReg ) . addReg ( SrcReg ) ; SrcReg = NewSrcReg ; } if ( SubRegs == <NUM_LIT> ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { Register SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR

) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ;


<s> temp << reader -> readLine ( line ) ; temp << <STR_LIT> ; this -> OutStreamer . EmitRawText ( Twine ( temp .


<s> StoreSDNode * ST = cast < StoreSDNode > ( Op ) ; assert ( ! ST -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( ST -> getMemoryVT ( ) == <STR_LIT> && <STR_LIT> ) ; if ( allowsMemoryAccessForAlignment ( Context , DAG . getDataLayout ( ) , ST -> getMemoryVT ( ) , * ST -> getMemOperand ( ) ) ) return SDValue ( ) ; SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; SDLoc dl ( Op ) ; if ( ST -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , Align ( <NUM_LIT> ) , ST -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , Align ( <NUM_LIT> ) , ST -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( Context ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry ) ; Entry . Node = Value ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG


<s> static unsigned copyPhysRegOpcode_AVX512 ( unsigned & DestReg , unsigned & SrcReg ) { if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) { DestReg = get512BitSuperRegister ( DestReg ) ; SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( MaskRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <STR_LIT> ) ; return <STR_LIT> ; } if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && MaskRegClassContains ( SrcReg ) ) { DestReg = get<ISA_LIT>SubSuperRegister (


<s> Parser . Lex ( ) ; return false ; } else if ( getLexer ( ) . is ( AsmToken :: Equal ) ) { getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const AsmToken & Reg = Parser . getTok ( ) ; if ( Reg . is ( AsmToken :: Identifier ) ) { AtRegNo = matchCPURegisterName ( Reg . getIdentifier ( ) ) ; } else if ( Reg . is ( AsmToken :: Integer ) ) { AtRegNo = Reg . getIntVal


<s> SmallVector < MachineOperand , <NUM_LIT> > LCond ; bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ; if ( NotAnalyzed ) return nullptr ; if ( TB == Latch ) TB = ( LTB == Header ) ? LTB : LFB ; else FB = ( LTB == Header ) ? LTB : LFB ; } assert ( ( ! FB || TB == Header || FB == Header ) && <STR_LIT> ) ; if ( ! TB || ( FB && TB != Header && FB != Header ) ) return nullptr ; bool Negated = TII -> predOpcodeHasNot ( Cond ) ^ ( TB != Header ) ; unsigned PredReg , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredReg , PredPos , PredRegFlags ) ) return nullptr ; MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ; unsigned CondOpc = CondI -> getOpcode ( ) ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int Mask = <NUM_LIT> , ImmValue = <NUM_LIT> ; bool AnalyzedCmp = TII -> analyzeCompare ( * CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ; if ( ! AnalyzedCmp ) return nullptr ; OldInsts . push_back ( CondI ) ; OldInsts . push_back ( IVOp ) ; Comparison :: Kind Cmp ; bool isSwapped = false ; const MachineOperand & Op1 = CondI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op2 = CondI -> getOperand ( <NUM_LIT> ) ; const MachineOperand * EndValue = nullptr ; if ( Op1 . isReg ( ) ) { if ( Op2 . isImm ( ) || Op1 . getReg ( ) == IVReg ) EndValue = & Op2 ; else { EndValue = & Op1 ; isSwapped = true ; } } if ( ! EndValue ) return nullptr ; Cmp = getComparisonKind ( CondOpc , InitialValue , EndValue , IVBump ) ; if ( ! Cmp ) return nullptr ; if ( Negated ) Cmp = Comparison :: getNegatedComparison ( Cmp ) ; if ( isSwapped ) Cmp = Comparison :: getSwappedComparison ( Cmp ) ; if ( InitialValue -> isReg ( ) ) { unsigned R = InitialValue -> getReg ( ) ; MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ; if ( ! MDT -> properlyDominates ( DefBB , Header ) ) return nullptr ; OldInsts . push_back ( MRI ->


<s> return ( __m512i ) __builtin_ia32_psrawi512_mask ( ( __v32hi ) __A , __imm , (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveR19R20X ( SMLoc L ) { int64_t Offset ; if ( parseImmExpr ( Offset


<s> static rtx riscv_got_load_tls_ie ( rtx dest , rtx sym ) { if ( Pmode == DImode ) return gen_got_load_tls_iedi ( dest , sym ) ; else return gen_got_load_tls_iesi ( dest , sym )


<s> return __builtin_mve_vrev32q_m_fv8hf ( __arm_vuninitializedq_f16 ( ) ,


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer


<s> int RegNo = ( int ) ( DefIdx + <NUM_LIT> ) - DefMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( DefClass , DefIdx ) ; int DefCycle ; if ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA7 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle +=


<s> inline static CondCode getInvertedCondCode ( CondCode Code ) { switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return NE ; case NE : return EQ ; case HS : return LO ; case LO : return HS ; case MI : return PL ; case PL : return MI ; case VS : return VC ; case VC : return VS ; case HI :


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand (


<s> FunctionPass * llvm :: create<ISA_LIT>FixupVectorISelPass (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , true ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , false ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , true ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , false ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddressELF (


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> break ; case <STR_LIT> : if ( Const ) { assert ( ConstVal != - <NUM_LIT> && <STR_LIT> ) ; ++ ConstVal ; TCC = <STR_LIT> ; break ; } Const = nullptr ; std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : Const = nullptr ; std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LHS = EmitFlipSign ( DL , LHS , DAG ) ; if ( Const ) ConstVal ^= SignVal ; else RHS = EmitFlipSign ( DL , RHS , DAG ) ; TCC = <STR_LIT> ; break ; case <STR_LIT> : Const = nullptr ; std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LHS = EmitFlipSign ( DL , LHS , DAG ) ; if ( Const ) ConstVal ^= SignVal ; else RHS = EmitFlipSign ( DL , RHS , DAG ) ; TCC = <STR_LIT> ; break ; } switch ( TCC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : if ( VT != <STR_LIT> && Const ) { Opc = <STR_LIT>


<s> prepareVolatileOrAtomicLoad ( SDValue Chain , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain


<s> bool <ISA_LIT>TargetELFStreamer :: EmitISAVersion ( ) { auto & Context = getContext ( ) ; auto * DescBegin = Context . createTempSymbol ( ) ; auto * DescEnd = Context . createTempSymbol ( ) ; auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; EmitNote ( ElfNote :: NoteNameV2 , DescSZ , ELF :: NT_AMD_HSA_ISA_NAME , [ & ] ( MCELFStreamer & OS ) { OS . emitLabel ( DescBegin ) ; OS . emitBytes ( getTargetID ( ) -> toString ( ) ) ; OS . emitLabel ( DescEnd ) ; }


<s> TargetPassConfig :: addILPOpts ( ) ; return false


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts % <NUM_LIT> != <NUM_LIT> ) return false ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != Idx ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; } return


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM

, CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) {


<s> bool hasAtomicFaddInsts ( ) const { return HasAtomicFaddRtnInsts ||


<s> unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo


<s> return lowerCall ( MIRBuilder , CallConv , Callee , OrigRet

, OrigArgs , <NUM_LIT> , KnownCallees ) ;


<s> BitVector Reserved = MRI . getReservedRegs ( ) ; BitVector CalleeSaved ( TRI -> getNumRegs ( ) ) ; const uint16_t * saved = TRI -> getCalleeSavedRegs ( & MF ) ; while ( * saved ) { CalleeSaved . set ( * saved ++ ) ; } for ( TargetRegisterClass :: iterator i = <STR_LIT> . begin ( ) , e = <STR_LIT> . end ( ) ; i != e ; ++ i ) { if ( MRI . isPhysRegUsed ( * i ) || * i == <STR_LIT> ) continue ; if ( Reserved [ * i ] || CalleeSaved [ * i ] ) continue ; SpillReg = * i ; break ; } if ( SpillReg ) { PMFI . setS0SpillReg ( SpillReg ) ; } } if ( TRI -> requiresRegisterScavenging ( MF ) ) { const TargetRegisterClass & RC = <STR_LIT> ; int fi = MFI . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) ,


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , <STR_LIT> . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening


<s> case 'm' : if ( GET_CODE ( x ) != CONST_INT ) { fatal_insn ( <STR_LIT> , x ) ; } fprintf ( stream , <STR_LIT> PRId64 , ( int64_t ) ( mmix_intval ( x ) - <NUM_LIT> ) ) ; return ; case 'p' : fprintf ( stream , <STR_LIT> , cfun -> machine -> highest_saved_stack_register + <NUM_LIT> ) ; return ; case 'r' : if ( ! REG_P ( x ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_destination_register = MMIX_OUTPUT_REGNO ( regno ) ; return ; case 'I' : if ( GET_CODE ( x ) != CONST_INT && ( GET_CODE ( x ) != CONST_DOUBLE || ( GET_MODE ( x ) != VOIDmode && GET_MODE ( x ) != DFmode && GET_MODE ( x ) != SFmode ) ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_register_setting ( stream , mmix_output_destination_register , mmix_intval ( x ) , <NUM_LIT> ) ; return ; case 'U' : if ( TARGET_ZERO_EXTEND ) putc ( 'U' , stream ) ; return ; case 'v' : mmix_output_shifted_value ( stream , ( int64_t ) mmix_intval ( x ) ) ; return ; case 'V' : mmix_output_shifted_value ( stream , ( int64_t ) ~ mmix_intval ( x ) ) ; return ; case 'W' : if ( GET_CODE ( x ) != CONST_INT ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( x ) & <NUM_LIT> ) ) ; return ; case <NUM_LIT> : break ; default : internal_error ( <STR_LIT> , code ) ; } switch ( GET_CODE ( modified_x


<s> const TargetRegisterClass * ThumbRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only

( ) ) return <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( MF , Kind ) ;


<s> MCELFStreamer :: emitInstruction ( Inst ,


<s> SDValue SizeNode = DAG . getConstant ( NumWords * <NUM_LIT> , <STR_LIT> ) ; MemOpChains . push_back ( DAG . getMemcpy ( Chain , dl , Dst , Arg , SizeNode , Flags . getByValAlign ( ) , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; int offset = VA . getLocMemOffset ( ) ; offset += Subtarget . hasSPBias ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue PtrOff = DAG . getIntPtrConstant ( offset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( ) ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { assert ( i < <NUM_LIT> ) ; Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; } if ( InFlag . getNode ( ) ) Ops


<s> if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , OffReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , OffReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , TII -> get ( NewOpc ) ) . addReg ( EvenReg , RegState :: Define ) . addReg ( OddReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( OffReg ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , TII -> get ( NewOpc ) ) . addReg ( EvenReg ) . addReg ( OddReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( OffReg ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; MRI -> setRegAllocationHint ( EvenReg , <STR_LIT> , OddReg ) ; MRI -> setRegAllocationHint ( OddReg , <STR_LIT> ,


<s> static std :: string getGraphName ( const ScheduleDAG


<s> for ( MBBVector :: const_iterator iterBlk = OrderedBlks . begin ( ) , iterBlkEnd = OrderedBlks . end ( ) ; iterBlk != iterBlkEnd ; ++ iterBlk , ++ i ) { dbgs ( ) << <STR_LIT> << ( * iterBlk ) -> getNumber ( ) ; dbgs ( ) << <STR_LIT> << getSCCNum ( * iterBlk ) << <STR_LIT> << ( * iterBlk ) -> size ( ) << <STR_LIT> ; if ( i != <NUM_LIT> && i % <NUM_LIT> == <NUM_LIT> ) { dbgs ( ) << <STR_LIT> ; } else { dbgs ( )


<s> if ( IS_NESTED ( arm_current_func_type ( ) ) && ( ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) || ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK && ! df_regs_ever_live_p ( LR_REGNUM ) ) ) && arm_r3_live_at_start_p ( ) && crtl -> args . pretend_args_size == <NUM_LIT> ) return <NUM_LIT> ; return


<s> if ( VPUEncoding ) { if ( RegNo < <NUM_LIT> || RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Register = RegisterTableVPU [ RegNo ] ; } else { if ( RegNo < <NUM_LIT> || RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Register = RegisterTableSPU [ RegNo ] ; } if ( Register == ~ <NUM_LIT>


<s> if ( AS != <STR_LIT> ) return <NUM_LIT> ; switch ( Size ) { case <NUM_LIT> : return RomData8bitsDirective ; case <NUM_LIT> : return


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef


<s> SDValue ChainLo1 = ChainLo , ChainLo2 = ChainLo , ChainHi1 = ChainHi , ChainHi2 = ChainHi ; if ( ChainLo . getOpcode ( ) == <STR_LIT> ) { ChainLo1 = ChainLo . getOperand ( <NUM_LIT> ) ; ChainLo2 = ChainLo . getOperand ( <NUM_LIT> ) ; } if ( ChainHi . getOpcode ( ) == <STR_LIT> ) { ChainHi1 = ChainHi . getOperand ( <NUM_LIT> ) ; ChainHi2 = ChainHi . getOperand ( <NUM_LIT> ) ; } SDValue Store1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainLo1 , SrcLo1 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue Store2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainLo2 , SrcLo2 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue Store3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainHi1 , SrcHi1 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue Store4 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainHi2 , SrcHi2 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue RetLo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , getChain ( Store1 ) , getChain ( Store2 ) ) ; SDValue RetHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , getChain ( Store3 ) , getChain ( Store4 ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetLo , RetHi ) ; } else if ( ValueType == <STR_LIT> ) { SDValue SrcLo , SrcHi ; GetExpandedParts ( Src , DAG , SrcLo , SrcHi ) ; SDValue ChainLo = Chain , ChainHi = Chain ; if ( Chain . getOpcode ( ) == <STR_LIT> ) { ChainLo = Chain . getOperand ( <NUM_LIT> ) ; ChainHi = Chain . getOperand ( <NUM_LIT> ) ; } SDValue Store1 = DAG . getStore ( ChainLo , dl , SrcLo , Ptr , NULL , <NUM_LIT> + StoreOffset ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , Ptr .


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> void setWAReg ( unsigned VReg , unsigned WAReg ) { assert ( WAReg != UnusedReg ) ; auto I = Register :: virtReg2Index ( VReg


<s> bool Is64Bit = STI . is64Bit ( ) ; unsigned CallOpc = Info . Callee . isReg ( ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpc ) . add ( Info . Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : Info . OrigArgs ) { if ( OrigArg . Flags . isByVal ( ) ) return false ; if ( OrigArg . Regs . size ( ) > <NUM_LIT> ) return false ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildUnmerge ( Regs , OrigArg . Regs [ <NUM_LIT> ] ) ; } ) ) return false ; } OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; bool IsFixed = Info . OrigArgs . empty ( ) ? true : Info . OrigArgs . back ( ) . IsFixed ; if ( STI . is64Bit ( ) && ! IsFixed && ! STI . isCallingConvWin64 ( Info . CallConv ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Handler . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit


<s> SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue CvtHi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue CvtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue LdExp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtHi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LdExp ,


<s> unsigned btihintop = ( MI -> getOperand ( OpNum ) . getImm ( ) ^ <NUM_LIT> ) >> <NUM_LIT> ; auto BTI = <STR_LIT> ( btihintop ) ; if ( BTI ) O << BTI -> Name ; else O << '#' << formatImm


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __bextri_u32 ( unsigned int __X , const unsigned int __I ) { return __builtin_ia32_bextri_u32 ( __X


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( Instruction * I ) { EVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) ,


<s> static bool incompatible_avl_p ( const vector_insn_info & info1 , const vector_insn_info


<s> RegHalf L , H ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! matchHalf ( RD . Reg , RC , <NUM_LIT> , H ) ) return false ; if ( L . Reg == H . Reg && L . Sub == H . Sub && ! H . Low && L . Low ) return false ; unsigned Opc = MI -> getOpcode ( ) ; unsigned COpc = getCombineOpcode ( H . Low , L . Low ) ; if ( COpc == Opc ) return false ; if ( ! validateReg ( H , COpc , <NUM_LIT> ) || ! validateReg ( L , COpc , <NUM_LIT> ) ) return false ; MachineBasicBlock & B = * MI -> getParent (


<s> if ( Space == <NUM_LIT> || Space > <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Count += Space ; } else { while ( parseOptionalToken ( AsmToken :: Comma ) ) { SMLoc Loc = getLoc ( ) ; StringRef NextKind ; unsigned Reg ; ParseRes = ParseVector ( Reg , NextKind , getLoc ( ) , true ) ; if ( ParseRes != MatchOperand_Success ) return ParseRes ; if ( Kind != NextKind ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } PrevReg = Reg ; ++ Count ; } } if ( parseToken ( AsmToken :: RCurly , <STR_LIT> ) ) return MatchOperand_ParseFail ; if ( Count > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned NumElements = <NUM_LIT> ; unsigned ElementWidth = <NUM_LIT> ; if ( ! Kind . empty ( ) ) { if ( const auto & VK = parseVectorKind ( Kind , VectorKind ) ) std :: tie ( NumElements , ElementWidth


<s> return static_cast < unsigned > ( ( MCInstD . TSFlags >> ImmEndBitStart ) &


<s> bool <ISA_LIT>DAGToDAGISel :: matchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) { return false


<s> if ( ! reserveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; Amount -= InternalAmt ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL ,


<s> if ( MIA -> evaluateMemoryOperandAddress ( * MI , nullptr , <NUM_LIT> , <NUM_LIT> ) ) return ; } const MCOperand & BaseReg = MI -> getOperand ( Op + <STR_LIT> ) ; unsigned ScaleVal = MI -> getOperand ( Op + <STR_LIT> ) . getImm ( ) ; const MCOperand & IndexReg = MI -> getOperand ( Op + <STR_LIT> ) ; const MCOperand & DispSpec = MI -> getOperand ( Op + <STR_LIT> ) ; printOptionalSegReg ( MI , Op + <STR_LIT> , O ) ; O << '[' ; bool NeedPlus = false ; if ( BaseReg . getReg


<s> fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , floor_log2 ( nds32_isr_vector_size ) , false ) ; fprintf ( asm_out_file , <STR_LIT> , reset_handler_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , <NUM_LIT> , true ) ; fprintf ( asm_out_file , <STR_LIT> , ( strlen ( nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) == <NUM_LIT> ) ? <STR_LIT> : nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) ,


<s> return buildEOR ( MBB , DL , MI ) . addReg ( Dst , RegState :: Define ) . addReg (

Dst ) . addReg ( Src ) . addImm ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( LHS == True ) return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; else return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> int c4x_label_conflict ( rtx insn , rtx jump , rtx db ) { while ( insn ) { if ( GET_CODE ( insn ) == CODE_LABEL ) { if ( CODE_LABEL_NUMBER ( jump ) == CODE_LABEL_NUMBER ( insn ) )


<s> if ( WaitEventMaskForInst [ VS_CNT ] & ( <NUM_LIT> << E ) ) return VS_CNT ; assert ( WaitEventMaskForInst [ EXP_CNT ] & ( <NUM_LIT> << E ) ) ; return


<s> return __aarch64_vset_lane_any ( * __src ,


<s> } else { uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> <ISA_LIT>SimplifyLibCalls ( const TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , Simplifier (


<s> inline unsigned getSlotOpCode ( const MCInstrDesc & MCInstD


<s> if ( ret ) { size = internalInstr . readerCursor - address ; return false ; } else { size = internalInstr . length ; translateInstruction ( instr , internalInstr ) ; return true


<s> const TargetRegisterClass * TRC = MRI -> getRegClass ( RegNo ) ; for ( MVT T : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( TRI -> isTypeLegalForClass ( * TRC , T ) ) return T ; DEBUG ( errs ( ) << <STR_LIT> << RegNo ) ; llvm_unreachable ( <STR_LIT>


<s> Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset == INT32_MIN ) { Offset = <NUM_LIT> ; isAdd = false ; } else if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd = false


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( F >> <STR_LIT> ) &


<s> if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ; unsigned Offset = TFL -> getFrameIndexOffset ( MF ,


<s> DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI .


<s> StringRef name = Tok . getString ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: parseVariantKind ( name ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . getKind ( ) != AsmToken :: LParen ) return false ; Parser . Lex ( ) ; const MCExpr * subExpr ; if ( Parser . parseParenExpression ( subExpr , EndLoc ) ) return false ; EVal = adjustPICRelocation ( VK , subExpr


<s> End = <NUM_LIT> - LSB ; return true ; } if ( isStringOfOnes ( Mask ^ allOnes ( BitSize ) , LSB , Length ) ) { assert ( LSB > <NUM_LIT> && <STR_LIT> ) ; assert ( LSB + Length < BitSize && <STR_LIT> ) ; Start = <NUM_LIT> - ( LSB - <NUM_LIT> ) ; End = <NUM_LIT> - ( LSB + Length ) ; return


<s> BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . addReg


<s> void BTFDebug :: emitBTFSection ( ) { if ( ! TypeEntries . size ( ) && StringTable . getSize ( ) == <NUM_LIT> ) return ; MCContext & Ctx = OS . getContext ( ) ; MCSectionELF * Sec = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; Sec -> setAlignment ( Align ( <NUM_LIT> ) ) ; OS . SwitchSection ( Sec ) ; emitCommonHeader ( ) ; OS . emitInt32 ( <STR_LIT> ) ; uint32_t TypeLen = <NUM_LIT> , StrLen ; for ( const auto & TypeEntry : TypeEntries ) TypeLen += TypeEntry -> getSize ( ) ; StrLen = StringTable . getSize ( ) ; OS . emitInt32 ( <NUM_LIT>


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg


<s> bool IsPop = isPopOpcode ( MI -> getOpcode ( ) ) ; bool IsPush = isPushOpcode ( MI -> getOpcode ( ) ) ; if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else


<s> SDValue Cst = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getBitcast ( VT ,


<s> case <STR_LIT> : LowerDextDins ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; if ( ! Size ) llvm_unreachable (


<s> void onDispExpr ( ) { switch ( State ) { default : State = IBES_ERROR ; break ; case IBES_START : State =


<s> if ( mode != BLKmode ) return GET_MODE_SIZE ( mode ) ; gcc_unreachable (


<s> for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N . getOpcode ( ) ) { case <STR_LIT> : return Mask ; case <STR_LIT>


<s> StackSlotInfo ( int f , int o , int r ) : FI ( f


<s> SDValue LHSlo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue LHShi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHSlo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue RHShi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHSlo , RHSlo ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHShi , RHShi , Cmp ) ; } else { Cmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> bool isMoveWideImm ( unsigned RegWidth , const <ISA_LIT>MCExpr :: VariantKind * PermittedModifiers , unsigned NumModifiers ) const { if ( ! isImmWithLSL ( ) ) return false ; if ( ImmWithLSL . ShiftAmount % <NUM_LIT> != <NUM_LIT> ) return false ; if ( ImmWithLSL . ShiftAmount >= RegWidth


<s> return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem .


<s> static DecodeStatus DecodeACC64DSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) return toc_section ; else return


<s> auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol

( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ;


<s> getAddrMode2OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg


<s> case Type :: DoubleTyID : return <STR_LIT> ; case Type :: PointerTyID : if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; else if ( useB4PTR ) return <STR_LIT> ; else return


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( CurDAG -> getTargetConstant ( RegClassIDs [ Regs . size ( ) - <NUM_LIT> ] , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < Regs . size ( ) ; ++ i ) { Ops . push_back ( Regs [ i ] ) ; Ops . push_back ( CurDAG -> getTargetConstant ( SubRegs [ i ] , <STR_LIT> ) ) ; } SDNode * N = CurDAG -> getMachineNode ( TargetOpcode

:: REG_SEQUENCE , DL , <STR_LIT> , Ops ) ;


<s> if ( NumOperands != <NUM_LIT> || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) llvm_unreachable ( <STR_LIT> ) ; auto Mapping = getValueMapping ( getPartialMappingIdx ( Ty , isFP ) , <NUM_LIT> ) ; return getInstructionMapping ( DefaultMappingID , <NUM_LIT>


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo (


<s> for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { DiagnosticInfoUnsupported Err ( DL , * MF . getFunction ( ) , <STR_LIT> , SDValue (


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < ReachingDefAnalysis > (


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) { if ( HasConditionalBranch ( MI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; } return MO . getImm


<s> struct argdata { int64_t argv_data [ kernel_argc ] ; char strings [ args_size ] ; } * args = device_malloc ( sizeof ( struct argdata ) , kernargs_region ) ; size_t heap_size = <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ; struct heap * heap = device_malloc ( heap_size , heap_region ) ; XHSA ( hsa_fns . hsa_memory_assign_agent_fn ( heap , device , HSA_ACCESS_PERMISSION_RW ) , <STR_LIT> ) ; void * stack = device_malloc ( stack_size , heap_region ) ; kernargs -> args . argc = kernel_argc ; kernargs -> args . argv = ( int64_t ) args -> argv_data ; kernargs -> abi . out_ptr = ( int64_t ) & kernargs -> output_data ; kernargs -> output_data . return_value = <NUM_LIT> ; kernargs -> output_data . next_output = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( kernargs -> output_data . queue ) / sizeof ( kernargs -> output_data . queue [ <NUM_LIT> ] ) ) ; i ++ ) kernargs -> output_data . queue [ i ] . written = <NUM_LIT> ; kernargs -> output_data . consumed = <NUM_LIT> ; int offset = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < kernel_argc ; i ++ ) { size_t arg_len = strlen ( kernel_argv [ i ] ) + <NUM_LIT> ; args -> argv_data [ i ] = ( int64_t ) & args -> strings [ offset ] ; memcpy ( & args -> strings [ offset ] , kernel_argv [ i ] , arg_len + <NUM_LIT> ) ; offset += arg_len ; } kernargs -> abi . heap_ptr = ( int64_t ) heap ; hsa_fns . hsa_memory_copy_fn ( & heap -> size , & heap_size , sizeof ( heap_size ) ) ; kernargs -> abi . arena_ptr = <NUM_LIT> ; kernargs -> abi . stack_ptr = ( int64_t ) stack ; kernargs -> abi . stack_size_per_thread = stack_size ; run ( init_array_kernel , kernargs ) ; run ( main_kernel , kernargs ) ; unsigned int return_value = ( unsigned int ) kernargs -> output_data . return_value ; run ( fini_array_kernel , kernargs ) ; unsigned int upper = ( return_value & ~ <NUM_LIT> ) >> <NUM_LIT> ; if ( upper == <NUM_LIT> ) { printf ( <STR_LIT> ) ; return_value = <NUM_LIT> ; } else if ( upper == <NUM_LIT> ) ; else if ( upper == <NUM_LIT> ) ; else printf ( <STR_LIT> <STR_LIT> , return_value


<s> DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation (


<s> while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister = <STR_LIT> ; bool HasFP = hasFP ( MF ) ; for ( auto & I : MFI . getCalleeSavedInfo ( ) ) { Register Reg = I . getReg ( ) ; if ( is<ISA_LIT>LowRegister ( Reg ) && ! ( HasFP && Reg == FramePtr ) ) { ScratchRegister = Reg ; break ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } } if ( needPopSpecialFixUp ( MF )


<s> EVT VT = VA . getValVT ( ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VT , InFlag ) . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } return


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return EmitShiftInstr ( MI , BB ) ; const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = BB ; ++ I ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB


<s> auto & LoadInst = * It ; auto LoadInsertIt = std :: next ( It ) ; unsigned CycleDist = <NUM_LIT> ; while ( ++ It != MBB . end ( ) && isFullNopInstr ( * It ) ) ++ CycleDist ; if ( It == MBB . end ( ) ) break ; if ( ! hasST_L_V ( * It ) ) { ++ It ; continue ; } auto & StoreInst = * It ; unsigned CommonReg = <NUM_LIT> ; if ( ! hasWriteToReadDep ( LoadInst , StoreInst , CommonReg , TRI ) ) { ++ It ; continue ; } auto StoreInsertIt = ++ It ; if ( It == MBB . end ( ) ) break ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > LoadIters , StoreIters ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CycleDist ) ; unsigned SequenceCount = <NUM_LIT> , PipeCount = <NUM_LIT> ; while ( SequenceCount ++ < CycleDist ) { if ( It == MBB . end ( ) ) break ; if ( ! hasLD_L_V ( * It ) ) { ++ It ; break ; } auto LoadIt = It ; unsigned CycleCount = <NUM_LIT> ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > NOPIters ; while ( ++ It != MBB . end ( ) && isFullNopInstr ( * It ) ) { NOPIters . push_back ( It ) ; ++ CycleCount ; } if ( CycleCount != CycleDist || It == MBB . end ( ) ) break ; if ( ! hasST_L_V ( * It ) ) { ++ It ; break ; } unsigned Reg = <NUM_LIT> ; if ( ! hasWriteToReadDep ( LoadInst , StoreInst , Reg , TRI ) || Reg != CommonReg ) { ++ It ; break ; } for ( auto NOPIt : NOPIters ) MBB . erase ( NOPIt ) ; LoadIters . push_back ( LoadIt ) ; StoreIters . push_back ( It ) ; ++ It ; ++ PipeCount ; } if ( ( LoadIters . size ( ) > <NUM_LIT> ) && ( StoreIters . size ( ) > <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( printMI ( & LoadInst ) ; { for ( auto & MIter : LoadIters ) printMI


<s> unsigned ScalarSize = N -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ; SDValue Op = peekThroughBitcasts ( SDValue ( N , <NUM_LIT> ) ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; if ( VT . getScalarSizeInBits ( ) != ScalarSize ) return SDValue ( ) ; if ( auto SVOp = dyn_cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ) { if ( ! SVOp -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; if ( SDValue NegOp0 = isFNEG ( DAG , SVOp -> getOperand ( <NUM_LIT> ) . getNode ( ) , Depth + <NUM_LIT> ) ) if ( NegOp0 . getValueType ( ) == VT ) return DAG . getVectorShuffle ( VT , SDLoc ( SVOp ) , NegOp0 , DAG . getUNDEF ( VT ) , SVOp -> getMask ( ) ) ; return SDValue ( ) ; } unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { SDValue InsVector = Op . getOperand ( <NUM_LIT> ) ; SDValue InsVal = Op . getOperand ( <NUM_LIT> ) ; if ( ! InsVector . isUndef ( ) ) return SDValue ( ) ; if ( SDValue NegInsVal = isFNEG ( DAG , InsVal . getNode ( ) , Depth + <NUM_LIT> ) ) if ( NegInsVal . getValueType ( ) == VT . getVectorElementType ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , InsVector , NegInsVal , Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ; } if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> >


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForCall ( CallerCC , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return CCInfo . getNextStackOffset ( )

<= FuncInfo -> getBytesInStackArgArea ( ) ;


<s> unsigned e = static_cast < unsigned > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> ( e


<s> return isImm ( - ( <NUM_LIT> << <NUM_LIT> ) ,


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef


<s> void <ISA_LIT>InstPrinter :: printS5ImmOperand ( const MCInst * MI


<s> SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue


<s> SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , OrigArg . Flags ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags } ) ; } SmallVector < uint64_t , <NUM_LIT> > BitOffsets


<s> ldgp = alpha_function_needs_gp ? <NUM_LIT> : <NUM_LIT> ; while ( i ) { next = ( * next_group ) ( i , & in_use , & len ) ; if ( LABEL_P ( i ) ) { unsigned int new_align = <NUM_LIT> << label_to_alignment ( i ) ; if ( new_align >= align ) { align = new_align < max_align ? new_align : max_align ; ofs = <NUM_LIT> ; } else if ( ofs & ( new_align - <NUM_LIT> ) ) ofs = ( ofs | ( new_align - <NUM_LIT> ) ) + <NUM_LIT> ; gcc_assert ( ! len ) ; } else if ( in_use == <NUM_LIT> ) { if ( len < <NUM_LIT> ) { ofs = <NUM_LIT> ; align = <NUM_LIT> ; len = <NUM_LIT> ; } } else if ( ( int ) align < len ) { unsigned int new_log_align = len > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; rtx_insn * prev , *


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction &


<s> if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const AsmToken & Reg = Parser . getTok ( ) ; if ( Reg . is ( AsmToken :: Identifier ) ) { AtRegNo = matchCPURegisterName ( Reg . getIdentifier ( ) ) ; } else if ( Reg . is ( AsmToken :: Integer ) ) { AtRegNo = Reg . getIntVal ( ) ; } else { reportParseError ( <STR_LIT> ) ; return false ; } if ( AtRegNo < <NUM_LIT> || AtRegNo > <NUM_LIT> ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! AssemblerOptions . back ( ) -> setATReg ( AtRegNo ) ) { reportParseError ( <STR_LIT>


<s> else if ( TARGET_COFF || TARGET_PECOFF ) objfmt = <STR_LIT> ; if ( objfmt == NULL


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger (


<s> void <ISA_LIT>InstPrinter :: printExpCompr ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo &


<s> return ( __m128d ) __builtin_ia32_vfmaddsd3_round ( ( __v2df ) __W , ( __v2df )


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>BETarget , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( TheThumbLETarget , createThumbDisassembler


<s> ++ ( * bbb ) ; CI -> eraseFromParent ( ) ; return true ; } StringRef calleeName = CI -> getOperand ( CI -> getNumOperands ( ) - <NUM_LIT> ) -> getName ( ) ; if ( calleeName . startswith ( <STR_LIT> ) ) { if ( optLevel == CodeGenOpt :: None ) { isConstVec . push_back ( CI ) ; return false ; } else { Constant * CV = dyn_cast < Constant > ( CI -> getOperand ( <NUM_LIT> ) ) ; Type * aType = Type :: getInt32Ty ( * mCTX ) ; Value * Val = ( CV != NULL ) ? ConstantInt :: get ( aType , <NUM_LIT> ) : ConstantInt :: get ( aType , <NUM_LIT> ) ; CI -> replaceAllUsesWith ( Val ) ; ++ ( * bbb ) ; CI -> eraseFromParent ( ) ; return true ; } } if ( calleeName . equals ( <STR_LIT> ) ) { ConstantInt * CV = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ; Type * aType = Type :: getInt32Ty ( * mCTX ) ; Value * Val = CV ; if ( Val ) { Val = ConstantInt :: get ( aType , mSTM -> device ( ) -> getDeviceFlag ( ) & CV -> getZExtValue ( ) ) ; } else { Val = ConstantInt :: get ( aType , <NUM_LIT> ) ; } CI -> replaceAllUsesWith ( Val ) ; ++ ( * bbb ) ; CI -> eraseFromParent ( ) ; return true ; } Function * F = dyn_cast < Function > ( CI -> getOperand ( CI -> getNumOperands ( ) - <NUM_LIT> ) ) ; if ( ! F ) { return false ; } if ( F -> getName ( ) . startswith ( <STR_LIT> ) && ! CI -> getNumUses ( ) && F -> getName ( ) . find ( <STR_LIT> ) == StringRef :: npos ) { std :: string buffer ( F -> getName ( ) . str ( ) + <STR_LIT> ) ; F = dyn_cast < Function > ( F -> getParent ( ) -> getOrInsertFunction ( buffer , F -> getFunctionType ( ) ) ) ; atomicFuncs . push_back ( std :: make_pair ( CI , F ) ) ; } if ( ! mSTM -> device ( ) -> isSupported ( <STR_LIT> ) && ! mSTM -> device ( ) -> isSupported ( <STR_LIT> ) ) { return false ; } if ( ! mConvertAtomics ) { return false ; } StringRef name = F -> getName


<s> static bool isSortedByValueNo ( ArrayRef < CCValAssign > ArgLocs ) { return std :: is_sorted ( ArgLocs . begin ( ) , ArgLocs . end ( ) , [ ] ( const CCValAssign


<s> break ; case <NUM_LIT> : mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE


<s> if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == STACK_POINTER_REGNUM ) ) { return ( cfun -> machine -> frame_info . total_size - ( cfun -> machine -> frame_info . pretend_size + cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ) ; } gcc_unreachable ( )


<s> char size_char ; len = get_attr_length ( insn ) ; far = len == <NUM_LIT> ; emit_nop = len == <NUM_LIT> ; if ( far ) code = reverse_condition ( code ) ; size_char = ( ( mode == SImode ) ? 'w' : 'x' ) ; switch ( code ) { case NE : cond_str = <STR_LIT> ; break ; case EQ : cond_str = <STR_LIT> ; break ; case GE : cond_str = <STR_LIT> ; break ; case GT : cond_str = <STR_LIT> ; break ; case LE : cond_str = <STR_LIT>


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ; MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI2 -> getOperand ( <NUM_LIT> )


<s> } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { unsigned Opc = ( CalleeAmt < <NUM_LIT> ) ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr )


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , DebugLoc dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack

( LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT>


<s> case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT>


<s> for ( BasicBlock * BB : L -> blocks ( ) ) for ( Instruction & I : * BB ) if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) if ( const Function * F = cast < CallBase

> ( I ) . getCalledFunction ( ) ) if ( isLoweredToCall ( F ) ) return ;


<s> const SDLoc & dl ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Address = N -> getOperand ( <NUM_LIT> ) ; SDValue Predicate = N -> getOperand ( <NUM_LIT> ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Modifier = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode ; unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> bool pru_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { bool in_memory = ( ! pru_arg_in_reg_bysize ( int_size_in_bytes ( type ) ) || int_size_in_bytes ( type ) == - <NUM_LIT> ) ; return


<s> if ( VT . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . hasOneUse ( ) && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( DAG . ComputeNumSignBits ( Cond ) != CondVT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( TValIsAllOnes && FValIsAllZeros ) return DAG . getBitcast ( VT


<s> return Kind == Memory && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem .


<s> for ( auto I = BB -> begin ( ) , I_END = BB -> end ( ) ; I != I_END ; I ++ ) { if ( isa < SwitchInst > ( I ) ) { const SwitchInst * SwitchInstPtr = dyn_cast < SwitchInst > ( I ) ; SwitchLeafData * newSwitch = new SwitchLeafData ( SwitchInstPtr ) ; newSwitch -> searchAndInsert


<s> while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; MVT NewVT = V . getSimpleValueType ( ) ; if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> && V . getOpcode ( ) == <STR_LIT> ) ) return DAG

. getNode ( <STR_LIT> , SDLoc ( V ) , EltVT , V . getOperand ( Idx ) ) ;


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return ( IsS11_3_Offset ( Offset . getNode ( ) ) ) ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> unsigned <ISA_LIT>FastISel :: getRegForSignedValue ( const Value * V ) { <STR_LIT> From = getSimpleType ( V -> getType ( ) ) ; <STR_LIT> To = getLegalType ( From ) ; unsigned VReg = getRegForValue ( V ) ; if ( VReg == <NUM_LIT> ) return <NUM_LIT> ; return signExtend ( VReg , V , From


<s> const SCEV * ptr = AddRec -> getStepRecurrence ( * p_SEL ) ; if ( const SCEVSignExtendExpr * ptr2 = dyn_cast < SCEVSignExtendExpr > ( ptr ) ) ptr = ptr2 -> getOperand


<s> bool <ISA_LIT>TTIImpl :: shouldMaximizeVectorBandwidth ( bool OptSize ) const { return false


<s> ST = & MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST -> hasRegisterBanking ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TRI = ST -> getRegisterInfo ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; VRM = & getAnalysis < VirtRegMap > ( ) ; LRM = & getAnalysis < LiveRegMatrix > ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Occupancy = MFI -> getOccupancy ( ) ; MaxNumVGPRs = ST -> getMaxNumVGPRs ( MF ) ; MaxNumSGPRs = ST -> getMaxNumSGPRs ( MF ) ; MaxNumVGPRs = std :: min ( ST -> getMaxNumVGPRs


<s> case <ISA_LIT>LibFunc :: EI_ATAN : return TableRef ( tbl_atan ) ; case <ISA_LIT>LibFunc :: EI_ATANH : return TableRef ( tbl_atanh ) ; case <ISA_LIT>LibFunc :: EI_ATANPI : return TableRef ( tbl_atanpi ) ; case <ISA_LIT>LibFunc :: EI_CBRT : return TableRef ( tbl_cbrt ) ; case <ISA_LIT>LibFunc :: EI_NCOS : case <ISA_LIT>LibFunc :: EI_COS : return TableRef ( tbl_cos ) ; case <ISA_LIT>LibFunc :: EI_COSH : return TableRef ( tbl_cosh ) ; case <ISA_LIT>LibFunc :: EI_COSPI : return TableRef ( tbl_cospi ) ; case <ISA_LIT>LibFunc :: EI_ERFC : return TableRef ( tbl_erfc ) ; case <ISA_LIT>LibFunc :: EI_ERF : return TableRef ( tbl_erf ) ; case <ISA_LIT>LibFunc :: EI_EXP : return TableRef ( tbl_exp ) ; case <ISA_LIT>LibFunc :: EI_NEXP2 : case <ISA_LIT>LibFunc :: EI_EXP2 : return TableRef (


<s> int nunits = GET_MODE_NUNITS ( mode ) ; int nsets = nunits / <NUM_LIT> ; int set = <NUM_LIT> ; int i , j ; for ( j = <NUM_LIT> ; j < nsets ; j ++ , set = <NUM_LIT> * j ) for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( INTVAL ( XVECEXP ( op , <NUM_LIT> , i ) ) != ( INTVAL ( XVECEXP ( op , <NUM_LIT> , set + i ) ) - set ) ) || ! IN_RANGE

( INTVAL ( XVECEXP ( op , <NUM_LIT> , set + i ) ) , <NUM_LIT> , set + <NUM_LIT> ) ) return false ;


<s> TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) || ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst


<s> else if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( static_cast < uint32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < uint32_t > :: max ( ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( static_cast < int32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < int32_t > :: max ( ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( static_cast < int32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < int32_t


<s> if ( XnackSupported ) { XnackSetting = * XnackRequested ? TargetIDSetting :: On : TargetIDSetting :: Off ; } else { if ( * XnackRequested ) { errs ( ) << <STR_LIT> <STR_LIT> ; } else { errs ( ) << <STR_LIT> <STR_LIT> ; } } } if ( SramEccRequested ) { if ( SramEccSupported ) { SramEccSetting = * SramEccRequested ? TargetIDSetting :: On : TargetIDSetting :: Off ; } else { if ( *


<s> return ( __m512i ) __builtin_ia32_prorq512_mask ( ( __v8di ) __A , __B , (

__v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> LaneBitmask LA = PA . second & RA . Mask ; LaneBitmask LB = PB . second & RB . Mask ; if ( LA . any ( ) && LB . any ( ) ) { unsigned Root = * MCRegUnitRootIterator ( PA . first , & TRI ) ; uint32_t SubA = TRI . getSubRegIndex ( RA . Reg , Root ) ; uint32_t SubB = TRI . getSubRegIndex ( RB . Reg , Root ) ; const TargetRegisterClass * RC = RegInfos [ Root ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ; LaneBitmask MaskA = TRI . reverseComposeSubRegIndexLaneMask ( SubA , LA ) ; LaneBitmask MaskB = TRI . reverseComposeSubRegIndexLaneMask ( SubB , LB ) ; if ( ( MaskA & MaskB & RCMask ) . any ( ) ) return true ; } ++ UMA ; ++ UMB ; continue ; } if ( PA . first < PB . first )


<s> static bool isNVVMAtomic ( const IntrinsicInst * II ) { switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case


<s> assert ( Subtarget -> supportsTailCall ( ) ) ; if ( isVarArg && ! Outs . empty ( ) ) return false ; if ( CallerF -> hasFnAttribute ( <STR_LIT> ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForNode ( CalleeCC , true , isVarArg ) , CCAssignFnForNode ( CallerCC , true , isVarArg ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo (


<s> if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) || ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ) Ret +=


<s> assert ( & ( * MF . begin ( ) ) == & PrologueMBB && <STR_LIT> ) ; const unsigned HipeLeafWords = <NUM_LIT> ; const unsigned CCRegisteredArgs = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; const unsigned Guaranteed = HipeLeafWords * SlotSize ; unsigned CallerStkArity = MF . getFunction ( ) -> arg_size ( ) > CCRegisteredArgs ? MF . getFunction ( ) -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; unsigned MaxStack = MFI -> getStackSize ( ) + CallerStkArity * SlotSize + SlotSize ; assert ( STI . isTargetLinux ( ) && <STR_LIT> ) ; if ( MFI -> hasCalls ( ) ) { unsigned MoreStackForCalls = <NUM_LIT> ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , MBBE = MF . end ( ) ; MBBI != MBBE ; ++ MBBI ) for ( MachineBasicBlock :: iterator MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { if ( ! MI -> isCall ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( const auto & LI : PrologueMBB . liveins ( ) ) { stackCheckMBB -> addLiveIn ( LI ) ; incStackMBB -> addLiveIn ( LI ) ; } MF . push_front ( incStackMBB ) ; MF . push_front ( stackCheckMBB ) ; unsigned ScratchReg , SPReg , PReg , SPLimitOffset ; unsigned LEAop , CMPop , CALLop ; if ( Is64Bit ) { SPReg = <STR_LIT> ; PReg =


<s> if ( ! host_integerp ( arg , <NUM_LIT> ) || ( elt = tree_low_cst ( arg , <NUM_LIT> ) , elt >


<s> unsigned <ISA_LIT>TTIImpl :: getAtomicMemIntrinsicMaxElementSize ( )


<s> O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm (


<s> assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; OldPacket . resize ( SchedModel -> getIssueWidth ( )


<s> unsigned Size = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Size = <NUM_LIT> ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<=


<s> EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; SDLoc dl ( Op ) ; unsigned Opc ; switch ( Op .


<s> int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; unsigned InstPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst2 = MCCFIInstruction :: createOffset ( nullptr , MRI . getDwarfRegNum ( InstPtr , true ) , stackGrowth ) ; MAI -> addInitialFrameState


<s> return ( __m128i ) __builtin_ia32_maskloadq ( ( const __v2di


<s> for ( unsigned Reg : * RC ) if ( ! MRI . isPhysRegUsed ( Reg


<s> if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; return SDValue (


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV (


<s> insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; addPass ( create<ISA_LIT>TLSDynamicCallPass


<s> } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) && canRealignStack ( MF ) ) ) { if ( isFrameOffsetLegal ( MI , FPOffset ) ) return