<s> if ( Subtarget . hasAVX512 ( ) && MaskVT . is512BitVector ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask .


<s> const LegalizerInfo * <ISA_LIT>Subtarget ::


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode (


<s> return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( CPUType , CPUSubtype )


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VTList , Ops ) ; if ( CondCode2 != <STR_LIT> ) { <ISA_LIT>cc = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Res , Dest , <ISA_LIT>cc , CCR , Res . getValue ( <NUM_LIT> ) } ; Res = DAG . getNode ( <STR_LIT> , dl


<s> return ( ( qword ) ( vec_add ( vec_mule ( ( vec_short8 ) ( a ) ,


<s> if ( SrcReg != <STR_LIT> ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( SrcReg ) * <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState (

MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) , FrameIndex ) ;


<s> return regClassCanUseInlineConstant ( RC -> getID (


<s> unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( CFAOffset ) { CFAOffset = isDestroy ? - CFAOffset


<s> OS << <STR_LIT> << Sym -> getName ( ) << <STR_LIT> ; OS << <STR_LIT> ( Sym -> getSignature ( ) ) ; OS << <STR_LIT>


<s> tree type = build_pointer_type ( fntype ) ; tree function_result_decl = build_decl ( BUILTINS_LOCATION , PARM_DECL , NULL_TREE , type ) ; DECL_ARG_TYPE ( function_result_decl ) = type ; TREE_CHAIN ( function_result_decl ) = fnargs ; fnargs = function_result_decl ; } INIT_CUMULATIVE_ARGS ( args_so_far_v , fntype , NULL_RTX , <NUM_LIT> , <NUM_LIT> ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; regno = GP_ARG_FIRST ; for ( cur_arg = fnargs ; cur_arg != <NUM_LIT> ; cur_arg = next_arg ) { tree passed_type = DECL_ARG_TYPE ( cur_arg ) ; machine_mode passed_mode = TYPE_MODE ( passed_type ) ; rtx entry_parm ; if ( TREE_ADDRESSABLE ( passed_type ) ) { passed_type = build_pointer_type ( passed_type ) ; passed_mode = Pmode ; } entry_parm = targetm . calls . function_arg ( args_so_far , passed_mode , passed_type , true ) ; if ( entry_parm ) { int words ; if ( GET_MODE ( entry_parm ) == BLKmode ) words = ( int_size_in_bytes ( passed_type ) + <NUM_LIT> ) / <NUM_LIT> ; else words = ( GET_MODE_SIZE ( GET_MODE ( entry_parm ) ) + <NUM_LIT> ) / <NUM_LIT> ; regno = REGNO ( entry_parm ) + words - <NUM_LIT> ; } else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } targetm . calls . function_arg_advance ( args_so_far , passed_mode , passed_type , true ) ; next_arg = TREE_CHAIN ( cur_arg ) ; if ( next_arg == <NUM_LIT>


<s> } MachineInstr * Instr = & ( * I ++ ) ; for ( auto MO : Instr -> uses ( ) ) { if ( ! MO . isReg ( ) || MO . getReg ( ) != DefRegNo ) continue ; if ( Instr -> getOpcode ( ) == FirstInstr -> getOpcode ( ) ) { SubregCount -- ; unsigned UseOpIdx = Instr -> findRegisterUseOperandIdx ( MO . getReg ( )


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex , unsigned & MemBytes ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) , MemBytes ) ) if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { return true


<s> void <ISA_LIT>ELFStreamer :: emitHandlerData ( ) { FlushUnwindOpcodes ( false )


<s> std :: unique_ptr < MCObjectTargetWriter

> create<ISA_LIT>WinCOFFObjectWriter ( ) {


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t TSFlags = Desc


<s> DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Base ; int64_t Offset ; if ( ! LD -> isVolatile ( ) && IsWordAlignedBasePlusConstantOffset ( BasePtr , Base , Offset ) ) { if ( Offset % <NUM_LIT> == <NUM_LIT> ) { return DAG . getLoad ( getPointerTy ( ) , DL , Chain , BasePtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue LowOffset = DAG . getConstant ( Offset & ~ <NUM_LIT> , <STR_LIT> ) ; SDValue HighOffset = DAG . getConstant ( ( Offset & ~ <NUM_LIT> ) + <NUM_LIT> , <STR_LIT> ) ; SDValue LowShift = DAG . getConstant ( ( Offset & <NUM_LIT> ) * <NUM_LIT> , <STR_LIT> ) ; SDValue HighShift = DAG . getConstant ( <NUM_LIT> - ( Offset & <NUM_LIT> ) * <NUM_LIT> , <STR_LIT> ) ; SDValue LowAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , LowOffset ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , HighOffset ) ; SDValue Low = DAG . getLoad ( getPointerTy ( ) , DL , Chain , LowAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue High = DAG . getLoad ( getPointerTy ( ) , DL , Chain , HighAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue LowShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , LowShift ) ; SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , HighShift


<s> FuseTest , FuseCmp , FuseInc } FuseKind ; switch ( Second -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseInc ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseCmp ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FuseKind = FuseTest ; break ; } switch ( First -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) { unsigned idx = Count - i - <NUM_LIT> ; unsigned Reg1 = CSI [ idx ] . getReg ( ) ; unsigned Reg2 = CSI [ idx + <NUM_LIT> ] . getReg ( ) ; assert ( CSI [ idx ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) && <STR_LIT> ) ; unsigned StrOpc ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { SDLoc dl ( N ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; AM . dump (


<s> rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [ <NUM_LIT>

] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ;


<s> if ( ( get ( Opcode ) . TSFlags & <STR_LIT> ) != <NUM_LIT> && ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ) Gen = <STR_LIT> ; if ( get ( Opcode ) . TSFlags & <STR_LIT> ) Gen = ST . getGeneration ( ) == <ISA_LIT>Subtarget :: GFX9 ? <STR_LIT> : <STR_LIT> ; int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ; return


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable (


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseSymbolicUnifiedFormat ( StringRef FormatStr , SMLoc Loc , int64_t & Format ) { using namespace llvm


<s> assert ( ( RegTy != VecListIdx_ZReg || NumRegs <= <NUM_LIT> ) && <STR_LIT> ) ; unsigned FirstReg = FirstRegs [ ( unsigned ) RegTy ] [ NumRegs ] ; Inst . addOperand ( MCOperand :: createReg ( FirstReg + getVectorListStart ( ) - FirstRegs [ (


<s> if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true


<s> } ; const DecodeTable Tables [ ] = { { DecoderTableVFP32 , false } , { DecoderTableVFPV832 , false } , { DecoderTableNEONData32 , true } , { DecoderTableNEONLoadStore32 , true } , { DecoderTableNEONDup32 , true } , { DecoderTablev8NEON32 , false } , { DecoderTablev8Crypto32 , false } , } ; for ( auto Table : Tables ) { Result = decodeInstruction ( Table . P , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( Table . DecodePred && ! DecodePredicateOperand ( MI , <NUM_LIT> , Address , this ) ) return MCDisassembler :: Fail ; return Result


<s> if ( MaxElts [ i ] - MinElts [ i ] >= NumElts ) { return SDValue ( ) ; } if ( MinElts [ i ] >= NumElts ) { VEXTOffsets [ i ] = NumElts ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; } else if ( MaxElts [ i ] < NumElts ) { VEXTOffsets [ i ] = <NUM_LIT> ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { VEXTOffsets [ i ] = MinElts [ i ] ; SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , VT , SourceVecs [ i ] , DAG . getIntPtrConstant ( NumElts ) ) ; ShuffleSrcs [ i ] = DAG . getNode ( <STR_LIT> , dl , VT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( VEXTOffsets [ i ] , <STR_LIT> ) ) ; } } SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Entry = Op . getOperand ( i ) ; if ( Entry . getOpcode ( ) == <STR_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } SDValue ExtractVec = Entry . getOperand ( <NUM_LIT> ) ; int ExtractElt = cast < ConstantSDNode > ( Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ExtractVec == SourceVecs [ <NUM_LIT> ] ) { Mask . push_back ( ExtractElt - VEXTOffsets [ <NUM_LIT> ] ) ; } else { Mask . push_back ( ExtractElt + NumElts -


<s> for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText ( S ) ; DwarfFiles . clear (


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects (


<s> OutStreamer -> AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer -> PushSection ( ) ; MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer -> SwitchSection ( M , nullptr ) ; OutStreamer -> emitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbolELF * Stub = cast < MCSymbolELF > ( OutContext . getOrCreateSymbol ( StringRef ( x ) ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . getOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer -> emitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer -> emitLabel ( Stub ) ; assert ( ! isPositionIndependent ( ) && <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( * STI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( * STI , Signature -> ParamSig , LE , true ) ; EmitJal ( * STI , MSymbol ) ; EmitSwapFPIntRetval ( * STI , Signature


<s> if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; unsigned i = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { const AttributeList & Attrs = F -> getAttributes ( ) ; if ( Attrs . hasParamAttribute ( i , Attribute :: ByVal ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftSelf ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftError ) || Attrs . hasParamAttribute ( i , Attribute :: InAlloca ) || Attrs . hasParamAttribute ( i , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; if ( ! Subtarget -> hasSIMD128 ( ) && ArgTy -> isVectorTy ( ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( ArgTy ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - ( STI -> isTargetDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ; return SDValue (


<s> unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1

, RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> MachineFunctionPass ( ID ) , TRI ( nullptr


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo


<s> return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ,


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , ExplicitKernArgSize ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , Mode ( MF . getFunction ( ) , MF . getSubtarget < GCNSubtarget > ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) , MemoryBound ( false ) , WaveLimiter ( false ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get (


<s> PHINode * Broken = PHINode :: Create ( Int64 , <NUM_LIT> , <STR_LIT> , & Target -> front ( ) ) ; SmallVector < WeakTrackingVH , <NUM_LIT> > LoopPhiConditions ; Value * Cond = Term -> getCondition ( ) ; Term -> setCondition ( BoolTrue ) ; Value * Arg = handleLoopCondition ( Cond , Broken , L , Term , LoopPhiConditions ) ; for ( BasicBlock * Pred : predecessors ( Target ) ) Broken -> addIncoming ( Pred == BB ? Arg


<s> if ( Generated . tryCombineAll ( Observer , MI , B , Helper ) ) return true ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode ::


<s> <ISA_LIT>TargetStreamer & <ISA_LIT>AsmPrinter :: getTargetStreamer (


<s> return ( ( qword ) ( vec_ld ( si_to_uint ( a ) & ~ <NUM_LIT> , ( vector unsigned char


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_DISPATCHSETUP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG ,


<s> union { _Float16 _Complex a ; float b ; } u = { . a = __A } ; return ( __m128h ) _mm_set1_ps


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<s> if ( ! FrameSize || FrameSize > Subtarget . getRedZoneSize ( ) ) return false ; if ( hasFP ( MF ) || RegInfo -> hasBasePointer ( MF ) ) return false ; if ( FI -> hasFastCall ( ) || FI -> usesPICBase ( )


<s> if ( isMClass ( ) && hasMinSize ( ) ) return false ; return useMachineScheduler (


<s> unsigned getMinNumVGPRs ( unsigned WavesPerEU )


<s> AllowHashAtStartOfIdentifier = ( AssemblerDialect == AD_HLASM ) ; DotIsPC = ( AssemblerDialect == AD_ATT ) ; StarIsPC = ( AssemblerDialect == AD_HLASM ) ; EmitGNUAsmStartIndentationMarker = ( AssemblerDialect == AD_ATT ) ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation =


<s> bool isImm ( ) const override { return Kind ==


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty ,


<s> } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DstVT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( FP ) ) ; updateValueMap ( I , ResultReg ) ; return


<s> DFAPacketizer * <ISA_LIT>InstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI


<s> uint64_t Target = Address + Imm ; if ( ! TT . is<ISA_LIT>64 ( ) ) Target &= <NUM_LIT> ; O << formatHex ( Target ) ; } else { if ( ! TT . isOSAIX ( ) ) O << <STR_LIT> ; else O


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI . isCall ( MachineInstr :: IgnoreBundle ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ! validateIntClampSupported ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateOpSel ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGD16 ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGDim ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGDataSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAddrSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAtomicDMask ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGGatherDMask ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateFlatOffset ( Inst , Operands ) ) { return false ; } return


<s> static DecodeStatus DecodeFCCRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return


<s> for ( ; mask ; mask >>= <NUM_LIT> , op ++ , hreg ++ ) if ( ( mask & <NUM_LIT> ) && * hreg ) emit_move_insn ( * hreg , * op ) ; return true


<s> if ( SupportedVectorShiftWithBaseAmnt ( ExtVT , Subtarget , Opcode ) ) { unsigned LogicalOp = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; unsigned Logical<ISA_LIT>Op = getTargetVShiftUniformOpcode ( LogicalOp , false ) ; BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; SDValue BitMask = DAG . getConstant ( - <NUM_LIT> , dl , ExtVT ) ; BitMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , BaseShAmt , Subtarget , DAG ) ; if ( Opcode != <STR_LIT> ) BitMask = getTargetVShiftByConstNode ( Logical<ISA_LIT>Op , dl , ExtVT , BitMask , <NUM_LIT> , DAG ) ; BitMask = DAG . getBitcast ( VT , BitMask ) ; BitMask = DAG . getVectorShuffle ( VT , dl , BitMask , BitMask , SmallVector < int , <NUM_LIT> > ( NumElts , <NUM_LIT> ) ) ; SDValue Res = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , DAG . getBitcast ( ExtVT , R ) , BaseShAmt , Subtarget , DAG ) ; Res = DAG . getBitcast ( VT , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , BitMask ) ; if ( Opcode == <STR_LIT> ) { SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , ExtVT ) ; SignMask = getTargetVShiftNode ( Logical<ISA_LIT>Op , dl , ExtVT , SignMask , BaseShAmt , Subtarget , DAG ) ; SignMask = DAG . getBitcast ( VT , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , SignMask ) ; } return Res


<s> debug ( <STR_LIT> ) ; return - <NUM_LIT> ; case ENCODING_VVVV : insn -> vvvv = ( Reg ) fixupRegValue ( insn , ( OperandType ) op -> type , insn -> vvvv , & valid ) ; if ( ! valid ) return - <NUM_LIT> ; break ; case ENCODING_REG : insn -> reg = ( Reg ) fixupRegValue ( insn , ( OperandType ) op -> type , insn -> reg -


<s> bool isMem128_RC256 ( ) const { return isMem128 ( ) && isMemIndexReg ( <STR_LIT> , <STR_LIT>


<s> while ( DstIdx && ( SrcIdx < Sz - <NUM_LIT> ) && Dst [ -- DstIdx ] == Src [ ++ SrcIdx ] && ! Aquired


<s> processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + <STR_LIT> ) ; int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I

) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) {


<s> MachineInstr * MI = getLoopendBlockBranchInstr ( ContingMBB ) ; if ( MI ) { assert ( isCondBranch ( MI ) ) ; MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * TrueBranch = getTrueBranch ( MI ) ; int OldOpcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool UseContinueLogical = ( ( & * ContingMBB ->


<s> if ( Node -> getOpcode ( ) == <STR_LIT> ) return SelectREAD_PARAM ( Node ) ; else return SelectCode ( Node )


<s> switch ( AM . Scale ) { case <NUM_LIT> : return true ; case <NUM_LIT> : return true ; case <NUM_LIT> : if ( AM . HasBaseReg ) { return false


<s> if ( ! PhiDef ) return false ; if ( PhiDef -> isPHI ( ) ) { if ( PhiInsns . find ( PhiDef ) != PhiInsns . end ( ) ) return false ; PhiInsns . insert ( PhiDef ) ; if ( ! isPhiFrom32Def ( PhiDef ) ) return false ; } if ( PhiDef -> getOpcode ( ) == <STR_LIT> && ! isCopyFrom32Def ( PhiDef ) )


<s> InstructionSelector * create<ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , <ISA_LIT>Subtarget & Subtarget , <ISA_LIT>RegisterBankInfo & RBI ) { return new <ISA_LIT>InstructionSelector ( TM , Subtarget , RBI


<s> return A0_REGS ; case A1_REGNO : return A1_REGS ; case SB_REGNO : return SB_REGS ; case FB_REGNO : return FB_REGS ; case SP_REGNO : return SP_REGS ; case FLG_REGNO : return FLG_REGS ; default : if ( IS_MEM_REGNO ( regno ) ) return MEM_REGS ; return ALL_REGS


<s> Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc


<s> static void findTemporariesForLR ( const BitVector & GPRsNoLRSP , const BitVector & PopFriendly , const LivePhysRegs & UsedRegs , unsigned & PopReg , unsigned & TmpReg , MachineRegisterInfo & MRI ) { PopReg = TmpReg = <NUM_LIT> ; for ( auto Reg : GPRsNoLRSP .


<s> MCInst <ISA_LIT>InstrInfo :: getNop ( ) const { MCInst Nop ; Nop . setOpcode (


<s> for ( i = <NUM_LIT> ; i < NR_C_MODES ; i ++ ) if ( constant_modes [ i ] == mode ) break ; gcc_assert ( i != NR_C_MODES ) ; for ( c = pool -> constants [ i ] ; c != NULL ; c = c -> next ) if ( rtx_equal_p ( val , c -> value ) ) break ; gcc_assert ( c ) ; offset = gen_rtx_MINUS ( Pmode , gen_rtx_LABEL_REF ( Pmode , c -> label ) , gen_rtx_LABEL_REF ( Pmode , pool -> label ) ) ; offset = gen_rtx_CONST ( Pmode , offset


<s> tmp = gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ; if ( reload_completed && ( ! TARGET_USE_MOV0 || optimize_size ) ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , <NUM_LIT> ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , tmp , clob


<s> const MCOperand & Op = MI . getOperand ( i ) ; if ( & Op == & MO ) return i ; } llvm_unreachable ( <STR_LIT> ) ; return ~ <NUM_LIT>


<s> static VectorType * getVectorType ( IntrinsicInst * I ) { unsigned TypeOp = I -> getIntrinsicID ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; auto * PtrTy = cast < PointerType > ( I -> getOperand ( TypeOp ) -> getType


<s> unsigned EAX = <NUM_LIT> , EBX = <NUM_LIT> , ECX = <NUM_LIT> , EDX = <NUM_LIT> ; union { unsigned u [ <NUM_LIT> ] ; char c [ <NUM_LIT> ] ; } text ; if ( <STR_LIT> ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; <STR_LIT> ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ; bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text .


<s> if ( const ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N ) ) return TII -> isInlineConstant ( C -> getValueAPF ( ) . bitcastToAPInt ( ) ) ; return


<s> if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Amt ) ) if ( auto * AmtSplat = AmtBV -> getConstantSplatNode ( ) ) { APInt ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getSimpleVT ( ) . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ShiftAmt . trunc ( <NUM_LIT> ) . uge ( MaxAmount ) ) return getZeroVector ( VT .

getSimpleVT ( ) , Subtarget , DAG , DL ) ;


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinCFISaveSP ( unsigned


<s> if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) { MI . setDesc ( TII -> get ( Opcode ) ) ; return


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<s> p = <NUM_LIT> + * max_element ( std :: begin ( parentPreds ) , std :: end ( parentPreds ) ) ; } else { p = <NUM_LIT> ; } auto blocks = Pub . getBlocksTopoOrd ( ) ; for ( auto block : blocks ) { CD_map_entry_t t = CD . at ( block ) ; int q = - <NUM_LIT> ; for ( auto pair : K ) { if ( t == pair . second ) { q = pair . first ; break ; } } if ( q != - <NUM_LIT> ) { blockPreds [ block ] = q ; } else { if ( ! Pub . isTopLevel ( ) && block == Pub . getHeader ( ) ) { K . insert ( make_pair ( * Pub . getHeader ( ) -> getBlockPredicates ( ) . begin ( ) , t ) ) ; blockPreds [ block ] = * Pub . getHeader ( ) -> getBlockPredicates ( ) . begin ( ) ; } else { K . insert ( make_pair ( p , t ) ) ; blockPreds [ block ] = p ++ ; } } } DEBUG_TRACE ( { dbgs ( ) << <STR_LIT> ; dbgs ( ) . indent ( <NUM_LIT> )


<s> case <STR_LIT> : return tryCombineFixedPointConvert ( N , DCI , DAG ) ; break ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( GrpCount % <NUM_LIT> ) Idx += <NUM_LIT> ; if ( SU != nullptr && ! fitsIntoCurrentGroup ( SU ) ) { if ( Idx == <NUM_LIT> || Idx == <NUM_LIT> ) Idx = <NUM_LIT> ; else if ( Idx == <NUM_LIT> || Idx == <NUM_LIT> ) Idx = <NUM_LIT> ; } return Idx


<s> Addr = N ; Update = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT>


<s> return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpgt ( a


<s> unsigned Opcode = MCID . getOpcode ( ) ; if ( ! ( <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) ) ) return - <NUM_LIT> ; unsigned NumUses = MCID . getNumOperands ( ) -


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = getLoc (


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; } else if ( Domain == <STR_LIT> ) { if ( MI -> getDesc ( ) . mayStore ( ) || MI -> getDesc ( ) . mayLoad ( ) ) return false ; } else return


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ; AFI -> setVarArgsFrameIndex ( FrameIndex


<s> void <ISA_LIT>CodeEmitter :: emitBasicBlock ( MachineBasicBlock & MBB ) { MCE . StartMachineBasicBlock ( & MBB ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++


<s> case VK_CALL : return <STR_LIT> ; case VK_LO12 : return <STR_LIT> ; case VK_ABS_G3 : return <STR_LIT> ; case VK_ABS_G2 : return <STR_LIT> ; case VK_ABS_G2_S : return <STR_LIT> ; case VK_ABS_G2_NC : return <STR_LIT> ; case VK_ABS_G1 : return <STR_LIT> ; case VK_ABS_G1_S : return <STR_LIT> ; case VK_ABS_G1_NC : return <STR_LIT> ; case VK_ABS_G0 : return <STR_LIT> ; case VK_ABS_G0_S : return <STR_LIT> ; case VK_ABS_G0_NC : return <STR_LIT> ; case VK_PREL_G3 : return <STR_LIT> ; case VK_PREL_G2 : return <STR_LIT> ; case VK_PREL_G2_NC : return <STR_LIT> ; case VK_PREL_G1 : return <STR_LIT> ; case VK_PREL_G1_NC : return <STR_LIT> ; case VK_PREL_G0 : return <STR_LIT> ; case VK_PREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_HI12 : return <STR_LIT> ; case VK_DTPREL_LO12 : return <STR_LIT> ; case VK_DTPREL_LO12_NC : return <STR_LIT> ; case VK_TPREL_G2 : return <STR_LIT> ; case VK_TPREL_G1 : return <STR_LIT> ; case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ; case VK_TPREL_HI12 : return <STR_LIT> ; case VK_TPREL_LO12 : return <STR_LIT> ; case VK_TPREL_LO12_NC : return <STR_LIT> ; case VK_TLSDESC_LO12 : return <STR_LIT> ; case VK_ABS_PAGE :


<s> inline static bool isMinSize ( const MachineFunction & MF ) { AttributeSet AF = MF . getFunction ( ) -> getAttributes (


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; const APFloat K0Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K0 = DAG . getConstantFP ( K0Val , SL , <STR_LIT> ) ; const APFloat K1Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K1 = DAG . getConstantFP ( K1Val , SL , <STR_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue r2 = DAG . getSetCC ( SL , SetCCVT , r1 , K0 , <STR_LIT> ) ; SDValue r3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r2 , K1 , One ) ; r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS , r3 ) ; SDValue r0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , r1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> ,


<s> if ( ! Subtarget . hasAVX ( ) || ( Factor != <NUM_LIT> && Factor != <NUM_LIT> ) ) return false ; if ( isa < LoadInst > ( Inst ) ) { WideInstSize = DL . getTypeSizeInBits ( Inst -> getType ( ) ) ; if ( cast < LoadInst > ( Inst ) -> getPointerAddressSpace ( ) ) return false ; } else WideInstSize = DL . getTypeSizeInBits ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; if ( ShuffleElemSize == <NUM_LIT> && WideInstSize == <NUM_LIT> && Factor == <NUM_LIT> ) return true ; if ( ShuffleElemSize == <NUM_LIT> && isa < StoreInst > ( Inst ) && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> ) ) return true ; if ( ShuffleElemSize == <NUM_LIT> && Factor == <NUM_LIT> && ( WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> || WideInstSize == <NUM_LIT> ) ) return true ; return false


<s> PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , DL ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff ,

MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>AsmParser :: emitPseudoExtend ( MCInst & Inst , bool SignExtend , int64_t Width , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; MCOperand SourceReg = Inst . getOperand ( <NUM_LIT> ) ; unsigned SecondOpcode = SignExtend ? <STR_LIT> : <STR_LIT> ; int64_t ShAmt = ( isRV64 ( ) ? <NUM_LIT> : <NUM_LIT> ) - Width ; assert ( ShAmt > <NUM_LIT> &&


<s> SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( SVOp ) ; MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i + NumElemsInLane )


<s> bool RegDefsUses :: isRegInSet ( const BitVector & RegSet , unsigned Reg ) const { for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . test ( * AI ) ) return true ; return


<s> typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_ssaddv2si3 ( ( v2si ) mm ,


<s> if ( RelocOp -> isGlobal ( ) ) { FinalSize += sizeGlobalAddress ( false ) ; } else if ( RelocOp -> isCPI ( ) ) { FinalSize += sizeConstPoolAddress ( false ) ; } else if ( RelocOp -> isJTI (


<s> vec_ushort8 bits ; vec_uint4 bytes ; bits = vec_sl ( vec_and ( ( vec_ushort8 ) ( a ) , vec_splat_u16 ( <NUM_LIT> ) ) , ( ( vec_ushort8 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; bytes = ( vec_uint4 ) vec_sums ( ( vec_int4 ) ( vec_sum4s ( ( vec_short8 ) ( bits


<s> SDValue ExtendToInt64 ( SDValue V , const SDLoc & dl ) { if ( V . getValueSizeInBits ( ) == <NUM_LIT> ) return V ; assert ( V . getValueSizeInBits ( ) == <NUM_LIT> ) ; SDValue SubRegIdx = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue ImDef = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> ,


<s> return ; case ADDRESS_CONST_INT : fprintf ( file , <STR_LIT> , reg_names [ GP_REG_FIRST ] ) ; output_addr_const ( file , x ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , loongarch_strip_unspec_address ( x ) ) ; return ; } if ( CONST_INT_P ( x ) ) output_addr_const ( file , x ) ; else gcc_unreachable (


<s> break ; case BRIG_COMPARE_LE : O << <STR_LIT> ; break ; case BRIG_COMPARE_GT : O << <STR_LIT> ; break ; case BRIG_COMPARE_GE : O << <STR_LIT> ; break ; case BRIG_COMPARE_EQU : O << <STR_LIT> ; break ; case BRIG_COMPARE_NEU : O << <STR_LIT> ; break ; case BRIG_COMPARE_LTU : O << <STR_LIT> ; break ; case BRIG_COMPARE_LEU : O << <STR_LIT> ; break ; case BRIG_COMPARE_GTU : O << <STR_LIT> ; break ; case BRIG_COMPARE_GEU : O << <STR_LIT> ; break ; case BRIG_COMPARE_NUM : O << <STR_LIT> ; break ; case BRIG_COMPARE_NAN : O << <STR_LIT> ; break ; case BRIG_COMPARE_SEQ : O << <STR_LIT> ; break ; case BRIG_COMPARE_SNE : O << <STR_LIT> ; break ; case BRIG_COMPARE_SLT : O << <STR_LIT> ; break ; case BRIG_COMPARE_SLE : O << <STR_LIT> ; break ; case BRIG_COMPARE_SGT : O << <STR_LIT> ; break ; case BRIG_COMPARE_SGE : O << <STR_LIT> ; break ; case BRIG_COMPARE_SGEU : O << <STR_LIT> ; break ; case


<s> MVT ValVT = VA . getValVT ( ) ; if ( VA . getValVT ( ) == <STR_LIT> || VA . getValVT ( ) == <STR_LIT> ) { std :: swap ( ValVT , LocVT ) ; MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } ValVReg = extendRegister ( ValVReg , VA , MaxSize ) ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBits ( ) < LocVT . getSizeInBits ( ) ) ValVReg = MIRBuilder . buildTrunc ( RegTy , ValVReg ) . getReg ( <NUM_LIT> ) ; } else { MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } assignValueToAddress ( ValVReg , Addr , MemSize , MPO , VA


<s> return ( __m512i ) __builtin_ia32_cvttps2dq512_mask ( ( __v16sf ) __A , ( __v16si ) _mm512_undefined_si512 ( ) , ( __mmask16


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG


<s> TargetRegistry :: RegisterTarget ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , true ) ; RegisterTarget < Triple :: bpfel , true > X ( getThe<ISA_LIT>leTarget ( ) ,


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , Op . getDebugLoc


<s> switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_GE ; case GT : return AARCH64_GT ; case LE : return AARCH64_LE ; case LT : return AARCH64_LT ; case GEU : return AARCH64_CS ; case GTU : return AARCH64_HI ; case LEU : return AARCH64_LS ; case LTU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case E_CC_SWPmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_LE ; case GT : return AARCH64_LT ; case LE : return AARCH64_GE ; case LT : return AARCH64_GT ; case GEU : return AARCH64_LS ; case GTU : return AARCH64_CC ; case LEU : return AARCH64_CS ; case LTU : return AARCH64_HI ; default : return - <NUM_LIT> ; } break ; case E_CC_NZmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_PL ; case LT : return AARCH64_MI ; default : return - <NUM_LIT> ; } break ; case E_CC_Zmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; default : return - <NUM_LIT> ; } break ; case E_CC_Cmode : switch ( comp_code ) { case LTU : return AARCH64_CS ; case GEU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case E_CC_ADCmode : switch ( comp_code ) { case GEU : return AARCH64_CS ; case LTU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case E_CC_Vmode : switch ( comp_code ) { case NE : return AARCH64_VS ; case EQ : return


<s> if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && ( ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg &&

OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ;


<s> rtx mem = gen_rtx_MEM ( word_mode , addr ) ; MEM_VOLATILE_P ( mem ) = <NUM_LIT> ; emit_insn ( gen_probe_stack ( mem )


<s> if ( mask1 != ~ mask2 ) return false ; if ( mask2 == <NUM_LIT> || mask2 == HOST_WIDE_INT_M1U ) return false ; gcc_assert ( shft_amnt < GET_MODE_BITSIZE (


<s> <ISA_LIT>PassConfig :: addPreISel ( ) ; addPass ( create<ISA_LIT>LateCodeGenPreparePass ( ) ) ; if ( EnableAtomicOptimizations ) { addPass ( create<ISA_LIT>AtomicOptimizerPass ( ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( & <ISA_LIT>UnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { if ( EnableStructurizerWorkarounds ) { addPass ( createFixIrreduciblePass ( ) ) ; addPass ( createUnifyLoopExitsPass ( ) ) ; } addPass ( createStructurizeCFGPass ( false ) ) ; } addPass ( create<ISA_LIT>AnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize


<s> static void getLabelAccessInfo ( bool IsPIC , const <ISA_LIT>Subtarget & Subtarget , unsigned & HiOpFlags , unsigned & LoOpFlags , const GlobalValue * GV = nullptr ) { HiOpFlags = <STR_LIT> ; LoOpFlags = <STR_LIT> ; if (


<s> cpp_assert ( pfile , <STR_LIT> ) ; cpp_assert ( pfile , <STR_LIT> ) ; cpp_define ( pfile , <STR_LIT> ) ; if ( TARGET_ZARCH ) cpp_define ( pfile , <STR_LIT> ) ; if ( TARGET_64BIT ) cpp_define ( pfile , <STR_LIT> ) ; if ( TARGET_LONG_DOUBLE_128 ) cpp_define ( pfile , <STR_LIT> ) ; cl_target_option_save ( & opts , &

global_options , & global_options_set ) ;


<s> void addToProcessedPHI ( PHINode * PHI


<s> void addVectorListOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> if ( Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; if ( Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; if ( Pred1 [ <NUM_LIT> ] . getReg ( ) != Pred2 [ <NUM_LIT> ] . getReg ( ) ) return false ; <STR_LIT> P1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> P2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( P1 == P2 ) return true ; if ( P1 == <STR_LIT> && ( P2 == <STR_LIT> || P2 == <STR_LIT> ) ) return true ; if ( P1 == <STR_LIT> && ( P2 == <STR_LIT> || P2 == <STR_LIT> ) ) return true ; return


<s> if ( TT . isOSBinFormatELF ( ) ) emitAttributes ( ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) && TT . isThumb ( )

) OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ;


<s> vec_st ( ( vec_uchar16 ) ( a ) , si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( b )

, ( vec_uint4 ) ( c ) ) ) ) , ( vector unsigned char * ) ( <NUM_LIT> ) ) ;


<s> } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case <STR_LIT> : break ; default : O << getRegisterName ( Op . getReg ( ) ) ; break ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op . isDFPImm ( ) ) { if ( Op . getDFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { O << bit_cast < double > ( Op . getDFPImm ( ) ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O <<


<s> fputs ( integer_asm_op ( size , FALSE ) , file ) ; assemble_name ( file , label ) ; fputs ( <STR_LIT> ,


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> NegatePredicate ( & * II ) ; } return true ; } int i = MI -> findFirstPredOperandIdx ( ) ; assert ( i != - <NUM_LIT> ) ; MachineOperand & PO2 = MI -> getOperand ( i + <NUM_LIT> ) ; assert ( PO2 . isImm ( ) && <STR_LIT> ) ; bool flag = ( PO2 . getImm ( ) != <NUM_LIT> ) ^ <NUM_LIT> ; PO2 . setImm ( flag ) ; return true


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering


<s> SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Op0 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , Op0 , Op1 , CC , dl , Op0 , Op1 , Chain , Op . getOpcode ( ) == <STR_LIT> ) ; if ( ! Op1 . getNode ( ) ) { assert ( Op0 . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; if ( IsStrict ) return DAG . getMergeValues ( { Op0 , Chain } , dl ) ; return Op0 ; } } if ( Op0 . getSimpleValueType ( ) . isInteger ( ) ) { SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC ) ; if ( ! EFLAGS ) return SDValue ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT>CC ,


<s> ++ begin ) { if ( ! strcmp ( begin -> name . data ( ) , arg . c_str ( ) ) ) { return & ( * begin ) ; } } return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CodeModel :: Medium , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) { initAsmInfo (


<s> return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [


<s> case <STR_LIT> : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT>


<s> void <ISA_LIT>InsertWaitcnts :: updateEventWaitcntAfter ( MachineInstr & Inst , WaitcntBrackets * ScoreBrackets ) { if ( TII -> isDS ( Inst ) && TII -> usesLGKM_CNT ( Inst ) ) { if ( TII -> isAlwaysGDS ( Inst . getOpcode ( ) ) || TII -> hasModifiersSet ( Inst , <STR_LIT> :: gds ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_ACCESS , Inst ) ; ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_GPR_LOCK , Inst ) ; } else { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; } } else if ( TII -> isFLAT ( Inst ) ) { assert ( Inst . mayLoadOrStore ( ) ) ; if ( TII -> usesVM_CNT ( Inst ) ) { if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; } if ( TII -> usesLGKM_CNT ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; if ( mayAccessLDSThroughFlat ( Inst ) ) ScoreBrackets -> setPendingFlat ( ) ; } } else if ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) || ( TII -> isMIMG ( Inst ) && ! Inst . mayLoad ( ) && ! Inst . mayStore ( ) ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else if ( Inst . mayStore ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; } else if ( Inst . isCall (


<s> unsigned Opcode = MI . getOpcode ( ) ; int TargetMemOpcode = <STR_LIT> ( Opcode ) ; if ( TargetMemOpcode != - <NUM_LIT> ) { MI . setDesc ( TII -> get ( TargetMemOpcode ) ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; if ( DstReg != SrcMO . getReg ( ) ) { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT>

) , DstReg ) . addReg ( SrcMO . getReg ( ) ) ;


<s> set_of_reg t_after_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , next_nonnote_insn_bb ) ; if ( t_before_negc . set_rtx != NULL_RTX && t_after_negc . set_rtx != NULL_RTX && rtx_equal_p ( t_before_negc . set_rtx , t_after_negc . set_rtx ) && ! reg_used_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_insn_operands_modified_between_p ( t_before_negc . insn , t_before_negc . insn , t_after_negc . insn ) && ! modified_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_unspec_insn_p ( t_after_negc . insn ) && ! volatile_insn_p ( PATTERN ( t_after_negc . insn ) )

&& ! side_effects_p ( PATTERN ( t_after_negc . insn ) ) && ! may_trap_or_fault_p ( PATTERN ( t_after_negc . insn ) ) ) {


<s> if ( mode == QImode ) rclass = reduce_class ( rclass , HL_REGS , rclass ) ; else if ( mode == HImode ) rclass = reduce_class ( rclass , HI_REGS , rclass ) ; else if ( mode == SImode ) rclass = reduce_class ( rclass , SI_REGS , rclass ) ; if ( rclass != A_REGS ) rclass =

reduce_class ( rclass , DI_REGS , rclass ) ;


<s> switch ( model ) { case TLSModel :: GeneralDynamic : if ( Subtarget . is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , PtrVT ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , PtrVT ) ; case TLSModel :: LocalDynamic : return LowerToTLSLocalDynamicModel ( GA , DAG , PtrVT , Subtarget . is64Bit ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , PtrVT , model , Subtarget . is64Bit ( ) , PositionIndependent ) ; } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget . isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget . isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = PositionIndependent && ! Subtarget . is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; SDLoc DL ( Op ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , DL ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , Chain . getValue ( <NUM_LIT> ) , DL ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; unsigned Reg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget . isTargetKnownWindowsMSVC ( ) || Subtarget . isTargetWindowsItanium ( ) || Subtarget . isTargetWindowsGNU ( ) ) { SDLoc dl ( GA ) ; SDValue Chain = DAG . getEntryNode


<s> if ( ! TARGET_ZVECTOR ) return NULL ; if ( ! VECTOR_TYPE_P ( type1 ) || ! VECTOR_TYPE_P ( type2 ) ) return NULL ; bool1_p = s390_vector_bool_type_p ( type1 ) ; bool2_p = s390_vector_bool_type_p ( type2 ) ; if ( ! bool1_p && ! bool2_p && TYPE_UNSIGNED ( type1 ) != TYPE_UNSIGNED ( type2 ) ) return N_ ( <STR_LIT> ) ; plusminus_p = ( op == PLUS_EXPR || op == MINUS_EXPR ) ; muldiv_p = ( op == MULT_EXPR || op == RDIV_EXPR || op == TRUNC_DIV_EXPR || op == CEIL_DIV_EXPR || op == FLOOR_DIV_EXPR || op == ROUND_DIV_EXPR ) ; compare_p = ( op == LT_EXPR || op == LE_EXPR || op == GT_EXPR || op

== GE_EXPR || op == EQ_EXPR || op == NE_EXPR ) ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses (


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) { unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & <STR_LIT> :


<s> if ( UseReg ) return isThumb2 ? <STR_LIT> : <STR_LIT> ; else return isThumb2 ? <STR_LIT>


<s> void <ISA_LIT>ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { if ( ! printAliasInstr ( MI , OS )


<s> if ( type ) return int_size_in_bytes ( type ) ; if ( mode != BLKmode ) return


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) ,

ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue X , Y ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { X = N0 . getOperand ( <NUM_LIT> ) ; Y =


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Op , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperands ( const <ISA_LIT>AddressingMode & AM , EVT VT , SDValue & Base , SDValue & Disp ) { Base = AM . Base ; if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; } else if ( Base . getValueType ( ) != VT


<s> if ( size ) fprintf ( file , <STR_LIT> , align , reg_names [ regno ] , size ) ; fprintf ( file , <STR_LIT> , POINTER_SIZE , reg_names [ regno ] ) ; fprintf ( file , ( size ? <STR_LIT> : <STR_LIT> ) , POINTER_SIZE , reg_names [ regno


<s> unsigned getReg213Opcode ( ) const { assert ( RegOpcodes && <STR_LIT>


<s> PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; SuccPrepCount = <NUM_LIT> ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE =

df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> else { if ( cfun -> machine -> call_via [ regno ] == NULL ) cfun -> machine -> call_via [ regno ] = gen_label_rtx ( ) ; labelp = cfun -> machine -> call_via + regno ; } output_asm_insn ( <STR_LIT> , labelp ) ; return <STR_LIT>


<s> LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT> ) ; SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; const Value * V = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; EVT VT = Node -> getValueType


<s> bool <ISA_LIT>InstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { return true


<s> Inst . addOperand ( MCOperand :: createReg (


<s> int64_t Offset = <NUM_LIT> ; if ( DAG . isBaseWithConstantOffset ( BasePtr ) && isWordAligned ( BasePtr -> getOperand ( <NUM_LIT> ) , DAG ) ) { SDValue NewBasePtr = BasePtr -> getOperand ( <NUM_LIT> ) ; Offset = cast < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; return lowerLoadWordFromAlignedBasePlusOffset ( DL , Chain , NewBasePtr , Offset , DAG ) ; } if ( TLI . isGAPlusOffset ( BasePtr . getNode ( ) , GV , Offset ) && MinAlign ( GV -> getAlignment ( ) , <NUM_LIT> ) == <NUM_LIT> ) { SDValue NewBasePtr = DAG . getGlobalAddress ( GV , DL , BasePtr -> getValueType ( <NUM_LIT> ) ) ; return lowerLoadWordFromAlignedBasePlusOffset ( DL , Chain , NewBasePtr , Offset , DAG ) ; } } if ( LD -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , LD -> getPointerInfo ( ) , <STR_LIT> , <NUM_LIT> , LD -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> static bool isValidLoadStoreOffset ( int64_t


<s> return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } return false ; case IS_VGPR : case IS_SGPR : case IS_TTMP : if ( Reg1 != Reg + RegWidth ) { return false ; } RegWidth ++ ; return true ; default : llvm_unreachable (


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; bool ClobbersCPSR = MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ; bool IsCPSR = MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ; if ( ClobbersCPSR || IsCPSR


<s> s390_indirect_branch_settings ( fndecl ) ; return ; } tree old_tree ; if ( s390_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( s390_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( s390_previous_fndecl ) ; else old_tree


<s> LowerFP_TO_SINT ( SDValue Op , SelectionDAG & DAG ) const { if ( ! Subtarget -> is<ISA_LIT>1 ( ) ) return Op ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CCReg = AddLiveIn ( MF , <STR_LIT> , <STR_LIT> ) ; SDValue Chain = DAG . getEntryNode ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue CondReg = DAG . getCopyFromReg ( Chain , dl , CCReg , <STR_LIT> ) ; CondReg = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , CondReg ) ; CondReg = DAG . getCopyFromReg ( CondReg , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CondReg ,


<s> computeIndirectRegAndOffset ( Vec , Reg , Off ) ; MachineInstr * MovRel = BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Reg ) . addReg ( <STR_LIT> , RegState

:: Implicit ) . addReg ( Vec , RegState :: Implicit ) ;


<s> bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( psbhintop , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O << Name ; else O << '#'


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> Value * convertTo16Bit ( Value & V , InstCombiner :: BuilderTy & Builder ) { Type * VTy = V . getType ( ) ; if ( isa < FPExtInst > ( & V ) || isa < SExtInst > ( & V ) || isa < ZExtInst > ( & V ) ) return cast < Instruction > ( & V ) -> getOperand ( <NUM_LIT> ) ; if ( VTy -> isIntegerTy ( ) ) return Builder . CreateIntCast ( & V , Type :: getInt16Ty ( V . getContext ( ) ) , false ) ; if ( VTy -> isFloatingPointTy ( ) ) return Builder . CreateFPCast ( & V ,

Type :: getHalfTy ( V . getContext ( ) ) ) ;


<s> if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold -


<s> adjust<ISA_LIT>StackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> hasCalls ( ) ) return ; if ( StackSize < <NUM_LIT> && MFI -> hasCalls ( ) ) StackSize = <NUM_LIT> ; int FPOffset = <ISA_LIT>FI -> getFPStackOffset ( ) ; int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) . addReg


<s> bool HasHazard = Candidate . isImplicitDef ( ) ; HasHazard |= IM . hasHazard ( Candidate ) ; HasHazard |= RegDU . update ( Candidate , <NUM_LIT> , Candidate .


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT> :: e_rf_vp ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT> :: e_rf_s ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT> :: e_rf_sp ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT> :: e_rf_i ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT>


<s> assert ( ( Imm & <NUM_LIT> ) == Imm && <STR_LIT> ) ; switch ( Imm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> return ; } for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * child_fma ; rtx fma_rtx , * accum_rtx_p ; if ( ! is_fmul_fmac_insn ( chain -> insn , false ) ) continue ; fma_rtx = SET_SRC ( PATTERN ( chain -> insn ) ) ; if ( GET_CODE ( fma_rtx ) == NEG ) fma_rtx = XEXP ( fma_rtx , <NUM_LIT> ) ; accum_rtx_p = & XEXP ( fma_rtx , <NUM_LIT> ) ; if ( ! REG_P ( * accum_rtx_p ) ) accum_rtx_p = & XEXP ( * accum_rtx_p , <NUM_LIT> ) ; if ( accum_rtx_p != chain -> loc ) continue ; if ( this -> get_fma_node ( chain -> insn ) ) continue ; child_fma = new fma_node ( node , chain ) ; node -> add_child (


<s> <STR_LIT> <STR_LIT> ( const MVT & Ty ) { switch ( Ty . SimpleTy ) { case <STR_LIT> : return <STR_LIT> :: I32 ; case <STR_LIT> : return <STR_LIT>


<s> std :: vector < SDValue > Ops ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) , Node -> op_begin ( ) + DmaskIdx ) ; Ops . push_back ( DAG . getTargetConstant ( NewDmask , SDLoc ( Node ) , <STR_LIT> ) ) ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) + DmaskIdx + <NUM_LIT> , Node -> op_end ( ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops ) ; if ( NewDmask && ( NewDmask & ( NewDmask - <NUM_LIT> ) ) == <NUM_LIT> ) { SDValue RC = DAG . getTargetConstant ( <STR_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = <STR_LIT> ; i < <NUM_LIT> ; ++ i ) { SDNode * User = Users [ i ] ; if ( ! User ) continue ; SDValue Op = DAG . getTargetConstant ( Idx , SDLoc ( User ) , <STR_LIT> ) ; DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Op ) ; switch ( Idx ) { default : break


<s> if ( crtl -> profile ) return false ; aarch64_layout_frame ( ) ; return cfun -> machine -> frame . frame_size ==


<s> Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm


<s> void <ISA_LIT>RegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; bool FP = hasFP ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( const_cast < Function * > ( MF . getFunction ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( ++ curgpdist ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addGlobalAddress ( const_cast < Function * > ( MF . getFunction ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( curgpdist ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( const_cast < Function * > ( MF . getFunction ( ) ) ) ; long NumBytes = MFI -> getStackSize ( ) ; if ( FP ) NumBytes += <NUM_LIT> ; if ( NumBytes == <NUM_LIT> ) return ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; NumBytes = ( NumBytes + Align - <NUM_LIT> ) / Align * Align ; MFI -> setStackSize


<s> unsigned NumElems = HwLen / ( ElemTy . getSizeInBits ( ) / <NUM_LIT> ) ; return <STR_LIT> ( ElemTy , NumElems


<s> unsigned PCAdj = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned BrOffset = GetOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBOffsets [ DestBB -> getNumber ( ) ] ; DEBUG ( errs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << MaxDisp << <STR_LIT> << GetOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset


<s> if ( isToken ( AsmToken :: Integer ) ) { SMLoc Loc = getToken ( ) . getEndLoc ( ) ; Token = std :: string ( getTokenStr ( ) ) ; Parser . Lex ( ) ; if ( getLoc ( ) != Loc ) return MatchOperand_ParseFail ; } if ( ! isToken ( AsmToken :: Identifier ) ) return MatchOperand_ParseFail ; Token += getTokenStr ( ) ; StringRef DimId = Token ; if ( DimId . startswith ( <STR_LIT> ) ) DimId = DimId . substr ( <NUM_LIT> ) ; const <STR_LIT> * DimInfo = <STR_LIT> ( DimId ) ; if ( ! DimInfo ) return


<s> static bool isKnownNeverSNan ( SelectionDAG & DAG , SDValue Op ) { if ( ! DAG . getTargetLoweringInfo ( ) . hasFloatingPointExceptions (


<s> } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM , Base , Scale , Index , Disp ) ; return true


<s> const TargetRegisterInfo & RI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; Register stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo (


<s> const <ISA_LIT>BufferPseudoSourceValue * getBufferPSV ( const <ISA_LIT>InstrInfo & TII ,


<s> const GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; return getAddr ( N ,


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! MFI . hasStackObjects ( ) ) return ; bool MayNeedScavengingEmergencySlot = MFI . hasStackObjects ( ) ; assert ( ( RS || ! MayNeedScavengingEmergencySlot ) &&


<s> } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; else return getParser ( ) . Error ( IDLoc , MemNoShuffMsg ) ; } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { } else return getParser ( ) . Error ( IDLoc , llvm :: Twine ( <STR_LIT> ) + Option + <STR_LIT> ) ; Lex ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> static const MCSymbolRefExpr * getGlobalOffsetTable ( MCContext &


<s> JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; return getAddr ( N , DAG


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSFreeBSD ( ) ) return make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) ) return make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ; if ( TT . isOSFuchsia ( ) ) return make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ; if ( TT . isOSBinFormatELF ( ) ) return make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) || TT . isWindowsCoreCLREnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile


<s> static const CostTblEntry ShuffleTbl [ ] = { { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Broadcast , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Transpose , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_Select , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , { TTI :: SK_PermuteSingleSrc , <STR_LIT> , <NUM_LIT> } , } ; std :: pair < int , MVT > LT = TLI

-> getTypeLegalizationCost ( DL , Tp ) ;


<s> void setReg ( unsigned Reg ) { assert ( isRegBase (


<s> return MIB . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addReg


<s> bool nds32_n13_last_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , -


<s> if ( ( from == FP_REGS && to == GR_REGS ) || ( from == GR_REGS && to == FP_REGS ) ) return


<s> unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI


<s> MachineInstrBuilder emitInstStore ( unsigned Opc , unsigned SrcReg , unsigned MemReg , int64_t MemOffset ) { return emitInst ( Opc ) . addReg ( SrcReg ) . addReg ( MemReg ) .


<s> const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string target = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; string source = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * load = ctx -> load ( <NUM_LIT> , source ) ; SExpr * stor = ctx -> store ( ctx -> address ( target ) , load ) ; alfbb . addStatement ( label , TII -> getName ( MI . getOpcode


<s> if ( UnifiedVGPRFile ) { return Value [ AGPR32 ] ? alignTo ( Value [ VGPR32 ] , <NUM_LIT> ) + Value [ AGPR32 ] : Value [ VGPR32 ] +


<s> else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { return Op ; } return SDValue ( )


<s> if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> ) ShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasBMI2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && ShiftAmt . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShiftAmt . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( ShiftAmt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == Size ) return false ; SDValue NewShiftAmt ; if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> || ShiftAmt -> getOpcode ( ) == <STR_LIT> ) { SDValue Add0 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; SDValue Add1 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Add1 ) && cast < ConstantSDNode > ( Add1 ) -> getZExtValue ( ) % Size == <NUM_LIT> ) { NewShiftAmt = Add0 ; } else if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Add0 ) && cast < ConstantSDNode > ( Add0 ) -> getZExtValue ( ) != <NUM_LIT> && cast < ConstantSDNode > ( Add0 ) -> getZExtValue ( ) % Size == <NUM_LIT> ) { EVT SubVT = ShiftAmt . getValueType ( ) ; SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , DL , SubVT ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = Neg ; insertDAGNode ( * CurDAG , OrigShiftAmt , Zero ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , Neg ) ; } else return false ; } else return false ; if ( NewShiftAmt . getValueType ( ) != <STR_LIT> ) { NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt ) ; insertDAGNode ( * CurDAG , OrigShiftAmt , NewShiftAmt ) ; } NewShiftAmt = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NewShiftAmt , CurDAG -> getConstant ( Size - <NUM_LIT> , DL , <STR_LIT> ) ) ; insertDAGNode ( * CurDAG , OrigShiftAmt ,


<s> SDValue Idx128 = Op . getOperand ( <NUM_LIT> ) ; auto * CIdx = dyn_cast < ConstantSDNode > ( Idx128 ) ; if ( CIdx && ( CIdx -> getZExtValue ( ) <= <NUM_LIT> ) ) { SDValue CI = DAG . getTargetConstant ( CIdx -> getZExtValue ( ) , DL , <STR_LIT> ) ; SDNode * DUPQ = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , V , CI ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( DUPQ , <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SplatOne = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , One ) ; SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SV , SplatOne ) ; SDValue Idx64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Idx128 , Idx128 ) ; SDValue SplatIdx64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Idx64 ) ; SDValue ShuffleMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) .


<s> Replacements . clear ( ) ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { for ( MachineBasicBlock :: iterator MI = MFI -> begin ( ) , ME = MFI -> end ( ) ; MI != ME ; ) { Modified |= runOnInstruction ( MI ++ ) ; } } for ( std :: set < MachineInstr * > :: iterator I = DeadInstr


<s> int getAddressOfCalleeRegister ( ) { return


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCT ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setStackPointerRegisterToSaveRestore (


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return


<s> MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg )

. addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> SmallVector < LiveInterval * , <NUM_LIT> > Intervals ; SmallVector < unsigned , <NUM_LIT> > OrigRegs ; SlotIndex MinInd , MaxInd ; for ( unsigned I = <NUM_LIT> ; I < Info -> VAddrDwords ; ++ I ) { const MachineOperand & Op = MI -> getOperand ( VAddr0Idx + I ) ; Register Reg = Op . getReg ( ) ; LiveInterval * LI = & LIS -> getInterval ( Reg ) ; if ( llvm :: find ( Intervals , LI ) != Intervals . end ( ) ) { Intervals . clear ( ) ; break ; } Intervals . push_back ( LI ) ; OrigRegs . push_back ( VRM -> getPhys ( Reg ) ) ; if ( LI -> empty ( ) ) { if ( I == <NUM_LIT> ) MinInd = MaxInd = LIS -> getInstructionIndex ( * MI ) ; continue ; } MinInd = I != <NUM_LIT> ? std :: min ( MinInd , LI -> beginIndex ( ) ) : LI -> beginIndex ( ) ; MaxInd = I != <NUM_LIT> ? std :: max ( MaxInd , LI -> endIndex ( ) ) : LI -> endIndex ( ) ; } if ( Intervals . empty ( ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ; for ( auto * LI : Intervals ) dbgs ( ) << <STR_LIT> << llvm :: printReg ( ( VRM -> getPhys ( LI -> reg ( ) ) ) , TRI ) ; dbgs ( ) << '\n' ) ; bool Success = scavengeRegs ( Intervals ) ; if ( ! Success ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( VRM -> hasPhys ( Intervals . back ( ) -> reg ( ) ) ) continue ; } else { auto I = std :: lower_bound ( Candidates . begin ( ) , & C , MinInd , [ this ] ( const Candidate & C , SlotIndex I ) { return LIS -> getInstructionIndex ( * C


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> EmitEpilogue ( OS ) ; XToJavaCounter ++ ; return true


<s> bool hasVInstructionsI64 ( ) const { return HasStdExtV || HasStdExtZve64x


<s> if ( decl == NULL ) return false ; if ( mep_section_tag ( DECL_RTL ( decl ) ) == 'f' ) return false ; if ( mep_interrupt_p ( ) || mep_disinterrupt_p


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ; Mask . push_back ( NumElems ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) Mask . push_back ( i ) ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 ,


<s> resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * I , * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * this , *


<s> static rtx frame_move ( rtx dst , rtx


<s> MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . add ( predOps ( <STR_LIT> ) ) ; ++ NumSplit ; NewBB -> transferSuccessors (


<s> void eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { MBB . erase


<s> void <ISA_LIT>LoadStoreOpt :: moveLiveRegsBefore ( const MachineBasicBlock & MBB , MachineBasicBlock :: const_iterator Before ) { if ( ! LiveRegsValid ) { LiveRegs . init ( TRI ) ; LiveRegs . addLiveOuts ( & MBB , true ) ; LiveRegPos = MBB . end ( ) ; LiveRegsValid = true ; } while ( LiveRegPos != Before ) { -- LiveRegPos ; LiveRegs . stepBackward (


<s> static DecodeStatus DecodeFPR128LoRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void *


<s> if ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses