<s> for ( unsigned i = <NUM_LIT> ; ; ++ i ) { unsigned regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; sa_mask |= HOST_WIDE_INT_1U << regno ; } } if ( sa_mask || alpha_ra_ever_killed ( ) ) sa_mask |= HOST_WIDE_INT_1U << REG_RA ; } sa_size = popcount_hwi ( sa_mask ) ; frame_size = get_frame_size ( ) ; if ( TARGET_ABI_OPEN_VMS ) { if ( ( sa_mask >> REG_RA ) & <NUM_LIT> || frame_pointer_needed ) alpha_procedure_type = PT_STACK ; else if ( frame_size != <NUM_LIT> ) alpha_procedure_type = PT_REGISTER ; else alpha_procedure_type = PT_NULL ; if ( alpha_procedure_type == PT_STACK ) sa_size -= <NUM_LIT> ; vms_base_regno = ( frame_pointer_needed || cfun -> has_nonlocal_label || alpha_procedure_type == PT_STACK || crtl -> outgoing_args_size ) ? REG_PV : HARD_FRAME_POINTER_REGNUM ; vms_save_fp_regno = - <NUM_LIT> ; if ( vms_base_regno == HARD_FRAME_POINTER_REGNUM ) for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! fixed_regs [ i ] && call_used_or_fixed_reg_p ( i ) && ! df_regs_ever_live_p ( i ) ) { vms_save_fp_regno = i ; break ; } if ( ( vms_save_fp_regno == - <NUM_LIT> && alpha_procedure_type == PT_REGISTER ) || cfun -> machine -> uses_condition_handler ) vms_base_regno = REG_PV , alpha_procedure_type = PT_STACK ; else if ( alpha_procedure_type == PT_NULL ) vms_base_regno = REG_PV ; vms_unwind_regno = ( vms_base_regno == REG_PV ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; if ( alpha_procedure_type == PT_STACK ) sa_size += <NUM_LIT> + cfun -> machine -> uses_condition_handler ; } else { if ( sa_size & <NUM_LIT> ) sa_size ++ ; } sa_size *= <NUM_LIT> ; if ( TARGET_ABI_OPEN_VMS ) frame_size = ALPHA_ROUND ( sa_size + ( alpha_procedure_type == PT_STACK ? <NUM_LIT> : <NUM_LIT> ) + frame_size + crtl -> args . pretend_args_size ) ; else frame_size = ( ALPHA_ROUND ( crtl -> outgoing_args_size ) + sa_size + ALPHA_ROUND ( frame_size + crtl -> args . pretend_args_size ) ) ; cfun -> machine -> sa_mask = sa_mask ; cfun -> machine ->


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Index ) ; MachineJumpTableInfo * MJTI = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) ; const auto & MBBs = MJTI -> getJumpTables ( ) [ JT -> getIndex ( ) ] . MBBs ; for ( auto MBB : MBBs ) Ops . push_back ( DAG


<s> for ( const auto & F : Forwards ) { Register ForwardedReg = F . PReg ; if ( any_of ( MIB -> uses ( ) , [ & ForwardedReg , & TRI ] ( const MachineOperand & Use ) { if ( ! Use . isReg ( ) ) return false ; return TRI -> regsOverlap ( Use . getReg ( ) , ForwardedReg ) ; } ) ) continue ; MIRBuilder . buildCopy ( ForwardedReg , Register ( F . VReg ) ) ; MIB . addReg ( ForwardedReg , RegState :: Implicit ) ; } } if ( ! IsSibCall ) { MIB -> getOperand ( <NUM_LIT> ) . setImm ( FPDiff ) ; CallSeqStart . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; MF . getFrameInfo ( ) .


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || Subtarget . hasBWI ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; if ( InVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; MVT ExtVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( )

) ExtVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ;


<s> static bool MCLDEmulate<ISA_LIT>ELF ( LinkerScript & pScript , LinkerConfig & pConfig ) { if ( ! MCLDEmulateELF ( pScript , pConfig ) ) return false ; pConfig . targets ( ) . setEndian ( TargetOptions :: Little ) ; pConfig . targets ( ) . setBitClass ( <NUM_LIT> ) ; pConfig . attribute ( ) . constraint ( ) . enableWholeArchive ( ) ; pConfig . attribute ( ) . constraint ( ) . enableAsNeeded ( ) ; pConfig . attribute ( ) . constraint ( ) . setSharedSystem ( ) ; pConfig . attribute ( ) . predefined ( ) . unsetWholeArchive ( ) ; pConfig . attribute ( ) . predefined ( ) . unsetAsNeeded ( ) ; pConfig . attribute ( ) . predefined ( ) . setDynamic


<s> if ( ! IsTailPredicationLegal ( ) ) return IsDo ? <STR_LIT> : <STR_LIT> ; return VCTPOpcodeToLSTP ( VCTPs . back ( ) ->


<s> addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget -> is64Bit ( ) ) return LowerFormalArguments_64 ( Chain , CallConv

, IsVarArg , Ins , DL , DAG , InVals ) ;


<s> std :: string ToYamlString ; if ( Metadata :: toYamlString ( FromYamlString , ToYamlString ) ) { errs ( ) << <STR_LIT> ; return ; } errs ( ) << ( YamlString == ToYamlString ? <STR_LIT> : <STR_LIT> ) << '\n' ; if ( YamlString != ToYamlString ) { errs ( ) << <STR_LIT> << YamlString << '\n' << <STR_LIT> << ToYamlString


<s> LiveIntervals & LIS = getAnalysis < LiveIntervals > ( ) ; for ( MachineBasicBlock & MBB : MF ) { for ( auto MII = MBB . rbegin ( ) ; MII != MBB . rend ( ) ; ++ MII ) { MachineInstr * Insert = & * MII ; if ( Insert -> getOpcode ( ) == TargetOpcode :: PHI ) break ; if ( Insert -> getOpcode ( ) == TargetOpcode :: INLINEASM ) break ; bool AnyStackified = false ; for ( MachineOperand & Op : reverse ( Insert -> uses ( ) ) ) { if ( ! Op . isReg ( ) || Op . isImplicit ( ) || ! Op . isUse ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ; if ( ! Def ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: INLINEASM ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: PHI ) continue ; if ( Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> ) continue ; if ( ! MRI . hasOneUse ( Reg ) ) continue ; if ( Def -> getParent ( ) != & MBB ) continue ; if ( ! IsSafeToMove ( Def , Insert , AA , LIS , MRI ) ) continue ; Changed = true ; AnyStackified = true ; MBB . splice ( Insert , & MBB , Def ) ; LIS . handleMove ( Def ) ; MFI . stackifyVReg ( Reg ) ; ImposeStackOrdering ( Def ) ; Insert = Def ; } if ( AnyStackified ) ImposeStackOrdering ( & * MII ) ; } } if ( Changed ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) MBB . addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > Stack ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { for ( MachineOperand & MO : reverse ( MI . explicit_operands ( ) ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned VReg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VReg ) ) continue ; if ( MFI . isVRegStackified ( VReg ) ) { if ( MO . isDef ( ) ) Stack . push_back ( VReg ) ; else assert ( Stack . pop_back_val ( ) == VReg ) ; } } } assert ( Stack . empty


<s> MemOp = DAG . getMemcpy ( Chain , dl , PtrOff , Arg , SizeNode , Flags . getByValAlign ( ) , false , true , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; } else { MemOp = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } MemOpChains . push_back ( MemOp ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass

[ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;


<s> result = arm_rtx_costs_internal ( x , ( enum rtx_code ) code , ( enum rtx_code ) outer_code , current_tune -> insn_extra_cost , total , speed ) ; if ( dump_file && (


<s> if ( load_p ) { reg1 = operands [ <NUM_LIT> ] ; reg2 = operands [ <NUM_LIT> ] ; mem1 = operands [ <NUM_LIT> ] ; mem2 = operands [ <NUM_LIT> ] ; } else { reg1 = operands [ <NUM_LIT> ] ; reg2 = operands [ <NUM_LIT> ] ; mem1 = operands [ <NUM_LIT> ] ; mem2 = operands [ <NUM_LIT> ] ; } if ( loongarch_address_insns ( XEXP ( mem1 , <NUM_LIT> ) , mode , false ) == <NUM_LIT> || loongarch_address_insns ( XEXP ( mem2 , <NUM_LIT> ) , mode , false ) == <NUM_LIT> ) return false ; loongarch_split_plus ( XEXP ( mem1 , <NUM_LIT> ) , & base1 , & offset1 ) ; loongarch_split_plus ( XEXP ( mem2 , <NUM_LIT> ) , & base2 , & offset2 ) ; if ( ! REG_P ( base1 ) || ! rtx_equal_p ( base1 , base2 ) ) return false ; if ( load_p && ( REGNO ( reg1 ) == REGNO ( base1 ) || ( REGNO ( reg2 ) == REGNO ( base1 ) ) ) ) return false ; if ( load_p && REGNO ( reg1 ) == REGNO ( reg2 ) ) return false ; rc1 = REGNO_REG_CLASS ( REGNO ( reg1 ) ) ; rc2 = REGNO_REG_CLASS ( REGNO ( reg2 ) ) ; if ( rc1 != rc2 && ! reg_class_subset_p ( rc1 , rc2 ) && ! reg_class_subset_p ( rc2 , rc1 ) ) return false ; if ( abs ( offset1 - offset2 ) != GET_MODE_SIZE ( mode ) ) return false ; return


<s> MCELFStreamer :: emitValueImpl ( Value , Size ,


<s> bool equal_nonrecursive ( stdict ) const { return


<s> case CallingConv :: Tail : case CallingConv :: Swift : case CallingConv :: SwiftTail : case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: Intel_OCL_BI : return isTargetWin64 ( ) ; case CallingConv :: Win64 : return true ; case CallingConv :: <ISA_LIT>_64_SysV


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( <ISA_LIT>TargetMachine & TM ) : TargetLowering ( TM , new <ISA_LIT>TargetObjectFile ( ) ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setIntDivIsCheap ( false ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedLoadAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setIndexedStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) .

addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> const <ISA_LIT>BaseTargetMachine & <ISA_LIT>_TM = static_cast < const <ISA_LIT>BaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = <ISA_LIT>_TM . TargetABI == <ISA_LIT>BaseTargetMachine :: <STR_LIT> ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM


<s> Reserved . set ( <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; unsigned MaxWorkGroupSGPRCount = getMaxWorkGroupSGPRCount ( MF ) ; unsigned MaxWorkGroupVGPRCount = getMaxWorkGroupVGPRCount ( MF ) ; unsigned NumSGPRs = <STR_LIT> . getNumRegs ( ) ; unsigned NumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxWorkGroupSGPRCount ; i < NumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( unsigned i = MaxWorkGroupVGPRCount ; i < NumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } const <ISA_LIT>Subtarget & ST = MF .

getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> if ( flag_pic && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_LOAD_SDATA && XEXP ( x , <NUM_LIT> ) == pic_offset_table_rtx && sdata_symbolic_operand ( XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) , SImode ) ) return ! no_large_offset && size <= <NUM_LIT> ; if ( flag_pic == <NUM_LIT> && mode == Pmode && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_LOAD_GOT && XEXP ( x , <NUM_LIT> ) == pic_offset_table_rtx && ( GET_CODE ( XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) == LABEL_REF ) ) return ! no_large_offset ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return false ; off = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; size1 = size ; if ( size == <NUM_LIT> * UNITS_PER_WORD && ! TARGET_STDW ) size = UNITS_PER_WORD ; if ( ( ( HOST_WIDE_INT ) size1 - <NUM_LIT> ) & off


<s> for ( unsigned i = <NUM_LIT> ; i < P -> getNumOperands ( ) ; ++ i ) Q -> addIncoming ( Zero , P -> getIncomingBlock ( i ) ) ; return Q ; } auto * A = dyn_cast < Argument > ( V ) ; auto * I = dyn_cast < Instruction > ( V ) ; assert ( ( A || I ) && <STR_LIT> ) ; auto InstPt = A ? & * A -> getParent ( ) -> getEntryBlock ( ) . begin ( ) : I -> getNextNode ( ) ; return new ZExtInst ( V , IntTy , <STR_LIT> , InstPt


<s> MCSection * getHSADataGlobalAgentSection ( MCContext & Ctx ) { return Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF

:: SHF_WRITE | ELF :: SHF_<ISA_LIT>_HSA_GLOBAL | ELF :: SHF_<ISA_LIT>_HSA_AGENT ) ;


<s> reportError ( I . getLoc ( ) , Twine ( <STR_LIT> ) + ( Inner ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + <STR_LIT> + <STR_LIT> + Twine ( RI . getName ( <STR_LIT> ) ) + <STR_LIT> ) ; return false


<s> FunctionPass * llvm :: create<ISA_LIT>FixupBWInsts


<s> op0 = XEXP ( x , <NUM_LIT> ) ; op1 = XEXP ( x , <NUM_LIT> ) ; if ( nios2_valid_addr_offset_p ( op1 ) ) return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , op0 ) , copy_rtx ( op1 ) ) ; else if ( nios2_symbolic_constant_p ( op1 ) ) { if ( nios2_large_constant_allowed ( ) ) return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , op0 ) , copy_rtx ( op1 ) ) ; else return nios2_split_plus_large_constant ( op0 , op1 ) ; } else if ( GET_CODE ( op1 ) == CONST ) { rtx unspec ,


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo )


<s> return ( __m512i ) __builtin_ia32_expandloaddi512_mask ( ( const __v8di * ) __P , ( __v8di


<s> const <ISA_LIT>Subtarget * getST ( ) const


<s> void <ISA_LIT>AsmPrinter :: EmitProgramInfo<ISA_LIT> ( const MachineFunction & MF ) { unsigned MaxGPR = <NUM_LIT> ; bool killPixel = false ; const <ISA_LIT>Subtarget & STM = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RI = STM . getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) killPixel = true ; unsigned numOperands = MI . getNumOperands ( ) ; for ( unsigned op_idx = <NUM_LIT> ; op_idx < numOperands ; op_idx ++ ) { const MachineOperand & MO = MI . getOperand ( op_idx ) ; if ( ! MO . isReg ( ) ) continue ; unsigned HWReg = RI -> getEncodingValue ( MO . getReg ( ) ) & <NUM_LIT> ; if ( HWReg > <NUM_LIT> ) continue ; MaxGPR = std :: max ( MaxGPR , HWReg ) ; } } } unsigned RsrcReg ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: EVERGREEN ) { switch ( MF . getFunction ( ) -> getCallingConv ( ) ) { default : LLVM_FALLTHROUGH ; case CallingConv :: <ISA_LIT>_CS : RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS ; break ; case CallingConv :: <ISA_LIT>_GS : RsrcReg = R_028878_SQ_PGM_RESOURCES_GS ; break ; case CallingConv :: <ISA_LIT>_PS : RsrcReg = R_028844_SQ_PGM_RESOURCES_PS ; break ; case CallingConv :: <ISA_LIT>_VS : RsrcReg = R_028860_SQ_PGM_RESOURCES_VS ;


<s> bool <ISA_LIT>TargetLowering :: supportSwiftError ( )


<s> unsigned <ISA_LIT>MachineFunctionInfo :: addFlatScratchInit ( const <ISA_LIT>RegisterInfo & TRI ) { ArgInfo . FlatScratchInit = ArgDescriptor :: createRegister ( TRI . getMatchingSuperReg ( getNextUserSGPR ( ) , <STR_LIT> , & <STR_LIT> ) ) ; NumUserSGPRs +=


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { auto & <ISA_LIT>Target = getThe<ISA_LIT>Target ( ) ; TargetRegistry :: RegisterMCAsmBackend ( <ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmInfo ( <ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( <ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( <ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( <ISA_LIT>Target , createELFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( <ISA_LIT>Target , create<ISA_LIT>InstrAnalysis


<s> gcc_assert ( ! VECTOR_MODE_P ( mode ) ) ; vmode = aarch64_simd_container_mode (


<s> unsigned <ISA_LIT>InstrInfo :: buildExtractSubReg ( MachineBasicBlock :: iterator MI , MachineRegisterInfo & MRI , MachineOperand & SuperReg , const TargetRegisterClass * SuperRC , unsigned SubIdx , const TargetRegisterClass * SubRC ) const { assert ( SuperReg . isReg ( ) ) ; unsigned NewSuperReg = MRI . createVirtualRegister ( SuperRC ) ; unsigned SubReg = MRI . createVirtualRegister (


<s> int shift_adv ; int shift = <NUM_LIT> ; int nelem ; switch ( GET_MODE ( op ) ) { case E_V2HImode : mask = <NUM_LIT> ; shift_adv = <NUM_LIT> ; nelem = <NUM_LIT> ; break ; case E_V4QImode : mask = <NUM_LIT> ; shift_adv = <NUM_LIT> ; nelem = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_BIG_ENDIAN ) { for ( i = <NUM_LIT> ; i < nelem ; ++ i ) { HOST_WIDE_INT val = XINT ( XVECEXP ( op , <NUM_LIT> , nelem - i - <NUM_LIT> ) , <NUM_LIT> ) ; hwint |= ( val & mask ) << shift ; shift = shift +


<s> } if ( const InsertElementInst * IE = dyn_cast < InsertElementInst > ( U ) ) { ConstantInt * CI = dyn_cast < ConstantInt > ( IE -> getOperand ( <NUM_LIT> ) ) ; unsigned Idx = - <NUM_LIT> ; if ( CI ) Idx = CI -> getZExtValue ( ) ; return getVectorInstrCost ( IE -> getOpcode ( ) , IE -> getType ( ) , Idx ) ; } if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( U ) ) { SmallVector < Value * , <NUM_LIT> > Args ( II -> arg_operands ( ) ) ; FastMathFlags FMF ; if ( auto * FPMO = dyn_cast < FPMathOperator > ( II ) ) FMF = FPMO -> getFastMathFlags ( ) ; return getIntrinsicInstrCost ( II -> getIntrinsicID ( ) , II -> getType ( ) , Args ,


<s> exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest )

. addReg ( incr ) . addImm ( <NUM_LIT> ) ;


<s> case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op


<s> bool <ISA_LIT>ompactDAGToDAGISel :: SelectADDRlir ( SDValue Addr , SDValue & Offset , SDValue & R1 ) { return


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , getSetCCResultType ( Ty ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand (

<NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; TII . adjustStackPtr ( <STR_LIT> , Amount , MBB , I ) ; } MBB . erase ( I )


<s> void addFGR64AsmRegOperands ( MCInst & Inst , unsigned N )


<s> MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ?


<s> remove_insn ( trailing_nott ( ) ) ; return true


<s> void setCalleeSaveBaseToFrameRecordOffset ( int


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned R12 = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } unsigned Opc = ( CallConv == CallingConv :: <ISA_LIT>_INTR ? <STR_LIT> : <STR_LIT> ) ; RetOps [ <NUM_LIT> ]


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetFrameLowering * TFI =


<s> return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : if ( VT == <STR_LIT> ) { ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> ) ; return ReplaceNode ( Node , New . getNode ( ) ) ; } if ( ConstNode -> isAllOnesValue


<s> unsigned <ISA_LIT>FastISel :: emitLogicalOp ( unsigned ISDOpc , MVT RetVT , const Value * LHS , const Value * RHS ) { if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; unsigned Opc ; switch ( ISDOpc ) { case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return <NUM_LIT> ; unsigned RHSReg ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) )

RHSReg = materializeInt ( C , <STR_LIT> ) ;


<s> return isImm ( ) && dyn_cast < MCConstantExpr >


<s> T . setSUnit ( Src ) ; auto F = std :: find ( Dst -> Preds . begin ( ) , Dst -> Preds . end ( ) , T ) ; assert ( F != Dst -> Preds


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { if ( TT . getArch ( ) == Triple :: r600 ) return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU


<s> for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } MachineIRBuilder MIRBuilder ( I ) ; Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIRBuilder ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg (

) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ;


<s> MachineInstr * MI = T2JumpTables [ i ] ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; int DTNumber = MBB -> getNumber


<s> return ( vector signed short ) __builtin_altivec_vmhaddshs ( ( vector signed short ) a1 , ( vector signed short )


<s> unsigned DMaskIdx = <STR_LIT> ( CI . I -> getOpcode ( ) , <STR_LIT> :: dmask ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) ; for ( unsigned I = <NUM_LIT> , E = ( * CI . I ) . getNumOperands ( ) ; I != E ; ++ I ) { if ( I == DMaskIdx ) MIB . addImm ( MergedDMask ) ; else MIB . add ( ( * CI . I ) . getOperand ( I ) ) ; } assert ( CI . I -> hasOneMemOperand ( ) && CI . Paired -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * CI . Paired -> memoperands_begin ( ) ; MachineInstr * New = MIB . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) ,


<s> LLVMContext & Ctx = IRB . getContext ( ) ; Type * EltTy = VecTy -> getElementType ( ) ; if ( EltTy -> isPointerTy ( ) ) { uint32_t EltSize = DL -> getTypeSizeInBits ( EltTy ) ; auto * NewTy = FixedVectorType :: get ( IntegerType :: get ( Ctx , EltSize ) , VecTy -> getNumElements ( ) ) ; V = IRB . CreatePointerCast ( V , NewTy ) ; } } return IRB . CreateBitOrPointerCast ( V , IRB . getIntNTy ( DL -> getTypeStoreSize ( V -> getType ( ) ) *


<s> if ( isa < ConstantPointerNull > ( Op1 ) ) Op1 = Constant :: getNullValue ( TD . getIntPtrType ( Op0 -> getContext ( ) ) ) ; if ( const ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( MBB , DL , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C


<s> if ( ! Cond [ <NUM_LIT> ] . isReg ( ) ) return ; Register CondReg = Cond [ <NUM_LIT> ]


<s> bool supportsFMA ( ) const { return SupportsFMA


<s> Value * <ISA_LIT>IREmitter :: visitVLD3DUP_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc


<s> void StackFixup :: removeAllElem ( Stack & stack , const StackVreg & vreg


<s> void setBasePointerSaveIndex ( int Idx ) { BasePointerSaveIndex =


<s> MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; if ( I == B ) return false ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; } if ( I == B ) return false ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; CmpInstr -> eraseFromParent (


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O <<


<s> case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent (


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler =


<s> if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( )

, Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ;


<s> static SDValue LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG , const TargetLowering & TLI ) { EVT VT = Op . getValueType ( ) ; SDValue lhs = Op . getOperand ( <NUM_LIT> ) ; SDValue rhs = Op . getOperand ( <NUM_LIT> ) ; SDValue trueval = Op . getOperand ( <NUM_LIT> ) ; SDValue falseval = Op . getOperand ( <NUM_LIT> ) ; SDValue condition = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue compare = DAG . getNode ( <STR_LIT> , dl , TLI . getSetCCResultType ( Op . getValueType ( ) ) , lhs , rhs , condition ) ; return DAG . getNode ( <STR_LIT> , dl , VT , falseval ,


<s> if ( ! OpInfo || UseOpIdx >= Desc . getNumOperands ( ) ) return false ; uint8_t OpTy = OpInfo [ UseOpIdx ] . OperandType ; if ( ( OpTy < <STR_LIT> || OpTy > <STR_LIT> ) && ( OpTy < <STR_LIT> || OpTy > <STR_LIT> ) ) return false ; if ( OpToFold . isImm ( ) && TII -> isInlineConstant ( OpToFold , OpTy ) && TII -> isOperandLegal ( * UseMI , UseOpIdx , & OpToFold ) ) { UseMI -> getOperand ( UseOpIdx ) . ChangeToImmediate ( OpToFold . getImm ( ) ) ; return true ; } if ( ! OpToFold . isReg ( ) ) return false ; Register UseReg = OpToFold . getReg ( ) ; if ( ! UseReg . isVirtual ( ) ) return false ; if ( isUseMIInFoldList ( FoldList , UseMI ) ) return false ; MachineRegisterInfo & MRI = UseMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * Def = MRI . getVRegDef ( UseReg ) ; MachineOperand & UseOp = UseMI -> getOperand ( UseOpIdx ) ; if ( ! UseOp . getSubReg ( ) && Def && TII -> isFoldableCopy ( * Def ) ) { MachineOperand & DefOp = Def -> getOperand ( <NUM_LIT> ) ; if ( DefOp . isImm ( ) && TII -> isInlineConstant ( DefOp , OpTy ) && TII -> isOperandLegal ( * UseMI , UseOpIdx , & DefOp ) ) { UseMI -> getOperand ( UseOpIdx ) . ChangeToImmediate ( DefOp . getImm ( ) ) ; return true ; } } SmallVector < std :: pair < MachineOperand * , unsigned > , <NUM_LIT> > Defs ; if ( ! getRegSeqInit ( Defs , UseReg , OpTy , TII , MRI ) ) return false ; int32_t Imm ; for ( unsigned I = <NUM_LIT> , E = Defs . size ( ) ; I != E ; ++ I ) { const MachineOperand * Op = Defs [ I ] . first ; if ( ! Op -> isImm ( ) ) return false ; auto SubImm = Op ->


<s> if ( ! opnd . isReg ( ) ) return false ; MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef ) return false ; if ( PhiDef -> isPHI ( ) ) { if ( PhiInsns . find ( PhiDef ) != PhiInsns . end ( )


<s> dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ; if ( rem > <NUM_LIT> ) { if ( CONST_INT_P ( value_rtx ) ) { const unsigned HOST_WIDE_INT value = UINTVAL ( value_rtx ) & <NUM_LIT> ; emit_move_insn ( adjust_address_nv ( dst , HImode , bytes ) , gen_int_mode ( ( value << <NUM_LIT> ) | value , HImode ) ) ; } else { rtx temp = convert_to_mode ( QImode , value_rtx , <NUM_LIT> ) ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , temp ) ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes +


<s> void <ISA_LIT>PassConfig :: addOptimizedRegAlloc ( FunctionPass * RegAllocPass ) { disablePass ( & RegisterCoalescerID ) ; TargetPassConfig :: addOptimizedRegAlloc ( RegAllocPass


<s> unsigned getFlatAddressSpace ( ) const { if ( IsGraphicsShader ) return - <NUM_LIT> ; return ST -> hasFlatAddressSpace ( ) ?


<s> if ( callprototype ) s << <STR_LIT> ; else s << <STR_LIT> ; s << <STR_LIT> ; } s << name ; int nargs = XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ; if ( nargs > <NUM_LIT> ) { s << <STR_LIT> ; for ( int i = <NUM_LIT> ; i < nargs ; i ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , i + <NUM_LIT> ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; int count = maybe_split_mode ( & mode ) ; while ( count -- > <NUM_LIT> ) { s << <STR_LIT> ; s << nvptx_ptx_type_from_mode ( mode , false ) ; s << <STR_LIT> ; if ( callprototype ) s << <STR_LIT> ; else s << <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: ParseAMDKernelCodeTValue ( StringRef ID , amd_kernel_code_t & Header ) { SmallString < <NUM_LIT> >


<s> if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_SHORT ; else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) call_type = CALL_LONG ; if ( call_type == CALL_LONG && ( flag_pic || ! TREE_ASM_WRITTEN ( decl ) ) ) return false ; if ( TARGET_INTERWORK && TREE_PUBLIC ( decl ) && !

TREE_ASM_WRITTEN ( decl ) ) return false ;


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getConstant


<s> bool isImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , Offset , isImmutable ) ; return DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , Offset , isImmutable ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI . setObjectZExt ( FI , true ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { MFI . setObjectSExt ( FI , true


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ; N0 = DAG . getNode ( <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( flag_omit_frame_pointer ) flag_omit_leaf_frame_pointer = false ; else if ( flag_omit_leaf_frame_pointer ) flag_omit_frame_pointer =


<s> void addITMaskOperands ( MCInst & Inst


<s> if ( CALL_P ( insn ) ) return <STR_LIT> ; if ( reg_mentioned_p ( gen_rtx_REG ( SImode , LR_REGNUM


<s> static bool isFPS16Immediate ( ConstantFPSDNode * FPN , short & Imm ) { EVT vt = FPN -> getValueType ( <NUM_LIT> ) ; if ( vt


<s> default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseAnyRegister ( Operands ) != MatchOperand_NoMatch ) return false ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E , * this ) ) ; return false ; } case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: Tilde : case AsmToken :: String : { DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; return ResTy != MatchOperand_Success ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return


<s> if ( Out . VT . isVector ( ) ) { MVT VT = Out . VT . getVectorElementType ( ) ; <STR_LIT> NewOut = Out ; NewOut . Flags . setSplit ( ) ; NewOut . VT = VT ; unsigned NumElements = Out . ArgVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { SDValue Elem = DAG . getNode ( <STR_LIT> , DL , VT , OutVals [ i ] , DAG . getConstant ( j , DL , <STR_LIT> ) ) ; SplitVals . push_back ( Elem ) ; Splits . push_back ( NewOut ) ; NewOut . PartOffset += NewOut . VT . getStoreSize ( ) ; } } else { SplitVals . push_back ( OutVals [ i ] ) ; Splits . push_back ( Out ) ; } } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturn ( CCInfo , Splits ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = SplitVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt


<s> report_fatal_error ( <STR_LIT> ) ; return true ; } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; bool Result = AsmPrinter :: doInitialization ( M ) ; emitHeader ( M , OS1 , * STI ) ; OutStreamer -> emitRawText ( OS1 . str ( )


<s> ED . OpNum = OpNum ; bool IsLoad = MI . mayLoad ( ) ; bool IsStore = MI . mayStore ( ) ; for ( MachineOperand & Op : MI . operands ( ) ) if ( Op . isFI ( ) && Op . getIndex ( ) < <NUM_LIT> ) return ; if ( IsLoad || IsStore ) { unsigned AM = HII -> getAddrMode ( MI ) ; switch ( AM ) { case <STR_LIT> : break ; case <STR_LIT> : ED . Rd = MI . getOperand ( OpNum - <NUM_LIT> ) ; ED . IsDef = true ; break ; case <STR_LIT> : if ( ! isStoreImmediate ( Opc ) ) ED . Expr . Rs = MI . getOperand ( OpNum - <NUM_LIT> ) ; break ; case <STR_LIT> : ED . Expr . Rs = MI . getOperand ( OpNum - <NUM_LIT> ) ; ED . Expr . S = MI . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( Opc ) { case <STR_LIT> : ED . Rd = MI . getOperand ( <NUM_LIT> ) ; ED . IsDef = true ; break ; case <STR_LIT> : case <STR_LIT> : ED . Rd = { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> } ; ED . IsDef = true ; break ; case <STR_LIT> : ED . Rd = { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> } ; ED . IsDef = true ; break ; case


<s> unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; switch ( Opcode


<s> DecodeStatus S = MCDisassembler :: Success ; if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; Check ( S , DecodeGPRwithZRRegisterClass ( Inst , RegNo , Address , Decoder ) ) ; return S


<s> unsigned Op = Win64EH :: UOP_AllocSmall ; if ( ! Wide ) { if ( Size / <NUM_LIT> > <NUM_LIT> ) Op = Win64EH :: UOP_AllocHuge ; else if ( Size / <NUM_LIT> > <NUM_LIT> ) Op = Win64EH :: UOP_AllocLarge ; } else { Op = Win64EH :: UOP_WideAllocMedium ; if ( Size / <NUM_LIT> > <NUM_LIT> ) Op = Win64EH ::


<s> if ( Priv -> UseLocs . count ( MBB ) ) { for ( auto ul : Priv -> UseLocs [ MBB ] ) { if ( ul . second . spill . first || ul . second . load . first ) { return true


<s> SmallVectorImpl < MachineInstr * > & getUseDefs


<s> void write ( unsigned int i ) { std :: stringstream s ; s << MF -> getFunction ( ) . getName ( ) . str ( ) << <STR_LIT> << i << <STR_LIT> ; std :: error_code err ; raw_fd_ostream f ( s . str ( ) . c_str ( ) , err ) ; WriteGraph ( f ,


<s> int <ISA_LIT>CFGStructurizer :: countActiveBlock ( MBBVector :: const_iterator It , MBBVector :: const_iterator E ) const { int Count =


<s> if ( ! Def ) return nullptr ; switch ( Def -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return nullptr ; case <STR_LIT> : case <STR_LIT> : { auto & Op1 = Def -> getOperand ( <NUM_LIT> ) ; if ( Op1 . isImm ( ) ) return &


<s> MachinePointerInfo <ISA_LIT>MachineFunctionInfo :: callPtrInfo ( const GlobalValue


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseAccessReg ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , nullptr ) ) return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: createAccessReg ( Reg . Num ,


<s> StringRef sbss [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto ELFSymbol = cast < MCSymbolELF > ( Symbol ) ; if ( ! ELFSymbol -> isBindingSet ( ) ) { ELFSymbol -> setBinding ( ELF :: STB_GLOBAL ) ; ELFSymbol -> setExternal ( true ) ; } ELFSymbol -> setType ( ELF :: STT_OBJECT ) ; if ( ELFSymbol -> getBinding ( ) == ELF :: STB_LOCAL ) { StringRef SectionName = ( ( AccessSize == <NUM_LIT> ) || ( Size == <NUM_LIT> ) || ( Size > GPSize ) ) ? <STR_LIT> : sbss [ ( Log2_64 ( AccessSize ) ) ] ; MCSection * CrntSection = getCurrentSection ( ) . first ; MCSection * Section = getAssembler ( ) . getContext ( ) . getELFSection ( SectionName , ELF :: SHT_NOBITS , ELF


<s> MachineInstr * LoHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . addReg ( Addr . Base . LoReg , <NUM_LIT> , Addr . Base . LoSubReg ) . add ( OffsetLo ) . addImm ( <NUM_LIT> ) ; ( void ) LoHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; LoHalf -> dump ( ) ; ) ; MachineInstr * HiHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . addReg ( Addr . Base . HiReg , <NUM_LIT> , Addr . Base . HiSubReg ) . add ( OffsetHi ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; ( void ) HiHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; HiHalf -> dump ( ) ; ) ; Register FullDestReg = MRI -> createVirtualRegister ( & <STR_LIT>


<s> Op = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ->

addAddrMode2Operands ( Inst , <NUM_LIT> ) ;


<s> if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; unsigned RegNum = Tok . getIntVal ( ) ; if ( RegNum != <NUM_LIT> ) return MatchOperand_ParseFail ; <ISA_LIT>Operand * op = <STR_LIT> ( <STR_LIT> , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( <STR_LIT> ) ; Operands . push_back


<s> } else if ( ! <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <ISA_LIT>Shuffler :: SHUFFLE_SUCCESS ; } bool doneShuffling = false ; unsigned shuffleError ; while ( possibleDuplexes . size ( ) > <NUM_LIT> && ( ! doneShuffling ) ) { DuplexCandidate duplexToTry = possibleDuplexes . pop_back_val ( ) ; MCInst Attempt ( MCB ) ; <ISA_LIT>MCInstrInfo :: replaceDuplex ( Context , Attempt , duplexToTry ) ; <ISA_LIT>MCShuffler MCS ( MCII , STI , Attempt


<s> return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return &


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( DestReg == SrcReg && Val == <NUM_LIT> ) return ; if ( DestReg != SrcReg ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; if ( isInt < <NUM_LIT> > ( Val ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( Val ) . setMIFlag ( Flag ) ; } else if ( isInt < <NUM_LIT> > ( Val ) ) { unsigned Opc = <STR_LIT>


<s> const auto & TRI = getRegisterInfo ( ) ; const auto * RCDst = TRI . getMaximalPhysRegClass ( Dst , MVTDst ) ; const auto * RCSrc = TRI . getMaximalPhysRegClass ( Src , MVTSrc ) ; assert ( RCDst && RCSrc && <STR_LIT> ) ; assert ( RCDst != RCSrc && <STR_LIT> ) ; unsigned SSrc = RI . getMatchingMegaReg ( Src , RCDst ) ; assert ( SSrc && <STR_LIT> ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; if ( Dst == SSrc ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB . getInstr ( ) << '\n' ) ; MIB -> eraseFromParent ( ) ; } else


<s> Addr = AddrDef -> Reg ; } else if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register SAddr = getSrcRegIgnoringCopies ( AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( SAddr && isSGPR ( SAddr ) ) { Register PtrBaseOffset = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register Off = matchZeroExtendFromS32 ( * MRI , PtrBaseOffset ) ) { Addr = SAddr ; VOffset = Off ; } } } } if ( isSGPR ( Addr ) ) { Opc = <STR_LIT> ( Opc ) ; if ( ! VOffset ) { VOffset = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , VOffset ) . addImm ( <NUM_LIT> ) ; } } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) ) . addReg ( Addr ) ; if ( isSGPR ( Addr ) ) MIB . addReg ( VOffset ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MachineMemOperand * LoadMMO = * MI . memoperands_begin ( ) ; MachinePointerInfo LoadPtrI = LoadMMO -> getPointerInfo ( ) ; LoadPtrI . Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachinePointerInfo StorePtrI = LoadPtrI ; LoadPtrI . AddrSpace = <ISA_LIT>AS :: GLOBAL_ADDRESS ; StorePtrI . AddrSpace = <ISA_LIT>AS :: LOCAL_ADDRESS ; auto F = LoadMMO -> getFlags ( ) & ~ ( MachineMemOperand :: MOStore | MachineMemOperand :: MOLoad ) ; LoadMMO = MF -> getMachineMemOperand ( LoadPtrI , F | MachineMemOperand :: MOLoad , Size , LoadMMO -> getBaseAlign ( ) ) ; MachineMemOperand * StoreMMO = MF -> getMachineMemOperand ( StorePtrI , F | MachineMemOperand :: MOStore

, sizeof ( int32_t ) , Align ( <NUM_LIT> ) ) ;


<s> StringRef str ( ) { return OS . str ( )


<s> CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; AllowAtInName = true ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; UseIntegratedAssembler = true ; PreserveAsmComments =


<s> return ggc_cleared_alloc < machine_function >


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getType ( ) == MachineOperand :: MO_Register && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { O << <STR_LIT> ; OutStreamer . AddBlankLine ( ) ; return ; } else if ( MI -> getOperand ( <NUM_LIT> ) . getType ( ) == MachineOperand :: MO_FPImmediate ) { if ( MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getType ( ) -> isFloatTy ( ) || MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getType ( ) -> isDoubleTy ( ) ) MI -> getOperand ( <NUM_LIT> ) . print ( O , & TM ) ; else { bool ignored ; APFloat APF = APFloat ( MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ) ; APF . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & ignored ) ; O << <STR_LIT> << APF . convertToDouble ( ) ; } } else printOperand ( MI , <NUM_LIT> ) ; } else { assert ( MI -> getOperand ( <NUM_LIT> ) . getType ( ) == MachineOperand :: MO_Register ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . getType ( ) == MachineOperand :: MO_Immediate ) ; O << '[' ; printOperand ( MI , <NUM_LIT> ) ; O << '+' ; printOperand ( MI , <NUM_LIT> ) ; O << ']' ; } O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> ) ; OutStreamer . AddBlankLine ( ) ; return ; } case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; const char * Prefix = MAI -> getPrivateGlobalPrefix ( ) ; MCSymbol * DotSym = OutContext . GetOrCreateSymbol ( Twine ( Prefix ) +

<STR_LIT> + Twine ( getFunctionNumber ( ) ) ) ;


<s> SDLoc dl ( Op ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; <STR_LIT> Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> isSwift ( ) && Ord == Release ) { Domain =


<s> static void rs6000_print_builtin_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , <STR_LIT> , &


<s> return ( t == float128_type_node || ( t && t == float128t_type_node ) || ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t ==


<s> case <STR_LIT> : { int Idx = Instr . findRegisterUseOperandIdx ( <STR_LIT> ) ; assert ( Idx >= <NUM_LIT> ) ; return static_cast < <STR_LIT> > ( Instr . getOperand ( Idx - <NUM_LIT> ) . getImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int Idx = Instr . findRegisterUseOperandIdx ( <STR_LIT> ) ; assert ( Idx >= <NUM_LIT> ) ; return static_cast < <STR_LIT> > ( Instr . getOperand ( Idx - <NUM_LIT>


<s> SDValue GA = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( CP ) , GA ) ; } SDValue CPIHi = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOHiFlag ) ; SDValue CPILo = DAG . getTargetConstantPool ( C , PtrVT , CP -> getAlignment ( ) , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( CPIHi , CPILo , IsPIC , DAG


<s> LatticeCell LS1 ; if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isBottom ( ) || LS1 . isProperty ( ) ) return false ; APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateSEXTi ( A , Width , Bits , XA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( XA ) ; Result . add ( C ) ; } return true


<s> if ( TARGET_LOONGSON_MMI && VECTOR_MODE_P ( mode ) ) return <NUM_LIT> ; return GET_MODE_BITSIZE ( mode


<s> if ( ArgFlags . isSecArgPass ( ) ) { if ( ArgFlags . isHva ( ) ) return CC_<ISA_LIT>_VectorCallAssignRegister ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; return true ; } if ( ! ( ValVT . isFloatingPoint ( ) || ( ValVT . isVector ( ) && ValVT . getSizeInBits ( ) >= <NUM_LIT> ) ) ) { if ( State . isAllocated ( <STR_LIT> ) ) { ( void ) State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ; } return false ; } if ( ! ArgFlags . isHva ( ) || ArgFlags . isHvaStart ( ) ) { ( void ) State . AllocateReg ( CC_<ISA_LIT>_64_VectorCallGetGPRs ( ) ) ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) { if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) State

. AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;


<s> break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; } break ; case 'a' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( <NUM_LIT> , nullptr ) ; case <NUM_LIT> : case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; return std :: make_pair ( <NUM_LIT> , RC ) ; } break ; } if ( RC && ( isTypeLegal ( VT ) || VT . SimpleTy == <STR_LIT> || VT . SimpleTy == <STR_LIT> || VT . SimpleTy == <STR_LIT> ) ) return std :: make_pair ( <NUM_LIT> , RC ) ; } if ( Constraint . size ( ) > <NUM_LIT> ) { if ( Constraint [ <NUM_LIT> ] == 'v' ) { RC = & <STR_LIT> ; } else if ( Constraint [ <NUM_LIT> ] == 's' ) { RC = & <STR_LIT> ; } else if ( Constraint [ <NUM_LIT> ] == 'a' ) { RC = & <STR_LIT> ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( <NUM_LIT> ) .


<s> case CortexA35 : break ; case CortexA53 : case CortexA55 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA65 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexR82 : case CortexX1 : case CortexX1C : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA510 : case CortexA710 : case CortexX2 : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; break ; case NeoverseN2 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case NeoverseV1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case Neoverse512TVB : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor =


<s> if ( TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return AS ; assert ( TargetRegisterInfo :: isPhysicalRegister ( RR . Reg ) ) ; unsigned R = RR . Reg ; if ( RR . Sub ) R = TRI . getSubReg ( RR . Reg , RR . Sub ) ; for ( MCRegAliasIterator AI ( R , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AS . push_back ( RegisterRef ( { * AI , <NUM_LIT> } ) ) ; return


<s> MachineInstr * AMDGPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return nullptr


<s> if ( ! matchShuffleWithSHUFPD ( VT , V1 , V2 , ForceV1Zero , ForceV2Zero , Immediate , Mask , Zeroable ) ) return SDValue ( ) ; if ( ForceV1Zero ) V1 = getZeroVector ( VT , Subtarget , DAG , DL ) ; if ( ForceV2Zero ) V2 = getZeroVector ( VT , Subtarget , DAG , DL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getTargetConstant ( Immediate


<s> cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Ins ) , DL , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT , OnesOrZeroesF ) ; SDValue ANDed = DAG . getNode ( <STR_LIT> , DL , IntVT , OnesOrZeroesI , DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ) ; SDValue OneBitOfTruth = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ANDed ) ; return OneBitOfTruth ; } } } } return SDValue ( )


<s> InsertedInstrs ++ ; } else { unsigned parentReg = parentPredRegs . count ( pred ) ? parentPredRegs [ pred ] : <STR_LIT> ; if ( predRegs [ pred ] != parentPredRegs [ pred ] ) { AddDefaultPred ( BuildMI ( * PrehdrMBB , PrehdrMBB -> end ( ) , DL , Pass . TII -> get ( <STR_LIT> )

, predRegs [ pred ] ) ) . addReg ( parentReg ) . addImm ( <NUM_LIT> ) ;


<s> if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new

<ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget , DAG ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBitfield64LSLOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return ( ( <NUM_LIT> - MO . getImm ( ) ) & <NUM_LIT> ) | ( <NUM_LIT>


<s> static DecodeStatus decodeMemoryOpValue ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; if ( Register > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register ] ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32


<s> return ( GV -> getValueType ( ) -> isFunctionTy ( ) || GV -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GV -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS || GV -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) .

shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( SplitVTs . size ( ) == <NUM_LIT> ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * SplitTy , DL ) ) , SplitTy , OrigArg . Flags , OrigArg . IsFixed } ) ; } for ( unsigned i = <NUM_LIT> ; i < Offsets . size ( ) ; ++ i ) PerformArgSplit ( SplitArgs [ FirstRegIdx +

i ] . Reg , Offsets [ i ] * <NUM_LIT> ) ;


<s> if ( RegName [ <NUM_LIT> ] == 's' ) { if ( RegName [ <NUM_LIT> ] == 'p' ) return RegName + <NUM_LIT> ; return RegName + <NUM_LIT> ; } return RegName +


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return


<s> void <ISA_LIT>AsmPrinter :: emitLinkageDirective ( const GlobalValue * V , raw_ostream & O ) { if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( V -> hasExternalLinkage ( ) ) { if ( isa < GlobalVariable > ( V ) ) { const GlobalVariable * GVar = cast < GlobalVariable > ( V ) ; if ( GVar ) { if ( GVar -> hasInitializer ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; } } else if ( V -> isDeclaration


<s> SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; Opcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , VT , ExOp ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) { unsigned NumVecs = VT . getSizeInBits ( ) / SplitSize ; unsigned NumSubElts = SplitSize / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; unsigned IROpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendVecSize ( DL , SrcVec , SplitSize ) ; SrcVec = DAG . getNode ( IROpc , DL , SubVT , SrcVec ) ; Opnds . push_back ( SrcVec ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Opnds ) ; } ; if ( ! Subtarget . hasAVX ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) return SplitAndExtendInReg ( <NUM_LIT> ) ; if ( ! Subtarget . useAVX512Regs ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) return SplitAndExtendInReg


<s> static SDValue PerformADDCombine ( SDNode * N , DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( VT == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ) if ( auto * C0 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) -> getOperand (

<NUM_LIT> ) , DCI . DAG . getTargetConstant ( * C0 -> getConstantIntValue ( ) , dl , <STR_LIT> ) ) ;


<s> state = alloca ( state_size ( ) ) ; state_reset ( state ) ; state_transition ( state , insn ) ; for ( unit = <NUM_LIT> ; unit < ARRAY_SIZE ( frv_unit_codes ) ; unit ++ ) if ( cpu_unit_reservation_p ( state , frv_unit_codes [ unit ] ) ) break ; gcc_assert ( unit != ARRAY_SIZE ( frv_unit_codes ) ) ; frv_type_to_unit [ type ]


<s> auto Reg = MO . getReg ( ) ; auto & LiveMask = LiveRegs [ Reg ] ; auto PrevMask = LiveMask ; LiveMask &= ~ getDefRegMask ( MO ) ; CurPressure . inc ( Reg , PrevMask , LiveMask , * MRI ) ; } for ( const auto & MO : MI . uses ( ) ) { if ( ! MO . isReg ( ) || ! MO . readsReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; auto Reg = MO . getReg ( ) ; auto & LiveMask = LiveRegs [ Reg ] ; auto PrevMask = LiveMask ; LiveMask |= getUsedRegMask ( MO ) ; CurPressure . inc ( Reg , PrevMask , LiveMask , * MRI ) ; } MaxPressure = max ( MaxPressure , CurPressure


<s> int ar6_reg_operand ( rtx op , enum machine_mode mode ) { return c4x_arn_reg_operand ( op , mode


<s> auto r = insn -> bytes ; uint64_t offset = insn -> readerCursor - insn -> startLocation ; if ( offset + sizeof ( T ) > r . size ( ) ) return true ; T ret =


<s> MachineLoop * LoopRep = MLI -> getLoopFor ( MBB ) ; while ( LoopRep && LoopRep -> getHeader ( ) == MBB ) { MachineBasicBlock * LoopLand = getLoopLandInfo ( LoopRep ) ; if ( ! LoopLand ) return true ; if ( ! isRetiredBlock ( LoopLand ) ) return true ; LoopRep = LoopRep -> getParentLoop


<s> return new <ISA_LIT>LoopRescheduling ( )


<s> static DecodeStatus DecodeFMOVLaneInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned IsToVec = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( IsToVec ) { DecodeVPR128RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Address , Decoder ) ; } else { DecodeGPR64RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeVPR128RegisterClass ( Inst , Rn , Address , Decoder ) ; } Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> LDSSize = YamlMFI . LDSSize ; GDSSize = YamlMFI . GDSSize ; DynLDSAlign = YamlMFI . DynLDSAlign ; HighBitsOf32BitAddress = YamlMFI . HighBitsOf32BitAddress ; Occupancy = YamlMFI . Occupancy ; IsEntryFunction = YamlMFI . IsEntryFunction ; NoSignedZerosFPMath = YamlMFI . NoSignedZerosFPMath ; MemoryBound = YamlMFI . MemoryBound ; WaveLimiter = YamlMFI . WaveLimiter ; HasSpilledSGPRs = YamlMFI . HasSpilledSGPRs ; HasSpilledVGPRs = YamlMFI . HasSpilledVGPRs ; BytesInStackArgArea = YamlMFI . BytesInStackArgArea ; ReturnsVoid = YamlMFI . ReturnsVoid ; if ( YamlMFI . ScavengeFI ) { auto FIOrErr = YamlMFI . ScavengeFI -> getFI ( MF . getFrameInfo ( ) ) ; if ( ! FIOrErr ) { const MemoryBuffer & Buffer = * PFS . SM -> getMemoryBuffer ( PFS . SM -> getMainFileID ( ) ) ; Error = SMDiagnostic ( * PFS . SM , SMLoc ( ) , Buffer . getBufferIdentifier ( ) , <NUM_LIT> , <NUM_LIT> , SourceMgr :: DK_Error , toString ( FIOrErr . takeError ( ) ) , <STR_LIT> , None , None ) ; SourceRange = YamlMFI . ScavengeFI -> SourceRange ; return true ; } ScavengeFI = * FIOrErr ; } else


<s> if ( dst_regnum == STACK_POINTER_REGNUM ) return ! TARGET_WINDOWED_ABI || ( mode == SImode && register_operand ( operands [ <NUM_LIT> ] , mode ) && ! ACC_REG_P ( xt_true_regnum ( operands [ <NUM_LIT> ] ) ) ) ; if ( ! ACC_REG_P ( dst_regnum )


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS


<s> } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } return


<s> if ( ! targetm . have_tls ) return false ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) x = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL


<s> static int32_t adjustDown ( int32_t V , uint8_t A , uint8_t O ) { assert ( isPowerOf2_32 (


<s> int <ISA_LIT>CFGStructurizer :: handleJumpintoIf ( MachineBasicBlock * HeadMBB , MachineBasicBlock * TrueMBB , MachineBasicBlock * FalseMBB ) { int Num = handleJumpintoIfImp ( HeadMBB , TrueMBB , FalseMBB ) ; if ( Num == <NUM_LIT> ) { DEBUG ( dbgs ( ) <<


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT>


<s> const AsmToken & Tok = getTok ( ) ; SMLoc S = getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned PStateImm = - <NUM_LIT> ; const auto * SVCR = <STR_LIT> ( Tok . getString


<s> unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; if ( HasStackObjects ) { unsigned ScratchWaveOffsetReg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_WAVE_BYTE_OFFSET ) ; Info . setScratchWaveOffsetReg ( ScratchWaveOffsetReg ) ; } else { unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } } if ( NeedSP ) { unsigned ReservedStackPtrOffsetReg = TRI . reservedStackPtrOffsetReg ( MF ) ; Info . setStackPtrOffsetReg ( ReservedStackPtrOffsetReg ) ; assert ( Info . getStackPtrOffsetReg ( ) != Info . getFrameOffsetReg ( ) ) ; assert ( ! TRI . isSubRegister ( Info . getScratchRSrcReg ( ) , Info


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return &


<s> <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int RASI = FI -> getReturnAddrSaveIndex ( ) ; if ( ! RASI ) { int LROffset = Subtarget . getFrameLowering ( ) -> getReturnSaveOffset ( ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , false ) ; FI -> setReturnAddrSaveIndex ( RASI


<s> return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction :: IntToPtr : { const DataLayout & DL = * TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , DL . getIntPtrType ( CV -> getType ( ) ) , false ) ; return lowerConstantForGV ( Op , ProcessingGeneric ) ; } case Instruction :: PtrToInt : { const DataLayout & DL = * TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = lowerConstantForGV ( Op , ProcessingGeneric ) ; if ( DL . getTypeAllocSize ( Ty ) == DL . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = DL . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: createAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : { const MCExpr * LHS = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; const MCExpr * RHS = lowerConstantForGV ( CE -> getOperand


<s> return ( __m128h ) __builtin_ia32_vfmulcsh_mask_round ( ( __v8hf ) __C , ( __v8hf )


<s> if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( *


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { if ( dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) || dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { return false ; } R1 = N . getOperand ( <NUM_LIT> ) ; R2 = N . getOperand ( <NUM_LIT> ) ; return true ; } return false


<s> __v2df c ; c = vec_sqrt ( ( __v2df ) _mm_set1_pd ( __B [ <NUM_LIT> ] ) ) ; return ( __m128d ) _mm_setr_pd ( c [ <NUM_LIT> ] , __A


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget -> getRegisterInfo ( ) ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL .


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . addReg ( SrcReg ) ; return Reg


<s> cfun -> machine -> eh_stack_adjust = sa ; } return cfun -> machine


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRRSext ( SDValue N , SDValue & Base , SDValue & Offset ) { if ( N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) { ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ; if ( ! NC || ! NC -> isZero ( ) ) return false ; Base = Offset = N ; return true


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT VT = Extract -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) . getSizeInBits ( ) > <NUM_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( RegSize / VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; unsigned BinOp = <NUM_LIT> ; SDValue Root = matchBinOpReduction ( Extract , BinOp , { <STR_LIT> } ) ; if ( Root && ( Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> ) ) Root = Root . getOperand ( <NUM_LIT> ) ; if ( ! Root || ( Root . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Zext0 , Zext1 ; if ( ! detectZextAbsDiff ( Root , Zext0 , Zext1 ) ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue SAD = createPSADBW ( DAG , Zext0 , Zext1 , DL ) ; unsigned Stages = Log2_32 ( VT . getVectorNumElements ( ) ) ; MVT SadVT = SAD . getSimpleValueType ( ) ; if ( Stages > <NUM_LIT> ) { unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD , DAG . getUNDEF ( SadVT )


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> HII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; Dependence = false ; PacketNum = <NUM_LIT> ; addMutation ( std :: make_unique < <ISA_LIT>Subtarget ::


<s> static __inline unsigned long long sh_media_LDHI_L ( void * p


<s> bool <ISA_LIT>PacketizerList :: isLegalToPruneDependencies ( SUnit *


<s> CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true


<s> return ( __m128i ) __builtin_ia32_vpcomleud ( ( __v4si ) __A ,


<s> MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , N -> getOffset ( ) , Mask , N -> getMemoryVT (

) , N -> getMemOperand ( ) , N -> getAddressingMode ( ) , N -> isTruncatingStore ( ) , N -> isCompressingStore ( ) ) ;


<s> return get ( MI . getOpcode ( ) ) . TSFlags &


<s> if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRVC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = true ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = false ; return false ; } if ( Option == <STR_LIT>


<s> void <ISA_LIT>TargetELFStreamer :: emitTextAttribute ( unsigned Attribute , StringRef Value


<s> fma_slot = this -> m_insn_fma_head_map -> get ( insn ) ; if ( fma_slot ) return * fma_slot ; return


<s> if ( Features . test ( FeatureWavefrontSize32 ) )


<s> state -> insns_left = state -> issue_rate ; state_transition ( state -> dfa_state , <NUM_LIT>


<s> if ( riscv_memmodel_needs_amo_acquire ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'F' : if ( riscv_memmodel_needs_release_fence ( ( enum memmodel ) INTVAL ( op ) ) ) fputs ( <STR_LIT> , file ) ; break ; case 'i' : if ( code != REG ) fputs ( <STR_LIT> , file ) ; break ; case 'S' : { rtx newop = GEN_INT ( ctz_hwi ( INTVAL ( op ) ) ) ; output_addr_const ( file , newop ) ; break ; } case 'T' : { rtx newop = GEN_INT ( ctz_hwi ( ~ INTVAL ( op ) ) ) ; output_addr_const ( file , newop


<s> MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = ( const TargetRegisterClass * ) & <STR_LIT> ; V0 = RegInfo . createVirtualRegister


<s> Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ( ( ( FrameReg != <STR_LIT> ) && ! isInt < <NUM_LIT> > ( Offset ) ) || ( ( FrameReg == <STR_LIT> ) && ! isInt < <NUM_LIT> > ( Offset ) ) ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; auto & HRI = * HST . getRegisterInfo ( ) ; assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; MachineBasicBlock * PrologB = & MF . front ( ) , * EpilogB = nullptr ; if ( EnableShrinkWrapping ) findShrunkPrologEpilog ( MF , PrologB , EpilogB ) ; insertCSRSpillsInBlock ( * PrologB , CSI , HRI ) ; insertPrologueInBlock ( * PrologB ) ; if ( EpilogB ) { insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ; insertEpilogueInBlock ( *


<s> std :: unique_ptr < <ISA_LIT>Operand > Offset ; OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand ( Offset ) ; if ( ResTy != MatchOperand_Success || ! Offset ) return MatchOperand_NoMatch ; Operands . push_back ( Offset -> isImm ( ) ? <STR_LIT> ( BaseReg , std :: move ( Offset ) ) : <STR_LIT> ( BaseReg , std :: move ( Offset ) ) ) ; return


<s> unsigned <ISA_LIT>TargetLowering :: getZeroReg ( ) const { return


<s> TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createImm ( Imm1 ) ) ; TmpInst . addOperand ( MCOperand :: createImm ( Imm2 ) ) ; TmpInst . setLoc ( IDLoc ) ; getStreamer ( ) . emitInstruction (


<s> break ; case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ) ; break ; case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : break ; case <STR_LIT> : case <STR_LIT> : assert ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; MovePCtoLROffset = ( void * ) MCE . getCurrentPCValue ( ) ; MCE . emitWordBE (


<s> const <STR_LIT> & Out = Outs [ i ] ; SDValue & OutVal = OutVals [ i ] ; if ( Out . Flags . isNest ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isByVal ( ) && Out . Flags . getByValSize ( ) != <NUM_LIT> ) { auto & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateStackObject ( Out . Flags . getByValSize ( ) , Out . Flags . getByValAlign ( ) , false ) ; SDValue SizeNode = DAG . getConstant ( Out . Flags . getByValSize ( ) , DL , <STR_LIT> ) ; SDValue FINode = DAG . getFrameIndex ( FI , getPointerTy ( Layout ) ) ; Chain = DAG . getMemcpy ( Chain , DL , FINode , OutVal , SizeNode , Out . Flags . getByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; OutVal = FINode ; } NumFixedArgs += Out . IsFixed ; } bool IsVarArg = CLI . IsVarArg ; auto PtrVT = getPointerTy ( Layout ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; if ( IsVarArg ) { for ( SDValue Arg : make_range ( OutVals . begin ( ) + NumFixedArgs , OutVals . end ( ) ) ) { EVT VT = Arg . getValueType ( ) ; assert ( VT != <STR_LIT> && <STR_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned Offset = CCInfo . AllocateStack ( Layout . getTypeAllocSize ( Ty ) , Layout . getABITypeAlignment ( Ty ) ) ; CCInfo . addLoc ( CCValAssign :: getMem ( ArgLocs . size ( ) , VT . getSimpleVT ( ) , Offset , VT . getSimpleVT ( ) , CCValAssign :: Full ) ) ; } } unsigned NumBytes = CCInfo . getAlignedCallFrameSize ( ) ; SDValue FINode ; if ( IsVarArg && NumBytes ) { int FI = MF . getFrameInfo ( ) . CreateStackObject ( NumBytes , Layout . getStackAlignment ( ) , false ) ; unsigned ValNo = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( SDValue Arg : make_range ( OutVals . begin ( ) + NumFixedArgs , OutVals . end ( ) ) ) { assert ( ArgLocs [ ValNo ] . getValNo ( )


<s> llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT>


<s> void DecodePUNPCKLBWMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) { DecodeUNPCKLPMask ( <STR_LIT> ( <STR_LIT> , NElts ) ,


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCOPY_FD ( MachineInstr & MI , MachineBasicBlock * BB ) const { assert ( Subtarget . isFP64bit ( ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Fd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; DebugLoc DL = MI . getDebugLoc (


<s> SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Len = DAG . getNode ( <STR_LIT> , DL


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned SGPRReg = findImplicitSGPRRead ( MI ) ; if ( SGPRReg != <STR_LIT> ) return SGPRReg ; unsigned UsedSGPRs [ <NUM_LIT> ] = { <STR_LIT> } ; const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = OpIndices [ i ] ; if ( Idx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; const TargetRegisterClass * OpRC = RI . getRegClass ( Desc . OpInfo [ Idx ] . RegClass ) ; bool IsRequiredSGPR = RI . isSGPRClass ( OpRC ) ; if ( IsRequiredSGPR ) return MO . getReg ( ) ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RegRC = MRI . getRegClass ( Reg ) ; if ( RI . isSGPRClass ( RegRC ) ) UsedSGPRs [ i ]


<s> else if ( GET_MODE ( x ) == DFmode ) { long l [ <NUM_LIT> ] ; REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , l ) ; val = l [ <NUM_LIT> ] ; val = ( val << <NUM_LIT> ) | ( l [ <NUM_LIT> ] &


<s> static inline unsigned getUnconditionalBrDisp ( int Opc ) { return ( Opc == <STR_LIT> ) ? ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) *


<s> case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addOperand ( PushOp ) ; break ; case <STR_LIT> : case <STR_LIT> : unsigned int Reg = PushOp . getReg ( ) ; if ( Is64Bit && MOV -> getOpcode ( ) == <STR_LIT> ) { unsigned UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . addOperand ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> isAtom ( ) || STI -> isSLM ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc (


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShufMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl


<s> DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case <STR_LIT>


<s> int dest_uid ; rtx pat = PATTERN ( branch ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; dest = SET_SRC ( pat ) ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , <NUM_LIT> ) ; dest = XEXP ( dest , <NUM_LIT>


<s> rtx mips_return_addr ( int count , rtx


<s> Register Reg ; if ( DT . find ( TD , & MIRBuilder . getMF ( ) , Reg ) ) return MIRBuilder . getMF ( ) . getRegInfo ( ) . getUniqueVRegDef ( Reg ) ; return nullptr


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return


<s> bool missingFeature ( llvm :: SMLoc const & Loc , uint64_t const & ) { return Error ( Loc ,


<s> PointerSize = CalleeSaveStackSlotSize = T . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; UseDataRegionDirectives = true ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; COMMDirectiveAlignmentIsInBytes =


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1


<s> tree type ; int nvreg = <NUM_LIT> ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { auto DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , getPointerTy ( DL ) , Offset ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy (


<s> bool <ISA_LIT>BitSimplify :: replaceReg ( Register OldR , Register NewR , MachineRegisterInfo & MRI ) { if ( ! OldR . isVirtual ( ) || ! NewR . isVirtual ( ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I