<s> static <ISA_LIT>Operand * CreateCoprocNum ( unsigned CopVal , SMLoc S ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_CoprocNum ) ; Op -> Cop . Val


<s> static bool printModifiedFPRAsmOperand ( const MachineOperand & MO , const TargetRegisterInfo * TRI , char RegType , raw_ostream & O ) { if ( ! MO . isReg ( ) ) return true ; for ( MCRegAliasIterator AR ( MO . getReg ( ) , TRI , true ) ; AR . isValid ( ) ; ++ AR ) { if ( <STR_LIT> . contains ( * AR ) ) { O << RegType << TRI -> getEncodingValue ( MO . getReg ( ) ) ; return false ; } } return true


<s> bool isSpecial ; bool isSigned = checkDTSpecial ( Desc , & isSpecial ) ; if ( isSpecial ) return isSigned ; <ISA_LIT>II :: OpType optype = getOpType ( Desc , MI ) ; isSigned = ( optype == <ISA_LIT>II :: OpType :: INT32 || optype == <ISA_LIT>II :: OpType :: INT16 || optype == <ISA_LIT>II :: OpType :: INT8 || optype == <ISA_LIT>II :: OpType :: INT4 ) ; return isSigned


<s> emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , DImode , <NUM_LIT> , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_lshrdi3 ( i0 , in , const1_rtx ) ) ; emit_insn ( gen_anddi3 ( i1 , in , const1_rtx ) ) ; emit_insn ( gen_iordi3 ( i0 , i0 , i1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_FLOAT ( mode , i0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label (


<s> if ( ! getParamsForOneTrueMaskedElt ( MS , DAG , Addr , VecIndex , Alignment , Offset ) ) return SDValue ( ) ; SDLoc DL ( MS ) ; EVT VT = MS -> getValue ( ) . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT


<s> if ( RestrictUseOfBaseReg ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base_Reg . getNode ( ) ) { if ( ! AM . IndexReg . getNode ( ) ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } AM . BaseType = <ISA_LIT>ISelAddressMode ::


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) ) ; return ( Base << <NUM_LIT> ) |


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Tmp = DAG . getConstantFP ( APF , dl , <STR_LIT> ) ; SDValue True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Tmp ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue False = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSelectCC ( dl , Op . getOperand ( <NUM_LIT> ) , Tmp , True , False , <STR_LIT> ) ; } } return SDValue ( ) ; } if ( Subtarget . hasDirectMove ( ) && Subtarget . is<ISA_LIT>64 ( ) ) return LowerFP_TO_INTDirectMove ( Op ,


<s> getTargetStreamer ( ) -> emitIndirectFunctionType ( getSymbol ( & F ) , Params , Results ) ; } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit

) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , Is<ISA_LIT>64 ( is64Bit ) , TargetTriple ( TT ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT OpVT = N0 . getSimpleValueType ( ) ; assert ( ( OpVT == <STR_LIT> || OpVT == <STR_LIT> ) && <STR_LIT> ) ; MVT VecVT = ( OpVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VecVT , N0 ) ; Res = DAG . getNode ( <STR_LIT>


<s> <ISA_LIT>ModeRegisterDefaults Mode ; Mode . DX10Clamp = true ; Mode . IEEE = IsCompute ; Mode . FP32InputDenormals = false ; Mode . FP32OutputDenormals


<s> if ( as_new != ADDR_SPACE_MEMX && as_new != as_old ) { location_t loc = EXPR_LOCATION ( expr ) ; const char * name_old = avr_addrspace [ as_old ] . name ; const char * name_new = avr_addrspace [ as_new ] . name ; warning ( OPT_Waddr_space_convert , <STR_LIT> , ADDR_SPACE_GENERIC_P ( as_old ) ? <STR_LIT> : name_old , ADDR_SPACE_GENERIC_P ( as_new ) ? <STR_LIT>


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Value > <NUM_LIT> ) { llvm_unreachable ( <STR_LIT>


<s> if ( BVN -> getValueType ( <NUM_LIT> ) != <STR_LIT> || BVN -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned LoElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned HiElt = <NUM_LIT> - LoElt ; ConstantSDNode * Lo0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt ) ) ; ConstantSDNode * Hi0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt ) ) ; ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ; ConstantSDNode * Hi1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt + <NUM_LIT> ) ) ; if ( ! Lo0 || ! Hi0 || ! Lo1 || ! Hi1 ) return false ; if ( isSigned ) { if ( Hi0 -> getSExtValue ( ) == Lo0 -> getSExtValue ( ) >> <NUM_LIT> && Hi1 -> getSExtValue ( ) == Lo1 -> getSExtValue ( ) >> <NUM_LIT> ) return true ; } else { if ( Hi0 -> isZero ( ) && Hi1 -> isZero ( ) ) return true ; } return false ; } if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) { unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned HalfSize = EltSize


<s> if ( ( sa_size == <NUM_LIT> && probed_size > probed - <NUM_LIT> ) || flag_stack_check || flag_stack_clash_protection ) emit_insn ( gen_stack_probe_internal ( GEN_INT ( - probed_size ) ) ) ; } if ( frame_size != <NUM_LIT> ) FRP ( emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - frame_size ) ) ) ) ; } else { HOST_WIDE_INT blocks = ( probed_size + <NUM_LIT> ) / <NUM_LIT> ; HOST_WIDE_INT leftover = probed_size + <NUM_LIT> - blocks * <NUM_LIT> ; rtx ptr = gen_rtx_REG ( DImode , <NUM_LIT> ) ; rtx count = gen_rtx_REG ( DImode , <NUM_LIT> ) ; rtx seq ; emit_move_insn ( count , GEN_INT ( blocks ) ) ; emit_insn ( gen_adddi3 ( ptr , stack_pointer_rtx , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_prologue_stack_probe_loop ( count , ptr ) ) ; if ( ( leftover > <NUM_LIT> && sa_size == <NUM_LIT> ) || flag_stack_check || flag_stack_clash_protection ) { rtx last = gen_rtx_MEM ( DImode , plus_constant ( Pmode , ptr , - leftover ) ) ; MEM_VOLATILE_P ( last ) = <NUM_LIT> ; emit_move_insn ( last , const0_rtx ) ; } if ( flag_stack_check || flag_stack_clash_protection ) { HOST_WIDE_INT lo , hi ; lo = ( ( frame_size & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; hi = frame_size - lo ; emit_move_insn ( ptr , GEN_INT ( hi ) ) ; emit_insn ( gen_adddi3 ( ptr , ptr , GEN_INT ( lo ) ) ) ; seq = emit_insn ( gen_subdi3 ( stack_pointer_rtx , stack_pointer_rtx , ptr ) ) ; } else { seq = emit_insn ( gen_adddi3 ( stack_pointer_rtx , ptr , GEN_INT ( - leftover ) ) ) ; } RTX_FRAME_RELATED_P ( seq ) = <NUM_LIT> ; add_reg_note ( seq , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - frame_size ) ) ) ; } sa_bias = <NUM_LIT> ; sa_reg = stack_pointer_rtx


<s> case <STR_LIT> : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DCI ) ; case <STR_LIT> : case


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc dl ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( DAG . getDataLayout


<s> void GCNPassConfig :: addPreLegalizeMachineIR ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt


<s> SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc


<s> Value * <ISA_LIT>IREmitter :: visitPSHUFHW ( const SDNode


<s> Value * <ISA_LIT>IREmitter :: visitVMOVDRR ( const SDNode


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override { return &


<s> assert ( ( isa < ConstantInt > ( Elt ) || isa < ConstantFP > ( Elt ) ) && <STR_LIT> ) ; bool Sign = V -> getElementType ( ) -> isIntegerTy ( ) ? cast < ConstantInt > ( Elt ) -> isNegative ( ) : cast < ConstantFP > ( Elt ) -> isNegative ( ) ; BoolVec . push_back ( ConstantInt :: get


<s> int64_t imm = static_cast < int64_t > ( ( helper_get_page_address ( pDest ) - helper_get_page_address ( pSource


<s> CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } MIB . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg =


<s> return ( __m64 ) __builtin_arm_wsubw ( ( __v2si


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredSegAlloca ( MachineInstr * MI , MachineBasicBlock * BB , bool Is64Bit ) const { const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; assert ( EnableSegmentedStacks ) ; unsigned TlsReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TlsOffset = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; MachineBasicBlock * mallocMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * bumpMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * continueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterClass * AddrRegClass = getRegClassFor ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; unsigned mallocPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , bumpSPPtrVReg = MRI . createVirtualRegister ( AddrRegClass ) , tmpSPVReg = MRI . createVirtualRegister ( AddrRegClass ) , sizeVReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , physSPReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineFunction :: iterator MBBIter = BB ; ++ MBBIter ; MF -> insert ( MBBIter , bumpMBB ) ; MF -> insert ( MBBIter , mallocMBB ) ; MF -> insert ( MBBIter , continueMBB ) ; continueMBB -> splice ( continueMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; continueMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , tmpSPVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( tmpSPVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( tmpSPVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , bumpSPPtrVReg ) . addReg ( tmpSPVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; if ( Is64Bit ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT>


<s> if ( ! MRI . getRegClassOrNull ( CondReg ) ) MRI . setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ; BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) .

addMBB ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ;


<s> const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT>

) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> EVT IntPtr = getPointerTy ( ) ; EVT SPTy = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr , SPTy


<s> auto SDWADst = make_unique < SDWADstOperand > ( Dst , Src1 , BYTE_1 , UNUSED_PAD ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << * SDWADst << '\n' ) ; SDWAOperands [ & MI ] = std :: move ( SDWADst ) ; ++ NumSDWAPatternsFound ; } else { auto SDWASrc = make_unique < SDWASrcOperand > ( Src1 , Dst , BYTE_1 , false , false , Opcode == <STR_LIT> ? false : true ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << * SDWASrc << '\n' ) ; SDWAOperands [ & MI ] = std :: move ( SDWASrc ) ; ++ NumSDWAPatternsFound ; } break ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; auto Offset = foldToImm ( * Src1 ) ; if ( ! Offset ) break ; MachineOperand * Src2 = TII -> getNamedOperand ( MI , <STR_LIT> :: src2 ) ; auto Width = foldToImm ( * Src2 ) ; if ( ! Width ) break ; SdwaSel SrcSel = DWORD ; if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = BYTE_0 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = WORD_0 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = DWORD ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = BYTE_1 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = BYTE_2 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = WORD_1 ; else if ( * Offset == <NUM_LIT> && * Width == <NUM_LIT> ) SrcSel = BYTE_3 ; else break ; MachineOperand * Src0 = TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ; MachineOperand * Dst = TII -> getNamedOperand ( MI , <STR_LIT> :: vdst ) ; if ( TRI -> isPhysicalRegister ( Src0 -> getReg ( ) ) || TRI -> isPhysicalRegister ( Dst -> getReg ( ) ) ) break ; auto SDWASrc = make_unique < SDWASrcOperand > ( Src0 , Dst , SrcSel , false , false , Opcode == <STR_LIT> ? false : true ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << * SDWASrc << '\n' ) ; SDWAOperands [ & MI ] = std :: move ( SDWASrc ) ; ++ NumSDWAPatternsFound ; break ; } case <STR_LIT> : { MachineOperand * Src0 = TII -> getNamedOperand (


<s> MCSymbol * Label = Ctx . GetOrCreateSymbol ( Twine ( Prefix ) + <STR_LIT> + Twine ( FunctionNumber ) + <STR_LIT> + Twine ( LabelId ) ) ; return Label


<s> if ( ! isGFX10Plus ( ) ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; if ( ! trySkipId ( <STR_LIT> , AsmToken :: Colon ) ) return MatchOperand_NoMatch ; std :: string Token ; if ( isToken ( AsmToken :: Integer ) ) { SMLoc Loc = getToken ( ) . getEndLoc ( ) ; Token = std :: string ( getTokenStr ( ) ) ; Parser . Lex ( ) ; if ( getLoc ( ) != Loc ) return MatchOperand_ParseFail ; } if ( ! isToken ( AsmToken :: Identifier ) ) return MatchOperand_ParseFail ; Token += getTokenStr ( ) ; StringRef DimId = Token


<s> const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std ::


<s> static DecodeStatus DecodeSPE4RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void *


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setLRStoreRequired ( ) ; bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddrFrameIndex ( DAG ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode (

) , RetAddrFI , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> if ( field == NULL || field == type || DECL_MODE ( field ) != DFmode ) return MAX ( computed , specified ) ; return MAX ( MAX ( computed , specified


<s> switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_m : if ( ! SelectMem ( Op , Op0 ) ) { return true ; } OutOps . push_back ( Op0 ) ; return false ; case InlineAsm :: Constraint_o : if ( ! SelectOff ( Op , Op0 , Op1 ) ) { return true ; } OutOps . push_back


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : <STR_LIT> ( ) ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize < <NUM_LIT> || ShiftSize > <NUM_LIT> || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> ) return NN ; else if ( SarConst . isNegative ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , NN , DAG . getConstant


<s> unsigned Reg = RS ? RS -> FindUnusedReg ( RC , true ) : ( unsigned ) <STR_LIT> ; assert ( ! AFI -> isThumbFunction (


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDValue ArgOut ; if ( VA . getValNo ( ) == <NUM_LIT> ) { ArgOut = DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ; } else if ( VA . getValNo ( ) == <NUM_LIT> ) { ArgOut = DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ; } else report_fatal_error ( <STR_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps .


<s> const DataLayout * DL = TM . getDataLayout ( ) ; const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ; break ; case MachineOperand ::


<s> static void microblaze_elf_asm_init_sections ( void ) { sdata2_section = get_unnamed_section ( SECTION_WRITE , output_section_asm_op


<s> return static_cast < const <ISA_LIT>Operand & > ( op )


<s> case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVX128BOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = &


<s> return ( uint8x16_t ) __builtin_neon_vqadduv16qi ( ( int8x16_t )


<s> return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( false , object :: mach :: CTM_<ISA_LIT> , object :: mach :: CS<ISA_LIT>_V7 )


<s> base = addr ; offset = const0_rtx ; } if ( base != NULL_RTX ) { int regno = REGNO ( base ) ; if ( regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM ) { if ( ( ( cfun != <NUM_LIT> && REGNO_POINTER_ALIGN ( regno ) >= desired * BITS_PER_UNIT ) || ( optimize && reload_completed ) ) && ( INTVAL ( offset ) & ( desired - <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; } else { if ( ( ( INTVAL ( offset ) - SPARC_STACK_BIAS ) & ( desired - <NUM_LIT> ) )


<s> if ( ! ST -> allowsUnalignedMem ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> isLittle ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LoopAccessInfo LAI ( L , SE , TLI , AA , DT , LI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; if ( ! RecordSequentialLoads ( Header ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT VT8Bit = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N0 ) ; SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N1 ) ; SDValue N3 = DAG . getNode ( <STR_LIT> , DL , VT8Bit


<s> SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ; SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi , <STR_LIT> ) ; SDValue CmpNum = DAG . getSetCC ( SL , <STR_LIT> , NumHi , Scale1Hi , <STR_LIT> ) ; Scale = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CmpNum , CmpDen ) ; } else { Scale = DivScale1 . getValue ( <NUM_LIT> ) ; } SDValue Fmas = DAG . getNode ( <STR_LIT> , SL ,

<STR_LIT> , Fma4 , Fma3 , Mul , Scale ) ;


<s> } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; } return


<s> int i ; for ( i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ] = <NUM_LIT> ; g -> get_passes ( ) -> execute_pass_mode_switching (


<s> bool FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . hasOneUse ( ) && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( DAG . ComputeNumSignBits ( Cond ) != CondVT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( TValIsAllOnes && FValIsAllZeros ) return DAG . getBitcast ( VT , Cond ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( CondVT ) ) return SDValue ( ) ; if ( TValIsAllOnes ) { SDValue CastRHS = DAG . getBitcast ( CondVT , RHS ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastRHS ) ; return DAG . getBitcast ( VT , Or ) ; } if ( FValIsAllZeros


<s> const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr ::

create ( <NUM_LIT> , OutContext ) , OutContext ) ;


<s> static DecodeStatus DecodeJumpTarget ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( JumpOffset ) ) ; return MCDisassembler


<s> inline unsigned M1 ( unsigned Val ) { return Val


<s> int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; FrameReg =


<s> o << getTagName ( PREFIX_SYMBOL ) << <STR_LIT> << num << <STR_LIT> ; return o . str (


<s> static bool pa_can_eliminate ( const int from , const int to ) { if ( TARGET_64BIT && from == ARG_POINTER_REGNUM ) return false ; return ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ?


<s> bool hasSymbolicDisplacement ( ) const { return GV != nullptr || CP != nullptr || ES != nullptr


<s> switch ( Rs ) { case <NUM_LIT> : if ( As == <NUM_LIT> ) return amSymbolic ; if ( As == <NUM_LIT> ) return amInvalid ; if ( As == <NUM_LIT> ) return amImmediate ; break ; case <NUM_LIT> : if ( As == <NUM_LIT> ) return amAbsolute ; if ( As == <NUM_LIT> ) return amConstant ; if ( As == <NUM_LIT> ) return amConstant ; break ; case <NUM_LIT> : return amConstant ; default : break ; } switch ( As )


<s> output_asm_insn ( <STR_LIT> , xoperands ) ; } output_asm_insn ( <STR_LIT> , xoperands ) ; } } if ( seq_length == <NUM_LIT> ) output_asm_insn ( <STR_LIT> , xoperands ) ; if ( seq_length == <NUM_LIT> || GET_CODE ( NEXT_INSN ( insn ) ) != JUMP_INSN ) return <STR_LIT> ; xoperands [ <NUM_LIT> ] = XEXP ( PATTERN ( NEXT_INSN ( insn ) ) , <NUM_LIT> ) ; if ( INSN_ADDRESSES_SET_P ( ) ) { seq_insn = NEXT_INSN ( PREV_INSN ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ; distance = ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( NEXT_INSN ( insn ) ) ) ) - INSN_ADDRESSES ( INSN_UID ( seq_insn ) ) - <NUM_LIT> ) ; if ( VAL_14_BITS_P ( distance ) ) { xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( xoperands [ <NUM_LIT> ] ) ) ; } else output_asm_insn ( <STR_LIT> , xoperands ) ; } else output_asm_insn ( <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot


<s> auto * CellUndef = UndefValue :: get ( CellTy ) ; if ( I . getOperand ( <NUM_LIT> ) != CellUndef ) return false ; IRBuilder < > Builder ( & I ) ; CallInst * Pushnull = Builder


<s> <ISA_LIT>PropagateAttributesLate ( const TargetMachine *


<s> rtx addr = XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) ; if ( modified_in_p ( addr , set_insn ) != <NUM_LIT> ) { rtx set = single_set ( set_insn ) ; if ( set && ( push_operand ( SET_DEST ( set ) , GET_MODE ( SET_DEST ( set ) ) ) || pop_operand ( SET_SRC ( set ) , GET_MODE ( SET_SRC ( set ) ) ) ) ) { struct ix86_address parts ; if ( ix86_decompose_address ( addr , & parts ) && parts . base == stack_pointer_rtx && ( parts . index == NULL_RTX || MEM_P ( SET_DEST ( set ) ) || ! modified_in_p ( parts . index , set_insn ) ) ) return false ; } return true ; } return false ; } return


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create ( <ISA_LIT>Subtarget


<s> static bool arm_default_short_enums (


<s> unsigned indexOffset = CheckEven ? <NUM_LIT> : <NUM_LIT> ; if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , indexOffset , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , indexOffset , <NUM_LIT> ) ; else return


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; int64_t Offset = <NUM_LIT> ; if ( ! mi_match ( Root . getReg ( ) , * MRI , m_ICst ( Offset ) ) || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( isStackPtrRelative ( PtrInfo ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } } }


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned Reg1 =


<s> MachineSDNode :: mmo_iterator MemEnd = std :: copy ( Op0 -> memoperands_begin ( ) , Op0 -> memoperands_end ( ) , MemBegin ) ; MemEnd = std :: copy ( Op1 -> memoperands_begin ( ) , Op1 -> memoperands_end ( ) , MemEnd ) ; MI -> setMemRefs ( MemBegin , MemEnd


<s> return true ; } } const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { <ISA_LIT>InstPrinter :: printRegOperand ( MO . getReg ( ) , O , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; return false ; } else if ( MO . isImm ( ) ) { int64_t Val = MO . getImm ( ) ; if ( <STR_LIT> (


<s> __inline__ static unsigned long long sh_media_MCMPGT_L ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> (


<s> inline vector float vec_min ( vector float a1 , vector


<s> return ( __m512i ) __builtin_ia32_vpopcountq_v8di ( ( __v8di


<s> static bool isZero ( Register Reg , MachineRegisterInfo &


<s> unsigned RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! getConstantVRegVal ( RHS , MRI ) ) std :: swap ( RHS , LHS ) ; const auto RHSImm = getConstantVRegVal ( RHS , MRI ) ; if ( ! RHSImm || * RHSImm != <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank ( LHS , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; const auto Pred = ( CmpInst :: Predicate ) CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ; if ( Pred != CmpInst :: ICMP_NE && Pred != CmpInst :: ICMP_EQ ) return false ; const unsigned CmpWidth = MRI . getType ( LHS ) . getSizeInBits ( ) ; unsigned CBOpc = <NUM_LIT> ; if ( CmpWidth <= <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ; else if ( CmpWidth == <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } SelectCode ( Node


<s> unsigned getMaxInterleaveFactor ( unsigned VF ) { return ST -> getMaxInterleaveFactor


<s> int BranchOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( BranchOffset > <NUM_LIT> ) BranchOffset = - <NUM_LIT> * ( <NUM_LIT> - BranchOffset ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler ::


<s> return m32c_hard_regno_nregs_1 ( regno , mode )


<s> void i386_pe_asm_named_section ( const char * name , unsigned int flags , tree decl ) { char flagchars [ <NUM_LIT> ] , * f = flagchars ; if ( ( flags & SECTION_EXCLUDE ) != <NUM_LIT> ) * f ++ = 'e' ; if ( ( flags & ( SECTION_CODE | SECTION_WRITE ) ) == <NUM_LIT> ) { * f ++ = 'd' ; * f ++ = 'r' ; } else { if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_PE_SHARED ) * f ++ = 's' ; if ( ( flags & SECTION_EXCLUDE ) != <NUM_LIT> ) * f ++ = 'n' ; } if ( startswith ( name , LTO_SECTION_NAME_PREFIX ) ) * f ++ = '0' ; * f = '\0' ; fprintf ( asm_out_file , <STR_LIT> , name , flagchars ) ; if ( flags & SECTION_LINKONCE


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return c4x_arn_mem_operand ( op , mode , IR1_REGNO


<s> static const int RegPressureLimit [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> FunctionPass * llvm :: create<ISA_LIT>FixupLEAs ( ) { return new FixupLEAPass


<s> llvm_unreachable ( <STR_LIT> ) ; break ; CASE_VSHUF ( <NUM_LIT> , m ) HasMemOp = true ; CASE_VSHUF ( <NUM_LIT> , r ) VT = getRegOperandVectorVT (


<s> const_packet_range insts ( ) const { return make_range ( cbegin ( )


<s> if ( OpNo < MI -> getNumOperands ( ) ) { <STR_LIT> e = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> ( e


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>31 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>35 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>4 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>51 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>6 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>TINY ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA1 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA3 ; else if ( Features [ <STR_LIT> ]

) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA4 ;


<s> bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddrFrameIndex ( DAG


<s> if ( ! Subtarget -> hasMulI24 ( ) || VT . isVector ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! isI24 ( N0 , DAG ) || ! isI24 ( N1 , DAG ) ) return SDValue ( ) ; N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; SDValue Mulhi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , N1 ) ; DCI . AddToWorklist ( Mulhi . getNode ( ) ) ; return DAG . getSExtOrTrunc ( Mulhi , DL


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) { Inst . setOpcode ( <STR_LIT> ) ; } else { if ( ! isIntN ( <NUM_LIT> , Offset . getImm ( ) ) ) Error ( IDLoc , <STR_LIT> ) ; if ( OffsetToAlignment ( Offset . getImm ( ) , <NUM_LIT> << <NUM_LIT> ) ) Error ( IDLoc , <STR_LIT> ) ; Inst . clear ( ) ; Inst . setOpcode (


<s> void assignValueId ( GlobalValue :: GUID


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , DL , <STR_LIT> ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) ; if ( Subtarget -> hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) , V1 ) ; return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; } if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 ,

V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> OS << getRegisterName ( MI -> getOperand ( opNum +


<s> return ( uint16x4_t ) __builtin_neon_vcgtv4hi ( __a ,


<s> HSACodeObject :: note_iterator HSACodeObject :: notes_end


<s> temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C


<s> int nreg = CEIL ( GET_MODE_SIZE ( arg . mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= <NUM_LIT> ) ; if ( arg . named )


<s> auto ArgAssignFn = TLI . CCAssignFnForCall ( Info . CallConv , IsVarArg ) ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , Info . OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; splitToValueTypes ( Info . OrigRet , ArgInfos , MF ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv , IsVarArg ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ; } CallSeqStart . addImm ( ArgHandler . StackSize ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( ArgHandler . StackSize ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; return true


<s> void <ISA_LIT>TargetStreamer :: emitRRI ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , int16_t Imm ,

SMLoc IDLoc , const MCSubtargetInfo * STI ) {


<s> unsigned FixedObject = getFixedObjectSize ( MF , AFI , IsWin64 , false ) ; unsigned FPAdjust = isTargetDarwin ( MF ) ? <NUM_LIT> : AFI -> getCalleeSavedStackSize ( MF


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand (


<s> static inline void desc_mem_stack_v ( unw_word t ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNum , SMLoc S ,


<s> int32_t i [ <NUM_LIT> ] ; } u ; u . v =


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> return getGeneration ( ) <= SEA_ISLANDS


<s> static bool arm_return_in_msb ( tree valtype ) { return ( TARGET_AAPCS_BASED && BYTES_BIG_ENDIAN && ( AGGREGATE_TYPE_P ( valtype

) || TREE_CODE ( valtype ) == COMPLEX_TYPE ) ) ;


<s> rtx label = s390_execute_label ( insn ) ; return label && label


<s> StringRef <ISA_LIT>TargetMachine :: getGPUName ( const Function & F ) const { Attribute GPUAttr = F . getFnAttribute (


<s> unsigned OffsetInBytes = <NUM_LIT> ; unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; Align Alignment = std :: min ( Flags . getNonZeroByValAlign ( ) , Align ( RegSizeInBytes ) ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) , RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; unsigned NumRegs = LastReg - FirstReg ; if ( NumRegs ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetByValArgRegs ( ) ; bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , Alignment . value ( ) ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> ,


<s> unsigned MatchResult ; bool PendConditionalInstruction = false ; SmallVector < NearMissInfo , <NUM_LIT> > NearMisses ; MatchResult = MatchInstruction ( Operands , Inst , NearMisses , MatchingInlineAsm , PendConditionalInstruction , Out ) ; switch ( MatchResult ) { case Match_Success : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; forwardVPTPosition ( ) ; return true ; } { while ( processInstruction ( Inst , Operands , Out ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; } forwardITPosition ( ) ; forwardVPTPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ; if ( isITBlockFull ( ) || isITBlockTerminator ( Inst ) ) flushPendingInstructions ( Out


<s> static DecodeStatus DecodeUImmWithOffsetAndScale ( MCInst & Inst , unsigned Value , uint64_t Address , const MCDisassembler * Decoder ) { Value &= ( ( <NUM_LIT> << Bits ) -


<s> static bool parseLEBImmediate ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , bool Signed ) { int64_t


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT>


<s> unsigned Reg = TRI -> getEncodingValue ( Op . getReg ( ) ) ; if ( TRI -> isVGPR ( MRIA , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . VGPR0 && Reg <= RegisterEncoding . VGPRL ) ; Result . first = Reg - RegisterEncoding . VGPR0 ; assert ( Result . first >= <NUM_LIT> && Result . first < SQ_MAX_PGM_VGPRS ) ; } else if ( TRI -> isSGPRReg ( MRIA , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . SGPR0 && Reg < SQ_MAX_PGM_SGPRS ) ; Result . first = Reg - RegisterEncoding . SGPR0 + NUM_ALL_VGPRS ; assert ( Result . first >= NUM_ALL_VGPRS && Result . first < SQ_MAX_PGM_SGPRS + NUM_ALL_VGPRS ) ; } else return { - <NUM_LIT> , - <NUM_LIT> } ; const MachineInstr & MIA = * MI ; const TargetRegisterClass * RC = TII -> getOpRegClass ( MIA , OpNo ) ; unsigned Size = RC


<s> return __builtin_loongson_pcmpgtw_u ( s ,


<s> if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { return CSR_FIQ_SaveList


<s> if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) getTargetStreamer ( ) -> getPALMetadata ( ) -> readFromIR ( M ) ; if ( IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ; IsaVersion Version = getIsaVersion ( getGlobalSTI ( ) -> getCPU


<s> return ( ( vec_short8 ) ( si_sfhi ( ( qword ) b ,


<s> end_sequence ( ) ; return tmp ; } end_sequence ( ) ; } start_sequence ( ) ; tmp = s390_expand_mask_and_shift ( ins , mode , ac -> shift ) ; * seq1 = get_insns ( ) ; end_sequence ( ) ; start_sequence ( ) ; tmp = expand_simple_binop ( SImode , IOR , tmp , val , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; * seq2 = get_insns ( ) ; end_sequence ( ) ; return


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) fixed_regs [ i ] = <NUM_LIT> ; } if ( TARGET_ES0 && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name ,


<s> DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ; return


<s> return true ; } case <STR_LIT> : { <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( <NUM_LIT> ) ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) -> getPointerElementType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand


<s> const MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( ! Src0 -> isReg ( ) || ! Src1 -> isReg ( ) || Src0 -> getReg ( ) != Src1 -> getReg ( ) || Src0 -> getSubReg ( ) != Src1 -> getSubReg ( ) || Src0 -> getSubReg ( ) != <STR_LIT> ) return nullptr ; if ( TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) return nullptr ; unsigned Src0Mods = TII -> getNamedOperand ( MI , <STR_LIT> :: src0_modifiers


<s> return __builtin_ia32_aesdec128kl_u8 ( ( __v2di * ) __A , ( __v2di ) __B ,


<s> if ( MBB . empty ( ) ) return false ; switch ( MBB . back ( ) . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> <ISA_LIT>_64RelType Type = getType64 ( Fixup . getKind ( ) , Modifier , IsPCRel ) ; if ( getEMachine ( ) == ELF :: EM_<ISA_LIT>_64 ) return getRelocType64 ( Modifier , Type , IsPCRel ) ; assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine

( ) == ELF :: EM_IAMCU ) && <STR_LIT> ) ;


<s> if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ; return selectAddrDefault ( Addr , Base ,


<s> if ( isVGPRToSGPRCopy ( SrcRC , DstRC , * TRI ) ) { MachineInstr * DefMI = MRI . getVRegDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned SMovOp ; int64_t Imm ; if ( isSafeToFoldImmIntoCopy ( & MI , DefMI , TII , SMovOp , Imm ) ) { MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm ) ; MI . addImplicitDefUseOperands ( MF ) ; MI . setDesc ( TII -> get ( SMovOp ) ) ; break ; } TII -> moveToVALU ( MI ) ; } break ; } case <STR_LIT> : { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( Reg ) ) ) break ; if ( MI . getNumExplicitOperands ( ) == <NUM_LIT> ) { MachineBasicBlock * MBB0 = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock * MBB1 = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! predsHasDivergentTerminator ( MBB0 , TRI ) && ! predsHasDivergentTerminator ( MBB1 , TRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI << '\n' ) ; break ; } } SmallSet < unsigned , <NUM_LIT> > Visited ; if ( phiHasVGPROperands ( MI , MRI , TRI , TII ) || ! phiHasBreakDef ( MI , MRI , Visited ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } break ; } case <STR_LIT> : { if ( TRI -> hasVGPRs ( TII -> getOpRegClass ( MI , <NUM_LIT> ) ) || ! hasVGPROperands ( MI , TRI ) ) { foldVGPRCopyIntoRegSequence ( MI , TRI , TII , MRI ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU (


<s> DecodeStatus Result = MCDisassembler :: Fail ; Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; Result = decodeInstruction ( DecoderTable16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler ::


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_VReg_128 ( unsigned Val ) const { return createRegOperand ( <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear (


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> )


<s> int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( )


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! ST . hasImageHandles ( ) ) addPass ( create<ISA_LIT>ReplaceImageHandlesPass ( ) ) ; return false


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr


<s> unsigned getSOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FK_Data_4 ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind


<s> if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) return ( STI . useThumbBacktraces ( ) || STI . isThumb ( ) ) ? <STR_LIT> : <STR_LIT> ; else return


<s> static void makeDMB ( IRBuilder < > & Builder , <STR_LIT> Domain ) { Module * M = Builder . GetInsertBlock ( ) -> getParent (


<s> InConstantPool = false ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) return expandTLSLA ( MI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return emitCustomConstantPool (


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>elTarget ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > A ( getThe<ISA_LIT>64Target (


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; } assert ( Opc && <STR_LIT> ) ; const MachineInstrBuilder & MI = BuildMI ( MBB , MBBI , DL , get ( Opc )

) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) ;


<s> for ( MCRegAliasIterator AI ( Reg , TM . getRegisterInfo ( ) , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI )


<s> rtx exp = SET_SRC ( PATTERN ( insn ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MAC : case TYPE_DMAC : if ( REG_P ( XEXP ( exp , <NUM_LIT> ) ) ) return XEXP ( exp , <NUM_LIT> ) ; else return XEXP ( exp , <NUM_LIT> ) ; default : gcc_unreachable ( )


<s> unsigned Size = Desc . getSize ( ) ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint8_t ByteBits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write ( OS , ByteBits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint16_t WordBits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write ( OS , WordBits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t ByteWordBits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint8_t OpcodeBits = ( ByteWordBits >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t ArgBits = ByteWordBits & <NUM_LIT> ; <STR_LIT> :: write ( OS , OpcodeBits , <STR_LIT>


<s> MachineFunctionPass ( ID ) , ST ( nullptr ) , TII ( nullptr ) , TRI ( nullptr

) , ExpInstrTypesSeen ( <NUM_LIT> ) , VCCZCorrupt ( false ) {


<s> Parser . Lex ( ) ; Parser . Lex ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , S , getLoc ( ) , getContext ( ) ) ) ; StringRef value = TokE . getString ( ) ; const char * extTypeName = getGPROffsetExtTypeName ( value ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( extTypeName , false , SS , getContext ( ) ) ) ; Parser . Lex ( ) ; SMLoc SSS = getLoc ( ) ; const AsmToken & TokH = Parser . getTok ( ) ; if ( TokH . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; const AsmToken & TokI = Parser . getTok ( ) ; if ( TokI . isNot ( AsmToken :: Integer ) ) { Error ( SSS , <STR_LIT>


<s> static bool isCondBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ||

Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> return Opcode == AMDGPU :: BRANCH || Opcode == AMDGPU :: BRANCH_COND_i32 || Opcode


<s> phiInfoElementSetDef ( findPHIInfoElement ( OldDestReg ) , NewDestReg


<s> return ( strncmp ( section , templ , len ) == <NUM_LIT> && ( section

[ len ] == <NUM_LIT> || section [ len ] == '.' ) ) ;


<s> bool <ISA_LIT>AsmParser :: validateMSAIndex ( int Val , int RegKind ) { <STR_LIT> Kind = ( <STR_LIT> ) RegKind ; if ( Val < <NUM_LIT> )


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> for ( unsigned int pi = <NUM_LIT> ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) if ( group . types [ <NUM_LIT> ] [ <NUM_LIT> ] == NUM_TYPE_SUFFIXES ) { gcc_assert ( mode32 != MODE_none && mode64 != MODE_none ) ; build_one ( b , signature , group , mode32 , <NUM_LIT> , pi , force_direct_overloads ) ; build_one ( b , signature , group , mode64 , <NUM_LIT> , pi , force_direct_overloads ) ; } else for ( unsigned int ti = <NUM_LIT> ; group . types [ ti ] [ <NUM_LIT> ] != NUM_TYPE_SUFFIXES ; ++ ti ) { unsigned int bits = type_suffixes [ group . types [ ti ] [ <NUM_LIT> ] ]


<s> const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> ,

MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ;


<s> static ArgDescriptor createStack ( unsigned Offset , unsigned Mask =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TargetOptions Options = Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options ; return ( Options . UnsafeFPMath || Options . AllowFPOpFusion == FPOpFusion :: Fast ) ; } return


<s> unsigned CommOpIdx2 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( ! TII -> findCommutedOpIndices ( * MI , CommOpIdx1 , CommOpIdx2 ) || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl


<s> cvtThumbMultiply ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCCOutOperands ( Inst , <NUM_LIT> ) ; unsigned RegOp = <NUM_LIT> ; if ( Operands . size ( ) == <NUM_LIT> && ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) == ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) ) RegOp = <NUM_LIT> ; ( ( <ISA_LIT>Operand * ) Operands [ RegOp ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ]

) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> void <ISA_LIT>OptimizeVGPRLiveRange :: updateLiveRangeInElseRegion ( Register Reg , Register NewReg , MachineBasicBlock * Flow , MachineBasicBlock * Endif , SmallSetVector < MachineBasicBlock * , <NUM_LIT> > & ElseBlocks ) const { LiveVariables :: VarInfo & NewVarInfo = LV -> getVarInfo ( NewReg ) ; LiveVariables :: VarInfo & OldVarInfo = LV -> getVarInfo ( Reg ) ; for ( auto * MBB : ElseBlocks ) { unsigned BBNum = MBB -> getNumber ( ) ; if ( OldVarInfo . AliveBlocks . test ( BBNum ) ) { NewVarInfo . AliveBlocks . set ( BBNum ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference


<s> return selectBitreverse ( ResVReg , ResType , I ) ; case TargetOpcode :: G_BUILD_VECTOR : return selectConstVector ( ResVReg , ResType , I ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : { MachineBasicBlock & BB = * I . getParent ( ) ; auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; for ( auto V : I . getOperand ( <NUM_LIT> ) . getShuffleMask ( ) ) MIB . addImm ( V ) ; return MIB . constrainAllUses ( TII , TRI , RBI ) ; } case TargetOpcode :: G_MEMMOVE : case TargetOpcode :: G_MEMCPY : return selectMemOperation ( ResVReg , I ) ; case TargetOpcode :: G_ICMP : return selectICmp ( ResVReg , ResType , I ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( ResVReg , ResType , I ) ; case TargetOpcode :: G_FRAME_INDEX : return selectFrameIndex ( ResVReg , ResType , I ) ; case TargetOpcode :: G_LOAD : return selectLoad ( ResVReg , ResType , I ) ; case TargetOpcode :: G_STORE : return selectStore ( I ) ; case TargetOpcode :: G_BR : return selectBranch ( I ) ; case TargetOpcode :: G_BRCOND : return selectBranchCond ( I ) ; case TargetOpcode :: G_PHI : return selectPhi ( ResVReg , ResType , I ) ; case TargetOpcode :: G_FPTOSI : return selectUnOp ( ResVReg , ResType , I , <STR_LIT> ) ; case TargetOpcode :: G_FPTOUI : return selectUnOp ( ResVReg , ResType , I , <STR_LIT> ) ; case TargetOpcode :: G_SITOFP : return selectIToF ( ResVReg , ResType , I , true , <STR_LIT> ) ; case TargetOpcode :: G_UITOFP : return selectIToF ( ResVReg , ResType , I , false , <STR_LIT> ) ; case TargetOpcode :: G_CTPOP : return selectUnOp ( ResVReg , ResType , I , <STR_LIT> ) ; case TargetOpcode :: G_SEXT : return selectExt ( ResVReg , ResType , I , true ) ; case TargetOpcode :: G_ANYEXT : case TargetOpcode :: G_ZEXT : return selectExt ( ResVReg , ResType , I , false ) ; case TargetOpcode :: G_TRUNC : return selectTrunc ( ResVReg , ResType , I ) ; case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FPEXT : return selectUnOp ( ResVReg , ResType , I , <STR_LIT> ) ; case TargetOpcode :: G_PTRTOINT : return selectUnOp ( ResVReg , ResType , I , <STR_LIT> ) ; case TargetOpcode :: G_INTTOPTR : return selectUnOp ( ResVReg , ResType , I , <STR_LIT>


<s> start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , got_register_rtx ) ; seq = get_insns ( ) ; end_sequence ( )


<s> static SDValue performDSPShiftCombine ( unsigned Opc , SDNode * N , EVT Ty , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned EltSize = Ty . getScalarSizeInBits ( ) ; BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Subtarget . hasDSP ( ) ) return SDValue ( ) ; if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget . isLittle ( ) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue ( ) >= EltSize ) ) return SDValue ( ) ; SDLoc DL ( N ) ; return DAG . getNode ( Opc , DL , Ty , N -> getOperand ( <NUM_LIT> ) , DAG .

getConstant ( SplatValue . getZExtValue ( ) , DL , <STR_LIT> ) ) ;


<s> auto * SingleMemOpTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; InstructionCost MemOpCost ; bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps ; if ( UseMaskedMemOp ) MemOpCost = getMaskedMemoryOpCost ( Opcode , SingleMemOpTy , Alignment , AddressSpace , CostKind ) ; else MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; unsigned VF = VecTy -> getNumElements ( ) / Factor ; MVT VT = <STR_LIT> ( <STR_LIT> ( VecTy -> getScalarType ( ) ) , VF ) ; InstructionCost MaskCost ; if ( UseMaskedMemOp ) { APInt DemandedLoadStoreElts = APInt :: getZero ( VecTy -> getNumElements ( ) ) ; for ( unsigned Index : Indices ) { assert ( Index < Factor && <STR_LIT> ) ; for ( unsigned Elm = <NUM_LIT> ; Elm < VF ; Elm ++ ) DemandedLoadStoreElts . setBit ( Index + Elm * Factor ) ; } Type * I1Type = Type :: getInt1Ty ( VecTy -> getContext ( ) ) ; MaskCost = getReplicationShuffleCost ( I1Type , Factor , VF , UseMaskForGaps ? DemandedLoadStoreElts : APInt :: getAllOnes ( VecTy -> getNumElements ( ) ) , CostKind ) ; if ( UseMaskForGaps ) { auto * MaskVT = FixedVectorType :: get ( I1Type , VecTy -> getNumElements ( ) ) ; MaskCost += getArithmeticInstrCost ( BinaryOperator :: And , MaskVT , CostKind ) ; } } if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return MaskCost + NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = UseMaskedMemOp || NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + MaskCost

+ NumOfUnfoldedLoads * MemOpCost + NumOfMoves ;


<s> static DecodeStatus decodePC24DBLBranchOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) { return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG ,


<s> void <ISA_LIT>InstPrinter :: printFORMAT ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream


<s> bool <ISA_LIT>LateEHPrepare :: mergeTerminatePads ( MachineFunction & MF ) { SmallVector < MachineBasicBlock * , <NUM_LIT> > TermPads ; for ( auto & MBB : MF ) if ( <STR_LIT> ( MBB ) ) TermPads . push_back ( & MBB ) ; if ( TermPads . empty ( ) ) return false ; MachineBasicBlock * UniqueTermPad = TermPads . front ( ) ; for ( auto * TermPad : llvm :: make_range ( std :: next ( TermPads . begin ( ) ) , TermPads .


<s> const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( )


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * * MI << <STR_LIT> ) ; MachineOperand & Dest = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; bool IsADDIInstRequired = ! useSameRegister ( Dest , TrueValue ) ; bool IsORIInstRequired = ! useSameRegister ( Dest , FalseValue ) ; if ( ! IsADDIInstRequired && ! IsORIInstRequired


<s> MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction ::

createOffset ( nullptr , DRegNum , Offset ) ) ;


<s> OS << getName ( ) << '(' ; getSubExpr ( ) -> print ( OS


<s> PredicateThen = std :: make_unique < PredicatedMI > ( MI ,


<s> printAMIndexedWB ( MI , OpNum , <NUM_LIT> ,


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; auto DL = DAG . getDataLayout ( ) ; SDLoc dl ( Op ) ; SDValue FI = DAG . getFrameIndex ( AFI -> getVarArgsFrameIndex ( ) , getPointerTy ( DL ) ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT>


<s> MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB .


<s> MachineBasicBlock :: iterator I , Next , Last ; for ( I = MBB . begin ( ) , Last = MBB . end ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : emitIf ( MI ) ; break ; case <STR_LIT> : emitElse ( MI ) ; break ; case <STR_LIT> : emitBreak ( MI ) ; break ; case <STR_LIT> : emitIfBreak ( MI ) ; break ; case <STR_LIT> : emitElseBreak ( MI ) ; break ; case <STR_LIT> : emitLoop ( MI ) ; break ; case <STR_LIT> : emitEndCf ( MI ) ; break ; case


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Addr = N -> getOperand ( <NUM_LIT> ) ; if ( Addr -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; unsigned IntNo = cast < ConstantSDNode > ( Addr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return <NUM_LIT> ; SDValue nextAddr = Addr -> getOperand ( <NUM_LIT> ) ; SDValue CheckEventChainOut ( Addr . getNode ( ) , <NUM_LIT> ) ; if ( ! CheckEventChainOut . use_empty ( ) ) { SDValue CheckEventChainIn = Addr -> getOperand ( <NUM_LIT> ) ; SDValue NewChain = replaceInChain ( CurDAG , Chain , CheckEventChainOut , CheckEventChainIn ) ; if ( ! NewChain . getNode (


<s> RegisterMCAsmInfoFn X ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmInfo ) ; for ( Target * T : { & getThe<ISA_LIT>Target ( ) } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T ,


<s> return getTM < <ISA_LIT>TargetMachine


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> bool useAA ( ) const override { return isCortexA53 ( )


<s> Value * TIdY = Builder . CreateCall ( ReadTIDIGY , { } ) ; Value * TIdZ = Builder . CreateCall ( ReadTIDIGZ , { } ) ; Value * Tmp0 = Builder . CreateMul ( TCntY , TCntZ ) ; Tmp0 = Builder . CreateMul ( Tmp0 , TIdX ) ; Value * Tmp1 = Builder . CreateMul ( TIdY , TCntZ ) ; Value * TID = Builder . CreateAdd ( Tmp0 , Tmp1 ) ; TID = Builder . CreateAdd ( TID , TIdZ ) ; std :: vector < Value * > Indices ; Indices . push_back ( Constant :: getNullValue ( Type :: getInt32Ty ( Mod -> getContext ( ) ) ) ) ; Indices . push_back ( TID ) ; Value * Offset = Builder . CreateGEP ( GVTy , GV , Indices ) ; I . mutateType ( Offset -> getType ( ) ) ; I . replaceAllUsesWith ( Offset ) ; I . eraseFromParent ( ) ; for ( std :: vector < Value * > :: iterator i = WorkList . begin ( ) , e = WorkList . end ( ) ; i != e ; ++ i ) { Value * V = * i ; CallInst * Call = dyn_cast < CallInst > ( V ) ; if ( ! Call ) { Type * EltTy = V -> getType ( ) -> getPointerElementType ( ) ; PointerType * NewTy = PointerType :: get ( EltTy , <ISA_LIT>AS :: LOCAL_ADDRESS ) ; if ( isa < AddrSpaceCastInst > ( V ) ) continue ; V -> mutateType ( NewTy ) ; continue ; } IntrinsicInst * Intr = dyn_cast < IntrinsicInst > ( Call ) ; if ( ! Intr ) { std :: vector < Type * > ArgTypes ; for ( unsigned ArgIdx = <NUM_LIT> , ArgEnd = Call -> getNumArgOperands ( ) ; ArgIdx != ArgEnd ; ++ ArgIdx ) { ArgTypes . push_back ( Call -> getArgOperand ( ArgIdx ) -> getType ( ) ) ; } Function * F = Call -> getCalledFunction ( ) ; FunctionType * NewType = FunctionType :: get ( Call -> getType ( ) , ArgTypes , F -> isVarArg ( ) ) ; Constant * C = Mod -> getOrInsertFunction ( ( F -> getName ( ) + <STR_LIT> ) . str ( ) , NewType , F -> getAttributes ( ) ) ; Function * NewF = cast < Function > ( C ) ; Call -> setCalledFunction ( NewF ) ; continue ; } Builder . SetInsertPoint ( Intr ) ; switch ( Intr -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : Intr -> eraseFromParent ( ) ; continue ; case <STR_LIT> : { MemCpyInst * MemCpy = cast < MemCpyInst


<s> unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: TIDIG_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: TIDIG_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: INPUT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( & Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm


<s> unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } const Function & CF = OF . Candidates . front ( ) . getMF ( ) -> getFunction ( ) ; bool ShouldSignReturnAddr = false ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { StringRef Scope = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( Scope . equals ( <STR_LIT> ) ) ShouldSignReturnAddr = true ; else if ( Scope . equals ( <STR_LIT> ) && ! IsLeafFunction ) ShouldSignReturnAddr = true ; } bool ShouldSignReturnAddrWithAKey = true ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { const StringRef Key = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; assert ( ( Key . equals_lower ( <STR_LIT> ) || Key . equals_lower ( <STR_LIT> ) ) && <STR_LIT> ) ; ShouldSignReturnAddrWithAKey = Key . equals_lower ( <STR_LIT> ) ; } if ( OF . FrameConstructionID == MachineOutlinerTailCall || OF . FrameConstructionID == MachineOutlinerThunk ) { signOutlinedFunction ( MF , MBB , ShouldSignReturnAddr , ShouldSignReturnAddrWithAKey ) ; return ; } if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT> ) ; MachineInstr * ret = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) .


<s> static bool isSoloInstruction ( StringRef Mnemonic ) { return StringSwitch < bool > ( Mnemonic ) . Case (

<STR_LIT> , true ) . Default ( false ) ;


<s> unsigned OperandsToMatch [ ] = { <STR_LIT> :: cpol , <STR_LIT> :: d16 , <STR_LIT> :: unorm , <STR_LIT> :: da , <STR_LIT> :: r128 , <STR_LIT> :: a16 } ; for ( auto op : OperandsToMatch ) { int Idx = <STR_LIT> ( CI . I -> getOpcode ( ) , op ) ; if ( <STR_LIT> ( Paired . I -> getOpcode ( ) , op ) != Idx ) return false ; if ( Idx != - <NUM_LIT> && CI . I -> getOperand ( Idx ) . getImm ( ) != Paired . I -> getOperand ( Idx ) . getImm ( ) ) return false ; } unsigned MaxMask = std :: max ( CI . DMask , Paired . DMask ) ; unsigned MinMask = std :: min ( CI . DMask , Paired . DMask ) ; unsigned AllowedBitsForMin = llvm :: countTrailingZeros


<s> static __inline__ float __fnmsubs ( float x , float y , float z ) { float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r


<s> tree riscv_builtin_decl ( unsigned int code , bool initialize_p


<s> if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i ) break ; ++ SubvecElts ; } assert ( SubvecElts != NumElts && <STR_LIT> ) ; SubvecElts = PowerOf2Floor ( SubvecElts ) ; if ( Zeroable . countLeadingOnes ( ) >= ( NumElts - SubvecElts ) ) { MVT ExtractVT = <STR_LIT> ( <STR_LIT> , SubvecElts ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , Extract , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( NumElts >= <NUM_LIT> || ( Subtarget . hasDQI ( ) && NumElts == <NUM_LIT> ) ) { unsigned Offset = <NUM_LIT> ; for ( SDValue V : { V1 , V2 } ) { unsigned Opcode ; int ShiftAmt = match1BitShuffleAsKSHIFT ( Opcode , Mask , Offset , Zeroable ) ; if ( ShiftAmt >= <NUM_LIT> ) return DAG . getNode ( Opcode , DL , VT , V , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; Offset += NumElts ; } } MVT ExtVT ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> )


<s> if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( OpNo == <NUM_LIT> ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles ,

BranchProbability Probability ) const override {


<s> void MetadataStreamerV4 :: emitTargetID ( const IsaInfo


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( CPUName , FS )


<s> if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax ) { if ( FixupKind == <STR_LIT> ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind


<s> static rtx ix86_erase_embedded_rounding ( rtx pat ) { if ( GET_CODE ( pat ) == INSN ) pat = PATTERN ( pat ) ; gcc_assert ( GET_CODE ( pat ) == PARALLEL ) ; if ( XVECLEN ( pat , <NUM_LIT> ) == <NUM_LIT> ) { rtx p0 = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; rtx p1 = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( p0 ) == SET && GET_CODE ( p1 ) == UNSPEC && XINT ( p1 , <NUM_LIT> ) == UNSPEC_EMBEDDED_ROUNDING ) ; return p0 ; } else { rtx * res = XALLOCAVEC ( rtx , XVECLEN ( pat , <NUM_LIT> ) ) ; int i = <NUM_LIT> ; int j = <NUM_LIT> ; for ( ; i < XVECLEN ( pat , <NUM_LIT> ) ; ++ i ) { rtx elem = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( elem ) != UNSPEC || XINT ( elem , <NUM_LIT> ) != UNSPEC_EMBEDDED_ROUNDING


<s> if ( VT == <STR_LIT> ) retval = <NUM_LIT> ; if ( VT == <STR_LIT> ) retval = <NUM_LIT> ; return retval


<s> bool isBranchTarget ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return true ; int64_t Val = MCE -> getValue ( ) ; if ( Val & <NUM_LIT> ) return false ; assert ( N > <NUM_LIT> && <STR_LIT> ) ; return ( Val >= - ( ( <NUM_LIT> << ( N - <NUM_LIT> ) ) << <NUM_LIT> ) && Val <= ( ( ( <NUM_LIT> << (

N - <NUM_LIT> ) ) - <NUM_LIT> ) << <NUM_LIT> ) ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned


<s> bool Error = AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; if ( Error && ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; if ( ExtraCode [ <NUM_LIT> ] >= 'A' && ExtraCode [ <NUM_LIT> ] <= 'Z' ) { const MachineOperand & RegOp = MI -> getOperand ( OpNum ) ; assert ( RegOp . isReg ( ) && <STR_LIT> <STR_LIT> ) ; unsigned Reg = RegOp . getReg ( ) ; unsigned ByteNumber = ExtraCode [ <NUM_LIT> ] - 'A' ; unsigned OpFlags = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned NumOpRegs = InlineAsm :: getNumOperandRegisters ( OpFlags ) ; ( void ) NumOpRegs ; const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; unsigned BytesPerReg = TRI . getMinimalPhysRegClass ( Reg ) -> getSize ( ) ; assert ( BytesPerReg <= <NUM_LIT> && <STR_LIT> ) ; unsigned RegIdx = ByteNumber / BytesPerReg ; assert ( RegIdx < NumOpRegs && <STR_LIT> ) ; Reg = MI -> getOperand ( OpNum + RegIdx ) . getReg ( ) ; if ( BytesPerReg == <NUM_LIT> ) { Reg = TRI . getSubReg ( Reg , ByteNumber % BytesPerReg ? <STR_LIT>


<s> vst2_p64 ( poly64_t * __a , poly64x1x2_t val ) { __builtin_aarch64_simd_oi __o ; poly64x2x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p64 ( val . val [ <NUM_LIT> ] , vcreate_p64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p64 ( val . val [ <NUM_LIT> ] , vcreate_p64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di_ssps ( __o , ( poly64x2_t ) temp .


<s> AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < MachineDominatorTree


<s> void <ISA_LIT>InstPrinter :: printDA ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo


<s> return <STR_LIT> . hasSubClassEq ( RC


<s> } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; updateValueMap ( II , DestReg ) ; return true ; } } return false ; } case <STR_LIT> : case <STR_LIT> : { const auto * MTI = cast < MemTransferInst > ( II ) ; if ( MTI -> isVolatile ( ) )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAtomicAddr ( SDNode * ParentAtomic , SDValue Addr , SDValue & Segment , SDValue & Order , SDValue & Scope , SDValue & Equiv , SDValue & Base , SDValue & Reg , SDValue & Offset ) const { if ( ! SelectAddr ( Addr , Base , Reg , Offset ) ) return false ; const AtomicSDNode * Atomic = cast < AtomicSDNode > ( ParentAtomic ) ; AtomicOrdering SuccOrder = Atomic -> getSuccessOrdering ( ) ; SynchronizationScope SyncScope = Atomic -> getSynchScope ( ) ; unsigned AS = Atomic -> getAddressSpace ( ) ; SDLoc SL ( ParentAtomic ) ; Segment = CurDAG -> getTargetConstant ( AS , SL , <STR_LIT> ) ; Order = CurDAG -> getTargetConstant ( getBrigMemoryOrder ( SuccOrder ) , SL , <STR_LIT> ) ; Scope = CurDAG -> getTargetConstant ( getBrigMemoryScope ( SyncScope , AS ) , SL , <STR_LIT> ) ; Equiv = CurDAG -> getTargetConstant ( <NUM_LIT> , SL


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg


<s> addPass ( & <ISA_LIT>FoldOperandsID ) ; if ( EnableDPPCombine ) addPass ( & GCNDPPCombineID ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( & <ISA_LIT>LoadStoreOptimizerID ) ; if ( EnableSDWAPeephole ) { addPass ( & <ISA_LIT>PeepholeSDWAID ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & <ISA_LIT>FoldOperandsID ) ; addPass ( &


<s> SDValue <ISA_LIT>TargetLowering :: lowerFCOPYSIGN ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget . isGP64bit ( ) ) return lowerFCOPYSIGN64 ( Op , DAG , Subtarget . hasExtractInsert ( ) ) ; return lowerFCOPYSIGN32 ( Op , DAG , Subtarget


<s> const <ISA_LIT>ArchEnum & get<ISA_LIT>ArchVersion ( ) const { return <ISA_LIT>ArchVersion


<s> static int mcore_ior_cost ( rtx x ) { HOST_WIDE_INT val ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) )


<s> int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( spOffset < <NUM_LIT> ) ? ( stackSize - spOffset ) : ( spOffset + <NUM_LIT> ) ; Offset += MI . getOperand ( oi ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( oi ) . ChangeToImmediate ( Offset ) ; MI . getOperand ( i ) . ChangeToRegister ( getFrameRegister ( MF ) , false ) ; return <NUM_LIT>


<s> unsigned getGlobalBaseReg ( ) const { return