<s> int ImmSize = <STR_LIT> ( TSFlags ) ? <STR_LIT> ( TSFlags ) : <NUM_LIT> ; EmitImmediate ( Disp , <NUM_LIT> , MCFixupKind ( FixupKind ) , CurByte , OS , Fixups , - ImmSize ) ; return ; } unsigned BaseRegNo = BaseReg ? Get<ISA_LIT>RegNum ( Base ) : - <NUM_LIT> ; if ( IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! Is64BitMode || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_4 , CurByte , OS , Fixups ) ; return ; } if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; return ; } if ( Disp . isImm ( ) && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ; return ; } EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_4 , CurByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( ! Disp . isImm ( ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } else if ( isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp8 = true ; } else { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; if ( BaseReg == <NUM_LIT>


<s> unsigned getMetadataOrNullID ( const Metadata * MD ) const { return MetadataMap . lookup ( MD


<s> return convReg ( BusyRegs [ REG_OFFSET_ADDRESS ] , VT


<s> assert ( getStreamer ( ) . Contents . empty ( ) && <STR_LIT> ) ; CurrentVendor =


<s> insn = next_real_insn ( insn ) ; last_call = prev = NULL ; prev_clock = - <NUM_LIT> ; earliest_bb_end = <NUM_LIT> ; prev_implicit_nops = <NUM_LIT> ; first = true ; while ( insn ) { int this_clock = - <NUM_LIT> ; rtx_insn * next ; int max_cycles = <NUM_LIT> ; next = next_real_insn ( insn ) ; if ( DEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || shadow_or_blockage_p ( insn ) || JUMP_TABLE_DATA_P ( insn ) ) goto next_insn ; if ( ! c6x_flag_schedule_insns2 ) PUT_MODE ( insn , TImode ) ; else { int cycles ; this_clock = insn_get_clock ( insn ) ; if ( this_clock != prev_clock ) { PUT_MODE ( insn , TImode ) ; if ( ! first ) { cycles = this_clock - prev_clock ; cycles -= prev_implicit_nops ; if ( cycles > <NUM_LIT> ) { rtx nop = emit_nop_after ( cycles - <NUM_LIT> , prev ) ; insn_set_clock ( nop , prev_clock + prev_implicit_nops + <NUM_LIT> ) ; } } prev_clock = this_clock ; if ( last_call && insn_get_clock ( last_call ) + <NUM_LIT> <= this_clock ) { emit_label_before ( call_labels [ INSN_UID ( last_call ) ] , insn ) ; last_call = NULL_RTX ; } prev_implicit_nops = <NUM_LIT> ; } } if ( recog_memoized ( insn ) >= <NUM_LIT> && ( c6x_flag_schedule_insns2 || ! returning_call_p ( insn ) ) ) { max_cycles = get_attr_cycles ( insn ) ; if ( get_attr_type ( insn ) == TYPE_CALLP ) prev_implicit_nops = <NUM_LIT> ; } else max_cycles = <NUM_LIT> ; if ( returning_call_p ( insn ) ) last_call = insn ; if ( c6x_flag_schedule_insns2 ) { gcc_assert ( this_clock >= <NUM_LIT> ) ; if ( earliest_bb_end < this_clock + max_cycles ) earliest_bb_end = this_clock + max_cycles ; } else if ( max_cycles > <NUM_LIT> ) emit_nop_after ( max_cycles - <NUM_LIT> , insn ) ; prev = insn ; first = false ; next_insn : if ( c6x_flag_schedule_insns2 && ( next == NULL_RTX || ( GET_MODE ( next ) == TImode && INSN_INFO_ENTRY ( INSN_UID ( next ) ) . ebb_start ) ) && earliest_bb_end > <NUM_LIT> ) { int cycles = earliest_bb_end - prev_clock ; if ( cycles > <NUM_LIT> ) { prev = emit_nop_after ( cycles - <NUM_LIT> , prev ) ; insn_set_clock ( prev , prev_clock + prev_implicit_nops + <NUM_LIT> ) ; } earliest_bb_end =


<s> for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned tt = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; if ( invSrc ) { MIB = BuildMI ( newMBB , dl , TII -> get ( notOpc ) , tt ) . addReg ( t1 ) ; } else tt = t1 ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; assert ( ( argOpers [ valArgIndx ] -> isReg ( ) || argOpers [ valArgIndx ] -> isImm ( ) ) && <STR_LIT> ) ; if ( argOpers [ valArgIndx ] -> isReg ( ) ) MIB = BuildMI ( newMBB , dl , TII -> get ( regOpc ) , t2 ) ; else MIB = BuildMI ( newMBB , dl , TII -> get ( immOpc ) , t2 ) ; MIB . addReg ( tt ) ; ( * MIB ) . addOperand ( * argOpers [ valArgIndx ] ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( copyOpc ) , EAXreg ) ; MIB . addReg ( t1 ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( CXchgOpc ) ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MIB . addReg ( t2 ) ; assert ( bInstr -> hasOneMemOperand ( ) && <STR_LIT> ) ; ( * MIB ) . setMemRefs ( bInstr -> memoperands_begin ( ) , bInstr -> memoperands_end ( ) ) ; MIB = BuildMI ( newMBB , dl , TII -> get ( copyOpc ) , destOper . getReg ( ) ) ; MIB . addReg ( EAXreg ) ; BuildMI ( newMBB , dl , TII -> get ( <STR_LIT>


<s> ZeroOperandPosition = I -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - <NUM_LIT> ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ; } else { for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . addOperand ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( *


<s> bool SPScope :: isTopLevel ( ) const { return ( NULL == Priv ->


<s> SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) { return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; } else { MVT ResVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( VT . getVectorNumElements ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + VT . getVectorNumElements ( ) ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getNode ( <STR_LIT> , DL , ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + VT . getVectorNumElements ( ) / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + VT . getVectorNumElements ( ) * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getNode ( <STR_LIT> , DL , ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedVT . getSizeInBits ( ) , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT>


<s> return new <ISA_LIT>CodeGenPrepare ( TM


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>Target64


<s> return ( vector float ) __builtin_altivec_vlogefp (


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Reg != <STR_LIT> ) return Reg ; report_fatal_error ( Twine ( <STR_LIT> + StringRef (


<s> fntype = TREE_TYPE ( * node ) ; if ( TREE_CODE ( * node ) == VAR_DECL || TREE_CODE ( * node ) == TYPE_DECL ) decl = * node ; } else fntype = * node ; while ( fntype && TREE_CODE ( fntype ) == POINTER_TYPE ) fntype = TREE_TYPE ( fntype ) ; if ( ( DECL_P ( * node ) && ! decl ) || TREE_CODE ( fntype ) != FUNCTION_TYPE ) { warning ( OPT_Wattributes , <STR_LIT> <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ; } * no_add_attrs |= cmse_func_args_or_return_in_stack ( NULL , name , fntype ) ; if ( * no_add_attrs ) return NULL_TREE ; if ( decl ) { type = build_distinct_type_copy ( TREE_TYPE ( decl ) ) ; TREE_TYPE ( decl ) = type ; } else { type = build_distinct_type_copy ( * node ) ; * node = type ; } fntype = type ; while ( TREE_CODE ( fntype ) != FUNCTION_TYPE ) { type =


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo

, uint64_t Addr , const void * Decoder ) {


<s> enum rtx_code code0 ; enum rtx_code code1 ; while ( GET_CODE ( xplus0 ) == SUBREG ) xplus0 = SUBREG_REG ( xplus0 ) ; code0 = GET_CODE ( xplus0 ) ; while ( GET_CODE ( xplus1 ) == SUBREG ) xplus1 = SUBREG_REG ( xplus1 ) ; code1 = GET_CODE ( xplus1 ) ; if ( code0 != REG && code1 == REG ) { xplus0 = XEXP ( addr ,


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> )


<s> MVT ExtVecVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT ExtEltVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> ,


<s> for ( auto II : instToExp -> users ( ) ) { if ( auto a = dyn_cast < PHINode > ( II ) ) continue ; std :: vector < const Instruction * > :: iterator it = std :: find ( fillVector -> begin ( ) , fillVector -> end ( ) , dyn_cast < Instruction > ( II ) ) ; if ( it != fillVector -> end ( ) ) continue ; fillVector -> push_back ( dyn_cast < Instruction > ( II ) ) ; fullmap ( dyn_cast < Instruction > (


<s> ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ; return ( CN != <NUM_LIT> && isI16IntS10Immediate


<s> MachineFunctionPass * llvm :: create<ISA_LIT>GenerateDecorationsPass (


<s> MVT EltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; assert ( EltVT == Src . getSimpleValueType ( ) . getVectorElementType ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Lo = extractSubVector ( Src , <NUM_LIT> , DAG ,


<s> const uint64_t V = getType ( MI ) ; return <STR_LIT> <= V &&


<s> return __builtin_ia32_scalefsh_mask_round ( __A , __B , _mm_setzero_ph ( ) , (


<s> bool Changed = false ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { if ( ! I -> hasLocalLinkage ( ) || I -> isThreadLocal ( ) || I -> hasSection ( ) ) continue ; unsigned Alignment = I -> getAlignment ( ) ; Type * Ty = I -> getType ( ) -> getElementType ( ) ; if ( Alignment > TD -> getABITypeAlignment ( Ty ) ) continue ; if ( I -> getName ( ) . startswith ( <STR_LIT> ) || I -> getName ( ) . startswith ( <STR_LIT> ) ) continue ; if ( TD -> getTypeAllocSize ( Ty ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( BSSGlobals ,


<s> if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; return <STR_LIT> ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT

( ) ) ) && is64Bit ( ) ) return <STR_LIT> ;


<s> static DecodeStatus DecodePredRegsRegisterClass ( MCInst & Inst , unsigned RegNo ,

uint64_t , const MCDisassembler * Decoder ) {


<s> for ( GlobalVariable & GV : M . globals ( ) ) { unsigned AS = GV . getAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: REGION_ADDRESS ) || ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && ( ! <ISA_LIT>TargetMachine :: EnableLowerModuleLDS || ! GV . hasInitializer ( ) ) ) ) recursivelyVisitUsers ( GV , FuncsToAlwaysInline ) ; } if ( ! <ISA_LIT>TargetMachine :: EnableFunctionCalls || StressCalls ) { auto IncompatAttr = StressCalls ? Attribute :: AlwaysInline : Attribute :: NoInline ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( IncompatAttr ) ) { if ( StressCalls ) { if ( ! FuncsToAlwaysInline . count ( & F ) ) FuncsToNoInline . insert


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode == CODE_FOR_ctrdi_internal2 ||

icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ;


<s> std :: unique_ptr < MCSubtargetInfo > STI ( TM . getTarget ( ) . createMCSubtargetInfo ( TM . getTargetTriple ( ) . str ( ) , TM . getTargetCPU ( ) , TM . getTargetFeatureString ( ) ) ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TS -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ; <STR_LIT> ISA = <STR_LIT> ( STI -> getFeatureBits ( ) ) ; TS -> EmitDirectiveHSACodeObjectISA ( ISA . Major , ISA . Minor , ISA . Stepping , <STR_LIT> , <STR_LIT> ) ; TS -> EmitRuntimeMetadata


<s> Inst . addOperand ( MCOperand :: CreateImm ( imm << <NUM_LIT> ) ) ; return MCDisassembler :: Success


<s> return ( __m128bh ) __builtin_ia32_cvtne2ps2bf16_v8hi ( __A ,


<s> static bool isSimpleShift ( SDValue N , unsigned & ShiftVal ) { ConstantSDNode * Shift = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Shift )


<s> auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Cond ) ; ( void ) SetI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; SetI -> dump ( ) ) ; ++ NumSetCCsInserted ; return Reg


<s> static int getKindID ( ) { if ( KindID == <NUM_LIT> ) KindID

= llvm :: getNextAvailablePluginDiagnosticKind ( ) ;


<s> void incNumLocalDynamicTLSAccesses ( ) { ++


<s> return getSubtargetImpl ( ) -> getSelectionDAGInfo


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( *


<s> Value * ExtRes = Builder . CreateCall ( I32 , { ExtOp } ) ; Value * LShrOp = Builder . CreateLShr ( ExtRes , <NUM_LIT> - getBaseElementBitWidth ( I . getType ( ) ) ) ; Value * TruncRes = Builder . CreateTrunc ( LShrOp , I . getType ( ) ) ; I . replaceAllUsesWith ( TruncRes ) ; I . eraseFromParent ( ) ; return true


<s> bool add_note = false ; if ( ! NONJUMP_INSN_P ( insn ) || NEXT_INSN ( insn ) ) add_note = true ; else { rtx set = single_set ( insn ) ; if ( set == NULL_RTX || SET_DEST ( set ) != end_addr || GET_CODE ( SET_SRC ( set ) ) != PLUS || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != stack_pointer_rtx || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != rs ) add_note = true ; } insn = emit_insn ( insn ) ; if ( add_note ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( end_addr , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , rs ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( TARGET_64BIT ) retval = emit_insn ( gen_probe_stack_rangedi ( stack_pointer_rtx , stack_pointer_rtx , orig_sp , end_addr ) ) ; else retval = emit_insn ( gen_probe_stack_rangesi ( stack_pointer_rtx , stack_pointer_rtx , orig_sp , end_addr ) ) ; RTX_FRAME_RELATED_P ( retval ) = <NUM_LIT> ; add_reg_note ( retval , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , end_addr ) ) ; emit_insn ( gen_blockage ( ) ) ; dump_stack_clash_frame_info ( PROBE_LOOP , rounded_size !=


<s> case <STR_LIT> : case <STR_LIT> : if ( ! isVGPR ( Src2 , TRI , MRI ) || TII -> hasModifiersSet ( MI , <STR_LIT> :: src2_modifiers ) ) return false ; break ; case <STR_LIT> : break ; } } const MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 && ( ! isVGPR ( Src1 , TRI , MRI ) || TII -> hasModifiersSet ( MI

, <STR_LIT> :: src1_modifiers ) ) ) return false ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved <


<s> assert ( Load -> getMemoryVT ( ) == Store -> getMemoryVT ( ) && <STR_LIT> ) ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; if ( Size > <NUM_LIT> && Size <= <NUM_LIT> ) { if ( Load -> getBasePtr ( ) . getOpcode ( ) == <STR_LIT> ) return false ; if ( Store -> getBasePtr ( ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( Load -> isInvariant ( ) ) return true ; if ( Load -> getAlignment ( ) >= Size && Store -> getAlignment ( ) >= Size ) return true ; const Value * V1 = Load -> getSrcValue ( ) ; const Value * V2 = Store -> getSrcValue ( ) ; if ( ! V1 || ! V2 ) return false ; int64_t End1 = Load -> getSrcValueOffset ( ) + Size ; int64_t End2 = Store -> getSrcValueOffset ( )


<s> case MI : return <STR_LIT> ; case PL : return <STR_LIT> ; case VS : return <STR_LIT> ; case VC : return <STR_LIT> ; case HI : return <STR_LIT> ; case LS : return <STR_LIT> ; case GE : return <STR_LIT> ; case LT : return <STR_LIT> ; case GT : return <STR_LIT> ; case LE : return <STR_LIT> ; case AL : return <STR_LIT> ; case NV :


<s> if ( m68k_read_tp == NULL_RTX ) m68k_read_tp = init_one_libfunc ( <STR_LIT> ) ; return


<s> void GCNPassConfig :: addFastRegAlloc ( ) { insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID , false ) ; insertPass ( & RegisterCoalescerID , & <ISA_LIT>PreAllocateWWMRegsID , false ) ; TargetPassConfig :: addFastRegAlloc (


<s> const unsigned Scale = V0EltSize / EltSize ; const unsigned V0BroadcastIdx = BroadcastIdx / Scale ; if ( ( V0Opc != <STR_LIT> || V0BroadcastIdx != <NUM_LIT> ) && V0Opc != <STR_LIT> ) return SDValue ( ) ; SDValue Scalar = V0 . getOperand ( V0BroadcastIdx ) ; if ( const int OffsetIdx = BroadcastIdx % Scale ) Scalar = DAG . getNode ( <STR_LIT> , DL , Scalar . getValueType ( ) , Scalar , DAG . getConstant

( OffsetIdx * EltSize , DL , <STR_LIT> ) ) ;


<s> if ( TargetTriple . getArch ( ) == Triple :: nios2 ) { if ( CPU != <STR_LIT> ) { CPU = <STR_LIT> ; <ISA_LIT>ArchVersion = <ISA_LIT>r1 ; } else { <ISA_LIT>ArchVersion = <ISA_LIT>r2 ; } } else { errs ( ) << <STR_LIT> << TargetTriple . getArch ( ) << <STR_LIT> << CPU << <STR_LIT> ; exit ( <NUM_LIT> ) ; } ParseSubtargetFeatures ( CPU , FS ) ; return *


<s> NVVMIntrRange ( unsigned int SmVersion ) : FunctionPass ( ID ) , SmVersion


<s> for ( Argument & Arg : F . args ( ) ) if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . hasByValAttr


<s> unsigned Opc = II -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; Register BasePtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Opc == <STR_LIT> ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; Register NewDestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const <ISA_LIT>InstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TII -> copyPhysReg ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , NewDestReg , BasePtr , MI . getOperand ( <NUM_LIT> )


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i

!= e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> unsigned * cost = XNEWVEC ( unsigned , <NUM_LIT> ) ; cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned


<s> return __builtin_aarch64_lroundhfdi (


<s> case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG , * this ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return LowerFNEGorFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : case


<s> } Start = Tok . getLoc ( ) ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , End ) ; unsigned RegNo = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) { return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; } return <STR_LIT> ( RegNo , Start , End ) ; } return ParseIntelSegmentOverride ( RegNo , Start , Size ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( <NUM_LIT> , Start , <NUM_LIT> , false , Size ) ; AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; bool isSymbol = SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) != MCExpr :: Constant ; int64_t Imm = SM . getImm ( ) ; if ( SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) == MCExpr :: Constant ) SM . getSym ( ) -> evaluateAsAbsolute ( Imm ) ; if ( StartTok . isNot ( AsmToken :: Identifier ) && StartTok . isNot ( AsmToken :: String ) && isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> emplace_back ( AOK_ImmPrefix , Start ) ; else InstInfo -> AsmRewrites -> emplace_back ( AOK_Imm , Start , Len , Imm ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( isSymbol ) { if ( isParsingInlineAsm ( ) ) return CreateMemForInlineAsm ( <NUM_LIT> , SM . getSym ( ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , SM . getSym ( ) , Start , End , Size ) ; } const MCExpr * ImmExpr = MCConstantExpr :: create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand (


<s> MachineOperand & Dest = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; bool IsADDIInstRequired = ! useSameRegister ( Dest , TrueValue ) ; bool IsORIInstRequired = ! useSameRegister ( Dest , FalseValue ) ; if ( ! IsADDIInstRequired && ! IsORIInstRequired ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumRemoved ++ ; ( * MI ) -> eraseFromParent ( ) ; MI = BIL . erase ( MI ) ; continue ; } if ( useSameRegister ( TrueValue , FalseValue ) && ( BIL . size ( ) == <NUM_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumFolded ++ ; BuildMI ( * MBB , ( * MI ) , dl , TII -> get ( isISEL8 ( * * MI ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; ( * MI ) -> eraseFromParent ( ) ; MI = BIL . erase


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { O << <STR_LIT> << ( Op . getImm ( ) * <NUM_LIT> ) ; return ; } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; }


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo


<s> const <ISA_LIT>InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Next = I -> getNextNode (


<s> FunctionPass * llvm :: create<ISA_LIT>OptimizeSZextends ( ) { return new <ISA_LIT>OptimizeSZextends


<s> V = rotr32 ( ~ <NUM_LIT> , getSOImmValRotate ( V ) ) & V ; assert ( V == ( rotr32 ( <NUM_LIT> , getSOImmValRotate


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx


<s> if ( Def -> getOpcode ( ) == <STR_LIT> ) continue ; bool SameBlock = Def -> getParent ( ) == & MBB ; bool CanMove = SameBlock && isSafeToMove ( Def , Insert , AA , MRI ) && ! TreeWalker . isOnStack ( Reg ) ; if ( CanMove && hasOneUse ( Reg , Def , MRI , MDT , LIS ) ) { Insert = moveForSingleUse ( Reg , Op , Def , MBB , Insert , LIS , MFI , MRI ) ; } else if ( shouldRematerialize ( * Def , AA , TII ) ) { Insert = rematerializeCheapDef ( Reg , Op , * Def , MBB , Insert -> getIterator ( ) , LIS , MFI , MRI , TII , TRI ) ; } else if ( CanMove && oneUseDominatesOtherUses ( Reg , Op , MBB , MRI , MDT , LIS , MFI ) ) { Insert = moveAndTeeForMultiUse ( Reg , Op , Def , MBB , Insert , LIS , MFI , MRI , TII ) ; } else { if ( ! CanMove && SameBlock ) Commuting . maybeCommute ( Insert , TreeWalker , TII ) ; continue ; } if ( Insert -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) convertImplicitDefToConstZero ( Insert , MRI , TII , MF , LIS ) ; Commuting . reset ( ) ; TreeWalker . pushOperands ( Insert ) ; } if ( Insert != & * MII ) { imposeStackOrdering ( & * MII ) ; MII = MachineBasicBlock :: iterator ( Insert ) . getReverse ( ) ; Changed = true ; } } } if ( Changed ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) MBB . addLiveIn (


<s> } auto I = <STR_LIT> ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) , FI ) . addImm ( Mask ) . setMIFlag ( MachineInstr :: FrameSetup ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const MachineRegisterInfo & RI = MF . getRegInfo ( ) ; for ( const auto & Info : CSI ) { Register Reg = Info . getReg ( ) ; bool IsLiveIn = RI . isLiveIn


<s> unsigned Val = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( <STR_LIT> ( Val ) == <STR_LIT> && <STR_LIT> ( Val )


<s> switch ( Ty . getTag ( ) ) { case dwarf :: DW_TAG_pointer_type : TypeNo = TypeNo << <STR_LIT> ; TypeNo = TypeNo | <STR_LIT> ; break ; default : TypeNo = TypeNo << <STR_LIT>


<s> void ix86_emit_i387_asinh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx cst1 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_mulxf3 ( e1 , op1 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , cst1 ) ) ; emit_insn ( gen_sqrtxf2 ( e2 , e2 ) ) ; emit_insn ( gen_addxf3 ( e2 , e2 , cst1 ) ) ; emit_insn ( gen_divxf3 ( e1 , e1 , e2 ) ) ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , op1 ) ) ; emit_insn ( gen_addxf3 ( e1 , e1 , e2 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label (


<s> if ( CONST_OK_FOR_N ( disp ) ) { * spill_fill_data . prev_addr [ iter ] = gen_rtx_POST_MODIFY ( DImode , spill_fill_data . iter_reg [ iter ] , gen_rtx_PLUS ( DImode , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; REG_NOTES ( spill_fill_data . prev_insn [ iter ] ) = gen_rtx_EXPR_LIST ( REG_INC , spill_fill_data . iter_reg [ iter ] , REG_NOTES ( spill_fill_data . prev_insn [ iter ] ) ) ; } else { if ( ! CONST_OK_FOR_I ( disp ) ) { rtx tmp = gen_rtx_REG ( DImode , next_scratch_gr_reg ( ) ) ; emit_move_insn ( tmp , disp_rtx ) ; disp_rtx = tmp ; } emit_insn ( gen_adddi3 ( spill_fill_data . iter_reg [ iter ] , spill_fill_data . iter_reg [ iter ] , disp_rtx ) ) ; } } else if ( disp == <NUM_LIT> && spill_fill_data . init_reg [ iter ] == stack_pointer_rtx && frame_pointer_needed ) { mem = gen_rtx_MEM ( GET_MODE ( reg


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~ <NUM_LIT> ; if ( MCELFStreamer * MES = dyn_cast < MCELFStreamer > ( & Parser . getStreamer ( ) ) ) MES -> getAssembler ( ) . setELFHeaderEFlags ( ELF


<s> if ( CurrentArgIndex == Args [ i ] . OrigArgIndex ) { Out . back ( ) ++ ; } else { Out . push_back


<s> const TargetSubtargetInfo & STM = MF . getSubtarget ( ) ; TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( STM . getRegisterInfo ( ) ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( STM


<s> <ISA_LIT>GOTEntry * <ISA_LIT>GOT :: createGOT ( ) { <ISA_LIT>GOTEntry * entry = new <ISA_LIT>GOTEntry ( <NUM_LIT> , NULL ) ; m_GOT . push_back (


<s> return MF . getFrameInfo ( ) . hasStackObjects ( ) || MF

. getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI , StringRef CPU ) { return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI , CPU


<s> MCAsmParser & getParser ( ) const { return Parser


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } O << getRegisterName (


<s> if ( OpVT . getVectorElementType ( ) == <STR_LIT> ) return insert1BitVector ( Op , DAG , Subtarget ) ; assert ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && <STR_LIT> ) ; if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , false ) ) return Ld ; } } if ( auto * Ld = dyn_cast < LoadSDNode > ( peekThroughOneUseBitcasts ( SubVec2 ) ) ) { if ( SubVec2 == SubVec && <STR_LIT> ( Ld ) && areOnlyUsersOf ( SubVec2 . getNode ( ) , { Op , Vec } ) ) { return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec ) ; } } if ( SubVec . getOpcode ( ) == <STR_LIT> && SubVec == SubVec2 ) { return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec . getOperand ( <NUM_LIT> ) ) ; } } } if ( SubVecVT . is128BitVector ( ) ) return insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( SubVecVT . is256BitVector ( ) ) return insert256BitVector ( Vec , SubVec , IdxVal ,


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) operands [ <NUM_LIT> ] = copy_to_mode_reg ( GET_MODE ( operands [

<NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ;


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo


<s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned e = ( isTwoAddr ? <STR_LIT> + <NUM_LIT> : <STR_LIT> ) ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; if ( NumOps > e && MI . getOperand ( e ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( e ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; for ( ; i != e ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <STR_LIT> ( MO . getReg ( ) ) ) REX |= <NUM_LIT> << Bit ; Bit ++ ; } } break ; } default : if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned e = NumOps ; i != e ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) )


<s> if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~


<s> void EmitByte ( unsigned char C , raw_ostream &


<s> if ( d -> perm [ i ] != i + nelt ) ident2 = false ; } else { dsecond . perm [ i ] = <NUM_LIT> ; dfirst . perm [ i ] = d -> perm [ i ] ; if ( d -> perm [ i ] != i ) ident1 = false ; } if ( two_insn && ! ident1 && ! ident2 ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( dfirst . perm [ i ] == <NUM_LIT> ) { if ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> && dfirst . perm [ i ^ ( nelt / <NUM_LIT> ) ] != <NUM_LIT> ) dfirst . perm [ i ] = dfirst . perm [ i ^ ( nelt / <NUM_LIT> ) ] ^ ( nelt / <NUM_LIT> ) ; else dfirst . perm [ i ] = i ; } else { if ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> && dsecond . perm [ i ^ ( nelt / <NUM_LIT> ) ] != <NUM_LIT> ) dsecond . perm [ i ] = dsecond . perm [ i ^ ( nelt / <NUM_LIT> ) ] ^ ( nelt / <NUM_LIT> ) ; else dsecond . perm [ i ] = i ; } if ( ! d -> testing_p ) { if ( ! ident1 ) dfinal . op0 = dfirst . target = gen_reg_rtx ( d -> vmode ) ; if ( ! ident2 ) dfinal . op1 = dsecond . target = gen_reg_rtx ( d -> vmode ) ; } bool ok ; rtx_insn * seq1 = NULL , * seq2 = NULL ; if ( ! ident1 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dfirst ) ; seq1 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( ! ident2 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dsecond ) ; seq2 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( d -> testing_p ) return true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) dfinal . perm [ i ] = ( d -> perm [ i ] >= nelt ? i + nelt : i ) ; emit_insn ( seq1 )


<s> Insn . push_back ( { <STR_LIT> , <NUM_LIT> , Encoding } ) ; unsigned ShiftAmt = <NUM_LIT> ; uint64_t Imm16 = <NUM_LIT> ; for ( ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } Insn . push_back ( { <STR_LIT> , Imm16 , <STR_LIT> ( <STR_LIT> , ShiftAmt ) } ) ; if ( CountThree ) return true ; for ( ShiftAmt += <NUM_LIT> ; ShiftAmt < <NUM_LIT> ; ShiftAmt += <NUM_LIT> ) { Imm16 = ( UImm >> ShiftAmt ) & <NUM_LIT> ; if ( Imm16 != ChunkVal ) break ; } Insn . push_back ( { <STR_LIT> , Imm16 , <STR_LIT> ( <STR_LIT> ,


<s> const AMDGPUSubtarget & ST = F . getTarget ( ) . getSubtarget < AMDGPUSubtarget > ( ) ; uint32_t FP32Denormals = ST . hasFP32Denormals ( ) ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ; uint32_t FP64Denormals = ST . hasFP64Denormals ( ) ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ; return FP_ROUND_MODE_SP ( FP_ROUND_ROUND_TO_NEAREST ) | FP_ROUND_MODE_DP ( FP_ROUND_ROUND_TO_NEAREST ) | FP_DENORM_MODE_SP ( FP32Denormals ) | FP_DENORM_MODE_DP


<s> unsigned MyPredReg = <NUM_LIT> ; if ( ! MI ) return false ; if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes

&& llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> bool hasDispatchPtr ( ) const { return DispatchPtr


<s> __builtin_sh_media_PREFO ( mm + s , <NUM_LIT> , <NUM_LIT>


<s> if ( Disable<ISA_LIT>LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; if ( MF . getFunction ( ) -> optForMinSize ( ) ) Changed |= removeRedundantLEAs ( LEAs ) ; Changed |= removeRedundantAddrCalc ( LEAs


<s> } unsigned ScalarStoreOp ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; if ( SpillToSMEM && isSGPRClass ( RC ) ) { std :: tie ( EltSize , ScalarStoreOp ) = getSpillEltSize ( getRegSizeInBits ( * RC ) / <NUM_LIT> , true ) ; } ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { unsigned SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToSMEM ) { int64_t FrOffset = FrameInfo . getObjectOffset ( Index ) ; unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; int64_t Offset = ( ST . getWavefrontSize ( ) * FrOffset ) + ( EltSize * i ) ; if ( Offset != <NUM_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( Offset ) ; } else { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( MFI -> getFrameOffsetReg ( ) ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( ScalarStoreOp ) ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( OffsetReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; continue ; } if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII ->

get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , SubKillState ) ;


<s> if ( in_p ) sri -> icode = ( TARGET_64BIT ? CODE_FOR_reloaddi_la_in : CODE_FOR_reloadsi_la_in ) ; else sri -> icode = ( TARGET_64BIT ? CODE_FOR_reloaddi_la_out : CODE_FOR_reloadsi_la_out ) ; } } if ( TARGET_Z10 ) { HOST_WIDE_INT offset ; rtx symref ; if ( in_p && s390_loadrelative_operand_p ( x , & symref , & offset ) && mode == Pmode && ! SYMBOL_FLAG_NOTALIGN2_P ( symref ) && ( offset & <NUM_LIT> ) == <NUM_LIT> ) sri -> icode = ( ( mode == DImode ) ? CODE_FOR_reloaddi_larl_odd_addend_z10 : CODE_FOR_reloadsi_larl_odd_addend_z10 ) ; if ( MEM_P ( x ) && s390_loadrelative_operand_p ( XEXP ( x , <NUM_LIT> ) , NULL , NULL ) && ( mode == QImode || ! reg_class_subset_p ( rclass , GENERAL_REGS ) || GET_MODE_SIZE ( mode ) > UNITS_PER_WORD || ! s390_check_symref_alignment ( XEXP ( x , <NUM_LIT> ) , GET_MODE_SIZE ( mode ) ) ) ) { case M ## mode : \ if ( TARGET_64BIT ) \ sri -> icode = in_p ? CODE_FOR_reload ## m ## di_toreg_z10 : \ CODE_FOR_reload ## m ## di_tomem_z10 ; \ else \ sri -> icode = in_p ? CODE_FOR_reload ## m ## si_toreg_z10 : \ CODE_FOR_reload ## m ## si_tomem_z10 ; \ break ; switch ( GET_MODE ( x ) ) { __SECONDARY_RELOAD_CASE ( QI , qi ) ; __SECONDARY_RELOAD_CASE ( HI , hi ) ; __SECONDARY_RELOAD_CASE ( SI , si ) ; __SECONDARY_RELOAD_CASE ( DI , di ) ; __SECONDARY_RELOAD_CASE ( TI , ti ) ; __SECONDARY_RELOAD_CASE ( SF , sf ) ; __SECONDARY_RELOAD_CASE ( DF , df ) ; __SECONDARY_RELOAD_CASE ( TF , tf ) ; __SECONDARY_RELOAD_CASE ( SD , sd ) ; __SECONDARY_RELOAD_CASE ( DD , dd ) ; __SECONDARY_RELOAD_CASE ( TD , td ) ; __SECONDARY_RELOAD_CASE ( V1QI , v1qi ) ; __SECONDARY_RELOAD_CASE ( V2QI , v2qi ) ; __SECONDARY_RELOAD_CASE ( V4QI , v4qi ) ; __SECONDARY_RELOAD_CASE ( V8QI , v8qi ) ; __SECONDARY_RELOAD_CASE ( V16QI , v16qi ) ; __SECONDARY_RELOAD_CASE ( V1HI , v1hi ) ; __SECONDARY_RELOAD_CASE ( V2HI , v2hi ) ; __SECONDARY_RELOAD_CASE ( V4HI , v4hi ) ; __SECONDARY_RELOAD_CASE ( V8HI , v8hi ) ; __SECONDARY_RELOAD_CASE ( V1SI , v1si ) ; __SECONDARY_RELOAD_CASE ( V2SI , v2si ) ; __SECONDARY_RELOAD_CASE ( V4SI , v4si ) ; __SECONDARY_RELOAD_CASE ( V1DI


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT>


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid


<s> const SDValue Ops [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , PtrLo , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , PtrHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DataLo , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DataHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; return DAG . getMachineNode ( <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode6Offset ( SDNode * Op , SDValue N ,


<s> bool isBDAddr32Disp20 ( ) const { return isMemDisp20 ( BDMem


<s> enum attr_i387_cw mode ; if ( CALL_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && ( asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) ) ) return I387_CW_UNINITIALIZED ; if ( recog_memoized ( insn ) < <NUM_LIT> ) return I387_CW_ANY ; mode = get_attr_i387_cw ( insn ) ; switch ( entity ) { case I387_TRUNC : if ( mode == I387_CW_TRUNC ) return


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target (


<s> BuildMI ( MBB , I , DL , SMovB32 , RsrcHi ) . addImm ( MFI -> getGITPtrHigh ( ) ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else { const MCInstrDesc & GetPC64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , GetPC64 , Rsrc01 ) ; } auto GitPtrLo = <STR_LIT> ; if ( ST . hasMergedShaders ( ) ) { switch ( MF . getFunction ( ) . getCallingConv ( ) ) { case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_GS : GitPtrLo = <STR_LIT> ; break ; default : break ; } } MF . getRegInfo ( ) . addLiveIn ( GitPtrLo ) ; MF . front ( ) . addLiveIn ( GitPtrLo ) ; BuildMI ( MBB , I , DL , SMovB32 , RsrcLo ) . addReg ( GitPtrLo ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; PointerType * PtrTy = PointerType :: get ( Type :: getInt64Ty ( MF . getFunction ( ) . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; const MCInstrDesc & LoadDwordX4 = TII -> get ( <STR_LIT> ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , <NUM_LIT> ) ; unsigned Offset = Fn . getCallingConv ( ) == CallingConv :: <ISA_LIT>_CS ? <NUM_LIT> : <NUM_LIT> ; const GCNSubtarget & Subtarget = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned EncodedOffset = <STR_LIT> ( Subtarget , Offset ) ; BuildMI ( MBB , I , DL , LoadDwordX4 , ScratchRsrcReg ) . addReg ( Rsrc01 ) . addImm ( EncodedOffset ) . addImm ( <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) . addMemOperand ( MMO ) ; return ; } if ( ST . isMesaGfxShader ( Fn ) || ( PreloadedPrivateBufferReg == <STR_LIT> ) ) { assert ( ! ST . isAmdHsaOrMesa ( Fn ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; unsigned Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; if ( MFI -> hasImplicitBufferPtr ( ) ) { unsigned Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { const MCInstrDesc & Mov64 = TII ->


<s> unsigned NumOperands = MI . getNumOperands ( ) ; auto GetBlendDomains = [ & ] ( unsigned ImmWidth , bool Is256 ) { uint16_t validDomains = <NUM_LIT> ; if ( MI . getOperand ( NumOperands - <NUM_LIT> ) . isImm ( ) ) { unsigned Imm = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( ! Is256 || Subtarget . hasAVX2 ( ) ) validDomains |= <NUM_LIT> ; } return validDomains ; } ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case


<s> TargetIDSetting getSramEccSetting ( ) const { return SramEccSetting


<s> return ( OpCmode << <NUM_LIT> ) | Val


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } else NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead (


<s> void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ fprintf ( asm_out_file ,

<STR_LIT> , SDATA_SECTION_ASM_OP ) ; \ in_section = in_sdata ; \ } \ }


<s> bool <ISA_LIT>FastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; unsigned i = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { const AttributeSet & Attrs = F -> getAttributes ( ) ; if ( Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: SwiftSelf ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: SwiftError ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: InAlloca ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; if ( ! Subtarget -> hasSIMD128 ( ) && ArgTy ->


<s> return ( __m64 ) __builtin_arm_wsrlw ( ( __v2si


<s> emit_move_insn ( tocompare , gen_int_mode ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> , SImode ) ) ; do_compare_rtx_and_jump ( opcode , tocompare , EQ , <NUM_LIT> , SImode , NULL_RTX , NULL_RTX , no_toc_save_needed ) ; mem = gen_frame_mem ( Pmode , gen_rtx_PLUS ( Pmode , stack_top , GEN_INT ( <NUM_LIT> * GET_MODE_SIZE ( Pmode


<s> break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; default : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; SegmentReg = <STR_LIT> ; break ; } unsigned NumPrefixes = std :: min ( NumBytes - NopSize , <NUM_LIT> ) ; NopSize += NumPrefixes ; for ( unsigned i = <NUM_LIT> ; i != NumPrefixes ; ++ i ) OS . EmitBytes (


<s> else fprintf ( s , <STR_LIT> , <STR_LIT> [ reg_push_size ( regno ) ] , reg_names


<s> if ( MO . isImplicit ( ) ) continue ; MCO = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm ( ) -> getValueAPF ( ) ; MCO = MCOperand :: CreateImm ( * Val . bitcastToAPInt ( ) . getRawData ( ) ) ; break ; } case MachineOperand :: MO_Immediate : MCO = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCO = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCO = GetSymbolRef ( MO , AP . Mang -> getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCO = GetSymbolRef ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO .


<s> getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { if ( MBB . empty ( ) ) return <NUM_LIT> ; unsigned NumRemoved = <NUM_LIT> ; auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I -> getOpcode (


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: mergePredStateIntoSP ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertPt , DebugLoc Loc , unsigned PredStateReg ) { Register TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( PredStateReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT>


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> : <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo ( * this ) , STTI ( & TLInfo )


<s> SDValue <ISA_LIT>TargetLowering :: lowerAtomicFence ( SDValue Op , SelectionDAG & DAG


<s> if ( ! RPhi ) return false ; if ( SelI != RPhi -> getIncomingValueForBlock ( LoopB ) ) return false ; PV . Res = SelI ; if ( CurLoop -> isLoopInvariant ( PV . X ) ) { PV . P = PV . X ; PV . Inv = false ; } else { PV . Inv = true ; if ( PV . X != PV . R ) { Value * Var = nullptr , * Inv = nullptr , * X1 = nullptr , * X2 = nullptr ; if ( ! match ( PV . X , m_Xor ( m_Value ( X1 ) , m_Value ( X2 ) ) ) ) return false ; auto * I1 = dyn_cast < Instruction > ( X1 ) ; auto * I2 = dyn_cast < Instruction > ( X2 ) ; if ( ! I1 || I1 -> getParent ( ) != LoopB ) { Var = X2 ; Inv = X1 ; } else if ( ! I2 || I2 -> getParent ( ) != LoopB ) { Var = X1 ; Inv = X2 ; } else return false ; if ( Var != PV . R ) return false ; PV . M = Inv ; } Value * EntryP = RPhi -> getIncomingValueForBlock ( PrehB ) ; PV . P = EntryP ; } return true ; } if ( matchRightShift ( SelI , PV ) ) { if ( PV . Inv && ! isa < ConstantInt > ( PV . Q ) ) return false ; if ( PreScan ) return true ; return false ; } return


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setHasSpills ( true ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT>


<s> Result = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , Op . getValueType ( ) , Chain , Jump , Cond ) ; return Result


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) { SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( MSB , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , <STR_LIT> , Ops64 ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SDLoc ( N ) , <STR_LIT> , SDValue ( BFM , <NUM_LIT> ) , SubReg ) ; return Node ; } SDValue Ops [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , VT ) , CurDAG -> getTargetConstant (


<s> } if ( TII -> isValidAutoIncImm ( LoadedVT , Val ) ) { SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result ; } else { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD


<s> unsigned oldval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned newval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned scratch = MRI . createVirtualRegister ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; if ( isThumb2 ) { MRI . constrainRegClass ( dest , <STR_LIT> ) ; MRI . constrainRegClass ( oldval , <STR_LIT> ) ; MRI . constrainRegClass ( newval , <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB =


<s> static void nios2_emit_stack_limit_check ( int size ) { rtx sum = NULL_RTX ; if ( GET_CODE ( stack_limit_rtx ) == SYMBOL_REF ) { sum = gen_rtx_REG ( Pmode , TEMP_REG_NUM ) ; emit_move_insn ( sum , plus_constant ( Pmode , stack_limit_rtx , size ) ) ; } else if ( ! REG_P ( stack_limit_rtx ) ) sorry ( <STR_LIT> ) ; else if ( size == <NUM_LIT> ) sum =


<s> FunctionPass * llvm :: create<ISA_LIT>LowerControlFlowPass ( ) { return new <ISA_LIT>LowerControlFlow ( )


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( )


<s> static void mcore_unique_section ( tree decl , int reloc ATTRIBUTE_UNUSED ) { int len ; const char * name ; char * string ; const char * prefix ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = ( * targetm . strip_name_encoding ) ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL


<s> static void encode_pattern ( rtx x ) { patternp =


<s> if ( Acc < <NUM_LIT> ) { unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; int Val = ( TotalSize == <NUM_LIT> ) ? int16_t ( Acc ) : int ( Acc ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR . getSubReg ( ) ) . addImm ( Off ) . addImm ( Val ) ; StI -> addMemOperand ( * MF , NewM ) ; NG . push_back ( StI ) ; } else { const MCInstrDesc & TfrD = TII -> get ( <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TfrD , <NUM_LIT> , TRI , * MF ) ; unsigned VReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * TfrI = BuildMI ( * MF , DL , TfrD , VReg ) . addImm ( int ( Acc ) ) ; NG . push_back ( TfrI ) ; unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > (


<s> MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> )


<s> unsigned int nregs = riscv_hard_regno_nregs ( regno , mode ) ; if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS (

mode ) != MODE_COMPLEX_FLOAT ) return false ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>Target ( )


<s> MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , NeedStub ) :

MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , NeedStub ) ;


<s> <ISA_LIT>ExpandSSR ( ) : MachineFunctionPass (


<s> inline vector signed int vec_msum ( vector signed short a1 , vector

signed short a2 , vector signed int a3 ) {


<s> if ( MI -> mayStore ( ) ) return false ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; if ( ( Domain & <STR_LIT> ) || ( Domain & <STR_LIT> ) ) return MI -> readsRegister ( Reg , TRI ) ; return false


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseMSA128WRegs ( SmallVectorImpl


<s> static bool is_leaf_function ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; if ( fn -> cfg == NULL ) return


<s> if ( Signed ) { Sign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , Sign ) , Sign ) ; std :: tie ( Lo , Hi ) = split64BitValue ( Abs , DAG ) ; } ShAmt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi ) ; } SDValue Norm = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , ShAmt ) ; std :: tie ( Lo , Hi ) = split64BitValue ( Norm , DAG ) ; SDValue Adjust = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Lo ) ; Norm = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , Adjust ) ; unsigned Opc = ( Signed && Subtarget -> isGCN ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FVal = DAG . getNode ( Opc , SL , <STR_LIT> , Norm ) ; ShAmt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , ShAmt ) ; if ( Subtarget -> isGCN ( ) ) return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FVal , ShAmt ) ; SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ShAmt , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue IVal = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FVal ) , Exp ) ; if ( Signed ) { Sign = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Sign ) , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; IVal = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , IVal , Sign ) ; } return DAG . getNode ( <STR_LIT> , SL


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , bool bigEndian ) : <ISA_LIT>DisassemblerBase ( STI ,


<s> if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned StackLoc = VA . getLocMemOffset ( ) + <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordLoadArgsFI ( FI , - StackLoc ) ; <ISA_LIT>FI -> recordLiveIn ( FI ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( ( isVarArg ) && ArgRegEnd ) { if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getRegister ( StackReg , getPointerTy ( ) ) ; TargetRegisterClass * RC = <STR_LIT> ; unsigned Begin = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; unsigned Start = get<ISA_LIT>RegisterNumbering ( ArgRegEnd + <NUM_LIT> ) ; unsigned End = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; unsigned StackLoc = Start - Begin + <NUM_LIT> ; for ( ; Start <= End ; ++ Start , ++ StackLoc ) { unsigned Reg = get<ISA_LIT>RegisterFromNumbering ( Start ) ; unsigned LiveReg = MF . addLiveIn ( Reg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , LiveReg , <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordStoreVarArgsFI ( FI , - ( StackLoc * <NUM_LIT> ) ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; OutChains . push_back ( DAG . getStore ( Chain , dl , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; if ( ! <ISA_LIT>FI -> getVarArgsFrameIndex ( )

) <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ;


<s> const ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsO32 ( ) ) return makeArrayRef (


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg ,


<s> ( void ) CC ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; int Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI


<s> break ; } const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S


<s> SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Load ; if ( VA . getValVT ( ) == <STR_LIT> || VA . getValVT ( ) == <STR_LIT> || VA . getValVT ( ) == <STR_LIT> || VA . getValVT ( ) == <STR_LIT> || VA . getValVT ( ) == <STR_LIT> ) { Load = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , FIPtr , MachinePointerInfo ( ) ) ; } else { <STR_LIT> LoadOp = <STR_LIT> ; unsigned Offset = <NUM_LIT> - std :: max ( <NUM_LIT> , VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ) ; FIPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FIPtr , DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; Load = DAG . getExtLoad ( LoadOp , DL , <STR_LIT> , Chain , FIPtr , MachinePointerInfo ( ) , VA . getValVT ( ) ) ; Load = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Load ) ; } InVals . push_back ( Load ) ; } <ISA_LIT>MachineFunctionInfo * VFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( isVarArg ) { int FirstVarArg = MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> , ParamEndOffset , false ) ; VFI -> setVarArgsFrameIndex ( FirstVarArg ) ; } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { unsigned Reg = VFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; VFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; } return


<s> MIB = BuildMI ( MBB , llvm :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT>


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveAMDHSAKernel ( ) ; if ( IDVal == <STR_LIT> :: V3 :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ; } else { if ( IDVal == <STR_LIT> ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveAMDKernelCodeT


<s> int m16_nuimm8_1 ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return m16_check_op ( op , -


<s> return FuncInfo -> hasSpilledSGPRs ( ) && ( ! FuncInfo -> hasSpilledVGPRs (

) && ! FuncInfo -> hasNonSpillStackObjects ( ) ) ;


<s> dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n' << <STR_LIT> ; if ( ES ) dbgs ( ) << ES ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( MCSym ) dbgs ( ) << MCSym ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << JT << <STR_LIT> <<


<s> const MCExpr * SizeExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( SymEnd , OutContext ) , MCSymbolRefExpr :: Create ( SymStart , OutContext ) , OutContext ) ; OutStreamer . EmitELFSize ( SymStart ,


<s> MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI )


<s> if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags =


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT>


<s> bool getMergeForward ( ) const { return MergeForward


<s> Register DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . hasOneUse ( DefReg ) || MI . getParent ( ) -> getParent ( ) -> getFunction ( ) . hasMinSize ( ) ) return true ; if ( ! STI . hasLSLFast ( ) ) return


<s> static bool isCSRestore ( MachineInstr & MI , const MCPhysReg * CSRegs ) { if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) return true ; else if ( MI . getOpcode ( ) ==


<s> assert ( Index < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 <


<s> static MCSymbol * getPICLabel ( StringRef Prefix , unsigned FunctionNumber ,


<s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( <STR_LIT> ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( <STR_LIT> ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; bool Unsigned = false ; if ( ShiftAmount > <NUM_LIT> && ! isInt < <NUM_LIT> > (


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) / <NUM_LIT>


<s> DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; if ( i != elem ) copy -> addOperand ( MachineOperand :: CreateReg ( src [ i ] , false ) ) ; else copy -> addOperand ( Instr -> getOperand


<s> bool getMaxNReg ( const Function & F , unsigned & x ) { return findOneNVVMAnnotation ( & F , <STR_LIT>


<s> CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return


<s> MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering . getPointerTy ( ) == <STR_LIT> ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ,


<s> addr = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == ZERO_EXTRACT ) addr = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; return gen_rtx_MEM ( HImode


<s> bool ProtectJTSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! Func . protectJT ( ) ) return false ; bool modified = false ; for ( MachineFunction :: iterator MBB = Func . begin ( ) ; MBB != Func . end ( ) ; MBB ++ ) { MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; while ( MI != MBB -> end ( ) ) { MachineBasicBlock :: iterator NMI = std :: next ( MI ) ; modified |= handleInst ( * MBB , MI ) ; MI = NMI ; } } return


<s> { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ; return makeArrayRef ( TargetFlags


<s> const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; AddressRegs Regs = getRegs ( Opcode , * TII ) ; if ( Regs . VAddr ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired .


<s> } if ( NewOpc ) { unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( Br . MI , DestBB , MaxOffs ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * Br . MI ) ; Br . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; if ( ! Br . MI -> killsRegister ( <STR_LIT> ) ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOffset = getOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( )


<s> return ( __m128i ) __builtin_ia32_pabsw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> targetm . file_start_file_directive = TARGET_ELF ; default_file_start (


<s> int ci_opr1 = ( int ) CINT -> getSExtValue ( ) ; if ( ci_opr1 == <NUM_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; replaceCall ( opr0 ) ; return true ; } if ( ci_opr1 == <NUM_LIT> ) { std :: vector < const Type * > ParamsTys ; ParamsTys . push_back ( opr0 -> getType ( ) ) ; Module * M = CI -> getModule ( ) ; if ( Constant * FPExpr = getFunction ( M , <ISA_LIT>LibFunc ( <ISA_LIT>LibFunc :: EI_SQRT , FInfo ) ) ) { DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; Value * nval = CreateCallEx ( B , FPExpr , opr0 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; } } else if ( ci_opr1 == <NUM_LIT> ) { Module * M = CI -> getModule ( ) ; if ( Constant * FPExpr = getFunction ( M , <ISA_LIT>LibFunc ( <ISA_LIT>LibFunc :: EI_CBRT , FInfo ) ) ) { DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * opr0 << <STR_LIT> ) ; Value * nval = CreateCallEx ( B , FPExpr ,


<s> if ( VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( Constraint == <STR_LIT> ) { if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , &


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseCoprocNumOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) . lower ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! isValidCoprocessorNumber ( Num , getSTI ( ) . getFeatureBits ( ) ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( CallType , dl , NodeTys ,


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; Register CFMask = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Def = MRI . getUniqueVRegDef ( CFMask ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator InsPt = Def && Def -> getParent ( ) == & MBB ? std :: next ( MachineBasicBlock :: iterator ( Def ) ) : MBB . begin ( ) ; MachineInstr * NewMI = BuildMI ( MBB , InsPt , DL , TII -> get ( OrOpc ) , Exec ) . addReg ( Exec ) . add ( MI . getOperand


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned FrameReg


<s> unsigned getWavefrontSizeLog2 ( ) const { return Log2_32 ( WavefrontSize


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup


<s> if ( isa < StructType > ( Ty ) ) return <STR_LIT> ; else if ( isa < ArrayType > ( Ty ) ) { Type * ElmTy = cast < ArrayType > ( Ty ) -> getElementType ( ) ; if ( isa < CompositeType > ( ElmTy ) ) return <STR_LIT> ; return GetLoadString ( ElmTy ) ; } else { const DataLayout & DL = MF -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * MF -> getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( MF -> getFunction ( ) ) . getTargetLowering ( ) ; EVT VT = TLI . getValueType (


<s> return __builtin_mve_vbicq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a , __b ,


<s> return ( int8x8x2_t ) { vtrn1_s8 ( a , b ) , vtrn2_s8 ( a , b


<s> MCOperand <ISA_LIT>Disassembler :: decodeSDWA9Src16 ( unsigned


<s> __rv . __o = __builtin_neon_vld3_dupv8qi ( ( const __builtin_neon_qi * ) __a ) ; return __rv .


<s> return ( __m128h ) __builtin_ia32_vfcmulcsh_round ( ( __v8hf )


<s> switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MCStreamer * S = createMachOStreamer ( Ctx , MAB , OS , Emitter , false ) ; new <ISA_LIT>TargetStreamer ( * S ) ; return S ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return create<ISA_LIT>WinCOFFStreamer ( Ctx , MAB , * Emitter , OS ) ; case Triple :: ELF : return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , false , TheTriple . getArch ( ) == Triple ::


<s> __v16qu a , b ; __v16qu vmin , vmax , vabsdiff ; __v4si vsum ; const __v4su zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4si result ; a = ( __v16qu ) __A ; b = ( __v16qu ) __B ; vmin = vec_min ( a , b ) ; vmax = vec_max ( a , b ) ; vabsdiff = vec_sub ( vmax , vmin ) ; vsum = ( __vector signed int ) vec_sum4s ( vabsdiff , zero ) ; result = vec_sum2s ( vsum , ( __vector signed int ) zero ) ; result = vec_sld ( result ,


<s> any_addr_mask = <NUM_LIT> ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = <NUM_LIT> ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= <NUM_LIT> && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > <NUM_LIT> || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= <NUM_LIT> && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == <NUM_LIT> ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DFmode : case E_DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize <= <NUM_LIT> && ( rc == RELOAD_REG_GPR || ( ( msize == <NUM_LIT> || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize == <NUM_LIT> && TARGET_P9_DFORM_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX_TIMODE ) ) ) { addr_mask |=


<s> DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; DReg = getCorrespondingDRegAndLane ( TRI , SrcReg , Lane ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB . addReg ( DstReg , RegState :: Define ) . addReg ( DReg , RegState :: Undef ) . addImm ( Lane ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; break ; case <STR_LIT> : { if ( Domain != ExeNEON ) break ; assert ( ! isPredicated ( MI ) && <STR_LIT> ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DReg = getCorrespondingDRegAndLane ( TRI , DstReg , Lane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DReg , Lane , ImplicitSReg ) ) break ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DReg , RegState :: Define ) . addReg ( DReg , getUndefRegState ( ! MI -> readsRegister ( DReg , TRI ) ) ) . addReg ( SrcReg ) . addImm ( Lane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg )


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_NOBITS , MCSectionELF ::

SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> unsigned Value = CE -> getValue ( ) ; Value = <STR_LIT> ( Value ) ; Inst . addOperand ( MCOperand ::


<s> return ( ( qword ) ( vec_cmpgt ( vec_andc ( ( vec_float4 ) ( a ) , msb ) , vec_andc (


<s> return ( vector unsigned short ) __builtin_altivec_vadduhm ( ( vector signed short


<s> bool <ISA_LIT>InstrInfo :: isLiteralConstant ( const


<s> clearProcResCounters ( ) ; GrpCount = <NUM_LIT> ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ; LLVM_DEBUG ( CurGroupDbg =


<s> static tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) { return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ; return NULL_TREE


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegPair ( unsigned RegNo , SMLoc S

, SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> static bool nvptx_return_in_memory ( const_tree type , const_tree ) { machine_mode mode = TYPE_MODE ( type ) ; if ( ! RETURN_IN_REG_P ( mode ) ) return true ; return


<s> return ( __m128i ) __builtin_ia32_pandn128 ( ( __v2di )


<s> return ( __m256i ) __builtin_ia32_psllqi256_mask ( ( __v4di ) __A , __B , (


<s> return ! ST -> isTargetDarwin ( ) && !


<s> return SelectAddrModeRO ( N , <NUM_LIT> , Base