<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Res = ExpandBIT_CONVERT ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerShift ( N , DAG , Subtarget ) ; break ; } if ( Res . getNode ( ) ) Results . push_back


<s> if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT>


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue IID = N -> getOperand ( <NUM_LIT> ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; SDValue Vec = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Lane = Op1 . getOperand ( <NUM_LIT> ) ; EVT ResTy = N -> getValueType ( <NUM_LIT> ) ; EVT VecResTy


<s> SDValue C = N -> getOperand ( <NUM_LIT> ) ; auto invertIfNegative = [ & DAG ] ( SDValue & V ) { if ( SDValue NegVal = isFNEG ( DAG , V . getNode ( ) ) ) { V = DAG . getBitcast ( V . getValueType ( ) , NegVal ) ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { if ( SDValue NegVal = isFNEG ( DAG , V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { NegVal = DAG . getBitcast ( V . getOperand ( <NUM_LIT> ) . getValueType (


<s> int UnscaledStOffset = TII -> isUnscaledLdSt ( StoreInst ) ? getLdStOffsetOp ( StoreInst ) . getImm ( ) : getLdStOffsetOp ( StoreInst ) . getImm ( ) * StoreSize ; int UnscaledLdOffset = TII -> isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp


<s> if ( cfun -> machine -> funtype && ( TREE_CODE ( cfun -> machine -> funtype ) == FUNCTION_TYPE || TREE_CODE ( cfun -> machine -> funtype ) == METHOD_TYPE ) && stdarg_p ( cfun -> machine -> funtype ) ) { has_varargs = true ; cfun -> machine -> has_call_with_varargs = true ; } vec = rtvec_alloc ( nargs + <NUM_LIT> + ( has_varargs ? <NUM_LIT> : <NUM_LIT> ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( has_varargs ) { rtx this_arg = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_move_insn ( this_arg , stack_pointer_rtx ) ; else emit_move_insn ( this_arg , stack_pointer_rtx ) ; XVECEXP ( pat , <NUM_LIT> , nargs + <NUM_LIT> ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } int i ; rtx arg ; for ( i = <NUM_LIT> , arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , <NUM_LIT> ) , i ++ ) { rtx this_arg = XEXP ( arg , <NUM_LIT> ) ; XVECEXP ( pat , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } rtx tmp_retval = retval ; t = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; if ( retval != NULL_RTX ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; t = gen_rtx_SET ( VOIDmode , tmp_retval , t ) ; } XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) = t ; if ( ! REG_P ( callee ) && ( decl_type == NULL_TREE || ( external_decl && TYPE_ARG_TYPES ( decl_type ) == NULL_TREE ) ) ) { rtx * slot = declared_libfuncs_htab -> find_slot ( callee , INSERT ) ; if ( * slot == NULL ) { * slot = callee ; write_func_decl_from_insn ( func_decls , retval , pat ,


<s> bool <ISA_LIT>Operand :: isSMRDOffset8 ( )


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII


<s> if ( OpClassID != - <NUM_LIT> ) { return TRI . getRegClass ( OpClassID ) ; } switch ( Op . getMachineOpcode ( ) ) { case AMDGPU :: COPY_TO_REGCLASS : OpClassID = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( OpClassID == AMDGPU :: VSrc_32RegClassID || OpClassID == AMDGPU :: VSrc_64RegClassID ) { return getRegClassForNode ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; } return TRI . getRegClass ( OpClassID ) ; case AMDGPU :: EXTRACT_SUBREG : { int SubIdx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const TargetRegisterClass * SuperClass = getRegClassForNode ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; return TRI . getSubClassWithSubReg ( SuperClass , SubIdx ) ; } case AMDGPU ::


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > (


<s> case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( )


<s> unsigned getWavesPerWorkGroup ( unsigned FlatWorkGroupSize ) const { return alignTo ( FlatWorkGroupSize , getWavefrontSize (


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == <STR_LIT> ) return <NUM_LIT> ; return <ISA_LIT>TargetLowering :: getNumRegisters ( Context


<s> frv_stack_t * info = frv_stack_info ( ) ; rtx fp = frame_pointer_rtx ; rtx sp = stack_pointer_rtx ; rtx return_addr ; int fp_offset ; fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; if ( ! crtl -> sp_is_unchanging ) emit_insn ( gen_addsi3 ( sp , fp , frv_frame_offset_rtx ( - fp_offset ) ) ) ; frv_frame_access_standard_regs ( FRV_LOAD , info ) ; if ( info -> save_p [ LR_REGNO ] ) { int lr_offset ; rtx mem ; lr_offset = info -> reg_offset [ LR_REGNO ] ; if ( frame_pointer_needed ) mem = frv_frame_mem ( Pmode , fp , lr_offset - fp_offset ) ; else mem = frv_frame_mem ( Pmode , sp , lr_offset ) ; return_addr = gen_rtx_REG ( Pmode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , return_addr , mem ) ) ; } else return_addr = gen_rtx_REG ( Pmode , LR_REGNO ) ; if ( frame_pointer_needed ) { emit_insn ( gen_rtx_SET ( VOIDmode , fp , gen_rtx_MEM ( Pmode , fp ) ) ) ; emit_use ( fp ) ; } if ( info -> total_size != <NUM_LIT> ) { rtx offset = frv_frame_offset_rtx ( info -> total_size ) ; emit_insn ( gen_stack_adjust ( sp , sp ,


<s> } else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; else emitFPU ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) : ( STI . hasFeature ( <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitFPU ( <STR_LIT> ) ; } if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && isV8M ( STI ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFeature ( <STR_LIT> ) && STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> ) ) emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( STI . hasFeature ( <STR_LIT> )


<s> return SamplerFilterMode :: Linear ; } else if ( bitmask & CLK_FILTER_NEAREST ) { return SamplerFilterMode :: Nearest ; }


<s> APInt DemandedElts = APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ; if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , KnownUndef , KnownZero , DCI ) ) return SDValue ( N


<s> Record . push_back ( VE . getMetadataOrNullID ( N -> getRetainedTypes ( ) . get ( ) ) ) ; Record . push_back ( <NUM_LIT> ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getGlobalVariables ( ) . get ( ) ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getImportedEntities ( ) . get ( ) ) ) ; Record . push_back ( N


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> MachineFunction * MF = MBB -> getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned IndexOperand = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool WaveRelease = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; bool WaveDone = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; if ( WaveDone && ! WaveRelease ) report_fatal_error ( <STR_LIT> ) ; unsigned OrderedCountIndex = IndexOperand & <NUM_LIT> ; IndexOperand &= ~ <NUM_LIT> ; unsigned CountDw = <NUM_LIT> ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { CountDw = ( IndexOperand >> <NUM_LIT> ) & <NUM_LIT> ; IndexOperand &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; if ( CountDw < <NUM_LIT> || CountDw > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } } if ( IndexOperand ) report_fatal_error ( <STR_LIT> ) ; unsigned Instruction = IntrID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned ShaderType = getDSShaderTypeValue ( * MF ) ; unsigned Offset0 = OrderedCountIndex << <NUM_LIT> ; unsigned Offset1 = WaveRelease | ( WaveDone << <NUM_LIT> ) | ( ShaderType << <NUM_LIT> ) | ( Instruction << <NUM_LIT> ) ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) Offset1 |= ( CountDw - <NUM_LIT> ) << <NUM_LIT> ; unsigned Offset = Offset0 | ( Offset1 << <NUM_LIT> ) ; Register M0Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Val ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder DS = BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( ValReg ) . addImm ( Offset ) . cloneMemRefs ( MI ) ; if ( ! RBI . constrainGenericRegister ( M0Val , <STR_LIT> , * MRI ) ) return false ; bool Ret = constrainSelectedInstRegOperands ( * DS , TII


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART (


<s> case <STR_LIT> : case <STR_LIT> : { MemSDNode * M = cast < MemSDNode > ( Op ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } default : return SDValue ( )


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S2 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectThumbAddrModeImm5S ( N , <NUM_LIT> ,


<s> unsigned getParamByOffset ( int64_t & Offset ) const { if ( Offset >= UINT_MAX || Offset < <NUM_LIT> ) return UINT_MAX ; unsigned o = ( unsigned ) Offset ; unsigned r = getParamByOffset ( o ) ; Offset = o ; return


<s> unsigned <ISA_LIT>AsmParser :: matchRegisterNameAlias ( StringRef Name , RegKind Kind ) { unsigned RegNum = <NUM_LIT> ; if ( ( RegNum = matchSVEDataVectorRegName ( Name ) ) ) return Kind == RegKind :: SVEDataVector ? RegNum : <NUM_LIT> ; if ( ( RegNum = matchSVEPredicateVectorRegName ( Name ) ) ) return Kind == RegKind :: SVEPredicateVector ? RegNum : <NUM_LIT> ; if ( ( RegNum = MatchNeonVectorRegName ( Name ) ) ) return Kind == RegKind :: NeonVector ? RegNum : <NUM_LIT> ; if ( ( RegNum = matchMatrixRegName ( Name ) ) ) return Kind ==

RegKind :: Matrix ? RegNum : <NUM_LIT> ;


<s> static scalar_int_mode cr16_unwind_word_mode ( void ) { return SImode


<s> void <ISA_LIT>AsmPrinter :: printMemBOption ( const MachineInstr * MI , int


<s> } } if ( NeedsRotate ) Res = SelectRotMask64 ( VRI . V , dl , VRI . RLAmt , VRI . Repl32 , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , InstCnt ) ; else Res = VRI . V ; if ( Res ) eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt && BG . Repl32 == VRI . Repl32 ; } ) ; } if ( ! Res ) for ( auto I = BitGroups . begin ( ) , IE = BitGroups . end ( ) ; I != IE ; ++ I ) { if ( SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , false ) < SelectRotMask64Count ( I -> RLAmt , I -> Repl32 , I -> StartIdx , I -> EndIdx , true ) ) { if ( I != BitGroups . begin ( ) ) { BitGroup BG = * I ; BitGroups . erase ( I ) ; BitGroups . insert ( BitGroups . begin ( ) , BG ) ; } break ; } } for ( auto & BG : BitGroups ) { if ( ! Res ) Res = SelectRotMask64 ( BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; else Res = SelectRotMaskIns64 ( Res , BG . V , dl , BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , InstCnt ) ; } if ( LateMask ) { uint64_t Mask = getZerosMask ( ) ; bool Use32BitInsts = isUInt < <NUM_LIT>


<s> unsigned getHWRegIndex ( unsigned Reg ) const { return getEncodingValue ( Reg


<s> SDValue <ISA_LIT>TargetLowering :: LowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FINode -> getIndex (


<s> if ( df_regs_ever_live_p ( i ) || call_p ) { size += <NUM_LIT> ; reg_saved |= <NUM_LIT> << i ; } break ; case <NUM_LIT> : case STACK_POINTER_REGNUM : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case EP_REGNUM : size += <NUM_LIT> ; break ; } } else { for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( df_regs_ever_live_p ( i ) && ( ( ! call_used_regs [ i ] ) || i == LINK_POINTER_REGNUM ) ) break ; if ( TARGET_PROLOG_FUNCTION && ( i == <NUM_LIT> || ( ( i >= <NUM_LIT> ) && ( i < <NUM_LIT> ) ) ) ) { if ( i == <NUM_LIT> ) { size += <NUM_LIT> ; reg_saved |= <NUM_LIT> << i ; i =


<s> void <ISA_LIT>InstPrinter :: printV3F32 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << '(' ; printF32 ( MI , OpNo + <NUM_LIT> , O ) ; O << <STR_LIT> ; printF32 ( MI , OpNo + <NUM_LIT> ,


<s> bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed


<s> const <ISA_LIT>InstrInfo * TII = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * TrueBB = nullptr , * FalseBB = nullptr ; SmallVector < MachineInstr * , <NUM_LIT> > BranchInstrs ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; <ISA_LIT>InstrInfo :: BranchType R = TII -> analyzeBranch ( MBB , TrueBB , FalseBB , Cond , false , BranchInstrs ) ; if ( ( R == <ISA_LIT>InstrInfo :: BT_None ) || ( R == <ISA_LIT>InstrInfo :: BT_NoBranch ) ) return std :: make_pair ( R , nullptr ) ; if ( R != <ISA_LIT>InstrInfo :: BT_CondUncond ) { if ( ! hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , nullptr ) ; assert ( ( ( R != <ISA_LIT>InstrInfo :: BT_Uncond ) || ( TrueBB == & Dst ) ) ) ; return std :: make_pair ( R , BranchInstrs [ <NUM_LIT> ] ) ; } assert ( ( TrueBB == & Dst ) || ( FalseBB == & Dst ) ) ; if ( hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_Cond , BranchInstrs [


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return <NUM_LIT> ; return MRI -> getUniqueVRegDef (


<s> MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; MIB . addUse ( PhysReg ,


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SPESpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else


<s> StringRef getPassName ( ) const override { return


<s> static bool avr_scalar_mode_supported_p ( machine_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> )

, InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) {


<s> return __builtin_mve_vmulq_n_uv4si ( __a ,


<s> return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseArithmeticLogic ( ) || hasFuseCCSelect ( ) ||

hasFuseAdrpAdd ( ) || hasFuseLiterals ( ) ;


<s> if ( Subtarget . hasZeroCycleZeroingGP ( ) ) { if ( Opcode == TargetOpcode :: COPY && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return true ; } if ( Subtarget . hasExynosCheapAsMoveHandling ( ) ) { if ( isExynosResetFast ( MI ) || isExynosShiftExtFast ( MI ) ) return true ; else return MI . isAsCheapAsAMove ( ) ; } switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT>


<s> static void frv_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == <NUM_LIT> ) ; fputs ( <STR_LIT> , file


<s> bool Valid ; StringRef Name ; if ( Opcode == <STR_LIT> ) Name = <STR_LIT> ( ) . toString ( Val , Valid ) ; else Name = <STR_LIT> ( ) . toString ( Val


<s> while ( true ) { if ( HasCutoff && ( ExtractCount >= Cutoff ) ) return Changed ; bool Last = ( I == Begin ) ; if ( ! Last ) NextI = std :: prev ( I ) ; Instruction * In = & * I ; bool Done = convert ( In ) ; if ( HasCutoff && Done ) ExtractCount ++ ; Changed |=


<s> if ( mode == V2DFmode ) return zero_constant ( op , mode ) ? <NUM_LIT> : <NUM_LIT> ; else if ( mode == V2DImode ) { if ( ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) || ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( zero_constant ( op , mode ) ) return <NUM_LIT> ; if ( INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; } else if ( mode == V1TImode ) return <NUM_LIT> ; step = GET_MODE_NUNITS ( mode ) / <NUM_LIT> ; copies = <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return <NUM_LIT> ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return <NUM_LIT> ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return <NUM_LIT> ; if ( vspltis_shifted ( op ) != <NUM_LIT> ) return GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; return <NUM_LIT>


<s> case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( HasSPE ) { switch ( Pred ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; } } else CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg1 = ExtReg ; if ( ! UseImm ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg2 = ExtReg ; } } if ( ! UseImm ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) , DestReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc )

, DestReg ) . addReg ( SrcReg1 ) . addImm ( Imm ) ;


<s> MIB . addReg ( AddrIn ) . addImm ( StSize ) ; AddDefaultPred ( MIB ) ; } else if ( IsThumb2 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( StSize ) ) ; } else { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) .

addReg ( <NUM_LIT> ) . addImm ( StSize ) ) ;


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; if ( ! TLI . hasStandaloneRem ( VT ) ) { return false ; } RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 : RTLIB :: UREM_I16 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I32 : RTLIB :: UREM_I32 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I64 : RTLIB :: UREM_I64 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB


<s> if ( ! REG_P ( sel ) ) sel = force_reg ( V16QImode , sel ) ; if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op0 , op1 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ; unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op0 , norreg ) , UNSPEC_VPERM ) ; } if ( ! REG_P ( target )


<s> switch ( I . getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT )


<s> ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; if ( const char * bzeroEntry = V && V -> isNullValue ( ) ? Subtarget . getBZeroEntry ( ) : nullptr ) { EVT IntPtr = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = DAG . getTargetLoweringInfo ( ) . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT>


<s> rs6000_gen_section_name ( & xcoff_tbss_section_name , main_input_filename , <STR_LIT> ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_quoted_string ( asm_out_file , main_input_filename ) ; fputc ( '\n' , asm_out_file ) ; if ( write_symbols != NO_DEBUG ) switch_to_section ( private_data_section ) ; switch_to_section ( toc_section ) ; switch_to_section ( text_section ) ; if ( profile_flag ) fprintf (


<s> static inline bool mode_supports_vsx_dform_quad ( machine_mode mode


<s> rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = reg3 ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops )


<s> for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ; if ( FFI -> getMaxAlignment ( ) == MaxAlign ) return false ; FFI -> setMaxAlignment ( MaxAlign ) ; return


<s> switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm


<s> if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; if ( cast < BinaryOperator > ( I ) -> isExact ( ) ) { unsigned ResultReg = emitASR_ri ( VT , VT , Src0Reg , Src0IsKill , Lg2 ) ; if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ; return true ; } unsigned Pow2MinusOne = ( <NUM_LIT> << Lg2 ) - <NUM_LIT> ; unsigned AddReg = emitAddSub_ri ( true , VT , Src0Reg , false , Pow2MinusOne ) ; if ( ! AddReg ) return false ; if ( ! emitICmp_ri ( VT , Src0Reg , false , <NUM_LIT> ) ) return false ; unsigned SelectOpc ; const TargetRegisterClass * RC ; if ( VT == <STR_LIT> ) { SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else { SelectOpc = <STR_LIT> ; RC = & <STR_LIT> ; } unsigned SelectReg = fastEmitInst_rri ( SelectOpc , RC , AddReg , true , Src0Reg , Src0IsKill , <STR_LIT> ) ; if ( ! SelectReg ) return false ; unsigned ZeroReg = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg


<s> rtx set = single_set ( insn ) ; rtx src = SET_SRC ( set ) ; rtx dest = SET_DEST ( set ) ; if ( MEM_P ( dest ) && ( REG_P ( src ) || src == CONST0_RTX ( GET_MODE ( dest ) ) ) ) { return CONSTANT_ADDRESS_P ( XEXP ( dest , <NUM_LIT> ) ) ; } else if ( REG_P ( dest ) && MEM_P ( src ) ) { return CONSTANT_ADDRESS_P ( XEXP ( src , <NUM_LIT> ) ) ; } return false ; } case CODE_FOR_call_insn


<s> unsigned Tmp = std :: min ( Tmp0 , Tmp1 ) ; if ( Tmp > ( SrcBits - VTBits ) ) return Tmp - ( SrcBits - VTBits ) ; return <NUM_LIT> ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; const APInt & ShiftVal = Op . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ShiftVal . uge ( VTBits ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; if ( ShiftVal . uge ( Tmp ) ) return <NUM_LIT> ; return Tmp - ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; APInt ShiftVal = Op . getConstantOperandAPInt ( <NUM_LIT> ) ; if ( ShiftVal . uge ( VTBits - <NUM_LIT> ) ) return VTBits ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , DemandedElts , Depth + <NUM_LIT> ) ; ShiftVal += Tmp ; return ShiftVal . uge ( VTBits ) ? VTBits : ShiftVal . getZExtValue ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> SDValue SignBit64 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Zero , SignBit ) ; SignBit64 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , SignBit64 ) ; SDValue BcInt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue FractMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> , <STR_LIT> ) ; SDValue Shr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FractMask , Exp ) ; SDValue Not = DAG . getNOT ( SL , Shr , <STR_LIT> ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BcInt , Not ) ; EVT SetCCVT = getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) ; const SDValue FiftyOne = DAG . getConstant ( FractBits - <NUM_LIT> , <STR_LIT> ) ; SDValue ExpLt0 = DAG . getSetCC ( SL , SetCCVT , Exp , Zero , <STR_LIT> ) ; SDValue ExpGt51 = DAG . getSetCC ( SL , SetCCVT , Exp , FiftyOne , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpLt0 , SignBit64 , Tmp0 ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpGt51 , BcInt


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo (


<s> if ( total_size > <NUM_LIT> ) { emit_move_insn ( scratch , GEN_INT ( total_size - UNITS_PER_WORD ) ) ; emit_insn ( gen_addsi3 ( scratch , frame , scratch ) ) ; a0_addr = scratch ; } insn = emit_move_insn ( gen_frame_mem ( SImode , a0_addr )


<s> Store . second -> eraseFromParent ( ) ; } if ( ThisReplaceable ) { ReturnTypes . push_back ( ArgTy ) ; OutArgIndexes . insert ( { OutArg -> getArgNo ( ) , ArgTy } ) ; ++ NumOutArgumentsReplaced ; Changing = true ; } } } while ( Changing ) ; if ( Replacements . empty ( ) ) return false ; LLVMContext & Ctx = F . getParent ( ) -> getContext ( ) ; StructType * NewRetTy = StructType :: create ( Ctx , ReturnTypes , F . getName ( ) ) ; FunctionType * NewFuncTy = FunctionType :: get ( NewRetTy , F . getFunctionType ( ) -> params ( ) , F . isVarArg ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewRetTy << '\n' ) ; Function * NewFunc = Function :: Create ( NewFuncTy , Function :: PrivateLinkage , F . getName ( ) + <STR_LIT> ) ; F . getParent ( ) -> getFunctionList ( ) . insert ( F . getIterator ( ) , NewFunc ) ; NewFunc -> copyAttributesFrom ( & F ) ; NewFunc -> setComdat ( F . getComdat ( ) ) ; NewFunc -> stealArgumentListFrom ( F ) ; AttributeMask RetAttrs ; RetAttrs . addAttribute ( Attribute :: SExt ) ; RetAttrs . addAttribute ( Attribute :: ZExt ) ; RetAttrs . addAttribute ( Attribute :: NoAlias ) ; NewFunc -> removeRetAttrs ( RetAttrs ) ; NewFunc -> getBasicBlockList ( ) . splice ( NewFunc -> begin ( ) , F . getBasicBlockList ( ) ) ; for ( std :: pair < ReturnInst * , ReplacementVec > & Replacement : Replacements ) { ReturnInst * RI = Replacement . first ; IRBuilder < > B ( RI ) ; B . SetCurrentDebugLocation ( RI -> getDebugLoc ( ) ) ; int RetIdx = <NUM_LIT> ; Value * NewRetVal = UndefValue :: get ( NewRetTy ) ; Value * RetVal = RI -> getReturnValue ( ) ; if ( RetVal ) NewRetVal = B . CreateInsertValue ( NewRetVal , RetVal , RetIdx ++ ) ; for ( std :: pair < Argument * , Value * > ReturnPoint : Replacement . second ) NewRetVal = B . CreateInsertValue ( NewRetVal , ReturnPoint . second , RetIdx ++ ) ; if ( RetVal ) RI -> setOperand ( <NUM_LIT> , NewRetVal ) ; else { B . CreateRet (


<s> unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ; MIB . add ( MI . getOperand ( OpIdx


<s> NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , false , false , true ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addReg ( LdReg , false , false , true ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , LdReg , NumBytes , <STR_LIT> , <NUM_LIT> , & TII , true , dl ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , false , false , true ) ; else MIB . addReg ( LdReg ) . addReg


<s> AddendH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Other , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; APInt HighMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; unsigned LHSSB = DAG . ComputeNumSignBits ( Mul . getOperand ( <NUM_LIT> ) ) ; unsigned RHSSB = DAG . ComputeNumSignBits ( Mul . getOperand ( <NUM_LIT> ) ) ; if ( DAG . MaskedValueIsZero ( Mul . getOperand ( <NUM_LIT> ) , HighMask ) && DAG . MaskedValueIsZero ( Mul . getOperand ( <NUM_LIT> ) , HighMask ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddendH , AddendL , LL , RL ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( LHSSB > <NUM_LIT> && RHSSB > <NUM_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddendH , AddendL , LL , RL ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } SDValue LH , RH ; LH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; RH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddendH , AddendL , LL , RL ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; RH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LL ,


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNo , raw_ostream & O , const char * Modifier ) { llvm_unreachable ( <STR_LIT> )


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM ) ; return


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; int Idx = CostTableLookup ( NEONAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx == - <NUM_LIT> ) return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; return LT . first * NEONAltShuffleTbl [ Idx


<s> <ISA_LIT>Gfx90ACacheControl ( const GCNSubtarget & ST ) : <ISA_LIT>Gfx7CacheControl ( ST


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo


<s> unsigned getMinimumNopSize ( ) const override { return <NUM_LIT>


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> if ( ! RM . hasValue ( ) ) return TT . isOSBinFormatMachO ( ) ? Reloc :: PIC_ : Reloc :: Static ; if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) )


<s> uint32_t Value = Writer -> getSymbolAddress ( * A , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target32 (


<s> static DecodeStatus DecodeGPRnopcRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t


<s> break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitAtomicCmpSwap ( MachineInstr & MI , MachineBasicBlock * BB ) const { MachineFunction * MF = BB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB


<s> bool <ISA_LIT>DAGToDAGISel :: tryIndexedLoad ( SDNode *


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 ,


<s> const MCExpr * getImm ( ) const { assert ( Kind == Immediate && <STR_LIT> ) ; return Imm . Val


<s> return std :: make_pair ( ExtLo . getReg ( <NUM_LIT> ) , ShiftHi . getReg ( <NUM_LIT> ) ) ; } auto ShiftHi = B . buildLShr ( S32 , Bitcast , B . buildConstant ( S32 , <NUM_LIT> ) ) ; if ( ExtOpcode == TargetOpcode :: G_ZEXT ) { auto ExtLo = B . buildAnd ( S32 , Bitcast , B . buildConstant ( S32 , <NUM_LIT> ) ) ; return std :: make_pair ( ExtLo . getReg ( <NUM_LIT> ) , ShiftHi . getReg ( <NUM_LIT> ) ) ; } assert ( ExtOpcode == TargetOpcode :: G_ANYEXT


<s> if ( InstrType == <STR_LIT> ) return ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) HasCTRSet = true ; if ( isStore && NumStores < <NUM_LIT> && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO -> getSize ( ) ; StoreOffset [ NumStores ] = MO -> getOffset ( ) ; StoreValue [ NumStores ] = MO -> getValue ( ) ; ++ NumStores ; } if ( InstrType == <STR_LIT> || isSingle ) NumIssued = <NUM_LIT> ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == <NUM_LIT>


<s> const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent (


<s> auto One = B . buildConstant ( S32 , <NUM_LIT> ) ; auto Cond = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , R , Y ) ; if ( IsDiv ) Q = B . buildSelect ( S32 , Cond , B . buildAdd ( S32 , Q , One ) , Q ) ; R = B . buildSelect ( S32 , Cond , B . buildSub ( S32 , R , Y ) , R ) ; Cond = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , R , Y ) ; if ( IsDiv ) B . buildSelect ( DstReg , Cond , B . buildAdd


<s> bool Changed = false ; MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next ( I )


<s> fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else if ( flag_pic == <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else fprintf ( file ,


<s> if ( ! NoImplicitFloat && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE2 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return


<s> SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ; return SDValue


<s> bool hasSSEUnalignedMem ( ) const { return


<s> MachineBasicBlock :: iterator J = I ; if ( ! MBDisableDelaySlotFiller ) D = findDelayInstr ( MBB , I ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , ++ J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( ++ J , & MBB , D ) ; } return


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG


<s> static SDValue skipExtensionForVectorMULL ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) return addRequiredExtensionForVectorMULL ( N -> getOperand ( <NUM_LIT> ) , DAG , N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , N -> getOpcode ( ) ) ; assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements (


<s> return Builder . CreatePointerCast ( Tmp0 , ValTy -> getPointerTo ( ) ) ; } PointerType * CharPtrTy = Type :: getInt8PtrTy ( HVC . F . getContext ( ) ) ; Value * Tmp0 = Builder . CreatePointerCast ( Ptr , CharPtrTy ) ; Value * Tmp1 = Builder . CreateGEP ( Tmp0 , HVC . getConstInt ( Adjust ) ) ; return Builder . CreatePointerCast ( Tmp1 , ValTy


<s> addPass ( create<ISA_LIT>InsertWaitcntsPass ( ) ) ; addPass ( create<ISA_LIT>ModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>InsertHardClausesID ) ; addPass ( & <ISA_LIT>LateBranchLoweringPassID ) ; if ( isPassEnabled ( EnableSetWavePriority , CodeGenOpt :: Less ) ) addPass ( create<ISA_LIT>SetWavePriorityPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>PreEmitPeepholeID ) ; addPass ( & PostRAHazardRecognizerID


<s> return ( Candidate . isTerminator ( ) || Candidate . isCall ( ) || Candidate . isPosition ( ) || Candidate . isInlineAsm ( ) || Candidate .


<s> if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target32 ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>Target64


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( )


<s> } else if ( Info . OperandType == <STR_LIT> ) { encodeSLEB128 ( int64_t ( MO . getImm ( ) ) , OS ) ; } else { encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else { assert ( Desc . TSFlags == ( <STR_LIT> | <STR_LIT> ) ) ; encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else if ( MO . isFPImm ( ) ) { assert ( i < Desc . getNumOperands ( ) && <STR_LIT> ) ; assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ i ] ; if ( Info . OperandType == <STR_LIT> ) { float f = float ( MO . getFPImm ( ) ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < float > ( f ) ; } else { assert ( Info . OperandType == <STR_LIT> ) ; double d = MO . getFPImm ( ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < double > ( d ) ; } } else if ( MO . isExpr ( ) ) { Fixups . push_back ( MCFixup :: create ( OS . tell ( ) - Start , MO . getExpr ( ) , STI . getTargetTriple (

) . isArch64Bit ( ) ? FK_Data_8 : FK_Data_4 , MI . getLoc ( ) ) ) ;


<s> IsGlob ? MCSymbolRefExpr :: VK_<ISA_LIT>_GLOBAL : MCSymbolRefExpr :: VK_None ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , VK , Ctx ) ; if ( Offset != <NUM_LIT> ) { if ( IsFunc ) report_fatal_error ( <STR_LIT> ) ; if ( IsGlob ) report_fatal_error (


<s> if ( IN_RANGE ( REGNO ( op ) ^ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return true ; return


<s> break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT>


<s> return new <ISA_LIT>InsertPrefetch ( PrefetchHintsFile


<s> static void write_function_decl_and_comment ( std :: stringstream & s , const char * name , const_tree decl ) { s << <STR_LIT> ; if ( TREE_PUBLIC ( decl ) ) s << <STR_LIT> ; s << <STR_LIT>


<s> gimple * ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = <NUM_LIT> ; unsigned int actual_versions = <NUM_LIT> ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= <NUM_LIT> ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - <NUM_LIT> ) ) ; default_decl = ( * fndecls ) [ <NUM_LIT> ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = <NUM_LIT> ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority


<s> return Kind == Memory && ( ! Mem . Size ||


<s> Roots . insert ( NewRoots . begin ( ) , NewRoots . end ( ) ) ; NewRoots . clear ( ) ; for ( auto & F : M . functions ( ) ) { if ( F . isDeclaration ( ) ) continue ; const FnProperties CalleeProps ( * TM , F ) ; SmallVector < std :: pair < CallBase * , Function * > , <NUM_LIT> > ToReplace ; SmallSet < CallBase * , <NUM_LIT> > Visited ; for ( User * U : F . users ( ) ) { Instruction * I = dyn_cast < Instruction > ( U ) ; if ( ! I ) continue ; CallBase * CI = dyn_cast < CallBase > ( I ) ; if ( ! CI || CI -> getCalledOperand ( ) != & F ) continue ; Function * Caller = CI -> getCaller ( ) ; if ( ! Caller || ! Visited . insert ( CI ) . second ) continue ; if ( ! Roots . count ( Caller ) && ! NewRoots . count ( Caller ) ) continue ; const FnProperties CallerProps ( * TM , * Caller ) ; if ( CalleeProps == CallerProps ) { if ( ! Roots . count ( & F ) ) NewRoots . insert ( & F ) ; continue ; } Function * NewF = findFunction ( CallerProps , & F ) ; if ( ! NewF ) { const FnProperties NewProps = CalleeProps . adjustToCaller ( CallerProps ) ; if ( ! AllowClone ) { setFeatures ( F , NewProps . Features ) ; setAttributes ( F , NewProps . Attributes ) ; NewRoots . insert ( & F ) ; Changed = true ; break ; } NewF = cloneWithProperties ( F , NewProps ) ; Clones . push_back ( Clone ( CallerProps , & F , NewF ) ) ; NewRoots . insert ( NewF ) ; } ToReplace . push_back ( std :: make_pair ( CI , NewF ) ) ; Replaced . insert ( & F ) ; Changed = true ; } while ( ! ToReplace . empty


<s> if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ; } else MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; } Regs . clear ( ) ; ++ MI


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> (


<s> bool <ISA_LIT>AsmParser :: ParseDirective (


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . isInteger ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits (


<s> if ( FiOpc != <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; MIBundleBuilder Bundle ( BB , I ) ; unsigned MalkrzOpc = TII . getMalkrzFromFiMalkrz ( Opc ) ; unsigned MalkrzNumOperands = TII . get ( MalkrzOpc ) . getNumOperands ( ) ; MachineInstrBuilder Malkrz = BuildMI ( F , DL , TII . get ( MalkrzOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < MalkrzNumOperands ; i ++ ) { Malkrz . add ( MI . getOperand ( i ) ) ; } Bundle . prepend ( Malkrz ) ; unsigned FiNumOperands = TII . get ( FiOpc ) . getNumOperands ( ) ; MachineInstrBuilder Fi = BuildMI ( F , DL , TII . get ( FiOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < FiNumOperands ; i ++ ) { Fi . add ( MI . getOperand ( i + MalkrzNumOperands ) ) ; } Bundle . prepend ( Fi


<s> static unsigned int iq2000_function_arg_boundary ( machine_mode mode , const_tree type ) { return ( type != NULL_TREE ? ( TYPE_ALIGN ( type ) <= PARM_BOUNDARY ? PARM_BOUNDARY : TYPE_ALIGN ( type ) )

: ( GET_MODE_ALIGNMENT ( mode ) <= PARM_BOUNDARY ? PARM_BOUNDARY : GET_MODE_ALIGNMENT ( mode ) ) ) ;


<s> return MatchOperand_ParseFail ; } if ( MCE -> getValue ( ) < <NUM_LIT> || MCE -> getValue ( ) > <NUM_LIT> ) { Error ( ExprLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( MCE -> getValue ( ) , DB ? DB -> Name : <STR_LIT> , ExprLoc , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto DB = <STR_LIT> ( Tok . getString ( ) ) ; if ( Mnemonic == <STR_LIT> && ( ! DB || DB -> Encoding != <STR_LIT> ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( ! DB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateBarrier ( DB -> Encoding , Tok . getString ( ) , getLoc ( ) , getContext


<s> ConstantSDNode * CS ; if ( ( CS = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ) && CS -> getZExtValue ( ) == <NUM_LIT> ) OpIdx = <NUM_LIT> ; if ( ( CS = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ) && CS -> getZExtValue ( ) == <NUM_LIT> ) OpIdx = <NUM_LIT> ; if ( OpIdx == - <NUM_LIT> ) break ; SetCC = SetCC . getOperand ( OpIdx ) ; truncatedToBoolWithAnd = true ; } else SetCC = SetCC . getOperand ( <NUM_LIT> ) ; } switch ( SetCC . getOpcode ( ) ) { case <STR_LIT> : if ( checkAgainstTrue && ! truncatedToBoolWithAnd ) break ; assert ( <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && <STR_LIT> ) ; case <STR_LIT> : CC = <STR_LIT> ( SetCC . getConstantOperandVal ( <NUM_LIT> ) ) ; if ( needOppositeCond ) CC = <STR_LIT> ( CC ) ; return SetCC . getOperand ( <NUM_LIT> ) ; case <STR_LIT> : { ConstantSDNode * FVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * TVal = dyn_cast < ConstantSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) ; if ( ! TVal ) return SDValue ( ) ; if ( ! FVal ) { SDValue Op = SetCC . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || Op . getResNo ( ) != <NUM_LIT> ) return SDValue ( ) ; } bool FValIsFalse = true ; if ( FVal && FVal -> getZExtValue ( ) != <NUM_LIT> ) { if ( FVal -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; needOppositeCond = ! needOppositeCond ; FValIsFalse =


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return


<s> default : return <STR_LIT> ( CI . InstClass , Width ) ; case UNKNOWN : llvm_unreachable ( <STR_LIT> ) ; case S_BUFFER_LOAD_IMM : switch (


<s> for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { CodeSize += MI . getDesc ( ) . Size ; unsigned numOperands = MI . getNumOperands ( ) ; for ( unsigned op_idx = <NUM_LIT> ; op_idx < numOperands ; op_idx ++ ) { const MachineOperand & MO = MI . getOperand ( op_idx ) ; unsigned width = <NUM_LIT> ; bool isSGPR = false ; if ( ! MO . isReg ( ) ) { continue ; } unsigned reg = MO . getReg ( ) ; if ( reg == AMDGPU :: VCC || reg == AMDGPU :: VCC_LO || reg == AMDGPU :: VCC_HI ) { VCCUsed = true ; continue ; } switch ( reg ) { default : break ; case AMDGPU :: SCC : case AMDGPU :: EXEC : case AMDGPU :: M0 : continue ; } if ( AMDGPU :: SReg_32RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_32RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_64RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_64RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_96RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_128RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_128RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_256RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_256RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_512RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_512RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned hwReg = RI -> getEncodingValue ( reg ) & <NUM_LIT> ; unsigned maxUsed = hwReg + width - <NUM_LIT> ; if ( isSGPR ) { MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR ; } else


<s> return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget . hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendVecSize ( DL , SrcVec , <NUM_LIT> ) ; SrcVec = Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( SrcVec , DL , SubVT ) : DAG . getZeroExtendVectorInReg ( SrcVec , DL ,


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT>


<s> llvm :: Optional < ArchEnum > GetCpu ( ArchCont const & ArchList , Val CPUString ) { llvm :: Optional < ArchEnum > Res ; auto Entry = ArchList . find ( CPUString


<s> Size = Msbd + <NUM_LIT> - Pos ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } InsnType Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand ::


<s> for ( const MachineOperand & Use : MI . uses ( ) ) { if ( ! Use . isReg ( ) || ! Use . isUse ( ) ) continue ; Register Reg = Use . getReg ( ) ; if ( ! Reg . isVirtual ( ) ) { if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) continue ; for ( MCRegUnitIterator RegUnit ( Reg . asMCReg ( ) , TRI ) ; RegUnit . isValid ( ) ; ++ RegUnit ) { LiveRange & LR = LIS -> getRegUnit ( * RegUnit ) ; const VNInfo * Value = LR . Query ( LIS -> getInstructionIndex ( MI ) ) . valueIn ( ) ; if ( ! Value ) continue ; if ( MRI -> isSSA ( ) ) { if ( Value -> isPHIDef ( ) ) continue ; markInstruction ( * LIS -> getInstructionFromIndex ( Value -> def ) , Flag


<s> MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if

( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> if ( F -> getName ( ) . startswith ( <STR_LIT> ) )


<s> if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back (

getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ;


<s> bool need_mem ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != PLUS || GET_MODE ( x ) != Pmode ) return orig_x ; if ( XEXP ( x , <NUM_LIT> ) == pic_offset_table_rtx ) ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { rtx x0 = XEXP ( x , <NUM_LIT> ) ; rtx x00 = XEXP ( x0 , <NUM_LIT> ) ; rtx x01 = XEXP ( x0 , <NUM_LIT> ) ; if ( x00 == pic_offset_table_rtx ) addend = x01 ; else if ( x01 == pic_offset_table_rtx ) addend = x00 ; else return orig_x ; } else return orig_x ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != CONST ) return orig_x ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != UNSPEC ) return orig_x ; ret = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; if ( XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFF ) need_mem = false ; else if ( XINT ( x , <NUM_LIT> ) == UNSPEC_GOT ) need_mem = true ; else return orig_x ; gcc_assert ( GET_CODE ( ret ) == SYMBOL_REF ) ; if ( need_mem != MEM_P (


<s> if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { if ( NoHelperNeeded . find ( S -> getSymbol ( ) ) != NoHelperNeeded . end ( ) ) { LookupHelper = false ; } } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . Args , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg ,


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> )


<s> Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET

) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ;


<s> if ( ST -> hasAVX2 ( ) ) { int Idx = CostTableLookup < MVT > ( AVX2CostTable , array_lengthof ( AVX2CostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX2CostTable [ Idx ] . Cost ; } static const CostTblEntry < MVT > SSE2UniformConstCostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( Op2Info == TargetTransformInfo :: OK_UniformConstantValue && ST -> hasSSE2 ( ) ) { int Idx = CostTableLookup < MVT > ( SSE2UniformConstCostTable , array_lengthof ( SSE2UniformConstCostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE2UniformConstCostTable [ Idx ] . Cost ; } static const CostTblEntry < MVT > SSE2CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT>


<s> if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Arg ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> ) , Flag ) ; Flag = Chain .


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF )


<s> auto PrevMask = LiveMask ; LiveMask &= ~ getDefRegMask ( MO ) ; CurPressure . inc ( Reg , PrevMask , LiveMask , * MRI ) ; } for ( const auto & MO : MI . uses ( ) ) { if ( ! MO . isReg ( ) || ! MO . readsReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; auto Reg = MO . getReg ( ) ; auto & LiveMask = LiveRegs [ Reg ] ; auto PrevMask =


<s> unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << MI


<s> const MCSubtargetInfo * <ISA_LIT>AsmPrinter :: getSTI ( )


<s> case <STR_LIT> : case <STR_LIT> : return combineSIntToFP ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineVTRUNC ( N , DAG ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineCVTPH2PS ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( Op . isReg ( ) ) ; if ( In . isCall ( ) ) if ( Op . isDef ( ) && Op . isDead ( ) ) return true ; return false


<s> int size = s390_function_arg_size ( arg . mode , arg . type ) ; if ( s390_function_arg_vector ( arg . mode , arg . type ) ) return false ; if ( size > <NUM_LIT> ) return true ; if ( tree type = arg . type ) { if ( AGGREGATE_TYPE_P ( type ) && exact_log2 ( size ) < <NUM_LIT> ) return true ; if ( TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) return true ; } return false


<s> rtx src_addr ; rtx dest_addr ; rtx src_mem ; rtx dest_mem ; rtx tmp_reg ; rtx stores [ MAX_MOVE_REG ] ; int move_bytes ; enum machine_mode mode ; if ( ! constp ) return FALSE ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return TRUE ; if ( bytes > TOTAL_MOVE_REG * align ) return FALSE ; dest_reg = copy_addr_to_reg ( XEXP ( orig_dest , <NUM_LIT> ) ) ; src_reg = copy_addr_to_reg ( XEXP ( orig_src , <NUM_LIT> ) ) ; num_reg = offset = <NUM_LIT> ; for ( ; bytes > <NUM_LIT> ; ( bytes -= move_bytes ) , ( offset += move_bytes ) ) { if ( offset == <NUM_LIT> ) { src_addr =


<s> ClobbersEFLAGS = true ; break ; } } if ( ClobbersEFLAGS && ! isSafeToClobberEFLAGS ( MBB , I ) ) { int Value ; switch ( Orig -> getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const DebugLoc & DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( Orig -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; } else { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I


<s> MCGNodeUInt :: const_iterator nodeOccupancy ( MinOccupancy . find ( node ) ) ; if ( nodeOccupancy == MinOccupancy . end ( ) ) MinOccupancy [ node ] = occupancy ; else MinOccupancy [ node ] = std :: min ( MinOccupancy


<s> bool ResourceAssignment :: isCopy ( SUnit *


<s> if ( ! register_operand ( cmp_op0 , cmp_mode ) ) cmp_op0 = force_reg ( cmp_mode , cmp_op0 ) ; insn = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( cc_mode , CC_REGNUM ) , gen_rtx_COMPARE ( cc_mode , cmp_op0 , cmp_op1 ) ) ; ret = insn_invalid_p ( emit_insn ( insn ) , false ) ; gcc_assert ( ! ret ) ; op_res = gen_rtx_fmt_ee ( cmp_code , GET_MODE ( dst ) , gen_rtx_REG ( cc_mode , CC_REGNUM ) , const0_rtx ) ; if ( src != const0_rtx ) { if ( ! register_operand ( src , GET_MODE ( dst ) ) ) src = force_reg ( GET_MODE ( dst ) , src ) ; op_res = gen_rtx_PLUS ( GET_MODE ( dst ) , op_res , src ) ; op_res = gen_rtx_PLUS ( GET_MODE ( dst ) , op_res , const0_rtx ) ; } p = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( p , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , dst , op_res ) ; RTVEC_ELT ( p , <NUM_LIT> ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , CC_REGNUM ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return true ; } if ( increment == constm1_rtx ) { if ( cmp_code == EQ || cmp_code == NE ) { if ( cmp_op1 != const0_rtx ) { cmp_op0 = expand_simple_binop ( cmp_mode , XOR , cmp_op0 , cmp_op1 , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; cmp_op1 = const0_rtx ; } cmp_code = cmp_code == EQ ? LEU : GTU ; } if ( cmp_code == GTU || cmp_code == GEU


<s> return SelectAddrRI12 ( Op , Addr , Base


<s> int regno ; if ( ! REG_P ( x ) ) return <NUM_LIT> ; regno = REGNO ( x ) ; if ( strict_p ) return THUMB1_REGNO_MODE_OK_FOR_BASE_P ( regno , mode ) ; return ( regno <= LAST_LO_REGNUM || regno > LAST_VIRTUAL_REGISTER || regno == FRAME_POINTER_REGNUM || ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> && (

regno == STACK_POINTER_REGNUM || regno >= FIRST_PSEUDO_REGISTER || x == hard_frame_pointer_rtx || x == arg_pointer_rtx ) ) ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target


<s> EmitAlignment ( <NUM_LIT> , F ) ; O << <STR_LIT> << CurrentFnName << '\n' ; printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << CurrentFnName << <STR_LIT> ; NumberForBB . clear ( ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++


<s> unsigned getWorkItemIDVGPR ( unsigned Dim ) const { switch ( Dim ) { case <NUM_LIT> : assert ( hasWorkItemIDX ( ) ) ; return <STR_LIT> ; case <NUM_LIT> : assert ( hasWorkItemIDY ( ) ) ; return <STR_LIT> ; case <NUM_LIT> : assert ( hasWorkItemIDZ ( ) ) ; return <STR_LIT>


<s> d . op1 = op1 ; d . vmode = vmode ; d . nelt = nelt ; d . one_operand_p = false ; d . testing_p = false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d


<s> static std :: string computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) return <STR_LIT> ; assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT>


<s> if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; } else { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true


<s> bool <ISA_LIT>AdvSIMDScalar :: runOnMachineFunction ( MachineFunction & mf ) { bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( skipFunction ( * mf .


<s> Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , InFlag , dl ) ; InFlag = Chain .


<s> } const MCConstantExpr * CE = static_cast < const MCConstantExpr * > ( getImm ( ) ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: createReg


<s> if ( C && C -> isNullValue ( ) ) VL = SDValue ( selectImm ( CurDAG , SDLoc ( N ) , <NUM_LIT> , Subtarget -> getXLenVT ( ) ) , <NUM_LIT> ) ; else VL = N ; return true


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { CPUString = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( getTargetTriple ( ) , CPU ) ; static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , } ; auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVXOps = false ; UseHVXDblOps = false ; UseLongCalls = false ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( Enable<ISA_LIT>HVX . getPosition ( ) ) UseHVXOps = Enable<ISA_LIT>HVX ; if ( Enable<ISA_LIT>HVXDouble . getPosition ( ) ) UseHVXDblOps = Enable<ISA_LIT>HVXDouble ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; return * this


<s> case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [


<s> bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg ) . addImm ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) . addReg ( DstReg , RegState :: Kill ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) . addReg ( DstReg , RegState :: Kill ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ; return true


<s> SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation =


<s> AM . GV = GV ; AM . GVOpFlags = STI . classifyGlobalReference ( GV ) ; if ( isGlobalStubReference ( AM . GVOpFlags ) ) return false ; if ( isGlobalRelativeToPICBase ( AM . GVOpFlags ) ) return false ; if ( STI . isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; unsigned NewOpc = getLeaOP ( Ty , STI ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF


<s> if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) return RR ; const TargetRegisterClass * RC = RegInfos [ RR . Reg ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ; LaneBitmask Common = RR .


<s> if ( Subtarget . hasFp256 ( ) ) { if ( ResVT . is128BitVector ( ) && ( InVT . is256BitVector ( ) || InVT . is512BitVector ( ) ) && isa < ConstantSDNode > ( Idx ) ) { return Extract128BitVector ( In , IdxVal ,


<s> if ( MRI -> isSSA ( ) ) { for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; unsigned TrueReg = TRI -> lookThruCopyLike ( Reg , MRI ) ; if ( TargetRegisterInfo :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III , true ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Reg = Reg - <STR_LIT> + <STR_LIT> ; for ( ; It != E ; ++ It


<s> unsigned Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) -> getReg ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . addReg ( Reg , getDefRegState ( ! IsStore ) ) . addOperand ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . addOperand ( * TII -> getNamedOperand ( * MI

, <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getPrefetchDistance ( ) const { return <NUM_LIT>


<s> if ( ! IsPreserveDIAccessIndexCall ( Call , CInfo ) || AIChain . find ( Call ) != AIChain . end ( ) ) continue ; traceAICall ( Call


<s> unsigned char OpFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; EVT DestEVT = TLI . getValueType ( GV -> getType ( ) , true ) ; if ( ! DestEVT . isSimple ( ) ) return <NUM_LIT> ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; unsigned ResultReg ; if ( OpFlags & <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> ,


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat ( )


<s> else if ( ! ( modes & GOMP_DIM_MASK ( mode ) ) ) { } else if ( par -> inner_mask & GOMP_DIM_MASK ( mode ) || ! par -> forked_insn ) neuter_mask |= GOMP_DIM_MASK ( mode ) ; else if ( ! par -> parent || ! par -> parent -> forked_insn || par -> parent -> inner_mask & GOMP_DIM_MASK ( mode ) ) skip_mask |= GOMP_DIM_MASK ( mode ) ; else { } } if ( neuter_mask ) { int ix , len ; if ( nvptx_optimize ) { bb_pair_vec_t regions ; nvptx_find_sese ( par -> blocks , regions ) ; len = regions .


<s> assert ( Phi -> isPHI ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) if ( isLoopFeeder ( L , MBB , Phi , & ( Phi -> getOperand ( i ) ) , LoopFeederPhi ) ) if ( loopCountMayWrapOrUnderFlow ( & ( Phi -> getOperand ( i ) ) , EndVal , Phi -> getParent ( ) , L , LoopFeederPhi ) ) return true ; return false


<s> SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; SDLoc dl ( Op ) ; if ( ST -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty =


<s> std :: vector < EVT > ResTys ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( SrcReg ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain


<s> void addAlignedMemory64Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst ,


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> )


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( Pred )

. addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> static inline bool isOptSize ( const MachineFunction & MF ) { const Function & F = MF . getFunction


<s> static bool isInSmallSection ( uint64_t


<s> return ( uint8x8_t ) __builtin_neon_vqshluv8qi ( (


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg


<s> CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; return true


<s> return Ret ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent


<s> if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> ,


<s> return ( __m64 ) __builtin_arm_wqmulm ( ( __v4hi ) a ,