<s> switch ( Modifier ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> return DAG . getRegister ( FI -> getGlobalBaseReg (


<s> MachineOperand & JTI3 = MI -> getOperand ( <NUM_LIT> ) ; if ( ! Reg0 . isReg ( ) ) return false ; if ( ! Reg2 . isReg ( ) ) return false ; if ( ! Reg4 . isReg ( ) ) return false ; if ( ! Imm1 . isImm ( ) ) return false ; if ( ! JTI3 . isJTI ( ) ) return false ; MI -> dump ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterClass * RC = STI . is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned VReg1 = MF . getRegInfo ( ) . createVirtualRegister


<s> auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG . getValueType ( RetVT ) ; if ( RetVT . isFloatingPoint ( ) ) OutVT = DAG . getValueType ( HwRetVt ) ; SDVTList VTs = DAG . getVTList ( HwRetVt , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Base , Offset , OutVT } ; SDValue Load = DAG . getNode ( Opcode , DL ,


<s> bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue NL = DAG . getLoad ( LN -> getAddressingMode ( ) , LN -> getExtensionType ( ) , <STR_LIT> , dl , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getOffset ( ) , LN -> getPointerInfo ( ) , <STR_LIT> , LN -> getAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) , LN -> getAAInfo ( ) , LN -> getRanges ( ) ) ; LN = cast < LoadSDNode > ( NL . getNode ( ) ) ; } Align ClaimAlign = LN -> getAlign ( ) ; if ( ! validateConstPtrAlignment ( LN -> getBasePtr ( ) , ClaimAlign , dl , DAG ) ) return replaceMemWithUndef ( Op , DAG ) ; SDValue LU = LowerUnalignedLoad ( SDValue ( LN , <NUM_LIT> ) , DAG ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , Ty , LU ) ; SDValue Ch = cast < LoadSDNode > ( LU . getNode ( ) ) -> getChain ( ) ; return DAG . getMergeValues ( { TC , Ch } , dl ) ; } return


<s> return CreateReg ( Index , RegKind_HWRegs , RegInfo , S ,


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Z ( TheARM64leTarget ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > W ( TheARM64beTarget


<s> static bool isUseSafeToFold ( const MachineInstr & MI , const MachineOperand & UseMO ) { return ! UseMO . isUndef


<s> tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( TARGET_SILVERMONT || TARGET_INTEL ) if ( stmt_info &&


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Rt == Rt2 ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt2 = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI -> isSubRegisterEq ( Rn , Rt ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; if ( RI -> isSubRegisterEq ( Rn , Rt2 ) ) return Error ( Loc [ <NUM_LIT> ] , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = Inst . getOperand ( <NUM_LIT> )


<s> uint8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a


<s> break ; } break ; } case Type :: FloatTyID : return <STR_LIT> ; case Type :: DoubleTyID : return <STR_LIT> ; case Type :: PointerTyID : if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; else if ( useB4PTR ) return <STR_LIT> ; else return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; return nullptr


<s> assert ( last -> getKind ( ) == Fragment :: Null ) ; tmp . splice ( tmp . end ( ) , list , first ) ; tmp . splice ( tmp . end ( ) , list , last ) ; } sort ( list , ExIdxFragmentComparator ( * m_pExData ) ) ; llvm :: StringRef cantUnwindRegion ( g_CantUnwindEntry , sizeof ( g_CantUnwindEntry ) ) ; SectionData :: FragmentListType :: iterator it = list . begin ( ) ; if ( it != list . end ( ) ) { Fragment * prevTextFrag = m_pExData -> getTupleByExIdx ( & * it ) -> getTextFragment ( ) ; uint64_t prevTextEnd = prevTextFrag -> getParent ( ) -> getSection ( ) . addr ( ) + prevTextFrag -> getOffset ( ) + prevTextFrag -> size ( ) ; ++ it ; while ( it != list . end ( ) ) { Fragment * currTextFrag = m_pExData -> getTupleByExIdx ( & * it ) -> getTextFragment ( ) ; uint64_t currTextBegin = currTextFrag -> getParent ( ) -> getSection ( ) . addr ( ) + currTextFrag -> getOffset ( ) ; if ( currTextBegin > prevTextEnd ) { RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . insert ( it , frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) , * FragmentRef :: Create ( * frag , <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( CreateLocalSymbolToFragmentEnd ( pModule , * prevTextFrag ) ) ; addExtraRelocation ( reloc ) ; } prevTextEnd = currTextBegin + currTextFrag -> size ( ) ; prevTextFrag = currTextFrag ; ++ it ; } RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . push_back ( frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) , * FragmentRef :: Create ( * frag , <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( CreateLocalSymbolToFragmentEnd ( pModule , * prevTextFrag ) ) ; addExtraRelocation ( reloc ) ; } list . splice ( list . begin ( ) , tmp , tmp . begin ( ) ) ; list . splice ( list . end ( ) , tmp , tmp . begin ( ) ) ; uint64_t offset = <NUM_LIT> ; for ( SectionData :: iterator it = sectData -> begin ( ) , end = sectData -> end ( ) ; it != end ; ++


<s> if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; return


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask ( ) const { return


<s> static <STR_LIT> GetCondFromBranchOpc ( unsigned BrOpc ) { switch ( BrOpc ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> return ( OptLevel >= CodeGenOpt :: Aggressive ) && ! VT


<s> unsigned NumVectors = getNumVectorRegs ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) { case TargetTransformInfo :: SK_ExtractSubvector : return ( Index == <NUM_LIT> ? <NUM_LIT> : NumVectors ) ; case TargetTransformInfo :: SK_Broadcast : return NumVectors - <NUM_LIT> ; default : return


<s> static alias_set_type ix86_GOT_alias_set ( void ) { static alias_set_type set = -


<s> return new <ISA_LIT>ELFObjectWriter ( true , OSType , ELF :: EM_<ISA_LIT>_64 ,


<s> return ( Val < <NUM_LIT> ) || ( Val >= Low && Val <


<s> if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) return ; if ( Operands . size ( ) < <NUM_LIT> ) return ; <ISA_LIT>Operand & Op2 = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; <ISA_LIT>Operand & Op3 = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( ! Op2 . isReg ( ) ) return ; if ( ! Op3 . isMem ( ) ) return ; const MCRegisterClass & GPR = MRI -> getRegClass ( <STR_LIT> ) ; if ( ! GPR . contains ( Op2 . getReg


<s> if ( isPopOpcode ( MI -> getOpcode ( ) ) ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return


<s> if ( InputModifiers & <STR_LIT> ) O << '-' ; if ( InputModifiers & <STR_LIT> ) O << '|' ; printOperand ( MI , OpNo


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) , RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TV = Op . getOperand ( <NUM_LIT> ) , FV = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue Sel1 ; if ( isFloatingPointZero ( RHS ) ) switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default :


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return reportParseError ( <STR_LIT> ) ; Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( )


<s> if ( ! Src0Reg ) return false ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( SrcVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Src0Reg ) . addReg ( Src1Reg ) . addReg


<s> if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitHi ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitLo ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_LO | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitHi ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_HI | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; return ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; return ; } assert ( ST . getGeneration ( ) <


<s> signed int i [ <NUM_LIT> ] ; } aa ; aa . v = ( vector signed int ) ( a ) ; if ( aa . i [ <NUM_LIT> ] > b ) {


<s> <STR_LIT> IntrID = <STR_LIT> :: not_intrinsic ; switch ( N ) { case <NUM_LIT> : IntrID = IsAMDGCN ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : IntrID = IsAMDGCN ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : IntrID = IsAMDGCN ? <STR_LIT> : <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Function * WorkitemIdFn = <STR_LIT> ( Mod , IntrID ) ; CallInst * CI = Builder .


<s> if ( Data && Op . isIdenticalTo ( * Data ) ) return true ; MachineOperand * Data0 = TII -> getNamedOperand ( MI , <STR_LIT> :: data0 ) ; if ( Data0 && Op . isIdenticalTo ( * Data0 ) ) return true ; MachineOperand * Data1 = TII -> getNamedOperand ( MI , <STR_LIT> :: data1 ) ; if ( Data1 && Op . isIdenticalTo ( * Data1 ) ) return true ; return false ; } for ( MachineInstr :: mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( I -> isReg ( ) && I -> isUse ( ) ) return Op . isIdenticalTo ( * I ) ; } return false


<s> unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( RegisterPair ) ) ; return S


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( Zeroable . countLeadingOnes ( ) < ( Mask . size ( ) - <NUM_LIT> ) ) return SDValue ( ) ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; V1 = DAG . getNode ( <STR_LIT> ,


<s> if ( ! RestrictUseOfBaseReg ( ) ) { if ( AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr ) { AM . Base_Reg = AM . IndexReg ; AM . Scale = <NUM_LIT> ; } } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr && AM . IndexReg . getNode ( ) == nullptr && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false


<s> static unsigned HOST_WIDE_INT riscv_asan_shadow_offset ( void ) { return TARGET_64BIT ? ( HOST_WIDE_INT_1


<s> static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC = <STR_LIT> ; for ( unsigned Reg : RC ) for ( MCSubRegIterator SI ( Reg , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) markSuperRegs ( Reserved , Reg ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm1 ( SDValue N , SDValue & Imm ) const { llvm_unreachable ( <STR_LIT>


<s> OS << getRegisterName ( MI -> getOperand ( opNum + <NUM_LIT> ) . getReg


<s> bool DelayHazardInfo :: hasHazard ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { if ( MI . isCall ( ) && PDSF . TII -> getInstrSize ( & * I ) != <NUM_LIT> ) return true ; if ( I -> isBundle ( ) ) { MachineBasicBlock :: instr_iterator II = I . getInstrIterator ( ) ; ++ II ; for ( ; II != MBB . instr_end ( ) && II -> isInsideBundle ( ) ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; if ( II -> isImplicitDef ( ) ) continue ; if ( hasHazard ( MBB , II ) ) return true ; } return false ; } assert ( ! I -> isKill ( ) && ! I -> hasDelaySlot ( ) ) ; const <ISA_LIT>InstrInfo * TII = PDSF . TII ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( I -> mayLoad ( ) ) { sawLoad = true ; if ( sawStore ) return true ; } if ( I -> mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ; if ( sawLoad ) return true ; } if ( I -> mayLoad ( ) && Candidates . empty ( ) && ( MI . isCall ( ) || MI . isReturn ( ) ) ) return true ; if ( I -> mayLoad ( ) && ! Candidates . empty ( ) && PDSF . hasDefUseDep ( & * I , Candidates . back ( ) ) ) return true ; if ( TII -> isStackControl ( & * I ) ) { sawSTC = true ; return true ; } if ( ( I -> mayLoad ( ) || I -> mayStore ( ) ) && TII -> getMemType ( * I ) == <STR_LIT> && sawSTC ) return true ; if ( I -> hasUnmodeledSideEffects ( ) && ! TII -> isSideEffectFreeSRegAccess ( & * I ) ) return true ; for ( MachineInstr :: const_mop_iterator MO = I -> operands_begin ( ) ; MO != I -> operands_end (


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! hasFP ( MF ) && ! AFI -> isInterruptOrSignalHandler ( ) ) { return ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize ) { restoreStatusRegister ( MF , MBB ) ; return ; } while ( MBBI != MBB . begin ( )


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT


<s> return ! Revert && FoundAllComponents ( ) && ! VCTPs . empty ( ) && ! CannotTailPredicate && ML . getNumBlocks (


<s> unsigned BasePtr = ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int Offset = getFrameIndexOffset ( MF , FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . setDesc ( TII . getMemoryInstr ( MI . getOpcode ( )


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter , bool IsThumb ) : MCELFStreamer ( Context , std :: move ( TAB )

, OS , std :: move ( Emitter ) ) , IsThumb ( IsThumb ) {


<s> static hsa_status_t get_heap_region ( hsa_region_t region , void * data __attribute__ ( ( unused ) ) ) { return get_memory_region ( region ,

& heap_region , HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED ) ;


<s> unsigned CPELogAlign = getCPELogAlign ( * CPEMI ) ; MachineBasicBlock * UserMBB = UserMI -> getParent ( ) ; const BasicBlockInfo & UserBBI = BBInfo [ UserMBB -> getNumber ( ) ] ; if ( BBHasFallthrough ( UserMBB ) ) { unsigned Delta = <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << UserMBB -> getNumber ( ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex =


<s> V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { V2 = V1 ; Shuffle = <STR_LIT> ; ShuffleVT = Mask . size ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { V2 = V1


<s> int R600InstrInfo :: getSrcIdx ( unsigned Opcode , unsigned SrcNum ) const { static const unsigned OpTable [ ] = { AMDGPU :: OpName :: src0 , AMDGPU :: OpName :: src1 , AMDGPU :: OpName ::


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy (


<s> OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst TC ; TC . setOpcode ( OpCode ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) )

TC . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> if ( Opc == TargetOpcode :: COPY && TargetRegisterInfo :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { CondCode = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( ! emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> rtx gen_df_reg ( rtx reg , int low ) { int regno = REGNO ( reg


<s> else { rtx got , tga , tmp1 , tmp2 ; if ( rs6000_pcrel_p ( ) ) got = const0_rtx ; else if ( TARGET_64BIT ) got = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else { if ( flag_pic == <NUM_LIT> ) got = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; else { rtx gsym = rs6000_got_sym ( ) ; got = gen_reg_rtx ( Pmode ) ; if ( flag_pic == <NUM_LIT> ) rs6000_emit_move ( got , gsym , Pmode ) ; else { rtx mem , lab ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr , got ) , UNSPEC_TLSGD ) ; tga = rs6000_tls_get_addr ( ) ; rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg ) ) ; global_tlsarg = arg ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , argreg , Pmode ) ; global_tlsarg = NULL_RTX ; rtvec vec = gen_rtvec ( <NUM_LIT> , copy_rtx ( arg ) ) ; rtx uns = gen_rtx_UNSPEC ( Pmode , vec , UNSPEC_TLS_GET_ADDR ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , uns ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , got ) , UNSPEC_TLSLD ) ; tga = rs6000_tls_get_addr ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg )


<s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> virtual void Initialize ( MCContext & Ctx , const TargetMachine


<s> Register FlagReg1 = createResultReg ( & <STR_LIT> ) ; Register FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( CC ) ; updateValueMap ( I , ResultReg )


<s> int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ; const char * fmt = GET_RTX_FORMAT


<s> EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value , Size


<s> bool <ISA_LIT>InstrInfo :: hasInstrModifiers ( unsigned Opcode ) const { unsigned TargetFlags = get (


<s> } else if ( IsIndirect ) { CallOp = <STR_LIT> ; } else if ( IsRetCall ) { CallOp = <STR_LIT> ; } else { CallOp = <STR_LIT> ; } MachineFunction & MF = * BB -> getParent ( ) ; const MCInstrDesc & MCID = TII . get ( CallOp ) ; MachineInstrBuilder MIB ( MF , MF . CreateMachineInstr ( MCID , DL ) ) ; if ( IsIndirect && MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ) { Register Reg32 = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; auto & FnPtr = CallParams . getOperand ( <NUM_LIT> ) ; BuildMI ( * BB , CallResults . getIterator ( ) , DL , TII . get ( <STR_LIT> ) , Reg32 ) . addReg ( FnPtr . getReg ( ) ) ; FnPtr . setReg ( Reg32 ) ; } if ( IsIndirect ) { auto FnPtr = CallParams . getOperand ( <NUM_LIT> ) ; CallParams . removeOperand ( <NUM_LIT> ) ; if ( IsFuncrefCall ) { Register RegZero = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder MIBC0 = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) , RegZero ) . addImm ( <NUM_LIT> ) ; BB -> insert ( CallResults . getIterator ( ) , MIBC0 ) ; MachineInstrBuilder ( MF , CallParams ) . addReg ( RegZero ) ; } else CallParams . addOperand ( FnPtr ) ; } for ( auto Def : CallResults . defs ( ) ) MIB . add ( Def ) ; if ( IsIndirect ) { MIB . addImm ( <NUM_LIT> ) ; MCSymbolWasm * Table = IsFuncrefCall ? <STR_LIT> ( MF . getContext ( ) , Subtarget ) : <STR_LIT> ( MF . getContext ( ) , Subtarget ) ; if ( Subtarget -> hasReferenceTypes ( ) ) { MIB . addSym ( Table ) ; } else { Table -> setNoStrip ( ) ; MIB . addImm ( <NUM_LIT> ) ; } } for ( auto Use : CallParams . uses ( ) ) MIB . add ( Use ) ; BB -> insert ( CallResults . getIterator ( ) , MIB ) ; CallParams . eraseFromParent ( ) ; CallResults . eraseFromParent


<s> auto IsExpiredFn = [ ] ( MachineInstr * MI , int ) { return MI && ( <ISA_LIT>InstrInfo :: isVALU ( * MI ) || ( MI -> getOpcode ( ) == <STR_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } ; if ( :: getWaitStatesSince ( IsHazardFn , MI , IsExpiredFn ) == std :: numeric_limits < int > :: max ( ) ) return false ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; return true


<s> unsigned BlackfinInstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond ) const { DebugLoc DL ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT>


<s> if ( isThumb2 ( STI ) ) { EncodedValue |= <NUM_LIT> ; } return


<s> int getFramePointerOffset ( ) const { return FramePointerOffset


<s> SDValue B = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , A , ShAmt ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , B , ShAmt ) ; EVT MulVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; A = DAG . getNode ( <STR_LIT> , dl , MulVT , A ) ; B = DAG . getNode ( <STR_LIT> , dl , MulVT , B ) ; Ahi = DAG . getNode ( <STR_LIT> , dl , MulVT , Ahi ) ; Bhi = DAG . getNode ( <STR_LIT> , dl , MulVT , Bhi ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT ,


<s> Register getTIDReg ( ) const { return TIDReg


<s> assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned FromSz = LdVT . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( ! Mld -> getSrc0 ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ]


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = Subtarget


<s> void <ISA_LIT>AIXAsmPrinter :: EmitFunctionDescriptor ( ) { const DataLayout & DL = getDataLayout ( ) ; const unsigned PointerSize = DL . getPointerSizeInBits ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > (

CurrentFnDescSym ) -> getContainingCsect ( ) ) ;


<s> static void emit<ISA_LIT>ValidatorVersion ( Module & M , VersionTuple & ValidatorVer ) { NamedMDNode * <ISA_LIT>ValidatorVersionMD = M . getNamedMetadata ( ValVerKey ) ; if ( <ISA_LIT>ValidatorVersionMD ) M . eraseNamedMetadata


<s> SDValue <ISA_LIT>TargetLowering :: LowerBUILD_VECTORvXi1 ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Imm = ConvertI1VectorToInteger ( Op , DAG ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , Imm ) ; SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef ( )


<s> LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; Register From = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register To = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT FromType = Builder . getMRI ( ) -> getType ( From ) ; LLT ToType = Builder . getMRI ( ) -> getType


<s> void printDstIdx8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printDstIdx ( MI , OpNo , O


<s> static __inline __m64 _mm_tbcst_pi32 ( int value ) { return ( __m64 ) __builtin_arm_tbcstw


<s> thunk_name = thunk_name_buf ; } else thunk_name = NULL ; if ( sibcall_p ) { if ( thunk_name != NULL ) { if ( need_prefix == indirect_thunk_prefix_bnd ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; } else output_indirect_thunk ( need_prefix , regno ) ; } else { if ( thunk_name != NULL ) { if ( need_prefix == indirect_thunk_prefix_bnd ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; return ; } char indirectlabel1 [ <NUM_LIT> ] ; char indirectlabel2 [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; if ( need_prefix == indirect_thunk_prefix_bnd ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( thunk_name


<s> unsigned regCode = getRegBinaryCode ( MI . getOperand ( OpNo ) . getReg ( ) ) ; return regCode >> shift ; return <NUM_LIT>


<s> MachineBasicBlock :: iterator DefMI = MRI -> getVRegDef ( Reg ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> || DefMI -> getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ; for ( auto I = DefMI ; I != FrameSetup ; ++ I ) if ( I -> isLoadFoldBarrier ( ) ) return nullptr ; return


<s> SDValue FrameIndex = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , FrameIndex , Op

. getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Imm . getActiveBits ( ) >= <NUM_LIT> ) return <NUM_LIT> ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( Bits == <NUM_LIT> || ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) ) return <NUM_LIT> ; if ( ( ~ SImmVal < <NUM_LIT> ) || <STR_LIT> ( ZImmVal ) ) return <NUM_LIT> ; return


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const <ISA_LIT>TargetLowering & TLI = * static_cast < const <ISA_LIT>TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType (


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > (


<s> inline vector signed char vec_splat_s8 ( const


<s> bool <ISA_LIT>LowerRefTypesIntPtrConv :: runOnFunction ( Function & F ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << F . getName ( ) << '\n' ) ; std :: set < Instruction * > worklist ; for ( inst_iterator I = inst_begin ( F ) , E = inst_end ( F ) ; I != E ; ++ I ) { PtrToIntInst * PTI = dyn_cast < PtrToIntInst > ( & *


<s> for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg

) . addReg ( VR ) . addImm ( ShiftAmount ) ;


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast <


<s> for ( s = cpu_string ; * s != <NUM_LIT> ; s ++ ) if ( ISUPPER ( * s ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; break ; } if ( strcasecmp ( cpu_string , <STR_LIT> ) == <NUM_LIT> ) return mips_cpu_info_from_isa ( ABI_NEEDS_32BIT_REGS ? <NUM_LIT> : ABI_NEEDS_64BIT_REGS ? <NUM_LIT> : ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) ; if ( strcasecmp ( cpu_string , <STR_LIT> ) == <NUM_LIT>


<s> case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << MI -> getOperand ( OpNum ) . getImm ( ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false ; case 'Q' : case 'R' : case 'H' : report_fatal_error ( <STR_LIT> ) ; return true ; } } printOperand ( MI , OpNum , O ) ; return false


<s> assert ( Kind == KindTy :: Immediate && <STR_LIT> ) ; return Imm . Val


<s> if ( Mask . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Mask . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N ,


<s> } if ( cfun -> va_list_fpr_size ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( fpr ) , fpr , build_int_cst ( NULL_TREE , n_fpr ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( call_ABI_of_interest ( cfun -> decl ) ) rs6000_passes_float = true ; } t = make_tree ( TREE_TYPE ( ovf ) , virtual_incoming_args_rtx ) ; if ( words != <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , words * MIN_UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovf ) , ovf , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( ! cfun -> va_list_gpr_size && ! cfun -> va_list_fpr_size && n_gpr < GP_ARG_NUM_REG && n_fpr < FP_ARG_V4_MAX_REG ) return ; t = make_tree ( TREE_TYPE ( sav ) , virtual_stack_vars_rtx ) ; if ( cfun -> machine -> varargs_save_offset ) t = fold_build_pointer_plus_hwi ( t , cfun -> machine -> varargs_save_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( sav ) , sav , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx ,


<s> if ( none_of ( Defs , isa < Instruction , Value * > ) ) return false ; for ( Value * V : Defs ) if ( ! isa < PHINode > ( V ) && ! isa < Constant > ( V ) && ! isa < Argument > ( V ) && ! isa < CallInst > ( V ) ) return false ; for ( Value * V : Defs ) if ( const PHINode * P = dyn_cast < PHINode > ( V ) ) if ( ! PromotablePHINodes . count ( P ) ) return false ; if ( isa < ReturnInst > ( U . getUser ( ) ) ) ++ NumBoolRetPromotion ; if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { User * First = dyn_cast < User > ( Pair . first ) ; User * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U


<s> if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isTerminator ( ) ) return MachineOutlinerInfo

( <NUM_LIT> , <NUM_LIT> , MachineOutlinerTailCall , MachineOutlinerTailCall ) ;


<s> return packBits ( Lgkmcnt , Waitcnt , getLgkmcntBitShift ( )

, getLgkmcntBitWidth ( Version . Major ) ) ;


<s> int i = <NUM_LIT> ; while ( PredefinedFuncs [ i ] . Name ) { name_ = PredefinedFuncs [ i ] .


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , EE = MBB . end ( ) ; MBBI != EE ; ++ MBBI ) { if ( MBBI -> getOpcode ( ) == <STR_LIT>


<s> Frame . Begin = getContext ( ) . createTempSymbol


<s> return Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg ==


<s> if ( DstRC == OpRC ) return ; unsigned DstReg = MRI . createVirtualRegister ( DstRC ) ; MachineInstr * Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . add ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def


<s> for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return Changed ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = LoLoop . Dec = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } assert ( LoLoop . Start -> getOpcode ( ) != <STR_LIT> && <STR_LIT> ) ; if ( LoLoop . Dec != LoLoop .


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTarget26OpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >>


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm ( ) && ! ( MO . getImm


<s> static bool scalar_move_insn_p ( rtx_insn * rinsn


<s> DebugLoc DL = Op . getDebugLoc ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode >


<s> return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return false ; Imm = N ; if ( N -> getOpcode ( ) != <STR_LIT> ) return TM . getCodeModel ( ) == CodeModel :: Small ; Optional < ConstantRange > CR = cast < GlobalAddressSDNode > ( N

) -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ;


<s> } EVT IdiomVT = Op . getValueType ( ) ; if ( isPackedVectorType ( IdiomVT ) && ! supportsPackedMode ( Op . getOpcode ( ) , IdiomVT

) ) return splitVectorOp ( Op , CDAG ) ;


<s> static void toggleSPDenormMode ( bool Enable , MachineIRBuilder & B , const GCNSubtarget & ST , <STR_LIT> Mode ) { unsigned SPDenormMode = Enable ? FP_DENORM_FLUSH_NONE : Mode . fpDenormModeSPValue ( ) ; if ( ST . hasDenormModeInst ( ) ) { uint32_t DPDenormModeDefault = Mode . fpDenormModeDPValue ( ) ; uint32_t NewDenormModeValue = SPDenormMode | ( DPDenormModeDefault << <NUM_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addImm ( NewDenormModeValue ) ; } else { unsigned SPDenormModeBitField = <STR_LIT> :: ID_MODE | ( <NUM_LIT> << <STR_LIT> :: OFFSET_SHIFT_ ) | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ; B . buildInstr ( <STR_LIT> ) . addImm

( SPDenormMode ) . addImm ( SPDenormModeBitField ) ;


<s> void pdp11_gen_int_label ( char * label , const char * prefix , int num ) { if ( TARGET_DEC_ASM ) sprintf ( label , <STR_LIT> , num + <NUM_LIT> ) ; else sprintf ( label , <STR_LIT>


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isInlineAsm ( ) )


<s> for ( const TargetRegisterClass * BaseClass : BaseClasses ) { if ( BaseClass -> contains ( Reg ) ) return BaseClass ; } return


<s> MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) ,


<s> SmallVector < SDValue , <NUM_LIT> > Res ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op0 ( MaxFactor ) ; SmallVector < SDValue , <NUM_LIT> > Op1 ( MaxFactor ) ; unsigned Factors = <NUM_LIT> ; Op0 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; Op1 [ <NUM_LIT> ] = Op . getOperand ( <NUM_LIT> ) ; for ( ; Factors < MaxFactor ; Factors *= <NUM_LIT> ) { VT = getDoubleWidthHalfCountVectorVT ( DAG , VT ) ; for ( unsigned i = Factors ; i > <NUM_LIT> ; -- i ) { Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op0 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtLoOpc , DL , VT , Op0 [ i - <NUM_LIT> ] ) ; Op1 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtHiOpc , DL , VT , Op1 [ i - <NUM_LIT> ] ) ; Op1 [ <NUM_LIT> * i - <NUM_LIT> ] = DAG . getNode ( ExtLoOpc , DL , VT , Op1 [ i - <NUM_LIT> ] ) ; } } for ( unsigned i = <NUM_LIT> ; i < Factors ; ++ i ) Res [ i ] = DAG . getNode ( Op . getOpcode ( ) , DL , VT , Op0 [ i ] , Op1 [ i ] ) ; for ( ; Factors > <NUM_LIT> ; Factors /= <NUM_LIT> ) { VT = getHalfWidthDoubleCountVectorVT ( DAG , VT


<s> initialize<ISA_LIT>LongBranchPass ( * PassRegistry :: getPassRegistry (


<s> if ( NewBB == CurBB ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; appendAndTransferDominatedUses ( NewPt , User , OpNo , IPI , InsertPts ) ; return true ; } BasicBlock * CommonDominator = DT . findNearestCommonDominator ( NewBB , CurBB ) ; if ( ! CommonDominator ) continue ; if ( CommonDominator != NewBB ) { assert ( CommonDominator != CurBB && <STR_LIT> ) ; NewPt = CommonDominator -> getTerminator ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI -> first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; DEBUG ( NewPt -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; appendAndTransferDominatedUses ( NewPt , User , OpNo ,


<s> case <STR_LIT> : if ( AllOnes ) return false ; case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; Invert = ! AllOnes ; if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> , VT ) ; else if ( N -> getOpcode ( ) == <STR_LIT> ) OtherOp = DAG . getConstant ( <NUM_LIT> , VT ) ; else OtherOp = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) ,


<s> unsigned <ISA_LIT>FrameLowering :: getEffectiveStackCacheSize ( ) const { return EnableBlockAlignedStackCache ? STC . getStackCacheSize ( ) - STC . getStackCacheBlockSize ( ) : STC . getStackCacheSize


<s> return new <ISA_LIT>OptimizeExecMaskingPreRA (


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return __builtin_aarch64_qtbx4v16qi ( r , __o , ( int8x16_t )


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps -


<s> PM . add ( createBasicTargetTransformInfoPass ( getTargetLowering ( ) ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass (


<s> if ( TT . isOSBinFormatMachO ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> )


<s> static const int MaskToOptimizeEven [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; static const int MaskToOptimizeOdd [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; bool MatchEvenMask = true ; bool MatchOddMask = true ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeEven [ i ] ) ) MatchEvenMask = false ; if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeOdd [ i ] )


<s> MachineMemOperand * MO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addConstantPoolIndex ( CPI ) . addMemOperand ( MO ) ; GlobalBaseReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( <STR_LIT> ) ; CFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return


<s> addr = plus_constant ( Pmode , stack_pointer_rtx , frame_bias + base_ofs ) ; mem = gen_rtx_MEM ( DImode , addr ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode ,


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; int gr_saved , vr_saved ; local_cum = * cum ; aarch64_function_arg_advance ( pack_cumulative_args ( & local_cum ) , mode , type , true ) ; gr_saved = NUM_ARG_REGS - local_cum . aapcs_ncrn ; vr_saved = NUM_FP_ARG_REGS - local_cum . aapcs_nvrn ; if ( ! TARGET_FLOAT ) { gcc_assert ( local_cum . aapcs_nvrn == <NUM_LIT> ) ; vr_saved = <NUM_LIT> ; } if ( ! no_rtl ) { if ( gr_saved > <NUM_LIT> ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > <NUM_LIT> ) { machine_mode mode = TImode ; int off , i ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) { PM . add ( create<ISA_LIT>AsmPrinterPass ( Out , * this


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T ,

const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) {


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> unsigned Imm ; switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 || MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 && <STR_LIT> ( Imm ) < <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'z' : case 'D' : case 'W' : case 'e' : case 'b' : case 'v' : case 'f' : case 'c' : case 't' : case 'u' : case 'k' : case 'x' : case 'y' : case 'w' : return CW_Register ; case 'A' : case 'B' : case 'C' : case 'Z' : case 'Y' : return CW_SpecificReg


<s> } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ; } else { unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; <ISA_LIT>AddressMode StubAM ; StubAM . Base . Reg = AM . Base . Reg ; StubAM . GV = GV ; StubAM . GVOpFlags = GVFlags ; SavePoint SaveInsertPt = enterLocalValueArea ( ) ; if ( TLI . getPointerTy ( DL ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; if ( Subtarget -> isPICStyleRIPRel ( ) ) StubAM . Base . Reg = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = nullptr ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg


<s> if ( getCodeModel ( ) != CodeModel :: Default


<s> PacketNum = <NUM_LIT> ; UsesDotCur = nullptr ; DotCurPNum = - <NUM_LIT> ; RegDefs . clear


<s> bool hasVFP3Base ( ) const { return hasVFPv3D16SP ( )


<s> static bool classof ( const DiagnosticInfo * DI ) { return DI -> getKind ( ) == getKindID (


<s> unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; MachineInstrBuilder CallseqStart = BuildMI ( MF , DL , TII . get ( AdjStackDown ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insert ( MachineBasicBlock :: iterator ( MI ) , CallseqStart ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MachineInstrBuilder CallseqEnd = BuildMI ( MF , DL , TII . get ( AdjStackUp ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BB -> insertAfter ( MachineBasicBlock :: iterator ( MI ) , CallseqEnd ) ; return BB


<s> if ( TARGET_ES0 && GET_CODE ( operands [ <NUM_LIT> ] ) == SYMBOL_REF && TREE_CODE ( SYMBOL_REF_DECL ( operands [ <NUM_LIT> ] ) ) == VAR_DECL && TREE_READONLY ( SYMBOL_REF_DECL ( operands [ <NUM_LIT> ] ) ) && ! TREE_SIDE_EFFECTS ( SYMBOL_REF_DECL ( operands [ <NUM_LIT> ] ) ) ) return <STR_LIT> ; switch ( alternative ) { case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> return ( intptr_t ) ( MR -> getResultPointer ( ) ) ; case <STR_LIT> : return ( intptr_t ) ( MR -> getResultPointer ( ) ) - MR -> getConstantVal ( ) ; case <STR_LIT> : return getJumpTableBaseAddr ( MR -> getJumpTableIndex ( ) ) ; case <STR_LIT> : case <STR_LIT> : return getConstantPoolEntryAddr ( MR -> getConstantPoolIndex ( ) ) ; case <STR_LIT>


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LoopPreIncPrepPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None )

addPass ( createHardwareLoopsPass ( ) ) ;


<s> int64_t <ISA_LIT>mm = static_cast < int64_t > ( Imm ) ; if ( <ISA_LIT>mm >= - <NUM_LIT> && <ISA_LIT>mm <= <NUM_LIT> ) { O << <ISA_LIT>mm ; return ; } if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else { assert ( isUInt < <NUM_LIT> > (


<s> static bool isInt5 ( Value & V ) { if ( auto * VTy = dyn_cast < VectorType > ( V . getType ( ) ) ) return VTy -> getVectorNumElements ( ) == <NUM_LIT> && VTy -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ; return false


<s> if ( isAllOnes ( Mask ) ) return Op ; if ( MaskVT . bitsGT ( Mask . getValueType ( ) ) ) { EVT newMaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , MaskVT . getSizeInBits ( ) ) ; VMask = DAG . getBitcast ( MaskVT , DAG . getNode ( <STR_LIT> , dl , newMaskVT , Mask ) ) ; } else { EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT>


<s> if ( ! satisfies_constraint_j00 ( op ) && ! satisfies_constraint_jm1 ( op ) && ! satisfies_constraint_jKK ( op ) && ! satisfies_constraint_jxx ( op ) && ! satisfies_constraint_jyy ( op ) ) return <NUM_LIT> ; } if ( ! SYMBOLIC_CONST ( op ) ) return <NUM_LIT> ; if ( larl_operand ( op , mode ) ) return <NUM_LIT> ; if ( TLS_SYMBOLIC_CONST ( op ) ) return <NUM_LIT> ; if ( flag_pic ) return <NUM_LIT> ; return


<s> const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( N , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , Ty , DAG , Has<ISA_LIT>64 ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , Ty , DAG , <STR_LIT> , <STR_LIT>

, DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( ) ) ;


<s> } } } unsigned RsrcReg ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: EVERGREEN ) { switch ( MF . getFunction ( ) -> getCallingConv ( ) ) { default : case CallingConv :: <ISA_LIT>_CS : RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS ; break ; case CallingConv :: <ISA_LIT>_GS : RsrcReg = R_028878_SQ_PGM_RESOURCES_GS ; break ; case CallingConv :: <ISA_LIT>_PS : RsrcReg = R_028844_SQ_PGM_RESOURCES_PS ; break ; case CallingConv :: <ISA_LIT>_VS : RsrcReg = R_028860_SQ_PGM_RESOURCES_VS ; break ; } } else { switch ( MF . getFunction ( ) -> getCallingConv ( ) ) { default : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_VS : RsrcReg = R_028868_SQ_PGM_RESOURCES_VS ; break ; case CallingConv :: <ISA_LIT>_PS : RsrcReg = R_028850_SQ_PGM_RESOURCES_PS ; break ; } } OutStreamer -> EmitIntValue ( RsrcReg , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_NUM_GPRS ( MaxGPR + <NUM_LIT> ) | S_STACK_<ISA_LIT>ZE ( MFI -> StackSize ) , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( R_02880C_DB_SHADER_CONTROL , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_02880C_KILL_ENABLE ( killPixel ) , <NUM_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) -> getCallingConv ( ) ) ) { OutStreamer -> EmitIntValue ( R_0288E8_SQ_LDS_ALLOC , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( alignTo ( MFI -> LDSSize , <NUM_LIT> ) >>


<s> return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getRegister ( <STR_LIT> , Ty ) , DAG .

getNode ( <STR_LIT> , DL , DAG . getVTList ( Ty ) , GPRel ) ) ;


<s> decl += <STR_LIT> ; if ( ST . is64Bit ( ) ) decl += <STR_LIT> ; else decl += <STR_LIT> ; decl += <STR_LIT> ; if ( ST . is64Bit ( ) ) decl += <STR_LIT> ; else decl += <STR_LIT> ; decl += <STR_LIT>


<s> case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : case <STR_LIT> :: ARMV8_7A : case <STR_LIT> :: ARMV8R : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; } } else if ( NoCrypto ) { switch ( ArchKind ) { default : case <STR_LIT> :: ARMV8_1A : case <STR_LIT> :: ARMV8_2A : case <STR_LIT> :: ARMV8_3A : RequestedExtensions . push_back ( <STR_LIT> ) ; RequestedExtensions . push_back ( <STR_LIT> ) ; break ; case <STR_LIT> :: ARMV8_4A : case <STR_LIT> :: ARMV8_5A : case <STR_LIT> :: ARMV8_6A : case <STR_LIT> :: ARMV8_7A


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned


<s> std :: string * Str = new std :: string ( S ) ; Pool . push_back


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_2 ; else EFlags |= ELF :: EF_MIPS_ARCH_1 ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_MACH_OCTEON ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_NAN2008 ; MCA . setELFHeaderEFlags


<s> { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Register = RegisterTableVPU [ RegNo ] ; if ( Register == ~ <NUM_LIT> ) return MCDisassembler :: Fail ; auto Ptr = VRF2DRF . find ( Register ) ; if ( Ptr == VRF2DRF . end (


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const Target & , TargetMachine & TM , MCContext


<s> StringRef Name = getIndexedValueName ( BaseName ) ; Instruction * Res = dyn_cast < Instruction > ( IRB -> CreateSub ( Op0 , Op1 , Name ) ) ; Res -> setDebugLoc ( N -> getDebugLoc ( ) ) ; VisitMap [ N ] = Res ; return


<s> static void report_out_of_range ( location_t location , tree fndecl , unsigned int argno , HOST_WIDE_INT actual ,

HOST_WIDE_INT min , HOST_WIDE_INT max ) {


<s> std :: string Str ; raw_string_ostream OS ( Str ) ; OS << Msg ; Val -> print ( OS ) ; OS . flush (


<s> TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed =


<s> for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) , EE = MBB -> end ( ) ; MBBI != EE ; ++ MBBI ) BlockSize += TII -> GetInstSizeInBytes ( MBBI ) ; BlockSizes [ MBB -> getNumber ( ) ] = BlockSize ; FuncSize += BlockSize ; } if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * Dest = nullptr ; if ( I -> getOpcode ( ) == <STR_LIT> && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! Dest ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT>


<s> } else { if ( regno_base == SP_REGNUM ) sprintf ( pattern , <STR_LIT> , conditional ) ; if ( update ) sprintf ( pattern , <STR_LIT> , conditional ) ; else sprintf ( pattern , <STR_LIT> , conditional ) ; strcat ( pattern , reg_names [ regno_base ] ) ; if ( update ) strcat ( pattern , <STR_LIT> ) ; else strcat ( pattern , <STR_LIT> ) ; } strcat ( pattern , reg_names [ REGNO ( XEXP ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , offset ) , <NUM_LIT> ) ) ] ) ; for ( i = offset + <NUM_LIT> ; i < num_saves ; i ++ ) { strcat ( pattern , <STR_LIT> ) ; strcat ( pattern , reg_names [ REGNO ( XEXP ( XVECEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> , i ) , <NUM_LIT> ) ) ] ) ; } strcat ( pattern , <STR_LIT> ) ; if ( IS_INTERRUPT ( arm_current_func_type ( ) ) && return_pc ) strcat ( pattern , <STR_LIT> ) ; output_asm_insn ( pattern , & cond


<s> void printS32ImmOperand ( const MachineInstr * MI , int OpNum ) { O << ( int32_t ) MI -> getOperand ( OpNum ) . getImm


<s> gcc_assert ( nreg <= <NUM_LIT> ) ; if ( named && * cum + nreg <= <NUM_LIT> ) return gen_rtx_REG (


<s> return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( <NUM_LIT> , <NUM_LIT> ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; else Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> SmallVector < unsigned , <NUM_LIT> > Regs ; int LRIdx = <NUM_LIT> ; Optional < int > FpOffset ; for ( auto & MO : MI . operands ( ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) == <STR_LIT> ) LRIdx = Regs . size ( ) ; Regs . push_back ( MO . getReg ( ) ) ; } else if ( MO . isImm ( ) ) { FpOffset = MO . getImm ( ) ; } } int Size = ( int ) Regs . size ( ) ; if ( Size == <NUM_LIT> ) return false ; assert ( Size % <NUM_LIT> == <NUM_LIT> ) ; assert ( MI . getOpcode ( ) == <STR_LIT> ) ; if ( FpOffset && shouldUseFrameHelper ( MBB , NextMBBI , Regs , FrameHelperType :: PrologFrame ) ) { emitStore ( MF , MBB , MBBI , * TII , <STR_LIT> , <STR_LIT> , - LRIdx - <NUM_LIT> , true ) ; auto * PrologFrameHelper = getOrCreateFrameHelper ( M , MMI , Regs , FrameHelperType :: PrologFrame , * FpOffset ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( PrologFrameHelper ) . setMIFlag ( MachineInstr :: FrameSetup ) . copyImplicitOps ( MI ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg


<s> const struct ldstwm_operand * op1 = ( const struct ldstwm_operand * ) arg1 ; const struct ldstwm_operand * op2 = ( const struct ldstwm_operand * ) arg2 ; if ( op1 -> bad ) return op2 -> bad ? <NUM_LIT> : <NUM_LIT> ; else if ( op2 -> bad ) return - <NUM_LIT> ; else return op1 -> offset


<s> bool <ISA_LIT>IfConversion :: isPredicatelessPseudoMI ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case TargetOpcode :: KILL : case TargetOpcode :: IMPLICIT_DEF : case <STR_LIT> : return true ; default :


<s> MachineInstr & SecondLastInst = * I ; if ( I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst . getOpcode ( ) == <STR_LIT> && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst . getOperand ( <NUM_LIT> ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst . getOpcode ( ) == <STR_LIT> || SecondLastInst . getOpcode ( ) == <STR_LIT> ) && LastInst . getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( )

) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { O << * Stubs [ i ] . first << <STR_LIT> ; O << * Stubs [ i ] . second << <STR_LIT> ; } } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment (


<s> MI != ME ; ++ MI ) { auto instructionPredicates = getInstructionPredicates ( ) ; os . indent ( indent + <NUM_LIT> ) << <STR_LIT> << & ( * MI ) << <STR_LIT> ; if ( instructionPredicates . count ( & * MI ) ) { os << getInstructionPredicates ( ) . at ( & * MI ) ; } else { os << <STR_LIT> ; } os << <STR_LIT> ; MI -> print ( os , & ( MF -> getTarget ( ) ) , false ) ; printMetaData ( & ( * MI


<s> uint64_t EncVal = Imm ; return ( EncVal << <NUM_LIT> ) | (


<s> if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( create<ISA_LIT>TLSDynamicCallPass (


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo )


<s> assert ( M . getSimpleValueType ( ) . SimpleTy == C . getSimpleValueType (


<s> const std :: vector < std :: pair < int , unsigned >> & Srcs = Swizzle ( IGSrcs [ i ] , Swz [ i ] ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < <NUM_LIT> || Src . first == <NUM_LIT> ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( <STR_LIT> ) ) ) { if ( Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < <NUM_LIT> ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned >


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) . add ( predOps ( <STR_LIT> ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i


<s> return __builtin_mve_vmulltq_poly_m_pv8hi ( __arm_vuninitializedq_u32 ( ) , __a


<s> if ( GET_MODE ( arg ) != mode && register_operand ( arg , VOIDmode ) && GET_MODE_SIZE ( GET_MODE ( arg ) ) == GET_MODE_SIZE ( mode ) ) return simplify_gen_subreg ( mode , arg , GET_MODE ( arg ) , <NUM_LIT> ) ; return


<s> emitInst ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( CLI . Ins , RetCC_<ISA_LIT> , CLI . RetTy , CLI . Symbol ? CLI . Symbol -> getName ( ) . data ( ) : nullptr ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) :


<s> return ( float64x1_t ) { vgetq_lane_f64 (


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg


<s> strcpy ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; if ( write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG ) dbxout_stabd ( N_SLINE , bi -> line_number ) ; if ( flag_pic ) { if ( TARGET_LINK_STACK ) { char name [ <NUM_LIT> ] ; get_ppc476_thunk_name ( name ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; } else { strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; } strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf


<s> rtx t1 , final_insn , sel ; int bmask ; t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case E_V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask = <NUM_LIT>


<s> return isMem ( MemKind , RegKind ) && inRange

( Mem . Disp , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( Num == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ; ) ; Num = handleJumpintoIfImp ( HeadMBB ,


<s> rtx reg ; if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , <NUM_LIT> ) ; if ( mode == BLKmode ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG


<s> static bool inline isField16 ( int64_t I ) { return isInt < <NUM_LIT> > ( I )


<s> int64_t ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op ,


<s> ( out_mode == SImode && out_n == C \ && in_mode == SFmode && in_n == C ) ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## v2sfv2si , false ) \ : ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## v4sfv4si , false ) \ : NULL_TREE ) ) ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## uv2sfv2si , false ) \ : ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## uv4sfv4si , false ) \ : NULL_TREE ) ) CASE_CFN_LROUND : return ( out_unsigned_p ? ARM_FIND_VCVTU_VARIANT ( vcvta ) : ARM_FIND_VCVT_VARIANT ( vcvta ) ) ; CASE_CFN_LCEIL : return ( out_unsigned_p ? ARM_FIND_VCVTU_VARIANT ( vcvtp ) : ARM_FIND_VCVT_VARIANT ( vcvtp ) ) ; CASE_CFN_LFLOOR : return ( out_unsigned_p ? ARM_FIND_VCVTU_VARIANT ( vcvtm ) : ARM_FIND_VCVT_VARIANT ( vcvtm ) ) ; ( out_mode == N ## mode && out_n == C \ && in_mode == N ## mode && in_n == C ) case CFN_BUILT_IN_BSWAP16 : if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , HI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv4hi , false ) ; else if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , HI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv8hi , false ) ; else return NULL_TREE ; case CFN_BUILT_IN_BSWAP32 : if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , SI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv2si , false ) ; else if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , SI ) ) return arm_builtin_decl ( ARM_BUILTIN_NEON_bswapv4si , false ) ; else return NULL_TREE ; case CFN_BUILT_IN_BSWAP64 : if ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> , DI ) ) return arm_builtin_decl

( ARM_BUILTIN_NEON_bswapv2di , false ) ;


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return

<ISA_LIT>MaterializeInt ( C , VT , VT != <STR_LIT> ) ;


<s> if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) )


<s> if ( ZeroVecIdx != UINT32_MAX ) { bool MaskFirst = true ; int ZeroIdx = - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) { unsigned OpNo = unsigned ( Bytes [ I ] ) / <STR_LIT> ; unsigned Byte = unsigned ( Bytes [ I ] ) % <STR_LIT> ; if ( OpNo == ZeroVecIdx && I == <NUM_LIT> ) { ZeroIdx = <NUM_LIT> ; break ; } if ( OpNo != ZeroVecIdx && Byte == <NUM_LIT> ) { ZeroIdx = I + <STR_LIT> ; MaskFirst = false ; break ; } } if ( ZeroIdx != - <NUM_LIT> ) { SDValue IndexNodes [ <STR_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) { if ( Bytes [ I ] >= <NUM_LIT> ) { unsigned OpNo = unsigned ( Bytes [ I ] ) / <STR_LIT> ; unsigned Byte = unsigned ( Bytes [ I ] ) % <STR_LIT> ; if ( OpNo == ZeroVecIdx ) IndexNodes [ I ] = DAG . getConstant ( ZeroIdx , DL , <STR_LIT> ) ; else { unsigned BIdx = MaskFirst ? Byte + <STR_LIT> : Byte ; IndexNodes [ I ] = DAG . getConstant ( BIdx , DL , <STR_LIT> ) ; } } else IndexNodes [ I ] = DAG . getUNDEF ( <STR_LIT> ) ; } SDValue Mask = DAG . getBuildVector ( <STR_LIT> , DL , IndexNodes ) ; SDValue Src = ZeroVecIdx == <NUM_LIT> ? Ops [ <NUM_LIT> ] : Ops [ <NUM_LIT> ] ; if ( MaskFirst ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask ,


<s> patternp = pattern ; encode_pattern_1 ( x


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> std :: string decl = <STR_LIT> ; if ( func -> getName ( ) == <STR_LIT> || func -> getName ( ) == <STR_LIT> ) { decl += <STR_LIT> ; if ( ST . is64Bit ( ) ) decl += <STR_LIT> ; else decl +=


<s> unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_ARCH_ASE_M16 ; MCA . setELFHeaderEFlags ( Flags


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT>


<s> return <STR_LIT> :: getVGPREncodingGranule ( getFeatureBits


<s> unsigned int <ISA_LIT>InstrInfo :: getPredicationCost ( const MachineInstr &


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm (


<s> } SDValue IncV = CurDAG -> getTargetConstant ( Inc , dl , <STR_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand ( ) ; SDValue From [ <NUM_LIT> ] = { SDValue ( ST , <NUM_LIT> ) , SDValue ( ST , <NUM_LIT> ) } ; SDValue To [ <NUM_LIT> ] ; if ( IsValidInc ) { SDValue Ops [ ] = { Base , IncV , Value , Chain } ; MachineSDNode * S = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Ops ) ; S -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( S , <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( S , <NUM_LIT> ) ; } else { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Zero , Value , Chain } ; MachineSDNode * S = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; S -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( S , <NUM_LIT> ) ; MachineSDNode * A = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , IncV ) ; To [ <NUM_LIT> ] = SDValue ( A , <NUM_LIT> ) ; } ReplaceUses ( From , To , <NUM_LIT>


<s> WasmEHFuncInfo * getWasmEHFuncInfo (


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , TM , LowGPR , false ) ; addSavedGPR ( MBB , MIB , TM , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , TM , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , TM , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { MBB . addLiveIn ( Reg ) ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CSI [ I ] . getFrameIdx


<s> return make_unique < <ISA_LIT>DCModule > ( * this , M


<s> assert ( ( Kind == k_Register || Kind == k_CCOut )


<s> if ( vec_flags & VEC_SVE_PRED ) return BYTES_PER_SVE_PRED ; if ( vec_flags & VEC_SVE_DATA ) return BYTES_PER_SVE_VECTOR ; } return


<s> case <STR_LIT> : SRVK = MCSymbolRefExpr :: VK_TLSLD ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MCSymbol * sym = MCInstLowering . GetSymbolFromOperand ( MI . getOperand ( <NUM_LIT> ) ) ; const MCSymbolRefExpr * symRef = MCSymbolRefExpr :: Create ( sym , SRVK , context ) ; MCInst LEA ; if ( is64Bits ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } OutStreamer . EmitInstruction ( LEA ) ; if ( needsPadding ) { OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> )


<s> encodeULEB128 ( uint32_t ( MO . getImm ( ) ) , OS ) ; break ; case <STR_LIT> : encodeSLEB128 ( int64_t ( MO . getImm ( ) ) , OS ) ; break ; case <STR_LIT> : OS << uint8_t ( MO . getImm ( ) ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint8_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint16_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint32_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint64_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else { encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else if ( MO . isFPImm ( ) ) { const MCOperandInfo & Info = Desc . OpInfo [ I ] ; if ( Info . OperandType == <STR_LIT> ) { auto F = float ( MO . getFPImm ( ) ) ; <STR_LIT> :: write < float > ( OS , F , <STR_LIT> ) ; } else { assert ( Info . OperandType == <STR_LIT> ) ; double D = MO . getFPImm ( ) ; <STR_LIT> :: write < double > ( OS , D , <STR_LIT> ) ; } } else if ( MO . isExpr ( ) ) { const MCOperandInfo & Info = Desc . OpInfo [ I ] ; llvm :: MCFixupKind FixupKind ; size_t PaddedSize = <NUM_LIT> ; switch ( Info . OperandType ) { case <STR_LIT> : FixupKind = MCFixupKind ( <STR_LIT> ) ; break ; case <STR_LIT> : FixupKind = MCFixupKind ( <STR_LIT> ) ; PaddedSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FixupKind = MCFixupKind ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Fixups . push_back ( MCFixup :: create ( OS . tell ( ) - Start , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; encodeULEB128 ( <NUM_LIT> , OS , PaddedSize ) ; } else { llvm_unreachable ( <STR_LIT>


<s> void setVisit ( bool val ) { visit =


<s> static CodeModel :: Model getEffective<ISA_LIT>CodeModel ( Optional < CodeModel :: Model > CM , Reloc :: Model RM , bool JIT ) { if ( CM


<s> RHSMaxIdx = NumEltsOut / NumEltsIn + RHSMinIdx ; SToVRHS = getSToVPermuted ( SToVRHS , DAG , Subtarget ) ; if ( SToVRHS . getValueType ( ) != RHS . getValueType ( ) ) SToVRHS = DAG . getBitcast ( RHS . getValueType ( ) , SToVRHS ) ; RHS = SToVRHS ; } fixupShuffleMaskForPermutedSToV ( ShuffV , LHSMaxIdx , RHSMinIdx , RHSMaxIdx , HalfVec , ValidLaneWidth , Subtarget ) ; Res = DAG . getVectorShuffle ( SVN -> getValueType ( <NUM_LIT> ) , dl , LHS , RHS , ShuffV ) ; if ( ! isa < ShuffleVectorSDNode > ( Res ) ) return Res ; Mask = cast < ShuffleVectorSDNode > ( Res ) -> getMask ( ) ; } SDValue TheSplat = IsLittleEndian ? RHS : LHS ; if ( ! isSplatBV ( TheSplat ) ) return Res ; if ( ! isAlternatingShuffMask ( Mask , NumElts ) ) return Res ; if ( IsLittleEndian ) { if ( Mask [ <NUM_LIT> ] < NumElts ) for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT> ) ShuffV [ i ] = ( ShuffV [ i - <NUM_LIT> ] + NumElts ) ; else for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT> ) ShuffV [ i ] = ( ShuffV [ i + <NUM_LIT> ] + NumElts ) ; } else { if ( Mask [ <NUM_LIT> ] < NumElts ) for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT> ) ShuffV [ i ] = ShuffV [ i + <NUM_LIT> ] - NumElts ; else for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i < e ; i += <NUM_LIT> ) ShuffV [ i

] = ShuffV [ i - <NUM_LIT> ] - NumElts ;


<s> if ( op && GET_CODE ( op ) == PLUS && CONST_SCALAR_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) { off = XEXP ( op , <NUM_LIT> ) ; op = XEXP ( op , <NUM_LIT> ) ; } while ( op && GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( op && GET_CODE ( op ) != REG ) return false ; if ( offset ) { if ( off == NULL_RTX ) * offset = <NUM_LIT> ; else if ( CONST_INT_P ( off ) ) * offset = INTVAL ( off ) ; else if ( CONST_WIDE_INT_P ( off ) ) * offset

= CONST_WIDE_INT_ELT ( off , <NUM_LIT> ) ;


<s> return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned CPI = getCombinedIndex ( CPEMI ) ; assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [


<s> RegInterval <ISA_LIT>InsertWaits :: getRegInterval ( MachineOperand & Op ) { if ( ! Op . isReg ( ) ) return std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ; unsigned Reg = Op . getReg ( ) ; unsigned Size = TRI -> getMinimalPhysRegClass ( Reg )


<s> SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; InstInfo -> AsmRewrites -> emplace_back ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ; bool Parse32 = is32BitMode ( ) ||


<s> if ( ! NeedCFI ) return false ; HFI . insertCFIInstructions ( MF ) ; return


<s> bool <STR_LIT> ( int64_t Offset , CodeModel :: Model M , bool hasSymbolicDisplacement ) { if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ; if ( ! hasSymbolicDisplacement ) return true ; if ( M != CodeModel :: Small && M != CodeModel :: Kernel ) return false ; if ( M == CodeModel :: Small && Offset

< <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ) return true ;