<s> if ( ! StartVal ) return std :: make_pair ( nullptr , nullptr ) ; APInt StrideVal ( StartVal -> getValue ( ) . getBitWidth ( ) , <NUM_LIT> ) ; ConstantInt * Prev = StartVal ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { auto * C = dyn_cast_or_null < ConstantInt > ( StartC -> getAggregateElement ( i ) ) ; if ( ! C ) return std :: make_pair ( nullptr , nullptr ) ; APInt LocalStride = C -> getValue ( ) - Prev -> getValue ( ) ; if ( i == <NUM_LIT> ) StrideVal = LocalStride ; else if ( StrideVal != LocalStride ) return std :: make_pair ( nullptr , nullptr ) ; Prev = C ; } Value * Stride = ConstantInt :: get ( StartVal -> getType ( ) , StrideVal ) ; return std :: make_pair (


<s> rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( <NUM_LIT> , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P (


<s> rtx op0 , op1 , target ; mips_emit_compare ( & code , & op0 , & op1 , TARGET_MIPS16 ) ; target = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 ,

op1 ) , gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) , pc_rtx ) ;


<s> if ( ! ResTy . is128BitVector ( ) ) return SDValue ( ) ; int ResTyNumElts = ResTy . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Indices ; for ( int i = <NUM_LIT> ; i < ResTyNumElts ; ++ i ) Indices . push_back ( Node -> getMaskElt ( i ) ) ; if ( isVECTOR_SHUFFLE_SPLATI ( Op , ResTy , Indices , DAG ) ) return lowerVECTOR_SHUFFLE_VSHF ( Op , ResTy , Indices , DAG ) ; SDValue Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVEV ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVOD ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVL ( Op , ResTy , Indices , DAG ) ) )


<s> void <ISA_LIT>InstPrinter :: printNEONModImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned EncodedImm = MI -> getOperand ( OpNum ) . getImm ( ) ; unsigned EltBits


<s> if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) { if ( OpVT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , OpVT ) ; return getOnesVector ( OpVT , DAG , SDLoc ( N ) ) ; } if ( InVec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( OpVT , SDLoc ( N ) , InVec . getNode ( ) -> ops ( ) . slice ( IdxVal , OpVT . getVectorNumElements ( ) ) ) ; return SDValue (


<s> FunctionPass * llvm :: create<ISA_LIT>CallFrameOptimization ( ) { return new <ISA_LIT>CallFrameOptimization (


<s> return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT> ,


<s> bool <ISA_LIT>InstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const { return false


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . getRelocationModel ( ) == Reloc ::


<s> assert ( std :: is_sorted ( std :: begin ( IntrinsicsWithoutChain ) , std :: end ( IntrinsicsWithoutChain ) ) && std :: is_sorted ( std :: begin ( IntrinsicsWithChain

) , std :: end ( IntrinsicsWithChain ) ) && <STR_LIT> ) ;


<s> unsigned getExpcntBitMask ( IsaVersion Version


<s> StringRef getPassName ( ) const override { return


<s> disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID


<s> SCANode * getRoot ( ) const { return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned Encoded = A64InvertCondCode ( getCondCode ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm


<s> Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = <STR_LIT> ; Op -> Mem . Off =


<s> Op = ( Part == OpRef :: HiHalf ) ? Op . getOperand ( <NUM_LIT> ) : Op . getOperand ( <NUM_LIT> ) ; } else { MVT HalfTy = <STR_LIT> ( OpTy . getVectorElementType ( ) , OpTy . getVectorNumElements ( ) / <NUM_LIT> ) ; unsigned Sub = ( Part == OpRef :: LoHalf ) ? <STR_LIT> : <STR_LIT> ; Op = DAG . getTargetExtractSubreg ( Sub , dl , HalfTy , Op ) ; } } Ops . push_back ( Op ) ; } assert ( Node . Ty != <STR_LIT> ) ; SDNode * ResN = ( Node . Opc == TargetOpcode :: COPY ) ? Ops . front ( ) . getNode ( ) : DAG . getMachineNode ( Node . Opc , dl , Node . Ty , Ops ) ; Output . push_back ( SDValue ( ResN , <NUM_LIT> ) ) ; } SDNode * OutN = Output . back ( ) . getNode ( ) ; SDNode * InpN = Results . InpNode ; DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << <STR_LIT> ; OutN -> dumpr ( & DAG ) ; } ) ; ISel . ReplaceNode ( InpN , OutN ) ; selectVectorConstants ( OutN


<s> if ( regclass == STACK_REG ) { if ( REG_P ( x ) && reg_class_subset_p ( REGNO_REG_CLASS ( REGNO ( x ) ) , POINTER_REGS ) ) return regclass ; return NO_REGS ; } if ( ! reg_class_subset_p ( regclass , GENERAL_REGS ) && GET_CODE ( x ) == PLUS ) { rtx lhs = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( lhs ) == SUBREG ) lhs = SUBREG_REG ( lhs ) ; gcc_assert ( REG_P ( lhs


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWindowsUnwindTables ( WinEH :: FrameInfo


<s> } LoadSDNode * LD = cast < LoadSDNode > ( N ) ; unsigned Align = LD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand


<s> int regsize = mep_reg_size ( i ) ; if ( ( i != TP_REGNO && i != GP_REGNO && i != LP_REGNO ) || mep_reg_set_in_function ( i ) ) really_need_stack_frame = true ; if ( cfun -> machine -> reg_save_slot [ i ] ) continue ; if ( regsize < <NUM_LIT> ) { cfun -> machine -> reg_save_size +=


<s> MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; for ( MachineBasicBlock :: succ_iterator SI = BB -> succ_begin ( ) , SE = BB -> succ_end ( ) ; SI != SE ; ++ SI ) EM -> insert ( std :: make_pair ( * SI , copy1MBB ) ) ; copy1MBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB )


<s> val = INTVAL ( first ) ; first_byte = val & <NUM_LIT> ; for ( i = <NUM_LIT> ; i < bytes ; i ++ ) { val >>= <NUM_LIT> ; if ( ( val & <NUM_LIT> ) != first_byte ) return false ; } return


<s> const NodeSet * node_class ( GepNode * N , NodeSymRel & Rel ) { for ( NodeSymRel :: iterator I = Rel . begin ( ) , E = Rel . end ( ) ; I != E ;

++ I ) if ( I -> count ( N ) ) return & * I ;


<s> static unsigned getBitExtrOpcode ( MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> unsigned Reg , RegNum , RegWidth ; if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth ) ) { return nullptr ; } if ( isHsaAbiVersion3 ( & getSTI ( ) ) ) { if ( ! updateGprCountSymbols ( RegKind , RegNum , RegWidth ) ) return nullptr ; } else KernelScope . usesRegister ( RegKind , RegNum , RegWidth ) ; return <ISA_LIT>Operand :: CreateReg ( this ,


<s> else alloc_offset = MIN ( seh -> cfa_offset + <NUM_LIT> , seh -> sp_offset ) ; offset = alloc_offset - INCOMING_FRAME_SP_OFFSET ; if ( offset > <NUM_LIT> ) fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; for ( int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( seh -> reg_offset [ regno ] > <NUM_LIT> && seh -> reg_offset [ regno ] <= alloc_offset ) { if ( SSE_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else if ( GENERAL_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else gcc_unreachable ( ) ; print_reg ( gen_rtx_REG ( DImode , regno ) , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , alloc_offset - seh -> reg_offset [ regno ] ) ; } if ( seh -> cfa_reg != stack_pointer_rtx ) { offset = alloc_offset - seh -> cfa_offset ; gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; gcc_assert ( IN_RANGE ( offset , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , f ) ; print_reg ( seh -> cfa_reg , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; } if ( alloc_offset != seh -> sp_offset ) { offset = seh -> sp_offset - alloc_offset ; if ( offset > <NUM_LIT> && offset < SEH_MAX_FRAME_SIZE ) fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; for ( int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( seh -> reg_offset [ regno ] > alloc_offset ) { if ( SSE_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else if ( GENERAL_REGNO_P ( regno ) ) fputs ( <STR_LIT> , f ) ; else gcc_unreachable ( ) ; print_reg ( gen_rtx_REG ( DImode , regno ) , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , seh -> sp_offset - seh -> reg_offset [ regno ] ) ; } } fputs ( <STR_LIT> , f


<s> Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : ThumbBit = <NUM_LIT> ; break ; } if ( Type == MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ) { uint32_t OtherHalf = MovtBit ? ( FixedValue & <NUM_LIT> ) : ( ( FixedValue & <NUM_LIT> ) >> <NUM_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( OtherHalf << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( MovtBit << <NUM_LIT> ) | ( ThumbBit << <NUM_LIT> ) | ( IsPCRel <<


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDForm2Addr ( SDValue Op , SDValue N , SDValue


<s> case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CombineBaseUpdate ( N


<s> uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getDispOpValue ( MI , OpNum + <NUM_LIT> , Fixups ,


<s> MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , flags , MFI .

getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ;


<s> SDValue rd = DAG . getNode ( <STR_LIT> , dl , Tys , & TheChain , <NUM_LIT> ) ; SDValue rax = DAG . getCopyFromReg ( rd , dl , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; SDValue rdx = DAG . getCopyFromReg ( rax . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , rax . getValue ( <NUM_LIT> ) ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rax ,

Tmp ) , rdx . getValue ( <NUM_LIT> ) } ;


<s> if ( GET_CODE ( x ) == LO_SUM && XEXP ( x , <NUM_LIT>

) == pic_offset_table_rtx ) return true ;


<s> } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg


<s> TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableVectorCombine ) addPass ( create<ISA_LIT>VectorCombineLegacyPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP


<s> unsigned int nelts_per_vq = INTVAL ( cnt_pat [ <NUM_LIT> ] ) ; unsigned int factor = INTVAL ( cnt_pat [ <NUM_LIT> ] ) * nelts_per_vq ; return aarch64_output_sve_cnt_immediate ( prefix , operands , pattern


<s> if ( register_operand ( op , mode ) || memory_operand ( op , mode ) || sh_unspec_insn_p ( op ) ) return false ; if ( ! can_create_pseudo_p ( ) ) return false ; recog_data_d prev_recog_data = recog_data ; rtx_insn * i = make_insn_raw ( gen_rtx_SET ( VOIDmode , get_t_reg_rtx ( ) , op ) ) ; SET_PREV_INSN ( i ) = NULL ; SET_NEXT_INSN ( i ) = NULL ; int result = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; if ( result < <NUM_LIT> && GET_CODE ( op ) == EQ ) { PUT_CODE ( op , NE ) ; result = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; PUT_CODE ( op , EQ ) ; } if ( result < <NUM_LIT> && GET_CODE ( op ) == NE ) { PUT_CODE ( op , EQ ) ; result = recog ( PATTERN ( i ) , i ,


<s> extern __inline __m512i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_maskz_loadu_epi64 ( __mmask8 __U , void const * __P ) { return ( __m512i ) __builtin_ia32_loaddqudi512_mask ( ( const long long * ) __P , ( __v8di ) _mm512_setzero_si512 ( ) ,


<s> static bool aarch64_could_trap_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ; return false


<s> if ( Converted . second ) Converted . first -> second . ShouldConvert = shouldConvertImpl ( & C ) ; return Converted . first -> second .


<s> int cost = <NUM_LIT> ; addrtype = crx_decompose_address ( addr , & address ) ; gcc_assert ( addrtype != CRX_INVALID ) ; if ( addrtype == CRX_ABSOLUTE ) cost += <NUM_LIT> ; if ( addrtype == CRX_POST_INC ) cost -= <NUM_LIT> ; if ( address . base ) cost ++ ; if ( address . index && address . scale == <NUM_LIT> ) cost += <NUM_LIT> ; if ( address . disp && ! INT_CST4 ( INTVAL ( address . disp ) ) ) cost += <NUM_LIT> ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , cost ) ; debug_rtx ( addr


<s> DestReg1 = TRI . getSubReg ( DestReg , SubIdx1 ) ; SubIdx1 = <NUM_LIT> ; IsUndef = false ; } BuildMI ( MBB , InsertBefore , DebugLoc ( ) , MCID ) . addReg ( DestReg0 , RegState :: Define | getUndefRegState ( IsUndef ) , SubIdx0 ) . addReg ( DestReg1 , RegState :: Define | getUndefRegState ( IsUndef ) , SubIdx1 ) . addFrameIndex ( FI ) . addImm


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF ,


<s> if ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 ( STI ) ; } return new <ISA_LIT>AsmInstrumentation (


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , false ,


<s> bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned SP = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( SP , PtrVT ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SaveSP = Op .


, __artificial__ ) ) _mm_undefined_pd ( void ) {


<s> do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE


<s> <ISA_LIT>SchedStrategy ( ) : DAG ( nullptr ) , SchedModel ( nullptr ) , Top ( TopQID , <STR_LIT> ) , Bot

( BotQID , <STR_LIT> ) , lastScheduledSU ( nullptr ) {


<s> if ( ! Offset || ! Offset -> isNullValue ( ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; return Width ? <NUM_LIT> - ( Width -> getZExtValue ( ) & <NUM_LIT> ) : <NUM_LIT> ; } default : return <NUM_LIT>


<s> if ( op == MOVE_BY_PIECES ) return false ; return default_use_by_pieces_infrastructure_p ( size , align


<s> WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , nullptr , - <NUM_LIT> , <NUM_LIT> ) ; CurFrame -> EpilogMap [ CurrentEpilog ] . push_back ( Inst ) ; CurrentEpilog =


<s> int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ) + <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm


<s> SetOfMachineInstr & BBOutSet = getSet ( Out , MBB , CurReg , NbReg ) ; unsigned Size = BBOutSet . size ( ) ; for ( MachineBasicBlock * PredMBB : MBB . predecessors ( ) ) { SetOfMachineInstr & PredOutSet = getSet ( Out , * PredMBB , CurReg , NbReg ) ; BBInSet . insert ( PredOutSet . begin ( ) , PredOutSet . end ( ) ) ; } for ( const MachineInstr * MI : BBInSet ) { SetOfMachineInstr & OpReachedUses = getUses ( ColorOpToReachedUses , CurReg , * MI ) ; OpReachedUses . insert ( BBReachableUses . begin ( ) , BBReachableUses . end ( ) ) ; } if ( ! Kill [ & MBB ] . test ( CurReg ) ) BBOutSet . insert ( BBInSet . begin ( ) , BBInSet . end ( ) ) ; if ( Gen [ & MBB ] [ CurReg ] ) BBOutSet . insert ( Gen [ & MBB


<s> short <ISA_LIT>InstrInfo :: changeAddrMode_io_abs ( short Opc ) const { return Opc >= <NUM_LIT> ? <STR_LIT>


<s> static SDValue combineVectorShiftVar ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( N1 , <NUM_LIT> , UndefElts , EltBits , true , false ) ) { unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( N -> getOpcode ( ) , false


<s> } mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + maskRegNum ) ) ; return


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo (


<s> for ( auto & rec : regRecord ) outs ( ) << rec . fName << <STR_LIT> << rec .

reg << <STR_LIT> << rec . isPointer << <STR_LIT> ;


<s> static bool nios2_symbolic_constant_p ( rtx x ) { rtx base , offset ; if ( flag_pic ) return false ; if ( GET_CODE ( x ) == LABEL_REF ) return true ; else if ( CONSTANT_P ( x ) ) { split_const ( x , & base , & offset ) ; return ( SYMBOL_REF_P ( base ) && ! SYMBOL_REF_TLS_MODEL ( base ) && ! gprel_constant_p ( base ) && ! r0rel_constant_p ( base ) &&


<s> explicit value ( Value * Val , const value_var & v ) { * static_cast < value_var * > ( this ) = v ; llvmVal = Val


<s> iq2000_load_reg = <NUM_LIT> ; iq2000_load_reg2 = <NUM_LIT> ; iq2000_load_reg3 = <NUM_LIT> ; iq2000_load_reg4 = <NUM_LIT> ; return ret ; } set_reg = operands [ <NUM_LIT> ] ; if ( set_reg == <NUM_LIT> ) return ret ; while ( GET_CODE ( set_reg ) == SUBREG ) set_reg = SUBREG_REG ( set_reg ) ; mode = GET_MODE ( set_reg ) ; dslots_number_nops = num_nops ; iq2000_load_reg = set_reg ; if ( GET_MODE_SIZE ( mode ) > ( unsigned ) ( UNITS_PER_WORD ) ) iq2000_load_reg2 = gen_rtx_REG ( SImode , REGNO ( set_reg


<s> static SDValue prepareTS1AM ( SDValue Op , SelectionDAG & DAG , SDValue & Flag , SDValue & Bits ) { SDLoc DL ( Op ) ; AtomicSDNode * N = cast < AtomicSDNode > ( Op ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = Ptr .


<s> unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT>


<s> assert ( Register :: isPhysicalRegister ( RS . Reg ) ) ; PhysR = RS . Reg ; } Register PhysS = ( RS . Sub == <NUM_LIT> ) ? PhysR : TRI -> getSubReg ( PhysR , RS . Sub ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( PhysS ) ; switch ( TRI -> getRegSizeInBits ( * RC ) ) { case <NUM_LIT> : return IfTrue ? A2_tfrt : A2_tfrf ; case <NUM_LIT> : return IfTrue ? A2_tfrpt : A2_tfrpf ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( SO . getType


<s> static inline long long load_half ( void * skb __attribute__ ( ( unused


<s> if ( ! ST . hasLOB ( ) ) return false ; MF = & mf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF -> getName ( ) << <STR_LIT> ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; RDA = & getAnalysis < ReachingDefAnalysis > ( ) ; MF -> getProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ; MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( ST . getInstrInfo ( ) ) ; BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( * MF ) ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF -> front ( ) ) ; bool Changed = false ; for ( auto ML : * MLI ) { if ( ! ML -> getParentLoop ( ) ) Changed |= ProcessLoop


<s> return getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS && getGeneration ( )


<s> } assert ( Adj != ~ <NUM_LIT> && <STR_LIT> ) ; for ( const auto Pred : BB -> predecessors ( ) ) { if ( OutgoingAdjustments . count ( Pred ) ) assert ( OutgoingAdjustments [ Pred ] == Adj


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( Reg1IsKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill (


<s> if ( ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> ) return SDValue ( ) ; for ( <STR_LIT> Op : { <STR_LIT> , <STR_LIT> } ) { SDValue Match = matchBinOpReduction ( Extract , Op ) ; if ( ! Match ) continue ; if ( Match . getScalarValueSizeInBits ( ) != BitWidth ) continue ; unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && ( ( Subtarget . hasAVX ( ) && BitWidth >= <NUM_LIT> ) || Subtarget . hasAVX2 ( ) ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; MVT MaskVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; APInt CompareBits ; <STR_LIT> CondCode ; if ( Op == <STR_LIT> ) { CompareBits = APInt :: getNullValue ( <NUM_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CompareBits = APInt :: getLowBitsSet ( <NUM_LIT> , MaskVT . getVectorNumElements ( ) ) ; CondCode = <STR_LIT> :: SETEQ ; } unsigned ResWidth = std :: max ( BitWidth , <NUM_LIT> ) ; EVT ResVT = EVT :: getIntegerVT ( * DAG . getContext


<s> if ( ! StatsFile . empty ( ) && ! AppendStatsFile && sys :: fs :: exists ( StatsFile ) ) { sys :: fs :: remove ( StatsFile . c_str (


<s> return gen_nvptx_barsync ( lock , GEN_INT ( threads


<s> O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT> ) ; printExpr ( Op . getExpr ( ) , O


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this


<s> df_ref def , use ; if ( ! prev || ! next ) return distance + ( distance & <NUM_LIT> ) + <NUM_LIT> ; if ( ! DF_INSN_USES ( next ) || ! DF_INSN_DEFS ( prev ) ) return distance + <NUM_LIT> ; FOR_EACH_INSN_USE ( use , next ) FOR_EACH_INSN_DEF ( def , prev ) if ( ! DF_REF_IS_ARTIFICIAL ( def ) && DF_REF_REGNO ( use ) == DF_REF_REGNO ( def ) ) return distance + ( distance & <NUM_LIT> ) + <NUM_LIT> ; return distance +


<s> memset ( Outputs , <NUM_LIT> , sizeof ( Outputs


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <=

<NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> return StackOffset :: getFixed ( MFI . getObjectOffset ( FI

) - getOffsetOfLocalArea ( ) + Adjustment ) ;


<s> return getNamedOperand ( MI , OpName


<s> bool hasSlowLoadDSubregister ( ) const { return


<s> return ( __a + ( __b * __aarch64_vget_lane_any (


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isCPI ( ) ) return true ; if ( MO . isGlobal ( ) ) return isGVStub ( MO . getGlobal ( ) , TM ) ; if ( MO . isFI ( ) ) { const MachineFrameInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; int Idx = MO . getIndex


<s> Inst . addOperand ( MCOperand :: createImm ( JumpOffset ) ) ; return MCDisassembler


<s> CommentStream = & cs ; uint8_t bytes [ <NUM_LIT> ] ; Size = <NUM_LIT> ; if ( Region . readBytes ( Address , <NUM_LIT> , ( uint8_t * ) bytes ) == - <NUM_LIT> ) return Fail ; Size = <NUM_LIT>


<s> void setRegKind ( RegisterKind RegKind ) { assert ( ( Kind == k_Register || Kind == k_PtrReg ) && <STR_LIT> ) ; Reg . Kind =


<s> return ( __m128 ) __builtin_ia32_vextractf128_ps256 ( ( __v8sf


<s> void <ISA_LIT>InstPrinter :: printMemOperandEA ( const MCInst * MI , int


<s> static bool isU24 ( SDValue Op , SelectionDAG & DAG ) { APInt KnownZero , KnownOne ; EVT VT = Op . getValueType ( ) ; DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; return ( VT . getSizeInBits ( ) - KnownZero . countLeadingOnes


<s> return ( vector unsigned int ) __builtin_altivec_vslw ( ( vector signed int ) a1 , ( vector signed int )


<s> const AMDGPUSubtarget & STM = MF . getSubtarget < AMDGPUSubtarget > ( ) ; const R600RegisterInfo * RI = static_cast < const R600RegisterInfo * > ( STM . getRegisterInfo ( ) ) ; const R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == AMDGPU :: KILLGT ) killPixel = true ; unsigned numOperands = MI . getNumOperands ( ) ; for ( unsigned op_idx = <NUM_LIT> ; op_idx < numOperands ; op_idx ++ ) { const MachineOperand & MO = MI . getOperand ( op_idx ) ; if ( ! MO . isReg ( ) ) continue ; unsigned HWReg = RI -> getEncodingValue ( MO . getReg ( ) )


<s> SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( ) , false , true , true , <NUM_LIT> ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack (


<s> gcc_assert ( DECL_P ( * node ) ) ; if ( TREE_CODE ( * node


<s> if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count ; } return


<s> SDLoc dl ( GA ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult .


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc =


<s> Target & getThe<ISA_LIT>leTarget ( ) { static Target


<s> if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( Expr ) ) { int16_t Val ; switch ( getVariantKind ( RelocStr ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : Val = MCE -> getValue ( ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : report_fatal_error ( <STR_LIT>


<s> break ; } } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; int Scale = RPI . Type == RegPairInfo :: FPR128 ? <NUM_LIT> : <NUM_LIT> ; Offset -= RPI . isPaired ( ) ? <NUM_LIT> * Scale : Scale ; if ( AFI -> hasCalleeSaveStackFreeSpace ( ) && RPI . Type != RegPairInfo :: FPR128 && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( Offset %


<s> const <ISA_LIT>InstrRelaxTableEntry * llvm :: lookupShortTable ( unsigned RelaxOp ) { auto & Table = ShortTable -> Table ; auto I = llvm :: lower_bound ( Table , RelaxOp ) ; if ( I != Table . end ( ) && I -> KeyOp == RelaxOp ) return & * I ; return nullptr


<s> State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( HST . useHVX64BOps ( ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstD ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( HST . useHVX128BOps ( ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstD ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT ,


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return


<s> SDValue Bytes = DAG . getLoad ( ByteTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; SDValue Sel = DAG . getSelect ( dl , VecTy , VecQ , DAG . getBitcast ( VecTy , Bytes ) , getZero ( dl , VecTy , DAG ) ) ; SDValue All1 = DAG . getSplatBuildVector ( <STR_LIT> , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Vrmpy = getInstr ( <STR_LIT> , dl , ByteTy , { Sel , All1 } , DAG ) ; SDValue Rot = getInstr ( <STR_LIT> , dl , ByteTy , { Vrmpy , Vrmpy , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue Vor = DAG . getNode ( <STR_LIT> , dl , ByteTy , { Vrmpy , Rot } ) ; SmallVector < int ,


<s> assignFIsToStackCache ( MF , SCFIs ) ; } unsigned int SCOffset = <NUM_LIT> ; unsigned int SSOffset = ( hasFP ( MF ) ? <NUM_LIT> : maxFrameSize ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getFunction ( ) . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MFI . print ( MF , dbgs ( ) ) ) ; for ( unsigned FI = <NUM_LIT> , FIe = MFI . getObjectIndexEnd ( ) ; FI != FIe ; FI ++ ) { if ( MFI . isDeadObjectIndex ( FI ) ) continue ; unsigned FIalignment = MFI . getObjectAlignment ( FI ) ; int64_t FIsize = MFI . getObjectSize ( FI ) ; if ( FIsize > INT_MAX ) { report_fatal_error ( <STR_LIT> ) ; } assert ( ! MFI . isFixedObjectIndex ( FI ) && ! MFI . isObjectPreAllocated ( FI ) ) ; if ( SCFIs [ FI ] ) { unsigned int next_SCOffset = align ( SCOffset , FIalignment ) ; if ( align ( next_SCOffset + FIsize , getEffectiveStackCacheBlockSize ( ) ) <= getEffectiveStackCacheSize ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << next_SCOffset << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; MFI . setObjectOffset ( FI , next_SCOffset ) ; SCOffset = next_SCOffset + FIsize ; continue ; } else { SCFIs [ FI ] = false ; FIsNotFitSC ++ ; } } { assert ( ! SCFIs [ FI ] ) ; SSOffset = align ( SSOffset , FIalignment ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << SSOffset << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; MFI . setObjectOffset ( FI , SSOffset ) ; SSOffset += FIsize


<s> return ggc_alloc_cleared_machine_function ( )


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> i = strlen ( cstr ) ; str = ( char * ) alloca ( i + <NUM_LIT> ) ; memcpy ( str , cstr , i + <NUM_LIT> ) ; blink = - <NUM_LIT> ; lpcount = - <NUM_LIT> ; dash = strchr ( str , '-' ) ; if ( ! dash ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> ) ; return ; } * dash = '\0' ; comma = strchr ( dash + <NUM_LIT> , ',' ) ; if ( comma ) * comma = '\0' ; first = decode_reg_name ( str ) ; if ( first != <NUM_LIT> ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> ) ; return ; } if ( ! strcmp ( dash + <NUM_LIT> , <STR_LIT> ) ) last = <NUM_LIT> ; else last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } if ( ! ( last & <NUM_LIT> ) ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( OPT_mirq_ctrl_saved_ , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } while ( comma ) { * comma = ',' ; str = comma + <NUM_LIT> ; comma = strchr ( str , ',' ) ; if ( comma ) * comma = '\0' ; xreg = decode_reg_name ( str ) ; switch ( xreg ) { case <NUM_LIT> : blink = <NUM_LIT> ; break ; case


<s> return isRepeatedShuffleMask ( <NUM_LIT> , VT , Mask


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return &


<s> static DecodeStatus decodeU4ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address ,


<s> assert ( MemOpcodes && <STR_LIT> ) ; return MemOpcodes [ Form231


<s> unsigned int i ; unsigned int count = ( high - low ) + <NUM_LIT> ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , (

count - <NUM_LIT> ) * UNITS_PER_WORD ) ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_VectorIndex , Ctx ) ; Op -> VectorIndex . Val = Idx ; Op -> StartLoc =


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) ) return false ; if ( Imm . isNegZero ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> void setPriority ( PriorityFunction p ) { PF = p


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X )


<s> if ( dwarf_index == <NUM_LIT> ) insn = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset + <NUM_LIT> ) ) ; tmp = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , j + <NUM_LIT> ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_index ++ ) = tmp ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else { if ( offset < <NUM_LIT> ) { tmp = plus_constant ( Pmode , stack_pointer_rtx , offset ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; mem = gen_frame_mem ( SImode , tmp ) ; offset = <NUM_LIT> ; } else if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , j ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; tmp = emit_insn ( tmp ) ; if ( dwarf_index == <NUM_LIT> ) insn =


<s> delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src ,


<s> if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = FixedVectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else { VecBaseTy = SubVecTy ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( )


<s> return ( __m64 ) __builtin_arm_wcmpgtsb ( ( __v8qi )


<s> void setFrequency ( const MachineBasicBlock * MBB


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) { MBB . addLiveIn ( Reg


<s> SDValue <ISA_LIT>TargetLowering :: LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy


<s> unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) :


<s> rtl_opt_pass * make_pass_s390_early_mach ( gcc :: context * ctxt ) { return new pass_s390_early_mach (


<s> const SmallVector < DTSortableEntry * , <NUM_LIT> >


<s> return <ISA_LIT>TargetLowering :: LowerReturn ( Chain , CallConv , isVarArg , Outs , OutVals , DL , DAG ) ; } bool IsShader = <STR_LIT> ( CallConv ) ; Info -> setIfReturnsVoid ( Outs . empty ( ) ) ; bool IsWaveEnd = Info -> returnsVoid ( ) && IsShader ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; SmallVector < <STR_LIT> , <NUM_LIT> > Splits ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; if ( ! Info -> isEntryFunction ( ) ) { const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; SDValue ReturnAddrReg = CreateLiveInRegister ( DAG , & <STR_LIT> , TRI -> getReturnAddressReg ( MF ) , <STR_LIT> ) ; SDValue ReturnAddrVirtualReg = DAG . getRegister ( MF . getRegInfo ( ) . createVirtualRegister ( CallConv != CallingConv :: <ISA_LIT>_Gfx ? & <STR_LIT> : & <STR_LIT> ) , <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , ReturnAddrVirtualReg , ReturnAddrReg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( ReturnAddrVirtualReg ) ; } for ( unsigned I = <NUM_LIT> , RealRVLocIdx = <NUM_LIT> , E = RVLocs . size ( ) ; I != E ; ++ I , ++ RealRVLocIdx ) { CCValAssign & VA = RVLocs [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ RealRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL ,


<s> ~ <ISA_LIT>ScheduleBlockScheduler ( )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> unsigned getSRetReturnReg ( ) const { return SRetReturnReg


<s> switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand ::


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OMods ( SDValue In , SDValue & Src , SDValue & Clamp , SDValue & Omod ) const { Src =


<s> DEBUG ( dbgs ( ) << <STR_LIT> << DstBlk -> getNumber ( )

<< <STR_LIT> << LandMBB -> getNumber ( ) << <STR_LIT> ; ) ;


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - <NUM_LIT>


<s> unsigned IndexReg = Inst -> getOperand ( IndexOpPosition ) . getReg ( ) ; if (


<s> return new <ISA_LIT>LowerKernelArgs (


<s> unsigned RegOffsetInSet = getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [ RegLargestSuper ] ; Value * Idx [ ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( RegOffsetInSet ) } ; Builder . CreateStore ( Val , Builder . CreateInBoundsGEP ( RegSet , Idx ) ) ; } ; InitRegTo ( <STR_LIT> , RSP ) ; InitRegTo ( <STR_LIT> , Builder . CreateZExt ( ArgC , Builder . getInt64Ty ( ) ) ) ; InitRegTo ( <STR_LIT> , Builder . CreatePtrToInt ( ArgV ,


<s> else if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op


<s> case PowerPCCC :: PL : return <STR_LIT> ; case PowerPCCC :: VS : return <STR_LIT> ; case PowerPCCC :: VC : return <STR_LIT> ; case PowerPCCC :: HI : return <STR_LIT> ; case PowerPCCC :: LS : return <STR_LIT> ; case PowerPCCC :: GE : return <STR_LIT> ; case PowerPCCC :: LT : return <STR_LIT> ; case PowerPCCC :: GT : return <STR_LIT> ; case PowerPCCC :: LE :


<s> case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) { rtx tmp = sh_compare_op0 ; sh_compare_op0 = sh_compare_op1 ; sh_compare_op1 = tmp ; } mode = GET_MODE ( sh_compare_op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( sh_compare_op1 ) ; sh_compare_op0 = force_reg ( mode , sh_compare_op0 ) ; if ( ( code != EQ && code != NE && ( sh_compare_op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && sh_compare_op1 != const0_rtx ) || (

TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) sh_compare_op1 = force_reg ( mode , sh_compare_op1 ) ;


<s> void Emitter < CodeEmitter > :: addPCLabel ( unsigned LabelID ) { DOUT << <STR_LIT> << LabelID << <STR_LIT> << ( void *


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond ) const { DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , Align ) ; unsigned LoadOp = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOp = <STR_LIT> ; } else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) LoadOp = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstrBuilder NewMI = BuildMI ( MBB , MBBI , DL , get ( LoadOp )


<s> for ( unsigned i = <NUM_LIT> ; i < blocks . size ( ) ; i ++ ) { if ( blocks [ i ] -> getMBB ( ) == MBB ) { return ! Priv -> LRs . at ( pred ) . hasDefBefore ( i ) ; } } return


<s> SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; int64_t ImmValue = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SDValue DownOffset , UpOffset ; if ( ImmValue >= <NUM_LIT> ) { DownOffset = DAG . getConstant ( ImmValue , DL , XLenVT ) ; UpOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DownOffset ) ; } else { UpOffset = DAG . getConstant ( - ImmValue , DL , XLenVT ) ; DownOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , UpOffset ) ; } SDValue TrueMask = getAllOnesMask ( VecVT , VLMax


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isSymbol ( ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT>


<s> return ( uint8x8_t ) __builtin_aarch64_sqmovunv8hi (


<s> if ( MO . isReg ( ) && MO . isDef ( ) && ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ) ) { return true ; } } return


<s> targetm . sched . first_cycle_multipass_issue = core2i7_first_cycle_multipass_issue ; targetm . sched . first_cycle_multipass_backtrack = core2i7_first_cycle_multipass_backtrack ; targetm . sched . first_cycle_multipass_end = core2i7_first_cycle_multipass_end ; targetm . sched . first_cycle_multipass_fini = core2i7_first_cycle_multipass_fini ; core2i7_secondary_decoder_max_insn_size = <NUM_LIT> ; core2i7_ifetch_block_size =


<s> if ( MI . isMetaInstruction ( ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return true


<s> auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - FirstSPAdjustAmount ) ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } } } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry .


<s> bool <ISA_LIT>InstrInfo :: isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock &


<s> void <ISA_LIT>ELFStreamer :: EmitLabel ( MCSymbol *


<s> SDValue AMDGPUTargetLowering :: LowerSREM64 ( SDValue Op , SelectionDAG & DAG ) const { return SDValue ( Op . getNode ( ) , <NUM_LIT>


<s> uint8_t BitG = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitH = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t EncVal = BitA ; EncVal <<= <NUM_LIT> ; EncVal |= BitB ; EncVal <<= <NUM_LIT> ; EncVal |= BitC ; EncVal <<= <NUM_LIT> ; EncVal |= BitD ; EncVal <<=


<s> FunctionPass * llvm :: create<ISA_LIT>LongBranchPass ( <ISA_LIT>TargetMachine & tm


<s> case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getTargetConstant ( x86cc , DL , <STR_LIT> ) ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Ins ) , DL , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getTargetConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> :


<s> unsigned HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; unsigned FstHalfBegin = ( Imm & <NUM_LIT> ) * HalfSize ; unsigned SndHalfBegin = ( ( Imm >> <NUM_LIT> ) &


<s> assert ( ( ( FenceArg >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'i' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O


<s> while ( V1 . getOpcode ( ) == <STR_LIT> ) V1 = V1 -> getOperand ( <NUM_LIT> ) ; while ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V2 -> getOperand ( <NUM_LIT> ) ; bool V1IsZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsZero = <STR_LIT> ( V2 . getNode ( ) ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> || ( M >= <NUM_LIT> && M < Size && V1IsZero ) || ( M >= Size && V2IsZero ) ) { Zeroable [ i ] = true ; continue ; } SDValue V = M < Size ? V1 : V2 ; if ( V . getOpcode ( ) != <STR_LIT> || Size != ( int )


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( XFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Addr , Op . getOperand ( <NUM_LIT> )


<s> SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 ,


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; <ISA_LIT>MCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; return MCDisassembler


<s> FunctionPass * llvm :: createMLxExpansionPass


<s> if ( RegWidth == <NUM_LIT> && N != <NUM_LIT> ) return false ; int Width = <NUM_LIT> ; if ( N == <NUM_LIT> ) Width = <NUM_LIT> ; else if ( ( ImmS & <NUM_LIT> ) == <NUM_LIT> ) Width = <NUM_LIT> ; else if ( ( ImmS & <NUM_LIT> ) == <NUM_LIT> ) Width = <NUM_LIT> ; else if ( ( ImmS & <NUM_LIT> ) == <NUM_LIT> ) Width = <NUM_LIT> ; else if ( ( ImmS & <NUM_LIT> ) == <NUM_LIT> ) Width = <NUM_LIT> ; else if ( ( ImmS & <NUM_LIT> ) == <NUM_LIT> ) Width = <NUM_LIT> ; else { return false


<s> assert ( checkValueMapping ( ValueMappings [ DPR3OpsIdx ] , & PartMappings [ PMI_DPR - PMI_Min ] ) && <STR_LIT> ) ; assert ( checkValueMapping ( ValueMappings [ DPR3OpsIdx + <NUM_LIT> ] , & PartMappings [ PMI_DPR - PMI_Min ] ) && <STR_LIT> ) ; assert ( checkValueMapping ( ValueMappings [ DPR3OpsIdx + <NUM_LIT> ] , & PartMappings [ PMI_DPR - PMI_Min ] )


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { TargetPassConfig :: addPreEmitPass ( ) ; addPass ( create<ISA_LIT>CFGStackify ( )


<s> case <STR_LIT> : { if ( ( Op == <STR_LIT> && MFI -> getMode ( ) . FP32OutputDenormals ) || ( Op == <STR_LIT> && MFI -> getMode ( ) . FP64FP16OutputDenormals ) ) return std :: make_pair ( nullptr , <STR_LIT> ) ; const MachineOperand * Src0 = TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src0 -> isReg ( ) && Src1 -> isReg ( ) && Src0 -> getReg ( ) == Src1 -> getReg ( ) && Src0 -> getSubReg ( ) == Src1 -> getSubReg ( ) && ! TII -> hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) && ! TII -> hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) && ! TII -> hasModifiersSet ( MI , <STR_LIT> :: clamp ) && ! TII -> hasModifiersSet ( MI , <STR_LIT> :: omod

) ) return std :: make_pair ( Src0 , <STR_LIT> ) ;


<s> assert ( ! VT . isVector ( ) ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( SrcVT ) ; if ( ! IsSigned && UseSSEReg ) { if ( Subtarget . hasAVX512 ( ) ) return Op ; if ( VT == <STR_LIT> ) return SDValue ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Src } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } if ( ! Subtarget . hasSSE3 ( ) ) return SDValue ( ) ; } if ( VT == <STR_LIT> && ( UseSSEReg || SrcVT == <STR_LIT> ) ) { assert ( IsSigned && <STR_LIT> ) ; SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Src } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } if ( UseSSEReg && IsSigned ) return Op ; if ( SrcVT == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( IsSigned ) LC = RTLIB :: getFPTOSINT ( SrcVT , VT ) ; else LC = RTLIB :: getFPTOUINT ( SrcVT , VT ) ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; MakeLibCallOptions CallOptions ; std :: pair < SDValue , SDValue > Tmp = makeLibCall ( DAG , LC , VT , Src , CallOptions , SDLoc ( Op ) , Chain ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp .


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { if ( TargetTriple . getArch ( ) == Triple :: sic ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { CPU = <STR_LIT> ; } else if ( CPU == <STR_LIT> ) { CPU = <STR_LIT> ; return * this ; } else if ( CPU != <STR_LIT> && CPU != <STR_LIT> ) { CPU = <STR_LIT> ; } } else { errs ( ) << <STR_LIT> << TargetTriple . getArch ( ) <<


<s> if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand (


<s> static bool SupportedVectorShiftWithImm ( MVT VT , const <ISA_LIT>Subtarget * Subtarget , unsigned Opcode ) { if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT . is512BitVector ( ) && ( VT . getScalarSizeInBits ( ) > <NUM_LIT> || Subtarget -> hasBWI ( ) ) ) return true ; bool LShift = VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ; bool AShift = LShift && ( Subtarget -> hasVLX ( ) || ( VT


<s> int Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg


<s> unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> . contains ( RegD ) ; RegD = II -> getRegisterInfo ( ) . getEncodingValue ( RegD ) ; if ( ! isSPVFP ) { Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> )


<s> unsigned getSRetReturnReg ( ) const { return


<s> unsigned SubReg = TRI -> getSubReg ( VecReg , <STR_LIT> ) ; if ( ! SubReg ) SubReg = VecReg ; const TargetRegisterClass * RC = TRI -> getPhysRegClass ( SubReg ) ; int RegIdx = TRI -> getHWRegIndex


<s> unsigned Id ; visitTypeEntry ( Ty , Id , false , false


<s> BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( Highest ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Higher ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Hi ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Lo ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } assert ( BalTgtMBBSize == BalTgtMBB -> size ( ) ) ; assert ( LongBrMBB -> size ( ) + BalTgtMBBSize == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( ) ; LongBrMBB -> addSuccessor (


<s> insn < <STR_LIT> ; ++ insn ) { NewMI = BuildMI ( B , I , DL , get ( insn ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getName ( NewMI -> getOpcode ( ) ) <<

<STR_LIT> << NewMI -> getDesc ( ) . getSchedClass ( ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . getMMI ( ) . hasDebugInfo ( ) || MF .

getFunction ( ) . needsUnwindTableEntry ( ) ;


<s> UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT>


<s> allPath ( CostLeaf * begin , CostLeaf * end ) : begin


<s> TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( create<ISA_LIT>InsertCopiesPass ( ) )


<s> if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) { ShuffleMask . clear ( ) ; return ; } if ( isa < UndefValue > ( COp ) ) ShuffleMask . push_back ( SM_SentinelUndef ) ; else { APInt Element = cast < ConstantInt > ( COp ) -> getValue ( ) ; Element = Element . getLoBits ( EltMaskSize ) ; ShuffleMask . push_back ( Element .


<s> return ; } if ( TARGET_MIPS16 ) { mips_emit_move ( temp , mips_cprestore_slot ( temp , true ) ) ; mips_emit_move ( pic_offset_table_rtx , temp ) ; } else mips_emit_move ( pic_offset_table_rtx , mips_cprestore_slot ( temp


<s> const TargetRegisterInfo & TRI = PRI . getTRI ( ) ; for ( MCRegUnitIterator U ( RR . Reg , & TRI ) ; U . isValid ( ) ; ++ U ) { MCRegUnitRootIterator R ( * U , & TRI ) ; ++ R ; if ( ! R . isValid ( )


<s> auto * Load = cast < LoadSDNode > ( Store -> getValue ( ) ) ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; if ( Size > <NUM_LIT> && Size <= <NUM_LIT> ) { if ( <STR_LIT> ( Load -> getBasePtr ( ) . getOpcode ( ) ) ) return false ; if ( <STR_LIT> ( Store -> getBasePtr ( ) .


<s> static rtx riscv_emit_binary ( enum rtx_code code , rtx dest , rtx x


<s> SectionData :: FragmentListType & frag_list = m_SectionData -> getFragmentList ( ) ; SectionData :: iterator frag , fragEnd = m_SectionData -> end ( ) ; for ( frag = m_SectionData -> begin ( ) ; frag != fragEnd ; ++ frag ) { frag -> setOffset ( offset ) ; offset += frag -> size ( ) ; } if ( ! m_GOTPLT . empty ( ) ) { m_pGOTPLTFront = m_GOTPLT . front ( ) ; entry_iterator it , end = m_GOTPLT . end ( ) ; for ( it = m_GOTPLT . begin ( ) ; it != end ; ++ it ) { <ISA_LIT>GOTEntry * entry = * it ; frag_list . push_back ( entry ) ; entry -> setParent ( m_SectionData ) ; entry -> setOffset ( offset ) ; offset += entry -> size ( ) ; } } m_GOTPLT . clear ( ) ; if ( ! m_GOT . empty ( ) ) { m_pGOTFront = m_GOT . front ( ) ; entry_iterator it , end = m_GOT . end ( ) ; for ( it = m_GOT . begin ( ) ; it != end ; ++


<s> if ( ! LastMI -> killsRegister ( <STR_LIT> ) && ! checkCCKill ( * LastMI , JoinMBB ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = skipDebugInstructionsForward ( std :: next ( MachineBasicBlock :: iterator ( LastMI ) ) , MBB -> end ( ) ) ; createPHIsForSelects ( MIItBegin , MIItEnd , StartMBB , FalseMBB


<s> switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstantExpression ( CE , AP . TM . getDataLayout ( ) ) ) if ( C != CE ) return LowerConstant ( C , AP ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; WriteAsOperand ( OS , CE , false , ! AP . MF ? <NUM_LIT> : AP . MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; const Constant * PtrVal = CE -> getOperand ( <NUM_LIT> ) ; SmallVector < Value * , <NUM_LIT> > IdxVec ( CE -> op_begin ( ) + <NUM_LIT> , CE -> op_end ( ) ) ; int64_t Offset = TD . getIndexedOffset ( PtrVal -> getType ( ) , IdxVec ) ; const MCExpr * Base = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; if ( Offset == <NUM_LIT> ) return Base ; if ( TD . getPointerSizeInBits ( ) != <NUM_LIT> ) { int SExtAmount = <NUM_LIT> - TD . getPointerSizeInBits ( ) ; Offset = ( Offset << SExtAmount ) >> SExtAmount ; } return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE


<s> EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != <STR_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind


<s> return __builtin_mve_vorrq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __b ,


<s> x = avoid_constant_pool_reference ( x ) ; if ( UNARY_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , <NUM_LIT> ) , reg_values ) ; return simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ; } if ( ARITHMETIC_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , <NUM_LIT> ) , reg_values


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && Cnt <= ElementBits


<s> case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { ControlFlowStack . pop_back ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; LastSeenEHInst = END_TRY ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( LastSeenEHInst != CATCH ) { if ( EHPadStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( EHPadStack . pop_back_val ( ) ) + ':' ) ; } } LastSeenEHInst = CATCH ; break ; } unsigned NumFixedOperands = Desc . NumOperands ; SmallSet < uint64_t , <NUM_LIT> > Printed ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i < e ; ++ i ) { if ( i < NumFixedOperands ) { if ( Desc . OpInfo [ i ] . OperandType != <STR_LIT> ) continue ; } else { if ( ! MI -> getOperand ( i ) . isImm ( ) ) continue ; } uint64_t Depth = MI -> getOperand ( i ) . getImm ( ) ; if ( ! Printed . insert ( Depth ) . second ) continue ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( Depth > EHPadStack . size ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else if ( Depth == EHPadStack . size ( ) ) { printAnnotation ( OS , utostr ( Depth ) + <STR_LIT> + <STR_LIT> ) ; } else { uint64_t CatchNo = EHPadStack . rbegin ( ) [ Depth ] ; printAnnotation ( OS , utostr ( Depth ) + <STR_LIT> + <STR_LIT> + utostr ( CatchNo ) ) ; } } else { if ( Depth >= ControlFlowStack . size


<s> vabal_s8 ( int16x8_t a , int8x8_t b , int8x8_t c ) { int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ,


<s> if ( scaleShuffleElements ( SVN0 -> getMask ( ) , <NUM_LIT> , ShuffleMask0 ) && scaleShuffleElements ( SVN1 -> getMask ( ) , <NUM_LIT> , ShuffleMask1 ) ) { SDValue Op00 = SVN0 -> getOperand ( <NUM_LIT> ) ; SDValue Op01 = SVN0 -> getOperand ( <NUM_LIT> ) ; SDValue Op10 = SVN1 -> getOperand ( <NUM_LIT> ) ; SDValue Op11 = SVN1 -> getOperand ( <NUM_LIT> ) ; if ( ( Op00 == Op11 ) && ( Op01 == Op10 ) ) { std :: swap ( Op10 , Op11 ) ; ShuffleVectorSDNode :: commuteMask ( ShuffleMask1 ) ; } if ( ( Op00 == Op10 ) && ( Op01 == Op11 ) ) { SmallVector < int , <NUM_LIT> > ShuffleMask ; ShuffleMask . append ( ShuffleMask0 . begin ( ) , ShuffleMask0 . end ( ) ) ; ShuffleMask . append ( ShuffleMask1 . begin ( ) , ShuffleMask1 . end ( ) ) ; SDLoc DL ( N ) ; SDValue Res = DAG . getNode ( Opcode , DL , VT , Op00 , Op01 ) ; Res = DAG . getBitcast ( <STR_LIT> ,


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseCoprocRegOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Reg = MatchCoprocessorOperandName ( Tok . getString ( ) , 'c' ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocReg


<s> else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( CopyOpcode ) , DestReg

) . addReg ( SrcReg , KillSrc ? RegState :: Kill : <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return


<s> while ( ( ( val <<= <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) ++ i ; return i ; } if ( ( val & <NUM_LIT> ) == <NUM_LIT> || ( val & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; i = <NUM_LIT>


<s> const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; <ISA_LIT>Operand :: CreateImm ( Op , IdVal , S , E ) ; return false ; case AsmToken :: LBrac : return ParseMemory ( Op ) ; case AsmToken :: LCurly : return ParseRegisterList ( Op ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal )


<s> sel = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , sel ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_1 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_1 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_mult ( SImode , sel , GEN_INT ( <NUM_LIT> ) , sel , <NUM_LIT> ) ; t_1 = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; break ; case V4HImode : t_1 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , sel ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_1 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_2 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_3 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_1 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , IOR , t_2 , t_3 , t_2 , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_2 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_mult ( SImode , sel , GEN_INT ( <NUM_LIT> ) , sel , <NUM_LIT> ) ; t_1 = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; break ; case V8QImode : sel = expand_simple_binop ( DImode , AND , sel , GEN_INT ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> | <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( DImode , IOR , sel , t_1 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( DImode , AND , sel , GEN_INT ( ( HOST_WIDE_INT ) <NUM_LIT> << <NUM_LIT> | <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( DImode , LSHIFTRT , sel , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT>


<s> DiagnosticInfoUnsupported IllegalCopy ( MF -> getFunction ( ) , <STR_LIT> , DL , DS_Error ) ; LLVMContext & C = MF -> getFunction ( ) . getContext ( ) ; C . diagnose ( IllegalCopy )


<s> void EmitARM64WinCFISaveRegPX ( unsigned Reg , int Offset ) override { OS << <STR_LIT> << Reg << <STR_LIT> << Offset


<s> isZBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; } unsigned NZCV = <STR_LIT> ( CmpBBTailCC ) ; const MCInstrDesc & MCID = TII -> get ( Opc ) ; MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; if ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . isReg ( ) ) MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , MCID ) . addOperand ( CmpMI -> getOperand ( FirstOp ) ) ; if ( isZBranch ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addOperand ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) ) ; MIB . addImm ( NZCV ) . addImm ( HeadCmpBBCC ) ; if ( isZBranch ) { bool isNZ = CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI -> getOpcode ( ) == <STR_LIT> ; BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( isNZ ? <STR_LIT> : <STR_LIT> ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; } CmpMI -> eraseFromParent ( ) ; Head -> updateTerminator ( ) ; RemovedBlocks . push_back ( CmpBB ) ; CmpBB -> eraseFromParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * Head ) ; ++


<s> DebugLoc DL = Op . getDebugLoc ( ) ; BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true ) ; return DAG . getNode ( <STR_LIT> , DL


<s> index = XEXP ( x , <NUM_LIT> ) ; if ( ! REG_P ( base ) ) return false ; if ( REG_P ( index ) ) { if ( ! TARGET_AM33 ) return false ; return ( REGNO_GENERAL_P ( REGNO ( base ) , strict ) && REGNO_GENERAL_P ( REGNO ( index ) , strict ) ) ; } if ( ! REGNO_STRICT_OK_FOR_BASE_P ( REGNO ( base ) , strict ) ) return false ; if ( CONST_INT_P ( index ) ) return IN_RANGE ( INTVAL ( index ) , - <NUM_LIT> - <NUM_LIT> , <NUM_LIT> ) ; if ( CONSTANT_ADDRESS_P ( index ) ) return ! flag_pic || mn10300_legitimate_pic_operand_p


<s> unsigned i = <NUM_LIT> ; const unsigned MAX_LOADS_IN_LDM = Subtarget -> isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue TFOps [ <NUM_LIT> ] ; SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , isVolatile , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstPtrInfo . getWithOffset ( DstOff ) , isVolatile , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT>


<s> const TargetMachine & TM = Fn . getTarget ( ) ; TL = TM . getTargetLowering ( ) ; AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI


<s> int mcore_num_zeros ( int mask ) { return <NUM_LIT> - mcore_num_ones (


<s> else output_asm_insn ( AS2 ( sbrc , % <NUM_LIT> , % <NUM_LIT> ) , operands ) ; } else { static char buf [ ] = <STR_LIT> ; int bit_nr = exact_log2 ( INTVAL ( operands [ <NUM_LIT> ] ) & GET_MODE_MASK ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ) ; buf [ <NUM_LIT> ] = ( comp == EQ ) ? 's' : 'c' ; buf [ <NUM_LIT> ] = 'A' + ( bit_nr >> <NUM_LIT> ) ; buf [ <NUM_LIT> ] = '0' + ( bit_nr & <NUM_LIT> ) ; output_asm_insn ( buf , operands ) ; } } if ( long_jump ) return ( AS1 ( rjmp , . + <NUM_LIT> ) CR_TAB AS1 ( jmp , % <NUM_LIT> ) ) ; if ( ! reverse ) return AS1 ( rjmp ,


<s> printAMIndexedWB ( MI , OpNum , BitWidth


<s> assert ( MCID . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; setOpcode ( op


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> type = TYPE_MOFFS64 ; break ; } } else if ( type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || type == TYPE_IMM64 ) { uint32_t Opcode = mcInst . getOpcode ( ) ; switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID : type = TYPE_MOFFS32 ; break ; case ENCODING_IO : type = TYPE_MOFFS64 ; break ; } } switch ( type ) { case TYPE_XMM128 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_XMM256 : mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_REL8 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset + insn . immediateSize ; case TYPE_MOFFS8 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_MOFFS16 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_REL32 : case TYPE_REL64 : isBranch = true ; pcrel = insn . startLocation + insn . immediateOffset + insn . immediateSize ; case TYPE_MOFFS32 : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case TYPE_MOFFS64 : default : break ; } if ( ! tryAddingSymbolicOperand ( immediate + pcrel , isBranch , insn . startLocation , insn . immediateOffset , insn . immediateSize , mcInst , Dis

) ) mcInst . addOperand ( MCOperand :: CreateImm ( immediate ) ) ;


<s> SDValue FlatNullPtr = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; unsigned SrcAS = ASC -> getSrcAddressSpace ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( getTargetMachine ( ) ) ; if ( SrcAS == <ISA_LIT>AS :: FLAT_ADDRESS ) { unsigned DestAS = ASC -> getDestAddressSpace ( ) ; if ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; if ( isKnownNonNull ( Src , DAG , TM , SrcAS ) ) return Ptr ; unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; SDValue SegmentNullPtr = DAG . getConstant ( NullVal , SL , <STR_LIT> ) ; SDValue NonNull = DAG . getSetCC ( SL , <STR_LIT> , Src , FlatNullPtr , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NonNull , Ptr , SegmentNullPtr ) ; } } if ( ASC -> getDestAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( SrcAS == <ISA_LIT>AS :: LOCAL_ADDRESS || SrcAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { SDValue Aperture = getSegmentAperture ( ASC -> getSrcAddressSpace ( ) , SL , DAG ) ; SDValue CvtPtr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src , Aperture ) ; CvtPtr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtPtr ) ; if ( isKnownNonNull ( Src , DAG , TM , SrcAS ) ) return CvtPtr ; unsigned NullVal = TM . getNullPointerValue


<s> return __builtin_mve_vaddvq_uv16qi (


<s> fndecl = fntype ; fntype = TREE_TYPE ( fntype ) ; } pcs_variant = arm_get_pcs_model ( fntype , fndecl ) ; } else pcs_variant = arm_pcs_default ; if ( type && INTEGRAL_TYPE_P ( type ) ) mode = arm_promote_function_mode ( type , mode , & unsignedp , fntype , <NUM_LIT> ) ; if ( pcs_variant != ARM_PCS_AAPCS ) { int i ; for ( i = <NUM_LIT> ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) if ( aapcs_cp_arg_layout [ i ] . is_return_candidate ( pcs_variant , mode , type ) ) return aapcs_cp_arg_layout [ i ] . allocate_return_reg ( pcs_variant


<s> rtx body = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == MEM ) ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; rtx_insn * and_insn ; rtx and_operation = find_alignment_op ( insn , base_reg , & and_insn ) ; if ( and_operation != <NUM_LIT> ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx and_base = XEXP ( and_operation


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSetFp ( Value ) ; StringRef ModuleValue ; OS << <STR_LIT> ; OS << ABIFlagsSection . getFpABIString


<s> static DecodeStatus DecodeRRRRInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s3 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s2 , Address , Decoder