<s> static void aarch64_emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / <NUM_LIT> - <NUM_LIT> ; insn = emit_jump_insn ( insn )


<s> unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Alignment . value ( ) , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( ( unsigned ) Alignment . value ( ) , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL ,


<s> } EVT ValueVT = Value . getValueType ( ) ; if ( StoreNode -> getAddressSpace ( ) != <STR_LIT> ) { return SDValue ( ) ; } SDValue Ret = AMDGPUTargetLowering :: LowerSTORE ( Op , DAG ) ; if ( Ret . getNode ( ) ) { return Ret ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( ValueVT . isVector ( ) ) { unsigned NumElemVT = ValueVT . getVectorNumElements ( ) ; EVT ElemVT = ValueVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Stores ( NumElemVT ) ; assert ( NumElemVT >= StackWidth && <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElemVT ; ++ i ) { unsigned Channel , PtrIncr ; getStackAddress ( StackWidth , i , Channel , PtrIncr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( PtrIncr , <STR_LIT> ) ) ; SDValue Elem = DAG . getNode ( <STR_LIT> , DL , ElemVT , Value , DAG . getConstant ( i , <STR_LIT> ) ) ; Stores [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Elem , Ptr , DAG . getTargetConstant ( Channel , <STR_LIT> ) ) ; } Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Stores ) ; } else


<s> if ( isToken ( AsmToken :: Identifier ) && ( HwReg . Id = getHwregId ( getTokenStr ( ) , getSTI ( ) ) ) != OPR_ID_UNKNOWN ) { HwReg . IsSymbolic = true ; lex ( ) ; } else if ( ! parseExpr ( HwReg . Id , <STR_LIT> ) ) { return false


<s> poly8x16x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t ) __builtin_aarch64_get_qregxiv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x16_t )


<s> MRT * getEntryTree ( ) { return Children . back


<s> unsigned XMMSize = WinEHXMMSlotInfo . size ( ) * TRI -> getSpillSize ( <STR_LIT> ) ; unsigned UsedSize ; EHPersonality Personality = classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ; if ( Personality == EHPersonality :: CoreCLR ) { UsedSize = getPSPSlotOffsetFromSP ( MF ) + SlotSize ; } else


<s> static inline const MachineInstrBuilder & addDirectMem ( const

MachineInstrBuilder & MIB , unsigned Reg ) {


<s> bool <ISA_LIT>Operand :: isABID ( ) const { return isImm ( ) && getImmTy ( ) == ImmTyABID && isUInt


<s> } if ( ! MI -> isDebugInstr ( ) ) { for ( auto & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isDef ( ) ) Op . setIsUndef ( false ) ; RegisterOperands RegOpers ; RegOpers . collect ( * MI , * TRI , MRI , true , false ) ; auto SlotIdx = LIS -> getInstructionIndex ( * MI ) . getRegSlot ( ) ; RegOpers . adjustLaneLiveness ( * LIS , MRI , SlotIdx , MI ) ; } Top = std :: next ( MI -> getIterator ( ) ) ; } RegionBegin = getMachineInstr ( Schedule . front ( ) ) ; if ( ! std :: is_same < decltype ( * Schedule . begin ( ) ) , MachineInstr * > :: value ) { placeDebugValues ( ) ; RegionEnd = R . End ; } R . Begin = RegionBegin ; R . MaxPressure = MaxRP ; const auto RegionMaxRP = getRegionPressure ( R ) ; const auto & ST = MF . getSubtarget < GCNSubtarget > ( ) ; assert ( ( SchedMaxRP == RegionMaxRP && ( MaxRP . empty ( ) || SchedMaxRP == MaxRP ) ) || ( dbgs ( ) << <STR_LIT> <STR_LIT> , SchedMaxRP . print ( dbgs ( ) , & ST ) , dbgs ( ) << <STR_LIT> , MaxRP . print ( dbgs ( ) , & ST )

, dbgs ( ) << <STR_LIT> , RegionMaxRP . print ( dbgs ( ) , & ST ) , false ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> bool aarch64_simd_imm_scalar_p ( rtx x , machine_mode mode ATTRIBUTE_UNUSED ) { HOST_WIDE_INT imm = INTVAL ( x ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned int byte = imm & <NUM_LIT> ; if ( byte != <NUM_LIT> && byte != <NUM_LIT> ) return false ; imm >>= <NUM_LIT> ; } return true


<s> emit_insn ( gen_movdi_er_tlsgd ( r16 , pic_offset_table_rtx , x , seq ) ) ; insn = gen_call_value_osf_tlsgd ( r0 , tga , seq ) ; insn = emit_call_insn ( insn ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , r16 ) ; insn = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insn , dest , r0 , x ) ; return dest ; case TLS_MODEL_LOCAL_DYNAMIC : start_sequence ( ) ; r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; r16 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; tga = get_tls_get_addr ( ) ; scratch = gen_reg_rtx ( Pmode ) ; seq = GEN_INT ( alpha_next_sequence_number ++ ) ; emit_insn ( gen_movdi_er_tlsldm ( r16 , pic_offset_table_rtx , seq ) ) ; insn = gen_call_value_osf_tlsldm ( r0 , tga , seq ) ; insn = emit_call_insn ( insn ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , r16 ) ; insn = get_insns ( ) ; end_sequence ( ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TLSLDM_CALL ) ; emit_libcall_block ( insn , scratch , r0 , eqv ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_DTPREL ) ; eqv = gen_rtx_CONST ( Pmode , eqv ) ; if ( alpha_tls_size == <NUM_LIT> ) { dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , eqv ) ) ; emit_insn ( gen_adddi3 ( dest , dest , scratch ) ) ; return dest ; } if ( alpha_tls_size == <NUM_LIT> ) { insn = gen_rtx_HIGH ( Pmode , eqv ) ; insn = gen_rtx_PLUS ( Pmode , scratch , insn ) ; scratch = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , insn ) ) ; } return gen_rtx_LO_SUM ( Pmode , scratch , eqv ) ; case TLS_MODEL_INITIAL_EXEC : eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TPREL ) ; eqv = gen_rtx_CONST ( Pmode , eqv ) ; tp = gen_reg_rtx ( Pmode ) ; scratch = gen_reg_rtx ( Pmode ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_get_thread_pointerdi ( tp ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , eqv ) ) ; emit_insn ( gen_adddi3 ( dest , tp , scratch ) ) ; return dest ; case TLS_MODEL_LOCAL_EXEC : eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TPREL ) ; eqv = gen_rtx_CONST ( Pmode , eqv ) ; tp = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_get_thread_pointerdi ( tp ) ) ; if ( alpha_tls_size == <NUM_LIT> ) { insn = gen_rtx_HIGH ( Pmode , eqv ) ; insn = gen_rtx_PLUS ( Pmode , tp , insn ) ; tp = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tp , insn ) ) ; } return gen_rtx_LO_SUM ( Pmode ,


<s> } if ( Op -> Kind == <ISA_LIT>Operand :: Token && Kind != InvalidMatchClass ) { StringRef myStringRef = StringRef ( Op -> Tok . Data , Op -> Tok . Length ) ; if ( matchTokenString ( myStringRef . lower ( ) ) == ( MatchClassKind ) Kind ) return Match_Success ; if ( matchTokenString ( myStringRef . upper ( ) ) == ( MatchClassKind ) Kind ) return Match_Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Op -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) ; addSegmentedMem ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) , <STR_LIT> , <STR_LIT> ) ; addSegmentedMem ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> )


<s> MRI = & MF . getRegInfo ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent ( ) ) ) ; bool Changed = false ; std :: set < unsigned > CoalUpd , PredUpd ; SmallVector < MachineInstr * , <NUM_LIT> > Condsets ; for ( auto & B : MF ) for ( auto & I : B ) if ( isCondset ( I ) ) Condsets . push_back ( & I ) ; Changed |= coalesceSegments ( Condsets , CoalUpd ) ; std :: set < unsigned > KillUpd ; for ( MachineInstr * MI : Condsets ) for ( MachineOperand & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) ) if ( ! CoalUpd . count ( Op . getReg ( ) ) ) KillUpd . insert ( Op . getReg ( ) ) ; updateLiveness ( KillUpd , false , true , false ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent ( ) ) ) ; for ( MachineInstr * MI : Condsets ) Changed |= split ( * MI , PredUpd ) ; Condsets . clear ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent ( ) ) ) ; for ( auto & B : MF ) Changed |= predicateInBlock ( B , PredUpd ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent


<s> if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( CantUnwindLoc . isValid (


<s> bool storeOfVectorConstantIsCheap ( EVT MemVT , unsigned NumElem , unsigned AddrSpace ) const override { return NumElem >


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false


<s> assert ( ( MRI -> getVRegDef ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) == & CmpValDefInstr ) && <STR_LIT> ) ; if ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; MachineInstr * VregDefInstr = MRI -> getVRegDef ( CmpValDefInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( VregDefInstr &&


<s> unsigned SelOp = Pred == SCC_TRUE ? <STR_LIT> : <STR_LIT> ; MachineInstr * Select = BuildMI ( MBB , I , DL , get ( SelOp ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } if ( DstSize == <NUM_LIT> && Pred == SCC_TRUE ) { MachineInstr * Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; assert ( NElts % <NUM_LIT> == <NUM_LIT> ) ; NElts /= <NUM_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) ; I = MIB -> getIterator ( ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( int Idx = <NUM_LIT> ; Idx != NElts ; ++ Idx ) { unsigned DstElt = MRI . createVirtualRegister (


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; } return isNullConstant ( Op


<s> MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getSubtarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++


<s> static void moxie_operand_lossage ( const char * msgid , rtx op ) { debug_rtx ( op ) ; output_operand_lossage ( <STR_LIT>


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ; CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ <NUM_LIT> ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return


<s> auto AddrI = BuildMI ( * Pred , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , TargetReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( & MBB ) . addReg ( <NUM_LIT> ) ; ++ NumInstsInserted ; ( void ) AddrI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } TargetAddrSSA . AddAvailableValue ( Pred , TargetReg ) ; } unsigned TargetReg = TargetAddrSSA . GetValueInMiddleOfBlock ( & MBB ) ; MBB . setHasAddressTaken ( ) ; auto InsertPt = MBB . SkipPHIsLabelsAndDebug ( MBB . begin ( ) ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { auto CheckI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( TargetReg , RegState :: Kill ) . addMBB ( & MBB ) ; ++ NumInstsInserted ; ( void ) CheckI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CheckI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } else { Register AddrReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto AddrI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , AddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( & MBB ) . addReg ( <NUM_LIT> ) ; ++ NumInstsInserted ; ( void ) AddrI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; auto CheckI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( TargetReg , RegState :: Kill ) . addReg ( AddrReg , RegState :: Kill ) ; ++ NumInstsInserted ; ( void ) CheckI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CheckI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; } int PredStateSizeInBytes = TRI -> getRegSizeInBits ( * PS -> RC ) / <NUM_LIT> ; auto CMovOp = <STR_LIT> ( PredStateSizeInBytes ) ; Register UpdatedStateReg = MRI -> createVirtualRegister ( PS -> RC ) ; auto CMovI = BuildMI ( MBB , InsertPt , DebugLoc ( ) , TII -> get ( CMovOp ) , UpdatedStateReg ) . addReg ( PS -> InitialReg ) . addReg ( PS -> PoisonReg ) . addImm ( <STR_LIT> ) ; CMovI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( true ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CMovI -> dump (


<s> vmla_f32 ( float32x2_t a , float32x2_t b ,


<s> UsedRegs . insert ( MO . getReg ( ) ) ; } } ; auto J = std :: prev ( I ) ; for ( ; J -> getOpcode ( ) != <STR_LIT> ; -- J ) { if ( J -> getOpcode ( ) == <STR_LIT> || DefinesUsedReg ( * J ) ) { bool SawStore = true ; assert ( J -> isSafeToMove ( nullptr , SawStore ) ) ; TrackUsedRegs ( * J ) ; auto NewJ = std :: next ( J ) ; PushedMIs . push_back ( J -> removeFromParent ( ) ) ; J = NewJ ; } } while ( ! PushedMIs . empty ( ) ) { MBB . insert ( J , PushedMIs . back ( ) ) ; PushedMIs . pop_back (


<s> static const Constant * getTargetShuffleMaskConstant ( SDValue MaskNode ) { while ( MaskNode . getOpcode ( ) == <STR_LIT> ) MaskNode = MaskNode . getOperand ( <NUM_LIT> ) ; auto * MaskLoad = dyn_cast < LoadSDNode > ( MaskNode ) ; if ( ! MaskLoad )


<s> static SDValue LowerPREFETCH ( SDValue Op , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; unsigned IsWrite = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Locality = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool IsStream = ! Locality ; if ( Locality ) { assert ( Locality <= <NUM_LIT> && <STR_LIT>


<s> tree gimple_folder :: load_store_cookie ( tree type ) { return build_int_cst ( build_pointer_type ( type ) , TYPE_ALIGN (


<s> Type * VecWidth = VecInst -> getType ( ) ; ( void ) VecWidth ; assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL .


<s> MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) { if ( ! It -> isDebugValue ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( MachineOperand & Op : MI . operands ( ) ) { if ( Op . isReg ( ) ) { if ( ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) LastDef [ * SubRegs ] = & MI ; } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = & MI ; } else if ( Op . isRegMask ( ) ) { for ( unsigned Reg : <STR_LIT> ) if ( Op . clobbersPhysReg ( Reg ) ) LastDef [ Reg ]


<s> } dbgs ( ) << <STR_LIT> << <STR_LIT> ; for ( MachineInstr * MI : Instrs ) { dbgs ( ) << <STR_LIT> ; MI -> print ( dbgs ( ) ) ; } dbgs ( )


<s> emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { gen_shrd = mode == DImode ? gen_x86_shrd : gen_x86_64_shrd ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; split_double_mode ( mode , operands , <NUM_LIT> , low , high ) ; emit_insn ( gen_shrd ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_ashr3 ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { rtx ( * gen_x86_shift_adj_1 ) ( rtx , rtx , rtx , rtx ) = mode == DImode ? gen_x86_shiftsi_adj_1 : gen_x86_shiftdi_adj_1 ; emit_move_insn ( scratch , high [ <NUM_LIT> ] ) ; emit_insn ( gen_ashr3 ( scratch , scratch , GEN_INT ( half_width


<s> const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; return MI . getOperand ( <NUM_LIT> ) . isReg ( ) || RI . isAGPR ( MRI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( ! C ) return false ; ScaledConstant = ( int ) C -> getZExtValue ( ) ; if ( ( ScaledConstant % Scale ) != <NUM_LIT> ) return false ; ScaledConstant /=


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode


<s> } else if ( getEMachine ( ) == ELF :: EM_386 ) { if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case FK_PCRel_1 : case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC8 ; break ; } break ; case FK_PCRel_2 : case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC16 ; break ; } break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_32 ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_386_GOT32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_386_GOTOFF ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_386_TLS_GD ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF


<s> static inline bool current_function_saves_lr


<s> if ( Occupancy >= MFI -> getMinAllowedOccupancy ( ) && MaxPressure . getVGPRNum ( ) <= MaxVGPRs && MaxPressure . getSGPRNum ( ) <= MaxSGPRs ) { LastRecordedOccupancy = Occupancy


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncodingMMImm16 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg (


<s> Alignment = ( Alignment & - Alignment ) ; if ( Alignment == <NUM_LIT> ) Alignment = <NUM_LIT> ; } Align = CurDAG -> getTargetConstant ( Alignment , dl , <STR_LIT> ) ; unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } std :: vector < EVT > ResTys ; if ( IsLoad ) { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx +


<s> vmvnq_u16 ( uint16x8_t __a ) { return ~


<s> static void parseCondBranch ( MachineInstr * LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT>


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return false ; return true


<s> auto & Func = MF . getFunction ( ) ; auto Kern = getHSAKernelProps ( MF , ProgramInfo ) ; assert ( Func . getCallingConv ( ) == CallingConv :: <ISA_LIT>_KERNEL || Func . getCallingConv ( ) == CallingConv :: SPIR_KERNEL ) ; auto Kernels = getRootMetadata ( <STR_LIT> ) . getArray ( true ) ; { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( Func . getName ( ) ) ; Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( ( Twine ( Func . getName ( ) ) + Twine ( <STR_LIT> ) ) . str ( ) , true ) ; emitKernelLanguage ( Func , Kern ) ; emitKernelAttrs ( Func , Kern ) ; emitKernelArgs ( Func ,


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstantFP ( APF . convertToFloat ( ) , dl , <STR_LIT> ) ) ) ; return ; } else if ( N -> getValueType ( <NUM_LIT> )


<s> if ( SDValue Sad = combineLoopSADPattern ( N , DAG , Subtarget ) ) return Sad ; } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return combineAddOrSubToADCOrSBB ( N , DAG


<s> unsigned getStackPtrReg ( ) const { return <ISA_LIT>StackPtr


<s> addMemoryRegisterOffsetOperands ( Inst , N , Mem . ShiftVal == <NUM_LIT>


<s> Val = DAG . getNode ( <STR_LIT> , DL , VT , Val ) ; Val = convertToScalableVector ( DAG , ContainerSrcVT , Val ) ; Val = getSVESafeBitCast ( CvtVT , Val , DAG ) ; Val = DAG . getNode ( Opcode , DL , ContainerDstVT , Pg , Val , DAG . getUNDEF ( ContainerDstVT ) ) ; return convertFromScalableVector ( DAG , VT , Val ) ; } else { EVT CvtVT = ContainerSrcVT . changeTypeToInteger ( ) ; SDValue Pg = getPredicateForVector ( DAG , DL , CvtVT ) ; Val = convertToScalableVector ( DAG , ContainerSrcVT , Val ) ; Val = DAG . getNode ( Opcode , DL , CvtVT , Pg , Val , DAG . getUNDEF (


<s> if ( CC >= LPCC :: UNKNOWN ) OS << <STR_LIT> ; else OS << <ISA_LIT>CondCodeToString ( CC


<s> if ( flag_pic ) return legitimize_pic_address ( orig_x , mode ,


<s> return ( uint32x2_t ) __builtin_neon_vqsubuv2si ( ( int32x2_t ) __a , (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI ,


<s> emit_move_insn ( mem , chain_value ) ; offset += size ; mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , SImode ) ) ; offset += <NUM_LIT> ; } else { rtx disp , chain ; chain = ix86_static_chain ( fndecl , true ) ; if ( REG_P ( chain ) ) { switch ( REGNO ( chain ) ) { case AX_REG : opcode = <NUM_LIT> ; break ; case CX_REG : opcode = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } } else opcode = <NUM_LIT> ; if ( need_endbr ) { mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , SImode ) ) ; offset += <NUM_LIT> ; } mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ; offset += <NUM_LIT> ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( <NUM_LIT> , QImode ) ) ; mem = adjust_address ( m_tramp , SImode ,


<s> int64_t ImmVal = CNode -> getSExtValue ( ) ; SDLoc DL ( N ) ; if ( ImmVal >= - <NUM_LIT> && ImmVal < <NUM_LIT> ) { Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } } return false


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo (


<s> MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned CmpOpc ; if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiOpc ; else if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiXOpc ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) ,

TII -> get ( BtOpc ) ) . addMBB ( target ) ;


<s> if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = <NUM_LIT> ; else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains = Subtarget . hasAVX2


<s> static __inline qword si_mpyhh ( qword a ,


<s> uint64_t SextImm = SignExtend64 ( Imm , MinSize ) ; SDValue SDImm = CurDAG -> getTargetConstant ( SextImm , dl , <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( SextImm ) ) return CurDAG -> getMachineNode (


<s> const unsigned Size = Ty . getScalarSizeInBits ( ) ; if ( ! mi_match ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_GAnd ( m_OneNonDBGUse ( m_GAShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShrAmt ) ) ) , m_ICst ( AndImm ) ) ) ) return false ; auto MaybeMask = static_cast < uint64_t > ( AndImm ) ; if ( MaybeMask & ( MaybeMask + <NUM_LIT> ) ) return false ; if ( static_cast < uint64_t > ( ShrAmt ) >= Size ) return false ; uint64_t Width = APInt ( Size , AndImm ) . countTrailingOnes ( ) ; if ( static_cast < uint64_t > ( ShrAmt ) + Width >= Size && ! Helper . getKnownBits ( ) -> signBitIsZero ( ShiftSrc ) ) return false ; MatchInfo = [ = ] ( MachineIRBuilder


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal ) ; setIndexedStoreAction ( im , VT . getSimpleVT ( )


<s> static SDValue insert256BitVector ( SDValue Result , SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , const SDLoc & dl ) { assert ( Vec . getValueType ( ) .


<s> if ( TARGET_EXPLICIT_RELOCS ) return false ; mips_split_const ( x , & x , & offset ) ; return global_got_operand ( x ,


<s> MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; LLVM_DEBUG ( dbgs ( )


<s> while ( insn ) { if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) { cfun -> machine -> asms_without_operands = <NUM_LIT> ; break ; } insn = NEXT_INSN (


<s> } if ( I . nodeVisited ( Term -> getSuccessor ( <NUM_LIT> ) ) ) { if ( isTopOfStack ( BB ) ) closeControlFlow ( BB ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( BB ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == BB && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; } closeControlFlow ( BB )


<s> EncodeAddrModeOpValues ( const MCInst & MI , unsigned OpIdx , unsigned & Reg , unsigned & Imm , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction &


<s> rtx words [ <NUM_LIT> ] ; split_double ( src , & words [ <NUM_LIT> ] , & words [ <NUM_LIT> ] ) ; emit_move_insn ( operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , words [ <NUM_LIT> ] ) ; emit_move_insn ( operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , words [ <NUM_LIT> ] ) ; } else if ( MEM_P ( src ) ) { rtx addr = XEXP ( src , <NUM_LIT> ) ; int reverse = ( refers_to_regno_p ( dregno , addr ) != <NUM_LIT> ) ; if ( GET_CODE ( addr ) == POST_INC ) { rtx mem ; rtx insn ; mem = change_address ( src , SImode , addr ) ; insn = emit_move_insn ( operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , mem ) ; if ( GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == POST_INC ) REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_INC , XEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> ) , REG_NOTES ( insn ) ) ; mem = copy_rtx ( mem ) ; insn = emit_move_insn ( operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , mem ) ; if ( GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == POST_INC ) REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_INC , XEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> ) , REG_NOTES ( insn ) ) ; } else { if ( side_effects_p ( addr ) ) fatal_insn ( <STR_LIT> , addr ) ; emit_move_insn ( operand_subword ( dest , reverse , TRUE , mode ) , change_address ( src , SImode , plus_constant ( Pmode , addr , reverse * UNITS_PER_WORD ) ) ) ; emit_move_insn ( operand_subword ( dest , ! reverse , TRUE , mode ) , change_address ( src , SImode , plus_constant ( Pmode , addr , ( ! reverse ) * UNITS_PER_WORD ) ) ) ; } } else internal_error (


<s> int GetFinalOffset ( ) { assert ( Start != INT_MIN ) ; return Start


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedGather ( Type * DataTy , MaybeAlign Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < VectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements (


<s> return ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT>


<s> if ( ! isIndirect ) return getSymbol ( GV ) ; MCSymbol * MCSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ?

MMIMachO . getHiddenGVStubEntry ( MCSym ) :


<s> case <STR_LIT> : { SDValue Ops [ ] = { ResourceDescriptorToi128 ( Op . getOperand ( <NUM_LIT> ) , DAG ) , Op . getOperand ( <NUM_LIT> ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , VT . getSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , <NUM_LIT> , VT , MMO ) ; } case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , ResourceDescriptorToi128 ( Op . getOperand ( <NUM_LIT> ) , DAG ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } } case <STR_LIT> : SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : { SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , ResourceDescriptorToi128 ( Op . getOperand ( <NUM_LIT> ) , DAG ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VT . getSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , sizeof ( Ops ) / sizeof ( Ops [ <NUM_LIT> ] ) , VT , MMO ) ; } default : break ; } } return SDValue (


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; } unsigned NZCV = <STR_LIT> ( CmpBBTailCC ) ; const MCInstrDesc & MCID = TII -> get ( Opc ) ; MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; if ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . isReg ( ) ) MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , MCID ) . add ( CmpMI -> getOperand ( FirstOp ) ) ; if ( isZBranch ) MIB . addImm ( <NUM_LIT> ) ; else MIB . add ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) ) ; MIB . addImm ( NZCV ) . addImm ( HeadCmpBBCC ) ; if ( isZBranch ) { bool isNZ = CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI ->


<s> if ( MRI . reg_nodbg_empty ( Reg ) ) continue ; auto LiveMask = getLiveLaneMask ( Reg , <ISA_LIT> , LIS , MRI ) ; if ( LiveMask . any ( ) ) LiveRegs [ Reg ] = LiveMask ; } return


<s> const int OldImm = ( int ) CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int NewImm = std :: abs ( OldImm + Correction ) ; if ( OldImm == <NUM_LIT> && ( ( Negative && Correction == <NUM_LIT> ) || ( ! Negative && Correction == - <NUM_LIT> ) ) ) { Opc = getComplementOpc ( Opc ) ; } return CmpInfo ( NewImm , Opc ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ; } ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; TOut . emitRRR ( <STR_LIT> , ATReg , <STR_LIT> , TReg , Inst . getLoc ( ) , STI ) ; TOut . emitRRR ( FirstShift , ATReg , SReg , ATReg , Inst . getLoc ( ) , STI ) ; TOut . emitRRR ( SecondShift , DReg , SReg , TReg , Inst . getLoc ( ) , STI ) ; TOut . emitRRR ( <STR_LIT> , DReg , DReg , ATReg , Inst . getLoc ( ) , STI ) ; return false ; } return


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl (


<s> static SDValue PerformHWLoopCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * ST ) { SDValue CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC -> getOpcode ( ) != <STR_LIT> && CC -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( CC -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Int = CC -> getOperand ( <NUM_LIT> ) ; unsigned IntOp = cast < ConstantSDNode > ( Int . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> ) return SDValue ( ) ; assert ( ( isa < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( CC -> getOperand ( <NUM_LIT> ) ) -> isOne ( ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SDValue Chain = N -> getOperand ( <NUM_LIT>


<s> std :: unique_ptr < TargetInstrInfo :: PipelinerLoopInfo > <ISA_LIT>InstrInfo :: analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const { MachineBasicBlock :: iterator I = LoopBB -> getFirstTerminator ( ) ; MachineBasicBlock * Preheader = * LoopBB -> pred_begin ( ) ; if ( Preheader == LoopBB ) Preheader = * std :: next ( LoopBB -> pred_begin ( ) ) ; MachineFunction * MF = Preheader -> getParent ( ) ; if ( I != LoopBB -> end ( ) && isBDNZ ( I -> getOpcode ( ) ) ) { SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Visited ; if ( MachineInstr * LoopInst = findLoopInstr ( * Preheader , Visited ) ) { Register LoopCountReg = LoopInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr * LoopCount = MRI . getUniqueVRegDef ( LoopCountReg ) ; return std :: make_unique < <ISA_LIT>PipelinerLoopInfo > ( LoopInst , & * I , LoopCount ) ; } } return nullptr


<s> assert ( Kind == Register && <STR_LIT>


<s> static void gr5_hazard_avoidance ( void ) { unsigned int last_reg = <NUM_LIT> ; bool last_insn_call = false ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN (


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( Kind == k_Immediate ) { addExpr ( Inst , getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg (


<s> static unsigned loongarch_save_libcall_count ( unsigned mask ) { for ( unsigned n = GP_REG_LAST ; n > GP_REG_FIRST ; n -- ) if ( BITSET_P ( mask , n ) ) return CALLEE_SAVED_REG_NUMBER


<s> return ( __m512 ) __builtin_ia32_rsqrt14ps512_mask ( ( __v16sf ) __A , (

__v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> return ( ( qword ) ( vec_mulo ( ( vec_short8 ) ( a ) , ( vec_short8


<s> SmallSet < BasicBlock * , <NUM_LIT> > LoopBlocks ; for ( auto * B : L -> blocks ( ) ) LoopBlocks . insert ( B ) ; SetVector < Instruction * > Worklist ( Insts . begin ( ) , Insts . end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < Worklist . size ( ) ; ++ i ) { Instruction * In = Worklist [ i ] ; for ( auto I = In -> op_begin ( ) , E = In -> op_end ( ) ; I != E ; ++ I ) { Instruction * OpI = dyn_cast < Instruction > ( I ) ; if ( ! OpI ) continue ; BasicBlock * PB = OpI ->


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCB . setLoc ( IDLoc ) ; const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; <ISA_LIT>MCChecker Check ( getContext ( ) , MII , getSTI ( ) , MCB , * RI ) ; bool CheckOk = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MII , getSTI ( ) , getContext ( ) , MCB , & Check ) ; if ( CheckOk


<s> static bool arm_scalar_mode_supported_p ( scalar_mode mode ) { if ( mode == HFmode ) return

( arm_fp16_format != ARM_FP16_FORMAT_NONE ) ;


<s> void <ISA_LIT>HazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == <NUM_LIT> ) LastMI = nullptr ; ScoreboardHazardRecognizer :: AdvanceCycle ( )


<s> if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum )

|| Memory . Alignment != <NUM_LIT> ) return false ;


<s> static bool isSafeOverflow ( Instruction * I ) { if ( isa < OverflowingBinaryOperator > ( I ) && I -> hasNoUnsignedWrap ( ) ) return true ; unsigned Opc = I -> getOpcode ( ) ; if ( Opc != Instruction :: Add && Opc != Instruction :: Sub ) return false ; if ( ! I -> hasOneUse ( ) || ! isa < ICmpInst > ( * I -> user_begin ( ) ) || ! isa < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) return false ; ConstantInt * OverflowConst = cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; bool NegImm = OverflowConst -> isNegative ( ) ; bool IsDecreasing = ( ( Opc == Instruction :: Sub ) && ! NegImm ) || ( ( Opc == Instruction :: Add ) && NegImm ) ; if ( ! IsDecreasing ) return false ; auto * CI = cast < ICmpInst > ( * I -> user_begin ( ) ) ; if ( CI -> isSigned ( ) || CI -> isEquality ( ) ) return false ; ConstantInt * ICmpConst = nullptr ; if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) ICmpConst = Const ; else if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) ICmpConst = Const ; else return false ; APInt Total = ICmpConst -> getValue ( ) . getBitWidth ( ) < <NUM_LIT> ? ICmpConst -> getValue ( ) . zext ( <NUM_LIT> ) : ICmpConst -> getValue ( ) ; Total += OverflowConst -> getValue ( ) . getBitWidth ( ) < <NUM_LIT> ? OverflowConst -> getValue ( ) . abs ( ) . zext ( <NUM_LIT> ) : OverflowConst -> getValue ( ) . abs ( ) ; APInt Max = APInt :: getAllOnesValue ( <ISA_LIT>CodeGenPrepare :: TypeSize ) ; if ( Total . getBitWidth ( ) > Max . getBitWidth ( ) ) { if ( Total . ugt ( Max . zext ( Total . getBitWidth ( ) )


<s> static Target The<ISA_LIT>Target64 ; return


<s> const std :: string FuncName = Func -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else if ( RC


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; unsigned FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL


<s> bool hasSoftFloat ( ) const { return


<s> __inline__ static unsigned long long sh_media_MSAD_UBQ ( unsigned long long mm , unsigned long long mn , unsigned long long mw ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ; return res


<s> unsigned AMDGPURegisterInfo :: getIndirectSubReg (


<s> void <ISA_LIT>TargetStreamer :: emitConstantPools ( ) { ConstantPools -> emitAll


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; return


<s> MachineBasicBlock * LoopHeader = LoopRep -> getHeader ( ) ; MachineBasicBlock * LoopLatch = LoopRep -> getLoopLatch ( ) ; if ( ! LoopHeader || ! LoopLatch ) return nullptr ; MachineInstr * BranchMI = getLoopendBlockBranchInstr ( LoopLatch ) ; if ( ! BranchMI || ! isUncondBranch ( BranchMI ) ) return nullptr ; MachineBasicBlock * DummyExitBlk = FuncRep -> CreateMachineBasicBlock ( ) ; FuncRep -> push_back ( DummyExitBlk ) ; SHOWNEWBLK ( DummyExitBlk , <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BranchMI << <STR_LIT> ; ) ; LLVMContext & Ctx = LoopHeader -> getParent ( ) -> getFunction ( ) . getContext ( ) ; Ctx . emitError ( <STR_LIT> ) ; return


<s> SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; NotSrc = DAG . getBitcast ( SrcVT , NotSrc ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , NotSrc ) , DAG . getConstant ( NotMask , DL , VT ) ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDLoc DL ( N ) ; APInt NotMask = APInt :: getLowBitsSet ( NumBits , NumElts ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( NotMask , DL , VT ) ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDValue LHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue RHS = Src . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; KnownBits KnownRHS = DAG . computeKnownBits ( RHS ) ; if ( KnownRHS . isConstant ( ) && KnownRHS


<s> static bool ShouldInstrument ( Function & F ) { return ! F . getReturnType ( ) ->


<s> if ( RxSBG . Rotate != <NUM_LIT> ) ShiftedIn = ( ( ShiftedIn << RxSBG . Rotate ) | ( ShiftedIn >> ( <NUM_LIT> - RxSBG . Rotate ) ) ) ; return ( ShiftedIn & RxSBG . Mask


<s> if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return Val > - <NUM_LIT> && Val < <NUM_LIT> ; } return false


<s> return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT>


<s> uint32_t Prop2 = LS2 . properties ( ) ; return evaluateCMPrp ( Cmp , R1 , Prop2 , Inputs , Result ) ; } APInt A ; bool IsTrue = true , IsFalse = true ; for ( unsigned i = <NUM_LIT> ; i < LS2 . size ( ) ; ++ i ) { bool Res ; bool Computed = constToInt ( LS2 . Values [ i ] , A ) && evaluateCMPri ( Cmp , R1 , A ,


<s> else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onRShift ( ) ; else if ( Name . equals_lower ( <STR_LIT> ) ) SM . onXor ( ) ; else if ( Name . equals_lower ( <STR_LIT>


<s> } else if ( Symbol -> isInSection ( ) && ! Symbol -> isVariable ( ) ) { Index = Symbol -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Value += Writer -> getSymbolAddress ( * Symbol , Layout ) ; if ( IsPCRel ) Value -= FixupAddress + ( <NUM_LIT> << Log2Size ) ; } else if ( Symbol -> isVariable ( ) ) { const MCExpr * Value = Symbol -> getVariableValue ( ) ; int64_t Res ; bool isAbs = Value -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ; if ( isAbs ) { FixedValue = Res ; return ; } else { report_fatal_error ( <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> , false ) ; } } else { report_fatal_error ( <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> , false ) ; } MCSymbolRefExpr :: VariantKind Modifier = Target . getSymA ( ) -> getKind ( ) ; if ( IsPCRel ) { if ( IsRIPRel ) { if ( Modifier == MCSymbolRefExpr :: VK_GOTPCREL ) { if ( unsigned ( Fixup . getKind ( ) ) == <STR_LIT> ) Type = MachO :: <ISA_LIT>_64_RELOC_GOT_LOAD ; else Type = MachO :: <ISA_LIT>_64_RELOC_GOT ; } else if ( Modifier == MCSymbolRefExpr :: VK_TLVP ) { Type = MachO :: <ISA_LIT>_64_RELOC_TLV ; } else if ( Modifier != MCSymbolRefExpr :: VK_None ) { report_fatal_error ( <STR_LIT> , false ) ; } else { Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED ; switch ( - ( Target . getConstant ( ) + ( <NUM_LIT> << Log2Size ) ) ) { case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_1 ; break ; case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_2 ; break ; case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_4 ; break ; } } } else { if ( Modifier != MCSymbolRefExpr :: VK_None ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; Type = MachO :: <ISA_LIT>_64_RELOC_BRANCH ; } } else { if ( Modifier == MCSymbolRefExpr :: VK_GOT ) { Type = MachO :: <ISA_LIT>_64_RELOC_GOT ; } else if ( Modifier == MCSymbolRefExpr :: VK_GOTPCREL ) { Type = MachO :: <ISA_LIT>_64_RELOC_GOT ; IsPCRel = <NUM_LIT> ; } else if ( Modifier == MCSymbolRefExpr :: VK_TLVP


<s> bool Filler :: searchSuccBBs ( MachineBasicBlock & MBB , Iter Slot ) const { if ( DisableSuccBBSearch ) return false ; MachineBasicBlock * SuccBB = selectSuccBB ( MBB ) ; if ( ! SuccBB ) return false ; RegDefsUses RegDU ( TM ) ; bool HasMultipleSuccs = false ; BB2BrMap BrMap ; std :: unique_ptr < InspectMemInstr > IM ; Iter Filler ; for ( MachineBasicBlock :: pred_iterator PI = SuccBB -> pred_begin ( ) , PE = SuccBB -> pred_end ( ) ; PI != PE ; ++ PI ) if (

! examinePred ( * * PI , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ;


<s> static bool or1k_strict_argument_naming ( cumulative_args_t


<s> return expandLoadImm ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadImm ( Inst , false , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressImm ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst , true , IDLoc , Instructions ) ; case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst ,


<s> rtx tmp ; model = SYMBOL_REF_TLS_MODEL ( symbol ) ; if ( model ) tmp = legitimize_tls_address ( symbol , model , true ) ; else tmp = legitimize_pe_coff_symbol ( symbol , true ) ; if ( tmp ) { tmp = force_operand ( tmp , NULL ) ; tmp = expand_simple_binop ( Pmode , PLUS , tmp , addend , op0 , <NUM_LIT> , OPTAB_DIRECT ) ; if ( tmp == op0 ) return ; op1 = convert_to_mode ( mode , tmp , <NUM_LIT> ) ; } } if ( ( flag_pic || MACHOPIC_INDIRECT ) && symbolic_operand ( op1 , mode ) ) { if ( TARGET_MACHO && ! TARGET_64BIT ) { if ( MACHOPIC_INDIRECT ) { rtx temp = ( op0 && REG_P ( op0 ) && mode == Pmode ) ? op0 : gen_reg_rtx ( Pmode ) ; op1 = machopic_indirect_data_reference ( op1 , temp ) ; if ( MACHOPIC_PURE ) op1 = machopic_legitimize_pic_address ( op1 , mode , temp == op1 ? <NUM_LIT> : temp ) ; } if ( op0 != op1 && GET_CODE ( op0 ) != MEM ) { rtx insn = gen_rtx_SET ( op0 , op1 ) ; emit_insn ( insn ) ; return ; } if ( GET_CODE ( op0 ) == MEM ) op1 = force_reg ( Pmode , op1 ) ; else { rtx temp = op0 ; if ( GET_CODE ( temp ) != REG ) temp = gen_reg_rtx ( Pmode ) ; temp = legitimize_pic_address ( op1 , temp ) ; if ( temp == op0 ) return ; op1 = temp ; } } else { if ( MEM_P ( op0 ) ) op1 = force_reg ( mode , op1 ) ; else if ( ! ( TARGET_64BIT && x86_64_movabs_operand ( op1 , DImode ) ) ) { rtx reg = can_create_pseudo_p ( ) ? NULL_RTX : op0 ; op1 = legitimize_pic_address ( op1 , reg ) ; if ( op0 == op1 ) return ; op1 = convert_to_mode ( mode , op1 , <NUM_LIT> ) ; } } } else { if ( MEM_P ( op0 ) && ( PUSH_ROUNDING ( GET_MODE_SIZE ( mode ) ) != GET_MODE_SIZE ( mode ) || ! push_operand ( op0 , mode ) ) && MEM_P ( op1


<s> void aarch64_asm_output_labelref ( FILE * f , const char * name ) { asm_fprintf ( f ,


<s> <ISA_LIT>ELFFrameLowering :: <ISA_LIT>ELFFrameLowering ( ) : <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) ,

false ) , RegSpillOffsets ( <NUM_LIT> ) {


<s> bool Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; if ( Res ) ++


<s> if ( align > max_common_align ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , align / BITS_PER_UNIT , name , max_common_align / BITS_PER_UNIT ) ; align = max_common_align ; } switch_to_section ( bss_section ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , MAX


<s> PM . add ( createUnpackMachineBundlesPass ( ) ) ; } PM . add ( create<ISA_LIT>ConstantIslandPass ( ) ) ; return


<s> bool isSImm12 ( ) const { return ( isConstantImm ( ) && isInt < <NUM_LIT> > ( getConstantImm


<s> unsigned getNumFixupKinds ( ) const override { return


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue N0 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; bool UseVPTERNLOG = ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) || Subtarget . hasVLX ( ) ; if ( ! ( Subtarget . hasXOP ( ) || UseVPTERNLOG || ! N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N1 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) return SDValue ( ) ; APInt UndefElts0 , UndefElts1 ; SmallVector < APInt , <NUM_LIT> > EltBits0 , EltBits1 ; if ( ! getTargetConstantBitsFromNode ( N0 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , UndefElts0 , EltBits0 , false , false ) ) return SDValue ( ) ; if ( ! getTargetConstantBitsFromNode ( N1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , UndefElts1 , EltBits1 , false , false ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> , e = EltBits0 . size ( ) ; i != e ; ++ i ) { if ( UndefElts0 [ i ] || UndefElts1 [ i ] ) return SDValue ( ) ; if ( EltBits0 [ i ] != ~ EltBits1 [ i ] ) return SDValue ( ) ; } SDLoc DL ( N ) ; if ( UseVPTERNLOG ) { SDValue A = DAG . getBitcast ( VT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue B = DAG . getBitcast ( VT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue C = DAG . getBitcast ( VT , N1 . getOperand ( <NUM_LIT> ) ) ; SDValue Imm = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , A , B , C , Imm ) ; } SDValue X = N -> getOperand ( <NUM_LIT>


<s> Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; ldi :: fixup ( Size , Fixup , Value


<s> DCI . CombineTo ( Root . getNode ( ) , getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , SDLoc ( Root ) ) ) ; return true ; } int MaskSize = Mask . size ( ) ; bool UseInput0 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return <NUM_LIT> <= Idx && Idx < MaskSize ; } ) ; bool UseInput1 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return MaskSize <= Idx ; } ) ; if ( UseInput0 && UseInput1 ) return false ; else if ( UseInput1 ) { std :: swap ( Input0 , Input1 ) ; ShuffleVectorSDNode :: commuteMask ( Mask ) ; } assert ( Input0 && <STR_LIT> ) ; HasVariableMask |= isTargetShuffleVariableMask ( Op . getOpcode ( ) ) ; if ( Op -> isOnlyUserOf ( Input0 . getNode ( ) ) && combine<ISA_LIT>ShufflesRecursively ( Input0 , Root , Mask , Depth + <NUM_LIT> , HasVariableMask , DAG , DCI , Subtarget ) ) return true ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > <NUM_LIT> && canWidenShuffleElements ( Mask , WidenedMask ) ) { Mask = std :: move ( WidenedMask


<s> static bool mips_function_has_gp_insn ( void ) { if ( ! cfun -> machine -> has_gp_insn_p ) { rtx insn ; push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && ( get_attr_got ( insn ) != GOT_UNSET || small_data_pattern ( PATTERN ( insn ) , VOIDmode ) ) ) break ; pop_topmost_sequence ( ) ; cfun -> machine -> has_gp_insn_p = ( insn != <NUM_LIT> ) ; } return cfun -> machine


<s> else if ( Subtarget -> isPICStyleGOT ( ) ) OpFlag = <STR_LIT> ; else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; Result . getNode ( ) -> setTrapInfo ( Op -> getTrapInfo ( ) ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT>


<s> else if ( Info . isStrided ( ) && std :: abs ( Info . getStride ( ) ) == <NUM_LIT> ) { if ( Info . isMasked ( ) ) Cost = getMaskedMemoryOpCost ( Opcode , Src , Alignment


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: createReg ( Reg


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; assert ( Size > <NUM_LIT> &&


<s> LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { SDValue ResNode ; ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; const Constant * C = N -> getConstVal ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDValue CPHi = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; CP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) , N -> getOffset ( ) , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load , Lo ) ; } return ResNode


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT>


<s> void <ISA_LIT>PostRASchedStrategy :: advanceTo ( MachineBasicBlock :: iterator NextBegin ) { MachineBasicBlock :: iterator LastEmittedMI = HazardRec -> getLastEmittedMI ( ) ; MachineBasicBlock :: iterator I = ( ( LastEmittedMI != nullptr && LastEmittedMI -> getParent ( ) ==

MBB ) ? std :: next ( LastEmittedMI ) : MBB -> begin ( ) ) ;


<s> while ( I1 != List . end ( ) ) { MachineInstr & First = * * I1 ; auto I2 = std :: next ( I1 ) ; while ( I2 != List . end ( ) ) { MachineInstr & Last = * * I2 ; int64_t AddrDispShift ; assert ( calcInstrDist ( First , Last ) > <NUM_LIT> && <STR_LIT> ) ; if ( ! isReplaceable ( First , Last , AddrDispShift ) ) { ++ I2 ; continue ; } Register FirstVReg = First . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LastVReg = Last . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto UI = MRI -> use_begin ( LastVReg ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; if ( MI . isDebugValue ( ) ) { replaceDebugValue ( MI , FirstVReg , AddrDispShift ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ; MO . setReg ( FirstVReg ) ; MachineOperand & Op = MI . getOperand ( MemOpNo + <STR_LIT> ) ; if ( Op . isImm ( ) ) Op . setImm ( Op . getImm ( ) + AddrDispShift ) ; else if ( ! Op . isJTI ( ) ) Op . setOffset

( Op . getOffset ( ) + AddrDispShift ) ;


<s> return ( __mmask16 ) __builtin_ia32_cmpw256_mask ( ( __v16hi ) __X , ( __v16hi )


<s> unsigned numWords ( ) const { assert ( ! ( NumWritten & <NUM_LIT> ) && <STR_LIT> ) ; return NumWritten >>


<s> DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t


<s> if ( getStreamer ( ) . getCurrentSection ( ) . first -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; return false


<s> std :: vector < std :: string > push_r6 ( ) { return D ( <STR_LIT>


<s> static bool isFirstMacroFusibleInst ( const MCInst & Inst , const MCInstrInfo & MCII ) { if ( isRIPRelative ( Inst , MCII ) ) return false ; <STR_LIT> FIK = <STR_LIT> ( Inst . getOpcode ( ) ) ; return FIK != <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned VectorSize = TRI -> getSpillSize ( <STR_LIT> ) ; assert ( isPowerOf2_32 ( VectorSize ) ) ; if ( Offset & ( VectorSize - <NUM_LIT> ) ) return false ; return isInt < <NUM_LIT> > ( Offset >> Log2_32 ( VectorSize ) ) ; } case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT>


<s> const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , DL , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( VaListSize , DL , <STR_LIT> ) , <NUM_LIT> , false , false ,

false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2SF ] ; if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return


<s> continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag (


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) )


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> :


<s> Value * <ISA_LIT>IREmitter :: visitVSHLI ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>EarlyIfConversion :: mergeBlocks ( MachineBasicBlock * PredB , MachineBasicBlock * SuccB ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( PredB ) << <STR_LIT> << PrintMB ( SuccB ) << <STR_LIT> ) ; bool TermOk = hasUncondBranch ( SuccB ) ; eliminatePhis ( SuccB ) ; TII -> RemoveBranch ( *


<s> return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( Reg1IsKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( Reg2IsKill ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( ( ME + <NUM_LIT>


<s> tree attr ; gcc_assert ( type ) ; attr = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { user_pcs = arm_pcs_from_attribute ( TREE_VALUE ( attr ) ) ; user_convention = true ; } if ( TARGET_AAPCS_BASED ) { bool base_rules = stdarg_p ( type ) ; if ( user_convention ) { if ( user_pcs > ARM_PCS_AAPCS_LOCAL ) sorry ( <STR_LIT> ) ; else if ( base_rules && user_pcs != ARM_PCS_AAPCS ) error ( <STR_LIT> ) ; } if ( base_rules ) return ARM_PCS_AAPCS ; else if ( user_convention ) return user_pcs ; else if ( decl && flag_unit_at_a_time ) { cgraph_local_info * i = cgraph_node :: local_info ( CONST_CAST_TREE ( decl ) ) ; if ( i && i -> local ) return ARM_PCS_AAPCS_LOCAL ; } } else if ( user_convention && user_pcs != arm_pcs_default


<s> } else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) { BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) ) . addReg ( TRI -> getSubReg ( SrcReg , SubRegIdx + I ) ) . addReg ( Base ) . addMemOperand ( * ( MBBI -> memoperands_begin ( ) ) ) ; if ( I != NF - <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Base ) . addReg ( Base ) . addReg ( VL ) ; } MBBI -> eraseFromParent ( ) ; return true


<s> if ( ! isSysReg ( ) ) return false ; bool IsKnownRegister ; auto Mapper = <STR_LIT> ( getSysRegFeatureBits ( ) ) ; Mapper . fromString ( getSysReg ( )


<s> } else CS . setFrameIdx ( INT32_MAX ) ; } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI ) ; MFI -> setRestoreGPRRegs ( LowGPR , HighGPR , LowOffset ) ; ProcessCSI ( Spills ) ; MFI -> setSpillGPRRegs ( LowGPR , HighGPR , LowOffset ) ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ; int FrameIdx = MFFrame . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; } return


<s> for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i ++ ) Out . push_back ( Mask [ i ] + LowOffset ) ; for ( unsigned i = <NUM_LIT> ; i < Mask . size ( ) ; i

++ ) Out . push_back ( Mask [ i ] + HighOffset + NumOfElm ) ;


<s> calculateWinCXXEHStateNumbers ( & F , FuncInfo ) ; addStateStoresToFunclet ( RegNode , FuncInfo , F , - <NUM_LIT> ) ; int RegNodeEscapeIndex = escapeRegNode ( F ) ; FuncInfo . EHRegNodeEscapeIndex =


<s> std :: tie ( Lo , Hi ) = splitVector ( Val , SL , LoVT , HiVT , DAG ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , LoMemVT . getStoreSize ( ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , BaseAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT

, HiAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> int regno_inc = - <NUM_LIT> ; if ( GET_CODE ( destreg ) == POST_INC ) increment += nregs * <NUM_LIT> ; if ( GET_CODE ( destreg ) == POST_INC || GET_CODE ( destreg ) == PLUS ) destreg = XEXP ( destreg , <NUM_LIT> ) ; CRIS_ASSERT ( REG_P ( destreg ) ) ; if ( nregs == <NUM_LIT> ) { rtx mov = gen_rtx_SET ( VOIDmode , dest , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; if ( increment == <NUM_LIT> ) { insn = emit_insn ( mov ) ; if ( frame_related ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return insn ; } vec = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( vec , <NUM_LIT> ) = mov ; RTVEC_ELT ( vec , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , destreg , plus_constant ( destreg , increment ) ) ; if ( frame_related ) { RTX_FRAME_RELATED_P ( mov ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( RTVEC_ELT ( vec , <NUM_LIT> ) ) = <NUM_LIT> ; } } else { vec = rtvec_alloc ( nregs + ( increment != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; RTVEC_ELT ( vec , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , replace_equiv_address ( dest , plus_constant ( destreg , increment ) ) , gen_rtx_REG ( SImode , regno ) ) ; regno += regno_inc


<s> Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc =


<s> if ( BoundCtrl == <NUM_LIT> ) { BoundCtrl = <NUM_LIT> ; return


<s> static void nvptx_goacc_reduction_fini ( gcall * call , offload_attrs * oa ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { for ( int shfl = PTX_WARP_SIZE / <NUM_LIT> ; shfl > <NUM_LIT> ; shfl = shfl >> <NUM_LIT> ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ; } } else { tree accum = NULL_TREE ; if ( level == GOMP_DIM_WORKER || level == GOMP_DIM_VECTOR ) { tree offset = gimple_call_arg ( call , <NUM_LIT> ) ; tree call = nvptx_get_shared_red_addr ( TREE_TYPE ( var ) , offset , level == GOMP_DIM_VECTOR ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; accum = ptr ; } else if ( integer_zerop ( ref_to_res ) ) r = var ; else accum = ref_to_res ; if ( accum


<s> Register Reg = Op . getReg ( ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return true ; return false


<s> const <ISA_LIT>TargetLowering * getTargetLowering


<s> return DecodeUImmWithOffsetAndScale < Bits , Offset , <NUM_LIT> >


<s> auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( HII . isValidOffset ( Opc , RealOffset ) ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; } const Function * F = MF . getFunction ( ) ; dbgs ( ) << <STR_LIT> ; if ( F ) dbgs ( ) << F -> getName ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MB . getNumber ( ) << <STR_LIT> << MI ; llvm_unreachable ( <STR_LIT> )


<s> unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; errInfo . setError ( <STR_LIT> , BadR ) ; addErrInfo ( errInfo ) ; return false ; } if ( ! isPredicateRegister ( R ) && Defs [ R ] . size ( ) > <NUM_LIT> ) { PredSet & PM = Defs [ R ] ; if ( PM . count ( Unconditional ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; errInfo . setError ( <STR_LIT> , BadR ) ; addErrInfo ( errInfo ) ; return false ; } for ( const auto & J : PM ) { PredSense P = J ; if ( PM . count ( P ) > <NUM_LIT> ) { errInfo . setError ( <STR_LIT> , R ) ; addErrInfo ( errInfo ) ; return false ; } P . second = ! P . second ; if ( PM . count ( P ) && PM . size ( ) > <NUM_LIT> ) { errInfo . setError ( <STR_LIT> , R ) ; addErrInfo ( errInfo ) ; return false ; } } } } for ( const auto & I : CurDefs ) { unsigned R = I ; if ( ! Uses . count ( R ) ) { errInfo . setWarning (


<s> void RecordRelocation ( MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , bool & IsPCRel , uint64_t & FixedValue ) override { assert ( !


<s> case RX_BUILTIN_MVFACMI : return rx_expand_int_builtin_0_arg ( target , gen_mvfacmi ) ; case RX_BUILTIN_MVTACHI : return rx_expand_void_builtin_1_arg ( op , gen_mvtachi , true ) ; case RX_BUILTIN_MVTACLO : return rx_expand_void_builtin_1_arg ( op , gen_mvtaclo , true ) ; case RX_BUILTIN_RMPA : if ( rx_allow_string_insns ) emit_insn ( gen_rmpa ( ) ) ; else error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; case RX_BUILTIN_MVFC : return rx_expand_builtin_mvfc ( arg , target ) ; case RX_BUILTIN_MVTC : return rx_expand_builtin_mvtc ( exp ) ; case RX_BUILTIN_MVTIPL : return rx_expand_builtin_mvtipl ( op ) ; case RX_BUILTIN_RACW : return rx_expand_void_builtin_1_arg ( op , gen_racw , false ) ; case RX_BUILTIN_ROUND : return rx_expand_builtin_round ( op , target ) ; case RX_BUILTIN_REVW : return rx_expand_int_builtin_1_arg ( op , target , gen_revw , false ) ; case RX_BUILTIN_WAIT : emit_insn ( gen_wait ( ) ) ; return NULL_RTX ; default : internal_error ( <STR_LIT> )


<s> case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : assert ( MI -> getNumOperands ( ) >= <NUM_LIT> ) ; const MachineOperand & Reg = MI -> getOperand ( <NUM_LIT> ) ; assert ( Reg . isReg ( ) && <STR_LIT> ) ; assert ( Reg . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Reg . getReg ( ) ) ; const MachineOperand & RegOrImm = MI -> getOperand ( <NUM_LIT> ) ; if ( RegOrImm . isImm ( ) ) break ; assert ( RegOrImm . isReg ( ) && <STR_LIT> ) ; assert ( RegOrImm . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( RegOrImm . getReg


<s> MachineBasicBlock :: iterator MBBI ( MI ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( hasCalls ) { TRI -> addOffset ( MBB , MBBI , DL , Dest , Src , Offset ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Src ) ; } ++ II ; MI -> eraseFromParent ( ) ; --


<s> if ( startswith ( format , <STR_LIT> ) ) { format += <NUM_LIT> ; return acle_svprfop ; } gcc_unreachable ( ) ; } if ( ch == 's' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return scalar_types [ type_suffixes [ suffix ] . vector_type ] ; } if ( ch == 't' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; vector_type_index vector_type = type_suffixes [ suffix ] . vector_type ; unsigned int num_vectors = instance . vectors_per_tuple ( ) ; return acle_vector_types [ num_vectors - <NUM_LIT> ] [ vector_type ] ; } if ( ch == 'v' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; return acle_vector_types [ <NUM_LIT> ] [ type_suffixes


<s> static NodePair node_pair ( GepNode * N1 , GepNode * N2 ) { uintptr_t P1 = uintptr_t ( N1 ) , P2 = uintptr_t ( N2 ) ; if ( P1 <= P2 ) return std :: make_pair ( N1 , N2 ) ; return std :: make_pair ( N2 ,


<s> Value * <ISA_LIT>IREmitter :: visitVZIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> } Init -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Init ) ; } else BuildMov ( LoLoop . Preheader -> instr_back ( ) , DestReg , Copy . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Reduce . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Reduce . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reduce ) ; MachineInstr & VPSEL = Reduction -> VPSEL ; if ( VPSEL . getOperand ( <NUM_LIT> ) . getReg ( ) != DestReg ) BuildMov ( VPSEL , VPSEL . getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Copy << <STR_LIT> << VPSEL << <STR_LIT> ) ; Copy . eraseFromParent ( ) ; VPSEL . eraseFromParent (


<s> if ( ! VT . isInteger ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return nullptr ; RxSBGOperands RISBG ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) ) ; unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return nullptr ; if ( Count == <NUM_LIT> ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return nullptr ; if ( VT == <STR_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) { auto * MaskN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( MaskN -> getZExtValue ( ) != RISBG . Mask ) { SDValue NewMask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewMask ) ; return SelectCode ( N ) ; } return nullptr ; } } if ( RISBG . Rotate == <NUM_LIT> && ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> ) ) { unsigned OpCode = ( RISBG . Mask == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( VT == <STR_LIT> ) { if ( Subtarget -> hasHighWord ( ) ) OpCode = ( RISBG


<s> static inline bool isAssignTypeInstr ( const Instruction * I ) { return isa < IntrinsicInst > ( I ) && cast < IntrinsicInst > ( I


<s> __builtin_mve_vst1q_uv4si ( ( __builtin_neon_si * )


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeRROperand ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , STI , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; if ( unsigned RegNum = MO2 . getReg ( ) ) { O << <STR_LIT> ; printRegName ( O , RegNum


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; return


<s> } ; const uint16_t * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( CC ) ; if ( SwapArgs ) std :: swap ( LHS


<s> void applyFixup ( MCFixup const & , char * , unsigned , uint64_t , bool )


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { OutStreamer . EmitRawText ( StringRef ( <STR_LIT>


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { cerr << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( )


<s> void <ISA_LIT>MachOTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ; LSDASection = getMachOSection ( <STR_LIT> , <STR_LIT> , <NUM_LIT> , SectionKind


<s> return new <ISA_LIT>Z80ELFStreamer ( S


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_NOREORDER ; MCA . setELFHeaderEFlags ( Flags


<s> if ( ! warned && warn_psabi ) { const char * url = CHANGES_ROOT_URL <STR_LIT> ; warned = true ; inform ( input_location , <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url ) ; } } else return MIN (


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = getTargetVShiftUniformOpcode ( Opcode , false ) ; unsigned <ISA_LIT>OpcV = getTargetVShiftUniformOpcode ( Opcode , true ) ; Amt = peekThroughEXTRACT_SUBVECTORs ( Amt ) ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) { if ( SDValue BaseShAmt = IsSplatValue ( VT , Amt , dl , DAG , Subtarget , Opcode ) ) { MVT EltVT = VT . getVectorElementType ( ) ; assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt

= DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ;


<s> const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_ADDR : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL : return <STR_LIT> ; case VK_<ISA_LIT>_GOT : return <STR_LIT> ; case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TPOFF : return <STR_LIT> ; case VK_<ISA_LIT>_TLSGD : return <STR_LIT>


<s> if ( const RegisterBank * RB = RCOrRB . dyn_cast < const RegisterBank * > ( ) ) return getRegClassForTypeOnBank ( MRI . getType ( MO .


<s> unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned oi = i == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( )


<s> bool <ISA_LIT>LowOverheadLoops :: ProcessLoop ( MachineLoop * ML ) { bool Changed = false ; for ( auto I = ML -> begin ( ) , E = ML -> end ( ) ; I != E ; ++ I ) Changed |= ProcessLoop ( * I ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * Preheader ) << <STR_LIT> ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true , true ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * Preheader ) << <STR_LIT> ; for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; } ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = LoLoop . Dec = & MI ; else if ( isLoopStart ( MI ) ) LoLoop .


<s> Inst . addOperand ( Opnd0 ) ; Inst . addOperand ( Opnd1 ) ; if ( Opnd2 . isValid ( ) ) Inst . addOperand


<s> return __builtin_aarch64_smax_nanpv4sf ( a ,


<s> if ( ! Op . isExpr ( ) ) return false ; const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( Op . getExpr ( ) ) ; return Ref && Ref -> getKind ( ) == MCSymbolRefExpr ::


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG


<s> void CFGStructurizer < PassT > :: reversePredicateSetter ( typename BlockT :: iterator I ) { while ( I -- ) { if ( I -> getOpcode ( ) == AMDGPU :: PRED_X ) { switch ( static_cast < MachineInstr * > ( I ) -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { case OPCODE_IS_ZERO_INT : static_cast < MachineInstr * > ( I ) -> getOperand ( <NUM_LIT> ) . setImm ( OPCODE_IS_NOT_ZERO_INT ) ; return ; case OPCODE_IS_NOT_ZERO_INT : static_cast < MachineInstr * > ( I ) -> getOperand ( <NUM_LIT> ) . setImm ( OPCODE_IS_ZERO_INT ) ; return ; case OPCODE_IS_ZERO : static_cast < MachineInstr * > ( I ) -> getOperand (

<NUM_LIT> ) . setImm ( OPCODE_IS_NOT_ZERO ) ;


<s> ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; } break ; case V32HImode : if ( TARGET_AVX512BW ) { tmp = gen_reg_rtx ( V16HImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v32hi ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v32hi ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; } break ; case V64QImode : if ( TARGET_AVX512BW ) { tmp = gen_reg_rtx ( V32QImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v64qi ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v64qi ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; } break ; case V16SFmode : tmp = gen_reg_rtx ( V8SFmode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v16sf ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v16sf ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V8DFmode : tmp = gen_reg_rtx ( V4DFmode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v8df ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v8df ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V16SImode : tmp = gen_reg_rtx ( V8SImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v16si ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v16si ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V8DImode : tmp = gen_reg_rtx ( V4DImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_vec_extract_lo_v8di ( tmp , vec ) ) ; else emit_insn ( gen_vec_extract_hi_v8di ( tmp , vec ) ) ; ix86_expand_vector_extract ( false , target , tmp , elt & <NUM_LIT> ) ; return ; case V8QImode : default : break ; } if ( use_vec_extr ) { tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , GEN_INT ( elt ) ) ) ; tmp = gen_rtx_VEC_SELECT ( inner_mode , vec , tmp ) ; if ( inner_mode == QImode || inner_mode == HImode ) { tmp = gen_rtx_ZERO_EXTEND ( SImode


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * ) const { return


<s> std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> if ( C . front ( ) != '{' || C . back ( ) != '}' ) return std :: make_pair ( false , false ) ; StringRef :: const_iterator I , B = C . begin ( ) + <NUM_LIT> , E = C . end ( ) - <NUM_LIT> ; I = std :: find_if ( B , E , isdigit ) ; Prefix = StringRef ( B , I - B ) ; if ( I == E ) return std


<s> int <ISA_LIT>CFGStructurizer :: improveSimpleJumpintoIf ( MachineBasicBlock * HeadMBB , MachineBasicBlock * TrueMBB , MachineBasicBlock * FalseMBB , MachineBasicBlock * * LandMBBPtr ) { bool MigrateTrue = false ; bool MigrateFalse = false ; MachineBasicBlock * LandBlk = * LandMBBPtr ; assert ( ( ! TrueMBB || TrueMBB -> succ_size ( ) <= <NUM_LIT> ) && ( ! FalseMBB || FalseMBB -> succ_size ( ) <= <NUM_LIT> ) ) ; if ( TrueMBB == FalseMBB ) return <NUM_LIT> ; MigrateTrue = needMigrateBlock ( TrueMBB ) ; MigrateFalse = needMigrateBlock ( FalseMBB ) ; if ( ! MigrateTrue && ! MigrateFalse ) return <NUM_LIT> ; if ( ! MigrateTrue && TrueMBB && TrueMBB -> pred_size ( ) > <NUM_LIT> ) MigrateTrue = true ; if ( ! MigrateFalse && FalseMBB && FalseMBB -> pred_size ( ) > <NUM_LIT> ) MigrateFalse = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; showImproveSimpleJumpintoIf ( HeadMBB , TrueMBB , FalseMBB , LandBlk , <NUM_LIT> ) ; ) ; const TargetRegisterClass * I32RC = TRI -> getCFGStructurizerRegClass ( <STR_LIT> ) ; if ( ! MigrateTrue || ! MigrateFalse ) { return <NUM_LIT> ; } int NumNewBlk = <NUM_LIT> ; bool LandBlkHasOtherPred = ( LandBlk -> pred_size ( ) > <NUM_LIT> ) ; MachineBasicBlock :: iterator I = insertInstrBefore ( LandBlk , <STR_LIT> ) ; if ( LandBlkHasOtherPred ) { report_fatal_error ( <STR_LIT> ) ; unsigned CmpResReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; report_fatal_error ( <STR_LIT> ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , CmpResReg , DebugLoc ( ) ) ; } unsigned InitReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , InitReg , DebugLoc ( ) ) ; if ( MigrateTrue ) { migrateInstruction ( TrueMBB , LandBlk , I ) ; report_fatal_error ( <STR_LIT> ) ; } insertInstrBefore ( I , <STR_LIT> ) ; if ( MigrateFalse ) { migrateInstruction ( FalseMBB , LandBlk , I ) ; report_fatal_error ( <STR_LIT> ) ; } if ( LandBlkHasOtherPred ) { insertInstrBefore ( I , <STR_LIT>