<s> } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ; return BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState ( KillSrc ) | getUndefRegState ( UndefSrc ) ) . addImm ( <NUM_LIT> - Size ) . addImm ( <NUM_LIT>


<s> Changed |= coalesceSegments ( Condsets , CoalUpd ) ; std :: set < unsigned > KillUpd ; for ( MachineInstr * MI : Condsets ) for ( MachineOperand & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) ) if ( ! CoalUpd . count ( Op . getReg ( ) ) ) KillUpd . insert ( Op . getReg ( ) ) ; updateLiveness ( KillUpd , false , true , false ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( ) ) ) ; for ( MachineInstr * MI : Condsets ) Changed |= split ( * MI , PredUpd ) ; Condsets . clear ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( )


<s> RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } insn = frame_insn ( insn ) ; for ( regno = start_reg , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } if ( arc_must_save_return_addr ( cfun ) ) { emit_insn ( gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_MEM ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , reg_size ) ) ) ) ; } for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( ( gmask & ( <NUM_LIT> <<


<s> Register SOffset ; int64_t Offset = <NUM_LIT> ; if ( ! selectMUBUFOffsetImpl ( Root , RSrcReg , SOffset , Offset ) ) return { } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RSrcReg ) ; } , [ = ]


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && ( Op . getConstantOperandVal ( <NUM_LIT> ) & <NUM_LIT> ) == <NUM_LIT> ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp > <NUM_LIT> ) return <NUM_LIT> ; } break ; } case <STR_LIT> : if ( Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) >

Subtarget . getXLen ( ) ) return <NUM_LIT> ;


<s> MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI -> addRegisterKilled ( SrcRegS , TRI , true ) ; } DEBUG ( dbgs ( ) << <STR_LIT>


<s> return ( FB [ <STR_LIT> ] && Reg == <STR_LIT> ) || ( FB [ <STR_LIT> ]


<s> void <ISA_LIT>InstPrinter :: printAddSubImmLSL0Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Imm12Op = MI -> getOperand ( OpNum ) ; if ( Imm12Op . isImm ( ) ) { int64_t Imm12 = Imm12Op . getImm ( ) ; assert ( Imm12 >= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << Imm12 ; } else


<s> bool <ISA_LIT>RegisterInfo :: opCanUseInlineConstant ( unsigned OpType ) const { if ( OpType >= <STR_LIT> && OpType <= <STR_LIT> ) return


<s> static bool isUndefInRange ( ArrayRef < int > Mask ,


<s> static void doAtomicBinOpExpansion ( const <ISA_LIT>InstrInfo * TII , MachineInstr & MI , DebugLoc DL , MachineBasicBlock * ThisMBB , MachineBasicBlock * LoopMBB , MachineBasicBlock * DoneMBB , AtomicRMWInst :: BinOp BinOp , int Width ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width )


<s> __arm_vddupq_u32 ( uint32_t * __a , const int


<s> static DecodeStatus readInstruction16 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint32_t & Insn ) { if ( Bytes . size ( ) < <NUM_LIT>


<s> } } } SmallPtrSet < Instruction * , <NUM_LIT> > Dead ; while ( ! MaybeDead . empty ( ) ) { auto * I = MaybeDead . front ( ) ; MaybeDead . remove ( I ) ; if ( I -> hasNUsesOrMore ( <NUM_LIT> ) ) continue ; for ( auto & U : I -> operands ( ) ) if ( auto * OpI = dyn_cast < Instruction > ( U ) ) MaybeDead . insert ( OpI ) ; Dead . insert ( I ) ; } for ( auto * I : Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; I -> eraseFromParent


<s> void <ISA_LIT>TargetLowering :: addQRTypeForNEON ( MVT VT ) { addRegisterClass ( VT , & <STR_LIT>


<s> for ( GlobalVariable & GV : M . globals ( ) ) { if ( GV . hasLocalLinkage ( ) ) { GV . setName ( cleanUpName ( GV . getName ( ) ) ) ; } } for ( Function & F : M . functions ( ) ) if ( F . hasLocalLinkage ( ) ) F . setName ( cleanUpName ( F . getName ( ) ) ) ; return true


<s> unsigned EvenRegNum = TRI -> getDwarfRegNum ( EvenReg , false ) ; unsigned OddRegNum = TRI -> getDwarfRegNum ( OddReg , false ) ; bool Errata602117 = EvenReg == BaseReg && STI -> isCortexM3 ( ) ; if ( ! Errata602117 && ( ( EvenRegNum & <NUM_LIT> ) == <NUM_LIT> && ( EvenRegNum + <NUM_LIT> ) == OddRegNum ) ) return false ; MachineBasicBlock :: iterator NewBBI = MBBI ; bool isT2 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isLd = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool EvenDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool EvenUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } NewBBI = llvm :: prior ( MBBI ) ; }


<s> unsigned getMemOffReg ( ) const { assert ( Kind == Memory && <STR_LIT> ) ; return Mem .


<s> bool <ISA_LIT>InstrInfo :: DefinesPredicate ( MachineInstr & , std :: vector < MachineOperand


<s> const MCInstrDesc & MC = MI . getDesc ( ) ; if ( ! <ISA_LIT>II :: isVPUInst ( MC ) ) return false ; if ( <ISA_LIT>II :: getSrcCIsStoreSrcC ( MC


<s> BuildMI ( MBB , J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; ++ FilledSlots ; Changed = true ; } return Changed


<s> if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return <STR_LIT> ( Imm )


<s> bool IsInteresting = AI . getAllocatedType ( ) -> isSized ( ) && AI . isStaticAlloca ( ) && AI . getAllocationSizeInBits ( * DL ) . getValue ( ) > <NUM_LIT> && ! AI . isUsedWithInAlloca ( ) &&

! AI . isSwiftError ( ) && ! ( SSI && SSI -> isSafe ( AI ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_LOAD_SUB ( SDValue Op , SelectionDAG & DAG ) const { auto & Subtarget = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; if ( ! Subtarget . hasLSE ( ) && ! Subtarget . outlineAtomics ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; AtomicSDNode * AN = cast < AtomicSDNode > ( Op . getNode ( ) ) ; RHS = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl


<s> FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( x ) , ALL ) { rtx sub = * iter ; if ( sub && GET_CODE ( sub ) == UNSPEC ) { int unspec_val = XINT ( sub , <NUM_LIT> ) ; switch ( unspec_val ) { case UNSPEC_PACISP : return true


<s> return ( __m256d ) __builtin_ia32_permdf256_mask ( ( __v4df ) __X , __imm , ( __v4df ) _mm256_setzero_pd ( ) ,


<s> MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; Push -> cloneMergedMemRefs ( MF , { DefMov , & * Store } ) ; DefMov -> eraseFromParent ( ) ; } else { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addReg ( Reg ) . getInstr ( ) ; Push -> cloneMemRefs ( MF , * Store ) ; } break ; } } if ( ! TFL -> hasFP ( MF ) ) TFL -> BuildCFI ( MBB , std :: next ( Push ) , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , SlotSize ) ) ; MBB . erase ( Store ) ; } if ( Context . SPCopy && MRI -> use_empty ( Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) Context . SPCopy -> eraseFromParent ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setHasPushSequences (


<s> <ISA_LIT>ELFStreamer :: <ISA_LIT>ELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; MCA . setELFHeaderEFlags (


<s> USet Rs ; for ( MachineLoop * L : WorkQ ) { Rs . clear ( ) ; collectIndRegsForLoop ( L , Rs ) ; if ( ! Rs . empty ( ) ) IRM . insert (


<s> return ( __m128i ) __builtin_ia32_pmullw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> RegisterRef PhysicalRegisterInfo :: normalize ( RegisterRef RR ) const { return


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .


<s> if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned RHSReg = getRegForValue (


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass *


<s> RuntimeMD :: KernelArg :: Value ) ; emitRuntimeMDIntValue ( OutStreamer , RuntimeMD :: KeyArgTypeKind , TypeKind , <NUM_LIT> ) ; emitRuntimeMDIntValue ( OutStreamer , RuntimeMD :: KeyArgValueType , getRuntimeMDValueType ( T , BaseTypeName ) , <NUM_LIT> ) ; auto AccQual = cast < MDString > ( F . getMetadata ( <STR_LIT> ) -> getOperand ( I ) ) -> getString ( ) ; auto AQ = StringSwitch < RuntimeMD :: KernelArg :: AccessQualifer > ( AccQual ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: ReadOnly ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: WriteOnly ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: ReadWrite ) . Default ( RuntimeMD :: KernelArg :: None ) ; emitRuntimeMDIntValue ( OutStreamer , RuntimeMD :: KeyArgAccQual , AQ , <NUM_LIT> ) ; if ( isa < PointerType > ( T ) ) emitRuntimeMDIntValue ( OutStreamer , RuntimeMD :: KeyArgAddrQual , T -> getPointerAddressSpace ( ) , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( RuntimeMD :: KeyArgEnd , <NUM_LIT> ) ; } if ( auto RWGS = F . getMetadata ( <STR_LIT> ) ) emitRuntimeMDThreeIntValues ( OutStreamer , RuntimeMD :: KeyReqdWorkGroupSize , RWGS , <NUM_LIT> ) ; if ( auto WGSH = F . getMetadata ( <STR_LIT> ) ) emitRuntimeMDThreeIntValues ( OutStreamer , RuntimeMD :: KeyWorkGroupSizeHint , WGSH , <NUM_LIT> ) ; if ( auto VTH = F . getMetadata ( <STR_LIT> ) ) { auto TypeName = getOCLTypeName ( cast < ValueAsMetadata > ( VTH -> getOperand ( <NUM_LIT> ) ) -> getType ( ) , mdconst :: extract < ConstantInt > ( VTH -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; emitRuntimeMDStringValue ( OutStreamer , RuntimeMD :: KeyVecTypeHint , TypeName ) ; } OutStreamer -> EmitIntValue ( RuntimeMD :: KeyKernelEnd


<s> static void appendAndTransferDominatedUses ( Instruction * NewPt , Instruction * User , unsigned OpNo , InsertionPoints :: iterator & IPI , InsertionPoints & InsertPts ) { IPI -> second . emplace_back ( User , OpNo ) ; Instruction * OldInstr = IPI -> first ; Uses OldUses = std :: move ( IPI -> second ) ; InsertPts [ NewPt ] = std :: move ( OldUses ) ; InsertPts . erase ( OldInstr


<s> Value * <ISA_LIT>IREmitter :: visitVCGEU ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ;


<s> return getTM < <ISA_LIT>TargetMachine > (


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> TREE_TYPE ( var ) = lds_type ; TREE_STATIC ( var ) = <NUM_LIT> ; lhd_set_decl_assembler_name ( var ) ; varpool_node :: finalize_decl ( var ) ; if ( machfun ) machfun -> use_flat_addressing = true ; return var


<s> case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case


<s> I != E ; ++ I ) { MachineInstr & MI = * I ; unsigned numOperands = MI . getNumOperands ( ) ; for ( unsigned op_idx = <NUM_LIT> ; op_idx < numOperands ; op_idx ++ ) { MachineOperand & MO = MI . getOperand ( op_idx ) ; unsigned width = <NUM_LIT> ; bool isSGPR = false ; if ( ! MO . isReg ( ) ) { continue ; } unsigned reg = MO . getReg ( ) ; if ( reg == AMDGPU :: VCC || reg == AMDGPU :: VCC_LO || reg == AMDGPU :: VCC_HI ) { VCCUsed = true ; continue ; } switch ( reg ) { default : break ; case AMDGPU :: SCC : case AMDGPU :: EXEC : case AMDGPU :: M0 : continue ; } if ( AMDGPU :: SReg_32RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_32RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_64RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_64RegClass . contains ( reg ) ) { isSGPR = false ; width =


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy )


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } return


<s> result = ( ( __vector unsigned long long ) vec_vbpermq ( ( __vector unsigned char ) __A , ( __vector unsigned char


<s> bool <ISA_LIT>DAGToDAGISel :: matchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) { SDValue Address = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == nullptr && ( Subtarget -> isTargetGlibc ( ) || Subtarget -> isTargetAndroid ( ) || Subtarget -> isTargetFuchsia ( ) ) ) switch ( N -> getPointerInfo ( ) . getAddrSpace ( ) ) { case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false ; case <NUM_LIT> : AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> bool <ISA_LIT>MachineCFGStructurizer :: containsDef ( MachineBasicBlock * MBB , LinearizedRegion *


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> static bool arm_memory_load_p ( rtx insn ) { rtx body , lhs , rhs ; ; if ( insn == NULL_RTX || GET_CODE ( insn ) != INSN ) return false ; body = PATTERN


<s> if ( ! <STR_LIT> . contains ( Op . getReg ( ) ) ) return false ; } assert ( HadDef ) ; for ( unsigned i = <NUM_LIT> ; i < II -> getNumOperands ( ) ; ++ i ) { if ( II -> getOperand ( i ) . isReg ( ) && ( II -> getOperand ( i ) . isUse ( ) || II -> getOperand ( i ) . isDef ( ) ) ) { MachineBasicBlock :: iterator localII = II ; ++ localII ; unsigned Reg = II -> getOperand ( i ) . getReg


<s> unsigned NumElems = SVOp -> getSimpleValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; unsigned NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , false , DAG , SVOp -> getMaskElt ( <NUM_LIT> ) ) ; unsigned OpSrc ; if ( ! NumZeros ) return


<s> return find_regno_note ( i , REG_DEAD , regno ) != NULL || find_regno_note ( i , REG_UNUSED , regno )


<s> Data . Offset = Offset ; } if ( MachineInstr * InputAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Data . N0 , * MRI ) ) { Data . N2 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N3 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N2 = getDefIgnoringCopies ( Data . N2 , * MRI ) -> getOperand ( <NUM_LIT> )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineModuleInfo > (


<s> return __arm_vuninitializedq_f32 ( )


<s> return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> ,


<s> EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( )


<s> unsigned PtrArgAS = PtrArg -> getType ( ) -> getPointerAddressSpace ( ) ; auto * PtrTy = llvm :: PointerType :: get ( PtrElemTy , PtrArgAS ) ; SmallVector < llvm :: Type * , <NUM_LIT> > ArgTys ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) ArgTys . push_back ( CI -> getArgOperand ( I ) -> getType ( ) ) ; ArgTys . push_back ( PtrTy ) ; Name = Name + <STR_LIT> + std :: to_string ( Size ) ; auto * FTy = FunctionType :: get ( Callee -> getReturnType ( ) , ArrayRef < Type * > ( ArgTys ) , false ) ; <ISA_LIT>LibFunc NewLibFunc ( Name , FTy ) ; FunctionCallee F = <ISA_LIT>LibFunc :: getOrInsertFunction ( M , NewLibFunc ) ; if ( ! F ) return false ; auto * BCast = B . CreatePointerCast ( PtrArg , PtrTy ) ; SmallVector < Value * , <NUM_LIT> > Args ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) Args .

push_back ( CI -> getArgOperand ( I ) ) ;


<s> static SmallVector < CalleeSavedInfo , <NUM_LIT> > getNonLibcallCSI ( const std :: vector < CalleeSavedInfo > & CSI ) { SmallVector < CalleeSavedInfo , <NUM_LIT> > NonLibcallCSI ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) >= <NUM_LIT> ) NonLibcallCSI . push_back ( CS ) ; return NonLibcallCSI


<s> Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Int ) || ! ( <NUM_LIT> <= Int && Int <= <NUM_LIT> ) ) return MatchOperand_ParseFail ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; int64_t Temp ; if ( getParser ( ) . parseAbsoluteExpression ( Temp ) || ! ( <NUM_LIT> <= Temp && Temp <= <NUM_LIT> ) ) return MatchOperand_ParseFail ; const int shift = i * <NUM_LIT> + <NUM_LIT> ; Int += ( Temp << shift ) ; } if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; } else { Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Int ) ) return MatchOperand_ParseFail ; if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_SHL0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_SHR0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_ROR0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_SHL1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_ROL1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_SHR1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_ROR1 ; } else if ( Prefix == <STR_LIT> ) { if ( Int == <NUM_LIT> ) { Int = DppCtrl :: BCAST15 ; } else if ( Int == <NUM_LIT> ) { Int = DppCtrl :: BCAST31 ; } else { return MatchOperand_ParseFail ; } } else


<s> else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p =


<s> if ( __B >= <NUM_LIT> && __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) lshift = ( __v8hu ) vec_splat_s16 ( __B ) ; else lshift = vec_splats ( ( unsigned short ) __B ) ; result = vec_sl ( ( __v8hi ) __A , lshift ) ; } return ( __m128i )


<s> int idx ; gen_cas_fn gen ; const gen_cas_fn split_cas [ ] = { gen_aarch64_compare_and_swapqi , gen_aarch64_compare_and_swaphi , gen_aarch64_compare_and_swapsi , gen_aarch64_compare_and_swapdi } ; const gen_cas_fn atomic_cas [ ] = { gen_aarch64_compare_and_swapqi_lse , gen_aarch64_compare_and_swaphi_lse , gen_aarch64_compare_and_swapsi_lse , gen_aarch64_compare_and_swapdi_lse } ; bval = operands [ <NUM_LIT> ] ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = operands [ <NUM_LIT> ] ; mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : cmp_mode = SImode


<s> isCand = isCMOVWithZeroOrAllOnesLHS ( N0 , isAND ) ; if ( isCand ) std :: swap ( N0 , N1 ) ; } if ( ! isCand ) return SDValue ( ) ; unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT>


, % o1 + <NUM_LIT> ) , op , plen , <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: RegisterMatchesArch ( unsigned MatchNum )


<s> switch ( Reg ) { default : return get<ISA_LIT>SubSuperRegister_ ( Reg , <STR_LIT> , false ) ; case


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_ROUND ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && Subtarget -> isFPOnlySP ( ) && <STR_LIT> ) ; RTLIB :: Libcall


<s> if ( skipFunction ( * F . getFunction ( ) ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; MF = & F ; <ISA_LIT>MachineFunctionInfo * MFI = F . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses (


<s> unsigned <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , bool IsComplex ) { unsigned NumVectorInstToHideOverhead =


<s> unsigned NumSrcBits = In . getScalarValueSizeInBits ( ) ; assert ( NumSrcBits > NumDstBits && <STR_LIT> ) ; auto MatchMinMax = [ ] ( SDValue V , unsigned Opcode , const APInt & Limit ) -> SDValue { APInt C ; if ( V . getOpcode ( ) == Opcode && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) . getNode ( ) , C ) && C == Limit ) return V . getOperand ( <NUM_LIT> ) ; return SDValue ( ) ; } ; APInt SignedMax , SignedMin ; if ( MatchPackUS ) { SignedMax = APInt :: getAllOnesValue ( NumDstBits ) . zext ( NumSrcBits ) ; SignedMin = APInt ( NumSrcBits , <NUM_LIT> ) ; } else { SignedMax = APInt :: getSignedMaxValue ( NumDstBits ) . sext ( NumSrcBits ) ; SignedMin = APInt :: getSignedMinValue ( NumDstBits ) .


<s> bool <ISA_LIT>MCInstrInfo :: hasNewValue ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI


<s> assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) && <STR_LIT> ) ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = vecWidth / ElVT .


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , MRI


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals =


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT ==


<s> const struct cpu_table * cpu ; unsigned int i ; int fpu ; if ( sparc_debug_string != NULL ) { const char * q ; char * p ; p = ASTRDUP ( sparc_debug_string ) ; while ( ( q = strtok ( p , <STR_LIT> ) ) != NULL ) { bool invert ; int mask ; p = NULL ; if ( * q == '!' ) { invert = true ; q ++ ; } else invert = false ; if ( ! strcmp ( q , <STR_LIT> ) ) mask = MASK_DEBUG_ALL ; else if ( ! strcmp ( q , <STR_LIT> ) ) mask = MASK_DEBUG_OPTIONS ; else error ( <STR_LIT> , q ) ; if ( invert ) sparc_debug &= ~ mask ; else sparc_debug |= mask ; } } if ( TARGET_DEBUG_OPTIONS ) { dump_target_flags ( <STR_LIT> , target_flags ) ; dump_target_flags ( <STR_LIT> , target_flags_explicit ) ; } SUBTARGET_OVERRIDE_OPTIONS ; if ( ! TARGET_64BIT != DEFAULT_ARCH32_P ) error ( <STR_LIT> , DEFAULT_ARCH32_P ? <STR_LIT> : <STR_LIT> ) ; if ( TARGET_ARCH64 && ! TARGET_LONG_DOUBLE_128 ) { error ( <STR_LIT> ) ; target_flags |= MASK_LONG_DOUBLE_128 ; } sparc_cmodel = SPARC_DEFAULT_CMODEL ; if ( TARGET_ARCH32 ) sparc_cmodel = CM_32 ; if ( sparc_cmodel_string != NULL ) { if ( TARGET_ARCH64 ) { for ( cmodel = & cmodels [ <NUM_LIT> ] ; cmodel -> name ; cmodel ++ ) if ( strcmp ( sparc_cmodel_string , cmodel -> name ) == <NUM_LIT> ) break ; if ( cmodel -> name == NULL ) error ( <STR_LIT> , sparc_cmodel_string ) ; else sparc_cmodel = cmodel -> value ; } else error ( <STR_LIT> ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! call_used_regs [ i ] ) { error ( <STR_LIT> ) ; call_used_regs [ i ] = <NUM_LIT> ; } fpu = target_flags & MASK_FPU ; if ( ! global_options_set . x_sparc_cpu_and_features ) { for ( def = & cpu_default [ <NUM_LIT> ] ; def -> cpu != - <NUM_LIT> ; ++ def ) if ( def -> cpu == TARGET_CPU_DEFAULT ) break ; gcc_assert ( def -> cpu != - <NUM_LIT> ) ; sparc_cpu_and_features = def -> processor ; } if ( ! global_options_set . x_sparc_cpu ) sparc_cpu = sparc_cpu_and_features ; cpu = & cpu_table [ ( int ) sparc_cpu_and_features ] ; if ( TARGET_DEBUG_OPTIONS ) { fprintf ( stderr , <STR_LIT> , cpu -> name ) ; fprintf ( stderr , <STR_LIT> , cpu_table [ ( int ) sparc_cpu ] . name ) ; dump_target_flags ( <STR_LIT> , cpu -> disable ) ; dump_target_flags ( <STR_LIT> , cpu -> enable ) ; } target_flags &= ~ cpu -> disable ; target_flags |= ( cpu -> enable & ~ ( MASK_FMAF | MASK_VIS3 ) & ~ MASK_CBCOND & ~ ( MASK_VIS4 | MASK_SUBXC ) & ~ ( MASK_LEON | MASK_LEON3 ) ) ; if ( target_flags_explicit & MASK_FPU ) target_flags = (


<s> unsigned <ISA_LIT>Subtarget :: getMispredictionPenalty ( ) const { if ( isCortexA8 ( ) ) return


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo


<s> SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_X : if ( ! selectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back (


<s> static inline int is_multilib_enabled ( struct loongarch_abi abi ) { return enabled_abi_types [ abi . base ] [ abi . ext


<s> inline static std :: string getISRAddr ( void ) { return


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( BaseReg ) ) return false ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_instr_iterator I = MRI . def_instr_begin ( BaseReg ) , E = MRI . def_instr_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = &


<s> int <ISA_LIT>Subtarget :: getAdjustedFrameSize ( int frameSize ) const { frameSize += <NUM_LIT> ; frameSize = alignTo ( frameSize , <NUM_LIT> ) ; return frameSize


<s> bool DstDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned AccReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Src2Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned LaneImm = HasLane ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; unsigned NextOp = HasLane ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NextOp ) . getImm ( ) ; unsigned PredReg = MI -> getOperand ( ++ NextOp ) . getReg ( ) ; const MCInstrDesc & MCID1 = TII -> get ( MulOpc ) ; const MCInstrDesc & MCID2 = TII -> get ( AddSubOpc ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; unsigned TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred ) . addReg (


<s> if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat (


<s> if ( isa < LoadInst > ( Inst ) && Ord == AtomicOrdering :: SequentiallyConsistent ) return Builder . CreateFence ( Ord ) ; if ( isa < StoreInst > ( Inst ) && isReleaseOrStronger ( Ord

) ) return Builder . CreateFence ( AtomicOrdering :: Release ) ;


<s> bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs ) ; if ( Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned Offset = State . AllocateStack ( ValVT . getSizeInBits ( ) >> <NUM_LIT> , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ,

<STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Src ) ;


<s> const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } else { report_fatal_error ( <STR_LIT> <STR_LIT>


<s> static bool c6x_return_in_memory ( const_tree type

, const_tree fntype ATTRIBUTE_UNUSED ) {


<s> rtx src1 = operands [ <NUM_LIT> ] ; rtx src2 = operands [ <NUM_LIT> ] ; rtx cr_reg = operands [ <NUM_LIT> ] ; rtx ret ; machine_mode cr_mode = GET_MODE ( cr_reg ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( cr_reg , gen_rtx_fmt_ee ( GET_CODE ( test ) , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; if ( GET_CODE ( src1 ) == CONST_INT && GET_CODE ( src2 ) == CONST_INT ) { HOST_WIDE_INT value1 = INTVAL ( src1 ) ; HOST_WIDE_INT value2 = INTVAL ( src2 ) ; if ( value1 == <NUM_LIT> ) { emit_move_insn ( dest , src2 ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_NE ( cr_mode , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , src1 ) ) ) ; } else if ( value2 == <NUM_LIT> ) { emit_move_insn ( dest , src1


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex (


<s> switch ( DefMI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>FrameLowering :: hasTailCall ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpcode = MBBI -> getOpcode


<s> bool hasMulI24 ( ) const { return HasMulI24


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRspii ( SDValue Op , SDValue Addr , SDValue & Base , SDValue & Offset ) { FrameIndexSDNode * FIN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT>


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , RM , CM ) , InstrInfo ( Subtarget . hasThumb2 ( )

? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) :


<s> arg_rtx = arm_function_arg ( args_so_far , arg ) ; gcc_assert ( REG_P ( arg_rtx ) ) ; to_clear_args_mask = compute_not_to_clear_mask ( arg_type , arg_rtx , REGNO ( arg_rtx ) , & padding_bits_to_clear [ <NUM_LIT> ] ) ; if ( to_clear_args_mask ) { for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_args_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap , regno ) ; } } first_param = false


<s> rtx set_src = SET_SRC ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; int len = shift_insns [ INTVAL ( XEXP ( set_src , <NUM_LIT> ) ) ] ; rtx op = XEXP ( set_src , <NUM_LIT>


<s> return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } SMLoc FPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int FPReg = tryParseRegister ( ) ; if ( FPReg == - <NUM_LIT> ) { Error ( FPRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; SMLoc SPRegLoc = Parser . getTok ( ) . getLoc ( ) ; int SPReg = tryParseRegister ( ) ; if ( SPReg == - <NUM_LIT> ) { Error ( SPRegLoc , <STR_LIT> ) ; return


<s> static bool s390_valid_pointer_mode ( enum machine_mode mode ) { return ( mode == SImode || ( TARGET_64BIT && mode ==


<s> return ( ( vec_uint4 ) ( si_mpyui ( ( qword


<s> AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass


<s> LocInfo = CCValAssign :: Indirect ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; unsigned Reg ; const <ISA_LIT>Subtarget & Subtarget = State . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isTargetELF ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else if ( Subtarget . isTargetXPLINK64 ( ) ) Reg = State . AllocateReg ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Offset = Reg && ! Subtarget . isTargetXPLINK64 ( ) ? <NUM_LIT> : State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; for ( auto & It : PendingMembers ) { if ( Reg ) It .


<s> void thumb_set_return_address ( rtx source , rtx scratch ) { arm_stack_offsets * offsets ; HOST_WIDE_INT delta ; HOST_WIDE_INT limit ; int reg ; rtx addr ; unsigned long mask ; emit_use ( source ) ; offsets = arm_get_frame_offsets ( ) ; mask = offsets -> saved_regs_mask ; if ( mask & ( <NUM_LIT> << LR_REGNUM ) ) { limit = <NUM_LIT> ; if ( frame_pointer_needed ) { delta = offsets -> soft_frame - offsets -> saved_args ; reg = THUMB_HARD_FRAME_POINTER_REGNUM ; if ( TARGET_THUMB1 ) limit = <NUM_LIT> ; } else { delta = offsets -> outgoing_args - offsets -> saved_args ; reg = SP_REGNUM ; } if ( TARGET_THUMB1 && TARGET_BACKTRACE ) delta -= <NUM_LIT> ; delta -= <NUM_LIT> ; addr = gen_rtx_REG ( SImode , reg ) ; if ( delta > limit


<s> bool isLittleEndian ( ) const { return isLittle


<s> MVT VT = <STR_LIT> ; TransposedMatrix . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > MaskLow ; SmallVector < int , <NUM_LIT> > MaskLowTemp1 , MaskLowWord ; SmallVector < int , <NUM_LIT> > MaskHighTemp1 , MaskHighWord ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { MaskLow . push_back ( i ) ; MaskLow . push_back ( i + <NUM_LIT> ) ; } createUnpackShuffleMask ( VT , MaskLowTemp1 , true , false ) ; createUnpackShuffleMask ( VT , MaskHighTemp1 , false , false ) ; scaleShuffleMask ( <NUM_LIT> , MaskHighTemp1 , MaskHighWord ) ; scaleShuffleMask ( <NUM_LIT> , MaskLowTemp1 , MaskLowWord


<s> void EmitInstrRegRegReg ( const MCSubtargetInfo & STI , unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( const MCSubtargetInfo & STI , unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( const MCSubtargetInfo & STI , <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; void EmitBasicBlockEnd ( const MachineBasicBlock & MBB ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum ,


<s> SDValue RetValue = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue


<s> SDValue CPIdx = DAG . getConstantPool ( C , PtrVT , <NUM_LIT> ) ; MVT LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mask1 = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Op1 , Mask1 ) ; if ( ConstantFPSDNode * Op0CN = dyn_cast < ConstantFPSDNode > ( Op0 ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; if ( APF . isPosZero ( ) ) return DAG . getNode ( <STR_LIT> , dl , SrcVT , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; APF . clearSign ( ) ; CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APF ) ; } else { CV [ <NUM_LIT> ] = ConstantFP :: get ( * Context , APFloat ( Sem , APInt :: getLowBitsSet ( SizeInBits , SizeInBits


<s> void <ISA_LIT>LowerKernelArgs :: handlePointerParam ( Argument * Arg ) { assert ( ! Arg -> hasByValAttr ( ) && <STR_LIT> ) ; Instruction * FirstInst = Arg -> getParent ( ) -> getEntryBlock (


<s> SmallSet < int64_t , <NUM_LIT> > Literals ; for ( unsigned i = <NUM_LIT> , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; for ( const auto & Src : getSrcs ( MI ) ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg


<s>
bool
CopyPropagation
::
run
(
)
{
scanBlock
(
&
DFG
.
getMF
(
)
.
front
(
)
)
;
if
(
trace
(
)
)
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
I
:
Copies
)
{
dbgs
(
)
<<
<STR_LIT>
<<
*
DFG
.
addr
<
StmtNode
*
>
(
I
)
.
Addr
->
getCode
(
)
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
J
:
CopyMap
[
I
]
)
dbgs
(
)
<<
' '
<<
Print
<
RegisterRef
>
(
J
.
first
,
DFG
)
<<
'='
<<
Print
<
RegisterRef
>
(
J
.
second
,
DFG
)
;
dbgs
(
)
<<
<STR_LIT>
;
}
}
bool
Changed
=
false
;
bool
HasLimit
=
CpLimit
.
getNumOccurrences
(
)
>
<NUM_LIT>
;
auto
MinPhysReg
=
[
this
]
(
RegisterRef
RR
)
->
unsigned
{
const
TargetRegisterInfo
&
TRI
=
DFG
.
getTRI
(
)
;
const
TargetRegisterClass
&
RC
=
*
TRI
.
getMinimalPhysRegClass
(
RR
.
Reg
)
;
if
(
(
RC
.
LaneMask
&
RR
.
Mask
)
==
RC
.
LaneMask
)
return
RR
.
Reg
;
for
(
MCSubRegIndexIterator
S
(
RR
.
Reg
,
&
TRI
)
;
S
.
isValid
(
)
;
++
S
)
if
(
RR
.
Mask
==
TRI
.
getSubRegIndexLaneMask
(
S
.
getSubRegIndex
(
)
)
)
return
S
.
getSubReg
(
)
;
llvm_unreachable
(
<STR_LIT>
)
;
return
<NUM_LIT>
;
}
;
for
(
auto
C
:
Copies
)
{
if
(
HasLimit
&&
CpCount
>=
CpLimit
)
break
;
auto
SA
=
DFG
.
addr
<
InstrNode
*
>
(
C
)
;
auto
FS
=
CopyMap
.
find
(
SA
.
Id
)
;
if
(
FS
==
CopyMap
.
end
(
)
)
continue
;
EqualityMap
&
EM
=
FS
->
second
;
for
(
NodeAddr
<
DefNode
*
>
DA
:
SA
.
Addr
->
members_if
(
DFG
.
IsDef
,
DFG
)
)
{
RegisterRef
DR
=
DA
.
Addr
->
getRegRef
(
DFG
)
;
auto
FR
=
EM
.
find
(
DR
)
;
if
(
FR
==
EM
.
end
(
)
)
continue
;
RegisterRef
SR
=
FR
->
second
;
if
(
DR
==
SR
)
continue
;
NodeId
AtCopy
=
getLocalReachingDef
(
SR
,
SA
)
;
for
(
NodeId
N
=
DA
.
Addr
->
getReachedUse
(
)
,
NextN
;
N
;
N
=
NextN
)
{
auto
UA
=
DFG
.
addr
<
UseNode
*
>
(
N
)
;
NextN
=
UA
.
Addr
->
getSibling
(
)
;
uint16_t
F
=
UA
.
Addr
->
getFlags
(
)
;
if
(
(
F
&
NodeAttrs
::
PhiRef
)
||
(
F
&
NodeAttrs
::
Fixed
)
)
continue
;
if
(
UA
.
Addr
->
getRegRef
(
DFG
)
!=
DR
)
continue
;
NodeAddr
<
InstrNode
*
>
IA
=
UA


<s> assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI

. getShiftAmountTy ( SrcOp . getValueType ( ) ) ) ) ) ;


<s> SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty ,


<s> case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = std :: min ( ( int ) GV -> getAlignment ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags


<s> * ( __mmask32 * ) __A = __builtin_ia32_kmovd (


<s> <ISA_LIT>RegBankCombinerHelper ( MachineIRBuilder & B , CombinerHelper & Helper ) : B ( B ) , MF ( B . getMF ( ) ) , MRI ( * B . getMRI ( ) ) ,

RBI ( * MF . getSubtarget ( ) . getRegBankInfo ( ) ) , TRI ( * MF . getSubtarget ( ) . getRegisterInfo ( ) ) , Helper ( Helper ) { }


<s> for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) { rtx tmp ; if ( GET_CODE ( insn ) != INSN && GET_CODE ( insn ) != JUMP_INSN ) continue ; tmp = PATTERN ( insn ) ; if ( GET_CODE ( tmp ) != SET ) continue ; tmp = SET_DEST ( tmp ) ; if ( GET_CODE ( tmp ) == REG && REGNO ( tmp ) == <NUM_LIT> ) { fcmp_count ++ ; continue ; } tmp = PATTERN ( insn ) ; if ( GET_CODE ( tmp ) == SET && SET_DEST ( tmp ) == pc_rtx && GET_CODE ( SET_SRC ( tmp ) ) == IF_THEN_ELSE && GET_CODE ( XEXP ( SET_SRC ( tmp ) , <NUM_LIT> ) ) == NE && GET_CODE ( XEXP ( XEXP ( SET_SRC ( tmp ) , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( XEXP ( SET_SRC ( tmp ) , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> ) { fbranch_count ++ ; continue ; } } for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) { rtx tmp , next ; if ( GET_CODE ( insn ) != INSN ) continue ; tmp = PATTERN ( insn


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , <NUM_LIT> ) ; dest = XEXP ( dest , <NUM_LIT> ) ; dest_uid = INSN_UID (


<s> } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; if ( ! Symbols ) return false ; auto Result = std :: find_if ( Symbols -> begin ( ) , Symbols -> end ( ) , [ Value ] ( const SymbolInfoTy & Val ) { return std :: get < <NUM_LIT> > ( Val ) == static_cast < uint64_t > ( Value ) && std :: get < <NUM_LIT> > ( Val ) == ELF :: STT_NOTYPE ; } )


<s> if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> ,


<s> SDLoc dl ( Op ) ; const auto & DL = DAG . getDataLayout ( ) ; const auto & TLI = DAG . getTargetLoweringInfo ( ) ; const char * Name = nullptr ; if ( Signed ) Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalSymbol ( Name , TLI . getPointerTy ( DL ) ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext


<s> return DAG . getLoad ( getPointerTy ( ) , SDLoc ( Op ) , DAG . getEntryNode ( ) , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false


<s> NumIssued = <NUM_LIT> ; HasCTRSet = false ; NumStores = <NUM_LIT>


<s> static inline std :: string createGlobalValueName ( const Module & M , const std :: string & Propose ) { std :: string Name =


<s> if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; if ( TwoRepStos ) { InFlag = Chain . getValue ( <NUM_LIT> ) ; Count = Size ; EVT CVT = Count . getValueType ( ) ; SDValue Left = DAG . getNode ( <STR_LIT> , dl , CVT , Count , DAG . getConstant ( ( AVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , CVT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , ( CVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> , Left , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( <STR_LIT> ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , array_lengthof ( Ops ) ) ; } else if ( BytesLeft ) { unsigned Offset = SizeVal


<s> ShuffleVectorSDNode * Shuffle = cast < ShuffleVectorSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; EVT SrcType = Shuffle -> getValueType ( <NUM_LIT> ) ; if ( ! Shuffle -> getOperand ( <NUM_LIT> ) -> isUndef ( ) ) return SDValue ( ) ; unsigned SrcSize = SrcType . getScalarSizeInBits ( ) ; unsigned NumElems = SrcType . getVectorNumElements ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! Vector -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) ) return SDValue ( ) ; unsigned ResSize = N1 . getValueType ( ) . getScalarSizeInBits ( ) ; if ( SplatBitSize > ResSize || ( SplatValue + <NUM_LIT> ) . exactLogBase2 ( ) != ( int ) SrcSize ) return SDValue ( ) ; if ( SrcSize >= ResSize || ResSize % SrcSize ) return SDValue ( ) ; unsigned ZextRatio = ResSize / SrcSize ; bool IsZext = true ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { if ( i % ZextRatio ) { if ( Shuffle -> getMaskElt ( i ) > <NUM_LIT> ) { IsZext = false ; break ; } } else


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Reg = <STR_LIT> ; MachineBasicBlock :: iterator MoveInstruction = BuildMI ( * BasicBlockIterator , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand (

<NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering


__A , long long __B , long long __C , long long __D ) {


<s> reorg_loops ( true , & bfin_doloop_hooks


<s> Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> )


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeMemChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned AddrSpace ) const { return ( AddrSpace != <ISA_LIT>AS :: PRIVATE_ADDRESS


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_RegMask


<s> void <ISA_LIT>TargetELFStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { setAttributeItem ( Attribute ,


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { bool adjustHeadCond = ( HeadImm < TrueImm ) ; if ( HeadCmp == <STR_LIT> ) { adjustHeadCond = ! adjustHeadCond ; } if ( adjustHeadCond ) { Changed |= adjustTo ( HeadCmpMI ,


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) { OutMI . setOpcode ( TII -> pseudoToMCOpcode ( <STR_LIT> ) ) ; MCOperand Dest , Src ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Src ) ; OutMI . addOperand ( Dest ) ; OutMI . addOperand ( Src ) ; return ; } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; lowerOperand ( MO , MCOp ) ; OutMI . addOperand ( MCOp ) ; } int FIIdx = <STR_LIT> ( MCOpcode , <STR_LIT>


<s> SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; unsigned Space = ( PrevReg < Reg ) ? ( Reg - PrevReg ) : ( Reg + <NUM_LIT> - PrevReg ) ; if ( Space == <NUM_LIT> || Space > <NUM_LIT> ) { return Error ( Loc , <STR_LIT> ) ; } Count += Space ; } else { while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) return Error ( Loc , <STR_LIT> ) ; PrevReg = Reg ; ++ Count ; } } if ( Parser . getTok ( ) . is ( AsmToken :: EndOfStatement ) ) Error ( getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; unsigned NumElements = <NUM_LIT> ; char ElementKind = <NUM_LIT> ; if ( ! Kind . empty ( ) ) parseValidVectorKind ( Kind , NumElements , ElementKind ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorList ( FirstReg , Count , NumElements , ElementKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return false ; } SMLoc E = getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo ::


<s> j < n ; ++ j ) { MCOperand const & Operand = I . getOperand ( j ) ; if ( Operand . isReg ( ) && Operand . getReg ( ) == Register ) return true ; } return


<s> vqmovn_high_u32 ( uint16x4_t a , uint32x4_t b ) { uint16x8_t result = vcombine_u16 ( a , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT>


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) S = MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return S


<s> break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { TargetRegisterClass * RC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering


<s> return ( poly16x4_t ) __builtin_neon_vreinterpretv4hidi (


<s> EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( C , VT ,


<s> return TargetTriple . getOS ( ) == Triple


<s> Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult =


<s> void <ISA_LIT>InstPrinter :: printGDS ( const MCInst * MI , unsigned OpNo , raw_ostream &


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = LowerSymbolOperand ( MO , GetConstantPoolIndexSymbol ( MO


<s> static const CostTblEntry < MVT > NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup < MVT > ( NEONShuffleTbl , array_lengthof ( NEONShuffleTbl ) , <STR_LIT> , LT .


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T ,


<s> addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , DImode , addr , i ) ; emit_move_insn ( mem , reg ) ; } } else val_reg = force_reg ( SImode , val_exp ) ; reg = ( use_strd_p ? gen_lowpart ( SImode , val_reg ) : val_reg ) ; for ( ; ( i + <NUM_LIT> <= length ) ; i += <NUM_LIT> ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; } if ( unaligned_access && i > <NUM_LIT> && ( i + <NUM_LIT> ) == length ) { addr = plus_constant ( Pmode , dst , i - <NUM_LIT> ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i - <NUM_LIT> ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; return true ; } if ( i + <NUM_LIT> <= length ) { reg = gen_lowpart ( HImode , val_reg ) ; addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , HImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT>


<s> if ( Pos != std :: string :: npos ) { Pos += StrToFind . length ( ) ; std :: string Color = <STR_LIT> ; char c = Sectn . at ( Pos ) ; while ( c >= '0' &&


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; ArgInfos . push_back ( AInfo ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( )


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) ) , VT . getVectorNumElements ( ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , VT ,


<s> if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ; return


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getValueSizeInBits ( ) == <NUM_LIT> && VT . getScalarSizeInBits ( ) == N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; unsigned NumSrcElts = N00 . getValueType ( ) .


<s> enum { N = <NUM_LIT> , Z = <NUM_LIT> , C = <NUM_LIT> , V = <NUM_LIT> } ; switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return Z ; case NE : return <NUM_LIT> ; case HS : return C ; case LO : return <NUM_LIT> ; case MI : return


<s> MachineInstr * DummyOp = nullptr ; if ( BasicBlockScopeOnly ) { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; DummyOp = MF . CreateMachineInstr ( TII -> get ( <STR_LIT> ) , DebugLoc ( ) ) ; } unsigned NbReg = RegToId . size ( ) ; bool Modified = false ; InstrToInstrs * ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , true , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( printReachingDef ( ColorOpToReachedUses , NbReg , TRI , IdToReg ) ) ; InstrToInstrs ADRPToReachingDefs ; reachedUsesToDefs ( ADRPToReachingDefs , ColorOpToReachedUses , RegToId , true ) ; computeADRP ( ADRPToReachingDefs , * <ISA_LIT>FI , MDT ) ; delete [ ] ColorOpToReachedUses ; ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , false , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( printReachingDef ( ColorOpToReachedUses , NbReg , TRI , IdToReg ) ) ; InstrToInstrs UsesToReachingDefs ; reachedUsesToDefs ( UsesToReachingDefs , ColorOpToReachedUses , RegToId , false ) ; computeOthers ( UsesToReachingDefs , ColorOpToReachedUses , * <ISA_LIT>FI , RegToId , MDT ) ; delete [ ] ColorOpToReachedUses ; if ( BasicBlockScopeOnly ) MF . DeleteMachineInstr ( DummyOp


<s> if ( R >= <STR_LIT> && R <= <STR_LIT> ) { static const char * S [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return S [ R - <STR_LIT> ] ; } if ( R >= <STR_LIT> && R <= <STR_LIT> ) { static const char * S [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> if ( ! DummyOp ) reachingDefAlgorithm ( MF , ColorOpToReachedUses , In , Out , Gen , Kill , ReachableUses , RegToId


<s> MCContext & Ctx = Asm . getContext ( ) ; const MCExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; MCFixup Fixup = MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , SMLoc ( ) ) ; uint64_t FixedValue


<s> std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; EVT LoVT , HiVT ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; SDValue RC = Op . getOperand ( <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , LoVT , Lo , RC ) ; Hi = DAG . getNode ( <STR_LIT> , dl


<s> State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned Offset = State . AllocateStack ( ValVT . getSizeInBits ( ) >> <NUM_LIT> , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; } else State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } if ( MI . getNumOperands ( ) == <NUM_LIT> ) { TmpInst = MCInstBuilder ( Opcode ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; } else if ( MI . getNumOperands ( ) == <NUM_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; TmpInst = MCInstBuilder ( Opcode ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; } else if ( MI . getNumOperands ( ) == <NUM_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( )


<s> return ( __m512i ) __builtin_ia32_expandloadsi512_maskz ( ( const __v16si * ) __P , ( __v16si ) _mm512_setzero_si512 ( ) ,


<s> static inline const MachineInstrBuilder & addRegIndirectWithDisp ( const MachineInstrBuilder & MIB , unsigned Reg


<s> static MCInstrInfo * createMCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo (


<s> if ( ! StoreVT . isVector ( ) ) return VData ; SDLoc DL ( VData ) ; unsigned NumElements = StoreVT . getVectorNumElements ( ) ; if ( Subtarget -> hasUnpackedD16VMem ( ) ) { EVT IntStoreVT = StoreVT . changeTypeToInteger ( ) ; SDValue IntVData = DAG . getNode ( <STR_LIT> , DL , IntStoreVT , VData ) ; EVT EquivStoreVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElements ) ; SDValue ZExt = DAG . getNode ( <STR_LIT> , DL , EquivStoreVT , IntVData ) ; return DAG . UnrollVectorOp ( ZExt . getNode ( ) ) ; } if ( ImageStore && Subtarget -> hasImageStoreD16Bug ( ) ) { EVT IntStoreVT = StoreVT . changeTypeToInteger ( ) ; SDValue IntVData = DAG . getNode ( <STR_LIT> , DL , IntStoreVT , VData ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; DAG . ExtractVectorElements ( IntVData , Elts ) ; SmallVector < SDValue , <NUM_LIT> > PackedElts ; for ( unsigned I = <NUM_LIT> ; I < Elts . size ( ) / <NUM_LIT> ; I += <NUM_LIT> ) { SDValue Pair = DAG . getBuildVector ( <STR_LIT> , DL , { Elts [ I * <NUM_LIT> ] , Elts [ I * <NUM_LIT> + <NUM_LIT> ] } ) ; SDValue IntPair = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Pair ) ; PackedElts . push_back ( IntPair ) ; } if ( ( NumElements % <NUM_LIT> ) == <NUM_LIT> ) { unsigned I = Elts . size ( ) / <NUM_LIT> ; SDValue Pair = DAG . getBuildVector ( <STR_LIT> , DL , { Elts [ I * <NUM_LIT> ] , DAG . getUNDEF ( <STR_LIT> ) } ) ; SDValue IntPair = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Pair ) ; PackedElts . push_back ( IntPair ) ; } PackedElts . resize ( Elts . size ( ) , DAG . getUNDEF ( <STR_LIT> ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , PackedElts . size ( ) ) ; return DAG . getBuildVector ( VecVT , DL , PackedElts ) ; } if ( NumElements == <NUM_LIT> ) { EVT IntStoreVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , StoreVT . getStoreSizeInBits ( ) ) ; SDValue IntVData = DAG . getNode ( <STR_LIT> , DL , IntStoreVT , VData ) ; EVT WidenedStoreVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreVT . getVectorElementType ( ) , NumElements + <NUM_LIT> ) ; EVT WidenedIntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidenedStoreVT . getStoreSizeInBits ( ) ) ; SDValue ZExt = DAG . getNode ( <STR_LIT> , DL , WidenedIntVT , IntVData ) ; return DAG . getNode ( <STR_LIT> , DL , WidenedStoreVT , ZExt ) ; } assert ( isTypeLegal ( StoreVT ) ) ; return


<s> virtual const TargetData * getTargetData


<s> temp = expand_binop ( mode , lshr_optab , count , GEN_INT ( <NUM_LIT> ) , blocks , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_label ( loop_start_label ) ; if ( TARGET_Z10 && ( GET_CODE ( len ) != CONST_INT || INTVAL ( len ) > <NUM_LIT> ) ) { rtx prefetch ; prefetch = gen_prefetch ( gen_rtx_PLUS ( Pmode , src_addr , GEN_INT ( <NUM_LIT> ) ) , const0_rtx , const0_rtx ) ; PREFETCH_SCHEDULE_BARRIER_P ( prefetch ) = true ; emit_insn ( prefetch ) ; prefetch = gen_prefetch ( gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( <NUM_LIT> ) ) , const1_rtx , const0_rtx ) ; PREFETCH_SCHEDULE_BARRIER_P ( prefetch ) = true ; emit_insn ( prefetch ) ; } emit_insn ( gen_movmem_short ( dst , src , GEN_INT ( <NUM_LIT> ) ) ) ; s390_load_address ( dst_addr , gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( <NUM_LIT> ) ) ) ; s390_load_address ( src_addr , gen_rtx_PLUS ( Pmode , src_addr , GEN_INT ( <NUM_LIT> ) ) ) ; temp = expand_binop ( mode , add_optab , blocks , constm1_rtx


<s> const LLT DstTy = MRI . getType ( DstReg ) ; unsigned VecSize = DstTy . getSizeInBits ( ) ; unsigned EltReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT EltTy = MRI . getType ( EltReg ) ; unsigned EltSize = EltTy . getSizeInBits ( ) ; if ( EltSize < <NUM_LIT> || EltSize > <NUM_LIT> ) return false ; unsigned IdxReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( IdxReg , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; MachineIRBuilder MIRBuilder ( I ) ; if ( VecSize < <NUM_LIT> ) { MachineInstr * ScalarToVec = emitScalarToVector ( VecSize , & <STR_LIT> , SrcReg , MIRBuilder ) ; if ( ! ScalarToVec ) return false ; SrcReg = ScalarToVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineInstr * InsMI = emitLaneInsert ( None , SrcReg , EltReg , LaneIdx , EltRB , MIRBuilder ) ; if ( VecSize < <NUM_LIT> ) { unsigned DemoteVec = InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = getMinClassForRegBank ( * RBI . getRegBank ( DemoteVec , MRI , TRI ) , VecSize ) ; if ( RC != & <STR_LIT> && RC != & <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SubReg


<s> SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( VT . is512BitVector ( ) || SVT . getVectorElementType ( )

== <STR_LIT> ) return LowerZERO_EXTEND_AVX512 ( Op , Subtarget , DAG ) ;


<s> SmallVector < LoadInst * , <NUM_LIT> > AggrLoads ; SmallVector < MemIntrinsic * , <NUM_LIT> > MemCalls ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( & I ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { auto * SI = cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlign ( ) , SI -> getAlign ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , TTI ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy , TTI ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) { expandMemMoveAsLoop ( Memmove ) ; } else if ( MemSetInst * Memset = dyn_cast < MemSetInst > ( MemCall ) ) { expandMemSetAsLoop ( Memset ) ; } MemCall -> eraseFromParent ( ) ; } return true


<s> case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } else { switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; } } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return Binary ; if ( Rs ) { assert ( <STR_LIT> ( MO2 . getImm ( )


<s> regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM ) return true ; if ( TARGET_MIPS16 && regno == STACK_POINTER_REGNUM ) return GET_MODE_SIZE ( mode ) == <NUM_LIT>

|| GET_MODE_SIZE ( mode ) == <NUM_LIT> ;


<s> unsigned getScalarDataSize ( ) const { return


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == <NUM_LIT> ) return AM . Base . Reg ; Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel (


<s> void cvtMubufLds ( MCInst & Inst , const


<s> __jcvt ( double __a ) { return __builtin_aarch64_jcvtzs (


<s> SDValue Carry = N -> getOperand ( <NUM_LIT> ) ; while ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT>

|| ( Carry . getOpcode ( ) == <STR_LIT> && isOneConstant ( Carry . getOperand ( <NUM_LIT> ) ) ) ) Carry = Carry . getOperand ( <NUM_LIT> ) ;


<s> unsigned ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; ResultReg = FastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; if ( ResultReg == <NUM_LIT> ) return false ; if ( DstVT != <STR_LIT> ) { ResultReg = FastEmit_r ( <STR_LIT> , DstVT . getSimpleVT ( ) , <STR_LIT> , ResultReg , true ) ; if ( ResultReg == <NUM_LIT> ) return false ; } UpdateValueMap ( I , ResultReg ) ; return


<s> if ( WasCandidate ) { MIReplacements . push_back ( std :: make_pair ( MI , NewMI ) ) ; if ( ! NewMI ) CandidateDidntGetTransformed = true ; } LiveRegs . stepBackward ( * MI ) ; } if ( CandidateDidntGetTransformed ) { LiveRegs . clear ( ) ; LiveRegs . addLiveIns ( MBB ) ; auto NextCandidateIter = MIReplacements . begin ( ) ; auto EndCandidateIter = MIReplacements . end ( ) ; for ( auto I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { MachineInstr * MI = & * I ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . stepForward ( * MI , Clobbers ) ; if ( NextCandidateIter == EndCandidateIter ) break ; if ( NextCandidateIter -> first == MI ) { if ( NextCandidateIter -> second == nullptr ) { MachineInstr * NewMI = tryReplaceInstr ( MI , MBB , WasCandidate ) ; NextCandidateIter -> second = NewMI ; } ++ NextCandidateIter ; } } } while ( ! MIReplacements . empty ( ) ) { MachineInstr * MI = MIReplacements .


<s> int getDynAllocFI ( ) const { if ( ! DynAllocFI ) DynAllocFI = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; return DynAllocFI


<s> SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode ,


<s> param_iterator call_ret_end ( ) const { return CallRetParams . end


<s> bool isPrefix ( ) const { return Kind ==


<s> InFlag = Chain . getValue ( <NUM_LIT> ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; if ( G ) Callee = DAG . getGlobalAddress ( G -> getGlobal ( ) , Loc , PtrVT , <NUM_LIT> ) ; std :: vector < SDValue > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const uint32_t * Mask ; const TargetRegisterInfo * TRI = DAG . getSubtarget ( ) . getRegisterInfo ( ) ; Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , Loc , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , Loc , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , Loc , true ) , InFlag , Loc ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , Loc , DAG ,


<s> for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF -> getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i -


<s> case <NUM_LIT> : break ; } return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> + OpOffset , <NUM_LIT> + OpOffset ) ; } case <STR_LIT> : if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned CommutableOpIdx1 = <NUM_LIT> ; unsigned CommutableOpIdx2 = <NUM_LIT> ; if ( <STR_LIT> ( Desc . TSFlags ) ) { ++ CommutableOpIdx1 ; ++ CommutableOpIdx2 ; } if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 ,


<s> std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , ValTy ) ; if ( Opcode == Instruction :: FCmp ) return LT . first + FloatFactor * getTypeNumElements (


<s> if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return


<s> LatticeCell ( ) : Kind ( Top ) , Size ( <NUM_LIT> )


<s> return true ; case ELF :: R_<ISA_LIT>_GOT16 : return true ; case ELF :: R_<ISA_LIT>_HI16 : case ELF :: R_<ISA_LIT>_LO16 : case ELF :: R_<ISA_LIT>_32 : return true ; case ELF :: R_<ISA_LIT>_GPREL16 : return false


<s> void <ISA_LIT>AsmPrinter :: LowerGETPCXAndEmitMCInsts ( const MachineInstr * MI , const MCSubtargetInfo & STI ) { MCSymbol * GOTLabel = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; MCOperand MCRegOP = MCOperand :: createReg ( MO . getReg ( ) ) ; if ( ! isPositionIndependent ( ) ) { switch ( TM . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , MCRegOP , OutContext , STI ) ; break ; case CodeModel :: Medium : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand lo = create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , GOTLabel , OutContext ) ; EmitOR ( * OutStreamer , MCRegOP , lo ,


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < <ISA_LIT>SinglePathInfo >


<s> void print<ISA_LIT>NOneImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) const { O << -