<s> Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ HiIndex ^ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = - <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; if ( HiIndex >= <NUM_LIT> ) { Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask1 [ <NUM_LIT> ] ) ; } else { Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = HiIndex & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; Mask1 [ <NUM_LIT> ] = PermMask [ <NUM_LIT> ] ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; if ( Mask1 [ <NUM_LIT> ] >= <NUM_LIT> ) Mask1 [ <NUM_LIT> ] += <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V2 , V1 , & Mask1 [ <NUM_LIT> ] ) ; } } Locs . clear ( ) ; Locs . resize ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > LoMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > HiMask ( <NUM_LIT> , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > * MaskPtr = & LoMask ; unsigned MaskIdx = <NUM_LIT> ; unsigned LoIdx = <NUM_LIT> ; unsigned HiIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) { MaskPtr = & HiMask ; MaskIdx = <NUM_LIT> ; LoIdx = <NUM_LIT> ; HiIdx = <NUM_LIT> ; } int Idx = PermMask [ i ] ; if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( - <NUM_LIT> , - <NUM_LIT> ) ; } else if ( Idx < <NUM_LIT> ) { Locs [ i ] = std :: make_pair ( MaskIdx , LoIdx ) ; ( * MaskPtr ) [ LoIdx ] = Idx ; LoIdx ++ ; } else { Locs [ i ] = std :: make_pair ( MaskIdx , HiIdx ) ; ( * MaskPtr ) [ HiIdx ] = Idx ; HiIdx ++ ; } } SDValue LoShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & LoMask [ <NUM_LIT> ] ) ; SDValue HiShuffle = DAG . getVectorShuffle ( VT , dl , V1 , V2 , & HiMask [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> >


<s> const LLT Ty = Query . Types [ TypeIdx ] ; const LLT EltTy = Ty . getElementType ( ) ; const int Size = Ty . getSizeInBits ( ) ; const int EltSize = EltTy . getSizeInBits (


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( canUseRedZone ( MF )


<s> MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst , CoverageInfo ) ) return false ; } MachineInstr & CopyInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( )

, TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( DefReg ) ;


<s> if ( ! I . isDebugInstr ( ) && ! I . isUnconditionalBranch ( ) ) return false ; } assert ( MBB . succ_size ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock * Succ = * MBB . succ_begin ( ) ; MachineBasicBlock * FallThrough = nullptr ; while ( ! MBB . predecessors ( ) . empty ( ) ) { MachineBasicBlock * P = * MBB . pred_begin ( ) ; if ( GetFallThroughSucc ( P ) == & MBB ) FallThrough = P ; P -> ReplaceUsesOfBlockWith ( & MBB , Succ ) ; } MBB . removeSuccessor ( Succ ) ; if ( LIS ) { for ( auto & I : MBB . instrs ( ) ) LIS -> RemoveMachineInstrFromMaps ( I ) ; } MBB . clear ( ) ; MBB . eraseFromParent ( ) ; if ( FallThrough && ! FallThrough -> isLayoutSuccessor ( Succ ) ) { if ( ! GetFallThroughSucc ( Succ ) ) { MachineFunction * MF = FallThrough -> getParent ( ) ; MachineFunction :: iterator FallThroughPos ( FallThrough


<s> const char * hsa_error_msg ; hsa_fns . hsa_status_string_fn ( status , & hsa_error_msg ) ; fprintf ( stderr , <STR_LIT> , str , hsa_error_msg ) ; exit ( <NUM_LIT>


<s> bool hasDomain ( unsigned domain ) const { return AvailableDomains & ( <NUM_LIT>


<s> static rtx mmix_function_arg ( cumulative_args_t argsp , const function_arg_info


<s> uint64_t NumBits1 = VT1 . getFixedSizeInBits ( ) ; uint64_t NumBits2 = VT2 . getFixedSizeInBits ( ) ; return NumBits1


<s> O << <STR_LIT> << MI -> getOperand (


<s> void <ISA_LIT>BitcodeWriter :: writeDIObjCProperty ( const DIObjCProperty * N , SmallVectorImpl < uint64_t > & Record ,


<s> SDValue PassThru = N -> getPassThru ( ) ; SDLoc dl ( Op ) ; if ( MaskVT . getVectorElementType ( ) != <STR_LIT> ) { if ( PassThru . isUndef ( ) || <STR_LIT> ( PassThru . getNode ( ) ) ) return Op ; SDValue NewLoad = DAG . getMaskedLoad ( VT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , getZeroVector ( VT , Subtarget , DAG , dl ) , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Select = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , NewLoad , PassThru ) ; return DAG . getMergeValues ( { Select , NewLoad . getValue ( <NUM_LIT> ) } , dl ) ; } assert ( ( ! N -> isExpandingLoad ( ) || Subtarget . hasAVX512 ( ) ) && <STR_LIT> ) ; assert ( ( ! N -> isExpandingLoad ( ) || ScalarVT . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ScalarVT . getSizeInBits ( ) >= <NUM_LIT> || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> (


<s> if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) .


<s> for ( unsigned i = <NUM_LIT> ; i < sizeof ( Bops ) / sizeof ( Bops [ <NUM_LIT> ] ) ; ++ i ) if ( MI -> getOpcode ( ) == Bops [ i ] ) { BI = MI ; ++ insInBops ; } } } if ( insInBops != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << insInBops << <STR_LIT> ) ; return nullptr ; } return


<s> unsigned e = static_cast < unsigned > ( MI -> getOperand ( OpNo ) .


<s> return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV )


<s> if ( Src1 -> getOpcode ( ) != <STR_LIT> || ! Src1 -> hasOneUse ( ) || Src1 -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) ) ; ReplaceUses ( N , Result ) ; return Result


<s> bool AMDGPUAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MF . setAlignment ( <NUM_LIT> ) ; SetupMachineFunction ( MF ) ; MCContext & Context = getObjFileLowering ( ) . getContext ( ) ; MCSectionELF * ConfigSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( ConfigSection ) ; const AMDGPUSubtarget & STM = MF . getSubtarget < AMDGPUSubtarget > ( ) ; <ISA_LIT>ProgramInfo KernelInfo ; if ( STM . isAmdHsaOS ( ) ) { get<ISA_LIT>ProgramInfo ( KernelInfo , MF ) ; EmitAmdKernelCodeT ( MF , KernelInfo ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> << ( MF . getAlignment ( ) - <NUM_LIT> ) ) ; } else if ( STM . getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { get<ISA_LIT>ProgramInfo ( KernelInfo , MF ) ; EmitProgramInfo<ISA_LIT> ( MF , KernelInfo ) ; } else { EmitProgramInfoR600 ( MF ) ; } DisasmLines . clear ( ) ; HexLines . clear ( ) ; DisasmLineMaxLen = <NUM_LIT> ; EmitFunctionBody ( ) ; if ( isVerbose ( ) ) { MCSectionELF * CommentSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( CommentSection ) ; if ( STM . getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { OutStreamer -> emitRawComment ( <STR_LIT> , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . CodeLen )


<s> unsigned UseIdx ; int CommuteIdx = - <NUM_LIT> ; bool TieOps = false ; switch ( UseOpc ) { case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; default : return false ; } if ( CommuteIdx != - <NUM_LIT> ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; if ( TieOps ) UseMI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; UseMI . getOperand ( UseIdx ) . ChangeToImmediate ( ImmVal ) ; if ( DeleteDef ) DefMI . eraseFromParent (


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; unsigned Flags = MI . getFlags ( ) ; B . setInstr ( MI ) ; auto Log2Operand = B . buildFLog2 ( Ty , Src , Flags ) ; auto Log2BaseInvertedOperand = B . buildFConstant ( Ty , Log2BaseInverted ) ; B . buildFMul ( Dst , Log2Operand


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( )


<s> if ( Subtarget -> hasV6T2Ops ( ) && isUInt < <NUM_LIT> > ( CI -> getZExtValue ( ) ) ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( ! Subtarget -> useConstIslands ( ) && Subtarget -> hasV6T2Ops ( ) && VT == <STR_LIT> ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( ! Subtarget -> useConstIslands ( ) ) return false ; if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI .


<s> if ( SDValue Res = combineVectorCompareAndMaskUnaryOp ( N , DAG ) ) return Res ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = Op0 . getValueType ( ) ; if ( InVT . isVector ( ) && InVT . getScalarSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = <STR_LIT> ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; if ( DCI . isBeforeLegalize ( ) || TruncVT != <STR_LIT> ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } assert ( InVT == <STR_LIT> && <STR_LIT> ) ; SDValue Cast = DAG . getBitcast ( <STR_LIT> , Op0 ) ; SDValue Shuf = DAG . getVectorShuffle ( <STR_LIT> , dl , Cast , Cast , { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Shuf ) ; } } if ( ! Subtarget . useSoftFloat ( ) && Subtarget . hasX87 ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue


<s> SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; EVT SubVT = <STR_LIT> ( ElType , NumElts ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT ) ; for ( unsigned i = Index , j = <NUM_LIT> ; i < ( Index + NumElts ) ; i ++ , j ++ ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV1 , DAG . getIntPtrConstant ( i , dl ) ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT , SubVec , Elt , DAG

. getConstant ( j , dl , <STR_LIT> ) ) ;


<s> if ( speed && ! CONSTANT_P ( addr ) ) cost += ( mode == QImode ) ? <NUM_LIT> : GET_MODE_SIZE ( mode ) ; } return


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { O << '%' ; unsigned Reg = MO . getReg ( ) ; if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { EVT VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; } O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ; return ; } case MachineOperand :: MO_Immediate : O << '$' << MO . getImm ( ) ; return ; case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : { O << '$' ; printSymbolOperand ( MO ,


<s> if ( TARGET_CBCOND && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && ( GET_MODE ( operands [ <NUM_LIT> ] ) == SImode || ( TARGET_ARCH64 && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) ) && ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT || SPARC_SIMM5_P ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) ) { emit_cbcond_insn ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } if ( TARGET_ARCH64 && operands [ <NUM_LIT> ] == const0_rtx && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) { emit_v9_brxx_insn ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [


<s> for ( i = <NUM_LIT> ; i < nregs - <NUM_LIT> ; i ++ ) vec [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , first_val_regnum + i ) , GEN_INT ( ( i + <NUM_LIT> ) * BITS_PER_UNIT ) ) ; vec [ nregs - <NUM_LIT> ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( cmode , first_val_regnum + nregs -


<s> return ( __m128d ) __builtin_ia32_fixupimmpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , (


<s> raw_string_ostream OS ( Code ) ; Func = & F ; return GenJavaClass (


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { EmitByte ( Val & <NUM_LIT> , OS )


<s> if ( LoadInst * LMemI = dyn_cast < LoadInst > ( MemI ) ) { return LMemI -> getPointerOperand ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( MemI ) ) { return SMemI -> getPointerOperand ( ) ; } else if ( IntrinsicInst * IMemI = dyn_cast < IntrinsicInst > ( MemI ) ) { if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> || IMemI -> getIntrinsicID ( ) == <STR_LIT> ) return IMemI -> getArgOperand ( <NUM_LIT> ) ; if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> ) return IMemI -> getArgOperand (


<s> rtx nval = gen_rtx_REG ( SImode , <NUM_LIT> ) ; emit_insn ( gen_movsi ( nval , val ) ) ; val = nval ; } if ( direction > <NUM_LIT> ) insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , val ) ; else insn = gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , val ) ; emit_insn ( insn )


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( parseSymbolicImmVal ( Expr ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Expr = <ISA_LIT>MCExpr :: Create ( Expr , <ISA_LIT>MCExpr :: VK_ABS_PAGE , getContext ( ) ) ; } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( DarwinRefKind != MCSymbolRefExpr :: VK_PAGE && DarwinRefKind != MCSymbolRefExpr :: VK_GOTPAGE && DarwinRefKind != MCSymbolRefExpr :: VK_TLVPPAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOT_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ; return


<s> return SYMBOL_REF_TLS_MODEL ( x ) == <NUM_LIT> ; case CONST_DOUBLE : if ( x == CONST0_RTX ( mode ) ) return true ; if ( FLOAT_MODE_P ( mode ) ) return false ; goto do_integer ; case CONST_VECTOR : if ( x == CONST0_RTX ( mode ) ) return true ; if ( GET_MODE_CLASS ( mode ) != MODE_VECTOR_INT ) return false ; if ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) return false ; goto do_integer ; case CONST_INT


<s> else cond = NULL_RTX ; if ( subtargets || code == SET || ( GET_CODE ( target ) == REG && GET_CODE ( source ) == REG && REGNO ( target ) != REGNO ( source ) ) ) { if ( ! after_arm_reorg && ! cond && ( arm_gen_constant ( code , mode , NULL_RTX , val , target , source , <NUM_LIT> , <NUM_LIT> ) > arm_constant_limit + ( code != SET ) ) ) { if ( code == SET ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , GEN_INT ( val ) ) ) ; return


<s> } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; } else assert ( <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != MaxElts ; ++ i ) { if ( SVN -> getMaskElt ( i ) < <NUM_LIT> ) continue ; unsigned SrcElt = SVN -> getMaskElt ( i ) ; if ( monotonic ) { if ( SrcElt >= V2EltIdx0 ) { if ( <NUM_LIT> >= ( ++ EltsFromV2 ) ) { V2Elt = ( V2EltIdx0 - SrcElt ) << <NUM_LIT> ; } } else if ( CurrElt != SrcElt ) { monotonic = false ; } ++ CurrElt ; } if ( rotate ) { if ( PrevElt > <NUM_LIT> && SrcElt < MaxElts ) { if ( ( PrevElt == SrcElt - <NUM_LIT> ) || ( PrevElt == MaxElts - <NUM_LIT> && SrcElt == <NUM_LIT> ) ) { PrevElt = SrcElt ; if ( SrcElt == <NUM_LIT> ) V0Elt = i ; } else { rotate = false ; } } else if ( PrevElt == <NUM_LIT> ) { PrevElt = SrcElt ; } else { rotate = false ; } } } if ( EltsFromV2 == <NUM_LIT> && monotonic ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue InitTempReg = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , VReg , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue ShufMaskOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getTargetConstant ( V2Elt , <STR_LIT> ) , DAG . getCopyFromReg ( InitTempReg , dl , VReg , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V2 , V1 , ShufMaskOp ) ; } else if ( rotate ) { int rotamt = ( MaxElts - V0Elt ) * EltVT . getSizeInBits ( ) / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , DAG . getConstant ( rotamt , <STR_LIT> ) ) ; } else


<s> return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT>


<s> if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; if ( SDValue R = combinePTESTCC ( EFLAGS , CC , DAG , Subtarget ) ) return R ; return combineSetCCAtomicArith ( EFLAGS , CC , DAG , Subtarget


<s> if ( VectorList . ElementKind != ElementKind ) return false ; if ( VectorList . IsSVE )


<s> bool aarch64_move_imm ( HOST_WIDE_INT val , machine_mode mode ) { if ( aarch64_movw_imm ( val , mode ) || aarch64_movw_imm ( ~ val , mode )


<s> bool isImm0_508s4 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue (


<s> } else base = XEXP ( ref , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PLUS ) offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) , base =


<s> if ( Value & ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) ) return static_cast < int64_t > ( Value ) - ( <NUM_LIT> << BitWidth ) ; else return


<s> if ( ! Name . equals ( Prefix ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; unsigned Val = <NUM_LIT> ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { if ( I != <NUM_LIT> ) { if ( getLexer ( ) . is ( AsmToken :: RBrac ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; } if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return MatchOperand_ParseFail ; int64_t Op ; if ( getParser ( ) . parseAbsoluteExpression ( Op ) ) return MatchOperand_ParseFail ; if ( Op != <NUM_LIT> && Op

!= <NUM_LIT> ) return MatchOperand_ParseFail ;


<s> bool targetSchedulesPostRAScheduling ( ) const override


<s> virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = true ) { return


<s> SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ,

DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 ) , Mask ) ) ;


<s> return isIntImmediate ( N . getNode ( ) ,


<s> struct s390_address ad ; gcc_assert ( GET_CODE ( src ) == PLUS ) ; gcc_assert ( GET_MODE ( src ) == Pmode ) ; sum1 = find_replacement ( & XEXP ( src , <NUM_LIT> ) ) ; sum2 = find_replacement ( & XEXP ( src , <NUM_LIT> ) ) ; src = gen_rtx_PLUS ( Pmode , sum1 , sum2 ) ; if ( ! s390_decompose_address ( src , & ad ) || ( ad . base && ! REGNO_OK_FOR_BASE_P ( REGNO ( ad . base ) ) ) || ( ad . indx && ! REGNO_OK_FOR_INDEX_P ( REGNO ( ad . indx ) ) ) ) { if ( true_regnum ( sum1 ) < <NUM_LIT> || true_regnum ( sum1 ) > <NUM_LIT> ) { emit_move_insn ( scratch , sum1 ) ; sum1 = scratch ; } if ( true_regnum ( sum2 ) < <NUM_LIT> || true_regnum ( sum2 ) > <NUM_LIT> ) { emit_move_insn ( scratch , sum2 ) ; sum2 = scratch ; } if ( sum1 == scratch && sum2 == scratch ) { debug_rtx ( src ) ; gcc_unreachable ( ) ; } src = gen_rtx_PLUS ( Pmode , sum1 , sum2 ) ; } s390_load_address ( target


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isMoveInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SrcSubIdx , unsigned & DstSubIdx ) const { SrcSubIdx = DstSubIdx = <NUM_LIT> ; unsigned oc = MI . getOpcode ( ) ; switch ( oc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case


<s> assert ( opcode == <STR_LIT> || opcode == <STR_LIT> ) ; SDValue SrcReg64 = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; SDValue Lo32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; Hi32 = DAG . getNode ( opcode , dl , <STR_LIT> , Hi32 ) ; SDValue DstReg64 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF


<s> <STR_LIT> llvm :: getITInstrPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ; return getInstrPredicate ( MI , PredReg


<s> bool Eval = constToInt ( LSL . Values [ i ] , LoVs [ i ] ) ; if ( ! Eval ) return false ; assert ( LoVs [ i ] . getBitWidth ( ) == <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < HN ; ++ i ) { bool Eval = constToInt ( LSH . Values [ i ] , HiVs [ i ] ) ; if ( ! Eval ) return false ; assert ( HiVs [ i ] . getBitWidth ( ) == <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < HiVs . size ( ) ; ++ i ) { APInt HV = HiVs [ i ] . zext ( <NUM_LIT> ) << <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LoVs . size ( ) ; ++ j ) { APInt LV = LoVs [ j ] . zext ( <NUM_LIT>


<s> ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type )


<s> return sh_recog_treg_set_expr_reent_count >


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset


<< <NUM_LIT> ) | __C , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> , __R ) ;


<s> static void addPipelineEdges ( const llvm :: ArrayRef < InstructionClass * > PipelineOrder , ScheduleDAGInstrs * DAG ) { for ( int i = <NUM_LIT> ; i < ( int ) PipelineOrder . size ( ) - <NUM_LIT> ; i ++ ) { auto StageA = PipelineOrder [ i ] ; for ( int j = i + <NUM_LIT> ; j < ( int ) PipelineOrder . size ( ) ; j ++ ) { auto StageB = PipelineOrder [ j ] ; for ( auto SUnitA : StageA -> Collection ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; DAG -> dumpNode ( * SUnitA ) ; ) ; for ( auto SUnitB : StageB -> Collection ) { if ( DAG -> canAddEdge ( SUnitB , SUnitA ) ) { DAG -> addEdge ( SUnitB , SDep ( SUnitA , SDep :: Artificial ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; DAG -> dumpNode ( * SUnitB ) ; ) ; } else { LLVM_DEBUG ( dbgs (


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF


<s> const GlobalValue * GV = GSD -> getGlobal ( ) ; if ( ( GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS && shouldUseLDSConstAddress ( GV ) ) || GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS || GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { if ( GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS && GV -> hasExternalLinkage ( ) ) { Type * Ty = GV -> getValueType ( ) ; if ( DAG . getDataLayout ( ) . getTypeAllocSize ( Ty ) . isZero ( ) ) { assert ( PtrVT == <STR_LIT> && <STR_LIT> ) ; MFI -> setDynLDSAlign ( DAG . getDataLayout ( ) , * cast < GlobalVariable > ( GV ) ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT ) , <NUM_LIT> ) ; } } return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op ,


<s> return ( _TEXASRU_EXTRACT_BITS ( texasru , <NUM_LIT> , <NUM_LIT> ) ) ? <NUM_LIT>


<s> MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel ( JTI ) ; OutStreamer -> EmitLabel ( JTISymbol ) ; OutStreamer -> EmitDataRegion ( MCDR_DataRegionJT32 ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( Expr ,


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass (


<s> if ( HaveReg1 && Reg1 . Group != RegGR && Reg1 . Group != RegV && parseAddressRegister ( Reg1 ) ) return true ; if ( HaveReg2 && parseAddressRegister ( Reg2 ) ) return true ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; if ( HaveReg1 || HaveReg2 || Length ) Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( StartLoc , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; return false


<s> DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec : { Offset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; break ; } case TLSModel :: LocalExec : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; break ; } } return DAG . getNode ( <STR_LIT> , DL , PtrVT


<s> } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ; SDValue Success = DAG . getNode ( <STR_LIT> , DL , Op -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveNops ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHSaveReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHSaveXMM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSEHPushFrame ( DirectiveID . getLoc ( ) ) ; return


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return &


<s> static bool IsRegDependence ( const SDep :: Kind DepType ) { return ( DepType == SDep :: Data || DepType == SDep ::


<s> bool <ISA_LIT>AsmPrinter :: doFinalization ( Module & M ) { for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I ) ; O << '\n' ; return AsmPrinter :: doFinalization


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( ! DisableLeafProc && isLeafProc


<s> timevar_push ( TV_MACH_DEP ) ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) replace_constant_pool_with_broadcast ( insn


<s> op1 = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; op2 = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; constant_op = ( CONSTANT_P ( op1 ) ) ? op1 : op2 ; tmp = gen_reg_rtx ( GET_MODE ( constant_op ) ) ; emit_move_insn ( tmp , constant_op ) ; if ( CONSTANT_P ( op1 ) ) new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , tmp , op2 ) ; else new_rtx = gen_rtx_VEC_CONCAT ( V2SFmode , op1 , tmp ) ; emit_move_insn ( target , new_rtx )


<s> Value = adjustFixupValue ( Fixup , Value , & Asm . getContext ( ) ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value <<= Info . TargetOffset ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; uint32_t Offset = Fixup . getOffset


<s> break ; case COMPLEX_TYPE : mode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( mode != DFmode && mode != SFmode && mode != TFmode ) return - <NUM_LIT> ; if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case VECTOR_TYPE : size = int_size_in_bytes ( type ) ; switch ( size ) { case <NUM_LIT> : mode = V2SImode ; break ; case <NUM_LIT> : mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count = count > sub_count ? count : sub_count ; } if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE (


<s> PairMapType Memo ; for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) pruneUsesTooFar ( I -> first , RPO , Memo ) ; pruneEmptyLists ( ) ; for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I )


<s> enum rtx_code test = GET_CODE ( operands [ <NUM_LIT> ] ) ; rtx cc_reg = frv_emit_comparison ( test , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; machine_mode cc_mode = GET_MODE ( cc_reg ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; test_rtx = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ; if_else = gen_rtx_IF_THEN_ELSE ( cc_mode , test_rtx , label_ref ,


<s> inline SDValue getI32Imm ( unsigned Imm , const SDLoc & DL ) { return CurDAG -> getTargetConstant ( Imm , DL ,


<s> LiveInterval & LI = LIS . getInterval ( Reg ) ; ShrinkToUses ( LI , LIS ) ; IsDead = ! LI . liveAt ( LIS . getInstructionIndex ( Def ) . getDeadSlot ( ) ) ; } if ( IsDead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SlotIndex Idx = LIS . getInstructionIndex ( Def ) . getRegSlot ( ) ; LIS . removePhysRegDefAt ( <STR_LIT> , Idx ) ; LIS . removeInterval ( Reg ) ; LIS . RemoveMachineInstrFromMaps ( Def ) ; Def . eraseFromParent ( ) ; MoveDebugValues ( Reg , & * Insert , MBB , MRI ) ; UpdateDebugValuesReg ( Reg , NewReg , MBB , MRI ) ; } else { CloneDebugValues ( Reg , & * Insert , NewReg , MBB , MRI , TII ) ; } return Clone


<s> case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : { unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7_6 = ( Value >> <NUM_LIT> )


<s> machine_mode ccm = GET_MODE ( XEXP ( cond , <NUM_LIT> ) ) ; enum rtx_code code = reverse_condition ( GET_CODE ( cond ) ) ; if ( code == UNKNOWN || ccm == CC_FP_GTmode || ccm == CC_FP_GEmode ) code

= reverse_condition_maybe_unordered ( GET_CODE ( cond ) ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { return &


<s> unsigned postOffset ( ) const { return Offset +


<s> return ( __m128i ) __builtin_ia32_prolq128_mask ( ( __v2di ) __A , __B , ( __v2di ) _mm_setzero_si128 ( ) , (


<s> int16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> vec_char16 av ; av = ( vec_char16 ) ( a ) ; return ( ( qword ) ( vec_unpackh ( vec_perm ( av , av , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> auto PtrInfo = MachinePointerInfo :: getCapTable ( DAG . getMachineFunction ( ) ) ; assert ( Ty . isFatPointer ( ) ) ; auto Result = getDataFromCapTable ( N , SDLoc ( N ) , Ty , DAG , DAG . getEntryNode ( ) , PtrInfo ) ; assert ( Result . getValueType ( ) == Ty ) ; return Result ; } if ( ! isPositionIndependent ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering (


<s> Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( TT . isOSDarwin ( ) || ReserveX18 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( hasBasePointer (


<s> static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) { addr = gen_rtx_HIGH ( Pmode , riscv_unspec_address (


<s> return __builtin_arm_stc2 ( __coproc ,


<s> ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , integer , GET_PENDING_INT ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , integer , GET_INT_PRIORITY ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , integer , SET_INT_PRIORITY ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , void , integer , CLR_PENDING_HWINT ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , void , integer , SET_TRIG_LEVEL ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , void , integer , SET_TRIG_EDGE ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , integer , GET_TRIG_TYPE ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , ptr_uint , LLW ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , ptr_uint , LWUP ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , char , ptr_uchar , LBUP ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , ptr_uint , unsigned , SCW ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , ptr_uint , unsigned , SWUP ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , ptr_uchar , char , SBUP ) ; ADD_NDS32_BUILTIN0 ( <STR_LIT> , void , CCTL_L1D_INVALALL ) ; ADD_NDS32_BUILTIN0 ( <STR_LIT> , void , CCTL_L1D_WBALL_ALVL ) ; ADD_NDS32_BUILTIN0 ( <STR_LIT> , void , CCTL_L1D_WBALL_ONE_LVL ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , ptr_uint , CCTL_VA_LCK ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , unsigned , CCTL_IDX_WBINVAL ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , ptr_uint , CCTL_VA_WBINVAL_L1 ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , void , integer , ptr_uint , CCTL_VA_WBINVAL_LA ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , integer , unsigned , CCTL_IDX_READ ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , integer , unsigned , unsigned , CCTL_IDX_WRITE ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_uchar , unsigned , integer , DPREF_QW ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_ushort , unsigned , integer , DPREF_HW ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_uint , unsigned , integer , DPREF_W ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_ulong , unsigned , integer , DPREF_DW ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , integer , integer , ABS ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , integer , integer , integer , AVE ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BCLR ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BSET ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BTGL ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , unsigned , unsigned , BTST ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , unsigned , integer , unsigned , CLIP ) ; ADD_NDS32_BUILTIN2 ( <STR_LIT> , integer , integer , unsigned , CLIPS ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , unsigned , CLZ ) ; ADD_NDS32_BUILTIN1 ( <STR_LIT> , unsigned , unsigned , CLO ) ; ADD_NDS32_BUILTIN3 ( <STR_LIT> , void , ptr_uint , unsigned , ptr_uint , BSE


? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ;


<s> return ( isRegInClass ( Reg , & <STR_LIT> ) ||


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumBits = VT . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnesValue ( NumBits


<s> assert ( hasStdExtV ( ) && <STR_LIT> ) ; assert ( RVVVectorLMULMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorLMULMax ) &&


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfaRegister


<s> bool shouldIgnoreForPipelining ( const MachineInstr * MI ) const override { return MI ==


<s> for ( int Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { int64_t Chunk = getChunk ( UImm , Idx ) ; Chunk = ( Chunk << <NUM_LIT> ) >> <NUM_LIT> ; if ( isStartChunk ( Chunk ) ) StartIdx = Idx ; else if ( isEndChunk ( Chunk ) ) EndIdx = Idx ; } if ( StartIdx == NotSet || EndIdx == NotSet ) return false ; uint64_t Outside = <NUM_LIT> ; uint64_t Inside = Mask ; if ( StartIdx > EndIdx ) { std :: swap ( StartIdx , EndIdx ) ; std :: swap ( Outside , Inside ) ; } uint64_t OrrImm = UImm ; int FirstMovkIdx = NotSet ; int SecondMovkIdx = NotSet ; for ( int Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { const uint64_t Chunk = getChunk ( UImm , Idx ) ; if ( ( Idx < StartIdx || EndIdx < Idx ) && Chunk != Outside ) { OrrImm = updateImm ( OrrImm , Idx , Outside == <NUM_LIT> ) ; if ( FirstMovkIdx == NotSet ) FirstMovkIdx = Idx ; else SecondMovkIdx =


<s> auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I =


<s> ProgmemDataSection = Ctx . getELFSection ( <STR_LIT> ,

ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ;


<s> static bool mips_matching_cpu_name_p ( const char * canonical , const char * given ) { if ( mips_strict_matching_cpu_name_p ( canonical , given ) ) return true ; if ( TOLOWER ( * given ) == 'r' ) given ++ ; if ( ! ISDIGIT ( * given ) ) return false ; if ( TOLOWER ( canonical [ <NUM_LIT> ] ) == 'v' && TOLOWER ( canonical [ <NUM_LIT> ] ) == 'r' ) canonical += <NUM_LIT> ; else if ( TOLOWER ( canonical [ <NUM_LIT> ] ) == 'r' && TOLOWER ( canonical [ <NUM_LIT> ] )


<s> void emitFill ( const MCExpr & NumBytes , uint64_t FillValue , SMLoc Loc ) override { EmitMappingSymbol ( <STR_LIT>


<s> unsigned AddrReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) ,


<s> <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val .


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { SupportsDebugInformation = true ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT>


<s> if ( MI . isBranch ( ) || MI . isReturn ( ) ) { RemovedSize += getInstSizeInBytes ( MI ) ; MI . eraseFromParent ( ) ; ++ Count


<s> bool <ISA_LIT>AsmParser :: ParseToken ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , AsmToken :: TokenKind Kind ) { MCAsmLexer & Lexer = getLexer ( ) ; if ( Lexer . isNot ( Kind ) ) { return Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Lexer . getTok ( ) . getString ( ) , Lexer . getLoc ( ) ) ) ; Lexer . Lex ( ) ; return false


<s> MCAsmBackend * create<ISA_LIT>AsmBackend ( Target const & T , MCRegisterInfo


<s> Function * Caller = CS . getCaller ( ) ; if ( ! Callee || Callee -> isDeclaration ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . isNoInline ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; TargetTransformInfo & TTI = TTIWP -> getTTI ( * Callee ) ; if ( ! TTI . areInlineCompatible ( Caller , Callee ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . hasFnAttr ( Attribute :: AlwaysInline ) ) { auto IsViable = isInlineViable ( * Callee ) ; if ( IsViable . isSuccess ( ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; return llvm :: InlineCost :: getNever ( IsViable . getFailureReason ( ) ) ; } if ( isWrapperOnlyCall ( CS ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; InlineParams LocalParams = Params


<s> parse_codes result = PC_OK ; diag = & ovld_diag ; if ( ! advance_line ( ovld_file ) ) return PC_OK ; while ( result == PC_OK ) result = parse_ovld_stanza (


<s> auto InsPt = MachineFunction :: iterator ( MBB ) ; ++ InsPt ; std :: vector < std :: pair < MachineBasicBlock * , unsigned >> TargetMBBs ; const DebugLoc & DL = JTInst -> getDebugLoc ( ) ; MachineOperand Selector = JTInst -> getOperand ( <NUM_LIT> ) ; const GlobalValue * CombinedGlobal = JTInst -> getOperand ( <NUM_LIT> ) . getGlobal ( ) ; auto CmpTarget = [ & ] ( unsigned Target ) { if ( Selector . isReg ( ) ) MBB -> addLiveIn ( Selector . getReg ( ) ) ; BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( CombinedGlobal , JTInst -> getOperand ( <NUM_LIT> + <NUM_LIT> * Target ) . getImm ( ) ) . addReg ( <NUM_LIT> ) ; BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( Selector ) . addReg ( <STR_LIT> ) ; } ; auto CreateMBB = [ & ] ( ) { auto * NewMBB = MF -> CreateMachineBasicBlock ( BB ) ; MBB -> addSuccessor ( NewMBB ) ; if ( ! MBB -> isLiveIn ( <STR_LIT> ) ) MBB -> addLiveIn ( <STR_LIT> ) ; return NewMBB ; } ; auto EmitCondJump = [ & ] ( unsigned CC , MachineBasicBlock * ThenMBB ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( ThenMBB ) . addImm ( CC ) ; auto * ElseMBB = CreateMBB ( ) ; MF -> insert ( InsPt , ElseMBB ) ; MBB = ElseMBB ; MBBI = MBB -> end ( ) ; } ; auto EmitCondJumpTarget = [ & ] ( unsigned CC , unsigned Target ) { auto * ThenMBB = CreateMBB ( ) ; TargetMBBs . push_back ( { ThenMBB , Target } ) ; EmitCondJump ( CC , ThenMBB ) ; } ; auto EmitTailCall = [ & ] ( unsigned Target ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . add ( JTInst -> getOperand ( <NUM_LIT> + <NUM_LIT> * Target ) ) ; } ; std :: function < void ( unsigned , unsigned ) > EmitBranchFunnel = [ & ] ( unsigned FirstTarget , unsigned NumTargets ) { if ( NumTargets == <NUM_LIT> ) { EmitTailCall ( FirstTarget ) ; return ; } if ( NumTargets == <NUM_LIT> ) { CmpTarget ( FirstTarget + <NUM_LIT>


<s> SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT ValVT = Val . getValueType ( ) ; dbgs ( ) << <STR_LIT> ; Val . dump ( ) ; if ( VT == <STR_LIT> ) { assert ( ValVT == <STR_LIT> && <STR_LIT> ) ; return EmitPair ( DL , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> )


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMatrixRegister ( unsigned RegNum , unsigned ElementWidth , MatrixKind Kind , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_MatrixRegister , Ctx ) ; Op -> MatrixReg . RegNum = RegNum ; Op -> MatrixReg . ElementWidth = ElementWidth ; Op -> MatrixReg . Kind = Kind ; Op -> StartLoc = S ; Op -> EndLoc =


<s> fcfg . printNode ( * ( * I ) -> ipdom ) << <STR_LIT> ; for ( Node :: child_iterator SI = ( * I ) -> succs_begin ( ) , SE = ( * I ) -> succs_end ( ) ; SI != SE ; ++ SI ) { fcfg . printNode ( * * SI )


<s> if ( reg_classes_intersect_p ( from , CR_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; if ( reg_classes_intersect_p ( to , CR_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; if ( from == MEM_REGS || to == MEM_REGS ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( reg_classes_intersect_p ( from , MEM_REGS ) || reg_classes_intersect_p ( to , MEM_REGS ) ) cost += COSTS_N_INSNS


<s> if ( ! isGFX10 ( ) && ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) return MatchOperand_NoMatch ; if ( ! isVI ( ) && ! isGFX9 ( ) && ( Prefix == <STR_LIT> || Prefix == <STR_LIT> || Prefix == <STR_LIT> || Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return MatchOperand_ParseFail ; if ( Prefix == <STR_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Int ) || ! ( <NUM_LIT> <= Int && Int <= <NUM_LIT> ) ) return MatchOperand_ParseFail ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; int64_t Temp ; if ( getParser ( ) . parseAbsoluteExpression ( Temp ) || ! ( <NUM_LIT> <= Temp && Temp <= <NUM_LIT> ) ) return MatchOperand_ParseFail ; const int shift = i * <NUM_LIT> + <NUM_LIT> ; Int += ( Temp << shift ) ; } if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; } else { Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Int ) ) return MatchOperand_ParseFail ; if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_SHL0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_SHR0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_ROR0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_SHL1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_ROL1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_SHR1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl ,

VA . getLocReg ( ) , ValToCopy , Flag ) ;


<s> unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) )


<s> assert ( WavesPerEU != <NUM_LIT> ) ; unsigned MaxNumVGPRs = alignDown ( getTotalNumVGPRs ( Features ) / WavesPerEU , getVGPRAllocGranule ( Features


<s> case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI .


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; if ( Lane == <NUM_LIT> ) BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Ws , <NUM_LIT> , <STR_LIT> ) ; else { unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT>

) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> void <ISA_LIT>GNULDBackend :: defineGOTSymbol ( IRBuilder & pBuilder ) { if ( m_pGOTSymbol != NULL ) { pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( * ( m_pGOTPLT ->

begin ( ) ) , <NUM_LIT> ) , ResolveInfo :: Hidden ) ;


<s> ConstantSDNode * FalseC = dyn_cast < ConstantSDNode > ( False ) ; if ( ! FalseC ) return SDValue ( ) ; const SDLoc DL ( N ) ; if ( ! FalseC -> getZExtValue ( ) ) { <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SetCC = DAG . getSetCC ( DL , SetCC . getValueType ( ) , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , <STR_LIT> ( CC , true ) ) ; return DAG . getNode ( <STR_LIT> , DL , FalseTy , SetCC , False , True ) ; } SDValue True = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * TrueC = dyn_cast < ConstantSDNode > ( True ) ; if ( ! TrueC || ! True . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; if ( True . getValueType ( ) == <STR_LIT> ) return SDValue (


<s> Size = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * <NUM_LIT> ) , ValVReg ) -> getOperand ( <NUM_LIT> ) .


<s> else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ,


<s> BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CfCount ) ; for ( MachineInstr * MI : Clause . second ) BB -> splice (


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X ,


<s> FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumbFunction ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( AFI -> isThumb2Function ( ) && FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } if ( RegInfo -> hasBasePointer ( MF ) ) { FrameReg = RegInfo -> getBaseRegister ( ) ; Offset -= SPAdj ; } return


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = {


<s> typename __altivec_bool_ret < vec_step ( T ) > :: __ret \ NAME ( T a1 , U a2


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { O << <STR_LIT> <<


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MCII . getName ( Opcode ) << <STR_LIT> << Opcode << <STR_LIT> ) ; const uint8_t * Beads = getGenInstrBeads ( MI ) ; if ( ! Beads || ! * Beads ) { llvm_unreachable ( <STR_LIT> ) ; } uint64_t Buffer = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; unsigned ThisByte = <NUM_LIT> ; for ( uint8_t Bead = * Beads ; Bead ; Bead = * ++ Beads ) { if ( ! ( Bead & <NUM_LIT> ) ) { switch ( Bead >> <NUM_LIT> ) { case <STR_LIT> : continue ; } } switch ( Bead & <NUM_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> ,


) _mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( errs ( ) ) ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; Offset += StackSize ; unsigned FrameReg = getFrameRegister (


<s> static inline bool isVPTOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>

|| Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; bool FP = hasFP ( MF ) ; if ( FP ) { unsigned FramePtr = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FramePtr ) ; } int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; FrameSize /= <NUM_LIT> ; bool isU6 = isImmU6 ( FrameSize ) ; if ( ! isU6 && ! isImmU16 ( FrameSize ) ) { report_fatal_error ( <STR_LIT> + Twine ( FrameSize )


<s> unsigned getWaitcntBitMask ( const IsaInfo :: IsaVersion & Version ) { unsigned Vmcnt = getBitMask ( getVmcntBitShift ( ) ,


<s> raw_svector_ostream VecOS ( Code ) ; Emitter . emitPrefix ( RF . getInst ( ) , VecOS , STI ) ; assert ( Code . size ( ) < <NUM_LIT> && <STR_LIT> ) ; unsigned ExistingPrefixSize = Code . size ( ) ; if ( TargetPrefixMax <= ExistingPrefixSize ) return <NUM_LIT> ; return TargetPrefixMax - ExistingPrefixSize ; } ( ) ; const unsigned PrefixBytesToAdd = std :: min ( MaxPossiblePad , RemainingPrefixSize ) ; if ( PrefixBytesToAdd == <NUM_LIT> ) return false ; const uint8_t Prefix = determinePaddingPrefix ( RF . getInst (


<s> if ( CC == <STR_LIT> ) { std :: string Msg = <STR_LIT> ; if ( ! Suggestion . empty ( ) ) Msg += <STR_LIT> + Suggestion + <STR_LIT> ; return TokError ( Msg ) ; } Lex ( ) ; if ( invertCondCode ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return TokError ( <STR_LIT> ) ; CC = <STR_LIT> ( <STR_LIT> ( CC ) ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , S


<s> } } } if ( ST . hasSwap ( ) && ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ) { if ( auto * NextMI = matchSwap ( MI , MRI , TII ) ) { Next = NextMI -> getIterator ( ) ; continue ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { const MachineOperand * Dest = & MI . getOperand ( <NUM_LIT> ) ; MachineOperand * Src0 = & MI . getOperand ( <NUM_LIT> ) ; MachineOperand * Src1 = & MI . getOperand ( <NUM_LIT> ) ; if ( ! Src0 -> isReg ( ) && Src1 -> isReg ( ) ) { if ( TII -> commuteInstruction ( MI , false , <NUM_LIT> , <NUM_LIT> ) ) std :: swap ( Src0 , Src1 ) ; } if ( Dest -> getReg ( ) . isVirtual ( ) && Src0 -> isReg ( ) ) { MRI . setRegAllocationHint ( Dest -> getReg ( ) , <NUM_LIT> , Src0 -> getReg ( ) ) ; MRI . setRegAllocationHint ( Src0 -> getReg ( ) , <NUM_LIT> , Dest -> getReg ( ) ) ; continue ; } if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Dest -> getReg ( ) ) { if ( Src1 -> isImm ( ) && isKImmOperand ( TII , * Src1 ) ) { unsigned Opc = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII -> get ( Opc ) ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; } } } if ( MI . isCompare ( ) && TII -> isSOPC ( MI ) ) { shrinkScalarCompare ( TII , MI ) ; continue ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . isImm ( ) && Dst . getReg ( ) . isPhysical ( ) ) { int32_t ReverseImm ; if ( isKImmOperand ( TII , Src ) ) MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( isReverseInlineImm ( TII , Src , ReverseImm ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Src . setImm (


<s> AM . Scale = <NUM_LIT> ; } switch ( TM . getCodeModel ( ) ) { default : break ; case CodeModel :: Small : case CodeModel :: Kernel : if ( Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr && AM . IndexReg . getNode ( ) == nullptr && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM .

Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ;


<s> MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } StringRef Arch = Parser . getTok ( ) . getString ( ) ; SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; getLexer ( ) . Lex ( ) ; unsigned ID = StringSwitch < unsigned > ( Arch ) . Case ( NAME , <STR_LIT> ) . Case ( NAME , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ID == <STR_LIT> ) { Error ( ArchLoc , <STR_LIT> +


<s> EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ( ! Subtarget -> hasFMA ( ) && ! Subtarget -> hasFMA4 ( ) && ! Subtarget -> hasAVX512 ( ) ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) == <STR_LIT> ) ; bool NegMul = ( NegA != NegB ) ; if ( NegA ) A = A . getOperand ( <NUM_LIT> ) ; if ( NegB ) B = B . getOperand (


<s> bool <ISA_LIT>FrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ) return false ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( GuaranteedTailCallOpt && MF . getInfo

< <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( hasFP ( MF ) ) { MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; } bool BigStack = MFI -> estimateStackSize ( MF ) >= TII . estimateRSStackLimit ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MFI -> adjustsStack ( ) && ! hasReservedCallFrame ( MF ) ) ; if ( ! BigStack ) return ; const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; uint16_t ExtraReg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo

( ) . isPhysRegUsed ( CSRegs [ i ] ) ) {


<s> emitRX ( Opcode , DstReg , MCOperand :: createImm (


<s> unsigned Res0 = MRI -> createVirtualRegister ( RC ) ; unsigned Res1 = MRI -> createVirtualRegister ( RC ) ; unsigned Res2 = MRI -> createVirtualRegister ( RC ) ; unsigned Res3 = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( AddOpc ) , Res0 ) . addReg ( Op1 , <NUM_LIT> , <STR_LIT> ) . addReg ( Op2 , <NUM_LIT> , <STR_LIT> ) . addImm ( Type ) . addImm ( <NUM_LIT> ) . addReg ( Res0 , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( AddOpc ) , Res1 ) . addReg ( Op1 , <NUM_LIT> , <STR_LIT> ) . addReg ( Op2 , <NUM_LIT> , <STR_LIT> ) . addImm ( Type ) . addImm ( <NUM_LIT> ) . addReg ( Res1 , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( AddOpc ) , Res2 ) . addReg ( Op1 , <NUM_LIT> , <STR_LIT> ) . addReg ( Op2 , <NUM_LIT> , <STR_LIT> ) . addImm ( Type ) . addImm ( <NUM_LIT> ) . addReg ( Res2 , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( AddOpc ) , Res3 ) . addReg ( Op1 , <NUM_LIT> , <STR_LIT> ) . addReg ( Op2 , <NUM_LIT> , <STR_LIT> ) . addImm ( Type ) . addImm ( <NUM_LIT> ) . addReg ( Res3 , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Accum , Accum -> end ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , Res ) . addReg ( Res0 ) . addImm ( <STR_LIT> ) . addReg ( Res1 ) . addImm (

<STR_LIT> ) . addReg ( Res2 ) . addImm ( <STR_LIT> ) . addReg ( Res3 ) . addImm ( <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine (


<s> PreAnalyzeCallResultForF128 ( Ins , CLI ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasFloat . clear


<s> SDValue StoreVal = Store -> getValue ( ) ; MVT VT = StoreVal . getSimpleValueType ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorNumElements ( ) < <NUM_LIT> ) { VT = <STR_LIT> ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , StoreVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDValue NewValue = convertToScalableVector ( ContainerVT , StoreVal , DAG , Subtarget ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Store -> getChain ( ) , NewValue , Store ->

getBasePtr ( ) , VL } , Store -> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ;


<s> if ( ! crtl -> sp_is_unchanging ) return true ; if ( cfun -> has_nonlocal_label


<s> static void riscv_block_move_straight ( rtx dest , rtx src , unsigned HOST_WIDE_INT length ) { unsigned HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; bits = MAX ( BITS_PER_UNIT , MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ) ; mode = mode_for_size ( bits , MODE_INT , <NUM_LIT> ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; riscv_emit_move ( regs [ i ] , adjust_address (


<s> Builder . setDebugLoc ( DL ) ; Builder . buildInstr ( <STR_LIT> ) . addMBB ( & NewDestBB


<s> TerminatorInst * Insert = From -> getTerminator ( ) ; Value * Arg = PhiInserter . GetValueAtEndOfBlock ( From ) ; Value * Ret = CallInst :: Create ( Break , Arg , <STR_LIT> , Insert ) ; PhiInserter . AddAvailableValue ( From , Ret ) ; } eraseIfUnused ( Phi ) ; } else if ( Instruction * Inst = dyn_cast < Instruction > ( Cond ) ) { BasicBlock * Parent = Inst -> getParent ( ) ; TerminatorInst * Insert = Parent -> getTerminator ( ) ; Value * Args [ ] = { Cond , PhiInserter . GetValueAtEndOfBlock ( Parent ) } ; Value * Ret = CallInst :: Create ( IfBreak , Args , <STR_LIT> ,


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( C

) ) return <ISA_LIT>MaterializeInt ( CI , VT , VT != <STR_LIT> ) ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; unsigned Pos = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) Pos -= <NUM_LIT> ; assert ( ( Pos < <NUM_LIT> || ( Pos < <NUM_LIT> && MCID . Opcode != <STR_LIT> && MCID . Opcode != <STR_LIT> ) ) && <STR_LIT> ) ; Binary |= Pos << <NUM_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) { unsigned ShiftOp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Opc = <STR_LIT> ( ShiftOp ) ; if ( Opc == <STR_LIT> ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; unsigned ShiftAmt = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ShiftAmt == <NUM_LIT> && Opc == <STR_LIT> ) ShiftAmt = <NUM_LIT> ; assert ( ShiftAmt < <NUM_LIT> && <STR_LIT>


<s> static bool CC_<ISA_LIT>O32_FP32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { llvm_unreachable (


<s> hasGPR = true ; LastReg = CSI [ i ] . getReg ( ) ; } if ( hasGPR ) { assert ( LastReg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , LastReg ) ; } } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; if ( ! MF . protectCSRs ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } else { if ( Reg != LastReg ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , LastReg ) . addReg ( LastReg ) . addReg ( Reg ) ; } else { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned OpcCJE = <ISA_LIT>InstrInfo :: getFSOpcode ( TII . getCompareRegAndStackOpcode ( LastReg , MRI , * TRI ) ) ; addRegOffset ( BuildMI ( MBB , MI , DL , TII . get ( OpcCJE ) ) . addReg ( LastReg ) , STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , false , <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned StackPtr = RegInfo -> getStackRegister ( ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; unsigned Opc = getADDriOpcode ( IsLP64 , SlotSize ) ; MachineInstr * mi = BuildMI ( MBB , MI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( SlotSize ) ; mi -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } } } return


<s> uint64_t Val = <NUM_LIT> ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; I . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Val ) ; } else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned NewOpc ; switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : NewOpc = <STR_LIT> ; break ; case <NUM_LIT> : NewOpc = <STR_LIT> ; break ; case <NUM_LIT> : NewOpc = <STR_LIT> ; break ; case <NUM_LIT> : { if ( isInt < <NUM_LIT> > ( Val ) ) NewOpc = <STR_LIT> ; else NewOpc = <STR_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT>


<s> unsigned <ISA_LIT>TargetMachine :: getModuleMatchQuality ( const Module & M ) { std :: string TT = M . getTargetTriple ( ) ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( ! TT . empty ( ) ) return <NUM_LIT> ; if ( M . getEndianness ( ) == Module :: BigEndian && M . getPointerSize ( ) == Module


<s> bool isDataType ( ) const { return Kind == OpKind


<s> void <ISA_LIT>FrameLowering :: replaceAdjDynAllocPseudo ( MachineFunction & MF ) const { const <ISA_LIT>InstrInfo & LII = * static_cast < const <ISA_LIT>InstrInfo * > ( STI . getInstrInfo ( ) ) ; unsigned MaxCallFrameSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; while ( MBBI != MBB -> end ( ) ) { MachineInstr * MI = MBBI ++ ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Dst = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , MI , DL , LII . get ( <STR_LIT> ) , Dst ) . addReg ( Src ) . addImm ( MaxCallFrameSize ) ; MI -> eraseFromParent (


<s> const Item * item ( ) const { return reinterpret_cast < const Item * > ( Ref . data (


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; Register StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) , dl ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl


<s> Callees . push_back ( Callee -> getMF ( ) ) ; return true ; } else if ( Callee && Callee -> isUnknown ( ) ) { for ( MCGSites :: const_iterator ci = Callee -> getSites ( ) . begin ( ) , ce = Callee -> getSites ( ) . end ( ) ; ci != ce ; ci ++ ) { MCGNode * MatchedCallee = ( * ci ) -> getCallee ( ) ; if ( MatchedCallee && MatchedCallee -> getMF ( ) ) { Callees . push_back ( MatchedCallee -> getMF ( ) ) ; } else if ( MatchedCallee && MatchedCallee -> isUnknown ( ) ) { llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; } } } return


<s> static inline unsigned getMBit ( uint32_t insn ) { return ( insn >>


<s> bool isShifterImm ( ) const { return Kind ==


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo .


<s> auto SysReg = <STR_LIT> ( Imm ) ; Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( SysReg ? SysReg -> Name : <STR_LIT> , S , Imm , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } Twine Msg = <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; auto SysReg = <STR_LIT> ( Identifier ) ; if ( ! SysReg ) SysReg = <STR_LIT> ( Identifier ) ; if ( SysReg ) { if ( ! SysReg -> haveRequiredFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createSysReg ( Identifier , S , SysReg -> Encoding , isRV64 ( ) ) ) ; return MatchOperand_Success ; } Twine Msg = <STR_LIT> <STR_LIT> ; Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> + Twine ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ; return MatchOperand_ParseFail ; } case AsmToken :: Percent


<s> const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; const MCRegisterClass & ImmRC = MRI . getRegClass ( Desc . OpInfo [ OpNo ] . RegClass ) ; if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , O ) ; else if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O


<s> if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) && Name == <STR_LIT> ) return FK_NONE ; return MCAsmBackend :: getFixupKind


<s> break ; case ADDRESS_POST_INC_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_MODIFY_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_FP_IMM7U : output_asm_insn ( <STR_LIT> , operands ) ; break ; case


) , ( __mmask16 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering


<s> int mmix_data_alignment ( tree type ATTRIBUTE_UNUSED


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64Bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Is64Bit ( is64Bit ) { initAsmInfo (


<s> bool isVGPRClass ( const TargetRegisterClass *


<s> return getSTI ( ) . getFeatureBits ( )


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL


<s> RegNum = ( RegLoNum != <STR_LIT> ) ? RegLoNum : RegNum ; } return getRegisterName (


<s> MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo * MMI = MFI -> getMachineModuleInfo ( ) ; DebugLoc dl = ( MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc :: getUnknownLoc ( ) ) ; bool hasDebugInfo = MMI && MMI -> hasDebugInfo ( ) ; unsigned FrameLabelId = <NUM_LIT> ; MBBI = MBB . begin ( ) ; determineFrameLayout ( MF ) ; int FrameSize = MFI -> getStackSize ( ) ; assert ( ( FrameSize & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( FrameSize > <NUM_LIT> || MFI -> hasCalls ( ) ) { FrameSize = - ( FrameSize + <ISA_LIT>FrameInfo :: minStackSize ( ) ) ; if ( hasDebugInfo ) { FrameLabelId = MMI -> NextLabelID ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( FrameLabelId ) ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; if ( isS10Constant ( FrameSize ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( FrameSize <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && FrameSize >= - ( <NUM_LIT> << <NUM_LIT> ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { std :: string msg


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const


<s> if ( ! ImmInRange ( MI , Entry ) ) return false ; if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! IsSP ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ; return ReplaceInstruction ( MI


<s> switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ; std :: swap ( LHS


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ]


<s> MachineBasicBlock :: iterator I = slot ; while ( true ) { if ( I == MBB . begin ( ) ) break ; -- I ; MCInstrDesc desc = I -> getDesc ( ) ; if ( desc . hasDelaySlot ( ) || desc . isBranch ( ) || isDelayFiller ( MBB , I ) || desc . isCall ( ) || desc . isReturn ( ) || desc . isBarrier ( ) || hasUnknownSideEffects ( I ) ) break ; if ( hasImmInstruction ( I ) || delayHasHazard ( I , slot ) ) continue ; return


<s> if ( V . getOpcode ( ) == <STR_LIT> ) { SDValue Src = V . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! SrcVT . isVector ( ) ) return SDValue ( ) ; if ( SDValue Not = IsNOT ( Src , DAG ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( V ) , VT , DAG . getBitcast ( SrcVT , Not ) ) ; } return SDValue ( ) ; } ; if ( SDValue Not = GetNot ( N0 ) ) { X = Not ; Y = N1 ; } else if ( SDValue Not = GetNot ( N1 ) ) { X = Not


<s> if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N ,


<s> SDLoc dl ( Op ) ; auto * C = cast < ConstantSDNode > ( ScaleOp ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , & Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , VMask , Src , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; return SDValue ( Res


<s> const TargetRegisterClass * RC = RegInfo . intRegClass ( VRegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned SrcKill = getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ; unsigned DstLo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc


<s> static inline bool isDCC ( const TargetRegisterClass * RC


<s> unsigned RR = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src ) ; if ( RR != <NUM_LIT> )


<s> const char * getPassName ( ) const override { return


<s> static rtx sparc_builtin_setjmp_frame_value ( void ) { return hard_frame_pointer_rtx


<s> rtx label , x , mask , shift ; retval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; val = operands [ <NUM_LIT> ] ; model = memmodel_base ( INTVAL ( operands [ <NUM_LIT> ] ) ) ; mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( ! TARGET_SYNC_HI_QI && ( mode == QImode || mode == HImode ) ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; val = convert_modes ( SImode , mode , val , <NUM_LIT> ) ; val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx (


<s> bool isAMXInstruction ( MachineInstr & MI ) { if ( MI . isPHI ( ) || MI . isDebugInstr ( )

|| MI . getNumOperands ( ) < <NUM_LIT> ) return false ;


<s> case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case TYPE_NEON_FP_SQRT_D : case TYPE_NEON_FP_SQRT_S_Q : case TYPE_NEON_FP_SQRT_D_Q : case TYPE_NEON_FP_DIV_S : case TYPE_NEON_FP_DIV_D : case TYPE_NEON_FP_DIV_S_Q : case TYPE_NEON_FP_DIV_D_Q