<s> MFI . setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineBasicBlock & MBBJ : llvm :: drop_begin ( MF ) ) MBBJ . addLiveIn ( <STR_LIT> ) ; } else NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes


<s> void \ switch_to_section ( enum in_section section , tree decl ) \ { \ switch ( section ) \ { \ case in_text : text_section ( ) ; break ; \ case in_unlikely_executed_text : unlikely_text_section ( ) ; break ; \ case in_data : data_section ( ) ; break ; \ case in_readonly_data : readonly_data_section ( ) ; break ; \ case in_named : named_section ( decl , NULL

, <NUM_LIT> ) ; break ; \ case in_drectve : drectve_section ( ) ; break ; \ default : abort ( ) ; break ; \ } \ }


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s> static bool pa_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return tls_referenced_p ( x )


<s> bool <ISA_LIT>ClauseMergePass :: isCFAluEnabled ( const MachineInstr & MI ) const { assert ( isCFAlu ( MI


<s> void thumb_expand_epilogue ( ) { HOST_WIDE_INT amount = ( get_frame_size ( ) + current_function_outgoing_args_size ) ; if ( IS_NAKED ( arm_current_func_type ( ) ) ) return ; if ( frame_pointer_needed ) emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; else if ( amount ) { amount = ROUND_UP ( amount ) ; if ( amount < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { rtx reg = gen_rtx ( REG , SImode , LAST_ARG_REGNUM ) ; emit_insn ( gen_movsi ( reg , GEN_INT ( amount ) ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx


<s> for ( MachineLoopInfo :: iterator It = MLI -> begin ( ) , E = MLI -> end ( ) ; It != E ; ++ It ) { df_iterator < MachineLoop * > LpIt = df_begin ( * It ) , LpE = df_end ( * It ) ; for ( ; LpIt != LpE ; ++ LpIt ) NestedLoops . push_back ( * LpIt ) ; } if ( NestedLoops . size ( ) == <NUM_LIT> ) return <NUM_LIT> ; int Num = <NUM_LIT> ; for ( std :: vector < MachineLoop * > :: reverse_iterator It = NestedLoops . rbegin ( ) , E = NestedLoops . rend ( ) ; It != E ; ++ It ) { MachineLoop * ExaminedLoop = * It ; if ( ExaminedLoop -> getNumBlocks ( ) == <NUM_LIT> || Visited [ ExaminedLoop ] ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ; ExaminedLoop -> dump ( ) ; ) ; int NumBreak = mergeLoop ( ExaminedLoop ) ; if ( NumBreak ==


<s> State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; unsigned T = State . AllocateReg ( LoRegList [ i ] ) ; ( void ) T ; assert ( T == LoRegList [ i ] && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , LocVT , LocInfo ) ) ; return true


<s> void <ISA_LIT>AsmPrinter :: printReturnValStr ( const Function * F , raw_ostream & O ) { const DataLayout & DL = getDataLayout ( ) ; const TargetLowering * TLI = nvptxSubtarget -> getTargetLowering ( ) ; Type * Ty = F -> getReturnType ( ) ; bool isABI = ( nvptxSubtarget -> getSmVersion ( ) >= <NUM_LIT> ) ; if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return ; O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( auto * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } if ( size < <NUM_LIT> ) size = <NUM_LIT> ; O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( DL ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned totalsz = DL . getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = DL . getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT>


<s> if ( LongSerialize ) { Instr -> print (


<s> const MachineFunction & MF = * MBB . getParent ( ) ; for ( const CalleeSavedInfo & CSI : MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ) for ( MCRegister Reg : TRI -> sub_and_superregs_inclusive ( CSI . getReg ( ) ) ) RegsToZero . reset ( Reg ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; for ( MachineBasicBlock :: iterator I = MBBI , E = MBB . end ( ) ; I != E ; ++ I ) for ( const MachineOperand & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; for ( const MCPhysReg & Reg : TRI -> sub_and_superregs_inclusive ( MO . getReg ( ) ) ) RegsToZero . reset ( Reg ) ; } DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; for ( MCRegister Reg : RegsToZero . set_bits ( ) ) { if ( ! <STR_LIT> . contains ( Reg ) ) continue ; unsigned NumFPRegs = ST . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumFPRegs ; ++ i ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumFPRegs ; ++ i ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; break ; } BitVector GPRsToZero ( TRI -> getNumRegs ( ) ) ; for ( MCRegister Reg : RegsToZero . set_bits ( ) ) if ( TRI -> isGeneralPurposeRegister ( MF , Reg ) ) { GPRsToZero . set ( get<ISA_LIT>SubSuperRegisterOrZero ( Reg , <NUM_LIT> ) ) ; RegsToZero . reset ( Reg ) ; } for ( MCRegister Reg : GPRsToZero . set_bits ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) .


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC


<s> unsigned VF = cast < VectorType > ( VecTy ) -> getNumElements ( ) / Factor ; MVT VT = <STR_LIT> ( <STR_LIT> ( VecTy -> getScalarType ( ) ) , VF ) ; if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; unsigned ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; Type * ResultTy = VectorType :: get ( cast < VectorType > ( VecTy ) -> getElementType ( ) , cast < VectorType > ( VecTy ) -> getNumElements ( ) / Factor ) ; unsigned NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; unsigned NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; bool hasFramePointer = hasFP ( MF ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; if ( RI -> needsStackRealignment ( MF ) && MFI . hasVarSizedObjects ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } Register FPReg = <STR_LIT> ; Register SPReg = <STR_LIT> ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( hasFramePointer ) StackSize ++ ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize


<s> unsigned Src1SubReg = Src1 -> getSubReg ( ) ; unsigned Src2Reg = Src2 -> getReg ( ) ; unsigned Src2SubReg = Src2 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src1 -> setReg ( Src2Reg ) ; Src1 -> setSubReg ( Src2SubReg ) ; Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( AMDGPU :: V_MADMK_F32 ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || ( Src1 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; const int64_t Imm = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI -> RemoveOperand ( AMDGPU :: getNamedOperandIdx ( AMDGPU :: V_MAD_F32 , AMDGPU :: OpName :: omod ) ) ; UseMI -> RemoveOperand ( AMDGPU :: getNamedOperandIdx ( AMDGPU :: V_MAD_F32 , AMDGPU :: OpName :: clamp ) ) ; Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( AMDGPU :: V_MADAK_F32 ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ; } } return


<s> long int <ISA_LIT>ELFWriterInfo :: computeRelocation ( unsigned SymOffset , unsigned RelOffset , unsigned RelTy ) const { llvm_unreachable ( <STR_LIT> <STR_LIT>


<s> __builtin_ia32_movntdq ( ( __v2di * ) __A , ( __v2di )


<s> const BitVector & getMaskUnits ( RegisterId MaskId )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; IntegerType * CallTy = Type :: getIntNTy ( * DAG . getContext ( ) , Ty . getSizeInBits ( ) ) ; const GlobalValue * GV = N -> getGlobal ( ) ; SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Load ; Entry . Ty = CallTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , CallTy , DAG . getExternalSymbol ( <STR_LIT> , Ty ) , std :: move ( Args ) ) ; return LowerCallTo ( CLI


<s> switch ( Type ) { default : return true ; case ELF ::


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( OpNum == <NUM_LIT> ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } break ; case <STR_LIT> : isFloat = true ; case <STR_LIT> : if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? <STR_LIT> : <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , false , false , isKill ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( isFloat ? <STR_LIT> : <STR_LIT> ) ) . addReg ( DstReg , true ,

false , false , isDead ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> int SccNum = <NUM_LIT> ; MachineBasicBlock * MBB ; for ( scc_iterator < MachineFunction * > It = scc_begin ( MF ) ; ! It . isAtEnd ( ) ; ++ It , ++ SccNum ) { const std :: vector < MachineBasicBlock * > & SccNext = * It ; for ( std :: vector < MachineBasicBlock * > :: const_iterator blockIter = SccNext . begin ( ) , blockEnd = SccNext . end ( ) ; blockIter != blockEnd ; ++ blockIter ) { MBB = * blockIter ; OrderedBlks . push_back ( MBB ) ; recordSccnum ( MBB , SccNum ) ; } } typedef GraphTraits < MachineFunction * > GTM ; auto It = GTM :: nodes_begin ( MF ) , E = GTM :: nodes_end ( MF ) ; for ( ; It != E ; ++ It ) { MachineBasicBlock * MBB = *


<s> bool isABI_EABI ( ) const { return ABI . IsEABI (


<s> NaCl<ISA_LIT>AsmBackend ( const Target & T , bool _is64Bit ) : <ISA_LIT>AsmBackend ( T , Triple :: NaCl ,


<s> if ( HST . useHVXOps ( ) ) { for ( auto & RC : { HvxVRRegClass , HvxWRRegClass , HvxQRRegClass , HvxVQRRegClass } ) if

( RC . contains ( Reg ) ) return TRI . getRegSizeInBits ( RC ) ;


<s> if ( AM . hasBaseOrIndexReg ( ) ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( G -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( CP -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || M == CodeModel :: Small || M == CodeModel :: Kernel ) { assert ( N . getOpcode ( ) != <STR_LIT> && <STR_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP ->


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { initAsmInfo ( )


<s> else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } else { if ( CSKY_ISA_FEATURE ( fpv2_df ) ) return <STR_LIT> ; else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } } if ( dstreg == basereg ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_DOUBLE ) { split_double ( src , operands + <NUM_LIT> , operands + <NUM_LIT> ) ; if ( CSKY_CONST_OK_FOR_I ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Uc ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Ub ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; if ( CSKY_CONST_OK_FOR_I ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Uc ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CSKY_CONST_OK_FOR_Ub ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } else gcc_unreachable ( ) ; } else if ( GET_CODE ( dst ) == MEM && GET_CODE ( src ) == REG ) { rtx memexp = XEXP ( dst , <NUM_LIT> ) ; int srcreg = REGNO ( src ) ; int basereg = - <NUM_LIT> ; struct csky_address op0 ; decompose_csky_address ( XEXP ( dst , <NUM_LIT> ) , & op0 ) ; if ( GET_CODE ( memexp ) == REG ) basereg = REGNO ( memexp ) ; else if ( GET_CODE ( memexp ) == PLUS ) { if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) basereg = REGNO ( XEXP ( memexp , <NUM_LIT> ) ) ; else if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) basereg = REGNO ( XEXP ( memexp , <NUM_LIT> ) ) ; else gcc_unreachable ( ) ; } else gcc_unreachable ( ) ; if ( CSKY_VREG_P ( srcreg ) ) { if ( op0 . index ) { if ( CSKY_ISA_FEATURE ( fpv2_df ) ) return <STR_LIT> ; else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } else { if ( CSKY_ISA_FEATURE ( fpv2_df ) ) return <STR_LIT> ; else if ( CSKY_ISA_FEATURE ( fpv3_df ) ) return <STR_LIT> ; else gcc_unreachable ( ) ; } } if ( srcreg == basereg ) return <STR_LIT> ; else return <STR_LIT> ; } else gcc_unreachable (


<s> return avr_lookup_function_attribute1 ( func ,


<s> MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , Copy0MBB ) ; F -> insert ( It , SinkMBB ) ; SinkMBB -> splice ( SinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( SinkMBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( SinkMBB ) ; BB = Copy0MBB ; BB -> addSuccessor ( SinkMBB ) ; BB = SinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) ; MI . eraseFromParent


<s> if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { if ( Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Ld -> getChain ( ) , Ld -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , Ld -> getMemoryVT ( ) , Ld -> getPointerInfo ( ) , Ld -> getAlignment ( ) , false , true , false ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getBitcast ( VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) ,


<s> assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank (

VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> case Instruction :: Add : if ( Match ( I -> getOperand ( <NUM_LIT> ) ) || ( Match ( I -> getOperand ( <NUM_LIT> ) ) ) ) return true ; break ; case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ; if ( isa < SExtInst > ( MulOp0 ) && isa < SExtInst > ( MulOp1 ) ) AddMACCandidate ( Candidates , I , MulOp0 , MulOp1 ) ; return


<s> Target & llvm :: getThe<ISA_LIT>32Target ( ) { static Target The<ISA_LIT>32Target ; return The<ISA_LIT>32Target


<s> unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg


<s> rtx cmp_rtx = tilepro_emit_cc_test ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands


<s> ++ NumADRSimpleCandidate ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( & Def ) ) && <STR_LIT> ) ; assert ( ( ! InvolvedInLOHs || InvolvedInLOHs -> insert ( & Use ) ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Def << '\n' << Use << '\n' ) ; SmallVector < const MachineInstr * , <NUM_LIT> > Args ; Args . push_back ( & Def ) ; Args . push_back ( & Use ) ; <ISA_LIT>FI . addLOHDirective ( Use . getOpcode ( )

== <STR_LIT> ? MCLOH_AdrpAdd : MCLOH_AdrpLdrGot , Args ) ;


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( AddSubFlagsOpcodeMap ) ; i != e ; ++ i ) if ( OldOpc == AddSubFlagsOpcodeMap [ i ] . PseudoOpc ) return AddSubFlagsOpcodeMap [ i ] . MachineOpc ; return


<s> const ArgDescriptor * Arg = getArgDescriptor ( B , <STR_LIT> ) ; if ( ! Arg ) return false ; MachineRegisterInfo & MRI = * B . getMRI ( ) ; Register SGPR01 ( <STR_LIT> ) ; Register LiveIn = getLiveInRegister ( B , MRI , SGPR01 , LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) , false ) ; if ( ! loadInputValue ( LiveIn , B , Arg ) ) return false ; B . buildCopy ( SGPR01


<s> for ( StringMap < const <ISA_LIT>CallEntry * > :: iterator I = ExternalCallEntries . begin ( ) , E

= ExternalCallEntries . end ( ) ; I != E ;


<s> if ( ! ( ( Subtarget . hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT>


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcSubIdx = MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; DstSubIdx = MI . getOperand ( <NUM_LIT> ) . getSubReg


<s> static void LLVM_ATTRIBUTE_UNUSED clearFeature ( MCSubtargetInfo * STI , uint64_t F ) { uint64_t FB = STI -> getFeatureBits ( )


<s> bool <ISA_LIT>RegisterInfo :: isAGPR ( const MachineRegisterInfo & MRI , Register Reg ) const { const TargetRegisterClass * RC = getRegClassForReg ( MRI , Reg ) ; return RC && hasAGPRs (


<s> Streamer -> EmitSymbolValue ( & S , <NUM_LIT>


<s> return ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) -> useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( CN -> getType (


<s> assert ( isMem ( BDLMem ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Mem . Base ) ) ; addExpr ( Inst , Mem . Disp


<s> Generation getGeneration ( ) const { return ( Generation


<s> return ( __m256i ) __builtin_ia32_movdqa64load256_mask ( ( __v4di * ) __P , ( __v4di ) __W , (


<s> Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . LoadSizes . push_back ( <NUM_LIT> ) ; return Options ; } ( ) ; static const auto EqZeroOptions = [ this ] ( ) { TTI :: MemCmpExpansionOptions Options ; if ( ST -> hasAVX2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( ST -> hasSSE2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( ST -> is64Bit ( ) ) { Options . LoadSizes . push_back ( <NUM_LIT> ) ; } Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . AllowOverlappingLoads = true ; return Options ; } (


<s> return combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , <STR_LIT> , false ,


<s> if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . cloneMemRefs ( MI ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> )

, BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ;


<s> SDValue LDL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return createLoadLR ( <STR_LIT> , DAG , LD , LDL . getValue ( <NUM_LIT> ) , LDL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } SDValue LWL = createLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; SDValue LWR = createLoadLR ( <STR_LIT> , DAG , LD , LWL . getValue ( <NUM_LIT> ) , LWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( VT == <STR_LIT> ) || ( ExtType == <STR_LIT> ) || ( ExtType == <STR_LIT> ) ) return LWR ; assert ( ( VT == <STR_LIT> )


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer & Out


<s> if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> (


<s> bool hasPkFmacF16Inst ( ) const { return HasPkFmacF16Inst


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE ->


<s> void <ISA_LIT>InstrInfo :: addUsersToMoveToVALUWorklist ( Register DstReg , MachineRegisterInfo & MRI , SetVectorType & Worklist ) const { for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( DstReg ) , E = MRI . use_end ( ) ; I != E ; ) { MachineInstr & UseMI = * I -> getParent ( ) ; unsigned OpNo


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; <ISA_LIT>TargetELFStreamer * ELFTargetStreamer = static_cast < <ISA_LIT>TargetELFStreamer * > ( getTargetStreamer ( ) ) ; for ( unsigned OpIndex = <NUM_LIT> ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op .


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ; uint64_t encoding = <STR_LIT> ( Val , <NUM_LIT>


<s> return FixedVectorType :: get ( ArgTy -> getScalarType ( ) , cast < VectorType > ( DstTy ) -> getNumElements ( ) ) ; } ; if ( ! DstTy -> isVectorTy ( ) || DstTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; switch ( Opcode ) { case Instruction :: Add : case Instruction :: Sub : break ; default : return false ; } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) || ! Args [ <NUM_LIT> ] -> hasOneUse ( ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL .


<s> break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) ,


<s> MachineBasicBlock * OrigBB = MI -> getParent ( ) ; MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end


<s> else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return true ; else if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( SecondOpcode == <STR_LIT> && SecondMI . getOperand


<s> bool AMDGPUDAGToDAGISel :: SelectMUBUFAddr64 ( SDValue Addr , SDValue & SRsrc , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return SelectMUBUFAddr64 ( Addr , SRsrc , VAddr , Offset


<s> return __builtin_loongson_pextrh_u ( s , field


<s> int reg_parm_stack_space = REG_PARM_STACK_SPACE ( NULL_TREE ) ; rtx arg_bytes , begin_label_rtx , mcount , sym ; rtx_insn * call_insn ; char begin_label_name [ <NUM_LIT> ] ; bool use_mcount_pcrel_call ; sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pa_encode_label ( sym ) ; mcount = gen_rtx_MEM ( Pmode , sym ) ; if ( ! TARGET_PORTABLE_RUNTIME && ! TARGET_LONG_CALLS && ( TARGET_SOM || flag_function_sections ) ) use_mcount_pcrel_call = TRUE ; else use_mcount_pcrel_call = FALSE ; ASM_GENERATE_INTERNAL_LABEL ( begin_label_name , FUNC_BEGIN_PROLOG_LABEL , label_no ) ; begin_label_rtx = gen_rtx_SYMBOL_REF ( SImode , ggc_strdup ( begin_label_name ) ) ; emit_move_insn ( gen_rtx_REG ( word_mode , <NUM_LIT> ) , gen_rtx_REG ( word_mode , <NUM_LIT> ) ) ; if ( ! use_mcount_pcrel_call ) { if ( TARGET_PA_20 ) emit_insn ( gen_lcla2 ( gen_rtx_REG ( SImode , <NUM_LIT> ) , label_rtx ) ) ; else emit_insn ( gen_lcla1 ( gen_rtx_REG ( SImode , <NUM_LIT> ) , label_rtx ) ) ; } if ( ! NO_DEFERRED_PROFILE_COUNTERS ) { rtx count_label_rtx , addr , r24 ; char count_label_name [ <NUM_LIT> ] ; funcdef_nos . safe_push ( label_no ) ; ASM_GENERATE_INTERNAL_LABEL ( count_label_name , <STR_LIT> , label_no ) ; count_label_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( count_label_name ) ) ; addr = force_reg ( Pmode , count_label_rtx ) ; r24 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( r24 , addr ) ; arg_bytes = GEN_INT ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( use_mcount_pcrel_call ) call_insn = emit_call_insn ( gen_call_mcount ( mcount , arg_bytes , begin_label_rtx ) ) ; else call_insn = emit_call_insn ( gen_call ( mcount , arg_bytes ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , r24 ) ; } else { arg_bytes = GEN_INT ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( use_mcount_pcrel_call ) call_insn = emit_call_insn ( gen_call_mcount ( mcount , arg_bytes


<s> setAttributeItems ( Attribute , IntValue , StringValue


<s> bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } NewBBI = llvm :: prior ( MBBI ) ; } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; unsigned NewOpc2 = ( isLd ) ? ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc2 , OddReg , OddDeadKill , false , BaseReg , false , BaseUndef , false , OffUndef , Pred , PredReg , TII , isT2 ) ; NewBBI = llvm ::


<s> NeedAddressOverride = true ; } else if ( MemoryOperand < <NUM_LIT> ) { NeedAddressOverride = false ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is16BitMemOperand ( MI , MemoryOperand , STI ) ) ; NeedAddressOverride = is32BitMemOperand ( MI , MemoryOperand ) ; } else if ( STI . hasFeature ( <STR_LIT> ) ) { assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; NeedAddressOverride = is16BitMemOperand ( MI , MemoryOperand , STI ) ; } else { assert ( STI . hasFeature ( <STR_LIT> ) ) ; assert ( ! is64BitMemOperand ( MI , MemoryOperand ) ) ; NeedAddressOverride = ! is16BitMemOperand ( MI , MemoryOperand , STI ) ; } if ( NeedAddressOverride ) emitByte ( <NUM_LIT> , OS ) ; uint64_t Encoding = TSFlags & <STR_LIT> ; bool HasREX = false ; if ( Encoding ) emitVEXOpcodePrefix ( MemoryOperand , MI , OS ) ; else HasREX = emitOpcodePrefix ( MemoryOperand , MI , STI , OS ) ; uint64_t Form = TSFlags & <STR_LIT> ; switch ( Form ) { default : break ; case <STR_LIT> : { unsigned siReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( ( siReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( siReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( siReg == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; if ( ( ! STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) ) emitByte ( <NUM_LIT> , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT> : { unsigned siReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; if ( ( ! STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) || ( STI . hasFeature ( <STR_LIT> ) && siReg == <STR_LIT> ) ) emitByte ( <NUM_LIT> , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT>


<s> } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; AddDefaultPred ( MIB ) ; NewMIs . push_back (


<s> rtx new_rtx = orig ; if ( TARGET_MACHO && ! TARGET_64BIT ) { if ( reg == <NUM_LIT> ) reg = gen_reg_rtx ( Pmode ) ; return machopic_legitimize_pic_address ( orig , GET_MODE ( orig ) , reg ) ; } if ( TARGET_64BIT && TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { rtx tmp = legitimize_pe_coff_symbol ( addr , true ) ; if ( tmp ) return tmp ; } if ( TARGET_64BIT && legitimate_pic_address_disp_p ( addr ) ) new_rtx = addr ; else if ( ( ! TARGET_64BIT || ix86_cmodel != CM_SMALL_PIC ) && ! TARGET_PECOFF && gotoff_operand ( addr , Pmode ) ) { if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , XEXP ( addr , <NUM_LIT> ) ) , UNSPEC_GOTOFF ) ; new_rtx = gen_rtx_PLUS ( Pmode , new_rtx , XEXP ( addr , <NUM_LIT> ) ) ; } else new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , UNSPEC_GOTOFF ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; if ( TARGET_64BIT ) new_rtx = copy_to_suggested_reg ( new_rtx , reg , Pmode ) ; if ( reg != <NUM_LIT> ) { gcc_assert ( REG_P ( reg ) ) ; new_rtx = expand_simple_binop ( Pmode , PLUS , pic_offset_table_rtx , new_rtx , reg , <NUM_LIT> , OPTAB_DIRECT ) ; } else new_rtx = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , new_rtx ) ; } else if ( ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( addr ) == <NUM_LIT> ) || ( TARGET_VXWORKS_RTP && GET_CODE ( addr ) == LABEL_REF ) ) { rtx tmp = legitimize_pe_coff_symbol ( addr , true ) ; if ( tmp ) return tmp ; if ( TARGET_64BIT && TARGET_PECOFF ) { new_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , UNSPEC_PCREL ) ; new_rtx = gen_rtx_CONST ( Pmode , new_rtx ) ; } else if ( TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC


<s> } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , Addr , <STR_LIT> ) ; } else { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; } return


<s> return ( __m512i ) __builtin_ia32_expandloadhi512_mask ( ( const __v32hi * ) __C , ( __v32hi ) __A , ( __mmask32


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( param >= <NUM_LIT> && param <= <NUM_LIT> ) nios2_register_custom_code ( param , CCS_FPU , fpu_insn_index ) ; else if ( param != - <NUM_LIT> ) error ( <STR_LIT>

, N2FPU_NAME ( fpu_insn_index ) , param ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveThumbSet ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; StringRef Name ; if ( check ( Parser . parseIdentifier ( Name ) , <STR_LIT> ) || parseToken ( AsmToken :: Comma , <STR_LIT> + Name + <STR_LIT> )


<s> } } if ( STI . isTargetDarwin ( ) && STI . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_iOS_SwiftError_SaveList ; if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < <ISA_LIT>FunctionInfo > (

) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ;


<s> MVT VT ; if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap


<s> Relocation :: Type getCopyRelType ( ) const { return m_CopyRel


<s> LastFPdOpCycleIdx = UINT_MAX ; DEBUG ( CurGroupDbg = <STR_LIT>


<s> } } else if ( frame_pointer_needed ) { unsigned int reg_offset = var_size + args_size ; if ( reg_offset == <NUM_LIT> ) emit_insn ( gen_movsi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; else if ( reg_offset < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , frame_pointer_rtx , GEN_INT ( reg_offset ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( reg_offset ) ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } } else gcc_unreachable ( ) ; if ( current_frame_info . save_lr ) pop ( RETURN_ADDR_REGNUM ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = M32R_MAX_INT_REGS - <NUM_LIT> ; regno >= <NUM_LIT> ; -- regno ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) pop ( regno ) ; } if ( current_frame_info . save_fp )


<s> return getFP16Imm ( FPImm . bitcastToAPInt (


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return <STR_LIT> ( funcInfo , libInfo


<s> expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ; return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op )


<s> rtx reg = * op ; if ( hreg ) * hreg = NULL_RTX ; if ( ( opmask & <NUM_LIT> ) && REG_P ( reg ) && REGNO ( reg ) < FIRST_PSEUDO_REGISTER && ( rmask & regmask ( GET_MODE ( reg ) , REGNO ( reg ) ) ) ) { * op = gen_reg_rtx (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <NUM_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> for ( MCSuperRegIterator Super ( Reg , this ) ; Super . isValid ( ) ; ++ Super ) if ( RC -> contains ( * Super ) ) return * Super ; return <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains (


<s> const DebugLoc & DbgLoc = I . getDebugLoc ( ) ; unsigned Opc = getLoadStoreOp ( DstTy , RegBank , TargetOpcode :: G_LOAD , Alignment ) ; const ConstantFP * CFP = I . getOperand ( <NUM_LIT> ) . getFPImm ( ) ; unsigned CPI = MF . getConstantPool ( ) -> getConstantPoolIndex ( CFP , Alignment . value ( ) ) ; MachineInstr * LoadInst = nullptr ; unsigned char OpFlag = STI . classifyLocalReference ( nullptr ) ; if ( CM == CodeModel :: Large && STI . is64Bit ( ) ) { Register AddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , MF . getDataLayout ( ) . getPointerSize ( ) , Alignment ) ; LoadInst = addDirectMem ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , AddrReg ) . addMemOperand ( MMO ) ; } else if ( CM == CodeModel :: Small || ! STI . is64Bit ( ) ) { unsigned PICBase = <NUM_LIT> ; if ( OpFlag == <STR_LIT> || OpFlag == <STR_LIT> ) { return false ; } else if ( STI . is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; LoadInst = addConstantPoolReference ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , CPI , PICBase , OpFlag ) ; } else return false ; constrainSelectedInstRegOperands ( * LoadInst , TII ,


<s> static unsigned CalculateStackSlotAlignment ( EVT ArgVT , EVT OrigVT , <STR_LIT> Flags , unsigned PtrByteSize ) { unsigned Align = PtrByteSize ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) Align = <NUM_LIT> ; else if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) Align = <NUM_LIT> ; if ( Flags . isByVal ( ) ) { unsigned BVAlign = Flags . getByValAlign ( ) ; if ( BVAlign > PtrByteSize ) { if ( BVAlign % PtrByteSize != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; Align = BVAlign ; } } if ( Flags . isInConsecutiveRegs ( ) ) { if ( Flags . isSplit ( ) && OrigVT != <STR_LIT> ) Align = OrigVT .


<s> case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>ELFStreamer :: EmitPad ( int64_t Offset ) { SPOffset -=


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; int ObjSize = MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; int LocalFrameSize = MF . getFrameInfo ( ) . getLocalFrameSize ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MI << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ObjSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocalFrameSize << <STR_LIT> ) ; ( void ) LocalFrameSize ; if ( MI . isDebugValue ( ) ) { unsigned FrameReg = getFrameRegister ( MF ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; if ( ! TFI -> hasFP ( MF ) ) { Offset = StackSize + Offset ; if ( FrameIndex >= <NUM_LIT> ) assert ( ( Offset >= <NUM_LIT> && Offset < StackSize ) && <STR_LIT> ) ; } else { if ( FrameIndex >= <NUM_LIT> ) { assert ( ( Offset < <NUM_LIT> && - Offset <= StackSize


<s> assert ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasMSA ( ) && <STR_LIT> ) ; return & <STR_LIT>


<s> const BitVector & getSpilledCSRegisters ( )


<s> } } assert ( EHPadStack . empty ( ) ) ; if ( EHPadToUnwindDest . empty ( ) ) return false ; NumCatchUnwindMismatches += EHPadToUnwindDest . size ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > NewEndTryBBs ; for ( auto & P : EHPadToUnwindDest ) { MachineBasicBlock * EHPad = P . first ; MachineBasicBlock * UnwindDest = P . second ; MachineInstr * Try = EHPadToTry [ EHPad ] ; MachineInstr * EndTry = BeginToEnd [ Try ] ; addTryDelegate ( Try , EndTry , UnwindDest ) ; NewEndTryBBs . insert ( EndTry -> getParent ( ) ) ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isTerminator ( ) ) { for ( auto & MO : MI . operands ( ) ) { if ( MO . isMBB ( ) && NewEndTryBBs . count ( MO . getMBB ( ) ) ) { auto * BrDest = MO . getMBB ( ) ; bool FoundEndBlock = false ; for ( ; std :: next ( BrDest -> getIterator ( ) ) != MF . end ( ) ; BrDest = BrDest -> getNextNode ( ) ) { for ( const auto & MI : * BrDest ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { FoundEndBlock = true ; break ; } } if ( FoundEndBlock ) break ; } assert ( FoundEndBlock ) ; MO . setMBB ( BrDest ) ; } } } } } return


<s> OperandMatchResultTy parseADDR64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegister ( Operands , RegGR , <STR_LIT> , <ISA_LIT>Operand :: ADDR64Reg ,


<s> const MCExpr * LaneIndex ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( LaneIndex ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LaneIndex ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; int64_t Val = CE -> getValue ( ) ; if ( Val < <NUM_LIT> || Val > <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return


<s> static void arm_init_fp16_builtins ( void ) { arm_simd_floatHF_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( arm_simd_floatHF_type_node ) = GET_MODE_PRECISION ( HFmode ) ; layout_type ( arm_simd_floatHF_type_node


<s> if ( isTargetDarwin ( ) ) return <STR_LIT> ; return nullptr


<s> break ; case <STR_LIT> : case <STR_LIT> : { MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; if ( Op1 . isSymbol ( ) ) { StringRef Name ( Op1 . getSymbolName ( ) ) ; if ( Name == TLI . getLibcallName ( RTLIB :: MEMCPY ) || Name == TLI . getLibcallName ( RTLIB :: MEMMOVE ) || Name == TLI . getLibcallName ( RTLIB :: MEMSET ) ) { LibFunc :: Func Func ; if ( LibInfo . getLibFunc ( Name , Func ) ) { const auto & Op2 = MI . getOperand ( <NUM_LIT> ) ; if ( ! Op2 . isReg ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; unsigned OldReg = MO . getReg ( ) ; unsigned NewReg = Op2 . getReg ( ) ; if ( MRI . getRegClass ( NewReg ) != MRI . getRegClass ( OldReg ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; Changed |= MaybeRewriteToDrop ( OldReg , NewReg , MO , MFI , MRI ) ; } } } break ; } case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT>


<s> void EmitAdjustRSP ( MCContext & Ctx , MCStreamer & Out , long Offset ) { const MCExpr * Disp = MCConstantExpr :: Create ( Offset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT>

, <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ;


<s> static MCTargetStreamer * createMCAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream &

OS , MCInstPrinter * InstPrint , bool IsVerboseAsm ) {


<s> SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> Function * Callee = CB . getCalledFunction ( ) ; if ( ! Callee || Callee -> size ( ) != <NUM_LIT> ) return false ; const BasicBlock & BB = Callee -> getEntryBlock ( ) ; if ( const Instruction * I = BB . getFirstNonPHI ( ) ) { if ( ! isa < CallInst > ( I


<s> void <ISA_LIT>InstPrinterBase :: printRegName ( raw_ostream &


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE


<s> requiresRegisterScavenging ( const MachineFunction


<s> uint32_t Extended = FullValue + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo ::

addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> static const FunctionType * getType ( LLVMContext & Context , unsigned id ) { const Type * ResultTy = NULL ; std :: vector < const Type * > ArgTys ; bool IsVarArg =


<s> if ( small_symbolic_operand ( x , Pmode ) ) return true ; if ( GET_CODE ( x ) == LO_SUM ) { rtx ofs = XEXP ( x , <NUM_LIT> ) ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) < GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) x = SUBREG_REG ( x ) ; if ( ! ( REG_P ( x ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( x ) : NONSTRICT_REG_OK_FOR_BASE_P ( x ) ) ) ) return false ; if ( local_symbolic_operand ( ofs , Pmode ) || dtp32_symbolic_operand ( ofs , Pmode ) || tp32_symbolic_operand ( ofs , Pmode


<s> static uint16_t name ( struct InternalInstruction * insn , OperandType type , \ uint8_t index , uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ if ( insn -> rexPrefix && index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _AX + index ; \ case TYPE_R32 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ index &= mask ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _RAX + index ; \ case TYPE_ZMM : \ return prefix ## _ZMM0 + index ; \ case TYPE_YMM : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_TMM : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _TMM0 + index ; \ case TYPE_VK : \ index &= <NUM_LIT> ; \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_VK_PAIR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0_K1 + ( index / <NUM_LIT> ) ; \ case

TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( ( index & <NUM_LIT> ) > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + ( index & <NUM_LIT> ) ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ case TYPE_MVSIBX : \ return prefix ## _XMM0 + index ; \ case TYPE_MVSIBY : \ return prefix ## _YMM0 + index ; \ case TYPE_MVSIBZ : \ return prefix ## _ZMM0 + index ; \ } \ }


<s> switch ( RC -> getID ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( isHReg ( Reg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT>


<s> assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= ( RC -> getSize ( ) / <NUM_LIT> ) && <STR_LIT> ) ; unsigned Alignment = ( RC -> getSize ( ) / <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >=

Alignment ) || RI . canRealignStack ( MF ) ;


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvt_roundss_si32 ( __m128 __A , const int __R ) { return ( int ) __builtin_ia32_vcvtss2si32 ( ( __v4sf )


<s> static int riscv_address_cost ( rtx addr , enum machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { return riscv_address_insns ( addr , mode , false


<s> } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; UndefElts = UndefElts [ <NUM_LIT> ] ; break ; case <STR_LIT> : case <STR_LIT> : simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; if ( ! UndefElts2 [ <NUM_LIT> ] ) UndefElts . clearBit ( <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { APInt DemandedElts2 = DemandedElts ; DemandedElts2 . clearBit ( <NUM_LIT> ) ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts2 , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; UndefElts . clearBit ( <NUM_LIT> ) ; UndefElts |= UndefElts2 [ <NUM_LIT> ] ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts ) ; if ( ! DemandedElts [ <NUM_LIT> ] ) { IC . addToWorklist ( & II ) ; return II . getArgOperand ( <NUM_LIT> ) ; } DemandedElts = <NUM_LIT> ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts2 ) ; simplifyAndSetOp ( & II , <NUM_LIT> , DemandedElts , UndefElts3 ) ; if ( ! UndefElts2 [ <NUM_LIT> ] || ! UndefElts3 [ <NUM_LIT> ] ) UndefElts . clearBit ( <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto * Ty0 = II . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; unsigned InnerVWidth = cast < FixedVectorType > ( Ty0 ) -> getNumElements ( ) ; assert ( VWidth == ( InnerVWidth * <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = Ty0 -> getPrimitiveSizeInBits


<s> unsigned int low ; unsigned int high ; unsigned int frame_size ; unsigned int stack_size ; unsigned int register_mask ; unsigned int regs_size ; unsigned int reg ; unsigned HOST_WIDE_INT total_size ; if ( is_naked_func ( NULL_TREE ) ) { gcc_assert ( ! is_sibcall ) ; emit_jump_insn ( gen_naked_return ( ) ) ; return ; } rx_get_stack_layout ( & low , & high , & register_mask , & frame_size , & stack_size ) ; total_size = frame_size + stack_size ; regs_size = ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ; if ( is_sibcall || is_fast_interrupt_func ( NULL_TREE ) || is_interrupt_func ( NULL_TREE ) || register_mask ) { if ( total_size ) gen_safe_add ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( total_size ) , false ) ; if ( MUST_SAVE_ACC_REGISTER ) { unsigned int acc_low , acc_high ; if ( register_mask ) { acc_low = acc_high = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < CC_REGNUM ; reg ++ ) if ( register_mask & ( <NUM_LIT> << reg ) ) { if ( acc_low == <NUM_LIT> ) acc_low = reg ; else { acc_high = reg ; break ; } } emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , acc_high ) ) ) ; emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , acc_low ) ) ) ; } else { acc_low = low ; acc_high = low + <NUM_LIT> ; emit_insn ( gen_stack_popm ( GEN_INT ( <NUM_LIT> * UNITS_PER_WORD ) , gen_rx_popm_vector ( acc_low , acc_high ) ) ) ; } emit_insn ( gen_ashlsi3 ( gen_rtx_REG ( SImode , acc_low ) , gen_rtx_REG ( SImode , acc_low ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_mvtaclo ( gen_rtx_REG ( SImode , acc_low ) ) ) ; emit_insn ( gen_mvtachi ( gen_rtx_REG ( SImode , acc_high ) ) ) ; } if ( register_mask ) { for ( reg = <NUM_LIT> ; reg < CC_REGNUM ; reg ++ ) if ( register_mask & ( <NUM_LIT> << reg ) ) emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , reg ) ) ) ; } else if ( low ) { if ( high == low ) emit_insn ( gen_stack_pop ( gen_rtx_REG ( SImode , low ) ) ) ; else emit_insn ( gen_stack_popm ( GEN_INT ( regs_size ) , gen_rx_popm_vector ( low , high ) ) ) ; } if ( is_fast_interrupt_func ( NULL_TREE ) ) { gcc_assert ( ! is_sibcall ) ; emit_jump_insn ( gen_fast_interrupt_return ( ) ) ; } else if ( is_interrupt_func ( NULL_TREE ) ) { gcc_assert ( ! is_sibcall ) ; emit_jump_insn ( gen_exception_return ( ) ) ; } else if ( ! is_sibcall ) emit_jump_insn ( gen_simple_return ( ) ) ; return ; } if ( total_size


<s> case TLSModel :: LocalDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = DAG . getNode ( <STR_LIT> , DL


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return


<s> void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerOperand ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const


<s> rtx cond2 ; bool invert_move = false ; if ( VECTOR_UNIT_NONE_P ( dest_mode ) ) return <NUM_LIT> ; gcc_assert ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( mask_mode ) && GET_MODE_NUNITS ( dest_mode ) == GET_MODE_NUNITS ( mask_mode ) ) ; switch ( rcode ) { case NE : case UNLE : case UNLT : case UNGE : case UNGT : invert_move = true ; rcode = reverse_condition_maybe_unordered ( rcode ) ; if ( rcode == UNKNOWN ) return <NUM_LIT> ; break ; case GE : case LE : if ( GET_MODE_CLASS ( mask_mode ) == MODE_VECTOR_INT ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; case GTU : case GEU : case LTU : case LEU : cc_mode = CCUNSmode ; if ( rcode == GEU || rcode == LEU ) { invert_move = true ; rcode = reverse_condition ( rcode ) ; } break ; default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return <NUM_LIT> ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return <NUM_LIT> ; } else if ( op_true == constant_0 && op_false == constant_m1 ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_NOT ( dest_mode , mask ) ) ) ; return <NUM_LIT> ; } if ( op_true == constant_m1 ) op_true = mask ; if ( op_false == constant_0 ) op_false = mask ; } if ( ! REG_P ( op_true ) && ! SUBREG_P ( op_true ) ) op_true = force_reg ( dest_mode , op_true ) ; if ( ! REG_P ( op_false ) && ! SUBREG_P ( op_false ) ) op_false = force_reg ( dest_mode , op_false ) ; cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2


<s> bool <ISA_LIT>InstrInfo :: isVector ( const


<s> void addThumbModImmNeg1_7Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Val = - CE ->


<s> bool <ISA_LIT>TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty ->


<s> if ( ! Subtarget -> hasV6T2Ops ( ) ) return NULL ; unsigned Shl_imm = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Shl_imm ) ) { assert ( Shl_imm > <NUM_LIT> && Shl_imm < <NUM_LIT> && <STR_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Srl_imm ) ) { assert ( Srl_imm > <NUM_LIT> && Srl_imm <


<s> switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = <NUM_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( signExtend && extendOpc


<s> struct ix86_address parts ; rtx base , index , disp ; HOST_WIDE_INT scale ; addr_space_t seg ; if ( ix86_decompose_address ( addr , & parts ) <= <NUM_LIT> ) return false ; base = parts . base ; index = parts . index ; disp = parts . disp ; scale = parts . scale ; seg = parts . seg ; if ( base ) { rtx reg = ix86_validate_address_register ( base ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_BASE_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_BASE_NONSTRICT_P ( reg ) ) ) return false ; } if ( index ) { rtx reg = ix86_validate_address_register ( index ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_INDEX_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P ( reg ) ) ) return false ; } if ( base && index && GET_MODE ( base ) != GET_MODE ( index ) ) return false ; if ( seg != ADDR_SPACE_GENERIC && ( ( base && GET_MODE ( base ) != word_mode ) || ( index && GET_MODE ( index ) != word_mode ) ) ) return false ; if ( scale != <NUM_LIT> ) { if ( ! index ) return false ; if ( scale != <NUM_LIT> && scale != <NUM_LIT> && scale != <NUM_LIT> ) return false ; } if ( disp ) { if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) != UNSPEC_MACHOPIC_OFFSET ) switch ( XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : gcc_assert ( flag_pic ) ; if ( ! TARGET_64BIT ) goto is_legitimate_pic ; return false ; case UNSPEC_GOTPCREL : case UNSPEC_PCREL : gcc_assert ( flag_pic ) ; goto is_legitimate_pic ; case UNSPEC_GOTTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : case UNSPEC_NTPOFF : case UNSPEC_DTPOFF


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF (

make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> switch ( static_cast < uint32_t > ( getKind ( ) ) ) { case VK_CALL : return <STR_LIT> ; case VK_LO12 : return <STR_LIT> ; case VK_ABS_G3 : return <STR_LIT> ; case VK_ABS_G2 : return <STR_LIT> ; case VK_ABS_G2_S : return <STR_LIT> ; case VK_ABS_G2_NC : return <STR_LIT> ; case VK_ABS_G1 : return <STR_LIT> ; case VK_ABS_G1_S : return <STR_LIT> ; case VK_ABS_G1_NC : return <STR_LIT> ; case VK_ABS_G0 : return <STR_LIT> ; case VK_ABS_G0_S : return <STR_LIT> ; case VK_ABS_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_HI12 :


<s> SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } if ( F . hasStructRetAttr ( ) && ( Subtarget -> is64Bit ( ) || Subtarget -> isTargetKnownWindowsMSVC ( ) ) ) { unsigned Reg = <ISA_LIT>MFInfo -> getSRetReturnReg ( ) ; assert ( Reg && <STR_LIT> ) ; unsigned CopyTo = Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CopyTo ) . addReg ( Reg ) ; } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB .

addReg ( RetRegs [ i ] , RegState :: Implicit ) ;


<s> return isSPVFP ? ( decodeRd ( insn ) << <NUM_LIT> | getDBit ( insn ) ) : ( decodeRd ( insn ) | getDBit ( insn


<s> else type = <STR_LIT> ; format = <STR_LIT> TYPE_OPERAND_FMT ; format = <STR_LIT> ; fprintf ( asm_out_file , format , type ) ; if ( flags & SECTION_ENTSIZE ) fprintf ( asm_out_file , <STR_LIT> , flags & SECTION_ENTSIZE ) ; if ( HAVE_COMDAT_GROUP && ( flags & SECTION_LINKONCE ) ) { if ( TREE_CODE ( decl ) == IDENTIFIER_NODE ) fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( decl ) ) ; else fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( DECL_COMDAT_GROUP ( decl ) ) ) ; } } putc ( '\n' ,


<s> target_flags |= MASK_EXPLICIT_RELOCS ; targetm . min_anchor_offset = <NUM_LIT> ; targetm . max_anchor_offset = <NUM_LIT> ; targetm . const_anchor = <NUM_LIT> ; target_flags &= ~ MASK_RELAX_PIC_CALLS ; target_flags &= ~ MASK_FIX_R4000 ; if ( flag_pic && ! TARGET_OLDABI ) sorry ( <STR_LIT> ) ; if ( TARGET_XGOT ) sorry ( <STR_LIT> ) ; if ( TARGET_HARD_FLOAT_ABI && ! TARGET_OLDABI ) sorry ( <STR_LIT> ) ; } else { if ( TARGET_MICROMIPS ) target_flags &= ~ MASK_BRANCHLIKELY ; if ( TARGET_64BIT ) { if ( align_loops == <NUM_LIT> ) align_loops = <NUM_LIT> ; if ( align_jumps == <NUM_LIT> ) align_jumps = <NUM_LIT> ; if ( align_functions == <NUM_LIT> ) align_functions = <NUM_LIT> ; } targetm . min_anchor_offset


<s> MI -> setDesc ( TII -> get ( TargetOpcode :: COPY ) ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; ++ MI ; } } if ( I != -- ( MR -> end ( ) ) && MBB -> getFirstTerminator ( ) == MBB -> end ( ) ) { assert ( false && <STR_LIT> ) ; assert ( ! MBB ->


<s> break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : ResultReg = createResultReg ( & <STR_LIT> ) ; break ; default : return false ; } } SmallVector < unsigned , <NUM_LIT> > Args ; for ( unsigned I = <NUM_LIT> , E = Call -> getNumArgOperands ( ) ; I < E ; ++ I ) { Value * V = Call -> getArgOperand ( I ) ; <STR_LIT> ArgTy = getSimpleType ( V -> getType ( ) ) ; if ( ArgTy == <STR_LIT> ) return false ; const AttributeList & Attrs = Call -> getAttributes ( ) ; if ( Attrs . hasParamAttribute ( I , Attribute :: ByVal ) || Attrs . hasParamAttribute ( I , Attribute :: SwiftSelf ) || Attrs . hasParamAttribute ( I , Attribute :: SwiftError ) || Attrs . hasParamAttribute ( I , Attribute :: InAlloca ) || Attrs . hasParamAttribute ( I , Attribute :: Nest ) ) return false ; unsigned Reg ; if ( Attrs . hasParamAttribute ( I , Attribute :: SExt ) ) Reg = getRegForSignedValue ( V ) ; else if ( Attrs . hasParamAttribute ( I , Attribute :: ZExt ) ) Reg = getRegForUnsignedValue ( V ) ; else Reg = getRegForValue ( V ) ; if ( Reg == <NUM_LIT> ) return false ; Args . push_back ( Reg ) ; } unsigned CalleeReg = <NUM_LIT> ; if ( ! IsDirect ) { CalleeReg = getRegForValue ( Call -> getCalledOperand ( ) ) ; if ( ! CalleeReg ) return false ; } auto MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; if ( ! IsVoid ) MIB . addReg


<s> CallContext ( ) : Call ( nullptr ) , SPCopy ( nullptr ) , ExpectedDist ( <NUM_LIT> ) ,

MovVector ( <NUM_LIT> , nullptr ) , NoStackParams ( false ) , UsePush ( false ) { }


<s> if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) . addMemOperand ( MMO ) ; else { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } return


<s> for ( uint64_t I = <NUM_LIT> ; I != Count ; ++


<s> if ( avr_arch -> asm_only ) cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_HAVE_MUL ) { cpp_define ( pfile , <STR_LIT> ) ; cpp_define ( pfile , <STR_LIT> ) ; } if ( AVR_HAVE_JMP_CALL ) cpp_define ( pfile , <STR_LIT> ) ; if ( avr_arch -> have_jmp_call ) cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_SHORT_CALLS ) cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_XMEGA ) cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_TINY ) { cpp_define ( pfile , <STR_LIT> ) ; cpp_define_formatted ( pfile , <STR_LIT> , avr_arch -> flash_pm_offset ) ; } if ( avr_arch -> flash_pm_offset ) cpp_define_formatted ( pfile , <STR_LIT> , avr_arch -> flash_pm_offset ) ; if ( AVR_HAVE_EIJMP_EICALL ) { cpp_define ( pfile , <STR_LIT> ) ; cpp_define ( pfile , <STR_LIT> ) ; } else { cpp_define ( pfile , <STR_LIT> ) ; } if ( AVR_HAVE_8BIT_SP ) cpp_define ( pfile , <STR_LIT> ) ; else cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_HAVE_SPH ) cpp_define ( pfile , <STR_LIT> ) ; else cpp_define ( pfile , <STR_LIT> ) ; if ( TARGET_NO_INTERRUPTS ) cpp_define ( pfile , <STR_LIT> ) ; if ( TARGET_SKIP_BUG ) { cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_HAVE_JMP_CALL ) cpp_define ( pfile , <STR_LIT> ) ; } if ( TARGET_RMW ) cpp_define ( pfile , <STR_LIT> ) ; cpp_define_formatted ( pfile , <STR_LIT> , avr_arch -> sfr_offset ) ; cpp_define ( pfile , <STR_LIT> ) ; cpp_define ( pfile , <STR_LIT> ) ; cpp_define ( pfile


<s> const char * platform ; platform = elf_platform ( ) ; if ( platform != NULL ) return platform ; else return


<s> MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI


<s> for ( int Idx : Mask ) { if ( Idx == - <NUM_LIT> ) return false ; Sum += Idx ; } int N = Mask . size ( ) ; return <NUM_LIT> * Sum == N * (


<s> unsigned BBNum = BB -> getNumber ( ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned Offset = BBInfo [ i - <NUM_LIT> ] . Offset + BBInfo [ i - <NUM_LIT> ] . Size ; BBInfo [ i ] . Offset =


<s> explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , pragma_or_attr ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ,


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; MachineInstr * LastInst = I ; return true


<s> else if ( TARGET_THUMB1 ) fprintf ( stream , <STR_LIT> ) ; else fprintf ( stream , <STR_LIT> ) ; } else fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> ,


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr *


<s> tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; rtx pat ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode2 ) ) op0 = copy_to_mode_reg ( mode2 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode1 ) ) op2 = copy_to_mode_reg ( mode1 , op2 ) ; pat = GEN_FCN ( icode ) (


<s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( IsCapMode ? <STR_LIT> : <STR_LIT> ) ; Res . addOperand ( MCOperand :: createReg ( IsCapMode ? <STR_LIT> : <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef ShiftName = Tok . getString ( ) ; if ( ShiftName != <STR_LIT> && ShiftName != <STR_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ShiftAmount ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE


<s> CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int ncrn , nvrn , nregs ; bool allocate_ncrn , allocate_nvrn ; HOST_WIDE_INT size ; if ( pcum -> aapcs_arg_processed ) return ; pcum -> aapcs_arg_processed = true ; size = ROUND_UP ( type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; allocate_ncrn = ( type ) ? ! ( FLOAT_TYPE_P ( type ) ) : ! FLOAT_MODE_P ( mode ) ; allocate_nvrn = aarch64_vfp_is_call_candidate ( pcum_v , mode , type , & nregs ) ; nvrn = pcum -> aapcs_nvrn ; if ( allocate_nvrn ) { if ( ! TARGET_FLOAT ) aarch64_err_no_fpadvsimd ( mode , <STR_LIT> ) ; if ( nvrn + nregs <= NUM_FP_ARG_REGS ) { pcum -> aapcs_nextnvrn = nvrn + nregs ; if ( ! aarch64_composite_type_p ( type , mode ) ) { gcc_assert ( nregs == <NUM_LIT> ) ; pcum -> aapcs_reg = gen_rtx_REG ( mode , V0_REGNUM + nvrn ) ; } else { rtx par ; int i


<s> <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const GCNSubtarget & Subtarget = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; Info -> allocateModuleLDSGlobal ( F . getParent ( ) ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; if ( ! IsEntryFunc ) { Register ReturnAddrReg = TRI -> getReturnAddressReg ( MF ) ; Register LiveInReturn = MF . addLiveIn ( ReturnAddrReg , & <STR_LIT> ) ; MBB . addLiveIn ( ReturnAddrReg ) ; B . buildCopy ( LiveInReturn , ReturnAddrReg ) ; } if ( Info -> hasImplicitBufferPtr ( ) ) { Register ImplicitBufferPtrReg = Info -> addImplicitBufferPtr ( * TRI ) ; MF . addLiveIn ( ImplicitBufferPtrReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( ImplicitBufferPtrReg ) ; } SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; unsigned P<ISA_LIT>nputNum = <NUM_LIT> ; if ( ! FLI . CanLowerReturn ) insertSRetIncomingArgument ( F , SplitArgs , FLI . DemoteRegister , MRI , DL ) ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == <NUM_LIT> ) continue ; const bool InReg = Arg . hasAttribute ( Attribute :: InReg ) ; if ( ! IsGraphics && InReg ) return false ; if ( Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; if ( CC == CallingConv :: <ISA_LIT>_PS && ! InReg && P<ISA_LIT>nputNum <= <NUM_LIT> ) { const bool ArgUsed = ! Arg .


<s> bool R600InstrInfo :: usesAddressRegister ( MachineInstr * MI ) const { return MI -> findRegisterUseOperandIdx ( AMDGPU :: AR_X )


<s> bool <ISA_LIT>TargetLowering :: isIntDivCheap ( EVT VT , AttributeList Attr ) const { return true


<s> return NULL_TREE ; } if ( ! VECTOR_TYPE_P ( type ) ) { error ( <STR_LIT> , <STR_LIT> , type ) ; return NULL_TREE ; } if ( ! sizeless_type_p ( type ) ) { error ( <STR_LIT> , <STR_LIT> , type ) ; return NULL_TREE ; } tree size = TREE_VALUE ( args ) ; if ( TREE_CODE ( size ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return NULL_TREE ; } unsigned HOST_WIDE_INT value = tree_to_uhwi ( size ) ; if ( maybe_ne ( value , BITS_PER_SVE_VECTOR ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; return NULL_TREE ; } tree new_sve_type_args = copy_list ( TREE_VALUE ( attr ) ) ; tree mangled_name_node = chain_index ( <NUM_LIT> , new_sve_type_args ) ; const char * old_mangled_name = IDENTIFIER_POINTER ( TREE_VALUE ( mangled_name_node ) ) ; char * new_mangled_name = xasprintf ( <STR_LIT> , old_mangled_name , ( int ) value ) ; TREE_VALUE ( mangled_name_node ) = get_identifier ( new_mangled_name ) ; free ( new_mangled_name


<s> return ( Kind == k_Register && Reg . Kind == RegKind :: SVEDataVector ) && <ISA_LIT>MCRegisterClasses [


<s> unsigned ValLen = ValTy . getVectorNumElements ( ) ; unsigned ResLen = ResTy . getVectorNumElements ( ) ; if ( ValLen == ResLen ) return Val ; const SDLoc & dl ( Val ) ; assert ( ValLen < ResLen ) ; assert ( ResLen % ValLen == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Concats


<s> rtx src = operands [ <NUM_LIT> ] ; rtx dst_addr , src_addr ; HOST_WIDE_INT size ; int align = INTVAL ( operands [ <NUM_LIT> ] ) ; unsigned n_pieces ; int piece = align ; rtx store [ <NUM_LIT> ] ; rtx tmpx [ <NUM_LIT> ] ; int i ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) return false ; size = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( align >= <NUM_LIT> ) { if ( TARGET_LL64 ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( ( size >> <NUM_LIT> ) & <NUM_LIT> ) + ( size & <NUM_LIT> ) ; else n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( size & <NUM_LIT> ) ; } else if ( align == <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ) return false ; if ( TARGET_LL64 && ( piece >= <NUM_LIT> ) && ( size >= <NUM_LIT> ) ) piece = <NUM_LIT> ; else if ( piece > <NUM_LIT> ) piece = <NUM_LIT> ; dst_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ; src_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> )


<s> void addRegACCRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; unsigned List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; unsigned DstPtr ; if ( Align > PtrSize ) { unsigned AlignMinus1 = MRI . createGenericVirtualRegister ( IntPtrTy ) ; MIRBuilder . buildConstant ( AlignMinus1 , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( ListTmp , List , AlignMinus1 ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ; unsigned SizeReg = MRI . createGenericVirtualRegister ( IntPtrTy ) ; MIRBuilder . buildConstant ( SizeReg , alignTo ( ValSize , PtrSize ) ) ; unsigned NewList = MRI .


<s> EVT VecVT = N -> getValueType ( <NUM_LIT> ) ; EVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = <NUM_LIT> / ElVT


<s> if ( Lane . getOpcode ( ) == <STR_LIT> ) { APInt LowBits ( EltTy . getSizeInBits ( ) , cast < ConstantSDNode > ( Lane ) -> getZExtValue ( ) ) ; Lane = DAG . getConstant ( LowBits . getZExtValue ( ) , <STR_LIT> ) ; } Ops . push_back ( Lane ) ; } return DAG . getNode ( <STR_LIT> , dl , VT


<s> const CallLowering * getCallLowering ( ) const override { return CL . get (


<s> static SDValue PerformExtendCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = N0 . getOperand ( <NUM_LIT> ) ; SDValue Lane = N0 . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EltVT = N0 . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> } else llvm_unreachable ( <STR_LIT> ) ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , SubLo , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt

, DoubleRegDest , HiOperand , LoOperand ) ;


<s> if ( Hzd -> isXResBusy ( xuse ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << ( dstSide ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ) ; return false ; } if ( Hzd -> moveUnitsAvailable ( dstSide ) ) { Hzd -> bookMove ( dstSide , xuse


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return


<s> EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) <= OptSize ) { S = Signed ; return true ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) { EVT OrigVT = Op . getOperand ( <NUM_LIT>


<s> assert ( LdNode && LdNode -> getOffset ( ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Hi64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LdNode -> getBasePtr ( ) , LdNode -> getPointerInfo ( ) , false , false , false , <NUM_LIT> ) ; EVT addrVT = LdNode -> getBasePtr ( ) . getValueType ( ) ; SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , LdNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , addrVT ) ) ; SDValue Lo64 = DAG . getLoad ( <STR_LIT> , dl , LdNode -> getChain ( ) , LoPtr , LdNode -> getPointerInfo (


<s> dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return <NUM_LIT> ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return


<s> return ( __m128 ) __builtin_ia32_vfmaddsubps128_maskz ( ( __v4sf ) __A , ( __v4sf ) __B , - (


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>64R2 (


<s> RegisterTarget < Triple :: jvm32 > X ( getThe<ISA_LIT>Target32 ( ) , <STR_LIT> , <STR_LIT>


<s> return false ; } int Num1s = ( ImmS & ( Width - <NUM_LIT> ) ) + <NUM_LIT> ; if ( Num1s == Width ) return false ; int Rotation = ( ImmR & ( Width - <NUM_LIT> ) ) ; uint64_t Mask = ( <NUM_LIT> << Num1s ) - <NUM_LIT> ; uint64_t WidthMask = Width == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << Width ) - <NUM_LIT> ; Mask = ( Mask >> Rotation ) | ( ( Mask << ( Width - Rotation ) ) & WidthMask ) ; Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < RegWidth / Width


<s> default : return false ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm = <NUM_LIT> ; break ; case <STR_LIT> : Imm =


<s> BA . Addr -> setCode ( BB ) ; Owner . Addr -> addMember ( BA , *


<s> if ( Printer . TM . getTargetTriple ( ) . isOSDarwin ( ) ) return lowerSymbolOperandDarwin ( MO , Sym ) ; if ( Printer . TM . getTargetTriple ( ) . isOSBinFormatCOFF ( ) ) return lowerSymbolOperandCOFF ( MO , Sym ) ; assert ( Printer . TM . getTargetTriple ( ) . isOSBinFormatELF ( ) && <STR_LIT> ) ; return lowerSymbolOperandELF ( MO , Sym


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeAlloca ( const AllocaInst * AI ) { return AI && <NUM_LIT>


<s> std :: string <ISA_LIT>AsmPrinter :: regToString ( const MachineOperand & MO ) { unsigned RegNo = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( RegNo ) && <STR_LIT>


<s> else if ( ! DC -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( DC -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( DC -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( DC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * AT = <STR_LIT> ( Op ) ; if ( ! AT ) return TokError ( <STR_LIT> ) ; else if ( ! AT -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( AT -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( AT -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( AT -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string (


<s> SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl