<s> if ( IdxVal == <NUM_LIT> ) { SDValue ShiftBits = DAG . getTargetConstant ( SubVecNumElems , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , ShiftBits ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , SubVec , ZeroIdx ) ; Op = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , SubVec ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Op , ZeroIdx ) ; } SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , SubVec , ZeroIdx ) ; if ( Vec . isUndef ( ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( <STR_LIT> ( Vec . getNode ( ) ) ) { assert ( IdxVal != <NUM_LIT> && <STR_LIT> ) ; NumElems = WideOpVT . getVectorNumElements ( ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; if ( ShiftRight != <NUM_LIT> ) SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( ShiftRight , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec , ZeroIdx ) ; } if ( IdxVal + SubVecNumElems == NumElems ) { SubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , SubVec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; if ( SubVecNumElems * <NUM_LIT> == NumElems ) { Vec = DAG . getNode ( <STR_LIT> , dl , SubVecVT , Vec , ZeroIdx ) ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , DAG . getConstant ( <NUM_LIT> , dl , WideOpVT ) , Vec , ZeroIdx ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT


<s> MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo (


<s> unsigned <ISA_LIT>_MC :: GetELFFlags ( const MCSubtargetInfo & STI ) { static std :: map < StringRef , unsigned > ElfFlags = { { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V5 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V55 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V60 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V62 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V65 } , } ; auto F = ElfFlags . find ( STI . getCPU ( ) ) ; assert ( F != ElfFlags . end ( ) && <STR_LIT> ) ; return F -> second


<s> inline SDValue XformSToSM2Imm ( unsigned Imm , const


<s> unsigned getReg ( ) const override { assert ( Kind == Register && <STR_LIT> ) ; return Reg .


<s> if ( GET_MODE ( insn ) == SImode ) { while ( GET_MODE ( insn ) != QImode


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ; return CostKind == TTI :: TCK_RecipThroughput ?


<s> return isImmTy ( ImmTyDFMT ) && isUInt <


<s> void msp430_start_function ( FILE * file , const char * name , tree decl ) { tree int_attr ; int_attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; if ( int_attr != NULL_TREE ) { tree intr_vector = TREE_VALUE ( int_attr ) ; if ( intr_vector != NULL_TREE ) { char buf [ <NUM_LIT> ] ; intr_vector = TREE_VALUE ( intr_vector ) ; if ( TREE_CODE ( intr_vector ) == STRING_CST ) sprintf ( buf , <STR_LIT> , TREE_STRING_POINTER ( intr_vector ) ) ; else sprintf ( buf , <STR_LIT> , ( unsigned int ) TREE_INT_CST_LOW ( intr_vector ) ) ; switch_to_section ( get_section ( buf , SECTION_CODE , decl ) ) ; fputs ( <STR_LIT> , file


<s> if ( It == BlockInfoMap . end ( ) ) return false ; return ( * It )


<s> unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec ,


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; bool NeedsStackRealignment = RegInfo . needsStackRealignment ( MF ) ; if ( ! NeedsStackRealignment && MFI . getMaxAlignment ( ) > getStackAlignment ( ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; NumBytes = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; if ( MFI . getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) .


<s> buildCFAOffs ( InsMBB , InsPt , DL , SPOffsetFromCFA , ZII ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( InsMBB , InsPt , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( Size - <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } ; bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; MachineBasicBlock * DoneMBB = nullptr ; MachineBasicBlock * LoopMBB = nullptr ; if ( NumFullBlocks < <NUM_LIT> ) { for ( unsigned int i = <NUM_LIT> ; i < NumFullBlocks ; i ++ ) allocateAndProbe ( * MBB , MBBI , ProbeSize , true ) ; } else { uint64_t LoopAlloc = ProbeSize * NumFullBlocks ; SPOffsetFromCFA -= LoopAlloc ; BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; buildDefCFAReg ( * MBB , MBBI , DL , <STR_LIT> , ZII ) ; emitIncrement ( * MBB , MBBI , DL , <STR_LIT> , - int64_t ( LoopAlloc ) , ZII ) ; buildCFAOffs ( * MBB , MBBI , DL , - int64_t ( <STR_LIT> + LoopAlloc ) , ZII ) ; DoneMBB = <STR_LIT> ( MBBI , MBB ) ; LoopMBB = <STR_LIT> ( MBB ) ; MBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; MBB = LoopMBB ; allocateAndProbe ( * MBB , MBB -> end ( ) , ProbeSize , false ) ; BuildMI ( * MBB , MBB -> end ( ) , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * MBB , MBB -> end ( ) , DL , ZII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( MBB ) ; MBB = DoneMBB ; MBBI = DoneMBB -> begin ( ) ; buildDefCFAReg ( * MBB , MBBI , DL , <STR_LIT> , ZII ) ; } if ( Residual ) allocateAndProbe ( * MBB , MBBI , Residual , true ) ; if ( StoreBackchain ) BuildMI ( * MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( getBackchainOffset ( MF ) ) . addReg ( <NUM_LIT> ) ; StackAllocMI -> eraseFromParent ( ) ; if ( DoneMBB


<s> st_addr_1 = change_address ( dmem , DImode , gen_rtx_AND ( DImode , dmema , im8 ) ) ; set_mem_alias_set ( st_addr_1 , <NUM_LIT> ) ; emit_move_insn ( st_tmp_2 , st_addr_2 ) ; emit_move_insn ( st_tmp_1 , st_addr_1 ) ; dreg = copy_addr_to_reg ( dmema ) ; if ( data_regs != NULL ) { for ( i = words - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { emit_insn ( gen_insqh ( ins_tmps [ i ] , data_regs [ i ] , dreg ) ) ; emit_insn ( gen_insql ( data_regs [ i ] , data_regs [ i ] , dreg ) ) ; } for ( i = words - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { ins_tmps [ i - <NUM_LIT> ] = expand_binop ( DImode , ior_optab , data_regs [ i ] , ins_tmps [ i - <NUM_LIT> ]

, ins_tmps [ i - <NUM_LIT> ] , <NUM_LIT> , OPTAB_WIDEN ) ;


<s> static bool isVecReg ( unsigned Reg ) { return ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg

>= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ;


<s> StringRef getPassName ( ) const override { return


<s> <STR_LIT> <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT ValType )


<s> } } if ( ChangeName ) { ( const_cast < GlobalVariable * > ( & GV ) ) -> setName ( str ) ; } O << '\t' ; Type * InitTy = Ty -> getElementType ( ) ; unsigned NElts = ~ <NUM_LIT> ; Type * EmitTy = <STR_LIT> ( InitTy , NElts , DL ) ; printAlignTypeQualifier ( GV , DL , InitTy , EmitTy , NElts , true , O ) ; str = <STR_LIT> ; O << '_' << getArgTypeName ( EmitTy ) << <STR_LIT> << GV . getName ( ) ; if ( NElts != <NUM_LIT> ) O << '[' << NElts << ']' ; if ( GV . hasInitializer ( ) && canInitAddressSpace ( AS ) ) { O << <STR_LIT> ; printGVInitialValue ( GV , cast < Constant > ( GV . getInitializer ( ) ) , DL , O ) ; } } } } const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; uint64_t SpillSize , PrivateSize ; unsigned PrivateAlign , SpillAlign ; computeStackUsage ( MFI , PrivateSize , PrivateAlign , SpillSize , SpillAlign ) ; if ( PrivateSize != <NUM_LIT> ) { O << <STR_LIT> << PrivateAlign << <STR_LIT> << PrivateSize << <STR_LIT> ; } if ( SpillSize != <NUM_LIT> ) { O << <STR_LIT> << SpillAlign << <STR_LIT> << SpillSize << <STR_LIT> ; } const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( Info -> hasScavengerSpill ( ) ) O << <STR_LIT> ; if ( usesGCNAtomicCounter ( ) ) O << <STR_LIT> ; OutStreamer -> EmitRawText ( O . str (


<s> return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op )


<s> SDValue <ISA_LIT>TargetLowering :: performMulCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Mul ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , N1 ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , N1 ) ; } else


<s> Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL ,


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . EatToEndOfStatement ( ) ; return Error ( L , <STR_LIT> ) ; } RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) ) ; Parser . Lex


<s> } if ( Mld -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = Mld -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT LdVT = Mld -> getMemoryVT ( ) ; SDLoc dl ( Mld ) ; assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getScalarSizeInBits ( ) ; unsigned FromSz = LdVT . getScalarSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( ! Mld -> getSrc0 ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat


<s> uint8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> SDValue AMDGPUTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default : Op . getNode ( ) -> dump ( ) ; assert ( <NUM_LIT> &&


<s> typedef std :: vector < MachineBasicBlock * > MBBVector ; MBBVector Preds ( MBB -> pred_begin ( ) , MBB -> pred_end ( ) ) ; for ( MBBVector :: iterator I = Preds . begin ( ) , E = Preds . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * PB = * I ; if ( ! Parent -> getLoopLatch ( ) ) { break ; } if ( PB != Parent -> getLoopLatch ( ) ) { Preheader = PB ; break ; } } if ( Preheader == nullptr ) { Parent = Parent -> getParentLoop ( ) ; continue ; } for ( MachineInstr & MI : Preheader -> instrs ( ) ) { if ( isLoop ( & MI )


<s> else if ( trySkipId ( <STR_LIT> ) ) CPolOn = <STR_LIT> :: SLC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOff = <STR_LIT> :: SLC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOn = <STR_LIT> :: DLC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOff = <STR_LIT> :: DLC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOn = <STR_LIT> :: SCC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOff = <STR_LIT> :: SCC ; else return MatchOperand_NoMatch ; if ( ! isGFX10Plus ( ) && ( ( CPolOn | CPolOff ) & <STR_LIT> :: DLC ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! isGFX90A ( ) && ( ( CPolOn | CPolOff ) & <STR_LIT> :: SCC ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( CPolSeen & ( CPolOn | CPolOff ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CPolSeen |= ( CPolOn | CPolOff ) ; for ( unsigned I = <NUM_LIT> ; I != Operands . size ( ) ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = ST . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; auto Opcode = MI . getOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! MI . mayStore ( ) ) { MachineOperand * TFE = TII -> getNamedOperand ( MI , <STR_LIT> :: tfe ) ; MachineOperand * LWE = TII -> getNamedOperand ( MI , <STR_LIT> :: lwe ) ; MachineOperand * D16 = TII -> getNamedOperand ( MI , <STR_LIT> :: d16 ) ; assert ( ( TFE && LWE ) && <STR_LIT> ) ; unsigned TFEVal = TFE -> getImm ( ) ; unsigned LWEVal = LWE -> getImm ( ) ; unsigned D16Val = D16 ? D16 -> getImm ( ) : <NUM_LIT> ; if ( TFEVal || LWEVal ) { const DebugLoc & DL = MI . getDebugLoc ( ) ; int DstIdx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vdata ) ; MachineOperand * MO_Dmask = TII -> getNamedOperand ( MI , <STR_LIT> :: dmask ) ; assert ( MO_Dmask && <STR_LIT> ) ; unsigned dmask = MO_Dmask -> getImm ( ) ; unsigned ActiveLanes = TII -> isGather4 ( Opcode ) ? <NUM_LIT> : countPopulation ( dmask ) ; static_assert ( <STR_LIT> == <NUM_LIT> && <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; bool Packed = ! ST . hasUnpackedD16VMem ( ) ; unsigned InitIdx = D16Val && Packed ? ( ( ActiveLanes + <NUM_LIT> ) >> <NUM_LIT> ) + <NUM_LIT> : ActiveLanes + <NUM_LIT> ; uint32_t DstSize = RI -> getRegSizeInBits ( * TII -> getOpRegClass ( MI , DstIdx ) ) / <NUM_LIT> ; if ( DstSize < InitIdx ) continue ; unsigned PrevDst = MRI . createVirtualRegister ( TII -> getOpRegClass ( MI


<s> y3 = gen_reg_rtx ( DFmode ) ; u0 = gen_reg_rtx ( DFmode ) ; v0 = gen_reg_rtx ( DFmode ) ; one = force_reg ( DFmode , CONST_DOUBLE_FROM_REAL_VALUE ( dconst1 , DFmode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( DFmode , gen_rtvec ( <NUM_LIT> , d ) , UNSPEC_FRES ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e0 , gen_rtx_MINUS ( DFmode , one , gen_rtx_MULT ( SFmode , d , x0 ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , y1 , gen_rtx_PLUS ( DFmode , gen_rtx_MULT ( DFmode , e0 , x0 ) , x0 ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , e1 , gen_rtx_MULT (


<s> case <STR_LIT> : if ( ! Op . hasOneUse ( ) || ! isTypeLegal ( VT ) || Subtarget . hasQPX ( ) ) break ; const TargetOptions & Options = getTargetMachine ( ) . Options ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; SDLoc Loc ( Op ) ; NegatibleCost N2Cost = NegatibleCost :: Expensive ; SDValue NegN2 = getNegatedExpression ( N2 , DAG , LegalOps , OptForSize , N2Cost , Depth + <NUM_LIT> ) ; if ( ! NegN2 ) return SDValue ( ) ; if ( Flags . hasNoSignedZeros ( ) || Options . NoSignedZerosFPMath ) { NegatibleCost N0Cost = NegatibleCost :: Expensive ; SDValue NegN0 = getNegatedExpression ( N0 , DAG , LegalOps , OptForSize , N0Cost , Depth + <NUM_LIT> ) ; NegatibleCost N1Cost = NegatibleCost ::


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF


<s> MachineBasicBlock :: iterator FrameSetup = Context . FrameSetup ; MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; TII -> setFrameAdjustment ( * FrameSetup , Context . ExpectedDist ) ; DebugLoc DL = FrameSetup -> getDebugLoc ( ) ; bool Is64Bit = STI -> is64Bit ( ) ; for ( int Idx = ( Context . ExpectedDist >> Log2SlotSize ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator Store = * Context . ArgStoreVector [ Idx ] ; MachineOperand PushOp = Store -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; unsigned PushOpcode ; switch ( Store -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; Push -> cloneMemRefs ( MF , * Store ) ; break ; case <STR_LIT>


<s> return __builtin_ia32_vec_ext_v2si ( ( __v2si


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override { unsigned NumBytes = getFixupKindInfo ( Fixup . getKind ( ) ) . TargetSize / <NUM_LIT> ; Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize &&


<s> SDValue Lo , Hi ; DAG . getTargetLoweringInfo ( ) . expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ; return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op


<s> if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getConstant ( ByteRotation , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ByteVT == <STR_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - ByteRotation ; int HiByteShift = ByteRotation ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( HiByteShift , DL , <STR_LIT> ) ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT>

, DL , <STR_LIT> , LoShift , HiShift ) ) ;


<s> std :: pair < unsigned , unsigned > Default = getDefaultFlatWorkGroupSize ( F . getCallingConv ( ) ) ; std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default ) ; if ( Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinFlatWorkGroupSize ( ) ) return Default ; if ( Requested . second > getMaxFlatWorkGroupSize ( ) ) return Default ; return Requested


<s> goto end ; } } else if ( ( count >= <NUM_LIT> && count <= <NUM_LIT> ) || ( TARGET_H8300S && count == <NUM_LIT> ) ) { info -> remainder = count - <NUM_LIT> ; switch ( shift_type ) { case SHIFT_ASHIFT : info -> special = <STR_LIT> ; goto end ; case SHIFT_LSHIFTRT : info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; goto end ; case SHIFT_ASHIFTRT : info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; goto end ; } } else if ( count == <NUM_LIT> ) { switch ( shift_type ) { case SHIFT_ASHIFT : case SHIFT_LSHIFTRT : goto end ; goto end ; case SHIFT_ASHIFTRT : if ( TARGET_H8300H ) { info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; } else gcc_unreachable ( ) ; goto end ; } } else if ( count == <NUM_LIT> ) { switch ( shift_type ) { case SHIFT_ASHIFT : info -> special = <STR_LIT> ; goto end ; case SHIFT_LSHIFTRT : info -> special = <STR_LIT> ; goto end ; case SHIFT_ASHIFTRT : info -> special = <STR_LIT> ; goto end ; } } gcc_unreachable ( ) ; case SIshift : if ( count == <NUM_LIT> ) { switch ( shift_type ) { case SHIFT_ASHIFT : info -> special = <STR_LIT> ; goto end ; case SHIFT_LSHIFTRT : info -> special = <STR_LIT> ; goto end ; case SHIFT_ASHIFTRT : info -> special = <STR_LIT> ; goto end ; } } else if ( count == <NUM_LIT> ) { switch ( shift_type ) { case SHIFT_ASHIFT : info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; goto end ; case SHIFT_LSHIFTRT : info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; goto end ; case SHIFT_ASHIFTRT : info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; goto end ; } } else if ( count >= <NUM_LIT> && count <= <NUM_LIT> ) { info -> remainder = count - <NUM_LIT> ; switch ( shift_type ) { case SHIFT_ASHIFT : info -> special = <STR_LIT> ; goto end ; case SHIFT_LSHIFTRT : info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; goto end ; case SHIFT_ASHIFTRT : info -> special = <STR_LIT> ; info -> cc_special = OLD_CC_SET_ZNV ; goto end ; } } else if ( TARGET_H8300S && count


<s> } else if ( i64vec . getOpcode ( ) == <STR_LIT> ) { SDValue lhs = i64vec . getOperand ( <NUM_LIT> ) ; SDValue rhs = i64vec . getOperand ( <NUM_LIT> ) ; SDValue shufmask = i64vec . getOperand ( <NUM_LIT> ) ; if ( lhs . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( lhs , lhs . getOperand ( <NUM_LIT> ) ) ; lhs = lhs . getOperand ( <NUM_LIT> ) ; } SDNode * lhsNode = ( lhs . getNode ( ) -> isMachineOpcode ( ) ? lhs . getNode ( ) : emitBuildVector ( lhs ) ) ; if ( rhs . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( rhs , rhs . getOperand ( <NUM_LIT> ) ) ; rhs = rhs . getOperand


<s> SU -> isScheduleHigh = ( AffectsGrouping || SU -> isUnbuffered ) ; Available . insert (


<s> bool isLDSDIR ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags &


<s> } if ( ! REG_P ( arg1 ) && ! CONSTANT_P ( arg1 ) ) arg1 = force_reg ( mode , arg1 ) ; switch ( fcode ) { case MSP430_BUILTIN_BIC_SR : emit_insn ( gen_bic_SR ( arg1 ) ) ; break ; case MSP430_BUILTIN_BIS_SR : emit_insn ( gen_bis_SR ( arg1 ) ) ; break ; default : internal_error ( <STR_LIT> ) ; break ; } return NULL_RTX


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT ValVT = VA . getValVT ( ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( IsVarArg ) { auto ArgRegs = IsRV32 ? RV32IntRegs : RV64IntRegs ; unsigned NumRegs = llvm :: <STR_LIT> ; unsigned Idx = CCInfo . getFirstUnallocated ( ArrayRef < MCPhysReg > ( ArgRegs , <NUM_LIT> ) ) ; unsigned RegSize = IsRV32 ? <NUM_LIT> : <NUM_LIT> ; MVT RegTy = <STR_LIT> ( RegSize * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; int VaArgOffset ; if ( NumRegs == Idx ) VaArgOffset = RoundUpToAlignment ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else VaArgOffset = - ( int ) ( RegSize * ( NumRegs - Idx ) ) ; int FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < NumRegs ; ++ I , VaArgOffset += RegSize ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSize ,


<s> ClonedF = cm_it -> second ; return ClonedF ; } CloneAutos ( OrgF ) ; ClonedF = CloneFunction ( OrgF , ValueMap ) ; ClonedF -> setName ( PAN :: getCloneFnName ( OrgF -> getName ( ) ) ) ; ClonedF -> setSection ( <STR_LIT> ) ; OrgF -> getParent ( ) -> getFunctionList ( ) . push_back ( ClonedF ) ; ClonedFunctionMap [ OrgF ] = ClonedF ; return


<s> rtx tmp = * ( const rtx * ) y ; rtx tmp2 = * ( const rtx * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? <NUM_LIT> : - <NUM_LIT> ; return INSN_LUID ( tmp ) - INSN_LUID ( tmp2


<s> auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ; Op -> Reg . Modifiers = - <NUM_LIT> ; Op -> Reg . IsForcedVOP3 = ForceVOP3 ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> bool riscv_epilogue_uses ( unsigned int regno ) { if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case MCOI :: OPERAND_IMMEDIATE : printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate64 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate16 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Op . getImm ( ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set (


<s> static MCStreamer * createMCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useCFI , bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) { MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useCFI , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S


<s> return CurDAG -> getTargetConstant ( Imm ,


<s> bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; if ( MaskedHighBits != Known . Zero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; insertDAGNode ( DAG , N , NewX ) ; X =


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > (


<s> const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; int32_t AdjustedOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , Address + AdjustedOffset , Address , true , <NUM_LIT> , <NUM_LIT> ) ) { Inst . addOperand ( MCOperand :: createImm ( AdjustedOffset ) ) ; } return MCDisassembler ::


<s> int <ISA_LIT>FunctionInfo :: getMoveF64ViaSpillFI ( const TargetRegisterClass * RC ) { if ( MoveF64ViaSpillFI ==


<s> } else if ( RegSpc == SingleHighTSpc ) { D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else if ( RegSpc == EvenDblSpc ) { D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg


<s> static bool xtensa_function_value_regno_p ( const unsigned int regno ) { return ( regno == GP_RETURN


<s> case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerUnalignedLoad ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE (


<s> } else { reg [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; } for ( num_reg = ( mode == DImode ) ? <NUM_LIT> : <NUM_LIT> ; num_reg > <NUM_LIT> ; num_reg -- ) { sub_reg = gen_lowpart ( QImode , reg [ <NUM_LIT> ] ) ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_move_insn ( mem [ <NUM_LIT> ] , sub_reg ) ; while ( width > <NUM_LIT> ) { offset = offset + offset_adj ; shift ++ ; width -- ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_insn ( gen_lshrsi3 ( temp_reg , reg [ <NUM_LIT> ] , GEN_INT ( shift * <NUM_LIT> ) ) ) ; emit_move_insn ( mem [ <NUM_LIT> ] , temp_sub_reg ) ; } if ( mode == DImode ) { reg [ <NUM_LIT> ] = reg [ <NUM_LIT> ] ; shift = <NUM_LIT> ; width = GET_MODE_SIZE ( SImode ) - <NUM_LIT> ; offset = offset +


<s> if ( UseST64 ) { NewOffset0 /= <NUM_LIT> ; NewOffset1 /= <NUM_LIT> ; Opc = ( EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } if ( NewOffset0 > NewOffset1 ) { std :: swap ( NewOffset0 , NewOffset1 ) ; std :: swap ( Data0 , Data1 ) ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Write2Desc = TII -> get ( Opc ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstrBuilder Write2 = BuildMI ( * MBB , Paired , DL , Write2Desc ) . add ( * Addr ) . add ( * Data0 ) . add ( * Data1 ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . addMemOperand ( * I -> memoperands_begin ( ) ) . addMemOperand ( * Paired -> memoperands_begin ( ) ) ; moveInstsAfter ( Write2 , InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( I ) ; I -> eraseFromParent ( ) ; Paired -> eraseFromParent ( )


<s> SDValue StackPtr ; if ( is<ISA_LIT>64 ) StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant ( ArgOffset , PtrVT ) ) ; } MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff ,


<s> unsigned <ISA_LIT>DAGToDAGISel :: getUsesInFunction ( const Value * V ) { if ( GAUsesInFunction . count ( V ) ) return GAUsesInFunction [ V ] ; unsigned Result = <NUM_LIT> ; const Function & CurF = CurDAG -> getMachineFunction ( ) . getFunction ( ) ; for ( const User * U : V -> users ( ) ) { if ( isa < Instruction > ( U ) && cast < Instruction > ( U ) -> getParent ( ) -> getParent ( ) ==


<s> function_builder :: function_builder ( ) { m_direct_overloads = lang_GNU_CXX ( ) ; gcc_obstack_init ( &


<s> bool <ISA_LIT>CFGStructurizer :: needMigrateBlock ( MachineBasicBlock * MBB ) const { unsigned BlockSizeThreshold = <NUM_LIT> ; unsigned CloneInstrThreshold = <NUM_LIT> ; bool MultiplePreds = MBB && ( MBB -> pred_size ( ) > <NUM_LIT> ) ; if ( ! MultiplePreds ) return


<s> static DecodeStatus decodeU12ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodeUImmOperand < <NUM_LIT> >


<s> MVT VecIntVT = V . getSimpleValueType ( ) ; bool Is128 = VecIntVT == <STR_LIT> ; MVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getSimpleValueType ( <NUM_LIT> ) ) return SDValue ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; SDValue VecCstLow = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstHigh = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstShift = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow ) ; High = DAG . getNode ( <STR_LIT> , DL , VecIntVT , HighShift , VecCstHigh ) ; } SDValue VecCstFAdd = DAG . getConstantFP ( APFloat ( APFloat :: IEEEsingle ,

APInt ( <NUM_LIT> , <NUM_LIT> ) ) , DL , VecFloatVT ) ;


<s> void addImm1_32Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast <


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT>


<s> else if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) Align = <NUM_LIT> ; if ( Flags . isByVal ( ) ) { unsigned BVAlign = Flags . getByValAlign ( ) ; if ( BVAlign > PtrByteSize ) { if ( BVAlign % PtrByteSize != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; Align = BVAlign ; } } if ( Flags . isInConsecutiveRegs ( ) ) { if ( Flags . isSplit ( ) && OrigVT != <STR_LIT> ) Align = OrigVT . getStoreSize ( ) ; else Align = ArgVT


<s> BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . first ) . addImm ( int32_t ( V & <NUM_LIT> ) ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addImm ( int32_t (


<s> RegisterRef RegisterAggr :: clearIn (


<s> if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , WidenedMask ) ) ; } } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) SumV2Indices += i ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) NumV1OddIndices += i


<s> return __builtin_mve_vshllbq_n_sv16qi ( __a ,


<s> CallInst * DispatchPtr = Builder . CreateCall ( DispatchPtrFn , { } ) ; DispatchPtr -> addRetAttr ( Attribute :: NoAlias ) ; DispatchPtr -> addRetAttr ( Attribute :: NonNull ) ; F . removeFnAttr ( <STR_LIT> ) ; DispatchPtr -> addDereferenceableRetAttr ( <NUM_LIT> ) ; Type * I32Ty = Type :: getInt32Ty ( Mod -> getContext ( ) ) ; Value * CastDispatchPtr = Builder . CreateBitCast ( DispatchPtr , PointerType :: get ( I32Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ) ; Value * GEPXY = Builder . CreateConstInBoundsGEP1_64 ( I32Ty , CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadXY = Builder . CreateAlignedLoad ( I32Ty , GEPXY , Align ( <NUM_LIT> ) ) ; Value * GEPZU = Builder . CreateConstInBoundsGEP1_64 ( I32Ty , CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadZU = Builder . CreateAlignedLoad ( I32Ty , GEPZU , Align ( <NUM_LIT> ) ) ; MDNode * MD = MDNode :: get ( Mod -> getContext ( ) , None ) ; LoadXY -> setMetadata ( LLVMContext :: MD_invariant_load , MD ) ; LoadZU -> setMetadata ( LLVMContext :: MD_invariant_load , MD ) ; ST . makeLIDRangeMetadata ( LoadZU ) ; Value * Y = Builder . CreateLShr ( LoadXY , <NUM_LIT> ) ; return std :: make_pair ( Y ,


<s> FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> || Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return


<s> const MachineOperand * <ISA_LIT>InstrInfo :: getNamedOperand ( const MachineInstr & MI , unsigned OperandName ) const { int Idx = AMDGPU :: getNamedOperandIdx ( MI . getOpcode ( ) , OperandName ) ; if ( Idx == - <NUM_LIT> ) return nullptr ; return & MI . getOperand (


<s> static bool allocateFloat ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { switch ( LocVT . SimpleTy ) { case <STR_LIT> : { State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; unsigned Offset = State . AllocateStack ( <NUM_LIT>


<s> llvm :: errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForReturn ( CallConv ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i < RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MFI . hasCalls ( ) || MFI . hasVarSizedObjects

( ) || TRI -> needsStackRealignment ( MF ) ;


<s> checkForInvalidNodes ( MF . getFunction ( ) ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction (


<s> if ( Bytes != <NUM_LIT> ) { unsigned SubRegImms [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned SubRegImm = SubRegImms [ Log2_32 ( Bytes ) ] ; Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC ) ; unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [ Log2_32 ( Bytes )


<s> __builtin_neon_vst3v4hi ( ( __builtin_neon_hi * ) __a ,


<s> case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP5 : insn -> opcodeType = MAP5 ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP6 : insn -> opcodeType = MAP6 ; return consume ( insn , insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) ; return true ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP5 : insn -> opcodeType = MAP5 ; return consume ( insn , insn -> opcode ) ; case VEX_LOB_MAP6 : insn -> opcodeType = MAP6 ; return consume ( insn , insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consume ( insn , insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) ; return true ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consume ( insn , insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType =


<s> InstructionSelector * create<ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & Subtarget , const RegisterBankInfo & RBI ) { return new <ISA_LIT>InstructionSelector ( TM , Subtarget , RBI


<s> if ( bitmap_empty_p ( bitdata ) ) return false ; int ratio = - <NUM_LIT> ; unsigned int bb_index ; sbitmap_iterator sbi ; EXECUTE_IF_SET_IN_BITMAP ( bitdata , <NUM_LIT> , bb_index , sbi ) { if ( ratio == - <NUM_LIT> ) ratio = vector_exprs [ bb_index ] -> get_ratio


<s> void addu16ImmOperands ( MCInst & Inst , unsigned N


<s> } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ; return false


<s> CCInfo . AnalyzeReturn ( Outs , ( Subtarget . isSVR4ABI ( ) && CallConv == CallingConv :: Cold ) ? RetCC_<ISA_LIT>_Cold : RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister (


<s> assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy =


<s> else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_LOX10 ) && <STR_LIT> ) ; else assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LO10 ) && <STR_LIT> ) ; } bool CloseParen = <ISA_LIT>MCExpr :: printVariantKind ( O , TF ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( )


<s> void <ISA_LIT>InstPrinterCommon :: printInstFlags ( const MCInst * MI , raw_ostream & O ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) O << <STR_LIT> ; if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> ) O << <STR_LIT> ; if ( ( Flags & <STR_LIT> ) || ( TSFlags & <STR_LIT> ) ) O << <STR_LIT> ; else if ( Flags & <STR_LIT> ) O << <STR_LIT> ; else if ( Flags &


<s> GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; HasDotLocAndDotFile = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: None ; UsesELFSectionDirectiveForBSS =


<s> if ( ! TLO . LegalOps ) return false ; EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return false ; if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; const APInt & Mask = C -> getAPIntValue ( ) ; APInt ShrunkMask = Mask & DemandedBits ; APInt ExpandedMask = Mask | ~ DemandedBits ; auto IsLegalMask = [ ShrunkMask , ExpandedMask ] ( const APInt & Mask ) -> bool { return ShrunkMask . isSubsetOf ( Mask ) && Mask . isSubsetOf ( ExpandedMask ) ; } ; auto UseMask = [ Mask , Op , VT , & TLO ] ( const APInt & NewMask ) -> bool { if ( NewMask == Mask ) return true ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( NewMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand (


<s> int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: ParseIntelOffsetOfOperator ( SMLoc Start ) { SMLoc OffsetOfLoc = Start ; Parser . Lex ( ) ; Start = Parser . getTok ( ) . getLoc ( ) ; assert ( Parser . getTok ( ) . is ( AsmToken ::


<s> auto * MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! needsSP ( MF , * MFI ) || ! needsSPWriteback ( MF , * MFI ) ) return ; auto * WFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) { DL = InsertPt -> getDebugLoc ( ) ; } if ( StackSize ) { unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( StackSize ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) .

addReg ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) . addReg ( OffsetReg ) ;


<s> rtx m , a ; if ( ! rl78_virt_insns_ok ( ) ) return false ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; fprintf ( stderr , <STR_LIT> ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( operands [ <NUM_LIT> ] ) != REG ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( GET_CODE ( operands [ i ] ) != GET_CODE ( operands [ i + <NUM_LIT> ] ) ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } if ( GET_MODE ( operands [ i ] ) != GET_MODE ( operands [ i + <NUM_LIT> ] ) ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } switch ( GET_CODE ( operands [ i ] ) ) { case REG : if ( REGNO ( operands [ i ] ) + <NUM_LIT> != REGNO ( operands [ i + <NUM_LIT> ] ) || GET_MODE ( operands [ i ] ) != QImode ) { fprintf ( stderr , <STR_LIT> , REGNO ( operands [ i ] ) , REGNO ( operands [ i + <NUM_LIT> ] ) , i ) ; return false ; } if ( ! rl78_hard_regno_mode_ok ( REGNO ( operands [ i ] ) , HImode ) ) { fprintf ( stderr , <STR_LIT> , REGNO ( operands [ i ] ) ) ; return false ; } break ; case CONST_INT : break ; case MEM : if ( GET_MODE ( operands [ i ] ) != QImode ) return false ; if ( MEM_ALIGN ( operands [ i ] ) < <NUM_LIT> ) return false ; a = XEXP ( operands [ i ] , <NUM_LIT> ) ; if ( GET_CODE ( a ) == CONST ) a = XEXP ( a , <NUM_LIT> ) ; if ( GET_CODE ( a ) == PLUS )


<s> return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; break ; case CONST_WIDE_INT


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Node -> getOpcode ( ) ) { default : break ; ( void ) VT ; } SelectCode ( Node )


<s> SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG .

getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( AMDGPU :: isMIMG ( MI -> getOpcode ( ) ) == - <NUM_LIT> ) return ; unsigned VReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned BitsSet = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) BitsSet += Writemask & ( <NUM_LIT> << i ) ? <NUM_LIT> : <NUM_LIT> ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case <NUM_LIT> : RC = & AMDGPU :: VReg_32RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_64RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU


<s> SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ; break ; } case TLSModel :: InitialExec : { Offset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; break ; } case TLSModel :: LocalExec : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; break ; } } return DAG . getNode ( <STR_LIT> , DL , PtrVT ,


<s> void addImm1_32Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> SmallPtrSet < const User * , <NUM_LIT> > Visited ; SmallVector < const User * , <NUM_LIT> > Stack ( GV . users ( ) ) ; SmallPtrSet < const GlobalValue * , <NUM_LIT> > GlobalUsers ; assert ( ! F || isKernelCC ( F ) ) ; while ( ! Stack . empty ( ) ) { const User * V = Stack . pop_back_val ( ) ; Visited . insert ( V ) ; if ( auto * G = dyn_cast < GlobalValue > ( V ) ) { StringRef GName = G -> getName ( ) ; if ( F && GName != <STR_LIT> && GName != <STR_LIT> ) { return false


<s> SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GAHi , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = IsN64 ? ( HasGotOfst


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPic0 ( ) { MCAssembler & MCA = getStreamer ( ) .


<s> uint16_t HI16 = static_cast < uint16_t > ( Bin >> <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) <STR_LIT> :: write < uint16_t > ( OS , HI16 , <STR_LIT> ) ; <STR_LIT> :: write < uint16_t > ( OS , LO16 , <STR_LIT> ) ; ++


<s> int <ISA_LIT>TTIImpl :: getMaskedMemoryOpCost ( unsigned Opcode , Type * SrcTy , unsigned Alignment , unsigned AddressSpace ) { bool IsLoad = ( Instruction :: Load == Opcode ) ; bool IsStore = ( Instruction :: Store == Opcode ) ; VectorType * SrcVTy = dyn_cast < VectorType > ( SrcTy ) ; if ( ! SrcVTy ) return getMemoryOpCost ( Opcode , SrcTy , MaybeAlign ( Alignment ) , AddressSpace ) ; unsigned NumElem = SrcVTy -> getVectorNumElements ( ) ; VectorType * MaskTy = VectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements ( )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS4 ( SDValue Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base ,


<s> <ISA_LIT>Z80SectionData ( StringRef N , <ISA_LIT>SectionType T = ST_NONE , uint16_t A = <NUM_LIT> , unsigned B = ~ <NUM_LIT> , unsigned Align = <NUM_LIT> , const GlobalObject * O


<s> break ; } } } } if ( ! YmmOrZmmUsed ) { return false ; } assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) processBasicBlock ( MBB ) ; if ( FnHasLiveInYmmOrZmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock * Succ : MBB . successors ( ) ) addDirtySuccessor ( * Succ ) ; } } BlockStates . clear ( ) ; return EverMadeChange


<s> switch ( Opcode ) { default : break ; case <STR_LIT> : return true ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return __builtin_ia32_vcvtudq2ph512_mask_round ( ( __v16si ) __A , _mm256_setzero_ph ( )


<s> static bool allocateFloat ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { switch ( LocVT . SimpleTy ) { case <STR_LIT> :


<s> } break ; case Instruction :: Mul : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Or : case Instruction :: Xor : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; } break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( BitSize <= <NUM_LIT> ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( ~ Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; const <ISA_LIT>InstrInfo * TII = ST -> getInstrInfo ( ) ; unsigned Start , End ; if ( TII -> isRxSBGMask ( Imm . getZExtValue ( ) , BitSize , Start , End ) )


<s> unsigned addr = <NUM_LIT> ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> unsigned <ISA_LIT>MCCodeEmitter :: getAddressWithFixup ( const MCOperand & MO , unsigned FixupKind , SmallVectorImpl < MCFixup > & Fixups ) const { if ( ! MO . isExpr ( ) ) { assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm (


<s> static DecodeStatus decodeRrMemoryValue ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Register = ( Insn >> <NUM_LIT>


<s> SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( VT . getScalarType ( ) == <STR_LIT> ) { assert ( VT . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops , VT . getVectorNumElements ( ) ) ; } else llvm_unreachable ( <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( <NUM_LIT> ) , Attr ) ) return SDValue ( N , <NUM_LIT> ) ; assert ( ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) && <STR_LIT> ) ; if ( ! Subtarget . hasStdExtZbt ( ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> || Lg2 >= <NUM_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && ! ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , VT , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode


<s> unsigned Block = MI -> getParent ( ) -> getNumber ( ) ; const BasicBlockInfo & BBI = BBInfo [ Block ] ; dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ; } )


<s> void insertRecoveryBlock ( MachineFunction & MF ) { DebugLoc DL3 = MF . begin ( ) -> begin ( ) -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( auto & reg : functionCallArgs ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( reg ) ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( getSlaveReg1 ( reg ) ) ; tzdcRecoveryMBB -> insert ( tzdcRecoveryMBB -> end ( ) , cmpInst ) ; tzdcRecoveryMBB -> insert ( tzdcRecoveryMBB -> end ( )


<s> } bool DoXform = false ; bool InvCC = false ; assert ( ( Opc == <STR_LIT> || ( Opc == <STR_LIT> && Slct == N -> getOperand ( <NUM_LIT> ) ) ) && <STR_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( LHS ) -> isNullValue ( ) ) { DoXform = true ; } else if ( CC != <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( RHS ) -> isNullValue ( ) ) { std :: swap ( LHS , RHS ) ; SDValue Op0 = Slct . getOperand ( <NUM_LIT> ) ; EVT OpVT = isSlctCC ? Op0 . getValueType ( ) : Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; bool isInt = OpVT . isInteger ( ) ; CC = <STR_LIT> ( CC , isInt ) ; if ( ! TLI . isCondCodeLegal ( CC , OpVT ) ) return SDValue ( ) ; DoXform = true ; InvCC = true ; } if ( DoXform )


<s> static bool isCondBranchOpcode ( int op ) { return ( op == <STR_LIT> ) || ( op == <STR_LIT> ) || ( op == <STR_LIT> ) || ( op == <STR_LIT> ) || ( op == <STR_LIT> )


<s> return ( __m256d ) __builtin_ia32_andnpd256 ( ( __v4df


<s> std :: bitset < <NUM_LIT> > Bits ( GetImplicitBits ( MCI ) ) ; return Bits . test


<s> if ( ! VI . isLiveIn ( * Endif , MOReg , * MRI ) ) { KillsInElse . insert ( MOReg ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOReg , TRI ) << <STR_LIT> ) ; } } } } } } for ( auto & MI : Endif -> phis ( ) ) { for ( unsigned Idx = <NUM_LIT> ; Idx < MI . getNumOperands ( ) ; Idx += <NUM_LIT> ) { auto & MO = MI . getOperand ( Idx ) ; auto * Pred = MI . getOperand ( Idx + <NUM_LIT> ) . getMBB ( ) ; if ( Pred == Flow ) continue ; assert ( ElseBlocks . contains ( Pred ) && <STR_LIT> ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) || MO . isUndef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg . isPhysical ( ) || ! TRI -> isVectorRegister ( * MRI , Reg ) ) continue ; LiveVariables :: VarInfo & VI = LV -> getVarInfo ( Reg ) ; if ( VI . isLiveIn ( * Endif , Reg , * MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; continue ; } const MachineBasicBlock * DefMBB = MRI -> getVRegDef ( Reg ) -> getParent ( ) ; if ( ( VI . AliveBlocks . test ( If -> getNumber ( ) ) || DefMBB == If ) && Loops -> getLoopFor ( DefMBB ) == Loops -> getLoopFor ( If ) ) KillsInElse . insert ( Reg ) ; } } auto IsLiveThroughThen = [ & ] ( Register Reg ) { for ( auto I = MRI -> use_nodbg_begin ( Reg ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { if ( ! I -> readsReg ( ) ) continue ; auto * UseMI = I -> getParent ( ) ; auto * UseMBB = UseMI -> getParent ( ) ; if ( UseMBB == Flow || UseMBB == Endif ) { if ( ! UseMI -> isPHI ( ) ) return true ; auto * IncomingMBB = UseMI -> getOperand ( I . getOperandNo ( )


<s> case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > StackSlotSize ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , LRSaveSize + VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( isVarArg ) { static const uint16_t ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs , array_lengthof ( ArgRegs ) ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { SmallVector < SDValue , <NUM_LIT> > MemOps ; int offset = <NUM_LIT> ; for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back


<s> DebugLoc dl = Ld -> getDebugLoc ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; if ( RegVT . isVector ( ) && Ext == <STR_LIT> && Subtarget -> hasSSE41 ( ) ) { assert ( MemVT != RegVT && <STR_LIT> ) ; assert ( MemVT . isVector ( ) && <STR_LIT> ) ; unsigned NumElems = RegVT . getVectorNumElements ( ) ; unsigned RegSz = RegVT . getSizeInBits ( ) ; unsigned MemSz = MemVT . getSizeInBits ( ) ; assert ( RegSz > MemSz && <STR_LIT> ) ; if ( ! isPowerOf2_32 ( RegSz * MemSz * NumElems ) ) return SDValue ( ) ; MVT SclrLoadTy = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) == MemSz ) { SclrLoadTy = Tp ; break ; } } if ( SclrLoadTy . getSizeInBits ( ) != MemSz ) return SDValue ( ) ; EVT LoadUnitVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SclrLoadTy , RegSz / SclrLoadTy . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , RegSz / MemVT . getScalarType ( ) . getSizeInBits ( ) ) ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; SDValue ScalarInVector = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , ScalarLoad ) ; SDValue SlicedVec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , ScalarInVector ) ; unsigned SizeRatio = RegSz /


<s> if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = MI . getOperand ( <NUM_LIT> ) ; Src = MI .


<s> static int const_costs_int ( HOST_WIDE_INT value , int zero_cost ) { if ( CONST_OK_FOR_I ( value ) ) return zero_cost ; else if ( CONST_OK_FOR_J ( value ) ) return <NUM_LIT> ; else if ( CONST_OK_FOR_K ( value


<s> return false ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , <NUM_LIT> ) ) { if ( MO . isImplicit ( ) || ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg < <STR_LIT> || Reg > <STR_LIT> ) { if ( ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) && ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) ) { ErrInfo = <STR_LIT> ; return false ; } } } } if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } <STR_LIT> AddrMode = ( <STR_LIT> ) ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Imm = <NUM_LIT> ; for ( auto Op : MI . operands ( ) ) { if ( Op . isImm ( ) ) { Imm = Op .


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>Disassembler


<s> return NULL ; } return CurDAG -> getMachineNode ( Opcode , N -> getDebugLoc ( ) , VT , <STR_LIT> , <STR_LIT> , LD -> getBasePtr


<s> } SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; GetSignature ( Subtarget , Name , Returns , Params ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setType ( <STR_LIT> ) ; return WasmSym


<s> ( const TargetRegisterClass * ) & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; int index = ArgLocs [ i ] . getValNo ( ) ; if ( index != lastInsIndex ) { <STR_LIT> Flags = Ins [ index ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned CurByValIndex = CCInfo . getInRegsParamsProcessed ( ) ; ByValStoreOffset = RoundUpToAlignment ( ByValStoreOffset , Flags . getByValAlign ( ) ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , CurOrigArg , CurByValIndex , Ins [ VA . getValNo ( ) ] . PartOffset , VA . getLocMemOffset ( ) , Flags . getByValSize ( ) , true , ByValStoreOffset , TotalArgRegsSaveSize ) ; ByValStoreOffset += Flags . getByValSize ( ) ; ByValStoreOffset = std :: min ( ByValStoreOffset , <NUM_LIT> ) ; InVals . push_back ( DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ) ; CCInfo . nextInRegsParam ( ) ; } else { unsigned FIOffset = VA . getLocMemOffset ( ) ; int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , FIOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } lastInsIndex = index ; } } } if ( isVarArg ) VarArgStyleRegisters ( CCInfo , DAG , dl , Chain , CCInfo . getNextStackOffset ( ) , TotalArgRegsSaveSize ) ; AFI -> setArgumentStackSize ( CCInfo . getNextStackOffset


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( C -> isNullValue ( ) && CC == <STR_LIT> ) { EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Zext = Op . getOperand ( <NUM_LIT> ) ; if ( VT . bitsLT ( <STR_LIT> ) ) { VT = <STR_LIT> ; Zext = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned Log2b = Log2_32 ( VT . getSizeInBits ( ) ) ; SDValue Clz = DAG . getNode ( <STR_LIT> , dl , VT , Zext ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , VT , Clz , DAG . getConstant ( Log2b , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scc ) ; } if ( C -> isAllOnesValue ( ) || C -> isNullValue (


<s> return Subtarget . isMClass ( ) && MF . getFunction


<s> const unsigned FP = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> ) . addReg ( FP ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg , RegState :: Define ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg2 , RegState :: Define ) . addReg ( LabelReg , RegState :: Kill ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( RegSize ) . addReg ( LabelReg2 , RegState :: Kill ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <ISA_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) . addImm ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) . addImm ( <STR_LIT> ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( restoreMBB


<s> switch ( VT . SimpleTy ) { case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { if ( UnsupportedFPMode ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } case <STR_LIT> : { if ( UnsupportedFPMode ) return false ; ResultReg = createResultReg ( & <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } default : return false ; } if ( Addr . isRegBase ( ) ) { simplifyAddress ( Addr ) ; emitInstLoad ( Opc , ResultReg , Addr . getReg ( ) , Addr . getOffset ( ) ) ; return true ; } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr . getFI ( ) ; unsigned Align = <NUM_LIT> ; unsigned Offset = Addr . getOffset ( ) ; MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg )

. addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> Ops . push_back ( CurDAG . getTargetConstant ( RegClassID , DL , <STR_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < Regs . size ( ) ; ++ I ) { Ops . push_back ( Regs [ I ] ) ; Ops . push_back ( CurDAG . getTargetConstant ( SubReg0 + I , DL , <STR_LIT> ) ) ; } SDNode * N = CurDAG . getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , <STR_LIT> , Ops ) ; return SDValue ( N , <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> bool R600InstrInfo :: isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return


<s> if ( GPRSaveSize != <NUM_LIT> ) { if ( IsWin64 ) { GPRIdx = MFI . CreateFixedObject ( GPRSaveSize , - ( int ) GPRSaveSize , false ) ; if ( GPRSaveSize & <NUM_LIT> ) MFI . CreateFixedObject ( <NUM_LIT> - ( GPRSaveSize & <NUM_LIT> ) , - ( int ) alignTo ( GPRSaveSize , <NUM_LIT> ) , false ) ; } else GPRIdx = MFI . CreateStackObject ( GPRSaveSize , Align ( <NUM_LIT> ) , false ) ; SDValue FIN = DAG . getFrameIndex ( GPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicGPR ; i < NumGPRArgRegs ; ++ i ) { Register VReg = MF . addLiveIn ( GPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , IsWin64 ? MachinePointerInfo :: getFixedStack ( MF , GPRIdx , ( i - FirstVariadicGPR ) * <NUM_LIT> ) : MachinePointerInfo :: getStack ( MF , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsWin64 ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI . CreateStackObject ( FPRSaveSize , Align ( <NUM_LIT> ) , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , PtrVT ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { Register VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( MF , i * <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; } } FuncInfo -> setVarArgsFPRIndex ( FPRIdx ) ; FuncInfo -> setVarArgsFPRSize ( FPRSaveSize ) ; } if ( ! MemOps . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT>


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL


<s> if ( ( format == <NUM_LIT> && write_symbols != DWARF2_DEBUG ) || format == <NUM_LIT> ) return regno ; if ( regno <= <NUM_LIT> ) return regno ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( format == <NUM_LIT> && regno == CR2_REGNO ) return


<s> } for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * child_fma ; rtx fma_rtx , * accum_rtx_p ; if ( ! is_fmul_fmac_insn ( chain -> insn , false ) ) continue ; fma_rtx = SET_SRC ( PATTERN ( chain -> insn ) ) ; if ( GET_CODE ( fma_rtx ) == NEG ) fma_rtx = XEXP ( fma_rtx , <NUM_LIT> ) ; accum_rtx_p = & XEXP ( fma_rtx , <NUM_LIT> ) ; if ( ! REG_P ( * accum_rtx_p ) ) accum_rtx_p = & XEXP ( * accum_rtx_p , <NUM_LIT> ) ; if ( accum_rtx_p != chain -> loc


<s> if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . hasOneUse ( ) && IsLegalToFold ( N1 , Op , Op , OptLevel ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N1 ) ; if ( ! isValidIndexedLoad ( LD ) ) return false ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opc = ( VT == <STR_LIT> ? Opc16 : Opc8 ) ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr ( ) , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( Op , Opc , VT , <STR_LIT> , <STR_LIT> , Ops0 ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue (


<s> if ( STI . is64Bit ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( CatchRetTarget ) . addReg ( <NUM_LIT> ) ; }


<s> mask = force_reg ( V4HImode , mask ) ; t0 = gen_reg_rtx ( V4HImode ) ; t1 = gen_reg_rtx ( V4HImode ) ; ok = expand_vselect ( t0 , d -> op0 , perm2 , <NUM_LIT> ) ; gcc_assert ( ok ) ; ok = expand_vselect ( t1 , d -> op1 , perm2 , <NUM_LIT> ) ; gcc_assert ( ok ) ; x = gen_rtx_AND ( V4HImode , mask , t0 ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( V4HImode , mask


<s> RHS = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( - <NUM_LIT> , dl , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , dl , AN -> getMemoryVT ( ) , Op . getOperand ( <NUM_LIT> )

, Op . getOperand ( <NUM_LIT> ) , RHS , AN -> getMemOperand ( ) ) ;


<s> uint64_t RsrcDataFormat = <STR_LIT> ; if ( ST . isAmdHsaOS ( ) ) { RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; } return RsrcDataFormat


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT>


<s> if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) Attrs . mWorkGroupSizeHint = getWorkGroupDimensions ( Node ) ; if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) { Attrs . mVecTypeHint = getTypeName ( cast < ValueAsMetadata > ( Node -> getOperand ( <NUM_LIT> ) ) -> getType ( ) , mdconst

:: extract < ConstantInt > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ;


<s> return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> )


<s> TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) { CreatedX2 =


<s> for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) { if ( A == MBB ) return false ; } MachineInstr * Def = MRI -> getVRegDef ( MO -> getReg ( ) ) ; LoopFeederPhi . insert ( std :: make_pair ( MO -> getReg ( ) , Def ) ) ; return true ; } else return false


<s> } ScheduleDAGMILive :: schedule ( ) ; Regions [ RegionIdx ] = std :: make_pair ( RegionBegin , RegionEnd ) ; if ( ! LIS ) return ; GCNMaxOccupancySchedStrategy & S = ( GCNMaxOccupancySchedStrategy & ) * SchedImpl ; auto PressureAfter = getRealRegPressure ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; PressureAfter . print ( dbgs ( ) ) ) ; if ( PressureAfter . getSGPRNum ( ) <= S . SGPRCriticalLimit && PressureAfter . getVGPRNum ( ) <= S . VGPRCriticalLimit ) { Pressure [ RegionIdx ] = PressureAfter ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } unsigned WavesAfter = getMaxWaves ( PressureAfter . getSGPRNum ( ) , PressureAfter . getVGPRNum ( ) , MF ) ; unsigned WavesBefore = getMaxWaves ( PressureBefore . getSGPRNum ( ) , PressureBefore . getVGPRNum ( ) , MF ) ; WavesAfter = std :: min ( WavesAfter , MFI . getMaxWavesPerEU ( ) ) ; WavesBefore = std :: min ( WavesBefore , MFI . getMaxWavesPerEU ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << WavesBefore << <STR_LIT> << WavesAfter << <STR_LIT> ) ; unsigned NewOccupancy = std :: max ( WavesAfter , WavesBefore ) ; if ( NewOccupancy < MinOccupancy ) { MinOccupancy = NewOccupancy ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MinOccupancy << <STR_LIT> ) ; } if ( WavesAfter >= WavesBefore ) { Pressure [ RegionIdx ] = PressureAfter ; return ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; RegionEnd = RegionBegin ; for ( MachineInstr * MI : Unsched ) { if ( MI -> isDebugInstr ( ) ) continue ; if ( MI -> getIterator ( ) != RegionEnd ) { BB -> remove ( MI ) ; BB -> insert ( RegionEnd , MI ) ; if ( ! MI -> isDebugInstr ( ) ) LIS -> handleMove ( * MI , true ) ; } for ( auto & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isDef ( ) ) Op . setIsUndef ( false ) ; RegisterOperands RegOpers ; RegOpers . collect ( * MI , * TRI , MRI , ShouldTrackLaneMasks , false ) ; if ( ! MI -> isDebugInstr ( ) ) { if ( ShouldTrackLaneMasks ) { SlotIndex SlotIdx = LIS -> getInstructionIndex ( * MI ) . getRegSlot ( ) ; RegOpers . adjustLaneLiveness ( * LIS , MRI , SlotIdx , MI ) ; } else { RegOpers . detectDeadDefs ( * MI ,


<s> SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ResultLo = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0Lo , Op1Lo ) ; SDValue ResultHi = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0Hi , Op1Hi ) ; return DAG . getNode ( <STR_LIT> , dl


<s> if ( mSTM -> device ( ) -> getGeneration ( ) == <STR_LIT> && ( mSTM -> getDeviceName ( ) == <STR_LIT> ) ) { return false ; } return CI -> getOperand ( CI -> getNumOperands ( ) - <NUM_LIT> ) -> getName

( ) . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ;


<s> CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ca -> force_mem ) ca -> force_mem = <NUM_LIT> ; else ca ->


<s> cumulative_args_t cum ; HARD_REG_SET call_saved_regset ; tree parameter ; machine_mode mode ; tree type ; rtx parm_rtx ; int i ; INIT_CUMULATIVE_ARGS ( cum_v , NULL , NULL , <NUM_LIT> , <NUM_LIT> ) ; cum = pack_cumulative_args ( & cum_v ) ; COMPL_HARD_REG_SET ( call_saved_regset , call_used_reg_set ) ; for ( i = <NUM_LIT> ; i < call_expr_nargs ( call_expr ) ; i ++ ) { parameter = CALL_EXPR_ARG ( call_expr , i ) ; gcc_assert ( parameter ) ; if ( TREE_CODE ( parameter ) == ERROR_MARK ) return true ; type = TREE_TYPE ( parameter ) ; gcc_assert ( type ) ; mode = TYPE_MODE ( type ) ; gcc_assert ( mode ) ; if ( pass_by_reference ( & cum_v , mode , type , true )


<s> return MI . isFullCopy ( ) && MI . getOperand ( <NUM_LIT> ) .


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > (


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } int BccOpc = Cond [ <NUM_LIT> ] . isImm ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( & MBB , dl


<s> I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC )


<s> if ( ! Formatter . get ( ) ) Formatter = std :: make_unique < <ISA_LIT>MIRFormatter > ( ) ; return Formatter . get


<s> bool <ISA_LIT>Subtarget :: allowBranchInsideCFLDelaySots ( ) const { return


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) { if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) PM -> add ( createThumb2SizeReductionPass ( ) ) ; addPass ( UnpackMachineBundlesID )


<s> char buf [ <NUM_LIT> ] ; snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_align ( POINTER_SIZE )


<s> return ( __m64 ) __builtin_ia32_psradi ( (