<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const SDValue & V : PN -> ops ( ) ) { if ( ! ToPromote . count ( V . getNode ( ) ) && V . getValueType ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V ) ) { SDValue ReplOpOps [ ] = { ISR . getOperand ( <NUM_LIT> ) , V , ISR . getOperand ( <NUM_LIT> ) } ; SDNode * ReplOp = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , SDLoc ( V ) , ISR . getNode ( ) -> getVTList ( ) , ReplOpOps ) ; Ops . push_back ( SDValue ( ReplOp , <NUM_LIT> ) ) ; } else { Ops . push_back ( V ) ; } } SmallVector < EVT , <NUM_LIT> > NewVTs ; SDVTList VTs = PN -> getVTList ( ) ; for ( unsigned i = <NUM_LIT> , ie = VTs . NumVTs ; i != ie ; ++ i ) if ( VTs . VTs [ i ] == <STR_LIT> ) NewVTs . push_back ( <STR_LIT> ) ; else NewVTs . push_back ( VTs . VTs [ i ] ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; CurDAG -> SelectNodeTo ( PN , NewOpcode , CurDAG -> getVTList ( NewVTs ) , Ops ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops , array_lengthof ( Ops ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return Op


<s> Inst . addOperand ( MCOperand :: CreateReg ( VRegs [ getReg


<s> if ( Info . MI1 != nullptr ) { DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToSTR ; } break ; case MCLOH_AdrpLdrGotLdr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToLDR ; break ; case MCLOH_AdrpLdrGotStr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info .


<s> void CompositeHandler :: visitAlloca ( AllocaInst


<s> static SDValue lowerVectorShuffleWithPACK ( const SDLoc & DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG , const


<s> bool ContainsWWM = false ; for ( auto WWM : WWMs ) { if ( Loop -> contains ( WWM -> getParent ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * WWM ) ; ContainsWWM = true ; break ; } } if ( ! ContainsWWM ) return false ; unsigned Reg = DefOpnd -> getReg ( ) ; for ( auto & Use : MRI -> use_operands ( Reg ) ) Use . setIsKill ( false ) ; SmallVector < MachineInstr * , <NUM_LIT> > Defs ; for ( auto & Def : MRI -> def_instructions ( Reg ) ) Defs . push_back ( & Def ) ; for ( auto Def : Defs ) { if ( DefOpnd -> getParent ( ) == Def ) continue ; Def -> addOperand ( MachineOperand :: CreateReg (


<s> const unsigned STATE_START = <NUM_LIT> ; assert ( HasLookup ( Instr ) && <STR_LIT> ) ; MachineBasicBlock :: reverse_iterator CurrentMII ( Instr ) ; ++ CurrentMII ; MachineBasicBlock * CurrentBB = Instr . getParent ( ) ; unsigned State = STATE_START ; for ( ; ; ) { if ( CurrentMII == CurrentBB -> rend ( ) ) { bool HasPrevious = false ; for ( MachineBasicBlock * Pred : CurrentBB -> predecessors ( ) ) { if ( Pred && Pred -> isLayoutSuccessor ( CurrentBB ) ) { CurrentBB = Pred ; CurrentMII = Pred -> rbegin ( ) ; HasPrevious = true ; break ; } } if ( ! HasPrevious ) break ; if ( CurrentBB -> empty ( ) ) break ; } MachineInstr & CurrentMI = * CurrentMII ; if ( ! CurrentMI . isBundle ( ) && ! isNopInstr ( & CurrentMI ) ) break ; bool HasST_L_V = false ; bool HasLD_L_V = false ; MachineBasicBlock :: const_instr_iterator BMII = CurrentMI . getIterator ( ) ; for ( ++ BMII ; BMII != CurrentBB -> instr_end ( ) && BMII -> isInsideBundle ( ) ; ++ BMII ) { const MachineInstr & BMI = * BMII ; const MCInstrDesc & BMID = BMI .


<s> if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < <NUM_LIT> > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > <NUM_LIT> && ( Offset / NumBytes ) <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == <NUM_LIT> || ( AM . Scale > <NUM_LIT> &&


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ||


<s> static MachineBasicBlock :: iterator findHBRPosition ( MachineBasicBlock & MBB ) { MachineBasicBlock :: iterator J = MBB . end (


<s> std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) { RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; } else { return RegNum ; } return


<s> static const char * aarch64_get_multilib_abi_name


<s> void function_expander :: add_integer_operand ( HOST_WIDE_INT x ) { m_ops . safe_grow ( m_ops . length ( )


<s> static const MachineOperand & getLoadStoreBaseOp ( const MachineInstr & MI


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm (


<s> } DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << <STR_LIT> << VecLen << <STR_LIT> << HwLen << <STR_LIT> << UseLeft << <STR_LIT> << UseRight << <STR_LIT> << HavePairs << '\n' ; } ) ; if ( ! UseLeft && ! UseRight ) { ISel . ReplaceNode ( N , ISel . selectUndef ( SDLoc ( SN ) , ResTy ) . getNode ( ) ) ; return ; } SDValue Vec0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Vec1 = N -> getOperand ( <NUM_LIT> ) ; ResultStack Results ( SN ) ; Results . push ( TargetOpcode :: COPY , ResTy , { Vec0 } ) ; Results . push ( TargetOpcode :: COPY , ResTy , { Vec1 } ) ; OpRef Va = OpRef :: res ( Results . top ( ) - <NUM_LIT> ) ; OpRef Vb = OpRef :: res ( Results . top ( ) ) ; OpRef Res = ! HavePairs ? shuffs2 ( ShuffleMask ( Mask ) , Va , Vb , Results ) : shuffp2 ( ShuffleMask ( Mask ) , Va , Vb , Results ) ; bool Done = Res .


<s> if ( size == <NUM_LIT> ) { if ( mode == VOIDmode ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } for ( available = regs_available_for_popping , required = regs_to_pop ; required != <NUM_LIT> && available != <NUM_LIT> ; available &= ~ ( available & - available ) , required &= ~ ( required & - required ) ) -- pops_needed ; if ( available > <NUM_LIT> ) regs_available_for_popping &= ~ available ; else if ( pops_needed ) { if ( regs_available_for_popping == <NUM_LIT> && reg_containing_return_addr == LAST_ARG_REGNUM ) { asm_fprintf ( f , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; reg_containing_return_addr = LR_REGNUM ; } else if ( size > <NUM_LIT> ) { restore_a4 = TRUE ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } if ( reg_containing_return_addr != LAST_ARG_REGNUM ) { regs_available_for_popping |= <NUM_LIT> << LAST_ARG_REGNUM ; -- pops_needed ; } } thumb_pop ( f , regs_available_for_popping ) ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop &= ~ ( <NUM_LIT> << LR_REGNUM ) ; reg_containing_return_addr = number_of_first_bit_set ( regs_available_for_popping ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << reg_containing_return_addr ) ; } if ( regs_available_for_popping ) { int frame_pointer ; frame_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , ARM_HARD_FRAME_POINTER_REGNUM , frame_pointer ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << frame_pointer ) ; regs_to_pop &= ~ ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) ; if ( regs_available_for_popping ) { int


<s> static DecodeStatus DecodeSBCInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned const4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( is32Bit ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand ::


<s> bool CopyPropagation :: propagateRegCopy ( MachineInstr & MI ) { bool Changed = false ; unsigned Opc = MI . getOpcode ( ) ; BitTracker :: RegisterRef RD = MI . getOperand ( <NUM_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) ; switch ( Opc ) { case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : { BitTracker :: RegisterRef RS = MI . getOperand ( <NUM_LIT> ) ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) break ; if ( RS . Sub != <NUM_LIT> ) Changed = HBS :: replaceRegWithSub ( RD . Reg , RS . Reg , RS . Sub , MRI ) ; else Changed = HBS :: replaceReg ( RD . Reg , RS . Reg , MRI ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { BitTracker :: RegisterRef SL , SH ; if ( HBS :: parseRegSequence ( MI ,


<s> } else { if ( helper_use_relative_reloc ( * rsym , pParent ) ) { got_entry -> setValue ( <ISA_LIT>Relocator :: SymVal ) ; Relocation & rel_entry = helper_DynRela_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_AARCH64_RELATIVE , pParent ) ; rel_entry . setAddend ( <ISA_LIT>Relocator :: SymVal ) ; pParent . getRelRelMap ( ) . record ( pReloc , rel_entry ) ; } else { helper_DynRela_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_AARCH64_GLOB_DAT , pParent ) ; got_entry -> setValue ( <NUM_LIT> ) ; } } return *


<s> constant = ( med_defect + max_defect ) * <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ; if ( constant < - <NUM_LIT> || constant > <NUM_LIT> ) abort ( ) ; constants [ i ] = constant ; calc_defect ( x_low , constant , factor ) ; calc_defect ( x_med , constant , factor ) ; calc_defect ( x_high , constant , factor ) ; } printf ( <STR_LIT> ) ; printf ( <STR_LIT> , BIAS ) ; printf ( <STR_LIT> , max_defect , max_defect_x ) ; printf ( <STR_LIT> , min_defect , min_defect_x ) ; printf ( <STR_LIT> , max_defect2 , max_defect2_x ) ; printf ( <STR_LIT> , min_defect2 , min_defect2_x ) ; printf ( <STR_LIT> , max_defect3 , max_defect3_val , max_defect3_x ) ; printf ( <STR_LIT> , min_defect3 , min_defect3_val , min_defect3_x ) ; printf ( <STR_LIT> , calc_defect ( <NUM_LIT> , constants [ <NUM_LIT> ] , factors [ <NUM_LIT> ] ) ) ; printf ( <STR_LIT> , calc_defect ( - <NUM_LIT> , constants [ steps ]


<s> std :: pair < MachineOperand * , unsigned > Src = Srcs [ j ] ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << <NUM_LIT> ) | Chan ) ; } } } return fitsConstReadLimitations ( Consts )


* punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT

, FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> } if ( REnd != RBegin ) ArgOffset = - <NUM_LIT> * ( <STR_LIT> - RBegin ) ; int FrameIndex = MFI -> CreateFixedObject ( ArgSize , ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg < REnd ; ++ Reg , ++ i ) { unsigned VReg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( OrigArg , <NUM_LIT> * i ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store


<s> return ST -> getMaxInterleaveFactor (


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { Inst . addOperand ( MCOperand :: CreateReg ( getReg (


<s> bool hasFRInt3264 ( ) const { return HasFRInt3264


<s> int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( AFI -> isGPRCalleeSavedArea1Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea1Offset ( ) ; else if ( AFI -> isGPRCalleeSavedArea2Frame ( FrameIndex ) ) Offset -= AFI -> getGPRCalleeSavedArea2Offset ( ) ; else if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( )


<s> BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT>

) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> bool isTargetMachO ( ) const { return TargetTriple . isOSBinFormatMachO ( )


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT>


<s> static bool aarch64_print_ldpstp_address ( FILE * f , machine_mode mode , rtx


<s> } uint64_t Buffer = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; unsigned ThisByte = <NUM_LIT> ; while ( * Beads ) { uint8_t Bead = * Beads ; Beads ++ ; if ( ! ( Bead & <NUM_LIT> ) ) { switch ( Bead >> <NUM_LIT> ) { case <STR_LIT> : continue ; } } switch ( Bead & <NUM_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset += EncodeBits ( ThisByte , Bead , MI , Desc , Buffer , Offset , Fixups , STI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset += EncodeReg ( ThisByte , Bead , MI , Desc , Buffer , Offset , Fixups , STI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset += EncodeImm ( ThisByte , Bead , MI , Desc , Buffer , Offset , Fixups , STI ) ; break ; } while ( Offset / <NUM_LIT> ) { OS . write ( ( char ) ( ( Buffer >> <NUM_LIT> ) & <NUM_LIT> ) ) ; OS . write ( ( char ) ( ( Buffer >> <NUM_LIT> ) & <NUM_LIT> ) ) ; Buffer >>= <NUM_LIT> ; Offset -= <NUM_LIT> ; ThisByte += <NUM_LIT>


<s> bool <ISA_LIT>MCInstrInfo :: hasImm ( MCInstrInfo const & MCII , MCInst const & MCI ) { return <ISA_LIT>II :: getHasImm ( getDesc ( MCII ,


<s> avr_fix_operands ( op , hreg , opmask , rmask ) ; lock = true ; emit_insn ( gen ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: COPY ) , Out ) . addReg ( DReg , <NUM_LIT> , Lane ) ; return Out


<s> case V4HImode : case V2SImode : case V1DImode : case V2SFmode : return SPE_CONST_OFFSET_OK ( offset ) ; case DFmode : case DDmode : case DImode : if ( TARGET_E500_DOUBLE ) return SPE_CONST_OFFSET_OK ( offset ) ; if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ; break ; case TFmode : case IFmode : case KFmode : if ( TARGET_E500_DOUBLE ) return ( SPE_CONST_OFFSET_OK ( offset ) && SPE_CONST_OFFSET_OK ( offset + <NUM_LIT> ) ) ; case TDmode : case TImode : case PTImode : extra = <NUM_LIT> ; if ( ! worst_case


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment (


<s> if ( TREE_CODE ( arg . type ) == VECTOR_TYPE && int_size_in_bytes ( arg . type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_pass_big_vectors = false ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; if ( ! warned_for_pass_big_vectors ) { warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> <STR_LIT> ) ; warned_for_pass_big_vectors = true ; } return <NUM_LIT>


<s> if ( HasAlloca || HasExtraAlign ) return true ; if ( MFI . getStackSize ( ) > <NUM_LIT> ) { const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . Options . DisableFramePointerElim ( MF ) || ! EliminateFramePointer ) return true ; if ( EnableStackOVFSanitizer ) return true ; } const auto & HMFI = * MF . getInfo


<s> return ( __m128i ) __builtin_ia32_loaddquqi128_mask ( ( __v16qi * ) __P , ( __v16qi ) _mm_setzero_hi ( ) , (


<s> assert ( NumOps >= <NUM_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && ( OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> || OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeNEONRd ( insn ) ) ) ) ; ++ OpIdx ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; ++ OpIdx ; } assert ( ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> || OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , OpInfo [ OpIdx ] . RegClass , decodeNEONRm ( insn ) ) ) ) ; ++ OpIdx


<s> Register SspFirstShrReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowMBB , DL , TII -> get ( ShrRIOpc ) , SspFirstShrReg ) . addReg ( SspSubReg ) . addImm ( Offset ) ; unsigned IncsspOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( fixShadowMBB , DL , TII -> get ( IncsspOpc ) ) . addReg ( SspFirstShrReg ) ; Register SspSecondShrReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowMBB , DL , TII -> get ( ShrRIOpc ) , SspSecondShrReg ) . addReg ( SspFirstShrReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( fixShadowMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( <STR_LIT> ) ; fixShadowMBB -> addSuccessor ( sinkMBB ) ; fixShadowMBB -> addSuccessor ( fixShadowLoopPrepareMBB ) ; unsigned ShlR1Opc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register SspAfterShlReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowLoopPrepareMBB , DL , TII -> get ( ShlR1Opc ) , SspAfterShlReg ) . addReg ( SspSecondShrReg ) ; Register Value128InReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned MovRIOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( fixShadowLoopPrepareMBB , DL , TII -> get ( MovRIOpc ) , Value128InReg ) . addImm ( <NUM_LIT> ) ; fixShadowLoopPrepareMBB -> addSuccessor ( fixShadowLoopMBB ) ; Register DecReg = MRI . createVirtualRegister ( PtrRC ) ; Register CounterReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( <STR_LIT> ) , CounterReg ) . addReg ( SspAfterShlReg ) . addMBB ( fixShadowLoopPrepareMBB ) . addReg ( DecReg ) . addMBB ( fixShadowLoopMBB ) ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( IncsspOpc ) ) . addReg ( Value128InReg ) ; unsigned DecROpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( DecROpc ) , DecReg ) . addReg ( CounterReg ) ; BuildMI ( fixShadowLoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( fixShadowLoopMBB ) . addImm ( <STR_LIT> ) ; fixShadowLoopMBB -> addSuccessor ( sinkMBB ) ; fixShadowLoopMBB -> addSuccessor


<s> } case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( MI . getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI . getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm (


<s> if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ; return


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext &


<s> gcc_assert ( GET_CODE ( x ) == CONST ) ; plus = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( plus ) == PLUS || GET_CODE ( plus ) == MINUS ) { rtx unspec ; rtx addend ; unspec = XEXP ( plus , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; addend = XEXP ( plus , <NUM_LIT> ) ; gcc_assert ( CONST_INT_P (


<s> if ( isUniform ( Term ) ) return ; Value * Ret = CallInst :: Create ( If , Term -> getCondition ( ) , <STR_LIT> , Term ) ; Term -> setCondition ( ExtractValueInst :: Create ( Ret ,


<s> switch ( LMUL ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return createM1Tuple ( CurDAG , Regs , NF ) ; case <STR_LIT> : return createM2Tuple ( CurDAG ,


<s> return - <NUM_LIT> ; } case MCExpr :: Unary : return - <NUM_LIT> ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ; int64_t LHSVal = EvaluateCRExpr ( BE -> getLHS ( ) ) ; int64_t RHSVal = EvaluateCRExpr ( BE -> getRHS ( ) ) ; int64_t Res ; if ( LHSVal < <NUM_LIT> || RHSVal < <NUM_LIT> ) return - <NUM_LIT> ; switch ( BE -> getOpcode ( ) ) { default : return - <NUM_LIT> ; case MCBinaryExpr :: Add : Res = LHSVal + RHSVal ; break ; case MCBinaryExpr :: Mul : Res = LHSVal * RHSVal ; break ; } return Res < <NUM_LIT> ? - <NUM_LIT> : Res ; } } llvm_unreachable ( <STR_LIT>


<s> <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetPush ( ) ; TS . emitDirectiveSetAt ( ) ; TS . emitDirectiveSetMacro (


<s> MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) .


<s> static bool isUndefOrZeroOrInRange ( ArrayRef < int > Mask , int Low , int


<s> if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> ,


<s> if ( OptimizationGoals == - <NUM_LIT> ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = <NUM_LIT> ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; emitAlignment ( Align ( <NUM_LIT> ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> emitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( TIP . first ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; } ThumbIndirectPads . clear ( ) ; } return false


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { TargetRegistry :: RegisterTarget ( getTheARM64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [

] ( Triple :: ArchType ) { return false ; } , true ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const

MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> return & ( InstrInfo . getRegisterInfo


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> if ( L && L -> empty ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) > <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) <= <NUM_LIT> ) { UP . PeelCount


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand ::


<s> OperandMatchResultTy parseBDAddr64 ( OperandVector & Operands


<s> SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode ,


<s> case E_TFmode : r1 = gen_rtx_REG ( DImode , gregno ) ; r1 = gen_rtx_EXPR_LIST ( VOIDmode , r1 , const0_rtx ) ; r3 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r3 = gen_rtx_EXPR_LIST ( VOIDmode , r3 , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , r1 , r3 ) ) ; case E_TCmode : r1 = gen_rtx_REG ( DImode , gregno ) ; r1 = gen_rtx_EXPR_LIST ( VOIDmode , r1 , const0_rtx ) ; r3 = gen_rtx_REG ( DImode , gregno + <NUM_LIT> ) ; r3 = gen_rtx_EXPR_LIST ( VOIDmode , r3 , GEN_INT


<s> old_label = JUMP_LABEL ( insn ) ; target = gen_rtx_LABEL_REF ( Pmode , old_label ) ; mips16_load_branch_target ( temp , target ) ; jump = emit_jump_insn ( PMODE_INSN ( gen_indirect_jump_and_restore , ( temp , temp , saved_temp ) ) ) ; JUMP_LABEL ( jump ) = old_label ; LABEL_NUSES ( old_label ) ++ ; mips16_lay_out_constants ( false ) ; if ( simplejump_p ( insn ) ) new_label = NULL ; else { new_label = gen_label_rtx ( ) ; emit_label ( new_label


<s> static DecodeStatus DecodeG8RCRegisterClass ( MCInst & Inst , uint64_t RegNo ,

uint64_t Address , const MCDisassembler * Decoder ) {


<s> auto IsHazardFn = [ TII ] ( MachineInstr * MI ) { return getHWReg ( TII , * MI ) == <STR_LIT> :: ID_TRAPSTS ; } ; int WaitStatesNeeded = getWaitStatesSinceSetReg ( IsHazardFn , RFEWaitStates ) ; return RFEWaitStates - WaitStatesNeeded


<s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; if ( CSI . empty ( ) ) { return false ; } bool ContiguousRegs = true ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned SuperReg = uniqueSuperReg ( Reg , TRI ) ; bool CanUseDblStore = false ; const TargetRegisterClass * SuperRegClass = <NUM_LIT> ; if ( ContiguousRegs && ( i < CSI .


<s> if ( VRM -> hasShape ( VirtReg ) ) return VRM -> getShape ( VirtReg ) ; const MachineOperand & Def = * MRI -> def_begin ( VirtReg ) ; MachineInstr * MI = const_cast < MachineInstr * > ( Def . getParent ( ) ) ; unsigned OpCode = MI -> getOpcode ( ) ; switch ( OpCode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MO2 = MI -> getOperand


<s> for ( const auto & MO : LastTrackedMI -> defs ( ) ) { if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg


<s> void printAMIndexed8 ( const MCInst * MI , unsigned


<s> int getReturnAddrSaveIndex ( ) const { return ReturnAddrSaveIndex


<s> printInstruction ( MI , OS ) ; printAnnotation ( OS


<s> } unsigned NumRegionInstrs = std :: distance ( begin ( ) , end ( ) ) ; enterRegion ( MBB , begin ( ) , end ( ) , NumRegionInstrs ) ; if ( begin ( ) == end ( ) || begin ( ) == std :: prev ( end ( ) ) ) { exitRegion ( ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << MF . getName ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> << * begin ( ) << <STR_LIT> ; if ( RegionEnd != MBB -> end (


<s> } if ( known_ge ( GET_MODE_SIZE ( mode ) , BYTES_PER_RISCV_VECTOR ) && GET_MODE_CLASS ( mode ) != MODE_VECTOR_BOOL ) { if ( MEM_P ( dest ) && ! REG_P ( src ) ) src = force_reg ( mode , src ) ; return false ; } if ( register_operand ( src , mode ) && register_operand ( dest , mode ) ) { emit_insn ( gen_rtx_SET ( dest , src ) ) ; return true ; } if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) emit_vlmax_op ( code_for_pred_mov ( mode ) , tmp , src , mask_mode ) ; else emit_move_insn ( tmp , src ) ; src = tmp ; } if ( satisfies_constraint_vu ( src ) ) return false ; emit_vlmax_op ( code_for_pred_mov ( mode ) , dest , src , mask_mode ) ; return true


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>BranchFixup :: verify ( ) { for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , E = MF -> end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; unsigned MBBId = MBB ->


<s> auto * MMIWP = getAnalysisIfAvailable < MachineModuleInfoWrapperPass > ( ) ; if ( ! MMIWP ) return true ; MachineModuleInfo & MMI = MMIWP -> getMMI ( ) ; MachineModuleInfoWasm & MMIW = MMI . getObjFileInfo < MachineModuleInfoWasm > ( ) ; for ( Function & F : M ) { MachineFunction * MF = MMI . getMachineFunction ( F ) ; if ( ! MF ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF -> getName ( ) << '\n' ) ; for ( MachineBasicBlock & MBB


<s> static SDValue PerformSExtCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue R = WidenMaskArithmetic ( N , DAG


<s> } else { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; } report_fatal_error ( <STR_LIT>


<s> if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success )


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> unsigned Divisor = <NUM_LIT> << Bits ; if ( Val % Divisor != <NUM_LIT> ) return false ; Val /= Divisor ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT>


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE && TREE_CODE ( type ) != OPAQUE_TYPE ) return NULL ; if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_long_type_node ) return <STR_LIT> ; if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) )


<s> void <ISA_LIT>InstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned * Reg , int64_t Value ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned Opcode ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = STI . isRV64 ( ) ? & <STR_LIT> : & <STR_LIT> ; unsigned ZERO = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; * Reg = RegInfo . createVirtualRegister ( RC ) ; if ( isInt < <NUM_LIT> > ( Value ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , * Reg ) . addReg ( ZERO )


<s> void <ISA_LIT>ATTInstPrinter :: printSTiRegOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & OS ) { const MCOperand & Op = MI -> getOperand ( OpNo


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return getFrameLowering ( MF ) -> hasFP ( MF ) ? ( Is24Bit ? <STR_LIT> : <STR_LIT> ) :


<s> void clearFeatureBits ( uint64_t Feature , StringRef FeatureString ) { if ( STI . getFeatureBits ( ) & Feature ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand (


<s> if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) mode = smallest_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , <NUM_LIT> , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST

( VOIDmode , reg , GEN_INT ( intoffset ) ) ;


<s> return frame_insn ( gen_rtx_SET ( VOIDmode , dst ,


<s> bool isMemPlaceholder ( const MCInstrDesc


<s> } if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( load ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeT2AddrModeImm8 ( Inst , addr , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> if ( * CM != CodeModel :: Small && * CM != CodeModel :: Tiny && * CM != CodeModel :: Large ) { if ( ! TT . isOSFuchsia ( ) ) report_fatal_error ( <STR_LIT> ) ; else if ( * CM != CodeModel :: Kernel ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else if ( * CM == CodeModel :: Tiny && ! TT . isOSBinFormatELF ( ) ) report_fatal_error ( <STR_LIT> ) ; return * CM


<s> flags_mode = GET_MODE ( flags ) ; if ( GET_MODE ( SET_SRC ( op1 ) ) != flags_mode ) return false ; if ( GET_MODE_CLASS ( flags_mode ) != MODE_CC ) return false ; if ( cc_flags_for_mode ( flags_mode ) & ~ cc_flags_for_mode ( cc_mode ) ) return false ; return true


<s> void <ISA_LIT>CFGStructurizer :: retireBlock ( MachineBasicBlock * MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; ) ; BlockInformation * & SrcBlkInfo = BlockInfoMap [ MBB


<s> next = NEXT_INSN ( insn ) ; } at_end = insn == BB_END ( bb ) ; if ( delete_this == NULL_RTX && ( at_end || GET_MODE ( next ) == TImode ) ) { if ( ( n_filled < <NUM_LIT> || ! gen_one_bundle ( slot ) ) && slot [ <NUM_LIT> ] != NULL_RTX ) { rtx pat = PATTERN ( slot [ <NUM_LIT> ] ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == UNSPEC && XINT ( SET_SRC ( pat ) , <NUM_LIT> ) == UNSPEC_32BIT ) { SET_SRC ( pat ) = XVECEXP ( SET_SRC ( pat ) , <NUM_LIT> , <NUM_LIT> ) ; INSN_CODE ( slot [ <NUM_LIT> ] ) = - <NUM_LIT> ; df_insn_rescan ( slot [


<s> } else if ( RRC == & <STR_LIT> ) { if ( LRC == & <STR_LIT> ) return <STR_LIT> ; else if ( LRC == & <STR_LIT> ) return <STR_LIT> ; else if ( LRC == & <STR_LIT> ) return <STR_LIT> ; } else if ( RRC == & <STR_LIT> ) { if ( LRC == & <STR_LIT> ) return <STR_LIT> ; else if ( LRC == &


<s> if ( IntKind == <STR_LIT> ) { MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; STI . getInstrInfo ( ) -> storeRegToStack ( MBB , MBBI , <STR_LIT> , false , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) , <NUM_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; STI . getInstrInfo ( ) -> storeRegToStack ( MBB , MBBI , <STR_LIT> , false , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) , <NUM_LIT> ) ; unsigned InsPosition = <NUM_LIT> ; unsigned InsSize = <NUM_LIT> ; unsigned SrcReg = <STR_LIT> ; if ( IntKind == <STR_LIT> ) { SrcReg = <STR_LIT> ; InsPosition = <NUM_LIT> ; InsSize = <NUM_LIT> ; } else InsSize = StringSwitch < unsigned > ( IntKind ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; assert ( InsSize != <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( InsPosition ) . addImm ( InsSize ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( ! STI . useSoftFloat ( ) ) BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg (


<s> OperandMatchResultTy parseBDRAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands , BDRMem


<s> if ( VT == <STR_LIT> ) { return Subtarget -> hasMadF16 ( ) && ! hasFP64FP16Denormals ( DAG . getMachineFunction ( ) ) ; } return


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return &


<s> case <STR_LIT> : case <STR_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; } break ; case 'a' : if ( VT != <STR_LIT> ) return { <NUM_LIT> , nullptr } ; return { <NUM_LIT> , & <STR_LIT> } ; case 'q' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; case <NUM_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVX128BOps ( ) ) return { <NUM_LIT> , & <STR_LIT> } ; return { <NUM_LIT> , & <STR_LIT> } ; case <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: storeRegToAddr ( MachineFunction & MF , unsigned SrcReg , bool isKill , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { llvm_unreachable ( <STR_LIT> )


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer (


<s> if ( RB0 == - <NUM_LIT> ) return RB1 ; if ( RB1 == -


<s> return TargetTriple . getOS ( ) == Triple


<s> Visited . insert ( Header ) ; while ( ! LoopWorklist . empty ( ) ) { SuccessorList & Top = LoopWorklist . back ( ) ; if ( Top . HasNext ( ) ) { MachineBasicBlock * Next = Top . Next ( ) ; if ( Next == Header || ( Loop && ! Loop -> contains ( Next ) ) ) continue ; if ( LLVM_LIKELY ( OnStack . insert ( Next ) . second ) ) { if ( ! Visited . insert ( Next ) . second ) { OnStack . erase ( Next ) ; continue ; } MachineLoop * InnerLoop = MLI . getLoopFor ( Next ) ; if ( InnerLoop != Loop ) LoopWorklist . push_back ( SuccessorList ( InnerLoop ) ) ; else LoopWorklist . push_back ( SuccessorList ( Next ) ) ; } else { RewriteSuccs . insert ( Top . getBlock ( ) ) ; } continue ; } OnStack . erase ( Top . getBlock ( ) ) ; LoopWorklist . pop_back ( ) ; } if ( LLVM_LIKELY ( RewriteSuccs . empty ( ) ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * Dispatch = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , Dispatch ) ; MLI . changeLoopFor ( Dispatch , Loop ) ; const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * Dispatch , Dispatch -> end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( Reg ) ; DenseMap < MachineBasicBlock * , unsigned


<s> inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl


<s> return ( ( qword ) ( vec_sel ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b ) , ( vec_uchar16 ) (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType


<s> static SDValue materializeVectorConstant ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return Op ; if ( Subtarget . hasSSE2 ( ) && <STR_LIT> ( Op . getNode ( ) ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> || VT


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return ST . hasGFX90AInsts ( ) ? CSR_<ISA_LIT>_GFX90AInsts_RegMask


<s> static bool is64bitCmpOp ( unsigned opCode ) { return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { <ISA_LIT>Operand * RegOp ; SMLoc VIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { unsigned RegNum = Parser . getTok ( ) . getIntVal ( ) ; int Reg = matchRegisterByNumber ( RegNum , regKindToRegClass ( <STR_LIT> ) ) ; if ( Reg == - <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegOp = <STR_LIT> ( Reg , VIdx , Parser . getTok ( ) . getLoc ( ) ) ; } else if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { int RegNum = - <NUM_LIT> ; std :: string RegName = Parser . getTok ( ) . getString ( ) . lower ( ) ; RegNum = matchCPURegisterName ( RegName ) ; if ( RegNum == - <NUM_LIT> ) { Error ( VIdx , <STR_LIT> ) ; return MatchOperand_ParseFail ; } RegNum = getReg ( regKindToRegClass ( <STR_LIT> ) , RegNum ) ; RegOp = <STR_LIT> ( RegNum , VIdx , Parser . getTok ( ) . getLoc ( ) ) ; } else return MatchOperand_ParseFail ; RegOp -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( RegOp ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } SMLoc VIdx = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * expr = dyn_cast <


<s> const SDValue & Shl = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * B = dyn_cast < ConstantSDNode > ( Shl -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( B &&


<s> static inline unsigned v2x ( unsigned v ) { return TargetRegisterInfo :: virtReg2Index ( v


<s> void <ISA_LIT>AnnotateUniformValues :: visitLoadInst ( LoadInst & I ) { Value * Ptr = I . getPointerOperand ( ) ; if ( ! DA -> isUniform (


<s> <ISA_LIT>Unbranch ( ) : FunctionPass ( ID ) { initialize<ISA_LIT>UnbranchPass ( * PassRegistry :: getPassRegistry ( )


<s> r11 = gen_rtx_REG ( DImode , FIRST_REX_INT_REG + <NUM_LIT> ) ; insn = emit_insn ( gen_rtx_SET ( DImode , r11 , offset ) ) ; if ( style < <NUM_LIT> ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_pro_epilogue_adjust_stack_rex64_2 ( dest , src , r11 , offset )


<s> unsigned i ; unsigned nunits = GET_MODE_NUNITS ( mode ) ; unsigned bitsize = GET_MODE_BITSIZE ( inner ) ; unsigned mask = GET_MODE_MASK ( inner ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - <NUM_LIT> ) ; HOST_WIDE_INT val = INTVAL ( last ) ; HOST_WIDE_INT splat_val = val ; HOST_WIDE_INT msb_val = val > <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= copies ; i *= <NUM_LIT> ) { HOST_WIDE_INT small_val ; bitsize /= <NUM_LIT> ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= <NUM_LIT> || ( step == <NUM_LIT> && copies == <NUM_LIT> ) ) ) ; else return false ; for ( i = <NUM_LIT> ; i < nunits - <NUM_LIT> ; ++ i ) { HOST_WIDE_INT desired_val ; if ( ( ( i + <NUM_LIT> ) & ( step - <NUM_LIT> )


<s> Value * OldSP = getReg ( <STR_LIT> ) ; Value * OpSizeVal = ConstantInt :: get ( IntegerType :: get ( getContext ( ) , OldSP -> getType ( ) -> getIntegerBitWidth ( ) ) , OpSize ) ; Value * NewSP = Builder . CreateSub ( OldSP , OpSizeVal ) ; Value * SPPtr = Builder . CreateIntToPtr ( NewSP , Val -> getType ( ) -> getPointerTo ( ) ) ; Builder . CreateStore ( Val , SPPtr


<s> const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize =


<s> unsigned <ISA_LIT>HazardRecognizer :: getNumDecoderSlots ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) )


<s> static unsigned getSubOpcode ( bool Is64Bit , int64_t Amount ) { if ( Is64Bit ) return isInt < <NUM_LIT> > ( Amount


<s> void <ISA_LIT>DelaySlotFiller :: insertNOPAfter ( MachineBasicBlock & MBB , const MachineBasicBlock :: iterator I ) { MachineBasicBlock :: iterator NI = llvm :: next (


<s> if ( Subtarget -> hasSMulHi ( ) && ! N -> isDivergent ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! isI24 ( N0 , DAG ) || ! isI24 ( N1 , DAG ) ) return


<s> return MRI . getRegClass ( Reg ) ; } const <ISA_LIT>RegisterInfo * TRI = static_cast < const GCNSubtarget * > ( Subtarget ) -> getRegisterInfo ( ) ; return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [


<s> rtx x = args [ argno ] ; if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) ) mode = GET_MODE_INNER ( mode ) ; x = simplify_unary_operation ( NEG , mode , x , mode ) ; if ( ! x ) return false ; args [ argno ] = x ; return true


<s> Ild . the_operandID = <STR_LIT> ; Ild . the_idxDst0 = false ; Ild . the_isOpTypeFloat = false ; Ild . the_isIRFDest = false ; Ild . the_isVectorPipe = false ; Ild . the_isLFSRImplicitDst = false ; Ild . the_isAccFp32 = false ; Ild . the_is2SrfDst = false ; Ild . the_is2xLookupAddSub = false ; Ild . the_registerFile = <STR_LIT> ; Ild . the_isFp16 = false


<s> StringRef Name = L -> getHeader ( ) -> getParent ( ) -> getName ( ) ; if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) return false ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; DL = & L -> getHeader ( ) -> getModule ( ) -> getDataLayout ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LF = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TLI = & getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( * L -> getHeader ( ) -> getParent ( ) ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; HasMemcpy = TLI -> has


<s> case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case


<s> MO . ChangeToTargetIndex ( <STR_LIT> , Depth ) ; Elem . DebugValue = & MI ; break ; } } } } else { for ( MachineOperand & MO : reverse ( MI . explicit_uses ( ) ) ) { if ( MO . isReg ( ) && MFI . isVRegStackified ( MO . getReg ( ) ) ) { auto Prev = Stack . back ( ) ; Stack . pop_back ( ) ; assert ( Prev . Reg == MO . getReg ( ) && <STR_LIT> ) ; if ( Prev . DebugValue && ! MI . isTerminator ( ) ) { BuildMI ( * Prev . DebugValue -> getParent ( ) , std :: next ( MII ) , Prev . DebugValue -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , false , Register ( ) , Prev . DebugValue

-> getOperand ( <NUM_LIT> ) . getMetadata ( ) , Prev . DebugValue -> getOperand ( <NUM_LIT> ) . getMetadata ( ) ) ;


<s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , GET_MODE_BITSIZE ( Pmode ) ) ; fputs ( <STR_LIT> , asm_out_file )


<s> if ( MO -> OperandType == MCOI :: OPERAND_MEMORY ) return i ; i ++ ; } return - <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; if ( isUnsupportedFloatingType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , false , SDLoc ( Op


<s> Inst . setOpcode ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( get<ISA_LIT>SubSuperRegister


<s> break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) ) { assert ( MAI . doesSetDirectiveSuppressesReloc ( ) ) ; MCSymbol * Label = Ctx . CreateTempSymbol ( ) ; AsmPrinter . OutStreamer . EmitAssignment ( Label , Expr ) ; Expr = MCSymbolRefExpr :: Create ( Label , Ctx


<s> return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) && MF . getSubtarget < <ISA_LIT>Subtarget > (


<s> char charVal = cast < ConstantInt > ( CVA -> getOperand ( i ) ) -> getZExtValue ( ) ; stringIsPrintable = stringIsPrintable && ( isprint ( charVal ) || ! charVal ) ; } if ( ! stringIsPrintable ) { for ( unsigned j = <NUM_LIT> , e = CVA -> getNumOperands ( ) ; j != e ; ++ j ) { char charVal = cast < ConstantInt > ( CVA -> getOperand ( j ) ) -> getZExtValue ( ) ; OS << MAI -> getData8bitsDirective ( ) << ( int ) charVal << '\t' ; if ( std :: isprint ( charVal ) ) OS << MAI -> getCommentString ( ) << <STR_LIT> << charVal << <STR_LIT> ; else OS << MAI -> getCommentString ( ) << <STR_LIT> ; } OutStreamer . EmitRawText ( OS . str ( ) ) ; refContents ( C ) ; return ; } } OutStreamer . EmitRawText ( OS . str ( )


<s> __builtin_aarch64_st1v8hi ( ( __builtin_aarch64_simd_hi * ) a


<s> return get_hard_reg_initial_val ( Pmode ,


<s> inline static unsigned HI22 ( int64_t imm ) { return ( unsigned ) ( ( imm >> <NUM_LIT> ) & ( (


<s> O << <STR_LIT> ; printMemReference ( MI


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( <STR_LIT> <STR_LIT> ) , InstrInfo ( ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) { initAsmInfo ( )


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsi_u64 ( unsigned long long __X ) { return __blsi_u64 (


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimmInvPow2 ( SDValue N ,


<s> emit_insn ( gen_vsx_sign_extend_v16qi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrhx ) { temp1 = simplify_gen_subreg ( V8HImode , tiscratch , TImode , <NUM_LIT> ) ; emit_insn ( gen_vsx_sign_extend_v8hi_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrwx ) { temp1 = simplify_gen_subreg ( V4SImode , tiscratch , TImode , <NUM_LIT> ) ; emit_insn ( gen_vsx_sign_extend_v4si_v2di ( discratch , temp1 ) ) ; } else if ( icode == CODE_FOR_vsx_lxvrdx ) discratch = simplify_gen_subreg ( V2DImode ,


<s> return GV != nullptr || CP != nullptr || ES != nullptr || MCSym != nullptr || JT != - <NUM_LIT> || BlockAddr


<s> if ( ! ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && isa < ConstantFPSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && isa < ConstantFPSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) ) return Op ; APInt E0 = cast < ConstantFPSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getValueAPF ( ) .


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF

:: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> ArrayRef < MCPhysReg > AllSGPR128s = TRI -> getAllSGPR128 ( MF ) ; AllSGPR128s = AllSGPR128s . slice ( std :: min ( static_cast < unsigned > ( AllSGPR128s . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPR128s ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq


<s> virtual const char * getPassName ( ) const { return


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: KILL ) , getCRFromCRBit ( SrcReg ) ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg

( Reg , RegState :: Kill ) , FrameIndex ) ;


<s> PHILinearize :: source_iterator PHILinearize :: sources_begin


<s> auto BA = newBlock ( Func , & B ) ; BlockNodes . insert ( std :: make_pair ( & B , BA ) ) ; for ( auto & I : B ) { if ( I . isDebugValue ( ) ) continue ; buildStmt ( BA , I ) ; } } NodeAddr < BlockNode * > EA = Func . Addr -> getEntryBlock ( * this ) ; BlockRefsMap RefM ; buildBlockRefs ( EA , RefM ) ; MachineRegisterInfo & MRI = MF . getRegInfo (


<s> OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBinaryData ( <STR_LIT> ) ; unsigned DestRegs [ ] = { <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false } ; unsigned SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = Op -> getReg ( ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; }


<s> bool <ISA_LIT>ConstantIslands :: OptimizeThumb2Branches ( MachineFunction & MF ) { bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) { ImmBranch & Br = ImmBranches [ i ] ; unsigned Opcode = Br . MI -> getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned Bits = <NUM_LIT> ; switch ( Opcode ) { default : break ; case <STR_LIT> : NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } } if ( NewOpc ) { unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( Br . MI , DestBB , MaxOffs ) ) { Br . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBSizes [ MBB -> getNumber ( ) ] -= <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , - <NUM_LIT> ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOffset = GetOffsetOf ( Br . MI )


<s> return ( VersionMajor >= <NUM_LIT> )


<s> void addExtraBytes ( const MachineBasicBlock :: iterator I , unsigned ExtraBytes ) { auto Info = llvm :: find_if ( Insts , [ & ] ( InstInfo & Info )


<s> void printMemOffs32 ( const MCInst * MI , unsigned OpNo


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O


<s> FunctionPass * create<ISA_LIT>OffsetAllocator ( ) { return new <ISA_LIT>OffsetAllocator


<s> <STR_LIT> BlackfinTargetLowering :: getSetCCResultType ( EVT VT ) const { return <STR_LIT>


<s> if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return AM . Scale == <NUM_LIT> && isImmUs ( AM . BaseOffs ) && isImmUs4 ( AM . BaseOffs ) ; const TargetData * TD = TM . getTargetData ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= <NUM_LIT> && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && AM . BaseOffs % <NUM_LIT> == <NUM_LIT> ; } switch ( Size ) { case <NUM_LIT> : if ( AM . Scale == <NUM_LIT> ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : if ( AM . Scale == <NUM_LIT> ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ; default : if ( AM . Scale == <NUM_LIT> ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == <NUM_LIT> &&


<s> if ( ! ExTab && ! CantUnwind ) FlushUnwindOpcodes ( true ) ; SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex < NUM_PERSONALITY_INDEX ) EmitPersonalityFixup ( GetAEABIUnwindPersonalityName ( PersonalityIndex ) ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( EXIDX_CANTUNWIND , <NUM_LIT> ) ; } else if ( ExTab ) { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> ) ; } else { assert ( PersonalityIndex == AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EmitBytes ( StringRef ( reinterpret_cast < const char * > ( Opcodes . data ( ) ) , Opcodes . size ( ) ) ) ; } SwitchSection ( & FnStart ->


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) .


<s> unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ; if ( Val -> getScalarType ( ) -> isFloatingPointTy ( ) && Index == <NUM_LIT> ) return <NUM_LIT> ; } return TargetTransformInfo :: getVectorInstrCost ( Opcode , Val , Index


<s> Register IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Opnd2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V ; if ( MRI -> getVRegDef ( IndReg ) == Phi && checkForImmediate ( Opnd2 , V ) ) { Register UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * TB = nullptr , * FB = nullptr ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return false ; unsigned PredR , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) return false ; MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; if ( ! PredI -> isCompare ( ) ) return false ; Register CmpReg1 , CmpReg2 ; int CmpImm = <NUM_LIT> , CmpMask = <NUM_LIT> ; bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ; if ( ! CmpAnalyzed ) return false ; InductionMap :: iterator IndMapEnd = IndMap . end ( ) ; InductionMap :: iterator F = IndMapEnd ; if ( CmpReg1 != <NUM_LIT> ) { InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ; if ( F1 != IndMapEnd ) F = F1 ; } if ( CmpReg2 != <NUM_LIT> ) { InductionMap :: iterator F2 = IndMap . find (


<s> addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ; addPass ( createInferAddressSpacesPass (


<s> static int avr_interrupt_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , <STR_LIT>


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT>


<s> unsigned VFPThumb2PostEncoder ( const MachineInstr & MI , unsigned Val ) const { return


<s> bool useFPForScavengingIndex ( const MachineFunction & MF


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc & dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , false

, false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> MF -> push_back ( BB ) ; unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( MaxAlign ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) &&


<s> m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset


<s> isThumb ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> )

, GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Identifier : { StringRef Tok = Parser . getTok ( ) . getString ( ) ; if ( Tok == Name ) { if ( Tok == <STR_LIT> && isGFX9 ( ) ) Error ( S , <STR_LIT> ) ; if ( Tok == <STR_LIT> && ! isGFX9 ( ) ) Error ( S , <STR_LIT> ) ; Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else if ( Tok . startswith ( <STR_LIT> ) && Tok . endswith ( Name ) ) { Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else { return MatchOperand_NoMatch ; } break ; } default : return MatchOperand_NoMatch ; } } if ( ! isGFX10 ( ) && ImmTy == <ISA_LIT>Operand ::

ImmTyDLC ) return MatchOperand_ParseFail ;


<s> if ( stackSize ) { if ( stackSize <= <NUM_LIT> ) { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( stackSize ) ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; } else { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) )


<s> return checkType ( N -> getMemOperand ( ) -> getValue


<s> if ( CurrentSCC . size ( ) == <NUM_LIT> ) continue ; InSet . insert ( CurrentSCC . begin ( ) , CurrentSCC . end ( ) ) ; MachineBasicBlock * Header = nullptr ; for ( MachineBasicBlock * MBB : CurrentSCC ) { for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) { if ( InSet . count ( Pred )


<s> __builtin_mve_vstrhq_uv8hi ( ( __builtin_neon_hi * ) __addr ,


<s> bool m68k_legitimate_constant_p ( machine_mode mode , rtx x ) { return mode != XFmode && ! m68k_illegitimate_symbolic_constant_p


<s> SDValue A64CMP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TheBit , DAG . getConstant ( <NUM_LIT> , TheBit . getValueType ( ) ) , DAG . getCondCode ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , A64CMP

, DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DestBB ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH (


<s> static void assureFPCallStub ( Function & F , Module * M , const <ISA_LIT>TargetMachine & TM ) { if ( TM . isPositionIndependent ( ) ) return ; LLVMContext & Context = M -> getContext ( ) ; bool LE = TM . isLittleEndian ( ) ; std :: string Name ( F . getName ( ) ) ; std :: string SectionName = <STR_LIT> + Name ; std :: string StubName = <STR_LIT> + Name ; Function * FStub = M -> getFunction ( StubName ) ; if ( FStub && ! FStub -> isDeclaration ( ) ) return ; FStub = Function :: Create ( F . getFunctionType ( ) , Function :: InternalLinkage , StubName , M ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( Attribute :: Naked ) ; FStub -> addFnAttr ( Attribute :: NoInline ) ; FStub -> addFnAttr ( Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub -> getReturnType ( ) ) ; FPParamVariant PV = whichFPParamVariantNeeded ( F ) ; std :: string AsmText ; AsmText += <STR_LIT> ; AsmText += swapFPIntParams ( PV , M , LE , true ) ; if ( RV != NoFPRet ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } else { AsmText += <STR_LIT> + Name + <STR_LIT> ; AsmText += <STR_LIT> + Name + <STR_LIT> ; } switch ( RV ) { case FRet : AsmText += <STR_LIT> ; break ; case DRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case CFRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } else { AsmText += <STR_LIT> ; AsmText += <STR_LIT> ; } break ; case CDRet : if ( LE ) { AsmText += <STR_LIT> ; AsmText += <STR_LIT>


<s> MachineBasicBlock * BB = MF . begin ( ) ; if ( Fn . hasExternalLinkage ( ) && Fn . getName ( )

== <STR_LIT> ) EmitSpecialCodeForMain ( BB , MF . getFrameInfo ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerEH_SJLJ_LONGJMP ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc DL = Op . getDebugLoc


<s> std :: pair < unsigned , unsigned > WavesPerEU = MFI . getWavesPerEU ( ) ; unsigned MaxNumSGPRs = getMaxNumSGPRs ( WavesPerEU . first , false ) ; unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs ( WavesPerEU . first , true ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Requested = <STR_LIT> ( F , <STR_LIT> , MaxNumSGPRs ) ; if ( Requested && ( Requested <= getReservedNumSGPRs ( MF ) ) ) Requested = <NUM_LIT> ; unsigned InputNumSGPRs = MFI . getNumPreloadedSGPRs ( ) ; if ( Requested && Requested < InputNumSGPRs ) Requested = InputNumSGPRs ; if ( Requested && Requested > getMaxNumSGPRs ( WavesPerEU . first , false ) ) Requested = <NUM_LIT> ; if ( WavesPerEU . second && Requested && Requested < getMinNumSGPRs ( WavesPerEU . second ) ) Requested = <NUM_LIT> ; if ( Requested ) MaxNumSGPRs


<s> virtual const TargetFrameLowering * getFrameLowering


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; MVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue OutLo = DAG . getSelectCC ( dl , Tmp5 , DAG . getConstant ( <NUM_LIT> , AmtVT ) ,


<s> ASSERT_STREQ ( <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( cfun -> decl ) ) ) ; rtx_insn * insn_1 = get_insn_by_uid ( <NUM_LIT> ) ; ASSERT_EQ ( NOTE , GET_CODE ( insn_1 ) ) ; rtx_insn * insn_7 = get_insn_by_uid ( <NUM_LIT> ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_7 ) ) ; ASSERT_EQ ( PARALLEL , GET_CODE ( PATTERN ( insn_7 ) ) ) ; rtx_insn * insn_15 = get_insn_by_uid ( <NUM_LIT> ) ; ASSERT_EQ ( INSN , GET_CODE ( insn_15 ) ) ; ASSERT_EQ ( USE , GET_CODE ( PATTERN ( insn_15 ) ) ) ; ASSERT_EQ ( REG , GET_CODE ( crtl -> return_rtx ) ) ; ASSERT_EQ ( <NUM_LIT> , REGNO ( crtl -> return_rtx ) ) ; ASSERT_EQ ( SImode , GET_MODE ( crtl


<s> if ( STi >= StackTop ) report_fatal_error ( <STR_LIT> ) ; return Stack [ StackTop - <NUM_LIT> - STi


<s> return true ; case FK_Data_2 : Log2Size = Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_4 : Log2Size = Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case FK_Data_8 : Log2Size = Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind (


<s> return static_cast < const <ISA_LIT>Subtarget & > (


<s> return ( __m128i ) __builtin_ia32_loaddqusi128_mask ( ( const int * ) __P , ( __v4si ) __W , ( __mmask8 )


<s> static DecodeStatus DecodeLoadCP ( MCInst & Inst , unsigned insn , uint64_t Address , const


<s> MapRegToId RegToId ; MapIdToReg IdToReg ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( <ISA_LIT>FI && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; collectInvolvedReg ( MF , RegToId , IdToReg , TRI ) ; if ( RegToId . empty ( ) ) return false ; MachineInstr * DummyOp = nullptr ; if ( BasicBlockScopeOnly ) { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; DummyOp = MF . CreateMachineInstr ( TII -> get ( <STR_LIT> ) , DebugLoc ( ) ) ; } unsigned NbReg = RegToId . size ( ) ; bool Modified = false ; InstrToInstrs * ColorOpToReachedUses = new InstrToInstrs [ NbReg ] ; reachingDef ( MF , ColorOpToReachedUses , RegToId , true , DummyOp ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> int offset = <NUM_LIT> ; for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; CFRegNode . push_back ( Val . getValue ( Val -> getNumValues ( ) - <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; } } else { XFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , LRSaveSize + CCInfo . getNextStackOffset ( ) , true ) ) ; } } if ( ! CFRegNode . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CFRegNode ) ; for ( SmallVectorImpl < ArgDataPair > :: const_iterator ArgDI = ArgData . begin ( ) , ArgDE = ArgData . end ( ) ; ArgDI != ArgDE ; ++ ArgDI ) { if ( ArgDI -> Flags . isByVal ( ) && ArgDI -> Flags . getByValSize ( ) ) { unsigned Size = ArgDI -> Flags . getByValSize ( ) ; unsigned Align = std :: max ( StackSlotSize , ArgDI -> Flags . getByValAlign ( ) ) ; int FI = MFI -> CreateStackObject ( Size , Align , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( FIN ) ; MemOps . push_back ( DAG . getMemcpy ( Chain , dl , FIN , ArgDI -> SDV , DAG . getConstant ( Size , dl , <STR_LIT> ) , Align , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ) ; } else { InVals . push_back ( ArgDI


<s> bool hasGridWorkgroupCountZ ( ) const { return GridWorkgroupCountZ


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo * TII = MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } unsigned LowGPR = ZFI -> getLowSavedGPR ( ) ; unsigned HighGPR = ZFI -> getHighSavedGPR ( ) ; unsigned StartOffset = RegSpillOffsets [ LowGPR ] ; if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( LowGPR , RegState :: Define ) ; MIB . addReg ( HighGPR , RegState :: Define ) ; MIB . addReg ( HasFP ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] .


<s> EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , DCI , Subtarget ) ) return FPLogic ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue R = combineAndNotIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode >

( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) {


<s> bool hasFSQRT ( ) const { return HasFSQRT


<s> Src [ i ] = Src [ sz - i - <NUM_LIT> ] ; Src [ sz - i - <NUM_LIT> ]


<s> unsigned <ISA_LIT>TTIImpl :: getNumberOfRegisters ( bool Vec )


<s> OpRef L = shuffp1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffp1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen


<s> return new <ISA_LIT>WinCOFFAsmTargetStreamer ( S , OS ,


<s> int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; bool IsMulVL = isSVEScaledImmInstruction ( MI . getOpcode ( ) ) ; int64_t Offset = IsMulVL ? ( SOffset . getScalableBytes ( ) ) : ( SOffset . getBytes ( ) ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ; assert ( MinOff < MaxOff && <STR_LIT> ) ; int64_t NewOffset = Offset / Scale ; if ( MinOff <= NewOffset && NewOffset <= MaxOff ) Offset = Remainder ; else { NewOffset = NewOffset < <NUM_LIT> ? MinOff : MaxOff ; Offset = Offset - NewOffset * Scale + Remainder ; } if ( EmittableOffset ) * EmittableOffset


<s> if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; } unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NegShift = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue NegShiftLeft = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Opc , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , NegShift ) ; return NegShiftLeft ; } return SDValue


<s> _Unwind_VRS_Set ( context , _UVRSC_CORE , regno , _UVRSD_UINT32 ,


<s> if ( isImm ( ) ) { Inst . addOperand ( MCOperand :: CreateExpr ( getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return ; } int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Val


<s> static int const_costs_int ( HOST_WIDE_INT value , int zero_cost ) { if ( CONST_OK_FOR_I ( value ) ) return zero_cost ; else if ( CONST_OK_FOR_J ( value ) ) return <NUM_LIT> ; else if ( CONST_OK_FOR_K ( value ) ) return <NUM_LIT> ; else return


<s> case <NUM_LIT> : return V8BImode ; case <NUM_LIT> : return V4BImode ; case <NUM_LIT> : return


<s> selected_cpu = NULL ; selected_arch = NULL ; selected_tune = NULL ; if ( aarch64_cpu_string ) valid_cpu = aarch64_validate_mcpu ( aarch64_cpu_string , & selected_cpu , & cpu_isa ) ; if ( aarch64_arch_string ) valid_arch = aarch64_validate_march ( aarch64_arch_string , & selected_arch , & arch_isa ) ; if ( aarch64_tune_string ) valid_tune = aarch64_validate_mtune ( aarch64_tune_string , & selected_tune ) ; if ( ! selected_cpu ) { if ( selected_arch ) { selected_cpu = & all_cores [ selected_arch -> ident ] ; aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ; if ( TARGET_ILP32 ) error ( <STR_LIT> ) ; if ( aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE && TARGET_ILP32 ) sorry


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName (


<s> const MCPhysReg * <ISA_LIT>BaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) .


<s> const MCExpr * Expr = MO . isImm ( ) ? MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) : MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) ,


<s> for ( const MachineInstr & UseI : MRI . use_nodbg_instructions ( Reg ) ) { if ( ! InstrExec . count ( & UseI ) ) continue ; if ( UseI . isPHI ( ) ) visitPHI ( UseI ) ; else if ( ! UseI . isBranch ( ) ) visitNonBranch ( UseI ) ; else visitBranchesFrom (


<s> return ToHex ( Address32 ( addr_low ,


<s> bool <ISA_LIT>FastISel :: DefinesOptionalPredicate ( MachineInstr * MI , bool * CPSR ) { const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . hasOptionalDef (


<s> if ( ResTy != MatchOperand_Success || ! Op ) return MatchOperand_ParseFail ; Operands . push_back ( std :: move ( Op ) ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: LParen ) ) break ; break ; } } return MatchOperand_Success


<s> void <ISA_LIT>InstPrinter :: printGLC ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo &


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options .


<s> static bool CheckTyN ( unsigned N , const LegalityQuery & Query , std :: initializer_list


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressELF ( SDValue Op , SelectionDAG & DAG ) { EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return Result ; } else


<s> static bool m32r_return_in_memory ( tree type


<s> Branch :: Branch ( const char * ConditionInit , const char * CodeInit ) : Ancestor ( nullptr )


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return &


<s> static unsigned GetAnalyzableBrOpc ( unsigned Opc ) { return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc ==

<STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> return llvm :: all_of ( MBB . successors ( ) , [ ] ( const MachineBasicBlock * Succ ) { return Succ -> isEHPad ( ) ; } ) && std :: all_of ( MBBI , MBB . end ( ) , [ ] ( const MachineInstr & MI ) { return MI . isMetaInstruction (


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return


<s> else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler ::


<s> return new ( Ctx ) <ISA_LIT>MCExpr (


<s> return getTM < <ISA_LIT>TargetMachine


<s> bool mayNeedRelaxation ( const MCInst & Inst


<s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; }


<s> return MachineFunctionProperties ( ) . set (

MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( ! TII -> hasVALU32BitEncoding ( MI . getOpcode ( ) ) ) continue ; if ( ! canShrink ( MI , TII , TRI , MRI ) ) { if ( ! MI . isCommutable ( ) || ! TII -> commuteInstruction ( & MI ) || ! canShrink ( MI , TII , TRI , MRI ) ) continue ; } int Op32 = AMDGPU :: getVOPe32 ( MI . getOpcode ( ) ) ; if ( Op32 == - <NUM_LIT> ) continue ; if ( TII -> isVOPC ( Op32 ) ) { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MRI . setRegAllocationHint ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , AMDGPU :: VCC ) ; continue ; } if ( DstReg != AMDGPU :: VCC ) continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << '\n' ; ) ; MachineInstrBuilder Inst32 = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( Op32 ) ) ; Inst32 . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Inst32 . addOperand ( * TII -> getNamedOperand ( MI , AMDGPU :: OpName :: src0 ) ) ; const MachineOperand * Src1 = TII -> getNamedOperand ( MI , AMDGPU