<s> } MachineBasicBlock * CondBranchTarget = nullptr ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { CondBranchTarget = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; } if ( ! LayoutSucc || ( CondBranchTarget != JumpAroundTarget ) ) { continue ; } if ( ( NumSuccs == <NUM_LIT> ) && LayoutSucc && ( LayoutSucc -> pred_size ( ) == <NUM_LIT> ) ) { if ( ( LayoutSucc -> size ( ) == <NUM_LIT> ) && IsUnconditionalJump ( LayoutSucc -> front ( ) . getOpcode ( ) ) ) { assert ( JumpAroundTarget && <STR_LIT> ) ; MachineBasicBlock * UncondTarget = LayoutSucc -> front ( ) . getOperand ( <NUM_LIT> ) . getMBB ( ) ; bool case1 = LayoutSucc -> isLayoutSuccessor ( JumpAroundTarget ) ; bool case2 = JumpAroundTarget -> isSuccessor ( UncondTarget ) && ! JumpAroundTarget -> empty ( ) && IsUnconditionalJump ( JumpAroundTarget -> back ( ) . getOpcode ( ) ) && JumpAroundTarget -> pred_size ( ) == <NUM_LIT> && JumpAroundTarget -> succ_size ( ) == <NUM_LIT> ; if ( case1 || case2 ) { InvertAndChangeJumpTarget ( MI , UncondTarget ) ; MBB . replaceSuccessor ( JumpAroundTarget , UncondTarget ) ; LayoutSucc -> erase ( LayoutSucc -> begin ( ) ) ; LayoutSucc -> replaceSuccessor ( UncondTarget , JumpAroundTarget ) ; if ( case2 && ! case1 ) { JumpAroundTarget -> moveAfter ( LayoutSucc ) ; if ( ! isOnFallThroughPath ( UncondTarget ) ) UncondTarget -> moveAfter ( JumpAroundTarget ) ; } std :: vector < MachineBasicBlock :: RegisterMaskPair > OrigLiveIn ( LayoutSucc -> livein_begin ( ) , LayoutSucc -> livein_end ( ) ) ; std :: vector < MachineBasicBlock :: RegisterMaskPair > NewLiveIn ( JumpAroundTarget -> livein_begin ( ) , JumpAroundTarget -> livein_end ( ) ) ; for ( const auto & OrigLI : OrigLiveIn ) LayoutSucc -> removeLiveIn ( OrigLI


<s> void reserveBlocks ( unsigned Size ) { Blocks . reserve (


<s> if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && FloatDomain ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> if ( CPU . empty ( ) ) CPU = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU ,


<s> static inline bool s390_preserve_gpr_arg_in_range_p ( int first , int last ) { int num_arg_regs = MIN ( crtl -> args . info . gprs

+ cfun -> va_list_gpr_size , GP_ARG_NUM_REG ) ;


<s> rtx tmp ; tmp = gen_rtx_PLUS ( word_mode , hard_frame_pointer_rtx , TARGET_64BIT ? GEN_INT ( - <NUM_LIT> ) : GEN_INT ( - <NUM_LIT> ) ) ; tmp = gen_rtx_MEM (


<s> for ( unsigned parti = <NUM_LIT> , parte = VTs . size ( ) ; parti != parte ; ++ parti ) { if ( VectorInfo [ parti ] & PVF_FIRST ) { assert ( VecIdx == - <NUM_LIT> && <STR_LIT> ) ; VecIdx = parti ; } if ( VectorInfo [ parti ] & PVF_LAST ) { unsigned NumElts = parti - VecIdx + <NUM_LIT> ; EVT EltVT = VTs [ parti ] ; EVT LoadVT = EltVT ; if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; else if ( EltVT == <STR_LIT> ) LoadVT = <STR_LIT> ; EVT VecVT = EVT :: getVectorVT ( F -> getContext ( ) , LoadVT , NumElts ) ; SDValue VecAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Arg , DAG . getConstant ( Offsets [ VecIdx ] , dl , PtrVT ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , ADDRESS_SPACE_PARAM ) ) ; SDValue P = DAG . getLoad ( VecVT , dl , Root , VecAddr , MachinePointerInfo ( srcValue ) , aggregateIsPacked , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; if ( P . getNode ( ) ) P . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , LoadVT , P , DAG . getIntPtrConstant ( j , dl ) ) ; if ( EltVT == <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; else if ( EltVT == <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; if ( Ins [ InsIdx ] . VT . isInteger ( ) && Ins [ InsIdx ] . VT . getSizeInBits ( ) > LoadVT . getSizeInBits ( ) ) { unsigned Extend = Ins [ InsIdx ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> ; Elt = DAG . getNode ( Extend , dl , Ins [ InsIdx ] . VT , Elt ) ; } InVals . push_back ( Elt ) ; } VecIdx = - <NUM_LIT> ; } ++ InsIdx ; } if ( VTs . size ( ) > <NUM_LIT> ) -- InsIdx ; continue ; } EVT ObjectVT = getValueType ( DL , Ty ) ; assert ( ObjectVT == Ins [ InsIdx ] . VT && <STR_LIT> ) ; SDValue Arg = getParamSymbol ( DAG , idx , PtrVT ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder (


<s> if ( domain ) { validDomains = getExecutionDomainCustom ( MI ) ; if ( validDomains ) return std :: make_pair ( domain , validDomains ) ; if ( lookup ( opcode , domain , ReplaceableInstrs ) ) { validDomains = <NUM_LIT> ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( lookup ( opcode , domain , ReplaceableInstrsFP ) ) { validDomains = <NUM_LIT> ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ; validDomains = <NUM_LIT> ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = <NUM_LIT> ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512 ( opcode , domain ,


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( reg ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> )


<s> GTI != E ; ++ GTI ) { NumIndices -- ; const Value * Idx = GTI . getOperand ( ) ; Type * IdxTy = GTI . getIndexedType ( ) ; if ( NextIndex == ARRAY_REF || NextIndex == STRUCT_REF ) { unsigned NodeOpcode = NextIndex == STRUCT_REF ? <STR_LIT> : <STR_LIT> ; IsInChain |= <NUM_LIT> << <NUM_LIT> ; IsInChain |= ( <NUM_LIT> == NumIndices ) << <NUM_LIT> ; SDValue InChainUse = DAG . getConstant ( IsInChain , dl , <STR_LIT> ) ; IsInChain &= ~ <NUM_LIT> ; SDValue Ops [ ] = { SDB -> getRoot ( ) , N , SDB -> getValue ( Idx ) , InChainUse } ; if ( isa < CompositeType > ( IdxTy ) ) { EVT VTs [ ] = { <STR_LIT> , <STR_LIT> } ; N = DAG . getNode ( NodeOpcode , dl , VTs , Ops ) ; SDNodeFlags Flags = N . getNode ( ) -> getFlags ( ) ; Flags . setIsComposite ( true ) ; N . getNode ( ) -> setFlags ( Flags ) ; } else { EVT IdxVT = getValueType ( DL , IdxTy ) ; EVT VTs [ ] = { IdxVT


<s> HOST_WIDE_INT const_double_to_hwint ( rtx x ) { HOST_WIDE_INT val ; REAL_VALUE_TYPE rv ; if ( GET_MODE ( x ) == SFmode ) { REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_SINGLE ( rv , val ) ; } else if ( GET_MODE ( x ) == DFmode ) { long l [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_DOUBLE ( rv


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; bool isAdd = MO1 . getImm (


<s> } case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> )


<s> static bool isInv2Pi ( const APFloat & APF ) { static const APFloat KF16 ( APFloat :: IEEEhalf ( ) , APInt ( <NUM_LIT> ,


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Memory , Ctx ) ; Op -> Mem . BaseRegNum = BaseReg ; Op -> Mem . OffsetRegNum = OffsetReg ; Op -> Mem . OffsetImm = nullptr ; Op -> Mem . ExtType = ExtType ; Op -> Mem . ShiftVal = ShiftVal ; Op -> Mem . ExplicitShift = ExplicitShift ; Op -> Mem . Mode = RegisterOffset ; Op -> StartLoc = S ; Op -> EndLoc


<s> builtin_mode_to_type [ SImode ] [ <NUM_LIT> ] = intSI_type_node ; builtin_mode_to_type [ SImode ] [ <NUM_LIT> ] = unsigned_intSI_type_node ; builtin_mode_to_type [ DImode ] [ <NUM_LIT> ] = intDI_type_node ; builtin_mode_to_type [ DImode ] [ <NUM_LIT> ] = unsigned_intDI_type_node ; builtin_mode_to_type [ TImode ] [ <NUM_LIT> ] = intTI_type_node ; builtin_mode_to_type [ TImode ] [ <NUM_LIT> ] = unsigned_intTI_type_node ; builtin_mode_to_type [ SFmode ] [ <NUM_LIT> ] = float_type_node ; builtin_mode_to_type [ DFmode ] [ <NUM_LIT> ] = double_type_node ; builtin_mode_to_type [ IFmode ] [ <NUM_LIT> ] = ibm128_float_type_node ; builtin_mode_to_type [ KFmode ] [ <NUM_LIT> ] = ieee128_float_type_node ; builtin_mode_to_type [ TFmode ] [ <NUM_LIT> ] = long_double_type_node ; builtin_mode_to_type [ DDmode ] [ <NUM_LIT> ] = dfloat64_type_node ; builtin_mode_to_type [ TDmode ] [ <NUM_LIT> ] = dfloat128_type_node ; builtin_mode_to_type [ V1TImode ] [ <NUM_LIT> ] = V1TI_type_node ; builtin_mode_to_type [ V1TImode ] [ <NUM_LIT> ] = unsigned_V1TI_type_node ; builtin_mode_to_type [ V2DImode ] [ <NUM_LIT> ] = V2DI_type_node ; builtin_mode_to_type [ V2DImode ] [ <NUM_LIT> ] = unsigned_V2DI_type_node ; builtin_mode_to_type [ V2DFmode ] [ <NUM_LIT> ] = V2DF_type_node ; builtin_mode_to_type [ V4SImode ] [ <NUM_LIT> ] = V4SI_type_node ; builtin_mode_to_type [ V4SImode ] [ <NUM_LIT> ] = unsigned_V4SI_type_node ; builtin_mode_to_type [ V4SFmode ] [ <NUM_LIT> ] = V4SF_type_node ; builtin_mode_to_type [ V8HImode ] [ <NUM_LIT> ] = V8HI_type_node ; builtin_mode_to_type [ V8HImode ] [ <NUM_LIT> ] = unsigned_V8HI_type_node ; builtin_mode_to_type [ V16QImode ] [ <NUM_LIT> ] = V16QI_type_node ; builtin_mode_to_type [ V16QImode ] [ <NUM_LIT> ] = unsigned_V16QI_type_node ; tdecl = add_builtin_type ( <STR_LIT> , bool_char_type_node ) ; TYPE_NAME ( bool_char_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , bool_short_type_node ) ; TYPE_NAME ( bool_short_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , bool_int_type_node ) ; TYPE_NAME ( bool_int_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , pixel_type_node ) ; TYPE_NAME ( pixel_type_node ) = tdecl ; bool_V16QI_type_node = rs6000_vector_type ( <STR_LIT> , bool_char_type_node , <NUM_LIT> ) ; bool_V8HI_type_node = rs6000_vector_type ( <STR_LIT> , bool_short_type_node , <NUM_LIT> ) ; bool_V4SI_type_node = rs6000_vector_type ( <STR_LIT> , bool_int_type_node , <NUM_LIT> ) ; bool_V2DI_type_node = rs6000_vector_type ( TARGET_POWERPC64 ? <STR_LIT> : <STR_LIT> , bool_long_long_type_node , <NUM_LIT> ) ; pixel_V8HI_type_node = rs6000_vector_type ( <STR_LIT> , pixel_type_node , <NUM_LIT> ) ; if ( TARGET_EXTRA_BUILTINS ) altivec_init_builtins ( ) ; if ( TARGET_HTM ) htm_init_builtins ( ) ; if ( TARGET_EXTRA_BUILTINS ) rs6000_common_init_builtins ( ) ; ftype = builtin_function_type ( DFmode , DFmode , DFmode , VOIDmode , RS6000_BUILTIN_RECIP , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RECIP ) ; ftype = builtin_function_type ( SFmode , SFmode , SFmode , VOIDmode , RS6000_BUILTIN_RECIPF , <STR_LIT> ) ; def_builtin ( <STR_LIT> , ftype , RS6000_BUILTIN_RECIPF ) ; ftype = builtin_function_type ( DFmode , DFmode , VOIDmode , VOIDmode ,


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New


<s> if ( stack_realign_fp ) return ( ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) || ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ) ; else return to == STACK_POINTER_REGNUM ? ! frame_pointer_needed :


<s> unsigned int i ; state = data ; if ( REG_P ( x ) ) for ( i = <NUM_LIT> ; i < HARD_REGNO_NREGS

( REGNO ( x ) , GET_MODE ( x ) ) ; i ++ ) {


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder < > & Builder ) const { if ( ! Subtarget -> hasV7Ops ( ) ) return ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoSSE2 ( ) { if ( ! Subtarget . hasSSE2 ( ) ) return ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v4s32 = LLT ::


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset ,


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; bool IsTU = IsMasked || ! isAllUndef ( Regs ) ; if ( IsTU ) { SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; } CurOp += NF ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands , true ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsTU , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; bool TailAgnostic = true ; bool MaskAgnostic = false ; if ( IsMasked ) { uint64_t Policy = Node -> getConstantOperandVal ( Node -> getNumOperands ( ) - <NUM_LIT> ) ; TailAgnostic = Policy & <STR_LIT> ; MaskAgnostic = Policy & <STR_LIT> ; } unsigned VType = <ISA_LIT>VType :: encodeVTYPE ( LMUL , SEW , TailAgnostic , MaskAgnostic ) ; SDValue VTypeOp = CurDAG -> getTargetConstant ( VType , DL , XLenVT ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , VTypeOp , SDValue ( Load ,


<s> DebugLoc DL = Inst -> getDebugLoc ( ) ; MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( AMDGPU :: V_BCNT_U32_B32_e64 ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & AMDGPU :: SGPR_32RegClass ; unsigned MidReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; unsigned ResultReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , AMDGPU :: sub0 ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , AMDGPU :: sub0 , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , AMDGPU :: sub1 , SrcSubRC ) ; MachineInstr * First = BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . addOperand ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; MachineInstr * Second = BuildMI ( MBB , MII , DL , InstDesc ,

ResultReg ) . addOperand ( SrcRegSub1 ) . addReg ( MidReg ) ;


<s> EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( std :: move ( Cs ) ) ; } llvm :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B . front ( ) ) ; } ) ; int Parity = <NUM_LIT>


<s> auto I32Ty = GR -> getOrCreate<ISA_LIT>IntegerType ( <NUM_LIT> , MIRBuilder ) ; Register scopeReg ; auto scope = Scope :: Workgroup ; if ( OrigArgs . size ( ) >= <NUM_LIT> ) { assert ( OrigArgs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; auto clScope = static_cast < CLMemScope > ( getIConstVal ( OrigArgs [ <NUM_LIT> ] , MRI ) ) ; scope = get<ISA_LIT>Scope ( clScope ) ; if ( clScope == static_cast < unsigned > ( scope ) ) scopeReg = OrigArgs [ <NUM_LIT> ] ; } if ( ! scopeReg . isValid ( ) ) scopeReg = GR -> buildConstantInt ( scope , MIRBuilder , I32Ty ) ; auto ptr = OrigArgs [ <NUM_LIT> ] ; auto scSem = getMemSemanticsForStorageClass ( GR -> getPointerStorageClass ( ptr ) ) ; Register memSemReg ; unsigned memSem = MemorySemantics :: None ; if ( OrigArgs . size ( ) >= <NUM_LIT> ) { auto memOrd = static_cast < CLMemOrder > ( getIConstVal ( OrigArgs [ <NUM_LIT> ] , MRI ) ) ; memSem = get<ISA_LIT>MemSemantics ( memOrd ) | scSem ; if ( memOrd == memSem ) memSemReg = OrigArgs [ <NUM_LIT> ] ; } if ( ! memSemReg . isValid ( ) ) memSemReg = GR -> buildConstantInt ( memSem , MIRBuilder , I32Ty ) ; auto MIB = MIRBuilder . buildInstr ( RMWOpcode ) . addDef ( resVReg ) . addUse ( GR -> get<ISA_LIT>TypeID ( resType ) ) . addUse ( ptr ) . addUse ( scopeReg ) . addUse ( memSemReg ) . addUse ( OrigArgs [ <NUM_LIT> ] ) ; return constrainRegOperands (


<s> unsigned CC = StringSwitch < unsigned > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> if ( instance . any_type_float_p ( ) ) return flags | CP_READ_FPCR | CP_RAISE_FP_EXCEPTIONS ; return


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const { return <STR_LIT>


<s> SPExcessSpillOffset = SinglePathFIs .


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo


<s> if ( GET_CODE ( value ) == CONST && GET_CODE ( XEXP ( value , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( value , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_LTREL_OFFSET && XVECLEN ( XEXP ( value , <NUM_LIT> ) , <NUM_LIT> ) == <NUM_LIT> ) { value = gen_rtx_MINUS ( Pmode , XVECEXP ( XEXP ( value , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) , gen_rtx_LABEL_REF ( VOIDmode , pool -> label ) ) ; value = gen_rtx_CONST ( VOIDmode , value ) ; } insn = emit_label_after ( c -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; value = gen_rtx_UNSPEC_VOLATILE ( constant_modes [ i ] , gen_rtvec ( <NUM_LIT> , value ) , UNSPECV_POOL_ENTRY ) ; insn = emit_insn_after ( value , insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; } insn = emit_insn_after ( gen_pool_align ( GEN_INT ( <NUM_LIT> ) ) , insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; for ( c = pool -> execute ; c ; c = c -> next ) { insn = emit_label_after ( c -> label , insn ) ; INSN_ADDRESSES_NEW ( insn , - <NUM_LIT> ) ; insn = emit_insn_after ( s390_execute_target ( c -> value


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode (


<s> MachineBasicBlock * MBB = & * It ; for ( auto & Terminator : MBB -> terminators ( ) ) { if ( ! isWhileLoopStart ( Terminator ) ) continue ; MachineBasicBlock * WLSTarget = getWhileLoopStartTargetBB ( Terminator ) ; if ( WLSTarget == Predecessor ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> <STR_LIT> <STR_LIT> ) ; return false ; } } } moveBasicBlock ( Predecessor , LoopExit ) ; return true


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT>


<s> default : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI .


<s> unsigned getFramePointerSaveOffset ( ) const


<s> bool <ISA_LIT>PartialReduction :: trySADPattern ( BinaryOperator * BO ) { if ( ! ST -> hasSSE2 ( ) ) return false ; if ( ! cast < VectorType > ( BO -> getType ( ) ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; bool Changed


<s> if ( TRI -> getCommonSubClass ( RC , & AMDGPU :: SGPR_32RegClass ) ) { unsigned Lane = MFI -> SpillTracker . reserveLanes ( MRI , MBB . getParent ( ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_WRITELANE_B32 ) , MFI -> SpillTracker . LaneVGPR ) . addReg ( SrcReg , KillFlag ) . addImm ( Lane ) ; MFI -> SpillTracker . addSpilledReg ( FrameIndex , MFI -> SpillTracker . LaneVGPR , Lane ) ; } else if ( RI . isSGPRClass ( RC ) ) { unsigned NumSubRegs = RC -> getSize ( ) / <NUM_LIT> ; unsigned FirstLane = MFI -> SpillTracker . reserveLanes ( MRI , MBB . getParent ( ) , NumSubRegs ) ; MFI -> SpillTracker . addSpilledReg ( FrameIndex , MFI -> SpillTracker . LaneVGPR , FirstLane ) ; unsigned Opcode ; switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S64_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S128_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S256_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S512_SAVE ; break ; default : llvm_unreachable (


<s> SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( NewInt ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) || TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) .


<s> if ( Kind == Immediate ) Inst . addOperand ( MCOperand :: CreateImm (


<s> return ( __m512i ) __builtin_ia32_broadcasti32x8_512_mask ( ( __v8si ) __A , ( __v16si ) _mm512_setzero_si512 ( )


<s> switch ( Imm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT>


<s> output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> ,


<s> if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost


<s> static ScheduleDAGInstrs * createVLIWMachineSched (


<s> <ISA_LIT>ISelAddressMode AM ; AM . GV = GA -> getGlobal ( ) ; AM . Disp += GA -> getOffset ( ) ; AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , N . getValueType ( ) ) ; AM . SymbolFlags = GA -> getTargetFlags ( ) ; if ( N . getValueType ( ) == <STR_LIT> ) { AM . Scale = <NUM_LIT> ; AM . IndexReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } else { AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT>


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> , * MBB . getParent ( ) ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { unsigned opcode = ( DestReg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( opcode ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT>


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = RS . scavengeRegister ( RI . getBoolRC ( ) ,


<s> bool <ISA_LIT>InstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const { return true


<s> bool ExtraLoadRequired = Subtarget . GVRequiresExtraLoad ( GV , getTargetMachine ( ) , false ) ; SDValue Result ; if ( ! IsPic && ! ExtraLoadRequired ) { Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : case V2HQmode : case V2UHQmode : case V2HAmode


<s> } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_SPESpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_SPE4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex =


<s> if ( LoopInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ShiftCounter = BuildMI ( * PrologBlock , InsertPos , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , v_reg ) . addReg ( LoopCounter ) . addImm ( LoopInst -> getOperand ( <NUM_LIT> ) . getImm ( ) * Counter ) . addImm ( <ISA_LIT>II :: OpType :: INT32 ) . addImm ( <NUM_LIT> ) . addReg ( LoopCounter , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { ShiftCounter = BuildMI ( * PrologBlock , InsertPos , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , v_reg ) . addReg ( LoopCounter ) . addReg ( LoopInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <ISA_LIT>II :: OpType :: INT32 ) . addImm ( <NUM_LIT> ) . addReg ( LoopCounter , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } unsigned ThreadCounter = ExecThreads [ i ] . VRegMap [ LoopCounter ] ; LLVM_DEBUG ( ExecThreads [ i ] . Dloop . push_back ( ShiftCounter ) ) ; if ( ThreadCounter != LoopCounter ) { MachineInstr * OriginalCounterInst = MRI -> getVRegDef ( ThreadCounter ) ; OriginalCounterInst -> removeFromParent ( ) ; } Register PrologCounter = InitialCounters [ i ] ; unsigned PhiCounter = MRI -> createVirtualRegister ( PrologBlock -> getParent ( ) -> getSubtarget ( ) . getTargetLowering ( ) -> getRegClassFor ( <STR_LIT> ) ) ; MachineInstr * Phi = BuildMI ( * Header , Header -> begin ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: PHI ) , PhiCounter ) . addReg ( PrologCounter ) . addMBB ( Prolog ) . addReg ( v_reg ) . addMBB ( Latch ) ; if ( PrologCounter . isPhysical (


<s> const char * tilepro_output_cbranch_with_opcode ( rtx_insn * insn , rtx * operands , const char * opcode , const char * rev_opcode , int regop , bool netreg_p ) { const char * branch_if_false ; rtx taken , not_taken ; bool is_simple_branch ; gcc_assert ( LABEL_P ( operands [ <NUM_LIT> ] ) ) ; is_simple_branch = true ; if ( INSN_ADDRESSES_SET_P ( ) ) { int from_addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int to_addr = INSN_ADDRESSES ( INSN_UID ( operands [ <NUM_LIT> ] ) ) ; int delta = to_addr - from_addr ; is_simple_branch = IN_RANGE ( delta , -


<s> } else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( CurDAG -> getEntryNode ( ) ) , <STR_LIT> , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; return


<s> unsigned SuccSize = StartMBB -> succ_size ( ) ; if ( SuccSize > <NUM_LIT> ) { MachineBasicBlock * StartMBBSucc = * ( StartMBB -> succ_begin ( ) ) ; for ( MachineBasicBlock :: succ_iterator PI = EndMBB -> succ_begin ( ) , E = EndMBB -> succ_end ( ) ; PI != E ; ++ PI ) { if ( ( * PI ) != StartMBB && ! ( ( * PI ) == StartMBBSucc && StartMBB != EndMBB && SuccSize == <NUM_LIT> ) ) { Succs . insert ( std :: pair < MachineBasicBlock * , MachineBasicBlock * > ( EndMBB , * PI ) ) ; } } } for ( MachineBasicBlock :: pred_iterator PI = StartMBB -> pred_begin ( ) , E = StartMBB -> pred_end ( ) ; PI != E ; ++ PI


<s> texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; * code = _TEXASRU_FAILURE_CODE ( texasru ) ; return _TEXASRU_ABORT (


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : assert ( <NUM_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } llvm_unreachable ( <STR_LIT> ) ; } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> ) O << 'f' ; if ( Mask & <NUM_LIT>


<s> if ( get<ISA_LIT>Subtarget ( ) . os16 ( ) ) addPass (

create<ISA_LIT>Os16Pass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> if ( R == Match_Success ) break ; } switch ( Result ) { default : break ; case Match_Success : if ( ! validateInstruction ( Inst , IDLoc , Operands ) ) { return true ; } Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ]


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF )


<s> uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( Binary <= UINT8_MAX ) { OS << uint8_t ( Binary ) ; } else { assert ( Binary <= UINT16_MAX && <STR_LIT> ) ; OS << uint8_t ( Binary >> <NUM_LIT> ) << uint8_t ( Binary ) ; } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) encodeULEB128 ( MI . getNumOperands ( ) - <NUM_LIT> , OS ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { } else if ( MO . isImm ( ) ) { if ( i < Desc . getNumOperands ( ) ) { assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ i ] ; if ( Info . OperandType == <STR_LIT> ) { encodeSLEB128 ( int32_t ( MO . getImm ( ) ) , OS ) ; } else if ( Info . OperandType == <STR_LIT> ) { encodeSLEB128 ( int64_t ( MO . getImm ( ) ) , OS ) ; } else if ( Info . OperandType == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( Info . OperandType == <STR_LIT> ) { OS << uint8_t ( MO . getImm ( ) ) ; } else { encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else { assert ( Desc . TSFlags == ( <STR_LIT> |


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int RegNo = - <NUM_LIT> ; RegNo = tryParseRegister ( Mnemonic ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <STR_LIT> ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ( val , ( STI .


<s> store_pos = - <NUM_LIT> ; load_pos = - <NUM_LIT> ; for ( i = nready - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { rtx_insn * insn = ready [ i ] ; if ( USEFUL_INSN_P ( insn ) ) switch ( get_attr_type ( insn ) ) { case TYPE_STORE : if ( store_pos == - <NUM_LIT> ) store_pos = i ; break ; case


<s> int i , n_elt ; rtvec v ; machine_mode scalar_mode ; switch ( mode ) { case E_V64QImode : case E_V32QImode : case E_V16QImode : case E_V32HImode : case E_V16HImode : case E_V8HImode : case E_V16SImode : case E_V8SImode : case E_V4SImode : case E_V8DImode : case E_V4DImode : case E_V2DImode : gcc_assert ( vect ) ; case E_V16SFmode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , <NUM_LIT> ) = value ; for ( i = <NUM_LIT> ; i < n_elt ; ++ i ) RTVEC_ELT ( v , i ) =

vect ? value : CONST0_RTX ( scalar_mode ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Val ) const { if ( Val < <NUM_LIT> ) Val = - Val ; return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> || ( Val & ~


<s> } Node * finger1 = ( b1 != NULL ) ? b1 : b2 ; Node * finger2 = b2 ; while ( finger1 -> num != finger2 -> num ) { while ( finger1 -> num < finger2 -> num ) finger1 = finger1 -> ipdom ; while ( finger2 -> num < finger1 -> num ) finger2 = finger2


<s> static inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Flags = <NUM_LIT> ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ; return MIB . addFrameIndex ( FI ) . addImm ( Offset ) . addReg (


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv16qi


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT ,


<s> return __aarch64_vdupq_lane_u32 ( __a ,


<s> int loongarch_regno_mode_ok_for_base_p ( int regno , machine_mode mode ATTRIBUTE_UNUSED , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM ||

regno == FRAME_POINTER_REGNUM ) return true ;


<s> SDLoc dl ( N ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Op . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || DstVT == <STR_LIT> ) && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( DstVT ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl ,


<s> case UNSPEC_TPOFF : x = XVECEXP ( inner , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_MACHOPIC_OFFSET : return legitimate_pic_address_disp_p ( x ) ; default : return false ; } case SYMBOL_REF


<s> __builtin_sh_media_STHI_L ( ( char * ) p + s


<s> Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move (


<s> BB -> setAlignment ( AlignConstantIslands ? MaxAlign : Align ( <NUM_LIT> ) ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( Log2 ( MaxAlign ) + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= Log2 ( MaxAlign ) ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } LLVM_DEBUG ( BB -> dump (


<s> unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i !=


<s> static SDValue joinDwords ( SelectionDAG & DAG , SDLoc DL , SDValue Op0 , SDValue Op1 ) { if ( Op0 . isUndef ( ) && Op1 . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; if ( Op0 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; else if ( Op1 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; else { Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> ,


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const


<s> unsigned <ISA_LIT>MCCodeEmitter :: getAdrpLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; unsigned Modifier = <ISA_LIT>MCExpr :: VK_AARCH64_None ; if ( const <ISA_LIT>MCExpr * Expr = dyn_cast < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) Modifier = Expr -> getKind ( ) ; unsigned FixupKind = <NUM_LIT> ; switch ( Modifier ) { case <ISA_LIT>MCExpr :: VK_AARCH64_None : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_GOT : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr


<s> bool mayNeedRelaxation ( const MCInst & Inst


<s> } msp430x = xisa ; break ; } if ( i < <NUM_LIT> ) { if ( msp430_hwmult_type == AUTO ) { if ( msp430_warn_mcu ) { if ( target_cpu == NULL ) warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; else warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; } msp430_hwmult_type = NONE ; } else if ( target_cpu == NULL ) { if ( msp430_warn_mcu ) warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; msp430x = false ; } else if ( msp430_warn_mcu ) warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; } } if ( target_cpu == NULL && target_mcu == NULL && msp430_hwmult_type == F5SERIES ) msp430x = true ; if ( TARGET_LARGE && ! msp430x ) error ( <STR_LIT> ) ; if ( msp430_code_region == UPPER && ! msp430x


<s> State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT


<s> opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ; opts -> x_aarch64_branch_protection_string = ptr -> x_aarch64_branch_protection_string ; if ( opts -> x_aarch64_branch_protection_string ) { aarch64_parse_branch_protection ( opts ->

x_aarch64_branch_protection_string , NULL ) ;


<s> void \ sdata_section ( ) \ { \ if ( in_section != in_sdata ) \ { \ fprintf ( asm_out_file , <STR_LIT> , SDATA_SECTION_ASM_OP )


<s> MVT IndexVT = <STR_LIT> ; unsigned IndexLen = <NUM_LIT> ; if ( Op . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { IndexVT = <STR_LIT> ; IndexLen = <NUM_LIT> ; } SDValue V1Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V1 ) ; SDValue V2Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V2 ) ; SDValue Shuffle ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { if ( IndexLen == <NUM_LIT> ) V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V1Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , V1Cst , DAG . getNode ( <STR_LIT> , DL , IndexVT , ArrayRef < SDValue > ( TBLMask . data ( ) , IndexLen ) ) ) ; } else { if ( IndexLen == <NUM_LIT> ) { V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V2Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , V1Cst , DAG . getNode ( <STR_LIT> , DL , IndexVT , ArrayRef < SDValue > ( TBLMask . data ( ) , IndexLen ) ) ) ; } else { Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , V1Cst , V2Cst , DAG . getNode ( <STR_LIT> , DL , IndexVT , ArrayRef < SDValue > ( TBLMask . data ( ) , IndexLen ) ) ) ; } } return DAG . getNode ( <STR_LIT> , DL , Op . getValueType


<s> assert ( HasVSrc || N -> getNumOperands ( ) == <NUM_LIT> ) ; SDLoc SL ( N ) ; SDValue BaseOffset = N -> getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) ; int ImmOffset = <NUM_LIT> ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( BaseOffset ) ) { glueCopyToM0 ( N , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; ImmOffset = ConstOffset -> getZExtValue ( ) ; } else { if ( CurDAG -> isBaseWithConstantOffset ( BaseOffset ) ) { ImmOffset = BaseOffset . getConstantOperandVal ( <NUM_LIT> ) ; BaseOffset = BaseOffset . getOperand ( <NUM_LIT> ) ; } SDNode * SGPROffset = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , BaseOffset ) ; SDNode * M0Base = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , SDValue ( SGPROffset , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; glueCopyToM0 ( N , SDValue ( M0Base , <NUM_LIT> ) ) ; } SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue OffsetField = CurDAG -> getTargetConstant ( ImmOffset , SL , <STR_LIT> ) ; SDValue GDS = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT>


<s> insertAfterLoad ( MachineBasicBlock & MBB , const MachineBasicBlock :: iterator I ) { MachineBasicBlock :: iterator J = TII -> nextNonPseudo ( MBB , I ) ; if ( J != MBB . end ( ) && hasDefUseDep ( & * I , & * J ) ) { TII -> insertNoop ( MBB , std :: next ( I ) ) ; ++ InsertedLoadNOPs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * J ) ; return true ; } else if ( J != MBB . end ( ) ) { ++ SkippedLoadNOPs ; return false ; } if ( J == MBB . end ( ) ) { if ( MBB . succ_empty ( ) ) return false ; bool inserted = false ; for ( MachineBasicBlock :: succ_iterator SMBB = MBB . succ_begin ( ) ; SMBB != MBB . succ_end ( ) ; ++ SMBB ) { auto FirstMI = ( * SMBB ) -> begin ( ) ; if ( ( * SMBB ) -> empty ( ) || hasDefUseDep ( & * I , & * FirstMI ) ) { TII -> insertNoop ( * * SMBB , ( * SMBB ) -> begin ( ) ) ; ++ InsertedLoadNOPs ; if ( ! inserted ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; inserted = true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * FirstMI ) ; } else { ++ SkippedLoadNOPs ; } } return inserted ; } return false


<s> IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getVectorElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 (


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ; case <STR_LIT> : adjust :: fixup_6_adiw ( Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: fixup_port5 ( Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: fixup_port6 ( Fixup , Value ,


<s> return parsePKHImm ( O , <STR_LIT> , <NUM_LIT>


<s> static unsigned createLaneVGPR ( MachineRegisterInfo & MRI ) { return MRI . createVirtualRegister ( & AMDGPU :: VReg_32RegClass


<s> static void addDefsToList ( const MachineInstr & MI , SmallVectorImpl < const MachineOperand * > & Defs ) { for ( const MachineOperand & Def : MI


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; SmallVector < int , <NUM_LIT> > RepeatedMask ; bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1


<s> Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc


<s> if ( Reg ) { assert ( Reg == <STR_LIT> && <STR_LIT> ) ; O << 's'


<s> else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; if ( A -> getSize ( ) == <NUM_LIT> ) return getCommonSubClass ( A , & <STR_LIT> ) ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) return A ; break ; case <STR_LIT> : if ( B == &


<s> unsigned Opc = MI . getOpcode ( ) ; int CommutedOpcode = commuteOpcode ( Opc ) ; if ( CommutedOpcode == - <NUM_LIT> ) return nullptr ; assert ( <STR_LIT> ( Opc , <STR_LIT> :: src0 ) == static_cast < int > ( Src0Idx ) && <STR_LIT> ( Opc , <STR_LIT> :: src1 ) == static_cast < int > ( Src1Idx ) && <STR_LIT> ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; MachineOperand & Src1 = MI . getOperand ( Src1Idx ) ; MachineInstr * CommutedMI = nullptr ; if ( Src0 . isReg ( ) && Src1 . isReg ( ) ) { if ( isOperandLegal ( MI , Src1Idx , & Src0 ) ) { CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , Src0Idx , Src1Idx ) ; } } else if ( Src0 . isReg ( ) && ! Src1 . isReg ( ) ) { CommutedMI = swapRegAndNonRegOperand ( MI , Src0 , Src1 ) ; } else if ( ! Src0 . isReg ( ) && Src1 . isReg ( ) ) { if ( isOperandLegal ( MI , Src1Idx , & Src0 ) )

CommutedMI = swapRegAndNonRegOperand ( MI , Src1 , Src0 ) ;


<s>
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
if
(
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
XINT
(
note
,
<NUM_LIT>
)
>=
REG_BR_PROB_BASE
/
<NUM_LIT>
)
^
far
)
<STR_LIT>
:
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
*
p
=
p
<
string
+
<NUM_LIT>
'\t'
:
' '
;
p
++
;
*
p
++
=
'%'
;
*
p
++
=
'0'
+
reg
;
*
p
++
=
','
;
*
p
++
=
' '
;
if
(
far
)
{
int
veryfar
=
<NUM_LIT>
,
delta
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
{
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
<NUM_LIT>
&&
delta
<
<NUM_LIT>
)
veryfar
=
<NUM_LIT>
;
}
strcpy
(
p
,
<STR_LIT>
)
;
if
(
annul
||
!
final_sequence
)
p
[
<NUM_LIT>
]
=
'6'
;
p
+=
<NUM_LIT>
;
if
(
veryfar
)
{
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
else
{
strcpy
(
p
,
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
}
}
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
+
label
;
*
p
++
=
'%'
;
*
p
++
=


<s> return getLinkageSize ( LP64 , isMacho ) + getMinCallArgumentsSize


<s> void EmitBasicBlockEnd ( const MachineBasicBlock & MBB


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Or = BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * Or ) ; MI . eraseFromParent


<s> bool <ISA_LIT>RegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { assert ( Offset <= INT_MAX && <STR_LIT>


<s> int _U_Qfuneq ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_UNORD | QCMP_EQ


<s> if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; print_rtl_single ( dump_file , cbranch_insn ) ; } unsigned int dist = <NUM_LIT> ; for ( rtx_insn * i = next_nonnote_insn ( cbranch_insn ) ; i != NULL && dist < max_dist ; i = next_nonnote_insn ( i ) ) { const unsigned int i_len = get_attr_length ( i ) ; dist += i_len ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( i ) , i_len , dist ) ; if ( rtx_code_label * l = dyn_cast < rtx_code_label * > ( i ) ) { if ( l == cbranch_insn -> jump_target ( ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , dist ) ; return dist ; } break ; } } if ( dump_file ) fprintf ( dump_file


<s> unsigned InUseReg = MI . getOperand ( OpNo ) . getReg ( ) ; MI . getOperand ( OpNo ) . ChangeToImmediate ( Imm ) ; if ( empty ( MI . implicit_operands ( ) ) ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >= <NUM_LIT> ) { MachineOperand & MO = MI .


<s> for ( auto F = M . begin ( ) , E = M . end ( ) ; F != E ; ++ F ) { MachineFunction * MF = MMI -> getMachineFunction ( * F ) ; if ( ! MF ) continue ; for ( MachineBasicBlock & MBB : * MF ) for ( MachineInstr & MI : MBB ) { if ( MAI . getSkipEmission ( & MI ) ) continue ; if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; SwitchRegs . insert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && SwitchRegs . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Register CmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * CBr = MI . getNextNode ( ) ; assert ( CBr && CBr -> getOpcode ( ) == <STR_LIT> && CBr -> getOperand ( <NUM_LIT> ) . isReg ( ) && CBr -> getOperand ( <NUM_LIT> ) . getReg ( ) == CmpReg ) ; MAI . setSkipEmission ( & MI ) ; MAI . setSkipEmission


<s> } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } EmitAndCountInstruction ( LEA ) ; if ( needsPadding ) { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT>


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_tune == PROCESSOR_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; } return false


<s> bool hasSMulHi ( ) const { return HasSMulHi


<s> if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] ) ; } if ( Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; else if ( Operands [ <NUM_LIT> ] . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! IsConstVectorInRange ( Operands [ i ] , <NUM_LIT> , <NUM_LIT> ) ) continue ; std :: swap ( Operands [ i ] , Operands [ <NUM_LIT> ] ) ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) if ( Operands [ j ] . getOpcode ( ) != <STR_LIT> || Operands [ j ] . getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) ; } return SDValue (


<s> default : break ; case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; OW -> Write8 ( <NUM_LIT> ) ; break ; } return true


<s> if ( mode == SImode ) icode = CODE_FOR_fetchadd_rel_si ; else icode = CODE_FOR_fetchadd_rel_di ; break ; default : gcc_unreachable ( ) ; } emit_insn ( GEN_FCN ( icode ) ( old_dst , mem , val ) ) ; if ( new_dst ) { new_reg = expand_simple_binop ( mode , PLUS , old_dst , val , new_dst , true , OPTAB_WIDEN ) ; if ( new_reg != new_dst ) emit_move_insn ( new_dst , new_reg ) ; } return ; } gcc_assert ( is_mm_relaxed ( model ) || is_mm_release ( model ) || MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg = cmp_reg ; if ( code == NOT ) { new_reg = expand_simple_binop ( DImode , AND , new_reg , val , NULL_RTX


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> FunctionPass * create<ISA_LIT>Combiner (


<s> bool isLegalToVectorizeLoadChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const { return Alignment >=


<s> void <ISA_LIT>AsmPrinter :: EmitJal ( const MCSubtargetInfo & STI , MCSymbol * Symbol ) { MCInst I ; I . setOpcode


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE

| ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;


<s> if ( Reg ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } return false


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Element = RawMask [ i ] ; uint64_t Index = Element & <NUM_LIT> ; uint64_t PermuteOp = ( Element >> <NUM_LIT> )


<s> if ( WlsInstr ) return WlsInstr ; if ( Predecessor -> pred_size ( ) == <NUM_LIT> ) return findWLSInBlock ( * Predecessor -> pred_begin ( ) ) ; return


<s> static MachineBasicBlock :: iterator getEarliestInsertPos ( MachineBasicBlock * MBB , const SmallPtrSet < const MachineInstr * , <NUM_LIT> > & BeforeSet , const SmallPtrSet < const MachineInstr * , <NUM_LIT> > & AfterSet ) { auto InsertPos = MBB -> end ( ) ; while ( InsertPos != MBB -> begin ( ) ) { if ( BeforeSet . count ( & * std :: prev ( InsertPos ) ) ) { for ( auto Pos = InsertPos , E = MBB -> begin ( ) ; Pos != E ; -- Pos ) assert ( ! AfterSet . count ( & * std :: prev ( Pos ) ) ) ; break ; } -- InsertPos


<s> LLT PtrType = getLLTForType ( * PtrTy , DL ) ; unsigned DstReg = MRI . createGenericVirtualRegister ( PtrType ) ; unsigned KernArgSegmentPtr = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned KernArgSegmentVReg = MRI . getLiveInVirtReg ( KernArgSegmentPtr ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( LLT :: scalar (


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry


<s> if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N ) ) return TII -> isInlineConstant ( C -> getAPIntValue ( ) ) ; if ( const ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N ) ) return TII

-> isInlineConstant ( C -> getValueAPF ( ) . bitcastToAPInt ( ) ) ;


<s> DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; Shuffle = SrcVT != MaskVT ? unsigned ( <STR_LIT> ) : unsigned ( <STR_LIT> ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ,


<s> case UNEQ : emit_insn ( gen_vec_cmpuneqv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case LTGT : emit_insn ( gen_vec_cmpltgtv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case ORDERED : emit_insn ( gen_vec_orderedv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; case UNORDERED : emit_insn ( gen_vec_unorderedv2df ( target , cmp_op1 , cmp_op2 ) ) ; return ; default : break ; } } else { switch ( cond ) { case NE : cond = EQ ; neg_p = true ; break ; case GE : cond = GT ; neg_p = true ; swap_p = true ; break ; case GEU : cond = GTU ; neg_p = true ; swap_p = true ; break ; case LE : cond = GT ; neg_p = true ; break ; case LEU : cond = GTU ; neg_p = true ; break ; case LT : cond = GT ; swap_p = true ; break ; case LTU : cond = GTU ; swap_p


<s> assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small && <STR_LIT> ) ; SDValue Hi = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; unsigned char LoFlags = <STR_LIT> | <STR_LIT> ; SDValue Lo = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , LoFlags ) ; SDValue PoolAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , DL , PtrVT ) ) ; return GlobalAddr ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ; } else { SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL

, PtrVT , <NUM_LIT> , OpFlags | <STR_LIT> ) ;


<s> } } else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } } next_arg_reg = FUNCTION_ARG ( args_so_far , VOIDmode , void_type_node , <NUM_LIT> ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx insn , pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; insn = emit_insn ( pattern ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_MAYBE_DEAD , NULL_RTX , REG_NOTES ( insn ) ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx_MEM ( gpr_mode , ptr ) , gen_rtx_REG (


<s> MachineInstr * BranchMI = getLoopendBlockBranchInstr ( ExitingMBB ) ; assert ( BranchMI && isCondBranch ( BranchMI ) ) ; DebugLoc DL = BranchMI -> getDebugLoc ( ) ; MachineBasicBlock * TrueBranch = getTrueBranch ( BranchMI ) ; MachineBasicBlock :: iterator I = BranchMI ; if ( TrueBranch != LandMBB )


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { MI -> setDesc ( get ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> addOperand ( MachineOperand :: CreateImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( Pred [ <NUM_LIT> ] . getReg ( ) , false ) ) ; return true ; } int PIdx = MI -> findFirstPredOperandIdx ( ) ; if ( PIdx != -


<s> case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerXALUO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_STORE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return lowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op


<s> rtx loongarch_prefetch_cookie ( rtx write , rtx locality ) { if ( INTVAL ( locality ) <= <NUM_LIT> ) return GEN_INT ( INTVAL ( write ) + <NUM_LIT> ) ; if ( INTVAL ( locality )


<s> else CPUName = <STR_LIT> ; } InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment ( )


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: ParseMemoryOperandV15 ( OperandVector & Operands


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; if ( Op . getValueType ( ) == <STR_LIT> ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getSetCC ( dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , CC ) ) ; } return SDValue ( ) ; } return Op ; } if ( SDValue V = lowerCmpEqZeroToCtlzSrl ( Op , DAG ) ) return V ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> )


<s> const LLT LoadTy = MRI . getType ( DstReg ) ; unsigned LoadSize = LoadTy . getSizeInBits ( ) ; const unsigned MaxNonSmrdLoadSize = <NUM_LIT> ; if ( LoadSize <= MaxNonSmrdLoadSize ) return false ; SmallVector < unsigned , <NUM_LIT> > DefRegs ( OpdMapper . getVRegs ( <NUM_LIT> ) ) ; SmallVector < unsigned , <NUM_LIT> > SrcRegs ( OpdMapper . getVRegs ( <NUM_LIT> ) ) ; if ( SrcRegs . empty ( ) ) return false ; assert ( LoadSize % MaxNonSmrdLoadSize == <NUM_LIT> ) ; MachineInstr * RepairInst = getOtherVRegDef ( MRI , DstReg , MI ) ; Register BasePtrReg = SrcRegs [ <NUM_LIT> ] ; LLT PtrTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MRI . setType ( BasePtrReg , PtrTy ) ; MachineIRBuilder B ( MI ) ; unsigned SplitElts = MaxNonSmrdLoadSize / LoadTy . getScalarType ( ) . getSizeInBits ( ) ; const LLT LoadSplitTy = LLT :: vector ( SplitElts , LoadTy . getScalarType ( ) ) ; ApplyRegBankMapping O ( MRI , & <STR_LIT> ) ; GISelObserverWrapper Observer ( & O ) ; B . setChangeObserver ( Observer ) ; LegalizerHelper Helper ( B . getMF ( ) , Observer , B ) ; if ( Helper . fewerElementsVector ( MI , <NUM_LIT> , LoadSplitTy ) != LegalizerHelper :: Legalized )


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target


<s> FunctionPass * llvm :: createAnnotationsInferencePass ( ) { return new AnnotationsInference


<s> assert ( Op . isImm ( ) && <STR_LIT> ) ; switch ( Op . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O <<


<s> bool hasMed3_16 ( ) const { return getGeneration (


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> static char buf [ <NUM_LIT> ] ; sprintf ( buf , <STR_LIT> ,


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else instantiateCondBranch ( MBB , DL , TBB , Cond ) ; return <NUM_LIT> ; } instantiateCondBranch ( MBB , DL , TBB , Cond ) ; BuildMI ( & MBB , DL , get (


<s> EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD ,


<s> bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv ::


<s> <ISA_LIT>ompactFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>ompactFunctionInfo > ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex (


<s> const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = MEMORY_REG_IMM ; Op -> Mem . BaseReg = BaseReg ; Op -> Mem . AluOp = AluOp ; Op -> Mem .


<s> unsigned <ISA_LIT>AsmParser :: parseCondCodeString ( StringRef Cond ) { unsigned CC = StringSwitch < unsigned > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; return CC


<s> for ( auto & MI : MBB ) { if ( <STR_LIT> ( MI . getDesc ( ) . TSFlags ) < <NUM_LIT> ) continue ; const DILocation * DI = MI . getDebugLoc ( ) ; if ( ! DI ) { DI = ReferenceDI ; } Location L = diToLocation ( DI ) ; DenseSet < unsigned > & Set = Seen [ L ] ; const std :: pair < DenseSet < unsigned > :: iterator , bool > TryInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; if ( ! TryInsert . second ) { unsigned BF , DF , CI = <NUM_LIT> ; DILocation :: decodeDiscriminator ( DI -> getDiscriminator ( ) , BF , DF , CI ) ; Optional < unsigned > EncodedDiscriminator = DILocation :: encodeDiscriminator ( MemOpDiscriminators [ L ] + <NUM_LIT> , DF , CI ) ; if ( ! EncodedDiscriminator ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << DI -> getFilename ( ) << <STR_LIT> << DI -> getLine ( ) << <STR_LIT> << DI -> getColumn ( ) << <STR_LIT> ) ; continue ; } ++ MemOpDiscriminators [ L ] ; DI = DI -> cloneWithDiscriminator ( EncodedDiscriminator . getValue ( ) ) ; assert ( DI && <STR_LIT> ) ; updateDebugInfo ( & MI , DI ) ; Changed = true ; std :: pair < DenseSet < unsigned > :: iterator , bool > MustInsert = Set . insert ( DI -> getBaseDiscriminator ( ) ) ; ( void ) MustInsert ; assert ( MustInsert .


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( VT . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> if ( ByVal . NumRegs ) { const uint16_t * ArgRegs = CC . intArgRegs ( ) ; bool LeftoverBytes = ( ByVal . NumRegs * RegSize > ByValSize ) ; unsigned I = <NUM_LIT> ; for ( ; I < ByVal . NumRegs - LeftoverBytes ; ++ I , Offset += RegSize ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSize == Offset ) return ; if ( LeftoverBytes ) { assert ( ( ByValSize > Offset ) && ( ByValSize < Offset + RegSize ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = RegSize / <NUM_LIT> , TotalSizeLoaded = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalSizeLoaded ; else Shamt = ( RegSize - ( TotalSizeLoaded + LoadSize ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL ,


<s> case LT : return GE ; case GE : return LT ; case LE : return


<s> return ( to == HARD_FRAME_POINTER_REGNUM


<s> if ( NewFrom != From ) { CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; continue ; } if ( ( NewToMask & CombinedToMask ) . getBoolValue ( ) ) return SDValue ( ) ; if ( BitsProperlyConcatenate ( ToMask , NewToMask ) && BitsProperlyConcatenate ( FromMask , NewFromMask ) ) return V ; if ( BitsProperlyConcatenate ( NewToMask , ToMask ) && BitsProperlyConcatenate ( NewFromMask , FromMask ) ) return V ; CombinedToMask |= NewToMask ; V = V . getOperand ( <NUM_LIT> ) ; } return SDValue (


<s> default : return true ; case <STR_LIT> : case <STR_LIT> ... <STR_LIT>


<s> const int ReadM0WaitStates = <NUM_LIT> ; auto IsHazardFn = [ TII ] ( const MachineInstr & MI ) { return TII -> isSALU ( MI ) ; } ; return ReadM0WaitStates - getWaitStatesSinceDef ( <STR_LIT> , IsHazardFn , ReadM0WaitStates


<s> return isMem256 ( ) && isMemIndexReg ( <STR_LIT>


<s> printf ( <STR_LIT> , mcu_name [ i ] , i == n_mcus - <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( i && ! strcmp ( mcu_name [ i ] , mcu_name [ i - <NUM_LIT> ] ) ) { duplicate =


<s> if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat


<s> MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . CPol ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I ,


<s> SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Op = LD -> getBasePtr ( ) . getNode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> ) return false ; if ( <STR_LIT> ( LD ) ) { return false ; } } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Op = ST -> getBasePtr ( ) . getNode ( ) ; if ( <STR_LIT> ( ST ) ) { return false ; } } else { return false ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) { return false ; } if ( Op -> getOpcode ( ) != <STR_LIT> && Op -> getOpcode ( ) != <STR_LIT> ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC !=


<s> if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) ) return false ; return true


<s> std :: string FullFS = FS ; if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS =


<s> InlineAsmHelper ( LLVMContext & C_ , BasicBlock * BB_ ) : C ( C_ ) , BB (


<s> const <ISA_LIT>IntrinsicInfo * getIntrinsicInfo ( ) const


<s> int alpha_using_fp ( ) { alpha_sa_size ( )


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel (


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT .


<s> return ( * registered_functions ) [ code ] ->


<s> Deleter ( SelectionDAG & D , T & C ) : SelectionDAG :: DAGNodeDeletedListener ( D , [ & C ] ( SDNode * N , SDNode * E ) { C . erase (


<s> x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_HIGH ( GET_MODE ( x ) , x ) , x ) ; push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == HIGH ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return


<s> return ( __m512i ) __builtin_ia32_pmovsxbw512_mask ( ( __v32qi ) __A , ( __v32hi ) _mm512_setzero_hi ( )


<s> StringRef getPassName ( ) const override { return


<s> void <ISA_LIT>MCExpr :: PrintImpl ( raw_ostream


<s> } else { for ( MCRegister Reg : RC ) { if ( LiveRegs . available ( MRI , Reg ) ) return Reg ; } } if ( ! Unused ) report_fatal_error ( <STR_LIT> ) ; return MCRegister ( )


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; Subtarget = & F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F


<s> Contents += UppercaseString ( String ) ; Contents +=


<s> MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate (


<s> HOST_WIDE_INT locals_size = get_frame_size ( ) ; int regno ; HOST_WIDE_INT stack_space_to_deallocate = ( current_function_outgoing_args_size + current_function_pretend_args_size + locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; HOST_WIDE_INT offset = current_function_outgoing_args_size ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) stack_space_to_deallocate += <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_deallocate += <NUM_LIT> ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_deallocate += <NUM_LIT> ; if ( frame_pointer_needed ) stack_space_to_deallocate += <NUM_LIT> ; if ( ( stack_space_to_deallocate % <NUM_LIT> ) != <NUM_LIT> ) internal_error ( <STR_LIT> , stack_space_to_deallocate ) ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= <NUM_LIT> ; regno ++ ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) { if ( offset > <NUM_LIT> )


<s> tree arg0 ; enum machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_altivec_lvx_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_altivec_lvx_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_altivec_lvx_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_altivec_lvx_v4sf ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0

) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ;


<s> bool hasVDSP2E60F ( ) const { return HasVDSP2E60F


<s> if ( Offset0 % Size != <NUM_LIT> || Offset1 % Size != <NUM_LIT> ) return false ; if ( ! isUInt < <NUM_LIT> > ( Offset0 / Size ) || !

isUInt < <NUM_LIT> > ( Offset1 / Size ) ) return false ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( auto Reg : ReservedRegs ) Reserved . set (


<s> MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; dumpBBs ( ) ; ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) ) MadeChange = true ; verify ( )