<s> Register BitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NegBitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned LOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; unsigned CSOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigOldVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register CmpVal = MRI . createVirtualRegister ( RC ) ; Register SwapVal = MRI . createVirtualRegister ( RC ) ; Register StoreVal = MRI . createVirtualRegister ( RC ) ; Register RetryOldVal = MRI . createVirtualRegister ( RC ) ; Register RetryCmpVal = MRI . createVirtualRegister ( RC ) ; Register RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = <STR_LIT> ( MI , MBB ) ; MachineBasicBlock * LoopMBB = <STR_LIT> ( StartMBB ) ; MachineBasicBlock * SetMBB = <STR_LIT> ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( DoneMBB )


<s> if ( sh_cfun_interrupt_handler_p ( ) && ! df_regs_ever_live_p ( new_reg ) ) return false ; return


<s> const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ; if ( ! SuperRC ) return false ; DRC = RI . getMatchingSuperRegClass ( SuperRC , DRC , MO .


<s> const char * section ; if ( rx_small_data_limit == <NUM_LIT> ) return false ; if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( TREE_READONLY ( decl ) || DECL_COMMON ( decl ) ) return false ; section = DECL_SECTION_NAME ( decl ) ; if ( section ) return ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) || ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) ; size = int_size_in_bytes ( TREE_TYPE ( decl


<s> bool <ISA_LIT>TTIImpl :: isLegalNTStore ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < <NUM_LIT> || DataSize > <NUM_LIT> || ! isPowerOf2_32 ( DataSize )


<s> const TargetMachine & TM = getTargetMachine ( ) ; bool IsRO = isReadOnly ( GV ) ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) && ! Subtarget -> genExecuteOnly ( ) ) if ( SDValue V = promoteToConstantPool ( GV , DAG , PtrVT , dl ) ) return V ; if ( isPositionIndependent ( ) ) { bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG .


<s> unsigned regSize ( ) const { return IsO32 ?


<s> MCInst TmpInst ; TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; TmpInst . addOperand ( MCOperand :: createReg


<s> if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) != <NUM_LIT> ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } } Relocator :: DWord X = S + A ; X >>= <NUM_LIT> ; if ( helper_check_signed_overflow ( X , <NUM_LIT> ) ) return Relocator :: Overflow ; val = helper_insert_val_thumb_movw_movt_inst ( val , X ) ; * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) ) = val >> <NUM_LIT> ; * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) + <NUM_LIT> ) = val & <NUM_LIT> ; return Relocator ::


<s> bool <ISA_LIT>MemoryLegalizer :: expandAtomicFence ( const <ISA_LIT>MemOpInfo & MOI , MachineBasicBlock :: iterator & MI ) { assert ( MI -> getOpcode ( ) == <STR_LIT> ) ; AtomicPseudoMIs . push_back ( MI ) ; bool Changed = false ; if ( MOI . isAtomic ( ) ) { if ( MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: Release || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Changed |= CC -> insertRelease (

MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: BEFORE ) ;


<s> int n_bytes = GET_MODE_SIZE ( mode ) ; return ( n_bytes > <NUM_LIT> && ! AVR_HAVE_LPMX && avr_mem_flash_p (


<s> bool <ISA_LIT>AnnotateUniformValues :: isClobberedInFunction ( LoadInst * Load ) { const MemoryAccess * MA = MSSA -> getWalker ( ) ->


<s> MemoryAccess * MA = WorkList . pop_back_val ( ) ; if ( ! Visited . insert ( MA ) . second ) continue ; if ( MSSA -> isLiveOnEntryDef ( MA ) ) continue ; if ( MemoryDef * Def = dyn_cast < MemoryDef > ( MA ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Def -> getMemoryInst ( ) << '\n' ) ; if ( isReallyAClobber ( Load -> getPointerOperand ( ) , Def , AA


<s> addPass ( & PostRAHazardRecognizerID ) ; addPass ( create<ISA_LIT>InsertWaitsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( create<ISA_LIT>LowerControlFlowPass ( ) ,


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case


<s> if ( known_eq ( width , <NUM_LIT> ) ) switch ( mode ) { case E_DFmode : return V2DFmode ; case E_SFmode : return V4SFmode ; case E_HFmode : return V8HFmode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; case E_DImode : return V2DImode ; default : break ; } else switch ( mode ) { case E_SFmode : return V2SFmode ; case E_HFmode : return V4HFmode ; case E_SImode : return V2SImode ; case


<s> case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex (


<s> if ( rest == NULL ) return - <NUM_LIT> ; char * after ; unsigned fint = strtol ( rest + <NUM_LIT> , & after , <NUM_LIT> ) ; if ( after == rest + <NUM_LIT>


<s> assert ( Reg . isPhysical ( ) ) ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg


<s> return AllParams . find ( Param ) ->


<s> if ( STUses && ! isMask_32 ( STUses ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTUses = countTrailingOnes ( STUses ) ; if ( STDefs && ! isMask_32 ( STDefs ) ) { MI . emitError ( <STR_LIT> ) ; STDefs = NextPowerOf2 ( STDefs ) - <NUM_LIT> ; } unsigned NumSTDefs = countTrailingOnes ( STDefs ) ; if ( STClobbers && ! isMask_32 ( STDefs | STClobbers ) ) MI . emitError ( <STR_LIT> ) ; unsigned STPopped = STUses & ( STDefs | STClobbers ) ; if ( STPopped && ! isMask_32 ( STPopped ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTPopped = countTrailingOnes ( STPopped ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NumSTUses << <STR_LIT> << NumSTPopped << <STR_LIT> << NumSTDefs << <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I < E ; ++ I ) if ( FRegIdx . count ( I ) ) { assert ( ( <NUM_LIT> << getFPReg ( MI . getOperand ( I ) ) & STDefs ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned FPKills = ( ( <NUM_LIT> << NumFPRegs ) - <NUM_LIT> ) & ~ <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( Op . isUse ( ) && Op . isKill ( ) ) FPKills |= <NUM_LIT> << FPReg ; } FPKills &= ~ ( STDefs | STClobbers ) ; unsigned char STUsesArray [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumSTUses ; ++ I ) STUsesArray [ I ] = I ; shuffleStackTop ( STUsesArray , NumSTUses , Inst ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; dumpStack ( ) ; } ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( FRegIdx . count ( i ) ) Op


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new


<s> unsigned getTIDReg ( ) const { return


<s> if ( VT . isVector ( ) && VT . getVectorNumElements ( ) > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } SDValue Ret = AMDGPUTargetLowering :: LowerSTORE ( Op , DAG ) ; if ( Ret . getNode ( ) ) return Ret ; if ( VT . isVector ( ) && VT . getVectorNumElements ( ) >= <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( VT == <STR_LIT> ) return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ; return SDValue (


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rounded_size = arg . promoted_size_in_bytes ( ) ; if ( rounded_size & <NUM_LIT> ) rounded_size ++ ; ( * cum )


<s> inline int vec_any_nge ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgefp_p ( __CR6_LT_REV , a1 , a2


<s> unsigned Opcode = <STR_LIT> ; if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if (


<s> void addNEONi32vmovNegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = ~ CE -> getValue ( ) ; if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) |

( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> StackAlignment = <NUM_LIT> ; DarwinDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasPaired = false ; HasAltivec = false ; HasQPX = false ; HasVSX = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasLDBRX = false


<s> SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; MachineFunction & MF = DAG . getMachineFunction ( ) ; isTailCall = false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; const Function * F = nullptr ; if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; F = cast < Function > ( GV ) ; Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } if ( isVarArg ) { CCInfo . AnalyzeCallOperands ( Outs , ArgCC_<ISA_LIT>_Vararg ) ; } else { analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , Outs , ArgLocs , CCInfo ) ; } unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; unsigned AI , AE ; bool HasStackArgs = false ; for ( AI = <NUM_LIT> , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { CCValAssign & VA = ArgLocs [ AI ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ AI ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL ,


<s> return symbol [ <NUM_LIT> ] == '@' && symbol [ <NUM_LIT> ] == 'e' && symbol [ <NUM_LIT>


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Identifier : { StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , HasRelocationAddend , OS


<s> static DecodeStatus decodeU12ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> > (


<s> } else regno = - <NUM_LIT> ; if ( TARGET_VSX && GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! mode_supports_vmx_dform ( mode ) && ( ( ( rclass == GENERAL_REGS || rclass == BASE_REGS ) && ( regno >= <NUM_LIT> && ALTIVEC_REGNO_P ( regno ) ) ) || ( ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) ) ) return FLOAT_REGS ; if ( rclass == GENERAL_REGS || rclass == BASE_REGS || ( regno >= <NUM_LIT> && INT_REGNO_P ( regno ) ) ) return NO_REGS ; if ( rclass == VSX_REGS && ( regno == - <NUM_LIT> || VSX_REGNO_P ( regno ) ) ) return NO_REGS ; if ( ( regno == - <NUM_LIT> || FP_REGNO_P ( regno ) ) && ( rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS ) ) return ( mode != SDmode || lra_in_progress ) ? NO_REGS : GENERAL_REGS ; if ( ( regno == - <NUM_LIT> || ALTIVEC_REGNO_P ( regno ) ) && rclass == ALTIVEC_REGS ) return NO_REGS ; if ( ( rclass == CR_REGS || rclass == CR0_REGS ) && regno >= <NUM_LIT> && CR_REGNO_P ( regno ) ) return NO_REGS ; return


<s> assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; unsigned NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ; MIRBuilder . buildExtract ( NewRegs [ <NUM_LIT> ] , Arg . Reg , <NUM_LIT> ) ; MIRBuilder . buildExtract ( NewRegs [ <NUM_LIT> ] , Arg . Reg , <NUM_LIT> ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT>


<s> ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget -> useSoftFloat ( ) && ! ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue ( <NUM_LIT> ) ; return DAG . getLoad ( ArgVT , dl , Chain , VAARG , MachinePointerInfo ( ) , false


<s> if ( regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS ) return


<s> void BTFDebug :: visitFwdDeclType ( const DICompositeType * CTy


<s> unsigned getBytesToPopOnReturn ( ) const { return BytesToPopOnReturn


<s> bool <ISA_LIT>InstructionSelector :: selectG_EXTRACT ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; assert ( I . getOperand ( <NUM_LIT> ) . getImm ( ) % <NUM_LIT> == <NUM_LIT> ) ; unsigned SubReg = TRI . getSubRegFromChannel ( I . getOperand ( <NUM_LIT> ) .


<s> EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Len = DAG . getNode ( <STR_LIT> , DL , PtrVT , End ,


<s> static rtx mn10300_libcall_value ( machine_mode mode ,


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoSSE2 ( ) { if ( ! Subtarget . hasSSE2 ( ) ) return ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT v16s8 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s64 , v2s64 } ) LegacyInfo . setAction ( { BinOp , Ty } , LegacyLegalizeActions :: Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) LegacyInfo . setAction ( { BinOp , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_MUL , v8s16 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPEXT , s64 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPEXT , <NUM_LIT> , s32 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPTRUNC , s32 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_FPTRUNC , <NUM_LIT> , s64 } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { TargetOpcode :: G_FCONSTANT , s64 } , LegacyLegalizeActions :: Legal ) ; for ( const auto & Ty : { v16s8 , v32s8 , v8s16 , v16s16 , v4s32 , v8s32 , v2s64 , v4s64 } ) { LegacyInfo . setAction ( { G_CONCAT_VECTORS , Ty } , LegacyLegalizeActions :: Legal ) ; LegacyInfo . setAction ( { G_UNMERGE_VALUES , <NUM_LIT> ,


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: ParseImmediate ( const MCExpr * & ExprVal ) { if ( getLexer ( ) . is ( AsmToken :: Colon ) ) { <ISA_LIT>MCExpr :: VariantKind RefKind ; OperandMatchResultTy ResTy = ParseRelocPrefix ( RefKind ) ; if ( ResTy != MatchOperand_Success ) return ResTy ; const MCExpr *


<s> if ( HasInt256 ) { SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( VT . is128BitVector ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> getBranchTarget7OpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO


<s> static inline bool s390_preserve_gpr_arg_p ( int regno ) { return s390_preserve_gpr_arg_in_range_p ( regno , regno


<s> } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; } StringRef ErrMsg


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Rsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; SOffset = CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr .


<s> } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection )


<s> return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , vec_splat ( ( vec_uchar16


<s> SDValue ByteIdx = convertToByteIndex ( IdxV , ElemTy , DAG ) ; SDValue ExWord = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { VecV , ByteIdx } ) ; if ( ElemTy == <STR_LIT> ) return ExWord ; SDValue SubIdx = getIndexInWord32 ( IdxV , ElemTy , DAG ) ; SDValue ExVec = DAG . getBitcast ( tyVector ( ty ( ExWord ) , ElemTy ) , ExWord ) ; return extractVector ( ExVec , SubIdx , dl , ElemTy


<s> void <ISA_LIT>InstructionSelector :: composePtr ( MachineIRBuilder & Builder , Register Dst , Register Lo , Register Hi ) { auto RegSeq = Builder . buildInstr ( <STR_LIT> ) . addDef ( Dst ) . addUse ( Lo ) . addImm ( <STR_LIT> ) . addUse ( Hi ) . addImm ( <STR_LIT> ) ; constrainGenericOp ( * RegSeq


<s> bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB << <STR_LIT> ) ; std :: map < unsigned , Chain * > ActiveChains ; std :: set < Chain * > AllChains ; unsigned Idx = <NUM_LIT> ; for ( auto & MI : MBB ) scanInstruction ( & MI , Idx ++ , ActiveChains , AllChains ) ; DEBUG ( dbgs ( ) << <STR_LIT> << AllChains . size ( ) << <STR_LIT> ) ; EquivalenceClasses < Chain * > EC ; for ( auto * I : AllChains ) EC . insert ( I ) ; for ( auto * I : AllChains ) { for ( auto * J : AllChains ) { if ( I != J && I -> rangeOverlapsWith ( J ) ) EC . unionSets ( I , J ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( Cs ) ; } std :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B . front ( ) ) ; } ) ; int Parity = <NUM_LIT> ; for ( auto & I : V ) Changed |= colorChainSet ( I , MBB , Parity ) ; for ( auto * C : AllChains ) delete C ; return Changed


<s> bool isToken ( ) const override { return Kind ==


<s> else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; else { rtx sum = XEXP ( op , <NUM_LIT>


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd


<s> case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , false , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , false , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , true , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , true , true ,


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( )

|| MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> __o = __builtin_aarch64_ld4di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o


<s> void DecodeScalarMoveMask ( MVT VT , bool IsLoad , SmallVectorImpl < int > & Mask ) { unsigned NumElts = VT . getVectorNumElements ( ) ; Mask . push_back (


<s> function_expander :: function_expander ( const function_instance & instance , tree fndecl_in , tree exp_in , rtx target_in ) : function_call_info ( EXPR_LOCATION ( exp_in ) , instance , fndecl_in ) , exp

( exp_in ) , target ( target_in ) , opno ( <NUM_LIT> ) {


<s> switch ( s390_tune ) { case PROCESSOR_2827_ZEC12 : if ( get_attr_zEC12_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_zEC12_expanded ( insn ) ) mask |= S390_SCHED_ATTR_MASK_EXPANDED ; if ( get_attr_zEC12_endgroup ( insn ) ) mask |= S390_SCHED_ATTR_MASK_ENDGROUP ; if ( get_attr_zEC12_groupalone ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPALONE ; break ; case PROCESSOR_2964_Z13 : if ( get_attr_z13_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_z13_expanded ( insn ) ) mask |= S390_SCHED_ATTR_MASK_EXPANDED ; if ( get_attr_z13_endgroup ( insn ) ) mask |= S390_SCHED_ATTR_MASK_ENDGROUP ; if ( get_attr_z13_groupalone ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPALONE ; if ( get_attr_z13_groupoftwo ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPOFTWO ; break ; case PROCESSOR_3906_Z14 : if ( get_attr_z14_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_z14_expanded ( insn ) ) mask |=


<s> unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , DL , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT>


<s> bool hasNullExportTarget ( ) const { return !


<s> DAG ( <NUM_LIT> ) , Available ( ID , Name + <STR_LIT> ) , Pending ( ID << ConvergingVLIWScheduler :: LogMaxQID , Name + <STR_LIT> ) , CheckPending ( false ) , HazardRec ( <NUM_LIT>

) , ResourceModel ( <NUM_LIT> ) , CurrCycle ( <NUM_LIT> ) , IssueCount ( <NUM_LIT> ) , MinReadyCycle ( UINT_MAX ) , MaxMinLatency ( <NUM_LIT> ) {


<s> return false ; } if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function & Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func . getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( * Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset =


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY_TO_REGCLASS ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; SrcReg = TmpReg ; } unsigned DestReg = createResultReg ( & <STR_LIT> ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) if ( IsSigned ) Opc


<s> VPTBlock . advanceVPTState ( ) ; } const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate ( ) ) { if ( CC != <STR_LIT> && ! <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , SoftFail ) ; I -> setImm ( CC ) ; ++


<s> bool atLeastM68060 ( ) const { return SubtargetKind >= M60


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups ) & <NUM_LIT> ) | RegBits ; if ( isSVR4ABI ( ) && is64BitMode ( ) ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; else Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind )


<s> bool CantUseFP = hasStackRealignment ( MF ) ; return CantUseFP && CantUseSP ( MFI )


<s> } Opc = isThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder CallMIB = BuildMI ( MF , DebugLoc ( ) , get ( Opc ) ) ; if ( isThumb ) CallMIB . add ( predOps ( <STR_LIT> ) ) ; CallMIB . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ; if ( C . CallConstructionID == MachineOutlinerRegSave ) { unsigned Reg = findRegisterToSaveLRTo ( C ) ; assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; if ( ! MBB . isLiveIn ( <STR_LIT> ) ) MBB . addLiveIn ( <STR_LIT>


<s> return ( pUpper16 & ~ <NUM_LIT> ) | ( ( pOffset >> <NUM_LIT> ) & <NUM_LIT> ) |


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : MCTargetStreamer ( S ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; MCA . setELFHeaderEFlags ( EFlags ) ; MCSection * AttributeSection = getStreamer ( ) . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ) ; Streamer . SwitchSection ( AttributeSection ) ; Streamer . emitInt8 ( <NUM_LIT>


<s> <STR_LIT> ShOpc = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> << <STR_LIT> ( ShOpc ) ; if ( ShOpc != <STR_LIT> ) O << <STR_LIT> << <STR_LIT> ( MO2


<s> void getAnalysisUsage ( AnalysisUsage & AU )


<s> const IntrinsicVector & getTrunc32_8 ( )


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI . eraseFromParent (


<s> ParseSubtargetFeatures ( CPU , FS ) ; return * this


<s> } Mod . setImm ( Mod . getImm ( ) & ~ <STR_LIT> ) ; Old . ChangeToImmediate ( Fold . ImmToFold & <NUM_LIT> ) ; return true ; } break ; default : break ; } } } if ( ( Fold . isImm ( ) || Fold . isFI ( ) || Fold . isGlobal ( ) ) && Fold . needsShrink ( ) ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; auto Liveness = MBB -> computeRegisterLiveness ( & TRI , <STR_LIT> , MI ) ; if ( Liveness != MachineBasicBlock :: LQR_Dead ) return false ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; int Op32 = Fold . getShrinkOpcode ( ) ; MachineOperand & Dst0 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Dst1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Dst0 . isDef ( ) && Dst1 . isDef ( ) ) ; bool HaveNonDbgCarryUse = ! MRI . use_nodbg_empty ( Dst1 . getReg ( ) ) ; const TargetRegisterClass * Dst0RC = MRI . getRegClass ( Dst0 . getReg ( ) ) ; unsigned NewReg0 = MRI . createVirtualRegister ( Dst0RC ) ; MachineInstr * Inst32 = TII . buildShrunkInst ( * MI , Op32 ) ; if ( HaveNonDbgCarryUse ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Dst1 . getReg ( ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } Dst0 . setReg ( NewReg0 ) ; for ( unsigned I = MI -> getNumOperands ( ) - <NUM_LIT> ; I > <NUM_LIT> ; -- I ) MI -> RemoveOperand ( I ) ; MI -> setDesc ( TII . get ( <STR_LIT> ) ) ; if ( Fold . isCommuted ( ) ) TII . commuteInstruction ( * Inst32 , false ) ; return true ; } assert ( ! Fold . needsShrink ( ) && <STR_LIT> ) ; if ( Fold . isImm ( ) ) { Old . ChangeToImmediate ( Fold . ImmToFold ) ; return true ; } if ( Fold . isGlobal ( ) ) { Old . ChangeToGA ( Fold . OpToFold -> getGlobal ( ) , Fold . OpToFold -> getOffset ( ) , Fold . OpToFold -> getTargetFlags ( ) ) ; return true ; } if ( Fold . isFI ( ) ) { Old . ChangeToFrameIndex ( Fold . FrameIndexToFold ) ; return true ; } MachineOperand * New = Fold . OpToFold ; Old . substVirtReg ( New -> getReg ( ) , New -> getSubReg ( ) , TRI ) ; Old . setIsUndef ( New -> isUndef (


<s> case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_BlockAddress


<s> if ( LoadInst * load = dyn_cast < LoadInst > ( II ) ) { if ( load -> hasOneUse ( ) == false ) continue ; if ( TD -> getTypeStoreSize ( load -> getType ( ) ) < MaxAggrCopySize ) continue ; User * use = * ( load -> use_begin ( ) ) ; if ( StoreInst * store = dyn_cast < StoreInst > ( use ) ) { if ( store -> getOperand ( <NUM_LIT> ) != load ) continue ; aggrLoads . push_back ( load ) ; } } else if ( MemTransferInst * intr = dyn_cast < MemTransferInst > ( II ) ) { Value * len = intr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemsets . push_back ( memsetintr ) ; } } else { aggrMemsets . push_back ( memsetintr ) ; } } } } if ( ( aggrLoads . size ( ) == <NUM_LIT> ) && ( aggrMemcpys . size ( ) == <NUM_LIT> ) && ( aggrMemsets . size ( ) == <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> , e = aggrLoads . size ( ) ; i != e ; ++ i ) { LoadInst * load = aggrLoads [ i ] ; StoreInst * store = dyn_cast < StoreInst > ( * load -> use_begin ( ) ) ; Value * srcAddr = load -> getOperand ( <NUM_LIT> ) ; Value * dstAddr = store -> getOperand


<s> static MCSymbolizer * create<ISA_LIT>Symbolizer ( const Triple & , LLVMOpInfoCallback , LLVMSymbolLookupCallback , void * DisInfo , MCContext * Ctx , std :: unique_ptr < MCRelocationInfo > && RelInfo ) { return new <ISA_LIT>Symbolizer ( * Ctx , std


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB .


<s> else FrameReg = TRI -> getFrameRegister ( MF ) ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; const <ISA_LIT>MachineFunctionInfo * MMFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; bool HasFP = hasFP ( MF ) ; if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI . getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI . getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! HasFP ) return Offset + StackSize ; Offset += SlotSize ; int TailCallReturnAddrDelta = MMFI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) Offset -= TailCallReturnAddrDelta ; } return Offset


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( Init ) ) { EVT VT = EVT :: getEVT ( CFP -> getType ( ) ) ; PointerType * PtrTy = PointerType :: get ( CFP -> getType ( ) , <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , DAG . getConstantFP ( * CFP , VT ) , InitPtr , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , false , false , TD -> getPrefTypeAlignment ( CFP -> getType ( ) ) ) ; } if ( StructType * ST = dyn_cast < StructType > ( InitTy ) ) { const StructLayout * SL = TD -> getStructLayout ( ST ) ; EVT PtrVT = InitPtr . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned I = <NUM_LIT> , N = ST -> getNumElements ( ) ; I != N ; ++ I ) { SDValue Offset = DAG . getConstant ( SL -> getElementOffset ( I ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , InitPtr , Offset ) ; Constant * Elt = Init -> getAggregateElement ( I ) ; Chains . push_back ( LowerConstantInitializer ( Elt , GV , Ptr , Chain , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( SequentialType * SeqTy = dyn_cast < SequentialType > ( InitTy ) ) { EVT PtrVT = InitPtr . getValueType ( ) ; unsigned NumElements ; if ( ArrayType * AT = dyn_cast < ArrayType > ( SeqTy ) ) NumElements = AT -> getNumElements ( ) ; else if ( VectorType * VT = dyn_cast < VectorType > ( SeqTy ) ) NumElements = VT -> getNumElements ( ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned EltSize = TD -> getTypeAllocSize ( SeqTy -> getElementType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) { SDValue Offset = DAG . getConstant ( i * EltSize , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , InitPtr , Offset ) ; Constant * Elt = Init -> getAggregateElement ( i ) ; Chains . push_back ( LowerConstantInitializer ( Elt , GV , Ptr , Chain , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( isa < UndefValue > ( Init ) ) { EVT VT = EVT :: getEVT ( InitTy ) ; PointerType * PtrTy = PointerType :: get ( InitTy , <STR_LIT>


<s> MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = VT . changeVectorElementType ( SVT ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } } if ( Opcode == InOpcode ) return DAG . getNode ( Opcode , SDLoc (

N ) , VT , In . getOperand ( <NUM_LIT> ) ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI


<s> switch ( N -> getOpcode ( ) ) { default : return ; case <STR_LIT> : Results . push_back ( LowerFPTOUINT ( N -> getOperand ( <NUM_LIT> )


<s> auto & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX512 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) { if ( Op . getOpcode ( ) == <STR_LIT> ) return getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; if ( Op . getOpcode ( ) == <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , R , ShiftAmt , DAG ) ; } if ( VT == <STR_LIT> ) { if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue SHL = getTargetVShiftByConstNode ( <STR_LIT> , dl , <STR_LIT> , R , ShiftAmt , DAG ) ; SHL = DAG . getNode ( <STR_LIT> , dl , VT , SHL ) ; SmallVector < SDValue , <NUM_LIT> > V ( <NUM_LIT> , DAG . getConstant ( uint8_t ( - <NUM_LIT> << ShiftAmt ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SHL , DAG . getNode ( <STR_LIT> , dl , VT , V ) ) ; } if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue SRL = getTargetVShiftByConstNode ( <STR_LIT> , dl , <STR_LIT> , R , ShiftAmt , DAG ) ; SRL = DAG . getNode ( <STR_LIT> , dl , VT , SRL ) ; SmallVector < SDValue , <NUM_LIT> > V ( <NUM_LIT> , DAG . getConstant ( uint8_t ( - <NUM_LIT> ) >> ShiftAmt , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SRL , DAG . getNode ( <STR_LIT> , dl , VT , V ) ) ; } if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ShiftAmt == <NUM_LIT> ) { SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Zeros , R ) ; } SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , R , Amt ) ; SmallVector < SDValue , <NUM_LIT> > V ( <NUM_LIT> , DAG . getConstant ( <NUM_LIT> >> ShiftAmt , <STR_LIT> ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , dl , VT , V ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , Mask ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res , Mask ) ; return Res


<s> SDValue Mask = MLN -> getMask ( ) ; SDValue Src0 = MLN -> getSrc0 ( ) ; EVT VT = Op . getValueType ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) || VT . isScalableVector ( ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; EVT DataVT , MaskVT ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : DataVT = <STR_LIT> ; MaskVT = <STR_LIT> ; break ; case <STR_LIT> : DataVT = <STR_LIT> ; MaskVT = <STR_LIT> ; break ; case <STR_LIT> : DataVT = <STR_LIT> ; MaskVT = <STR_LIT> ; break ; case <STR_LIT> : DataVT = <STR_LIT> ; MaskVT = <STR_LIT> ; break ; case <STR_LIT> : DataVT = <STR_LIT> ; MaskVT = <STR_LIT> ; break ; case <STR_LIT> : DataVT = <STR_LIT> ; MaskVT = <STR_LIT> ; break ; } <STR_LIT> PgPattern ; switch ( VT . getVectorNumElements ( ) ) { default : return SDValue ( ) ; case <NUM_LIT> : PgPattern = VL16 ; break ; case <NUM_LIT> : PgPattern = VL8 ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; return AM . Scale == <NUM_LIT> || AM . Scale


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) ,

DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS , * this ) {


<s> __arm_ldc2 ( const unsigned int __coproc , const unsigned int __CRd , const void * __p ) { return __builtin_arm_ldc2 ( __coproc , __CRd


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { llvm_unreachable ( <STR_LIT>


<s> MIB . setMF ( MF ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; processPHIs ( MF


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplat ( SDNode * N , APInt & Imm ) const { llvm_unreachable ( <STR_LIT> ) ; return false


<s> bool isu16_1Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , true


<s> case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case PROCESSOR_PPCE6500 : case PROCESSOR_TITAN : return <NUM_LIT> ; case PROCESSOR_PPC476 : case PROCESSOR_PPC604 : case PROCESSOR_PPC604e : case PROCESSOR_PPC620 : case PROCESSOR_PPC630 : return <NUM_LIT> ; case PROCESSOR_POWER4 : case PROCESSOR_POWER5 : case PROCESSOR_POWER6 : case PROCESSOR_POWER7 : return <NUM_LIT> ; case


<s> return new <ISA_LIT>FavorNonGenericAddrSpaces


<s> long int <ISA_LIT>ELFWriterInfo :: getDefaultAddendForRelTy ( unsigned RelTy , long int Modifier ) const { llvm_unreachable ( <STR_LIT> <STR_LIT> )


<s> switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI -> getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ; if ( Subtarget . isSwift ( ) ) { int UOps = <NUM_LIT> + NumRegs ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i

+= <NUM_LIT> ) OW -> Write32 ( <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( )


<s> MCInst MCI ; MCInstLowering . Lower ( MI , MCI ) ; <ISA_LIT>InstPrinter PIP ( * OutContext . getAsmInfo ( ) , * TM . getInstrInfo ( ) , * TM . getRegisterInfo ( ) ) ; PIP . printOperand ( & MCI , OpNo , O , ExtraCode ) ; return false


<s> inline static bool isLocalToFunc ( std :: string & FuncName , std :: string & VarName ) { if ( VarName . find ( FuncName + <STR_LIT> ) != std :: string :: npos || VarName . find ( FuncName + <STR_LIT> ) != std :: string :: npos ) return true ; return


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( )


<s> int nds32_can_use_return_insn ( void ) { if ( ! reload_completed ) return <NUM_LIT> ; return ( cfun -> machine -> naked_p && (

cfun -> machine -> va_args_size == <NUM_LIT> ) ) ;


<s> uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst


<s> case k_ShiftedImm : { unsigned Shift = getShiftedImmShift ( ) ; OS << <STR_LIT> ; getShiftedImmVal ( ) -> print ( OS ) ; OS << <STR_LIT> << <STR_LIT> ( Shift ) << <STR_LIT> ; break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( ( Mask & ( ~ Mask2 ) ) == <NUM_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue CombineBFI = FindBFIToCombineWith ( N ) ; if ( CombineBFI == SDValue ( ) ) return SDValue ( ) ; APInt ToMask1 , FromMask1 ; SDValue From1 = ParseBFI ( N , ToMask1 , FromMask1 ) ; APInt ToMask2 , FromMask2 ; SDValue From2 = ParseBFI ( CombineBFI . getNode ( ) , ToMask2 , FromMask2 ) ; assert ( From1 == From2 ) ; ( void ) From2 ; DCI . DAG . ReplaceAllUsesWith ( CombineBFI , CombineBFI . getOperand ( <NUM_LIT> ) ) ; APInt NewFromMask = FromMask1 | FromMask2 ; APInt NewToMask =


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> SmallVector < GlobalValue * , <NUM_LIT> > TmpVec ; collectUsedGlobalVariables ( M , TmpVec , true ) ; UsedList . insert ( TmpVec . begin ( ) , TmpVec . end ( ) ) ; TmpVec . clear ( ) ; collectUsedGlobalVariables ( M , TmpVec , false ) ; UsedList . insert ( TmpVec . begin ( ) , TmpVec . end ( ) ) ; return


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target (


<s> static bool BBIsJumpedOver ( MachineBasicBlock * MBB ) { if ( MBB -> pred_size ( ) != <NUM_LIT> || MBB -> succ_size


, ( VALUE ) ) ; \ assemble_name ( ( FILE ) , buf ) ; \ fputc ( '\n' , ( FILE ) ) ; \ }


<s> case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; mask = gen_int_mode ( <NUM_LIT> , SImode ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( <NUM_LIT> , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t2 , op1 , mask ) ) ; op0 = t1 ; op1 =


<s> else Opc = isSub ? getSUBriOpcode ( Is64BitStackPtr , Offset ) : getADDriOpcode ( Is64BitStackPtr , Offset ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = Is64BitTarget ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64BitTarget ) : getADDrrOpcode ( Is64BitTarget ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Offset = <NUM_LIT> ; continue ; } } uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64BitTarget ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = isSub ? ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) .

addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ;


<s> SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Match , DL ) ; Match = DAG . getNode ( BinOp , DL , Lo . getValueType ( ) , Lo , Hi ) ; NumElts /= <NUM_LIT> ; } EVT MovmskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; Movmsk = combineBitcastvxi1 ( DAG , MovmskVT , Match , DL , Subtarget ) ; } if ( ! Movmsk ) return SDValue ( ) ; Movmsk = DAG . getZExtOrTrunc ( Movmsk , DL , NumElts > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else { unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && Subtarget . hasAVX ( ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; if ( MatchSizeInBits == <NUM_LIT> && BitWidth < <NUM_LIT> && ! Subtarget . hasInt256 ( ) ) { SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Match , DL ) ; Match = DAG . getNode ( BinOp , DL , Lo . getValueType ( ) , Lo , Hi ) ; MatchSizeInBits = Match . getValueSizeInBits ( ) ; } MVT MaskSrcVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskSrcVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskSrcVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; SDValue BitcastLogicOp = DAG . getBitcast ( MaskSrcVT , Match ) ; Movmsk = getPMOVMSKB ( DL , BitcastLogicOp , DAG , Subtarget ) ; NumElts = MaskSrcVT . getVectorNumElements ( ) ; } assert ( ( NumElts <= <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; MVT CmpVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( BinOp == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , DL , CmpVT , Movmsk ) ; return DAG . getZExtOrTrunc ( Result , DL , ExtractVT ) ; } SDValue CmpC ; <STR_LIT> CondCode ; if ( BinOp == <STR_LIT> ) { CmpC = DAG . getConstant ( <NUM_LIT> , DL , CmpVT ) ; CondCode = <STR_LIT> :: SETNE ; } else { CmpC = DAG . getConstant ( APInt :: getLowBitsSet ( CmpVT . getSizeInBits ( ) , NumElts ) , DL , CmpVT ) ; CondCode = <STR_LIT> :: SETEQ ; } EVT SetccVT = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , CmpVT ) ; SDValue Setcc = DAG . getSetCC ( DL , SetccVT , Movmsk


<s> return ( TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && int_size_in_bytes ( valtype ) >=


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT>


<s> std :: stringstream SpillDirty ; MCGSiteUInt :: const_iterator it = WorstCaseSpillDirty . find ( j -> first ) ; assert ( it != WorstCaseSpillDirty . end ( ) ) ; if ( it == WorstCaseSpillDirty . end ( ) ) SpillDirty << <STR_LIT> ; else SpillDirty << it -> second ; MachineFunction * MF = j -> first -> getCaller (


<s> Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = LowerADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT>


<s> std :: ostringstream o ; o << getTagName ( PREFIX_SYMBOL ) << prefix <<


<s> for ( MCRegAliasIterator R ( <STR_LIT> , & MRI , true ) ; R . isValid ( ) ; ++ R ) { if ( * R == RegNo ) return isGFX9 ( ) || isGFX10 ( ) ; } for ( MCRegAliasIterator R ( <STR_LIT> , & MRI , true ) ; R . isValid ( ) ; ++ R ) { if ( * R == RegNo ) return hasSGPR104_SGPR105 ( ) ; } switch ( RegNo ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! isCI ( ) && ! is<ISA_LIT> ( ) && ! isVI ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! isGFX9 ( ) && ! isGFX10 ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! isCI ( ) && ! is<ISA_LIT> ( ) && ! isGFX10 ( ) && hasXNACK ( ) ; case <STR_LIT> : return isGFX10 ( ) ; default : break ; } if ( isCI ( ) ) return true ; if ( is<ISA_LIT> ( ) || isGFX10 ( ) ) { switch ( RegNo ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ; } } for ( MCRegAliasIterator R ( <STR_LIT> , &


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , dl , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) ,

MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> static Target The<ISA_LIT>Target ; return


<s> } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . padShortFunctions ( ) ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . LEAusesAG ( ) ) { addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; ShouldPrint = true


<s> __builtin_ia32_pmovswb256mem_mask ( ( __v16qi * ) __P , ( __v16hi )


<s> SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( DestVT . bitsGT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl


<s> bool <ISA_LIT>DAGToDAGISel :: isFlatStore ( const MemSDNode * N ) { if ( ! N -> writeMem ( )


<s> tree addr , t , type_size , rounded_size , valist_tmp ; unsigned HOST_WIDE_INT align , boundary ; bool indirect ; indirect = pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; if ( indirect ) type = build_pointer_type ( type ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = targetm . calls . function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; if ( boundary > align ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p )


<s> case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : return true ; case MEMMODEL_ACQUIRE : case MEMMODEL_CONSUME : case MEMMODEL_SYNC_ACQUIRE : case


<s> bool SelectAddrModeRO32 ( SDValue N , SDValue & Base , SDValue


<s> for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) Functions . insert ( & F ) ; } CallGraphUpdater CGUpdater ; BumpPtrAllocator Allocator ; <ISA_LIT>InformationCache InfoCache ( M , AG , Allocator , nullptr , * TM ) ; DenseSet < const char * > Allowed ( { & AAAMDAttributes :: ID , & AAAMDWorkGroupSize :: ID , & AACallEdges :: ID } ) ; Attributor A ( Functions , InfoCache , CGUpdater , & Allowed ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ; A . getOrCreateAAFor < AAAMDWorkGroupSize > ( IRPosition :: function ( F ) ) ; } } ChangeStatus Change = A . run ( ) ; return Change ==


<s> inline vector unsigned short vec_vsplth ( vector unsigned short a1


<s> } if ( lastpos < pos ) return <NUM_LIT> ; char * buf = ( char * ) malloc ( lastpos - pos + <NUM_LIT> ) ; memcpy ( buf , & linebuf [ pos ] , lastpos - pos +


<s> } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups ,


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FramePtr , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned OffHi = ( unsigned ) Offset >> <NUM_LIT> ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( FramePtr ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false


) , - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } printExpr ( Op . getExpr ( ) , O


<s> case V8SFmode : extract = gen_avx_vextractf128v8sf ; load_unaligned = gen_avx_loadups256 ; store_unaligned = gen_avx_storeups256 ; mode = V4SFmode ; break ; case V4DFmode : extract = gen_avx_vextractf128v4df ; load_unaligned = gen_avx_loadupd256 ; store_unaligned = gen_avx_storeupd256 ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_LOAD && optimize_insn_for_speed_p ( ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , <NUM_LIT> ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , <NUM_LIT> ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , op1 ) ) ; else emit_insn ( load_unaligned ( op0 , op1 ) ) ; } else if ( MEM_P ( op0 ) ) { if ( TARGET_AVX256_SPLIT_UNALIGNED_STORE && optimize_insn_for_speed_p ( ) ) { m = adjust_address ( op0


<s> static void msp430_print_operand_addr ( FILE * file , machine_mode , rtx addr ) { switch ( GET_CODE ( addr ) ) { case PLUS : msp430_print_operand_raw ( file , XEXP ( addr , <NUM_LIT> ) ) ; gcc_assert ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; return ; case REG


<s> } if ( MI . getOpcode ( ) == <STR_LIT> && ! Subtarget . hasV6Ops ( ) ) { if ( ! <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ! <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI


<s> MemoryLocation StoreLoc ( Ptr , AccessSize ) ; for ( auto * B : L -> blocks ( ) ) for ( auto & I : * B ) if ( Ignored . count ( & I ) == <NUM_LIT> && isModOrRefSet ( intersectModRef ( AA . getModRefInfo ( & I , StoreLoc )


<s> unsigned AS = findMemSDNode ( N ) -> getAddressSpace ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , AS , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } else { SDLoc DL ( N ) ; uint64_t ImmField ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( AS , IsSigned ) ; if ( IsSigned ) { ImmField = SignExtend64 ( COffsetVal , NumBits ) ; if ( static_cast < int64_t > ( COffsetVal ) > <NUM_LIT> ) { if ( static_cast < int64_t > ( ImmField ) < <NUM_LIT> ) { const uint64_t OffsetMask = maskTrailingOnes < uint64_t > ( NumBits - <NUM_LIT> ) ; ImmField = COffsetVal & OffsetMask ; } } } else { const uint64_t OffsetMask = maskTrailingOnes < uint64_t > ( NumBits ) ; ImmField = COffsetVal & OffsetMask ; } uint64_t RemainderOffset = COffsetVal - ImmField ; assert ( TII -> isLegalFLATOffset ( ImmField , AS , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; OffsetVal = ImmField ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT>


<s> return UseHVXQFloatOps && <ISA_LIT>HVXVersion >= <STR_LIT>


<s> Parms = <STR_LIT> ; break ; case FDSig : Parms = <STR_LIT> ; break ; case DSig : Parms = <STR_LIT> ; break ; case DDSig : Parms = <STR_LIT> ; break ; case DFSig : Parms = <STR_LIT> ; break ; case NoSig : Parms = <STR_LIT> ; break ; } OutStreamer . AddComment ( <STR_LIT> + Twine ( RetType ) + <STR_LIT> + Twine ( Symbol ) + <STR_LIT> + Twine ( Parms ) + <STR_LIT> ) ; OutStreamer . PushSection ( ) ; const MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer . SwitchSection ( M , nullptr ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbol * Stub = OutContext . GetOrCreateSymbol ( StringRef ( x ) ) ; TS . emitDirectiveEnt ( * Stub )


<s> assert ( <STR_LIT> ( ShiftOpnd ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftVal = <STR_LIT> ( ShiftOpnd ) ; assert ( ( ShiftVal == <NUM_LIT> || ShiftVal == <NUM_LIT> ) && <STR_LIT> ) ; auto Immediate = MI . getOperand ( OpIdx )


<s> static int thumb_far_jump_used_p ( void ) { rtx insn ; if ( cfun -> machine -> far_jump_used ) return <NUM_LIT> ; if ( ! ( ARM_DOUBLEWORD_ALIGN || reload_completed ) ) { if ( regs_ever_live [ ARG_POINTER_REGNUM ] ) cfun -> machine -> arg_pointer_live = <NUM_LIT> ; else if ( ! cfun -> machine -> arg_pointer_live ) return <NUM_LIT> ; } for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) ,

N -> getOperand ( <NUM_LIT> ) , NegVal ) ;


<s> Phi = cast < PHINode > ( Offs -> getOperand ( <NUM_LIT> ) ) ; OffsSecondOp = <NUM_LIT> ; } else if ( isa < PHINode > ( Offs -> getOperand ( <NUM_LIT> ) ) ) { Phi = cast < PHINode > ( Offs -> getOperand ( <NUM_LIT> ) ) ; OffsSecondOp = <NUM_LIT> ; } else { return false ; } } if ( Phi -> getParent ( ) != L -> getHeader ( ) ) return false ; BinaryOperator * IncInstruction ; Value * Start , * IncrementPerRound ; if ( ! matchSimpleRecurrence ( Phi , IncInstruction , Start , IncrementPerRound ) || IncInstruction -> getOpcode ( ) != Instruction :: Add ) return false ; int IncrementingBlock = Phi -> getIncomingValue ( <NUM_LIT> ) == IncInstruction ? <NUM_LIT> : <NUM_LIT> ; Value * OffsSecondOperand = Offs -> getOperand ( OffsSecondOp ) ; if ( IncrementPerRound -> getType ( ) != OffsSecondOperand -> getType ( ) || ! L -> isLoopInvariant ( OffsSecondOperand ) ) return false ; if ( ! isa < Constant > ( IncrementPerRound ) && ! ( isa < Instruction > ( IncrementPerRound ) && ! L -> contains ( cast < Instruction > ( IncrementPerRound ) ) ) ) return false ; PHINode * NewPhi ; if ( Phi -> getNumUses ( ) == <NUM_LIT> ) { if ( IncInstruction -> getNumUses ( ) != <NUM_LIT> ) { IncInstruction = BinaryOperator :: Create ( Instruction :: BinaryOps ( IncInstruction -> getOpcode ( ) ) , Phi , IncrementPerRound , <STR_LIT> , IncInstruction ) ; Phi -> setIncomingValue ( IncrementingBlock , IncInstruction ) ; } NewPhi = Phi ; } else { NewPhi = PHINode :: Create ( Phi -> getType ( ) , <NUM_LIT> , <STR_LIT> , Phi ) ; NewPhi -> addIncoming ( Phi -> getIncomingValue ( IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , Phi -> getIncomingBlock ( IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; IncInstruction = BinaryOperator :: Create ( Instruction :: BinaryOps ( IncInstruction -> getOpcode ( ) ) , NewPhi , IncrementPerRound , <STR_LIT> , IncInstruction ) ; NewPhi -> addIncoming ( IncInstruction , Phi -> getIncomingBlock ( IncrementingBlock ) ) ; IncrementingBlock = <NUM_LIT> ; } IRBuilder < > Builder ( BB -> getContext ( ) ) ; Builder . SetInsertPoint ( Phi ) ; Builder . SetCurrentDebugLocation ( Offs -> getDebugLoc ( ) ) ; switch ( Offs -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Or : pushOutAdd ( NewPhi , OffsSecondOperand , IncrementingBlock == <NUM_LIT> ?


<s> for ( MachineInstr * Instr : EarlyTermInstrs ) { if ( MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: <ISA_LIT>_GS ) earlyTerm ( * Instr , EarlyExitBlock ) ; Instr -> eraseFromParent ( ) ; } EarlyTermInstrs . clear ( ) ; MadeChange = true ; } if ( ! EpilogInstrs . empty ( ) ) { MachineBasicBlock * EmptyMBBAtEnd = nullptr ; assert ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( EpilogInstrs . size ( ) > <NUM_LIT> ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } for ( auto MI : EpilogInstrs ) { auto MBB = MI -> getParent ( ) ; if ( MBB == & MF . back ( ) && MI == & MBB -> back ( ) ) continue ; if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB -> addSuccessor ( EmptyMBBAtEnd ) ; MDT -> getBase ( ) . insertEdge ( MBB , EmptyMBBAtEnd ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( EmptyMBBAtEnd ) ; MI -> eraseFromParent ( ) ; MadeChange =


<s> TargetName = std :: string ( CPU . empty ( ) ? <STR_LIT> : CPU ) ; ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ; } return *


<s> R600ControlFlowFinalizer ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( nullptr ) , TRI ( nullptr ) , ST ( tm . getSubtarget < AMDGPUSubtarget > ( ) ) { const AMDGPUSubtarget & ST = tm . getSubtarget < AMDGPUSubtarget > ( ) ; MaxFetchInst = ST . getTexVTXClauseSize (


<s> case TLSModel :: InitialExec : Modifier = <STR_LIT> ; break ; case TLSModel :: LocalExec : Modifier = <STR_LIT> ; break ; } } else if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { Modifier = <STR_LIT> ; } } break ; case MachineOperand :: MO_BlockAddress : Name = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Name = MO . getSymbolName ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Name = GetCPISymbol ( MO . getIndex ( ) ) -> getName ( ) ; break ; } if ( PrintImmediatePrefix ) O


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = ( ( FlagSfiLoad && N -> getOpcode ( ) == <STR_LIT> ) || ( FlagSfiStore && N -> getOpcode ( ) == <STR_LIT> ) ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeImm5S4 ( SDValue N , SDValue & Base


<s> switch ( MI -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return NULL ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase


<s> char * newsym ; tree formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return NULL_TREE ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - <NUM_LIT> ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> unsigned <ISA_LIT>RegisterInfo :: getPtrSizedStackRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Register StackReg = getStackRegister ( ) ; if ( Subtarget . isTarget64BitILP32 ( ) ) StackReg

= get<ISA_LIT>SubSuperRegister ( StackReg , <NUM_LIT> ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static SDValue lowerShuffleAsShift ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { int Size = Mask . size ( ) ; assert ( Size == ( int ) VT . getVectorNumElements ( ) && <STR_LIT> ) ; MVT ShiftVT ; SDValue V = V1 ; unsigned Opcode ; int ShiftAmt = matchShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , <NUM_LIT> , Zeroable , Subtarget ) ; if ( ShiftAmt < <NUM_LIT> ) { ShiftAmt = matchShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , Size , Zeroable , Subtarget ) ; V = V2 ; } if ( ShiftAmt < <NUM_LIT> ) return


<s> unsigned getTIDReg ( ) const { return TIDReg


<s> if ( GET_CODE ( patt ) == SET ) { rtx lhs = XEXP ( patt , <NUM_LIT> ) ; if ( REG_P ( lhs ) && REGNO ( lhs ) == STATIC_CHAIN_REGNUM ) return true ; } } } return


<s> if ( I . getOpcode ( ) != TargetOpcode :: G_UADDE ) return false ; const unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned CarryOutReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Op1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CarryInReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; MachineInstr * Def = MRI . getVRegDef ( CarryInReg ) ; while ( Def -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) { CarryInReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Def = MRI . getVRegDef ( CarryInReg ) ; } unsigned Opcode ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_UADDE ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CarryInReg ) ; if ( ! RBI . constrainGenericRegister ( CarryInReg , <STR_LIT> , MRI ) ) return false ; Opcode = <STR_LIT> ; } else if ( auto val = getConstantVRegVal ( CarryInReg , MRI ) ) { if ( * val != <NUM_LIT> ) return false ; Opcode = <STR_LIT> ; } else return


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase &


<s> if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; to_add = reg ; } insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ) ; if ( frame_related_p ) { if ( REG_P ( to_add ) ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , orig_to_add ) ) ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> for ( const SDValue & V : Op -> op_values ( ) ) { if ( isa < CondCodeSDNode > ( V ) ) { Operands . push_back ( V ) ; continue ; } if ( const VTSDNode * VTNode = dyn_cast < VTSDNode > ( V ) ) { EVT VTArg = VTNode -> getVT ( ) . getVectorElementType ( ) ; EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( useSVEForFixedLengthVectorVT ( V . getValueType ( ) , OverrideNEON ) && <STR_LIT> ) ; Operands . push_back ( convertToScalableVector ( DAG , ContainerVT , V ) ) ; } if ( isMergePassthruOpcode ( NewOp ) ) Operands . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) &&


<s> bool from_partial_sve_p = from_sve_p && ( from_flags & VEC_PARTIAL ) ; bool to_partial_sve_p = to_sve_p && ( to_flags & VEC_PARTIAL ) ; bool from_pred_p = ( from_flags & VEC_SVE_PRED ) ; bool to_pred_p = ( to_flags & VEC_SVE_PRED ) ; if ( from_pred_p != to_pred_p ) return false ; if ( from_partial_sve_p != to_partial_sve_p ) return false ; if ( from_partial_sve_p && ( aarch64_sve_container_bits ( from ) != aarch64_sve_container_bits ( to ) || GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) ) return false ; if ( maybe_ne ( BITS_PER_SVE_VECTOR , <NUM_LIT> ) ) { if ( from_sve_p && ! to_sve_p && maybe_gt ( GET_MODE_BITSIZE (


<s> unsigned JTI = MO1 . getIndex ( ) ; MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; O << * JTISymbol << <STR_LIT> ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool ByteOffset = false , HalfWordOffset


<s> static LaneBitmask getUsedRegMask ( const MachineOperand & MO , const MachineRegisterInfo & MRI , const LiveIntervals & LIS ) { assert ( MO . isUse ( ) && MO . isReg ( ) && MO . getReg ( ) . isVirtual ( ) ) ; if ( auto SubReg = MO . getSubReg ( ) ) return MRI . getTargetRegisterInfo ( ) -> getSubRegIndexLaneMask ( SubReg ) ; auto MaxMask = MRI . getMaxLaneMaskForVReg ( MO . getReg (


<s> } if ( Opt == <STR_LIT> ) { ArchRegNames = true ; return true ; } return false


<s> switch ( AS ) { case <ISA_LIT>AS :: GLOBAL_ADDRESS : if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { return isLegalFlatAddressingMode ( AM ) ; } return isLegalMUBUFAddressingMode ( AM ) ; case <ISA_LIT>AS :: CONSTANT_ADDRESS : if ( AM . BaseOffs % <NUM_LIT> != <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( DL . getTypeStoreSize ( Ty ) < <NUM_LIT> ) return isLegalMUBUFAddressingMode ( AM ) ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM .


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { unsigned TCOpcode = ( RetOpcode == <STR_LIT> ) ? ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return requiresRegisterScavenging (


<s> unsigned regno2 ; poly_int64 offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; int offset_diff ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ; offset_diff = cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF -> getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PerformExtendFixups ( DT -> getRootNode (


<s> int mcore_arith_S_operand ( rtx op ) { if ( GET_CODE ( op ) == CONST_INT && CONST_OK_FOR_M

( ~ INTVAL ( op ) ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>LowerControlFlow :: If ( MachineInstr & MI ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Vcc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( Vcc ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) .


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & ,


<s> Ret , Chain } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( LoadNode -> getAddressSpace ( ) == <STR_LIT> && isa < GlobalVariable > ( GetUnderlyingObject ( LoadNode -> getMemOperand ( ) -> getValue ( ) , * getDataLayout ( ) ) ) ) { SDValue Ptr = DAG . getZExtOrTrunc ( LoadNode -> getBasePtr ( ) , DL , getPointerTy ( <STR_LIT> ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op -> getVTList ( ) , LoadNode -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } if ( LoadNode -> getAddressSpace ( ) == <STR_LIT> && VT . isVector ( ) ) { SDValue MergedValues [ <NUM_LIT> ] = { ScalarizeVectorLoad ( Op , DAG ) , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } int ConstantBlock = ConstantAddressBlock ( LoadNode -> getAddressSpace ( ) ) ; if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < ConstantExpr > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getNode ( <STR_LIT> , DL , NewVT , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <STR_LIT> , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result


<s> if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ; if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc ) return false ; DEBUG ( AM . dump (


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindCondCode , StartLoc , EndLoc ) ; Op -> CondCode


<s> unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; const DebugLoc & DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) . addImm ( <NUM_LIT> ) ; }


<s> void addGPRMM16AsmRegZeroOperands ( MCInst & Inst , unsigned


<s> SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDNode * R = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) ; SDValue M0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue M1 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * C = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , M0 , N ->


<s> break ; } case <STR_LIT> : { Register Src1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ptr = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Src1 ) ; unsigned Opc ; if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S8 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S16 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S32 ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , S64 ) || Ty == LLT :: fixed_vector ( <NUM_LIT> , P0 ) ) Opc = <STR_LIT> ; else if ( Ty == S64 || Ty == P0 ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SmallVector < Register , <NUM_LIT> > Regs = { Src1 , Src2 } ; Register Tuple = Ty . getSizeInBits ( ) == <NUM_LIT> ? createQTuple ( Regs , MIB ) : createDTuple ( Regs , MIB ) ; auto Store = MIB . buildInstr ( Opc , { } , { Tuple , Ptr } ) ; Store . cloneMemRefs ( I ) ; constrainSelectedInstRegOperands ( * Store , TII , TRI , RBI ) ; break ; } case <STR_LIT> : { Register DstDef = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstUse = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ValUse = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SizeUse = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SizeDef = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Memset = MIB . buildInstr ( <STR_LIT> , { DstDef , SizeDef


<s> SDValue <ISA_LIT>TargetLowering :: LowerGC_TRANSITION_END ( SDValue Op , SelectionDAG & DAG ) const { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Op . getOperand


<s> static bool mips_small_register_classes_for_mode_p ( machine_mode mode


<s> assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; unsigned OpNo = getOpIdxForMO ( MI , MO ) ; unsigned Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MCII . get ( MI . getOpcode ( ) ) , MO . getReg ( ) , OpNo ) ; return CTX . getRegisterInfo ( )


<s> const char * getPassName ( ) const override { return <STR_LIT>