<s> if ( ! HeadTail . second . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( String . substr ( HeadTail . first . size ( ) , <NUM_LIT> ) , Loc ) ) ; String = HeadTail . second ; } while ( ! String . empty ( ) ) ; return false


<s> return get_spec_unspec_code ( x ) !=


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall ( )


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS1 = extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT NewVT = <STR_LIT> ( EltVT


<s> void mips_expand_vec_minmax ( rtx target , rtx op0 , rtx op1 , rtx ( * cmp ) ( rtx , rtx , rtx ) , bool min_p ) { machine_mode vmode = GET_MODE ( target ) ; rtx tc , t0 , t1 , x ; tc = gen_reg_rtx ( vmode ) ; t0 = gen_reg_rtx ( vmode ) ; t1 = gen_reg_rtx ( vmode ) ; emit_insn ( cmp ( tc , op0 , op1 ) ) ; x = gen_rtx_AND ( vmode , tc , ( min_p ? op1 : op0 ) ) ; emit_insn ( gen_rtx_SET ( t0 , x ) ) ; x = gen_rtx_NOT ( vmode , tc ) ; x = gen_rtx_AND ( vmode , x , ( min_p ? op0 : op1 ) ) ; emit_insn ( gen_rtx_SET ( t1


<s> vmlaq_u8 ( uint8x16_t a , uint8x16_t b , uint8x16_t c ) { uint8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> __v4sf mask = _mm_cmpeq_ps ( src , src ) ; return ( __m128 ) __builtin_ia32_gatherdiv4sf ( src , base , ( __v2di ) index ,


<s> ptr = to_host_file_spec ( argv [ i ] ) ; exefilename = xstrdup ( ptr ) ; out_len = strlen ( ptr ) ; buff = xmalloc ( out_len + <NUM_LIT> ) ; if ( share ) strcpy ( buff , <STR_LIT> ) ; else strcpy ( buff , <STR_LIT> ) ; strcat ( buff , ptr ) ; addarg ( buff ) ; if ( share ) { sharefilename = xmalloc ( out_len + <NUM_LIT> ) ; if ( ptr == strchr ( argv [ i ] , ']' ) ) strcpy ( sharefilename , ++ ptr ) ; else if ( ptr == strchr ( argv [ i ] , ':' ) ) strcpy ( sharefilename , ++ ptr ) ; else if ( ptr == strrchr ( argv [ i ] , '/' ) ) strcpy ( sharefilename , ++ ptr ) ; else strcpy ( sharefilename , argv


<s> HST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; const auto & HRI = * HST -> getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Register AR = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackAlignBaseVReg ( ) ; std :: map < unsigned , SmallVector < MachineInstr * , <NUM_LIT> >> VExtractMap ; MaybeAlign MaxAlign ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { unsigned Opc = MI . getOpcode ( ) ; if ( Opc != <STR_LIT> ) continue ; Register VecR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; VExtractMap [ VecR ] . push_back ( & MI ) ; } } auto EmitAddr = [ & ] ( MachineBasicBlock & BB , MachineBasicBlock :: iterator At , DebugLoc dl , int FI , unsigned Offset ) { Register AddrR = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned FiOpc = AR != <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( BB , At , dl , HII -> get ( FiOpc ) , AddrR ) ; if ( AR ) MIB . addReg ( AR ) ; MIB . addFrameIndex ( FI ) . addImm ( Offset ) ; return AddrR ; } ; for ( auto & P : VExtractMap ) { unsigned VecR = P . first ; if ( P . second . size ( ) <= VExtractThreshold ) continue ; const auto & VecRC = * MRI . getRegClass ( VecR ) ; Align Alignment = HRI . getSpillAlign ( VecRC ) ; MaxAlign = max ( MaxAlign , Alignment ) ; int FI = MFI . CreateStackObject ( HRI . getSpillSize ( VecRC ) , Alignment , false ) ; MachineInstr * DefI = MRI . getVRegDef ( VecR ) ; MachineBasicBlock :: iterator At = std :: next ( DefI -> getIterator ( ) ) ; MachineBasicBlock & DefB = * DefI -> getParent ( ) ; unsigned StoreOpc = VecRC . getID ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Register AddrR = EmitAddr ( DefB , At , DefI -> getDebugLoc ( ) , FI , <NUM_LIT> ) ; BuildMI ( DefB , At , DefI -> getDebugLoc ( ) , HII -> get ( StoreOpc ) ) . addReg ( AddrR ) . addImm ( <NUM_LIT> ) . addReg ( VecR ) ; unsigned VecSize = HRI . getRegSizeInBits ( VecRC ) / <NUM_LIT> ; for ( MachineInstr * ExtI : P . second ) { assert ( ExtI -> getOpcode ( ) == <STR_LIT> ) ; unsigned SR = ExtI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; assert ( ExtI -> getOperand ( <NUM_LIT> ) . getReg ( ) == VecR ) ; MachineBasicBlock & ExtB = *


<s> void <ISA_LIT>TargetMachine :: adjustPassManager ( PassManagerBuilder & PMB ) { PMB . addExtension ( PassManagerBuilder :: EP_LateLoopOptimizations , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>LoopIdiomPass ( ) ) ; } )


<s> if ( ST ) OS << <STR_LIT> << ST -> getOccupancyWithNumVGPRs ( getVGPRNum ( ST -> hasGFX90AInsts ( ) ) ) << ')' ; OS << <STR_LIT> << getSGPRNum ( ) ; if ( ST ) OS << <STR_LIT> << ST -> getOccupancyWithNumSGPRs ( getSGPRNum ( ) ) << ')' ; OS << <STR_LIT> << getVGPRTuplesWeight ( ) << <STR_LIT> << getSGPRTuplesWeight ( ) ; if ( ST ) OS << <STR_LIT> << getOccupancy ( * ST ) ; OS <<


<s> } if ( GET_CODE ( reg ) != REG || REGNO ( reg ) > A7_REG || REGNO ( reg ) + HARD_REGNO_NREGS ( A7_REG , mode ) <= A7_REG ) return opnd ; gcc_assert ( REGNO ( reg ) + HARD_REGNO_NREGS ( A7_REG , mode ) - <NUM_LIT> == A7_REG ) ; cfun -> machine -> need_a7_copy = false ; push_to_sequence ( entry_insns ) ; tmp = gen_reg_rtx ( mode ) ; switch ( mode ) { case DFmode : case DImode : emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_rtx_REG ( SImode , A7_REG - <NUM_LIT> ) ) ) ; emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_raw_REG ( SImode , A7_REG ) ) ) ; break ; case SFmode : emit_insn ( gen_movsf_internal ( tmp , gen_raw_REG


<s> ( void ) rs6000_option_override_internal


<s> bool <ISA_LIT>TTIImpl :: isWideningInstruction ( Type * DstTy , unsigned Opcode , ArrayRef < const Value * > Args ) { auto toVectorTy = [ & ] ( Type * ArgTy ) { return FixedVectorType :: get ( ArgTy -> getScalarType ( ) , cast < VectorType > ( DstTy ) -> getNumElements ( ) ) ; } ; if ( ! DstTy -> isVectorTy ( ) || DstTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; switch ( Opcode ) { case Instruction :: Add : case Instruction :: Sub


<s> unsigned NewOffset0 = CI . Offset ; unsigned NewOffset1 = Paired . Offset ; unsigned Opc = CI . UseST64 ? read2ST64Opcode ( CI . EltSize ) : read2Opcode ( CI . EltSize ) ; unsigned SubRegIdx0 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SubRegIdx1 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( NewOffset0 > NewOffset1 ) { std :: swap ( NewOffset0 , NewOffset1 ) ; std :: swap ( SubRegIdx0 , SubRegIdx1 ) ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; Register BaseReg = AddrReg -> getReg ( ) ; unsigned BaseSubReg = AddrReg -> getSubReg ( ) ; unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { Register ImmReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , Paired . I , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) . addImm ( <NUM_LIT> ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Read2 = BuildMI ( * MBB , Paired . I , DL , Read2Desc , DestReg ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1

) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * Paired . I } ) ;


<s> bool <ISA_LIT>InstrInfo :: isCompoundBranchInstr ( const MachineInstr & MI ) const { return ( getType ( MI ) == <STR_LIT> && MI


<s> return DecodeRegisterClassByID ( Inst , RegNo ,


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeSelect = <STR_LIT> ; break ; } if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( OpcodeSelect , dl , VT , VMask


<s> HARD_REG_SET left ; size = <NUM_LIT> ; COPY_HARD_REG_SET ( left , reg_class_contents [ ( int ) rclass ] ) ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) ST_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( ST_REG_FIRST , mode ) ) size = MIN ( size , <NUM_LIT> ) ; AND_COMPL_HARD_REG_SET ( left , reg_class_contents [ ( int ) ST_REGS ] ) ; } if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FP_REGS ] ) ) { if ( HARD_REGNO_MODE_OK ( FP_REG_FIRST , mode ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) size = MIN ( size , UNITS_PER_MSA_REG ) ; else size = MIN ( size


<s> return ( uint64x1_t ) __builtin_neon_vpaddluv2si ( (


<s> __inline__ static unsigned long long sh_media_MSHARD_L ( unsigned long long mm , unsigned int mn


<s> if ( ! isAddress || RegNo ) { RegNo = Regs [ RegNo ] ; if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; return MCDisassembler ::


<s> bool <ISA_LIT>InstrInfo :: isTailCall ( const MachineInstr & MI ) const { if ( ! MI . isBranch ( ) )


<s> bool <ISA_LIT>InstrInfo :: copyRegToReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , unsigned SrcReg , const TargetRegisterClass * DestRC , const TargetRegisterClass * SrcRC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC


<s> } else { LinearizedRegion * SubRegion = CI -> getRegionMRT ( ) -> getLinearizedRegion ( ) ; for ( auto MBBI : SubRegion -> MBBs ) { storeMBBLiveOuts ( MBBI , MRI , TRI , PHIInfo , TopRegion ) ; } } } if ( CurrentTopRegion == nullptr ) { auto Succ = Region -> getSucc ( ) ; for ( auto & II : * Succ ) { if ( II . isPHI ( ) ) { MachineInstr & PHI = II ; int numPreds = getPHINumInputs ( PHI


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> bool isDPRCalleeSavedAreaFrame ( int fi ) const { if ( fi < <NUM_LIT> || fi >= ( int ) DPRCSFrames . size


<s> void addCoprocNumOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> &&


<s> switch ( RegNo ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! isGFX9 ( ) ; default : break ; } if ( isCI ( ) ) return true ; if ( is<ISA_LIT> ( ) ) { switch ( RegNo ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ; } } for ( MCRegAliasIterator R ( <STR_LIT> , & MRI , true ) ; R . isValid ( ) ; ++ R ) { if ( * R == RegNo


<s> if ( XINT ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_EXECUTE ) return XVECEXP ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; else { gcc_assert ( JUMP_P ( insn ) ) ; return XEXP ( XVECEXP ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> )

, <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> if ( Enable<ISA_LIT>IfConvert ) addPass ( & IfConverterID ) ; addPass ( create<ISA_LIT>ClauseMergePass ( )


<s> return false ; } auto BinPrefix = F . getSectionPrefix ( ) . getValue ( ) ; auto & CPEntries = MF . getConstantPool ( ) -> getConstants ( ) ; SmallSet < int , <NUM_LIT> > CPIndices ; int Index = <NUM_LIT> ; for ( auto & E : CPEntries ) { if ( isIntraBin ( E , BinPrefix ) ) CPIndices . insert ( Index ) ; Index ++ ; } if ( CPIndices . empty ( ) ) return false ; std :: vector < MachineInstr * > Uses ; for ( auto & BB : MF ) { for ( auto & MI


<s> if ( ! LiveEFLAGS ) CheckingMBB . addLiveIn ( <STR_LIT> ) ; auto InsertPt = CheckingMBB . begin ( ) ; assert ( ( InsertPt == CheckingMBB . end ( ) || ! InsertPt -> isPHI ( ) ) && <STR_LIT> <STR_LIT> ) ; unsigned CurStateReg = PS -> InitialReg ; for ( <STR_LIT> Cond : Conds ) { int PredStateSizeInBytes = TRI -> getRegSizeInBits ( * PS -> RC ) / <NUM_LIT> ; auto CMovOp = <STR_LIT> ( PredStateSizeInBytes ) ; unsigned UpdatedStateReg = MRI -> createVirtualRegister ( PS -> RC ) ; auto CMovI = BuildMI ( CheckingMBB , InsertPt , DebugLoc ( ) , TII -> get ( CMovOp ) , UpdatedStateReg ) . addReg ( CurStateReg ) . addReg ( PS -> PoisonReg ) . addImm ( Cond ) ; if ( ! LiveEFLAGS && Cond == Conds . back ( ) ) CMovI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( true ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; CMovI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( CurStateReg == PS -> InitialReg ) CMovs . push_back ( & * CMovI ) ; CurStateReg = UpdatedStateReg ; } PS -> SSA . AddAvailableValue ( & CheckingMBB , CurStateReg ) ; } ; std :: vector < <STR_LIT> > UncondCodeSeq ; for ( auto * CondBr : CondBrs ) { MachineBasicBlock & Succ = * CondBr -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int & SuccCount = SuccCounts [ & Succ ] ; <STR_LIT> Cond = <STR_LIT> ( * CondBr ) ; <STR_LIT> InvCond = <STR_LIT> ( Cond ) ; UncondCodeSeq . push_back ( Cond ) ; BuildCheckingBlockForSuccAndConds ( MBB , Succ , SuccCount , CondBr , UncondBr , { InvCond } ) ; -- SuccCount ; } MBB . normalizeSuccProbs ( ) ; if ( ! UncondSucc ) continue ; assert ( SuccCounts [ UncondSucc ] ==


<s> case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * getSymbol ( GV


<s> if ( Cost != - <NUM_LIT> ) return Cost ; return BaseT :: getIntrinsicInstrCost ( ICA , CostKind


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) , false ) , RegSpillOffsets ( <NUM_LIT> ) { RegSpillOffsets . grow ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( SpillOffsetTable ) ; I != E ; ++ I )

RegSpillOffsets [ SpillOffsetTable [ I ] . Reg ] = SpillOffsetTable [ I ] . Offset ;


<s>
rtx
note
;
int
v8
=
<NUM_LIT>
;
if
(
!
far
&&
insn
&&
INSN_ADDRESSES_SET_P
(
)
)
{
int
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
<
<NUM_LIT>
||
delta
>=
<NUM_LIT>
)
v8
=
<NUM_LIT>
;
}
switch
(
mode
)
{
case
E_CCmode
:
case
E_CCNZmode
:
case
E_CCCmode
:
case
E_CCVmode
:
labelno
=
<STR_LIT>
;
if
(
v8
)
labelno
=
<STR_LIT>
;
break
;
case
E_CCXmode
:
case
E_CCXNZmode
:
case
E_CCXCmode
:
case
E_CCXVmode
:
labelno
=
<STR_LIT>
;
gcc_assert
(
!
v8
)
;
break
;
case
E_CCFPmode
:
case
E_CCFPEmode
:
{
static
char
v9_fcc_labelno
[
]
=
<STR_LIT>
;
v9_fcc_labelno
[
<NUM_LIT>
]
=
REGNO
(
cc_reg
)
SPARC_FIRST_V9_FCC_REG
+
'0'
;
labelno
=
v9_fcc_labelno
;
if
(
v8
)
{
gcc_assert
(
REGNO
(
cc_reg
)
==
SPARC_FCC_REG
)
;
labelno
=
<STR_LIT>
;
}
}
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
*
labelno
&&
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
profile_probability
::
from_reg_br_prob_note
(
XINT
(
note
,
<NUM_LIT>
)
)
>=
profile_probability
::
even
(
)
)
^
far
)
<STR_LIT>
:
<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
spaces
-=
<NUM_LIT>
;
}
}
else
labelno
=
<STR_LIT>
;
if
(
spaces
>
<NUM_LIT>
)
*
p
++
=
'\t'
;
else
*
p
++
=
' '
;
strcpy
(
p
,
labelno
)
;
p
=
strchr
(
p
,
'\0'
)
;
if
(
far
)
{
strcpy
(
p
,
<STR_LIT>
)
;
if
(
annul
||
!
final_sequence
)
p
[
<NUM_LIT>
]
=
'6'
;
p
+=
<NUM_LIT>
;
}
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
label
+
'0'
;
*
p
++
=
'%'


<s> MIB . add ( Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , <NUM_LIT> ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset


<s> MVT VT ; if ( ! isLoadStoreTypeLegal ( I -> getType ( ) , VT ) || cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; Address Addr


<s> unsigned <ISA_LIT>LowerMemoryIntrinsics :: OptMemTransferScalar ( IRBuilder < > & IRB , Value * Src , Value * Dst , MemIntrinsic * Inst ) { assert ( ! isa < CompositeType > ( Src -> getType ( ) ) && ! isa < CompositeType > ( Dst -> getType ( ) ) ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; Type * SrcTy = GetRootType ( Src -> getType ( ) ) ; Type * DstTy = GetRootType ( Dst -> getType ( ) ) ; uint64_t SrcSz = DL . getTypeSizeInBits ( SrcTy ) ; uint64_t DstSz = DL . getTypeSizeInBits ( DstTy ) ; unsigned MemTransferDst = DstSz - CurrDstOffset ; unsigned MemTransferSrc = isa < MemSetInst > ( Inst ) ? MemTransferDst : SrcSz - CurrSrcOffset ; unsigned MemTransferSz = MemTransferDst < MemTransferSrc ? MemTransferDst : MemTransferSrc ; Value * LoadSrc = nullptr ; if ( MemSetInst * MSI = dyn_cast < MemSetInst > ( Inst ) ) { LoadSrc = PrepareValueForMemSet ( IRB , MSI -> getValue ( ) , DstTy ) ; SrcSz =


<s> return ! IsFMSMul ( I ) ; case Instruction :: Sub : case Instruction :: FSub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return Operand == <NUM_LIT> ; default : return false ; } } ; int Op = <NUM_LIT> ; if ( ! isa < ShuffleVectorInst > ( I -> getOperand ( Op ) ) ) Op = <NUM_LIT> ; if ( ! IsSinker ( I , Op ) ) return false ; if ( ! match ( I -> getOperand ( Op ) , m_ShuffleVector ( m_InsertElement ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) { return false ; } Instruction * Shuffle = cast < Instruction > ( I -> getOperand ( Op ) ) ; for ( Use & U : Shuffle -> uses (


<s> MCELFStreamer & getStreamer ( ) { return static_cast < MCELFStreamer & >


<s> MI . eraseFromParent ( ) ; return true ; } assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < Register , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy , <NUM_LIT> } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy , <NUM_LIT> } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy , <NUM_LIT> } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MIRBuilder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred ,

ProcessedResult , LibcallResult , Zero ) ;


<s> SDValue getAddrGlobal ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , unsigned Flag , SDValue Chain , const MachinePointerInfo &


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ; return MCDisassembler ::


<s> case <STR_LIT> : case <STR_LIT> : Scale = - <NUM_LIT> ; CheckCPSRDef = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; CheckCPSRDef = true ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; CheckCPSRDef = false ; break ; case <STR_LIT> : Scale = - <NUM_LIT> ; CheckCPSRDef = false ; break ; default : return <NUM_LIT> ; } Register MIPredReg


<s> bool <ISA_LIT>DAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( OptLevel == CodeGenOpt :: None ) return false ; if ( ! N . hasOneUse ( ) ) return false ; if ( N . getOpcode ( ) != <STR_LIT> ) return true ; if ( U == Root ) { switch ( U -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> optForMinSize ( ) ; bool Changed = false ; CmpConv . runOnMachineFunction ( MF ) ; for ( auto * I : depth_first ( DomTree ) ) if ( tryConvert ( I -> getBlock ( ) ) ) Changed = true ; return Changed


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const Align Alignment = MFI . getObjectAlign ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Alignment ) ; switch ( TRI -> getSpillSize ( * RC ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB ; if ( Subtarget . hasV5TEOps ( ) ) { MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else


<s> uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = <STR_LIT> ; return


<s> default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( riscv_emit_attribute_p ) riscv_emit_attribute (


<s> <ISA_LIT>VSXFMAMutate ( ) : MachineFunctionPass ( ID


<s> for ( int i = ExtraSteps ; i > <NUM_LIT> ; -- i ) { SDValue Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } ExtraSteps = <NUM_LIT> ; return Estimate


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return nullptr ; auto * RC = MRI . getRegClass ( RR . Reg ) ; if ( RR . Sub == <NUM_LIT> ) return RC ; auto VerifySR = [ ] ( unsigned


<s> int <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src


<s> bool <ISA_LIT>ExpandPseudo :: expandAtomicArithmeticOp ( unsigned Width , unsigned ArithOpcode , Block & MBB , BlockIt MBBI ) { return expandAtomic ( MBB , MBBI , [ & ] ( MachineInstr & MI ) { auto Op1 = MI . getOperand ( <NUM_LIT> ) ; auto Op2 = MI . getOperand ( <NUM_LIT> ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode ) . addOperand ( Op1 ) . addOperand ( Op2 ) ; buildMI ( MBB , MBBI , ArithOpcode ) . addOperand ( Op1 ) . addOperand ( Op1 ) . addOperand ( Op2 ) ; buildMI ( MBB , MBBI , StoreOpcode ) . addOperand ( Op2 ) . addOperand ( Op1 ) ; } )


<s> void <ISA_LIT>InstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * P<ISA_LIT> , BlockFrequencyInfo * BFI ) { MRI = & MF . getRegInfo ( ) ; Subtarget = & MF . getSubtarget < GCNSubtarget


<s> ScheduleDAGMI * PS = new ScheduleDAGMI ( C , std :: make_unique < <ISA_LIT>VLIWSchedStrategy > ( )


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG , unsigned VarArgsFrameIndex ) { DebugLoc dl = Op . getDebugLoc ( ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy (


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT>


<s> if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( term ) == PLUS && ( CONST_INT_P ( XEXP ( term , <NUM_LIT> ) ) || GET_CODE ( XEXP ( term , <NUM_LIT> ) ) == CONST_DOUBLE ) ) term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( term , <NUM_LIT> ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , <NUM_LIT> , <NUM_LIT> ) ; } return ix86_delegitimize_address ( x


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) ; void EmitInstrWithMacroNoAT ( const MachineInstr * MI ) ; private : bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; void emitPseudoIndirectBranch ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; const MachineConstantPool * MCP ; bool InConstantPool ; std :: map < const char * , const llvm :: <STR_LIT> * > StubsNeeded ; void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; bool isLongBranchPseudo ( int Opcode ) const ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MCInstLowering ( * this ) { } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int


<s> static bool IsVPRDefinedOrKilledByBlock ( MachineBasicBlock :: iterator Iter , MachineBasicBlock :: iterator End ) { for ( ; Iter != End ; ++ Iter ) if ( Iter -> definesRegister ( <STR_LIT> ) || Iter ->

killsRegister ( <STR_LIT> ) ) return true ;


<s> static std :: vector < CalleeSavedInfo > :: iterator getSavedReg ( std :: vector < CalleeSavedInfo > & V , unsigned reg ) { for ( auto I = V . begin ( ) , E = V . end ( ) ; I != E ;


<s> MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugInstr ( ) ) ; if ( I != MBB -> end ( ) &&

I -> getOpcode ( ) == <STR_LIT> ) return true ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc =


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNum , SMLoc


<s> bool hasMTHC1 ( ) const { return true


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI , DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI , Hi ) ; return Lo


<s> uint16x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock


<s> SDValue Res = DCI . DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; return DCI . DAG . getMergeValues ( { Res , DCI . DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } , DL ) ; } if ( SDNode * GenericAddSub = DCI . DAG . getNodeIfExists ( <STR_LIT> , DCI . DAG . getVTList ( VT ) , { LHS , RHS } ) ) DCI . CombineTo ( GenericAddSub , SDValue ( N , <NUM_LIT> ) ) ; return SDValue ( )


<s> BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> && Base != <STR_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; } if ( ! TL -> isLegalAddImmediate ( Offset ) ) return nullptr ; bool KillOldBase = BaseKill && ( ! isi32Store ( Opcode ) || ! ContainsReg ( Regs , Base ) ) ; if ( isThumb1 ) { if ( Base != NewBase && ( BaseOpc == <STR_LIT> || BaseOpc == <STR_LIT> ) ) { if ( is<ISA_LIT>LowRegister ( NewBase ) && is<ISA_LIT>LowRegister ( Base ) && ! STI -> hasV6Ops ( ) ) { if ( Pred != <STR_LIT> ) return nullptr ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) ; } else BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Pred ) . addReg ( PredReg ) ; Base = NewBase ; KillOldBase = true ; } if ( BaseOpc == <STR_LIT> ) { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset / <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) ; } else AddDefaultT1CC ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) , true ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { BuildMI ( MBB , InsertBefore , DL , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( KillOldBase ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } Base = NewBase ; BaseKill =


<s> if ( ! SU || SU -> isScheduled ) return ResCount ; auto & QST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & QII = * QST . getInstrInfo ( ) ; if ( SU -> isInstr ( ) && QII . mayBeCurLoad ( * SU -> getInstr ( ) ) ) { if ( Q . getID ( ) == TopQID && Top . ResourceModel -> isResourceAvailable ( SU , true ) ) { ResCount += PriorityTwo ; LLVM_DEBUG ( if ( verbose )


<s> emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( val , x ) ) ; x = gen_rtx_NOT ( mode , val ) ; } else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after ) emit_insn ( gen_rtx_SET ( after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch


<s> PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return false


<s> pinsrh_1_u ( uint16x4_t s , uint16x4_t t ) { return __builtin_loongson_pinsrh_1_u ( s


<s> static void rbt_right_rotate ( struct rbt_strings * t , struct rbt_string_node * node ) { struct rbt_string_node * left = node -> left ; assert ( left ) ; node -> left = left -> right ; if ( left -> right != t -> rbt_nil ) left -> right -> par = node ; left -> par = node -> par ; if ( node -> par == t -> rbt_nil ) t -> rbt_root = left ; else if ( node == node -> par -> right ) node -> par -> right = left ; else node -> par -> left =


<s> int count ( void ) const { return m_counter


<s> unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VSRCTmp1 ) . addReg ( NewVReg ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; insertSwap ( MI , InsertPoint , VSRCTmp2 , VSRCTmp1 ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( VSRCTmp2 ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; } else


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream


<s> if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> Offset = <NUM_LIT> ; MachineBasicBlock & MBB = * MBBI -> getParent ( ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( MBBI == BeginMBBI ) return EndMBBI ; MachineBasicBlock :: iterator PrevMBBI = std :: prev


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op .


<s> Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return


<s> if ( getLexer ( ) . getTok ( ) . getString ( ) != <STR_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; std :: string Token ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { SMLoc Loc = getLexer ( ) . getTok ( ) . getEndLoc ( ) ; Token = std :: string ( getLexer ( ) . getTok ( ) . getString ( ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getTok ( ) . getLoc ( ) != Loc ) return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return MatchOperand_ParseFail ; Token += getLexer ( ) . getTok ( ) . getString ( ) ; StringRef DimId = Token ; if ( DimId . startswith ( <STR_LIT> ) ) DimId = DimId . substr ( <NUM_LIT> ) ; const <STR_LIT> * DimInfo = <STR_LIT> ( DimId ) ; if ( ! DimInfo ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , DimInfo -> Encoding , S , <ISA_LIT>Operand :: ImmTyDim ) ) ; return MatchOperand_Success


<s> unsigned ResultReg = Root . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src0IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg1 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( VR ) ) MRI . constrainRegClass ( VR , RC ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addReg ( VR ) ; InsInstrs . push_back ( MIB ) ; return MUL


<s> emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; } if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames (


<s> Lo = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; } else { Hi = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Bytes [ <NUM_LIT> ] & <NUM_LIT> ) << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; Lo = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes


<s> if ( CC != - <NUM_LIT> ) { BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( getBRccForPseudo ( MI ) ) ) . addMBB ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) .

add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( getCCForBRcc ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> SDValue <ISA_LIT>DAGToDAGISel :: getUNDEF ( const SDLoc & DL , EVT VT ) const { SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL


<s> void <ISA_LIT>InstPrinter :: printLiteral ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream &


<s> bool <ISA_LIT>RegisterBankInfo :: isSALUMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( const RegisterBank * Bank = getRegBank ( Reg , MRI , * TRI


<s> int VAddr0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr0 ) ; unsigned NewAddrDwords = Info -> VAddrDwords ; const TargetRegisterClass * RC ; if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else { RC = & <STR_LIT> ; NewAddrDwords = <NUM_LIT> ; } unsigned VgprBase = <NUM_LIT> ; bool IsUndef = true ; bool IsKill = NewAddrDwords == Info -> VAddrDwords ; for ( unsigned i = <NUM_LIT> ; i < Info -> VAddrDwords ; ++ i ) { const MachineOperand & Op = MI . getOperand ( VAddr0Idx + i ) ; unsigned Vgpr = TRI -> getHWRegIndex ( Op . getReg ( ) ) ; if ( i == <NUM_LIT> ) { VgprBase = Vgpr ; } else if ( VgprBase + i != Vgpr ) return ; if ( ! Op . isUndef (


<s> bool <ISA_LIT>ExpandISEL :: isExpandISELEnabled ( const MachineFunction & MF ) { return ! GenerateISEL || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> FunctionPass * llvm :: create<ISA_LIT>CFGSort


<s> if ( ! isMove ( SU ) ) return false ; unsigned side , xuse ; tie ( side , xuse ) = analyzeMove ( SU ) ; Hzd -> bookMove ( side , xuse ) ; return


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , TargetLowering :: CallLoweringInfo & CLI ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> , CLI ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( VA . isUpperBitsInLoc ( ) ) { unsigned ValSizeInBits = Ins [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT


<s> bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; if ( HasMemOp4 ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> MachineBasicBlock :: iterator MI = mi ; MachineBasicBlock * MBB = mbbi ; ++ mi ; if ( MI -> getDesc ( ) . getOpcode ( ) == <STR_LIT> ) { expandLoadImm ( * MBB , MI , TII ) ; MBB -> erase ( MI ) ; ++ ExpandPseudo ; continue ; } if ( MI -> getDesc ( ) . getOpcode ( ) == <STR_LIT> ) { expandIJmp ( * MBB , MI , TII ) ; MBB -> erase


<s> } return LPCC :: ICC_GT ; case <STR_LIT> : return LPCC :: ICC_UGT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_MI ; return LPCC :: ICC_LT ; case <STR_LIT> : return LPCC :: ICC_ULT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_MI ; } return LPCC :: ICC_LE ; case <STR_LIT> : return LPCC :: ICC_ULE ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_PL ; return LPCC :: ICC_GE ; case <STR_LIT> : return LPCC :: ICC_UGE ; case <STR_LIT> : return LPCC :: ICC_NE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> set_reg ( sr -> curr . reg + reg , UNW_WHERE_SPREL , sr -> region_start + sr -> region_len - <NUM_LIT> ,


<s> if ( Op . getValueType ( ) == <STR_LIT> && ( ! hasHardQuad || ! TLI . isTypeLegal ( OpVT ) ) ) { const char * libName = TLI . getLibcallName ( OpVT == <STR_LIT> ? RTLIB :: SINTTOFP_I32_F128 : RTLIB :: SINTTOFP_I64_F128 ) ; return TLI . LowerF128Op ( Op , DAG , libName , <NUM_LIT> ) ; } if ( ! TLI . isTypeLegal ( OpVT ) ) return


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> bool mips_expand_ins_as_unaligned_store ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { rtx left , right ; machine_mode mode ; if ( ! mips_get_unaligned_mem ( dest , width , bitpos , & left , & right ) ) return false ; mode = mode_for_size ( width , MODE_INT , <NUM_LIT> ) ; src = gen_lowpart ( mode , src ) ; if ( mode == DImode ) { emit_insn ( gen_mov_sdl ( dest , src , left )


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind


<s> iterator_range < MCInst :: const_iterator > <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCInst const &


<s> SDValue getCapToCapTable ( NodeTy * N , const SDLoc & DL , SelectionDAG & DAG , unsigned HiFlag , unsigned LoFlag , unsigned SmallFlag , unsigned HiOpc ) const { assert ( ABI . IsCheriPureCap


<s> const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getFrameOffsetReg ( ) && <STR_LIT> ) ; MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ; int64_t NewOffset = OffsetOp -> getImm ( ) + Offset ; assert ( isUInt < <NUM_LIT> > ( NewOffset ) &&


<s> return new <ISA_LIT>DebuggerInsertNops (


<s> Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; return false ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) { FixedValue = OriginalFixedValue ; return false ; } } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; return true


<s> if ( VT == LLT :: scalar ( <NUM_LIT> ) ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) .


<s> const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; int DTNumber = MBB -> getNumber ( ) ; if ( DTNumber < JTNumber ) { MachineBasicBlock * NewBB = AdjustJTTargetBlockForward ( MBB


<s> void <ISA_LIT>InstrInfo :: legalizeOperandsSMRD ( MachineRegisterInfo & MRI , MachineInstr & MI ) const { MachineOperand * SBase = getNamedOperand ( MI , <STR_LIT> :: sbase ) ; if ( SBase && ! RI . isSGPRClass ( MRI . getRegClass ( SBase -> getReg ( ) ) ) ) { unsigned SGPR = readlaneVGPRToSGPR ( SBase -> getReg ( ) ,


<s> typedef enum { none , zpreg } TCopyKind ; for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , MBBE = MF -> end ( ) ; MBBI != MBBE ; ++ MBBI ) { MBB = & * MBBI ; for ( MachineBasicBlock :: iterator mi = MBB -> begin ( ) , me = MBB -> end ( ) ; mi != me ; ) { MachineBasicBlock :: iterator nmi = std :: next ( mi ) ; MachineInstr * MI = & * mi ; auto opc = MI -> getOpcode ( ) ; if ( opc == TargetOpcode :: COPY ) { MachineOperand des = MI -> getOperand ( <NUM_LIT> ) ; if ( des . isReg ( )


<s> assert ( MemRefBeginIdx >= <NUM_LIT> && <STR_LIT> ) ; MemRefBeginIdx += <STR_LIT> ( Desc ) ; MachineOperand & BaseMO = UseMI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; MachineOperand & IndexMO = UseMI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; if ( ( BaseMO . isReg ( ) && BaseMO . getReg ( ) == DefReg ) || ( IndexMO . isReg ( ) && IndexMO . getReg ( ) == DefReg ) ) return { } ; continue ; } if ( SingleUseMI ) return { } ; if ( ! isDataInvariant ( UseMI ) || UseMI . getParent ( ) != MI . getParent ( ) ) return { } ; if ( UseMI . getDesc ( ) . getNumDefs ( ) > <NUM_LIT> ) return { } ; unsigned UseDefReg = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( UseDefReg ) || ! canHardenRegister ( UseDefReg ) ) return { } ; SingleUseMI = & UseMI ; } return { SingleUseMI } ; } ; MachineInstr * MI = & InitialMI ; while ( Optional < MachineInstr * > SingleUse = SinkCheckToSingleUse ( * MI ) ) { MI = * SingleUse


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ?


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createLower16 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createUpper16 ( Expr , OutContext ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , OutContext ) , OutContext ) ; return MCOperand :: createExpr ( Expr


<s> if ( ST . isAmdHsaOS ( ) ) { if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; } return


<s> if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ) ; return SDValue ( ) ; } std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FIST


<s> return ACCUMULATE_OUTGOING_ARGS ? crtl ->


<s> bool ScheduleDAGPostRA :: canAddEdge ( SUnit * SuccSU , SUnit * PredSU ) { return SuccSU == & ExitSU || ! Topo .


<s> MachineInstr * MovImm = buildDefaultInstruction ( BB , I , AMDGPU

:: MOV , DstReg , AMDGPU :: ALU_LITERAL_X ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SDValue Flag ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState ccinfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG


<s> for ( ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i + <NUM_LIT> < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = ( BaseReg == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale -

<NUM_LIT> ) ) != <NUM_LIT> ) return false ;


<s> BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , NewExec ) . addReg ( CondReg , RegState :: Kill ) ; MRI . setSimpleHint ( NewExec , CondReg ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) { IdxReg = CurrentIdxReg ; } else { IdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , IdxReg ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ; } unsigned IdxMode = IsIndirectSrc ? <STR_LIT> :: SRC0_ENABLE : <STR_LIT> :: DST_ENABLE ; MachineInstr * SetOn = BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IdxReg , RegState :: Kill ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else { if ( Offset == <NUM_LIT> ) { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) ; } else { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT>


<s> if ( isPowerOf2_64 ( MulAmt ) || MulAmt == <NUM_LIT> || MulAmt == <NUM_LIT> || MulAmt == <NUM_LIT> ) return SDValue ( ) ; uint64_t MulAmt1 = <NUM_LIT> ; uint64_t MulAmt2 = <NUM_LIT> ; if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } SDLoc DL ( N ) ; SDValue NewMul ; if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) { if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT

, NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ;


<s> switch ( opc ) { default : break ; case <STR_LIT> : return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG


<s> assert ( Node -> getIDom ( ) == HeadNode && <STR_LIT> ) ; while ( Node -> getNumChildren ( ) ) DomTree -> changeImmediateDominator ( Node -> getChildren ( ) . back ( ) , HeadNode ) ; DomTree -> eraseNode (


<s> return new <ISA_LIT>CodeEmitter ( TM , MCE


<s> bool Modified = false ; for ( std :: list < CombineInfo > & MergeList : MergeableInsts ) { if ( MergeList . size ( ) < <NUM_LIT> ) continue ; bool OptimizeListAgain = false ; if ( ! optimizeInstsWithSameBaseAddr ( MergeList , OptimizeListAgain ) ) { MergeList . clear ( ) ; continue ; } if ( ! OptimizeListAgain ) MergeList . clear ( ) ; OptimizeAgain |= OptimizeListAgain ; Modified = true ; } return Modified


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDLoc SL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc != <STR_LIT> ) std :: swap ( RHS , LHS ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) , RHS ,


<s> static SDValue getFPTernOp ( SelectionDAG & DAG , unsigned Opcode , const SDLoc & SL , EVT VT , SDValue A , SDValue B , SDValue C , SDValue GlueChain ) { if ( GlueChain -> getNumValues ( ) <= <NUM_LIT> ) { return DAG . getNode ( Opcode , SL , VT ,


<s> static int bpf_core_is_maybe_aggregate_access ( tree expr ) { enum tree_code code = TREE_CODE ( expr ) ; if ( code == COMPONENT_REF || code == ARRAY_REF ) return <NUM_LIT> ; if ( code == ADDR_EXPR ) return bpf_core_is_maybe_aggregate_access ( TREE_OPERAND ( expr ,


<s> bool <ISA_LIT>ompactTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt ::


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options

( Options ) , TargetABI ( <ISA_LIT>_ABI_APCS ) {


<s> b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( a , float_exp_mask ) ; d = ( __vector unsigned int ) vec_cmpgt ( b , float_exp_mask ) ; return ( ( __m128 ) vec_or ( c , d


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) .


<s> add_mem_operand ( mem_mode , get_contiguous_base ( mem_mode ) ) ; add_input_operand ( icode , args . last ( ) ) ; add_input_operand ( icode , args [ <NUM_LIT>


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; setFeatureBits ( <STR_LIT> ,


<s> Ctx . emitError ( <STR_LIT> ) ; } BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg ) . addImm ( Spill . Lane ) ; } MI -> eraseFromParent ( ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { unsigned SubReg = getPhysRegSubReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & <STR_LIT> , i ) ; struct <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = MFI -> getSpilledReg ( MF , Index , i ) ; if ( Spill . VGPR == <STR_LIT> ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> ) ; } BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , SubReg ) . addReg ( Spill . VGPR ) . addImm ( Spill . Lane ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitDefine ) ; } switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) ) { case <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS : TII -> insertWaitStates ( MI , <NUM_LIT> ) ; break ; case <ISA_LIT>Subtarget :: SEA_ISLANDS : break ; default : TII -> insertWaitStates ( MI , <NUM_LIT>


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) { Triple TheTriple ( TT ) ; return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ,


<s> static int readMaskRegister ( struct InternalInstruction * insn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( insn -> vectorExtensionType != TYPE_EVEX ) return - <NUM_LIT> ; insn -> writemask = static_cast < Reg > ( aaaFromEVEX4of4 (

insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ;


<s> static SDValue PromoteSplat ( ShuffleVectorSDNode * SV , SelectionDAG & DAG ) { EVT SrcVT = SV -> getValueType ( <NUM_LIT> ) ; SDValue V1 = SV -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SV -> getDebugLoc ( ) ; int EltNo = SV -> getSplatIndex ( ) ; int NumElems = SrcVT .


<s> case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op ,


<s> vmls_f32 ( float32x2_t a , float32x2_t b , float32x2_t c ) { return a - b *


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg


<s> bool nds32_n13_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer ) == TYPE_LOAD ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; return n13_consumed_by_e2_dep_p ( consumer , def_reg


<s> int Offset = <NUM_LIT> ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase (


<s> vst1q_p64 ( poly64_t * a , poly64x2_t b ) { __builtin_aarch64_st1v2di_sp ( ( __builtin_aarch64_simd_di * ) a , ( poly64x2_t ) b


<s> char * <ISA_LIT>JITInfo :: allocateThreadLocalMemory ( size_t size ) { TLSOffset -= size ; return TLSOffset ; llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } unsigned Scale , Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ; assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT>


<s> unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize


<s> unsigned getMaxNumSGPRs ( unsigned WavesPerEU , bool Addressable ) const { return <STR_LIT> :: getMaxNumSGPRs ( this


<s> case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , * this


<s> } ; if ( ! DstTy -> isVectorTy ( ) || DstTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; switch ( Opcode ) { case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : break ; default : return false ; } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto * Arg0 = dyn_cast < CastInst > ( Args [ <NUM_LIT> ] ) ; if ( Opcode == Instruction :: Mul && ( ! Arg0 || Arg0 -> getOpcode ( ) != Extend -> getOpcode ( ) || Arg0 -> getOperand ( <NUM_LIT> ) -> getType ( ) != Extend -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ) return false ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ; auto * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ; auto SrcTyL = TLI -> getTypeLegalizationCost ( DL , SrcTy ) ; unsigned SrcElTySize = SrcTyL . second . getScalarSizeInBits ( ) ; if ( ! SrcTyL . second . isVector ( ) || SrcElTySize != SrcTy -> getScalarSizeInBits (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAME_TO_ARGS_OFFSET ( SDValue Op , SelectionDAG & DAG ) const { return DAG . getIntPtrConstant ( <NUM_LIT> * TD -> getPointerSize


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable (


<s> return ( __m128i ) __builtin_ia32_expandsi128_mask ( ( __v4si ) __A , ( __v4si )


<s> if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OL != CodeGenOpt :: None ) { if ( ! FullFS . empty ( ) )


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } const bool IsWrite = MII . get ( Inst . getOpcode ( ) ) . mayStore ( ) ; for ( unsigned Ix = <NUM_LIT> ; Ix < Operands . size ( ) ; ++ Ix ) { assert ( Operands [ Ix ] ) ; MCParsedAsmOperand & Op = *


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; emitDemotedVars ( & MF -> getFunction (


<s> bool useRetpolineIndirectBranches ( ) const { return


<s> static ScheduleDAGInstrs * create<ISA_LIT>MachineScheduler ( MachineSchedContext * C ) { return new <ISA_LIT>ScheduleDAGMI ( C


<s> if ( ! decompose_csky_address ( XEXP ( op , <NUM_LIT> ) , & addr ) ) return false ; if ( ! is_csky_address_register_rtx_p ( addr . base , <NUM_LIT> ) ) return false ; if ( addr . index && ( constraint [ <NUM_LIT> ] == 'Q' || constraint [ <NUM_LIT> ] == 'W' ) ) { if ( ! is_csky_address_register_rtx_p ( addr . index , <NUM_LIT> ) ) return false ; if ( addr . scale == <NUM_LIT> || addr . scale == <NUM_LIT> || addr . scale == <NUM_LIT> || addr . scale == <NUM_LIT>


<s> unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else { assert ( VT == <STR_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( IdxVal , dl ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } if ( Subtarget . hasSSE41 ( ) ) { if ( EltVT == <STR_LIT> ) { bool MinSize = DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ; if ( IdxVal == <NUM_LIT> && ( ! MinSize || ! MayFoldLoad ( N1 ) ) ) { N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } N2 = DAG . getIntPtrConstant ( IdxVal << <NUM_LIT> , dl ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return Op ; } return SDValue


<s> if ( REAL_VALUES_LESS ( r , dconst1 ) ) return <NUM_LIT> ; exp = real_exponent ( & r ) ; real_2expN ( & r1 , exp , DFmode ) ; if ( REAL_VALUES_EQUAL ( r1 , r ) )


<s> if ( auto USatVal = detectUSatPattern ( In , VT , DAG , DL ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ! Subtarget . hasAVX512 ( ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT>


<s> if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugInstr ( ) ) ++ I ; if ( I != E ) { unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( * I , NPredReg ) ; if ( NCC == CC || NCC == OCC ) return true ; } return false


<s> SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } } if ( RHSC && RHSC -> getSExtValue ( ) == - <NUM_LIT> && CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; SDValue BR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , CC1Val , Cmp ) ; if ( CC2 != <STR_LIT> ) { SDValue CC2Val = DAG . getConstant ( CC2 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BR1 , Dest , CC2Val , Cmp ) ; } return


<s> } else { assert ( Binary <= UINT16_MAX && <STR_LIT> ) ; OS << uint8_t ( Binary >> <NUM_LIT> ) << uint8_t ( Binary ) ; } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) encodeULEB128 ( MI . getNumOperands ( ) - <NUM_LIT> , OS ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) encodeULEB128 ( MI . getNumOperands ( ) - <NUM_LIT> , OS ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { } else if ( MO . isImm ( ) ) { if ( i < Desc . getNumOperands ( ) ) { assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ i ] ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << int ( Info . OperandType ) << <STR_LIT> ) ; switch ( Info . OperandType ) { case <STR_LIT> : encodeSLEB128 ( int32_t ( MO . getImm ( ) ) , OS ) ; break ; case <STR_LIT> : encodeULEB128 ( uint32_t ( MO . getImm ( ) ) , OS ) ; break ; case <STR_LIT> : encodeSLEB128 ( int64_t ( MO . getImm ( ) ) , OS ) ; break ; case <STR_LIT> : OS << uint8_t ( MO . getImm ( ) ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint8_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint16_t > ( OS , MO . getImm (


<s> return ( __m256i ) __builtin_ia32_loaddquhi256_mask ( ( const short * ) __P , ( __v16hi ) _mm256_setzero_si256 (


<s> MFI -> Occupancy = ST . computeOccupancy ( MF . getFunction ( ) , MFI -> getLDSSize ( ) ) ; } auto parseRegister = [ & ] ( const yaml :: StringValue & RegName , Register & RegVal ) { Register TempReg ; if ( parseNamedRegisterReference ( PFS , TempReg , RegName . Value , Error ) ) { SourceRange = RegName . SourceRange ; return true ; } RegVal = TempReg ; return false ; } ; auto diagnoseRegisterClass = [ & ] ( const yaml :: StringValue & RegName ) { const MemoryBuffer & Buffer = * PFS . SM -> getMemoryBuffer ( PFS . SM -> getMainFileID ( ) ) ; Error = SMDiagnostic ( * PFS . SM , SMLoc ( ) , Buffer . getBufferIdentifier ( ) , <NUM_LIT> , RegName . Value . size ( ) , SourceMgr :: DK_Error , <STR_LIT> , RegName . Value , None , None ) ; SourceRange = RegName . SourceRange ; return true ; } ; if ( parseRegister ( YamlMFI . ScratchRSrcReg , MFI -> ScratchRSrcReg ) || parseRegister ( YamlMFI . FrameOffsetReg , MFI -> FrameOffsetReg ) || parseRegister ( YamlMFI . StackPtrOffsetReg , MFI -> StackPtrOffsetReg ) ) return true ; if ( MFI -> ScratchRSrcReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> ScratchRSrcReg ) ) { return diagnoseRegisterClass ( YamlMFI . ScratchRSrcReg ) ; } if ( MFI -> FrameOffsetReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> FrameOffsetReg ) ) { return diagnoseRegisterClass ( YamlMFI . FrameOffsetReg ) ; } if ( MFI -> StackPtrOffsetReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> StackPtrOffsetReg ) ) { return diagnoseRegisterClass ( YamlMFI . StackPtrOffsetReg ) ; } auto parseAndCheckArgument = [ & ] ( const Optional < yaml :: <ISA_LIT>Argument > & A , const TargetRegisterClass & RC , ArgDescriptor & Arg

, unsigned UserSGPRs , unsigned SystemSGPRs ) {


<s> void addSDGOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isSDG ( )


<s> unsigned encodeExpcnt ( IsaVersion Version , unsigned Waitcnt ,


<s> if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } return NULL_TREE


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return &


<s> Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64 = Is<ISA_LIT>64 ; return Op


<s> StartLoc = Parser . getTok ( ) . getLoc ( ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; RegNo = tryParseRegister (


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDSReadWrite2 ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 , unsigned Size ) const { SDLoc DL ( Addr ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; unsigned OffsetValue0 = C1 -> getZExtValue ( ) ; unsigned OffsetValue1 = OffsetValue0 + Size ; if ( isDSOffset2Legal ( N0 , OffsetValue0 , OffsetValue1 , Size ) ) { Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( OffsetValue0 / Size , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( OffsetValue1 / Size , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned OffsetValue0 = C -> getZExtValue ( ) ; unsigned OffsetValue1 = OffsetValue0 + Size ; if ( isDSOffset2Legal ( SDValue ( ) , OffsetValue0 , OffsetValue1 , Size ) ) { SDLoc DL ( Addr ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> )


<s> RestoreReg ( Out , RegCtx . addressReg ( <STR_LIT> ) ) ; RestoreReg ( Out , RegCtx . shadowReg ( <STR_LIT> ) ) ; EmitAdjustRSP ( Ctx , Out , <NUM_LIT> ) ; unsigned FrameReg = GetFrameReg ( Ctx , Out ) ; if ( Ctx . getRegisterInfo ( ) && FrameReg != <STR_LIT> ) { RestoreReg ( Out , <STR_LIT>


<s> bool isThumb ( ) const { return isThumbMode


<s> rtx modaddr = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( tlsname ) ) ; SYMBOL_REF_FLAGS ( modaddr ) |= SYMBOL_FLAG_LOCAL ; tocref = create_TOC_reference ( modaddr , NULL_RTX ) ; rtx modmem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( modmem , get_TOC_alias_set ( ) ) ; rtx modreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( modreg , modmem ) ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_32BIT ) emit_insn ( gen_tls_get_addrsi ( dest , modreg , tmpreg ) ) ; else emit_insn ( gen_tls_get_addrdi ( dest , modreg , tmpreg ) ) ; return dest ; } else if ( TARGET_32BIT ) { tlsreg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tls_get_tpointer ( tlsreg ) ) ; } else { tlsreg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; xcoff_tls_exec_model_detected = true ; } tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_MINUS ( Pmode , addr , tlsreg ) ) ; dest = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , tmpreg ,


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( Kind == k_Imm && <STR_LIT> ) ; assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExprOperand ( Inst , Imm


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> MCSymbol * <ISA_LIT>AsmPrinter :: lookUpOrCreateTOCEntry ( MCSymbol * Sym ) { const DataLayout * DL = TM . getDataLayout ( ) ; MCSymbol * & TOCEntry = TOC [ Sym ] ; while ( ! TOCEntry ) { if ( OutContext . LookupSymbol ( Twine ( DL -> getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( TOCLabelID ++ ) ) == nullptr ) { TOCEntry = GetTempSymbol ( <STR_LIT> , TOCLabelID


<s> bool isGFX11Plus ( ) const { return <STR_LIT> ( getSTI


<s> bool doFinalization ( Module & M ) override { return false


<s> RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else { return false ; } EVT VT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( VT == <STR_LIT> || ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( MBB , DL , TII . get ( OpImm ) , ResultReg ) . addReg ( Op0Reg ) . addImm ( CI -> getZExtValue ( ) & <NUM_LIT> ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; TII . copyRegToReg ( * MBB , MBB -> end ( ) , CReg , Op1Reg , RC


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( Op . getSimpleValueType ( ) == XLenVT && CondV . getOpcode ( ) == <STR_LIT> && CondV . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == XLenVT ) { SDValue LHS = CondV . getOperand ( <NUM_LIT> ) ; SDValue RHS = CondV . getOperand ( <NUM_LIT> ) ; auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( <NUM_LIT> ) ) ; <STR_LIT> CCVal = CC -> get ( ) ; if ( isa < ConstantSDNode > ( TrueV ) && isa < ConstantSDNode > ( FalseV ) && CCVal == <STR_LIT> ) { const APInt & TrueVal = cast < ConstantSDNode > ( TrueV ) -> getAPIntValue ( ) ; const APInt & FalseVal = cast < ConstantSDNode > ( FalseV ) -> getAPIntValue ( ) ; if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT


<s> ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation =


<s> return ( poly128_t ) __builtin_neon_vreinterprettiv4si ( (


<s> if ( ! Value ) continue ; if ( Value -> isPHIDef ( ) ) continue ; markInstruction ( * LIS -> getInstructionFromIndex ( Value -> def ) , Flag , Worklist ) ; } continue ; } for ( MachineInstr & DefMI : MRI -> def_instructions ( Use . getReg

( ) ) ) markInstruction ( DefMI , Flag , Worklist ) ;


<s> bool hasTransactionalExecution ( ) const { return HasTransactionalExecution


<s> MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; const SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , In2L , In2H , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp , MemOp


<s> else if ( ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CODE ( decl ) == VAR_DECL ) && DECL_RTL ( decl ) != NULL_RTX && GET_CODE ( DECL_RTL ( decl ) ) == MEM && GET_CODE ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ) ==

MEM && GET_CODE ( XEXP ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && mcore_dllimport_name_p ( XSTR ( XEXP ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) {


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; for ( auto * CSR = TRI -> getCalleeSavedRegs ( & MF ) ; CSR && * CSR ; ++ CSR ) if ( MI -> modifiesRegister ( * CSR , TRI ) ) return true ; return


<s> LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ; if ( ! IsMasked ) doAtomicBinOpExpansion ( TII , MI , DL , & MBB , LoopMBB , DoneMBB , BinOp , Width ) ; else doMaskedAtomicBinOpExpansion ( TII , MI , DL , & MBB , LoopMBB , DoneMBB , BinOp , Width ) ; NextMBBI = MBB . end (


<s> unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( ! <STR_LIT> . contains ( Reg ) && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; } } <ISA_LIT>FI -> setCalleeSavedFrameSize (


<s> PointerType * PtrTy = PointerType :: get ( CFP -> getType ( ) , <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , DAG . getConstantFP ( * CFP , VT ) , InitPtr , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , false , false , TD -> getPrefTypeAlignment ( CFP -> getType ( ) ) ) ; } if ( StructType * ST = dyn_cast < StructType > ( InitTy ) ) { const StructLayout * SL = TD -> getStructLayout ( ST ) ; EVT PtrVT = InitPtr . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned I = <NUM_LIT> , N = ST -> getNumElements ( ) ; I != N ; ++ I ) { SDValue Offset = DAG . getConstant ( SL -> getElementOffset ( I ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , InitPtr , Offset ) ; Constant * Elt = Init -> getAggregateElement ( I ) ; Chains . push_back ( LowerConstantInitializer ( Elt , GV , Ptr , Chain , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } if ( SequentialType * SeqTy = dyn_cast < SequentialType > ( InitTy ) ) { EVT PtrVT = InitPtr . getValueType ( ) ; unsigned NumElements ; if ( ArrayType * AT = dyn_cast < ArrayType > ( SeqTy ) ) NumElements = AT -> getNumElements ( ) ; else if ( VectorType * VT = dyn_cast < VectorType > ( SeqTy ) ) NumElements = VT -> getNumElements ( ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned EltSize = TD -> getTypeAllocSize (


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL ,

<STR_LIT> , N , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool Changed = false ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = HST . getInstrInfo ( ) ; TRI = HST . getRegisterInfo (


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return false


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return


<s> mask = _mm_cmpeq_pi8 ( ( __N & hibit ) , hibit ) ; tmp = ( tmp & ( ~ mask ) ) | ( __A & mask ) ; * p =


<s> static void seh_emit_stackalloc ( FILE * f , struct seh_frame_state * seh , HOST_WIDE_INT offset ) { gcc_assert ( offset < <NUM_LIT> ) ; offset = -


<s> rtx xops [ <NUM_LIT> ] ; int regno ; for ( regno = <NUM_LIT> ; regno < <NUM_LIT> ; ++ regno ) { char name [ <NUM_LIT> ] ; if ( ! ( ( pic_labels_used >> regno ) & <NUM_LIT> ) ) continue ; get_pc_thunk_name ( name , regno ) ; if ( USE_HIDDEN_LINKONCE ) { tree decl ; decl = build_decl ( FUNCTION_DECL , get_identifier ( name ) , error_mark_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_ONE_ONLY ( decl ) = <NUM_LIT> ; ( * targetm . asm_out . unique_section ) ( decl , <NUM_LIT> ) ; named_section ( decl , NULL , <NUM_LIT> ) ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputc ( '\n' ,


<s> MachineFunction * MF = MBB . getParent ( ) ; DebugLoc DL ; if ( ! EarlyExitBlock ) { EarlyExitBlock = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( MF -> end ( ) , EarlyExitBlock ) ; generatePsEndPgm ( * EarlyExitBlock , EarlyExitBlock -> end ( ) , DL , TII ) ; EarlyExitClearsExec = false ; } if ( ClearExec && ! EarlyExitClearsExec ) { const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; unsigned Mov = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; Register Exec = ST . isWave32 ( ) ? <STR_LIT> :


<s> void <ISA_LIT>LowerControlFlow :: findMaskOperands ( MachineInstr & MI , unsigned OpNo , SmallVectorImpl < MachineOperand > & Src ) const { MachineOperand & Op = MI . getOperand ( OpNo ) ; if ( ! Op . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( Op . getReg ( ) ) ) { Src . push_back ( Op ) ; return ; } MachineInstr * Def = MRI -> getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Def || Def -> getParent ( ) != MI . getParent ( ) || ! ( Def -> isFullCopy ( ) || ( Def -> getOpcode ( ) == MI . getOpcode ( ) ) ) ) return ; for ( auto I = Def -> getIterator ( ) ; I != MI . getIterator ( ) ; ++ I ) if ( I -> modifiesRegister ( <STR_LIT> , TRI ) && ! ( I -> isCopy ( ) && I -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) ) return ; for ( const auto & SrcOp : Def -> explicit_operands ( ) ) if ( SrcOp . isUse ( ) && ( ! SrcOp . isReg ( ) || TargetRegisterInfo :: isVirtualRegister ( SrcOp . getReg ( ) ) || SrcOp

. getReg ( ) == <STR_LIT> ) ) Src . push_back ( SrcOp ) ;