<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset ; if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister


<s> case GlobalValue :: WeakODRLinkage : case GlobalValue :: ExternalLinkage : case GlobalValue :: CommonLinkage : emitArrayBound ( GVSym , GV ) ; OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Global ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Weak ) ; LLVM_FALLTHROUGH ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; default : llvm_unreachable ( <STR_LIT> ) ; } EmitAlignment ( Align > <NUM_LIT> ? Align : <NUM_LIT> , GV ) ; if ( GV -> isThreadLocal ( ) ) { report_fatal_error ( <STR_LIT> ) ; } unsigned Size = DL . getTypeAllocSize ( C -> getType ( ) ) ; if ( MAI -> hasDotTypeDotSizeDirective ( ) ) { OutStreamer -> EmitSymbolAttribute (


<s> const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && isa < MemSDNode > ( Op ) ; Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! restrict_addressing_modes_for_nacl && Sh ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal )


<s> hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI ->


<s> return iterator_range < MCInst :: const_iterator > ( MCI . begin ( ) + bundleInstructionsOffset , MCI


<s> return TargetLowering :: shouldFormOverflowOp ( Opcode , VT


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef


<s> unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc ; LoadOpc = NeedAlign <= HasAlign ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; LoadOpc = NeedAlign <= MinAlign ( HasAlign , Size ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstHi ) . addFrameIndex ( FI ) . addImm


<s> isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumCyclesT , unsigned ExtraPredCyclesT , MachineBasicBlock &

FMBB , unsigned NumCyclesF , unsigned ExtraPredCyclesF , BranchProbability Probability ) const {


<s> if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; MBB . addSuccessor ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else return true


<s> unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && ! add ) imm =


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer &


<s> static void write_stmt ( FILE * out , const Stmt * stmt ) { if ( ( stmt -> vis & V_mask ) != V_comment ) { write_tokens ( out , stmt -> tokens , stmt -> len , ( stmt -> vis & V_mask ) == V_pred ) ; fputs ( stmt -> vis & V_no_eol ? <STR_LIT> :


<s> SmallVector < EVT , <NUM_LIT> > VTs ; ComputeValueVTs ( TLI , GV -> getParent ( ) -> getDataLayout ( ) , GV -> getValueType ( ) , VTs ) ; if ( VTs . size ( ) != <NUM_LIT> || TLI . getNumRegisters ( GV -> getParent ( ) -> getContext ( ) , VTs [ <NUM_LIT> ] ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; MVT VT = TLI . getRegisterType ( GV -> getParent ( ) -> getContext ( ) , VTs [ <NUM_LIT> ] ) ; bool Mutable = true ; <STR_LIT> Type = <STR_LIT> ( VT ) ; Sym -> setType ( <STR_LIT> ) ; Sym -> setGlobalType ( <STR_LIT> { uint8_t ( Type ) , Mutable } ) ; } emitVisibility ( Sym , GV -> getVisibility ( ) , ! GV -> isDeclaration ( ) ) ; if ( GV -> hasInitializer ( ) ) { assert ( getSymbolPreferLocal ( * GV ) == Sym ) ; emitLinkage ( GV , Sym ) ; getTargetStreamer ( ) -> emitGlobalType ( Sym ) ; OutStreamer -> emitLabel ( Sym ) ; OutStreamer -> AddBlankLine ( )


<s> StringRef getToken ( ) const { assert ( isToken ( )


<s> return :: getContainerForFixedLengthVector ( * this , VT , getSubtarget


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) { AlignmentIsInBytes = false ; PrivateGlobalPrefix =


<s> if ( TT . isArch64Bit ( ) && ! FeatureBits [ <STR_LIT> ] ) report_fatal_error ( <STR_LIT> ) ; if ( ! TT . isArch64Bit ( ) && FeatureBits [ <STR_LIT> ] ) report_fatal_error (


<s> if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand


<s> for ( i = <NUM_LIT> ; i < pool_size ; i ++ ) { pool_node * p = & pool_vector [ i ] ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label


<s> bool <ISA_LIT>CFGStructurizer :: isRetiredBlock ( MachineBasicBlock * MBB ) const { MBBInfoMap :: const_iterator It = BlockInfoMap . find ( MBB ) ; if ( It == BlockInfoMap . end


<s> rtx call [ <NUM_LIT> ] ; rtx insn ; int cookie_val = INTVAL ( cookie ) ; bool make_island = false ; if ( ( cookie_val & CALL_LONG ) != <NUM_LIT> && GET_CODE ( func_desc ) == SYMBOL_REF ) { if ( darwin_emit_branch_islands && TARGET_32BIT ) make_island = true ; else { func = rs6000_longcall_ref ( func_desc , NULL_RTX ) ; cookie_val &= ~ CALL_LONG ; } } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = gen_rtx_USE ( VOIDmode , GEN_INT ( cookie_val ) ) ; if ( sibcall ) call [ <NUM_LIT> ] = simple_return_rtx ; else call [ <NUM_LIT> ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( <NUM_LIT>


<s> static inline struct bpf_sock * bpf_get_listener_sock ( struct


<s> bool isABI_N64 ( ) const { return <ISA_LIT>ABI ==


<s> return TII -> getRegisterInfo ( ) . isSGPRReg ( * MRI , Reg ) && TII -> getRegisterInfo ( ) . getRegSizeInBits ( Reg , * MRI )


<s> static const uint8_t Nops [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OW -> write8 ( <NUM_LIT> ) ; return true ; } uint64_t MaxNopLength = <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) MaxNopLength =


<s> SDValue VecCstShift = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow


<s> return MFI -> getStackSize ( ) && ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF


<s> static SDValue performXORCombine ( SDNode * N , SelectionDAG & DAG ) { return combineSelectAndUseCommutative ( N ,


<s> bool isTargetWindowsCoreCLR ( ) const { return TargetTriple .


<s> if ( name [ len - <NUM_LIT> ] == ']' ) return

ggc_alloc_string ( name , len - <NUM_LIT> ) ;


<s> if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>

) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>8 ; case FK_Data_2 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>16 ; case FK_Data_4 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>30 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_H44


<s> UsesELFSectionDirectiveForBSS = true ; AllowAtInName = true ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid


<s> void <ISA_LIT>InstrInfo :: insertSelect ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DstReg , ArrayRef < MachineOperand > Cond , unsigned TrueReg , unsigned FalseReg ) const { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; const TargetRegisterClass & RC = * MRI . getRegClass ( DstReg ) ; assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( TRI . getRegSizeInBits ( RC ) / <NUM_LIT> , false ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addImm


<s> return ( arg . type != <NUM_LIT> && ( TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST || TREE_ADDRESSABLE ( arg


<s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( )


_mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> enum machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) { rtx tmp = gen_reg_rtx ( mode1 ) ; emit_move_insn ( tmp , op1 ) ; op1 = op0 ; op0 = tmp ; } if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; op2 = gen_rtx_fmt_ee ( comparison , mode0 , op0 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , RegNo ) ) ) ; return MCDisassembler


<s> unsigned Opc = Op . getOpcode ( ) ; bool IsPairOp = isHvxPairTy ( ty ( Op ) ) || llvm :: any_of ( Op . getNode ( ) -> ops ( ) , [ this ] ( SDValue V ) { return isHvxPairTy ( ty ( V ) ) ; } ) ; if ( IsPairOp ) { switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : return SplitHvxMemOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerHvxShift ( Op , DAG ) ; case <STR_LIT> : return LowerHvxMul ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerHvxMulh ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtend ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return SDValue ( ) ; } Op . dumpr ( & DAG ) ; llvm_unreachable (


<s> return new <ISA_LIT>MCLowerPrePass ( )


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT>


<s> rtx mask = gen_reg_rtx ( TImode ) ; rtx offset ; if ( GET_CODE ( ops [ <NUM_LIT> ] ) == CONST_INT ) offset = GEN_INT ( INTVAL ( ops [ <NUM_LIT> ] ) * GET_MODE_SIZE ( imode ) ) ; else { offset = gen_reg_rtx ( SImode ) ; emit_insn ( gen_mulsi3 ( offset , ops [ <NUM_LIT> ] , GEN_INT ( GET_MODE_SIZE ( imode ) ) ) ) ; } emit_insn ( gen_cpat ( mask , stack_pointer_rtx , offset , GEN_INT ( GET_MODE_SIZE ( imode ) ) ) ) ; emit_insn ( gen_shufb ( ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , mask


<s> emitGlobals ( M ) ; GlobalsEmitted = true ; } Module :: GlobalListType & global_list = M . getGlobalList ( ) ; int i , n = global_list . size ( ) ; GlobalVariable * * gv_array = new GlobalVariable * [ n ] ; i = <NUM_LIT> ; for ( Module :: global_iterator I = global_list . begin ( ) , E = global_list . end ( ) ; I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; delete [


<s> SUnit SU ( MI , <NUM_LIT> ) ; SU . isCall = MI -> isCall ( ) ; const MCSchedClassDesc * SC = SchedModel -> resolveSchedClass ( MI ) ; for ( const MCWriteProcResEntry & PRE : make_range ( SchedModel -> getWriteProcResBegin ( SC ) , SchedModel -> getWriteProcResEnd ( SC ) ) ) { switch ( SchedModel -> getProcResource ( PRE . ProcResourceIdx ) -> BufferSize ) { case <NUM_LIT> : SU . hasReservedResource = true


<s> SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( ) ; bool is64bit = Subtarget . is<ISA_LIT>64 ( ) ; TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( Model == TLSModel :: LocalExec ) { SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue GOTEntryHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTEntryHi , TGA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , GOTEntry ) ; SDValue ParmReg = DAG . getRegister


<s> bool <ISA_LIT>AsmParser :: ParseDirective (


<s> bool isUImm5 ( ) const { return isUImm < <NUM_LIT> > (


<s> assert ( useSVEForFixedLengthVectorVT ( InVT ) && <STR_LIT> ) ; assert ( Op . getValueType ( ) == InVT . changeTypeToInteger ( ) && <STR_LIT> ) ; if ( InVT . isFloatingPoint ( ) ) return SDValue ( ) ; auto Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; auto Op2 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; auto Pg = getPredicateForFixedLengthVector ( DAG , DL , InVT


<s> DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const16 ) ) ; status = DecodeOperandRegister ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; return MCDisassembler


<s> if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get (

<STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CalleeAmt ) ;


<s> EVT VT0 = Op0 . getValueType ( ) ; EVT VT1 = Op1 . getValueType ( ) ; if ( VT0 != VT1 || ! VT0 . isSimple ( ) || ! VT0 . isInteger ( ) ) return SDValue ( ) ; APInt SplatVal ; if ( ! <STR_LIT> ( Op1 . getNode ( ) , SplatVal ) || ! SplatVal . isMask ( ) ) return SDValue ( ) ; if ( isBitwiseNot ( Op0 ) ) return SDValue ( ) ; if ( ! SupportedVectorShiftWithImm ( VT0 . getSimpleVT ( ) , Subtarget , <STR_LIT> ) ) return SDValue ( ) ; unsigned EltBitWidth = VT0 . getScalarSizeInBits ( ) ; if ( EltBitWidth != DAG . ComputeNumSignBits ( Op0 ) ) return SDValue ( ) ; SDLoc DL ( N


<s> else if ( trySkipId ( <STR_LIT> ) ) CPolOff = <STR_LIT> :: DLC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOn = <STR_LIT> :: SCC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOff = <STR_LIT> :: SCC ; else return MatchOperand_NoMatch ; if ( ! isGFX10Plus ( ) && ( ( CPolOn | CPolOff ) & <STR_LIT> :: DLC ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! isGFX90A ( ) && ( ( CPolOn | CPolOff ) & <STR_LIT> :: SCC ) ) { Error ( S , <STR_LIT> ) ; return


<s> case <NUM_LIT> : ParseBytes = PrintAsEncoded ; break ; case <NUM_LIT> : ParseBytes = PrintCallAsBytes ; break ; case <NUM_LIT> : ParseBytes =


<s> Clone ( FeatureBitset FeatureMask , Function * OrigF


<s> if ( SPDiff ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * FL = Subtarget . getFrameLowering ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; int NewRetAddrLoc = SPDiff + FL -> getReturnSaveOffset ( ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( MF , NewRetAddr ) ) ; if ( Subtarget . isDarwinABI ( ) ) { int NewFPLoc = SPDiff + FL -> getFramePointerSaveOffset ( ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc ,


<s> OS << MAI -> getCommentString ( ) <<


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; int types [ ] = { ( int ) <STR_LIT> , ( int ) <STR_LIT> } ; size_t NumTypes = sizeof ( types ) / sizeof ( * types ) ; for ( unsigned int x = <NUM_LIT> ; x < NumTypes ; ++ x ) { <STR_LIT> VT = ( <STR_LIT> ) types [ x ] ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT


<s> virtual const char * getPassName ( ) const { return


<s> <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl ,


<s> GA = dyn_cast < GlobalAddressSDNode > ( V -> getOperand ( <NUM_LIT> ) ) ; if ( V -> getOpcode ( ) != <STR_LIT> || V -> getNumOperands ( ) != <NUM_LIT> || ! GA ) return false ; SDValue IdxV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base -> getOperand ( <NUM_LIT> ) , V -> getOperand (


<s> void <ISA_LIT>RegisterInfo :: storeToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , int Offset , DebugLoc dl ) const { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printBankMask ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT>


<s> for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_RequiresFlagSetting ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; if ( Opc == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; } else if ( isThumbOne ( ) ) { if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } if ( Opc == <STR_LIT> && ! hasV8Ops ( ) ) { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresV8 ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return Match_RequiresV8 ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ( isThumb ( ) && ! hasV8Ops ( ) ) ) return Match_InvalidOperand ; break ; default : break ; } for ( unsigned I = <NUM_LIT> ; I < MCID . NumOperands ; ++ I ) if ( MCID

. OpInfo [ I ] . RegClass == <STR_LIT> ) {


<s> std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return


<s> for ( unsigned Idx = <NUM_LIT> ; Idx < NumElts ; ++ Idx ) { SDValue V = N -> getOperand ( Idx ) ; if ( V . isUndef ( ) ) continue ; if ( V . getOpcode ( ) == <STR_LIT> && V -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; else { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , <STR_LIT> , V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } SDValue LaneIdx = DAG . getConstant ( Idx , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , V , LaneIdx ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ; DCI . AddToWorklist ( Vec . getNode ( )


<s> int64_t Min = - ( <NUM_LIT> * ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ; int64_t Max = <NUM_LIT> * ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) ; return ( Val % <NUM_LIT> ) == <NUM_LIT> && Val >= Min && Val <= Max ; } return true


<s> if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && PatternNodeWithChain . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; PatternNodeWithChain = SDValue ( LD , <NUM_LIT> ) ; return true ; } return


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) ,


<s> static bool isZero ( Register Reg , const MachineRegisterInfo & MRI ) { int64_t Val ; return mi_match ( Reg , MRI , m_ICst (


<s> switch ( getKind ( ) ) { default : return ; case VK_<ISA_LIT>_TPREL_HI


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; IndirectTlsSegRefs = MF . getFunction (


<s> InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , DstReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , true , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( - <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , DstReg , CntReg , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , true , RegCtx , Ctx ,


<s> unsigned TruncBits = <NUM_LIT> ; unsigned SExtBits = <NUM_LIT> ; unsigned ZExtBits = <NUM_LIT> ; if ( UserI -> hasOneUse ( ) ) { unsigned UserBits = UserI -> getType ( ) -> getScalarSizeInBits ( ) ; if ( isa < TruncInst > ( UserI ) ) TruncBits = UserBits ; else if ( isa < SExtInst > ( UserI ) ) SExtBits = UserBits ; else if ( isa < ZExtInst > ( UserI ) ) ZExtBits = UserBits ; } if ( TruncBits || SExtBits || ZExtBits ) { FoldedValue = UserI ; UserI = cast < Instruction > ( * UserI -> user_begin ( ) ) ; } if ( ( UserI -> getOpcode ( ) == Instruction :: Sub || UserI -> getOpcode ( ) == Instruction :: SDiv || UserI -> getOpcode ( ) == Instruction :: UDiv ) && UserI -> getOperand ( <NUM_LIT> ) != FoldedValue ) return false ; unsigned LoadOrTruncBits = ( ( SExtBits || ZExtBits ) ? <NUM_LIT> : ( TruncBits ? TruncBits : LoadedBits ) ) ; switch ( UserI -> getOpcode ( ) ) { case Instruction :: Add : case Instruction ::


<s> MVT LogicVT ; MVT EltVT ; unsigned NumElts ; if ( VT . isVector ( ) ) { LogicVT = VT ; EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } else if ( IsF128 ) { LogicVT = <STR_LIT> ; EltVT = VT ; NumElts = <NUM_LIT> ; } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; NumElts = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) || IsF128 ) return DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; Operand = DAG . getNode ( <STR_LIT> , dl , LogicVT , Operand ) ; SDValue LogicNode = DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LogicNode

, DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + <NUM_LIT> ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if (


<s> if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( !


<s> static void ix86_add_cfa_restore_note ( rtx_insn * insn , rtx reg , HOST_WIDE_INT cfa_offset ) { if ( ! crtl -> shrink_wrapped && cfa_offset <= cfun -> machine -> fs . red_zone_offset ) return ; if ( insn ) { add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT>


<s> return MCDisassembler :: Fail ; } uint32_t insn32 = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return result ; } MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb232 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFP32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } } MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFPV832 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableNEONDup32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONLdStInsn = insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail )


<s> unsigned <ISA_LIT>MCCodeEmitter :: getAddSubImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; unsigned FixupKind = <NUM_LIT> ; switch ( cast < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_AARCH64_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_HI12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_LO12_NC : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT>


<s> bool <ISA_LIT>MCInstrInfo :: isPrefix ( MCInstrInfo const & MCII , MCInst const & MCI ) { return <STR_LIT> == <ISA_LIT>MCInstrInfo :: getType ( MCII ,


<s> emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_move_insn ( mem ,


<s> HOST_WIDE_INT no_flag = flags [ i ] . no_flag ; if ( ( rs6000_isa_flags & no_flag ) == <NUM_LIT> && ( rs6000_isa_flags_explicit & no_flag ) != <NUM_LIT> ) { HOST_WIDE_INT dep_flags = flags [ i ] . dep_flags ; HOST_WIDE_INT set_flags = ( rs6000_isa_flags_explicit & rs6000_isa_flags & dep_flags ) ; if ( set_flags ) { for ( j = <NUM_LIT> ; j < ARRAY_SIZE ( rs6000_opt_masks ) ; j ++ ) if ( ( set_flags & rs6000_opt_masks [ j ] . mask ) != <NUM_LIT> ) { set_flags &= ~ rs6000_opt_masks [ j ] . mask ; error ( <STR_LIT> , flags [ i ] . name , rs6000_opt_masks [ j


<s> if ( LoadVT . isVector ( ) ) { EquivLoadVT = Unpacked ? UnpackedLoadVT : getEquivalentMemType ( * DAG . getContext ( ) , LoadVT ) ; } SDVTList VTList = DAG . getVTList ( EquivLoadVT , <STR_LIT> ) ; SDValue Load = DAG . getMemIntrinsicNode ( IsIntrinsic ? <STR_LIT> : Opcode , DL , VTList , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; SDValue Adjusted = adjustLoadValueTypeImpl ( Load , LoadVT , DL , DAG , Unpacked ) ; return DAG . getMergeValues ( { Adjusted , Load . getValue ( <NUM_LIT> ) } ,


<s> return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace ,


<s> if ( TARGET_CLD || cfun -> machine -> func_type != TYPE_NORMAL ) return X86_DIRFLAG_ANY ; return X86_DIRFLAG_RESET


<s> static void fail ( SDLoc DL , SelectionDAG & DAG , const char * msg ) { MachineFunction & MF = DAG


<s> else basereg = <NUM_LIT> ; } { if ( mode == VOIDmode ) return alpha_arg_info_reg_val ( * cum ) ; num_args = cum -> num_args ; if ( num_args >= <NUM_LIT> || targetm . calls . must_pass_in_stack ( mode , type ) ) return NULL_RTX ; } { if ( * cum >= <NUM_LIT> ) return NULL_RTX ; num_args = * cum


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter >


<s> BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg


<s> } } if ( cfun -> machine -> funtype && ( TREE_CODE ( cfun -> machine -> funtype ) == FUNCTION_TYPE || TREE_CODE ( cfun -> machine -> funtype ) == METHOD_TYPE ) && stdarg_p ( cfun -> machine -> funtype ) ) { has_varargs = true ; cfun -> machine -> has_call_with_varargs = true ; } vec = rtvec_alloc ( nargs + <NUM_LIT> + ( has_varargs ? <NUM_LIT> : <NUM_LIT> ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( has_varargs ) { rtx this_arg = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_move_insn ( this_arg , stack_pointer_rtx ) ; else emit_move_insn ( this_arg , stack_pointer_rtx ) ; XVECEXP ( pat , <NUM_LIT> , nargs + <NUM_LIT> ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } int i ; rtx arg ; for ( i = <NUM_LIT> , arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , <NUM_LIT> ) , i ++ ) { rtx this_arg = XEXP ( arg , <NUM_LIT> ) ; XVECEXP ( pat , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } rtx tmp_retval = retval ; t = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; if ( retval != NULL_RTX ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; t = gen_rtx_SET ( VOIDmode , tmp_retval , t ) ; } XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) = t ; if ( ! REG_P ( callee ) && ( decl_type == NULL_TREE || ( external_decl && TYPE_ARG_TYPES ( decl_type ) == NULL_TREE ) ) ) { rtx * slot = declared_libfuncs_htab -> find_slot ( callee , INSERT ) ; if ( * slot == NULL ) { * slot = callee ; write_func_decl_from_insn ( func_decls , retval , pat ,


<s> tmpInst . addOperand ( MCOperand :: createImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= - <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT>


<s> DINodeArray Elements = CTy -> getElements ( ) ; uint32_t VLen = Elements . size ( ) ; if ( VLen > <STR_LIT> ) return ; auto TypeEntry = llvm :: make_unique < BTFTypeEnum > ( CTy , VLen ) ; addType ( std :: move ( TypeEntry


<s> for ( const std :: pair < unsigned , RegisterCell > P : Map ) dbgs ( ) << PrintReg ( P . first , & ME .

TRI ) << <STR_LIT> << P . second << <STR_LIT> ;


<s> bool mips_pad_arg_upward ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type != <NUM_LIT> ? ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || FIXED_POINT_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) ) return false ; if ( mips_abi == ABI_O64 ) if ( type != <NUM_LIT> ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return false ; if ( mips_abi != ABI_EABI ) return


<s> assert ( Op . getValueType ( ) . is128BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Val = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; MF . getFrameInfo ( ) -> setFrameAddressIsTaken ( true ) ; SDLoc DL ( Op ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant

( FuncInfo -> getVarArgsFrameOffset ( ) , DL ) ) ;


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim


<s> const DenseMap < int , unsigned > & getWinEHXMMSlotInfo ( ) const { return WinEHXMMSlotInfo ;


<s> bool <ISA_LIT>InsertWaitcnts :: mayAccessLDSThroughFlat ( const MachineInstr & MI ) const { assert ( TII -> isFLAT ( MI ) ) ; if ( ! TII -> usesLGKM_CNT (


<s> unsigned b = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( addr ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { assert ( SyntaxVariant == <NUM_LIT>


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr


<s> if ( ! Defs . count ( P ) || LatePreds . count ( P ) || Defs . count ( <STR_LIT> ) ) { reportErrorNewValue ( P ) ; return false ; } } for ( const auto & I : LatePreds ) { unsigned P = I ; if ( LatePreds . count ( P ) > <NUM_LIT> || Defs . count ( P ) ) { reportErrorRegisters ( P ) ; return


<s> It != E ; ++ It ) { if ( It -> getOpcode ( ) == AMDGPU :: CF_ALU || It -> getOpcode ( ) == AMDGPU :: CF_ALU_PUSH_BEFORE ) return llvm :: prior ( It . base ( ) ) ; } return MBB . end (


<s> unsigned ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; ArrayRef < MCPhysReg > AllSGPRs = getAllSGPRs ( MF , TRI ) ; if ( NumPreloaded > AllSGPRs . size ( ) ) return ScratchWaveOffsetReg ; AllSGPRs = AllSGPRs . slice ( NumPreloaded ) ; if ( AllSGPRs . size ( ) < <NUM_LIT> ) return ScratchWaveOffsetReg ; for ( MCPhysReg Reg : AllSGPRs . drop_back ( <NUM_LIT>


<s> static const MCPhysReg DataRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg AddrRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const auto & ArgTypes = CCInfo . ArgTypeList ; auto I = ArgTypes . begin ( ) , End = ArgTypes . end ( ) ; int No = ValNo ; while ( No > <NUM_LIT> && I != End ) { No -= ( * I ) -> isIntegerTy ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ++ I


<s> rtx op1 = XEXP ( addis_value , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) && satisfies_constraint_L ( op1 ) ) { fuse_ops [ <NUM_LIT> ] = op0 ; fuse_ops [ <NUM_LIT> ] = op1 ; addis_str = <STR_LIT> ; } } else if ( GET_CODE ( addis_value ) == HIGH ) { rtx value = XEXP ( addis_value , <NUM_LIT> ) ; if ( GET_CODE ( value ) == UNSPEC && XINT ( value , <NUM_LIT> ) == UNSPEC_TOCREL ) { fuse_ops [ <NUM_LIT> ] = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_ELF ) addis_str = <STR_LIT> ; else if ( TARGET_XCOFF ) addis_str = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( GET_CODE ( value ) == PLUS ) { rtx op0 = XEXP ( value , <NUM_LIT> ) ; rtx op1 = XEXP ( value , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == UNSPEC && XINT ( op0 , <NUM_LIT> ) == UNSPEC_TOCREL && CONST_INT_P ( op1 ) ) { fuse_ops [ <NUM_LIT> ] = XVECEXP ( op0 , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( op0 , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] =


<s> align_rtx = expand_binop ( Pmode , and_optab , scratch1 , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_2_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , GTU , NULL , Pmode , <NUM_LIT> , align_3_label ) ; } else { align_rtx = expand_binop ( Pmode , and_optab , scratch1 , const2_rtx , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; } mem = change_address ( src , QImode , out ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( gen_add2_insn ( out , const1_rtx ) ) ; if ( align != <NUM_LIT> ) { emit_label ( align_2_label ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( gen_add2_insn ( out , const1_rtx ) ) ; emit_label ( align_3_label ) ; } emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( gen_add2_insn ( out , const1_rtx ) ) ; } emit_label ( align_4_label ) ; mem = change_address ( src , SImode , out ) ; emit_move_insn ( scratch , mem ) ; emit_insn ( gen_add2_insn ( out , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addsi3 ( tmpreg , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_one_cmplsi2 ( scratch , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , gen_int_mode ( <NUM_LIT> , SImode ) ) ) ; emit_cmp_and_jump_insns ( tmpreg , const0_rtx , EQ , <NUM_LIT> ,


<s> MemOps . push_back ( MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugValue ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps ) ; auto LessThan = [ ] ( const MergeCandidate * M0 , const MergeCandidate * M1 ) { return M0 -> InsertPos < M1 -> InsertPos ; } ; std :: sort ( Candidates . begin ( ) , Candidates . end ( ) , LessThan ) ; bool Changed = false ; for ( const MergeCandidate * Candidate : Candidates ) { if ( Candidate -> CanMergeToLSMulti || Candidate


<s> if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget


<s> * no_add_attrs = true ; } if ( m68k_get_function_kind ( * node ) != m68k_fk_normal_function ) { error ( <STR_LIT> ) ; * no_add_attrs = true ; } if ( ! TARGET_FIDOA && ! strcmp ( IDENTIFIER_POINTER ( name ) , <STR_LIT> ) ) { error ( <STR_LIT> ) ; * no_add_attrs = true ; } return


<s> return CONST_INT_P ( val ) && INTVAL ( val ) == trunc_int_for_mode (

HOST_WIDE_INT_C ( <NUM_LIT> ) , mode ) ;


<s> static SDValue getTargetNode ( ExternalSymbolSDNode * N , SDLoc DL , EVT Ty ,


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsTbx = true ; Layout = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsTbx = false ; Layout =


<s> Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , DAG ) ; Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , DAG ) ; } for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) / <NUM_LIT> ; i < e ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Regs [ i * <NUM_LIT> ] ,


<s> Inst . addOperand ( MCOperand :: createReg ( getCheriReg0IsDDC ( )


<s> if ( GET_CODE ( x ) == HIGH ) return true ; split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x ) ) return


<s> void addUImm4Operands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return ST . get<ISA_LIT>AS ( ) . CONSTANT_ADDRESS ; } return ST . get<ISA_LIT>AS (


<s> ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t


<s> printOperand ( MI -> getOperand ( OpNum ) ,


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( Node -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; return NULL ; } switch ( Node ->


<s> Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) && ! Subtarget -> slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , VT ) ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; Op = New ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ; if ( EFLAGS . getNode ( ) ) return EFLAGS ; } Opcode = <STR_LIT> ; break ; } } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode


<s> PrivateLabelPrefix = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling ::


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( )


<s> PM . add ( create<ISA_LIT>FPMoverPass ( * this ) ) ; PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB ,

MachineBasicBlock :: iterator MBBI ) const {


<s> machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , <NUM_LIT> , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , res ,


<s> bool SVEVecStackRegion :: allocatesType ( const Type * Type ) const { if ( auto ST = dyn_cast < StructType > ( Type ) ) if ( std :: equal ( ST -> element_begin ( ) , ST -> element_end ( ) , ST -> element_begin ( ) ) ) return ( ST -> getNumElements ( ) != <NUM_LIT> ) ? allocatesType ( * ST -> element_begin ( ) ) : false ; if ( isa < ArrayType > ( Type ) ) return allocatesType ( cast < ArrayType > ( Type ) -> getElementType ( ) ) ; const VectorType * VT = dyn_cast < const VectorType > ( Type ) ; if ( IsPredicateRegion ) return VT && VT -> isScalable ( ) && ( VT -> getBitWidth ( ) % <NUM_LIT> > <NUM_LIT> ) ; else return VT && VT -> isScalable ( ) && ( VT

-> getBitWidth ( ) % <NUM_LIT> == <NUM_LIT> ) ;


<s>
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
<ISA_LIT>MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
<ISA_LIT>MachineFunctionInfo
>
(
)
;
OutStreamer
->
emitRawComment
(
Twine
(
<STR_LIT>
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
OutStreamer
->
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
<STR_LIT>
+
HexLines
[
i
]
+
<STR_LIT>
;
OutStreamer
->
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = TFI -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - Amount ) . addReg ( <STR_LIT> ) ; } else


<s> if ( StubSym == <NUM_LIT> ) StubSym = GetGlobalValueSymbol ( GV ) ; } } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; O << * GetExternalSymbolSymbol ( ACPV -> getSymbol ( ) ) ; } if ( ACPV -> hasModifier ( ) ) O << <STR_LIT> << ACPV -> getModifier ( ) << <STR_LIT> ; if ( ACPV -> getPCAdjustment ( ) != <NUM_LIT> ) { O << <STR_LIT> << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << ACPV -> getLabelId ( ) << <STR_LIT> << ( unsigned ) ACPV -> getPCAdjustment ( ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) O << <STR_LIT> ; O << ')'


<s> FunctionPass * llvm :: create<ISA_LIT>MergeBaseOffsetOptPass ( ) { return new <ISA_LIT>MergeBaseOffsetOpt (


<s> bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; return


<s> if ( m == NULL ) { start_sequence ( ) ; m = assign_stack_local ( DImode , UNITS_PER_WORD , BITS_PER_WORD ) ; m = validize_mem ( m ) ; emit_move_insn ( m , pic_offset_table_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_after ( seq , entry_of_function ( )


<s> const std :: vector < <ISA_LIT>Section * > & UDATASections ( ) const { return


<s> SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE


<s>
if
(
ReadyBlocks
.
empty
(
)
)
return
nullptr
;
DAG
->
fillVgprSgprCost
(
LiveRegs
.
begin
(
)
,
LiveRegs
.
end
(
)
,
VregCurrentUsage
,
SregCurrentUsage
)
;
if
(
VregCurrentUsage
>
maxVregUsage
)
maxVregUsage
=
VregCurrentUsage
;
if
(
VregCurrentUsage
>
maxSregUsage
)
maxSregUsage
=
VregCurrentUsage
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
<ISA_LIT>ScheduleBlock
*
Block
:
ReadyBlocks
)
dbgs
(
)
<<
Block
->
getID
(
)
<<
' '
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
LiveRegs
)
dbgs
(
)
<<
PrintVRegOrUnit
(
Reg
,
DAG
->
getTRI
(
)
)
<<
' '
;
dbgs
(
)
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
VregCurrentUsage
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
SregCurrentUsage
<<
'\n'
;
)
;
Cand
.
Block
=
nullptr
;
for
(
std
::
vector
<
<ISA_LIT>ScheduleBlock
*
>
::
iterator
I
=
ReadyBlocks
.
begin
(
)
,
E
=
ReadyBlocks
.
end
(
)
;
I
!=
E
;
++
I
)
{
<ISA_LIT>BlockSchedCandidate
TryCand
;
TryCand
.
Block
=
*
I
;
TryCand
.
IsHighLatency
=
TryCand
.
Block
->
isHighLatencyBlock
(
)
;
TryCand
.
VGPRUsageDiff
=
checkRegUsageImpact
(
TryCand
.
Block
->
getInRegs
(
)
,
TryCand
.
Block
->
getOutRegs
(
)
)
[
DAG
->
getVGPRSetID
(
)
]
;
TryCand
.
NumSuccessors
=
TryCand
.
Block
->
getSuccs
(
)
.
size
(
)
;
TryCand
.
NumHighLatencySuccessors
=
TryCand
.
Block
->
getNumHighLatencySuccessors
(
)
;
TryCand
.
LastPosHighLatParentScheduled
=
(
unsigned
int
)
std
::
max
<
int
>
(
<NUM_LIT>
,
LastPosHighLatencyParentScheduled
[
TryCand
.
Block
->
getID
(
)
]
LastPosWaitedHighLatency
)
;
TryCand
.
Height
=
TryCand


<s> void <ISA_LIT>PassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( )


<s> if ( ( ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) && ( ( TARGET_FLOATXX && ! ISA_HAS_MXHC1 ) || TARGET_O32_FP64A_ABI ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return true ; return false


<s> const int * EHSlot = XFI -> getEHSpillSlot ( ) ; SpillList . push_back ( StackSlotInfo ( EHSlot [ <NUM_LIT> ] , MFI . getObjectOffset ( EHSlot [ <NUM_LIT> ] ) , TL -> getExceptionPointerRegister ( PersonalityFn ) ) ) ; SpillList . push_back ( StackSlotInfo ( EHSlot [ <NUM_LIT> ] , MFI . getObjectOffset ( EHSlot [ <NUM_LIT> ] ) ,

TL -> getExceptionSelectorRegister ( PersonalityFn ) ) ) ;


<s> bool MVETailPredication :: runOnLoop ( Loop * L , LPPassManager & ) { if ( skipLoop ( L ) || ! EnableTailPredication ) return false ; MaskedInsts . clear ( ) ; Function & F = * L -> getHeader ( ) -> getParent ( ) ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; this -> L = L ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) { if ( ! Preheader -> getSinglePredecessor ( ) ) return false ; Setup = FindLoopIterations ( Preheader -> getSinglePredecessor ( ) ) ; if ( ! Setup ) return false ; } IntrinsicInst * Decrement


<s> unsigned getCSRFirstUseCost ( ) const override


<s> for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - <NUM_LIT> ] = true ; if ( bitmap_bit_p ( components , <NUM_LIT> ) ) cfun ->

machine -> lr_is_wrapped_separately = true ;


<s> if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second -> getOperand ( Second -> getNumOperands ( ) - <NUM_LIT> ) ; if ( ! Stored . isReg ( ) ) return


<s> initializeAnnotationsInferencePass ( * PassRegistry ::


<s> if ( SP ) { std :: string FunctBeginSym = <STR_LIT> + FunctName ; std :: string BlockBeginSym = <STR_LIT> + FunctName ; int FunctBeginLine = SP -> getLineNumber ( ) ; int BFAux [ <STR_LIT> ]


<s> static unsigned int rest_of_handle_insert_vzeroupper ( void ) { for ( int i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ] = <NUM_LIT> ; g -> get_passes ( ) -> execute_pass_mode_switching ( ) ; df_analyze ( ) ; return <NUM_LIT>


<s> static inline AMSubMode getAM5SubMode ( unsigned


<s> return DAG . getTargetConstant ( ( unsigned ) CN -> getZExtValue ( )


<s> if ( ! isSingleSpacedVectorIndexed ( ) )


<s> if ( funcInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . useFastISel ( ) ) return

new <ISA_LIT>FastISel ( funcInfo , libInfo ) ;


<s> if ( GepI -> idx_begin ( ) == GepI -> idx_end ( ) ) return false ; return true


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc StartLoc , SMLoc EndLoc , bool NeedRewrite = true ) { <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Immediate , StartLoc , EndLoc ) ; Res -> Imm . Val = Val ; Res -> Imm . NeedAsmRewrite = NeedRewrite ; return


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBBI . getNumber ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ) ; } FallthroughMap [ & MBBI ] =


<s> if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; if ( MBB -> empty ( ) ) return true ; return ( MBB -> back ( ) . getOpcode ( )


<s> EmitMappingSymbol ( <STR_LIT> ) ; LastEMS =


<s> assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; case <STR_LIT> : BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; default : { unsigned Opc = GetCondBranchFromCond ( CC ) ; BuildMI ( & MBB , DL , get ( Opc ) ) . addMBB ( TBB ) ; ++


<s> IterTy CurrI = I ; ++ I ; if ( CurrI -> isDebugValue ( ) ) continue ; if ( terminateSearch ( * CurrI ) ) break ; assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; if ( IsReverseIter && I != End ) I = CurrI ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; Filler =


<s> bool isTargetELF ( ) const { return TargetTriple . isOSBinFormatELF (


<s> void <ISA_LIT>CodeEmitter :: addPCLabel ( unsigned LabelID ) { DOUT << <STR_LIT> << LabelID << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << '\n' ; JTI -> addPCLabelAddr ( LabelID , MCE .


<s> if ( d -> parm [ <NUM_LIT> ] != SPU_BTI_VOID ) ops [ i ++ ] = target ; for ( a = <NUM_LIT> ; d -> parm [ a + <NUM_LIT> ] != SPU_BTI_END_OF_PARAMS ; i ++ , a ++ ) { tree arg = CALL_EXPR_ARG ( exp , a ) ; if ( arg == <NUM_LIT> ) abort ( ) ; ops [ i ] = expand_expr ( arg , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; } gcc_assert ( i == insn_data [


<s> static void nvptx_init_builtins ( void ) { ( nvptx_builtin_decls [ NVPTX_BUILTIN_ ## ID ] \ = add_builtin_function ( <STR_LIT> NAME , \ build_function_type_list T , \ NVPTX_BUILTIN_ ## ID , BUILT_IN_MD , NULL , NULL ) ) DEF ( SHUFFLE , <STR_LIT> , ( UINT , UINT , UINT , UINT , NULL_TREE ) ) ; DEF ( SHUFFLELL , <STR_LIT> , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( VECTOR_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , <STR_LIT> , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAPLL , <STR_LIT> , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ; DEF ( MEMBAR_GL , <STR_LIT> , ( VOID , VOID , NULL_TREE ) ) ; DEF ( MEMBAR_CTA , <STR_LIT> , ( VOID , VOID ,


<s> const APInt * CV = & C -> getAPIntValue ( ) ; return CV -> isPowerOf2 ( )


<s> const uint8_t * <ISA_LIT>ToTHMStub :: getContent


<s> if ( reg != mips_epilogue . cfa_reg || offset != mips_epilogue . cfa_offset ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , plus_constant ( Pmode , reg , offset ) , REG_NOTES ( insn ) ) ; mips_epilogue . cfa_reg = reg ; mips_epilogue . cfa_offset =


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget ::


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size

, Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const {


<s> PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ; MachineBasicBlock :: succ_iterator I , E = SuccB -> succ_end ( ) ; for ( I = SuccB -> succ_begin ( ) ; I != E ; ++ I ) PredB -> addSuccessor ( * I ) ; PredB -> normalizeSuccProbs ( ) ; replacePhiEdges ( SuccB , PredB ) ; removeBlock ( SuccB


<s> Has<ISA_LIT>_64 = true ; HasCMov = true ; } DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! Is64Bit || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( TT . length ( ) > <NUM_LIT> ) { size_t Pos ; if ( ( Pos = TT . find ( <STR_LIT> ) ) != std :: string :: npos ) { TargetType = isDarwin ; if ( isdigit ( TT [ Pos + <NUM_LIT> ] ) ) DarwinVers = atoi ( & TT [ Pos + <NUM_LIT> ] ) ; else DarwinVers = <NUM_LIT> ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isELF ; } else if ( TT . find ( <STR_LIT> ) != std :: string :: npos ) { TargetType = isCygwin


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand (


<s> Register <ISA_LIT>InstructionSelector :: buildOnesVal ( bool AllOnes , const <ISA_LIT>Type * ResType , MachineInstr & I ) const { unsigned BitWidth = GR . getScalarOrVectorBitWidth ( ResType ) ; APInt One = AllOnes ? APInt :: getAllOnesValue ( BitWidth ) :

APInt :: getOneBitSet ( BitWidth , <NUM_LIT> ) ;


<s> int zap_mask ( HOST_WIDE_INT value ) { int i ; for ( i = <NUM_LIT> ; i


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Builder . CreateCall ( llvm :: <STR_LIT> ( M , <STR_LIT> )


<s> if ( LaneMask . all ( ) || TargetRegisterInfo :: isPhysicalRegister ( Reg ) || LaneMask == MRI -> getMaxLaneMaskForVReg ( Reg ) ) { Func ( <NUM_LIT> ) ; return ; } const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; unsigned E = TRI -> getNumSubRegIndices ( ) ; SmallVector < unsigned , <STR_LIT> > CoveringSubregs ; for ( unsigned Idx = <NUM_LIT> ; Idx < E ; ++ Idx ) { if ( TRI -> getSubClassWithSubReg ( RC , Idx ) != RC ) continue ; LaneBitmask SubRegMask = TRI -> getSubRegIndexLaneMask ( Idx ) ; if ( SubRegMask == LaneMask ) { Func ( Idx ) ; return ; } if ( ( SubRegMask & ~ LaneMask ) . any ( ) || ( SubRegMask & LaneMask ) . none ( ) ) continue ; CoveringSubregs . push_back ( Idx ) ; } llvm :: sort ( CoveringSubregs , [ this ] ( unsigned A , unsigned B ) { LaneBitmask MaskA = TRI -> getSubRegIndexLaneMask ( A ) ; LaneBitmask MaskB = TRI -> getSubRegIndexLaneMask ( B ) ; unsigned NA = MaskA . getNumLanes ( ) ; unsigned NB = MaskB . getNumLanes ( ) ; if ( NA != NB ) return NA > NB ; return MaskA . getHighestLane ( ) > MaskB . getHighestLane ( ) ; } ) ; for ( unsigned Idx :


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_PHI && <STR_LIT> ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstRB = MRI . getRegBankOrNull ( DstReg ) ; assert ( DstRB && <STR_LIT> ) ; MachineIRBuilder MIB ( MI ) ; for ( unsigned OpIdx = <NUM_LIT> ; OpIdx < MI . getNumOperands ( ) ; ++ OpIdx ) { MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) continue ; Register OpReg = MO . getReg ( ) ; const RegisterBank * RB = MRI . getRegBankOrNull ( OpReg ) ; if ( RB != DstRB ) { auto * OpDef = MRI . getVRegDef ( OpReg ) ; const LLT & Ty = MRI . getType ( OpReg ) ; MIB . setInsertPt ( * OpDef -> getParent ( ) , std :: next ( OpDef -> getIterator ( ) ) ) ; auto Copy = MIB . buildCopy ( Ty , OpReg ) ; MRI . setRegBank ( Copy . getReg ( <NUM_LIT> ) , * DstRB ) ; MO . setReg ( Copy . getReg


<s> return ( vector unsigned short ) __builtin_altivec_vslh ( ( vector signed short ) a1 , ( vector signed short )


<s> auto Res = tryParseScalarRegister ( RegNo ) ; EndLoc = SMLoc :: getFromPointer ( getLoc ( )


<s> return getIntrinsicInstrCost < Type > ( ID , RetTy , Tys ,


<s> const MCExpr * Disp ; const MCExpr * Length ; if ( parseAddress ( Base , Disp , Index , IsVector , Length , Regs , RegKind ) ) return MatchOperand_ParseFail ; if ( IsVector && MemKind != BDVMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! IsVector && MemKind == BDVMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Index && MemKind != BDXMem && MemKind != BDVMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Length && MemKind != BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! Length && MemKind == BDLMem ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail


<s> return ( __m128i ) __builtin_ia32_pmaxud128 ( ( __v4si


<s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> )


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier


<s> for ( unsigned int pi = <NUM_LIT> ; group . preds [ pi ]

!= NUM_PREDS ; ++ pi ) for ( unsigned int ti = <NUM_LIT> ;


<s> static SDValue PerformFNEGCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SVT = VT . getScalarType ( ) ; SDValue Arg = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) -> hasNoSignedZeros ( ) && Subtarget -> hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL ,


<s> unsigned IID = getIntrinsicID ( N1 . getNode ( ) ) ; if ( IID == <STR_LIT> || N1 . getOpcode ( ) == <STR_LIT> || IID == <STR_LIT> || N1 . getOpcode ( ) == <STR_LIT> ) return N0 . getOpcode ( ) != <STR_LIT> ; return


<s> switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_lds : return Operand . isLDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot


<s> bool isPredicateRegister ( unsigned R ) const { return ( <STR_LIT> == R || <STR_LIT> == R || <STR_LIT> ==


<s> const MCOperand & Operand = Inst . getOperand ( Inst . getNumOperands ( ) - <NUM_LIT> ) ; assert ( Operand . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Operand . getExpr ( ) ; const MCSymbolRefExpr * SymExpr = static_cast < const MCSymbolRefExpr * > ( Expr ) ; assert ( SymExpr -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT && <STR_LIT> ) ; MCSymbol * LabelSym = getContext ( ) . getOrCreateSymbol ( SymExpr -> getSymbol ( ) . getName ( ) ) ; emitLabel ( LabelSym , Inst .


<s> return EltSize == <NUM_LIT> || EltSize == <NUM_LIT> || ( EltSize == <NUM_LIT> && Ty . getNumElements ( ) % <NUM_LIT> == <NUM_LIT> ) || EltSize == <NUM_LIT>


<s> return ( __m512 ) __builtin_ia32_vpermilvarps512_mask ( ( __v16sf ) __A , ( __v16si ) __C , ( __v16sf ) _mm512_setzero_ps ( ) ,


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_SHUFFLE_VECTOR ) ; auto MaybeLane = getSplatIndex ( MI ) ; if ( ! MaybeLane ) return false ; int Lane =


<s> void GCNHazardRecognizer :: RecedeCycle ( ) { llvm_unreachable ( <STR_LIT>


<s> bool SelectAddrModeUnscaled64 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeUnscaled ( N , <NUM_LIT> , Base


<s> machine_mode mode , cmp_mode ; bval = operands [ <NUM_LIT> ] ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = operands [ <NUM_LIT> ] ; mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_THUMB1 ) cmp_mode = E_SImode ; else cmp_mode = CC_Zmode


<s> if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) << ']' ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( ImmOffs || ( op == <STR_LIT> ) ) O << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs ; O << ']'


<s> if ( ! H_REG_P ( operands [ <NUM_LIT> ] ) && operands [ <NUM_LIT> ] && ( INTVAL ( result ) != <NUM_LIT> || IS_STACK_PUSH ( operands [ <NUM_LIT> ] ) ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , result ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { emit_move_insn ( operands [ <NUM_LIT> ] , result ) ; } } else if ( operands [ <NUM_LIT> ] != <NUM_LIT> && operands [ <NUM_LIT> ] != <NUM_LIT> ) { rtx insn ; if ( ! H_REG_P ( operands [ <NUM_LIT> ] ) && operands [ <NUM_LIT> ] ) { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( mode , operands [ <NUM_LIT> ] , gen_rtx_fmt_ee ( code , mode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) ; insn = emit_move_insn ( operands [ <NUM_LIT> ] , operands [


<s> } unsigned ElmSz = DL . getTypeSizeInBits ( STy -> getTypeAtIndex ( ElmIdx ) ) / <NUM_LIT> ; if ( SL -> hasPadding ( ) && ( Offset - SL -> getElementOffset ( ElmIdx ) ) > ElmSz ) { unsigned Alignment = SL -> getAlignment ( ) ; PadOffset = Alignment - ( ( Offset - SL -> getElementOffset ( ElmIdx ) ) ) ; } return ElmIdx


<s> } if ( TARGET_AVX && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( GET_MODE ( op0 ) != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; } op1 = gen_lowpart ( V32QImode , op1 ) ; case MODE_VECTOR_FLOAT : ix86_avx256_split_vector_move_misalign ( op0 , op1 ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; break ; default : gcc_unreachable ( ) ; } return ; } if ( MEM_P ( op1 ) ) { if ( TARGET_AVX && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; else if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( GET_MODE ( op0 ) != V16QImode ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V16QImode ) ; } op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_loaddquv16qi ( op0 , op1 ) ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } else if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_AVX || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL || optimize_insn_for_size_p ( ) ) { emit_insn ( gen_sse2_loadupd ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE_SPLIT_REGS ) { emit_clobber ( op0 ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { rtx t ; if ( TARGET_AVX || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL || optimize_insn_for_size_p ( ) ) { if ( GET_MODE ( op0 ) != V4SFmode ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V4SFmode ) ; } op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_loadups ( op0 , op1 ) ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; return ; } if ( mode != V4SFmode ) t


<s> static void encodeDwarfRegisterLocation ( int DwarfReg , raw_ostream & OS ) { if ( DwarfReg < <NUM_LIT> ) { OS << uint8_t ( dwarf :: DW_OP_reg0 + DwarfReg ) ; } else { OS << uint8_t (


<s> auto isORCandidate = [ ] ( SDValue N ) { return ( N -> getOpcode ( ) == <STR_LIT> && N -> hasOneUse ( ) ) ; } ; if ( ! N -> hasOneUse ( ) || ! N -> getSimpleValueType ( <NUM_LIT> ) . bitsGE ( <STR_LIT> ) || ! isORCandidate ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto isSetCCCandidate = [ ] ( SDValue N ) { return N -> getOpcode ( ) == <STR_LIT> && N -> hasOneUse ( ) && <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isNullConstant ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) && N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . bitsGE ( <STR_LIT> ) ; } ; SDNode * OR = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDValue LHS = OR -> getOperand ( <NUM_LIT> ) ; SDValue RHS = OR -> getOperand ( <NUM_LIT> ) ; SmallVector < SDNode * , <NUM_LIT> > ORNodes ; while ( ( ( isORCandidate ( LHS ) && isSetCCCandidate ( RHS ) ) || ( isORCandidate ( RHS ) && isSetCCCandidate ( LHS ) ) ) ) { ORNodes . push_back ( OR ) ; OR = ( LHS -> getOpcode ( ) == <STR_LIT> ) ? LHS . getNode ( ) : RHS . getNode ( ) ; LHS = OR -> getOperand ( <NUM_LIT> ) ; RHS = OR -> getOperand ( <NUM_LIT> ) ; } if ( ! ( isSetCCCandidate ( LHS ) && isSetCCCandidate ( RHS ) ) || ! isORCandidate ( SDValue ( OR , <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue NewLHS = lower<ISA_LIT>CmpEqZeroToCtlzSrl ( LHS , DAG ) ; SDValue Ret , NewRHS ; if ( NewLHS && ( NewRHS = lower<ISA_LIT>CmpEqZeroToCtlzSrl ( RHS , DAG ) ) ) Ret = DAG . getNode ( <STR_LIT> , SDLoc ( OR ) , <STR_LIT> , NewLHS , NewRHS ) ; if ( ! Ret ) return SDValue ( ) ; while ( ORNodes . size ( ) > <NUM_LIT> ) { OR = ORNodes . pop_back_val ( ) ; LHS = OR -> getOperand ( <NUM_LIT> ) ; RHS = OR -> getOperand ( <NUM_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( ! FBB && Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } if ( Cond . size ( ) == <NUM_LIT> && Cond [ <NUM_LIT> ] . isReg ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( TBB && Cond [ <NUM_LIT> ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; if ( ! FBB ) { Cond [ <NUM_LIT> ] . isUndef (


<s> printOperand ( MI , opNum , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; return ; } const MCOperand & MO = MI -> getOperand ( opNum + <NUM_LIT> ) ; if ( ! MO . isImm ( ) || MO . getImm ( ) != <NUM_LIT> ) { printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; } O <<


<s> unsigned Tmp1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Tmp2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , Tmp1 ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Tmp2 ) . addReg ( Tmp1 ) . addReg ( Hi ) . addImm ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Dest ) . addReg ( Tmp2 ) .


<s> parseAccessReg ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , <NUM_LIT> )


<s> int getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node


<s> valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , type , <NUM_LIT> , true ) ; if ( valret ) return false ; } if ( AGGREGATE_TYPE_P ( type ) && ( aix_struct_return || ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) return true ; if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( TYPE_MODE ( type ) ) ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_return_big_vectors = false ; if ( ! warned_for_return_big_vectors ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; warned_for_return_big_vectors = true ; } return true ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE ( type ) == TFmode


<s> static bool allocateCCRegs ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State , const TargetRegisterClass * RC , unsigned NumRegs ) { ArrayRef < MCPhysReg > RegList = makeArrayRef ( RC -> begin ( ) , NumRegs ) ; unsigned RegResult = State . AllocateReg ( RegList ) ; if ( RegResult == <STR_LIT> ) return false ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , RegResult , LocVT , LocInfo ) ) ; return true


<s> if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ] ]


<s> return std :: make_pair ( domain , domain && lookup ( MI

-> getOpcode ( ) , domain ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; if ( ! ShowVSRNumsAsVR ) Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MII . get ( MI -> getOpcode ( ) ) , Reg , OpNo ) ; const char * RegName ; RegName = getVerboseConditionRegName ( Reg , MRI . getEncodingValue ( Reg ) ) ; if ( RegName == nullptr ) RegName = getRegisterName (


<s> StackTop = <NUM_LIT> ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Processed ; MachineBasicBlock * Entry = MF . begin ( ) ; bool Changed = false ; for ( MachineBasicBlock * BB : depth_first_ext ( Entry , Processed ) ) Changed |= processBasicBlock ( MF , * BB ) ; if ( MF . size ( ) != Processed . size ( ) ) for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) if ( Processed . insert ( BB ) . second ) Changed |= processBasicBlock ( MF , * BB ) ; LiveBundles . clear (


<s> else I = SetRegister ( I , & TLSBaseAddrReg ) ; Changed = true ; break ; default : break ; } } for ( auto I = Node -> begin ( ) , E = Node -> end ( ) ; I != E ; ++ I ) Changed |= VisitNode ( * I , TLSBaseAddrReg ) ; return Changed


<s> if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue V = combineAddOrSubToHADDorHSUB ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL


<s> static bool isInRage ( int DistanceInBytes ) { const int WordSize


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtm64_si64 ( __m64 __i ) { return ( long long


<s> bool <ISA_LIT>InstructionSelector :: isWorthFoldingIntoExtendedReg ( MachineInstr & MI , const MachineRegisterInfo & MRI ) const { Register DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . hasOneNonDBGUse ( DefReg ) || MI . getParent ( ) -> getParent ( ) -> getFunction ( ) . hasOptSize ( ) ) return true ; if ( ! STI . hasLSLFast ( ) ) return


<s> get_scratch_register_on_entry ( & sr , regno1 , live_regs ) ; emit_move_insn ( reg1 , GEN_INT ( first ) ) ; rounded_size = size & - PROBE_INTERVAL ; emit_move_insn ( sr . reg , GEN_INT ( rounded_size ) ) ; emit_set_insn ( reg1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , reg1 ) ) ; emit_set_insn ( sr . reg , gen_rtx_MINUS ( Pmode , reg1 , sr . reg ) ) ; emit_insn ( gen_probe_stack_range ( reg1 , reg1 , sr . reg ) ) ; if ( size != rounded_size ) { HOST_WIDE_INT rem = size - rounded_size ; if ( rem > <NUM_LIT> || ( TARGET_THUMB2 && rem > <NUM_LIT> ) ) { emit_set_insn ( sr . reg , plus_constant ( Pmode , sr . reg , - PROBE_INTERVAL ) ) ; emit_stack_probe ( plus_constant ( Pmode , sr . reg , PROBE_INTERVAL - rem ) ) ; } else emit_stack_probe ( plus_constant ( Pmode , sr . reg , - rem ) ) ; } release_scratch_register_on_entry ( & sr ) ; } emit_insn ( gen_blockage ( )


<s> c = atoi ( ptr ) ; frv_print_operand ( f , frv_insn_operands [ c ] , letter ) ; while ( ( c = * ptr ) >= '0' && c <= '9' ) ptr ++ ; } else fputc ( c , f ) ; } fprintf ( f , <STR_LIT> ) ; return


<s> assert ( ( VT . is512BitVector ( ) || VT . is256BitVector ( ) || VT . is128BitVector ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op . getNode ( ) ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasVPOPCNTDQ ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems < <NUM_LIT> || ( NumElems == <NUM_LIT> && Subtarget . canExtendTo512DQ ( ) ) ) { MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , NewVT , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } } if ( ! Subtarget . hasSSSE3 ( ) ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOPBitmath ( Op0 , DL , Subtarget , DAG ) ; } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI (

) ) return Lower512IntUnary ( Op , DAG ) ;


<s> MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else { ReplaceVCMPWithVPT ( VCMP , VCMP ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert ( VPST ) ; } else if ( Block . containsVCTP ( ) ) { MachineInstr * VPST = Insts . front ( ) ; if ( Block . size ( ) == <NUM_LIT> ) { assert ( VPST -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; LoLoop . ToRemove . insert ( VPST ) ; } else LoLoop . BlockMasksToRecompute . insert ( VPST ) ; } else if ( Insts . front ( ) -> getOpcode ( ) == <STR_LIT> ) { MachineInstr * VPST = Insts . front ( ) ; auto Next = ++ MachineBasicBlock :: iterator ( VPST ) ; assert ( getVPTInstrPredicate ( * Next ) != <STR_LIT> && <STR_LIT> ) ; ( void ) Next ; MachineInstr * VprDef = RDA -> getUniqueReachingMIDef ( VPST , <STR_LIT> ) ; if ( VprDef && VCMPOpcodeToVPT ( VprDef -> getOpcode ( ) ) && ! LoLoop . ToRemove . contains ( VprDef ) ) { MachineInstr * VCMP = VprDef ; if ( std :: none_of ( ++ MachineBasicBlock :: iterator ( VCMP ) , MachineBasicBlock :: iterator ( VPST ) , hasVPRUse ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ReplaceVCMPWithVPT ( VCMP , VPST ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert (


<s> else tmp = gen_reg_rtx ( mode ) ; alpha_expand_unaligned_load ( tmp , operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( tmp != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ] , tmp ) ; } else if ( MEM_P ( operands [


<s> void VLIWResourceModel :: savePacket ( ) { OldPacket =


<s> EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; totalsz += sz / <NUM_LIT> ; } } unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else assert ( false && <STR_LIT> ) ; } } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [


<s> pmuluw ( uint32x2_t s , uint32x2_t t ) { return __builtin_loongson_pmuluw ( s ,


<s> return :: isPSHUFDMask ( N -> getMask ( ) ,


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; if ( isRefInMap ( RR , Defs , Exec_Then ) ) return false ; if ( Op . isDef ( ) && isRefInMap ( RR , Uses , Exec_Then )


<s> bool arc_branch_size_unknown_p ( void