<s> static DecodeStatus DecodeVecShiftLImm ( llvm :: MCInst & Inst , unsigned Imm , unsigned Add ) { Inst . addOperand ( MCOperand :: CreateImm ( ( Imm + Add ) & ( Add - <NUM_LIT> ) ) ) ; return


<s> Use64BitRegs = false ; UseCRBits = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx =


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NumElts = MRI . getType ( Dst ) . getNumElements ( ) ; if ( ! isZipMask ( ShuffleMask , NumElts , WhichResult ) ) return false ; unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register V1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register V2 = MI . getOperand ( <NUM_LIT> )


<s> struct machine_function * p = ggc_cleared_alloc < machine_function > ( ) ; p -> ret_reg_mode = VOIDmode ; return


<s> emitFrameOffset ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , FrameReg , Offset , TII , MachineInstr :: NoFlags , ( Opcode == <STR_LIT> ) ) ; MI . eraseFromParent ( ) ; Offset = <NUM_LIT> ; return true ; } int NewOffset ; unsigned UnscaledOp ; bool UseUnscaledOp ; int Status = is<ISA_LIT>FrameOffsetLegal ( MI , Offset , & UseUnscaledOp , & UnscaledOp , & NewOffset ) ; if ( Status & <ISA_LIT>FrameOffsetCanUpdate ) { if ( Status & <ISA_LIT>FrameOffsetIsLegal ) MI . getOperand ( FrameRegIdx ) .


<s> SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M


<s> NewOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else return false ; } MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . add ( Reg0Op ) . add ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) . add ( Reg0Op ) . add ( Reg1Op ) ; } MIB . addReg ( BaseOp . getReg ( ) , RegState :: Kill ) . addImm ( Offset ) . addImm


<s> void setCurrentFunc ( MachineFunction & MF ) { CurMF = &


<s> switch ( Desc . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } case <STR_LIT> : switch ( MI -> getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT>


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( DAG ) ; InitReservedFrameCount ( F , DAG ) ; const char * tmpName = ESNames :: createESName ( PAN :: getArgsLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue BS = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgVals ; ++ i ) { SDValue Offset = DAG . getConstant ( i , <STR_LIT> ) ; SDValue PICLoad = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , ES , BS , Offset ) ; Chain = getChain ( PICLoad


<s> __vector __bool long long shmask ; const __v2du shmax = { <NUM_LIT> , <NUM_LIT> } ; __v2du result ; rshift = vec_splat ( ( __v2du ) __B , <NUM_LIT> ) ; shmask = vec_cmplt ( rshift ,


<s> AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; unsigned Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> isSwift ( ) && Ord == Release ) { Domain = <STR_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( Domain


<s> unsigned getAlign ( ) const { return


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( isTargetHardFloat ( ) ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } setSupportsDebugEntryValues ( true ) ; initAsmInfo ( )


<s> unsigned <ISA_LIT>ABIInfo :: GetEhDataReg ( unsigned I ) const { static const unsigned EhDataReg [ ]


<s> EltTy = AT -> getElementType ( ) ; AT = dyn_cast < ArrayType > ( EltTy ) ; } unsigned EltElts = ~ <NUM_LIT> ; Type * Tmp = analyzeType ( EltTy , EltElts , DL ) ; if ( EltElts != <NUM_LIT> ) NElts *= EltElts ; return Tmp ; } if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { Type * EltTy = VT -> getElementType ( ) ; NElts = DL . getTypeAllocSize ( Ty ) / DL . getTypeAllocSize ( EltTy ) ; assert ( NElts >= VT -> getNumElements ( ) ) ; if ( EltTy -> isIntegerTy ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; return EltTy ; } if ( isa < StructType > ( Ty ) ) { NElts = DL . getTypeAllocSize ( Ty ) ; return Type :: getInt8Ty ( Ty -> getContext ( ) ) ; } assert ( ! Ty -> isAggregateType ( ) ) ; NElts = <NUM_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) return Type :: getInt8Ty ( Ty -> getContext ( ) ) ; return


<s> regno = REGNO ( XEXP ( XVECEXP ( pattern , <NUM_LIT> , i ) , store_p ) ) ; if ( automod_offset < <NUM_LIT> ) { if ( FP_REGNO_P ( regno ) ) mask |= <NUM_LIT> << ( regno - FP0_REG ) ; else mask |= <NUM_LIT> << ( <NUM_LIT> - ( regno - D0_REG ) ) ; } else { if ( FP_REGNO_P ( regno ) ) mask |= <NUM_LIT> << ( <NUM_LIT> - ( regno - FP0_REG ) ) ; else mask |= <NUM_LIT> << ( regno - D0_REG ) ; } } CC_STATUS_INIT ; if ( automod_offset == <NUM_LIT> ) operands [ <NUM_LIT> ] = XEXP ( XEXP ( XVECEXP ( pattern , <NUM_LIT> , first ) , ! store_p ) , <NUM_LIT> ) ; else if ( automod_offset < <NUM_LIT> ) operands [ <NUM_LIT> ] = gen_rtx_PRE_DEC ( Pmode , SET_DEST ( XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ) ) ; else operands [ <NUM_LIT> ] = gen_rtx_POST_INC ( Pmode , SET_DEST ( XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( mask ) ; if ( FP_REGNO_P ( REGNO ( XEXP ( XVECEXP ( pattern , <NUM_LIT> , first ) , store_p ) ) ) ) { if ( store_p )


<s> assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) ; bool ExecModified = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; MachineBasicBlock :: iterator Start = MBB . begin ( ) ; MachineInstr * OrSaveExec = BuildMI ( MBB , Start , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock * DestBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: iterator ElsePt ( MI ) ; if ( ExecModified ) { MachineInstr * And = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( <STR_LIT> ) . addReg ( DstReg ) ; if ( LIS ) LIS -> InsertMachineInstrInMaps ( * And ) ; } MachineInstr * Xor = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( DstReg ) ; MachineBasicBlock :: iterator Term = MBB . getFirstTerminator ( ) ; MachineInstr * Branch = BuildMI ( MBB , Term , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) . addReg ( DstReg ) ; if ( ! LIS


<s> __builtin_altivec_dstt ( ( void * ) a1 , a2


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value


<s> return ( __m128 ) __builtin_ia32_cmpltss ( ( __v4sf ) __A ,


<s> enum ix86_builtin_func_type ftype ; const struct builtin_description * d ; size_t i ; tree decl ; tree attrs_load , attrs_type_load , attrs_store , attrs_type_store ; tree attrs_log , attrs_type_log ; if ( ! flag_tm ) return ; if ( ! builtin_decl_explicit_p ( BUILT_IN_TM_LOAD_1 ) ) return ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOAD_1 ) ; attrs_load = DECL_ATTRIBUTES ( decl ) ; attrs_type_load = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_STORE_1 ) ; attrs_store = DECL_ATTRIBUTES ( decl ) ; attrs_type_store = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOG ) ; attrs_log = DECL_ATTRIBUTES ( decl


<s> int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc = NeedAlign <= HasAlign ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstR ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; B . erase ( It ) ; return true


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L !=

LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> std :: map < enum AMDGPUOperand :: ImmTy , unsigned > OptionalIdx ; for ( unsigned i = <NUM_LIT> , e = Operands . size ( ) ; i != e ; ++ i ) { AMDGPUOperand & Op = ( ( AMDGPUOperand & ) * Operands [ i ] ) ; if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isImm ( ) && Op . getImmTy ( ) == AMDGPUOperand :: ImmTyNone ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isToken ( ) ) { continue ; } assert ( Op . isImm ( ) ) ; OptionalIdx [ Op . getImmTy ( ) ] = i ; } assert ( OptionalIdx . size ( ) == <NUM_LIT> ) ; unsigned OffsetIdx = OptionalIdx [ AMDGPUOperand :: ImmTyOffset ] ; unsigned GLCIdx = OptionalIdx [ AMDGPUOperand :: ImmTyGLC ] ; unsigned SLCIdx = OptionalIdx [ AMDGPUOperand ::


<s> case HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : case DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s


<s> void <ISA_LIT>TargetStreamer :: emitPersonalityIndex ( unsigned Index ) { llvm_unreachable ( <STR_LIT>


<s> static DecodeStatus DecodeL4RSrcDstInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Op1 , Op2 , Op3 ; unsigned Op4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = Decode3OpInstruction ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Op1 , Op2 , Op3 ) ; if ( S == MCDisassembler :: Success ) { DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; S = DecodeGRRegsRegisterClass ( Inst , Op4 , Address , Decoder ) ; } if ( S == MCDisassembler :: Success ) { DecodeGRRegsRegisterClass ( Inst , Op4 ,


<s> TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ; continue ; } assert ( Cond . size ( ) <= <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != ThisTarget -> getMBB ( ) )


<s> return __builtin_mve_vrshrq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) ,


<s> final_emit_insn_group_barriers ( dump ) ; bundling ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; if ( sched_verbose && dump ) fprintf ( dump , <STR_LIT> , INSN_UID ( NEXT_INSN ( current_sched_info ->

prev_head ) ) , INSN_UID ( PREV_INSN ( current_sched_info -> next_tail ) ) ) ;


<s> bool isTargetMingw ( ) const { return TargetTriple . getOS ( ) == Triple :: MinGW32 || TargetTriple . getOS ( ) == Triple ::


<s> assert ( op != nullptr ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * op ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> rtx src = op [ <NUM_LIT> ] ; rtx base = XEXP ( dest , <NUM_LIT> ) ; int reg_base = true_regnum ( base ) ; int reg_src = true_regnum ( src ) ; if ( reg_base == reg_src ) { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB TINY_ADIW ( % E0 , % F0 , <NUM_LIT> ) CR_TAB <STR_LIT> CR_TAB <STR_LIT> ,


<s> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset (


<s> PhysRegs . set ( PhysReg ) ; ShapeT Shape = VRM -> getShape ( VirtReg ) ; Register RowReg = Shape . getRow ( ) -> getReg ( ) ; Register ColReg = Shape . getCol ( ) -> getReg ( ) ; unsigned Index = getTilePhysRegIndex ( PhysReg ) ; int RowOffset = <NUM_LIT> + Index ; int ColOffset = <NUM_LIT> + Index * <NUM_LIT> ; unsigned BitSize = <NUM_LIT> ; for ( const auto & Pair : { std :: make_pair ( RowReg , RowOffset ) , std :: make_pair ( ColReg , ColOffset ) } ) { int64_t Imm ; int ImmCount = <NUM_LIT> ; for ( const MachineOperand & MO : MRI -> def_operands ( Pair . first ) ) { const auto * Inst = MO . getParent ( ) ; if ( Inst -> isMoveImmediate ( ) ) { ImmCount ++ ; Imm = Inst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; } } auto StoreConfig = [ & ] ( int Offset ) { MachineInstr * NewMI = nullptr ; if ( ImmCount ) NewMI = storeImmToStackSlot ( * MBB , * MI , Imm , BitSize , SS , Offset , TII ) ; else { const TargetRegisterClass * RC = MRI -> getRegClass ( Pair . first ) ; NewMI = storeRegToStackSlot ( * MBB , * MI , Pair . first , BitSize , SS , Offset , TII , RC , TRI ) ; } SlotIndex SIdx = LIS -> InsertMachineInstrInMaps ( * NewMI ) ; if ( ! ImmCount ) { SmallVector < SlotIndex , <NUM_LIT> > EndPoints = { SIdx . getRegSlot (


<s> static DecodeStatus DecoderForMRRC2AndMCRR2 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned CRm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned opc1 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned cop = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( cop ) ) ; Inst . addOperand ( MCOperand :: createImm ( opc1 ) ) ; if ( Inst . getOpcode ( )


<s> void <ISA_LIT>GOT :: applyGOT0 ( uint64_t pAddress ) { llvm :: cast < <ISA_LIT>GOTEntry > ( * ( m_SectionData -> getFragmentList ( ) . begin ( )


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { if ( Count % <NUM_LIT> != <NUM_LIT>


<s> bool needsFrameMoves = MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { assert ( ! HasFP && <STR_LIT> ) ; AFI -> setLocalStackSize ( NumBytes ) ; MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; if ( NumBytes && ! canUseRedZone ( MF ) ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( FrameLabel , - NumBytes ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } else if ( NumBytes ) { ++ NumRedZoneFunctions ; } return ; } int FPOffset = <NUM_LIT> ; if ( HasFP ) { assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> && ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) ; FPOffset = - ( MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) * <NUM_LIT> ; assert ( FPOffset >= <NUM_LIT> && <STR_LIT> ) ; } while ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; NumBytes -= <NUM_LIT> ; } assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( HasFP ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } AFI -> setLocalStackSize ( NumBytes ) ; if ( NumBytes ) { if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr


<s> const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , ++ MachineBasicBlock :: iterator ( I ) , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ; return Copy


<s> MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( TRI -> getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode (


<s> static vector < Instruction * > extractIntrinFromList ( vector < IntrinsicInst * > intrinsicList , <STR_LIT> intrinId


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) -> getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> +


<s> if ( ( regs -> size_1word + regs -> size_2words ) > <NUM_LIT> ) { int first = regs -> first ; int last = regs -> last ; int regno ; fprintf ( stderr , <STR_LIT> , regs -> name , regs -> size_1word + regs -> size_2words , regs -> size_1word , regs -> size_2words ) ; for ( regno = first ; regno <= last ; regno ++ ) { if ( info -> save_p [ regno ] == REG_SAVE_1WORD ) fprintf ( stderr , <STR_LIT> , reg_names [ regno ]


<s> return EnableBlockAlignedStackCache ? <NUM_LIT> : STC


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( )


<s> static bool isIndirectBranchOpcode ( int Opc ) { using namespace llvm :: <ISA_LIT> ; ( Opc == NAME ## ari || Opc == NAME ## ari_nt || Opc == NAME ## ari_t ) assert ( ! BRKIND ( BCFW ) && ! BRKIND ( BCFD ) && ! BRKIND ( BCFS ) && <STR_LIT> ) ; return BRKIND ( BCFL )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; bool Changed = false ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>FunctionInfo & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto * TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; AliasAnalysis & AA = getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; LiveIntervals & LIS = getAnalysis < LiveIntervals > ( ) ; for ( MachineBasicBlock & MBB : MF ) { for ( auto MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ++ MII ) { auto & MI = * MII ; if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) continue ; if ( MI . getOpcode ( ) ==


<s> return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT>


<s> bool aarch64_mov_operand_p ( rtx x , enum aarch64_symbol_context context , machine_mode mode ) { if ( GET_CODE ( x ) == HIGH && aarch64_valid_symref ( XEXP ( x , <NUM_LIT> ) ,

GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ) return true ;


<s> if ( isa < ConstantSDNode > ( Offset ) ) { SDValue Tmp1 , Tmp2 ; if ( Subtarget -> getGeneration ( ) > <ISA_LIT>Subtarget :: SEA_ISLANDS || SelectMUBUFConstant ( Offset , Tmp1 , Tmp2 ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Offset ) ) { SDValue N0 = Offset . getOperand ( <NUM_LIT> ) ; SDValue N1 = Offset . getOperand ( <NUM_LIT>


<s> switch ( LC ) { case RTLIB :: MEMCPY : AEABILibcall = AEABI_MEMCPY ; break ; case RTLIB :: MEMMOVE : AEABILibcall = AEABI_MEMMOVE ; break ; case RTLIB :: MEMSET : AEABILibcall = AEABI_MEMSET ; if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . IsSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( TLI -> getLibcallCallingConv ( LC ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( FunctionNames [ AEABILibcall ] [ AlignVariant ] ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI


<s> } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return <NUM_LIT> ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; } return <NUM_LIT>


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( ArchFeature ) ) ) ; AssemblerOptions . back ( ) -> setFeatures ( getAvailableFeatures


<s> int getVarArgsFrameOffset ( ) const { return


<s> return ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc ==


<s> return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } unsigned addrmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; addrmode |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeT2AddrModeSOReg ( Inst , addrmode , Address , Decoder )


<s> unsigned Lgkmcnt = getBitMask ( getLgkmcntBitShift ( ) , getLgkmcntBitWidth ( Version . Major ) ) ; unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt ; if ( Version . Major < <NUM_LIT> ) return Waitcnt ; unsigned VmcntHi = getBitMask ( getVmcntBitShiftHi (


<s> for ( int i = <NUM_LIT> ; i < NumLanes ; ++ i ) if ( Lanes [ i ] >= <NUM_LIT> ) { LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; LaneMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * Lanes [ i ] + <NUM_LIT> ; } V1 = DAG . getBitcast ( LaneVT , V1 ) ; V2 = DAG . getBitcast ( LaneVT , V2 ) ; SDValue LaneShuffle = DAG . getVectorShuffle ( LaneVT , DL , V1 , V2 , LaneMask ) ; LaneShuffle = DAG . getBitcast ( VT , LaneShuffle ) ; SmallVector < int , <NUM_LIT> > NewMask ( ( unsigned ) Size , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) NewMask [ i ] = ( i / LaneSize ) * LaneSize + Mask [ i ] % LaneSize ; assert ( ! is128BitLaneCrossingShuffleMask ( VT , NewMask


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSIReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSIReg ? <STR_LIT> : <STR_LIT>


<s> if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , VT . getVectorNumElements ( ) ) ; } SDValue Load = DAG . getLoad ( EltVT , DL , ML -> getChain ( ) , Addr , ML -> getPointerInfo ( ) . getWithOffset ( Offset ) , Alignment , ML -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue PassThru = DAG . getBitcast ( CastVT , ML -> getPassThru ( ) ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , DL , CastVT , PassThru , Load , VecIndex ) ; Insert = DAG . getBitcast ( VT , Insert


<s> for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; bool decrement = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; if ( ! increment && ! decrement ) continue ; new_rhs = rhs + ( increment ? <NUM_LIT> : - <NUM_LIT> ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) && ( rhs < <NUM_LIT> ) == ( new_rhs < <NUM_LIT> ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ; } } } loongarch_extend_comparands ( * code , op0 , op1 ) ; * op0 = force_reg ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = force_reg ( word_mode ,


<s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file


<s> assert ( OPW_FIRST_ <= Width && Width < OPW_LAST_ ) ; switch ( Width ) { default : case OPW32


<s> void neg ( ) { asm_fprintf ( t_file , <STR_LIT>


<s> static LegalizeMutation oneMoreElement ( unsigned TypeIdx ) { return [ = ] ( const LegalityQuery & Query ) { const LLT Ty = Query . Types [ TypeIdx ] ; const LLT EltTy = Ty


<s> case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 )


<s> const iterator_range < mop_iterator > & Range ( Instr -> explicit_uses


<s> static void mips_start_ll_sc_sync_block ( void ) { if ( !


<s> MachineOperand & Op = MI . getOperand ( I ) ; if ( ! Op . isImm ( ) && ! ( Op . isReg ( ) && ! TRI -> isVGPR ( * MRI , Op . getReg ( ) ) ) ) continue ; if ( Desc . OpInfo [ I ] . RegClass == - <NUM_LIT> || ! TRI -> hasVGPRs ( TRI -> getRegClass ( Desc . OpInfo [ I ] . RegClass ) ) ) continue ; unsigned VGPR = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto Copy = BuildMI ( * MI . getParent ( ) , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VGPR ) ; if ( Op . isImm ( ) ) Copy . addImm ( Op . getImm ( ) ) ; else if ( Op . isReg ( ) ) Copy . addReg ( Op . getReg ( ) , Op

. isKill ( ) ? RegState :: Kill : <NUM_LIT> , Op . getSubReg ( ) ) ;


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char * ) mm


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( ShuffleVectorSDNode :: isSplatMask ( M . data ( ) ,


<s> bool <ISA_LIT>AsmParser :: parseHwregBody ( OperandInfoTy & HwReg , OperandInfoTy & Offset , OperandInfoTy & Width ) { using namespace llvm :: <STR_LIT> ; HwReg . Loc = getLoc ( ) ; if ( isToken ( AsmToken :: Identifier ) && ( HwReg . Id = getHwregId ( getTokenStr ( ) , getSTI ( ) ) ) != OPR_ID_UNKNOWN ) { HwReg . IsSymbolic = true ; lex ( ) ; } else if ( ! parseExpr ( HwReg .


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true


__artificial__ ) ) _mm256_set1_epi32 ( int __A ) {


<s> Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( IndxTy -> isVectorTy ( ) ) IndxTy = IndxTy -> getVectorElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ; std :: pair < int , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ; std :: pair < int , MVT > SrcLT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; int SplitFactor = std :: max ( IdxsLT . first , SrcLT . first ) ; if ( SplitFactor > <NUM_LIT> ) { Type * SplitSrcTy = VectorType :: get ( SrcVTy -> getScalarType ( ) , VF / SplitFactor ) ; return SplitFactor * getGSVectorCost ( Opcode , SplitSrcTy , Ptr ,


<s> <ISA_LIT>InstrInfo :: ~ <ISA_LIT>InstrInfo ( ) { delete RS


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ; DebugLoc DL ; determineFrameLayout (


<s> if ( I == StackPtrCopyInst ) continue ; Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ; if ( Classification != Convert ) continue ; if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp & ( SlotSize - <NUM_LIT> ) ) return ; StackDisp >>= Log2SlotSize ; assert ( ( size_t ) StackDisp < Context . ArgStoreVector . size ( ) && <STR_LIT> ) ; if ( Context . ArgStoreVector [ StackDisp ] != nullptr ) return ; Context . ArgStoreVector [ StackDisp ] = & * I ; for ( const MachineOperand & MO : I -> uses ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( RegInfo . isPhysicalRegister ( Reg ) ) UsedRegs . insert ( Reg ) ; } } -- I ; if ( I == MBB . end ( ) || ! I -> isCall


<s> unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . getSymbol ( GVar ) ; PointerType * PTy = dyn_cast < PointerType > ( GVar -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; O << * Name ; O << <STR_LIT> ; } else { O << * Name ; } } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr ,


<s> Index = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: RBrac ) ) { LaneKind = AllLanes ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; return MatchOperand_Success ; } if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; const MCExpr * LaneIndex ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( LaneIndex ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LaneIndex ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; int64_t Val = CE -> getValue (


<s> unsigned Code = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Code == <NUM_LIT> ) O << <STR_LIT> ; else if ( Code == <NUM_LIT> )


<s> const std :: pair < unsigned , int > * <ISA_LIT>FrameLowering :: getCalleeSaveSpillSlots ( unsigned & NumEntries ) const { NumEntries = <NUM_LIT> ; return & LR [ <NUM_LIT>


<s> const std :: string & <ISA_LIT>LA25Stub :: name ( ) const { return m_Name


<s> Inst . addOperand ( MCOperand :: CreateReg ( FRegs [ getReg ( )


<s> unsigned opcode = issub ? ( unsign ? <STR_LIT> : <STR_LIT> ) : ( unsign ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder paddrnMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; paddrnMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; paddrnMI . addOperand ( MI . getOperand ( reg1 ) ) ; paddrnMI . addOperand ( MI . getOperand ( reg2 ) ) ; paddrnMI . addImm ( n2 ) ; } else { MachineInstrBuilder sra = BuildMI ( * BB , MI , DL , TII -> get ( unsign ? <STR_LIT> : <STR_LIT> ) ) ; sra . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; sra . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; sra . addImm ( n2 ) ; MachineInstrBuilder addsub = BuildMI ( * BB , sra . getInstr ( ) , DL , TII -> get ( <STR_LIT> ) ) ; addsub . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; addsub . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; addsub . addImm ( n1 ) ; MachineInstrBuilder add = BuildMI ( * BB , addsub . getInstr ( ) , DL ,

TII -> get ( issub ? <STR_LIT> : <STR_LIT> ) ) ;


<s> case AtomicOrdering :: AcquireRelease : if ( Subtarget -> preferISHSTBarriers ( ) ) return makeDMB ( Builder , <STR_LIT> ) ; else return makeDMB ( Builder , <STR_LIT> ) ; } llvm_unreachable (


<s> auto * CPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( E . Val . MachineCPVal ) ; auto * CPC = dyn_cast < <ISA_LIT>ConstantPoolConstant > ( CPV ) ; if ( ! CPC )


<s> return ( uint32x2_t ) __builtin_aarch64_sqmovunv2di (


<s> bool <ISA_LIT>LegalizerInfo :: legalizeFrem ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Flags = MI . getFlags ( ) ; LLT Ty = MRI . getType ( DstReg ) ; auto Div = B . buildFDiv ( Ty , Src0Reg , Src1Reg , Flags ) ; auto Trunc = B . buildIntrinsicTrunc ( Ty , Div , Flags ) ; auto Neg = B . buildFNeg ( Ty , Trunc , Flags ) ; B . buildFMA ( DstReg , Neg , Src1Reg , Src0Reg , Flags ) ; MI . eraseFromParent


<s> gcc_assert ( operand . predicate == aarch64_any_register_operand ) ; mode = GET_MODE ( x ) ; } else if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) && VECTOR_MODE_P ( mode ) ) x = expand_vector_broadcast ( mode , x ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; x = gen_lowpart ( mode , x ) ; } m_ops . safe_grow ( m_ops . length ( ) + <NUM_LIT> , true ) ; create_input_operand ( & m_ops . last ( )


<s> if ( isEntryFunction ( ) ) FrameOffsetReg =


<s> bool doInitialization ( Module & M )


<s> if ( DumpCodeInstEmitter && ! isBlockOnlyReachableByFallthrough ( & MBB ) ) { DisasmLines . push_back ( ( Twine ( <STR_LIT> ) + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( MBB . getNumber ( ) ) + <STR_LIT> ) . str ( ) ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines


<s> return ( DEFAULT_ABI == ABI_V4 && ! flag_pic && ! TARGET_TOC && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST )


<s> void Emitter < CodeEmitter > :: emitLEApcrelJTInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit (


<s> const MCExpr * Disp = nullptr ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( * InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: createAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( ( Parser . getTok ( ) . getKind ( ) == AsmToken :: Identifier || Parser . getTok ( ) . getKind ( ) == AsmToken :: Dot || Parser . getTok ( ) . getKind ( ) == AsmToken :: Real ) && Parser . getTok ( ) . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } if ( isSymbol ) { if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> ,

<NUM_LIT> , <NUM_LIT> , Start , End , Size ) ;


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) { PM . add ( createBasicTargetTransformInfoPass ( this ) ) ; PM . add ( create<ISA_LIT>TargetTransformInfoPass ( this )


<s> unsigned VecNum = Subtarget . isLittleEndian ( ) ? NumVecs - <NUM_LIT> - Idx : Idx ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( VecNum , dl , <STR_LIT> ) ) ; SDValue Store = DAG . getStore ( StoreChain , dl , Elt , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * <NUM_LIT> ) , commonAlignment ( Alignment , Idx * <NUM_LIT> ) , SN -> getMemOperand ( ) -> getFlags ( ) , SN -> getAAInfo ( ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , BasePtr


<s> machine_mode mode_with_wider_elts = aarch64_sve_int_mode ( GET_MODE ( dest ) ) ; machine_mode mode_with_narrower_elts = aarch64_sve_int_mode ( GET_MODE ( src ) ) ; if ( GET_MODE_UNIT_SIZE ( mode_with_wider_elts ) < GET_MODE_UNIT_SIZE ( mode_with_narrower_elts ) ) std

:: swap ( mode_with_wider_elts , mode_with_narrower_elts ) ;


<s> symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; fputs ( TARGET_32BIT ? <STR_LIT> : <STR_LIT> , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; in_section = NULL ; switch_to_section ( function_section ( decl ) ) ; putc ( '.' , file ) ; RS6000_OUTPUT_BASENAME ( file , buffer ) ; fputs ( <STR_LIT> , file ) ; data . function_descriptor = true ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; if ( ! DECL_IGNORED_P ( decl ) ) { if ( write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG ) xcoffout_declare_function ( file , decl , buffer ) ; else if ( write_symbols == DWARF2_DEBUG ) { name = ( * targetm . strip_name_encoding ) ( name ) ; fprintf ( file , <STR_LIT> , name


<s> unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg


<s> bool mips_store_by_pieces_p ( unsigned HOST_WIDE_INT size , unsigned int align ) { if ( align <= BITS_PER_UNIT ) return size <


<s> return ( uint32x2_t ) __builtin_neon_vmls_nv2si ( ( int32x2_t ) __a ,


<s> unsigned DestReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = MemMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned RegSize = TII -> getRegClass ( MemMI -> getDesc ( ) , <NUM_LIT> , TRI , MF ) -> getSize ( ) ; if ( MBBI == B || Offset != <NUM_LIT> ) return E ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; BitVector ModifiedRegs , UsedRegs ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs (


<s> bool mayNeedAGPRs ( ) const { return


<s> bool <ISA_LIT>Subtarget :: useMovt ( const MachineFunction & MF


<s> SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( ( Shamt != SMPos0 ) || ( SMPos0 + SMSize0 > ValTy . getSizeInBits ( ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , ValTy , Shl . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SMPos0 , <STR_LIT> ) , DAG . getConstant ( SMSize0 ,

<STR_LIT> ) , And0 . getOperand ( <NUM_LIT> ) ) ;


<s> case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << <STR_LIT> ; return false ; case 'U' : case 'X' : assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; return false ; } } assert ( MI -> getOperand ( OpNo ) . isReg


<s> for ( j = <NUM_LIT> ; j < unit_size ; j ++ ) { if ( ( c & <NUM_LIT> ) != <NUM_LIT> && ( c & <NUM_LIT> ) != <NUM_LIT> ) return false ; tmp_mask |= ( c & <NUM_LIT> ) << ( ( nunit - <NUM_LIT> - i ) * unit_size + j ) ; c = c >> BITS_PER_UNIT ; } } if ( mask != NULL


<s> static rtx gen_fr_spill_x ( rtx dest , rtx src , rtx


<s> Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; ArgInfos . push_back ( Arg ) ; OrigArgIndices . push_back ( i ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; bool IsCalleeVarArg = false ; if ( Info . Callee . isGlobal ( ) ) { const Function * CF = static_cast < const Function * > ( Info . Callee . getGlobal ( ) ) ; IsCalleeVarArg = CF -> isVarArg ( ) ; } <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , IsCalleeVarArg , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( Info . CallConv ) , <NUM_LIT> ) ; const char * Call = Info . Callee . isSymbol ( ) ? Info . Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; if ( IsCalleeGlobalPIC ) { MIRBuilder . buildCopy ( Register ( <STR_LIT> ) , MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseRegForGlobalISel ( ) ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( MIB -> getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( MIRBuilder . getMF ( )


<s> return __builtin_loongson_pcmpgtb_s ( s , t


<s> <STR_LIT> Flags ; Flags . setOrigAlign ( DL . getABITypeAlign ( ArgTy ) ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; Register CalleeReg ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = constrainOperandRegClass ( TII . get ( CallOpc ) , CalleeReg , isThumb2 ? <NUM_LIT> : <NUM_LIT> ) ; MIB . addReg ( CalleeReg ) ; } else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( Register R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < Register , <NUM_LIT> >


<s> assert ( MaskDef -> getOpcode ( ) == TargetOpcode :: G_BUILD_VECTOR && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MaskDef -> getNumOperands ( ) ; i < e ; ++ i ) { MachineInstr * ScalarDef = getDefIgnoringCopies ( MaskDef -> getOperand ( i ) . getReg ( ) ,


<s> maxoff = <NUM_LIT> ; if ( vcall_offset > maxoff || vcall_offset < - maxoff ) fprintf ( file , <STR_LIT> ) ; else if ( delta > maxoff || delta < - maxoff ) fprintf ( file , <STR_LIT> ) ; } if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) thiz = <STR_LIT> ; if ( delta != <NUM_LIT> ) { if ( delta > maxoff || delta < - maxoff ) { fprintf ( file , <STR_LIT> , reg0 , ( long ) delta ) ; fprintf ( file , <STR_LIT> , thiz , thiz , reg0 ) ; } else fprintf ( file , <STR_LIT> , ( delta > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , thiz , thiz , ( long ) ( delta > <NUM_LIT> ? delta : - delta ) ) ; } if ( vcall_offset != <NUM_LIT> ) { fprintf ( file , <STR_LIT> , reg0 , thiz ) ; if ( vcall_offset > maxoff || vcall_offset < - maxoff ) { fprintf ( file , <STR_LIT> , reg1 , ( long ) vcall_offset ) ; fprintf ( file , <STR_LIT> , reg0 , reg0 , reg1 ) ; } else fprintf ( file , <STR_LIT> , ( vcall_offset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , reg0 , reg0 , ( long ) ( vcall_offset > <NUM_LIT> ? vcall_offset : - vcall_offset ) ) ; fprintf ( file , <STR_LIT> , reg0


<s> SDValue Src0 = peekThroughBitcasts ( V . getOperand ( <NUM_LIT> ) ) ; SDValue Src1 = peekThroughBitcasts ( V . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpc0 = Src0 . getOpcode ( ) ; unsigned SrcOpc1 = Src1 . getOpcode ( ) ; EVT SrcVT0 = Src0 . getValueType ( ) ; EVT SrcVT1 = Src1 . getValueType ( ) ; if ( ! Src1 . isUndef ( ) && ( SrcVT0 != SrcVT1 || SrcOpc0 != SrcOpc1 ) ) return SDValue ( ) ; switch ( SrcOpc0 ) { case <STR_LIT> : { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) ) ; return DAG . getBitcast ( VT , Res ) ; } case <STR_LIT> : if ( SrcVT0 == <STR_LIT> ) { uint64_t Mask = Src0 . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Mask & <NUM_LIT> ) != ( ( Mask >> <NUM_LIT> ) & <NUM_LIT> ) ) break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Src1 . isUndef ( ) || Src0 . getOperand ( <NUM_LIT> ) == Src1 . getOperand ( <NUM_LIT> ) ) { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS ,


<s> case E_HImode : return <NUM_LIT> ; case E_SImode : return <NUM_LIT> ; case E_DImode : return <NUM_LIT> ; case E_SFmode : return <NUM_LIT> ; case E_DFmode : return <NUM_LIT> ; case E_XFmode : return <NUM_LIT> ; case E_TImode


<s> if ( optimize_size ) return <NUM_LIT> ; insn = next_active_insn ( label ) ; if ( insn == <NUM_LIT> ) return <NUM_LIT> ; else if ( ( get_attr_length ( insn ) % <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else return


<s> bool MachineConstEvaluator :: evaluateANDii ( const APInt & A1 , const APInt & A2 , APInt & Result ) { Result = A1 &


<s> if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugInstr ( ) ) ++ I ; if ( I != E )


<s> static rtx cris_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED , bool outgoing


<s> temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel

( RM ) , getEffective<ISA_LIT>CodeModel ( CM ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) {


<s> return BRIG_COMPARE_EQ ; case <STR_LIT> : return BRIG_COMPARE_GT ; case <STR_LIT> : return BRIG_COMPARE_GE ; case <STR_LIT> : return BRIG_COMPARE_LT ; case <STR_LIT> : return BRIG_COMPARE_LE ; case <STR_LIT> : Signed = true ; return BRIG_COMPARE_NE ; case <STR_LIT> : Signed = true ; return BRIG_COMPARE_EQ ; case <STR_LIT> : Signed = true ; return BRIG_COMPARE_GT ; case <STR_LIT> : Signed = true ; return BRIG_COMPARE_GE


<s> return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> E . push_back ( new SCAEdge ( src -> yId , dst -> yId , MBB -> getName ( ) , index , MBB


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ) ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> )


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL


<s> SmallVectorImpl < CCValAssign > & PendingHAMembers = State . getPendingLocs ( ) ; assert ( PendingHAMembers . size ( ) < <NUM_LIT> ) ; if ( PendingHAMembers . size ( ) > <NUM_LIT> ) assert ( PendingHAMembers [ <NUM_LIT> ] . getLocVT ( ) == LocVT ) ; PendingHAMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ArgFlags . isInConsecutiveRegsLast ( ) ) { assert ( PendingHAMembers . size ( ) > <NUM_LIT> && PendingHAMembers . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; ArrayRef < uint16_t > RegList ; switch ( LocVT . SimpleTy ) { case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingHAMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingHAMembers . begin ( ) ; It != PendingHAMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingHAMembers . clear ( ) ; return true ; } for ( unsigned regNo = <NUM_LIT> ; regNo < <NUM_LIT> ; ++ regNo ) State . AllocateReg ( SRegList [ regNo ] ) ; unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned Align = std :: min ( Size , <NUM_LIT> ) ; for ( auto It : PendingHAMembers ) { It . convertToMem ( State . AllocateStack ( Size , Align ) ) ; State . addLoc ( It


<s> for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) compute_local_backward_infos ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) emit_local_forward_vsetvls ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ; if ( dump_file ) fprintf (


<s> unsigned getNumFixupKinds ( ) const override { return


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) .


<s> rtx m32c_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED


<s> return ; case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : { assert ( SDValue ( N , <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; if ( ! LoadNode -> isVolatile ( ) || LoadNode -> getMemoryVT ( ) != <STR_LIT> ) { return ; } SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ; Results . append ( { Pair , Result . getValue ( <NUM_LIT> ) } ) ; return ; } case <STR_LIT> : ReplaceExtractSubVectorResults ( N , Results , DAG ) ; return ; case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , V ) ) ; return ; } case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true


<s> if ( NoOpt && ! HasExtraAlign ) UseFP = true ; if ( MFI . isFixedObjectIndex ( FI ) || MFI . isObjectPreAllocated ( FI ) ) { UseFP |= ( HasAlloca || HasExtraAlign ) ; } else { if ( HasAlloca ) { if ( HasExtraAlign ) UseAP = true ; else UseFP = true ; } } bool HasFP = hasFP ( MF ) ; assert ( ( HasFP || ! UseFP ) && <STR_LIT> ) ; if ( Offset > <NUM_LIT> && ! HasFP ) Offset -= <NUM_LIT> ; if ( UseFP ) FrameReg = FP ; else if ( UseAP ) FrameReg = AP ; else FrameReg = SP ; int RealOffset = Offset ; if ( ! UseFP && ! UseAP ) RealOffset = FrameSize + Offset ; return StackOffset :: getFixed


<s> return Reinterpret ; case <STR_LIT> : if ( InOp . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) return Reinterpret ; } SDValue Mask = getPTrue ( DAG , DL , InVT , <STR_LIT> ) ; SDValue MaskReinterpret = DAG . getNode ( <STR_LIT> , DL , OutVT ,


<s> } if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx xop2 = operands [ <NUM_LIT> ] ; if ( mode != vimode ) { xop2 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop2 , gen_rtx_SUBREG ( vimode , operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; } emit_move_insn ( src2 , xop2 ) ; } else { gcc_assert ( operands [ <NUM_LIT> ] == CONST0_RTX ( mode ) ) ; emit_move_insn ( src2 , mask ) ; } bsel = gen_rtx_IOR ( vimode , gen_rtx_AND ( vimode , gen_rtx_NOT ( vimode , mask ) , src2 ) , gen_rtx_AND ( vimode , mask , src1 ) ) ; emit_insn ( gen_rtx_SET ( mask ,


<s> auto & Tok = Lexer . getTok ( ) ; switch ( Tok . getKind ( ) ) { case AsmToken :: Identifier : { auto & Id = Lexer . getTok ( ) ; const MCExpr * Val ; SMLoc End ; if ( Parser . parsePrimaryExpr ( Val , End ) ) return Error ( <STR_LIT> , Lexer . getTok ( ) ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Id . getLoc ( ) , Id . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; break ; } case AsmToken :: Minus : Parser . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: Integer ) ) return Error ( <STR_LIT> , Lexer . getTok ( ) ) ; if ( ParseOperandStartingWithInteger ( true , Operands , NamePair . second ) ) return true ; break ; case AsmToken :: Integer : if ( ParseOperandStartingWithInteger ( false , Operands , NamePair . second ) ) return true ; break ; case AsmToken :: Real : { double Val ; if ( Tok . getString ( ) . getAsDouble ( Val , false ) ) return Error


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ,


<s> Inst . addOperand ( MCOperand :: createImm


<s> int f_target , n_target = <NUM_LIT> ; if ( optimize ) { if ( INSN_ADDRESSES_SIZE ( ) <= ( unsigned ) INSN_UID ( new_mova ) ) return - <NUM_LIT> ; n_addr = INSN_ADDRESSES ( INSN_UID ( new_mova ) ) ; n_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( new_mova ) , <NUM_LIT> ) ) ) ; if ( n_addr > n_target || n_addr + <NUM_LIT> < n_target ) { fixup_mova ( new_mova ) ; return <NUM_LIT> ; } } if ( ! ( * num_mova ) ++ ) { * first_mova = new_mova ; return <NUM_LIT> ; } if ( ! optimize || ( ( f_target = INSN_ADDRESSES ( INSN_UID ( XEXP ( MOVA_LABELREF ( * first_mova ) , <NUM_LIT> ) ) ) ) >= n_target ) ) return - <NUM_LIT> ; ( * num_mova ) -- ; if ( f_target - INSN_ADDRESSES ( INSN_UID ( * first_mova ) ) > n_target - n_addr ) { fixup_mova ( * first_mova ) ; return <NUM_LIT> ; } else { fixup_mova ( new_mova ) ; return


<s> bool Duplex = <ISA_LIT>MCInstrInfo :: isDuplex ( MCII , MCI ) ; if ( Instruction == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( Instruction != Last ) ; return <STR_LIT> ; } } if ( Instruction == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( Instruction


<s> void GCNTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { CommonTTI . getPeelingPreferences ( L , SE


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { StringRef CPU (


<s> for ( const MachineOperand & Use : VMEM -> uses ( ) ) { if ( ! Use . isReg ( ) || TRI . isVGPR ( MF . getRegInfo ( ) , Use . getReg ( ) ) ) continue ; int WaitStatesNeededForUse = VmemSgprWaitStates - getWaitStatesSinceDef ( Use . getReg ( ) , IsHazardDefFn , VmemSgprWaitStates ) ; WaitStatesNeeded = std :: max ( WaitStatesNeeded , WaitStatesNeededForUse ) ; } return WaitStatesNeeded


<s> switch ( rs6000_tune ) { case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : return <NUM_LIT> ; case


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) { Subtarget = & funcInfo . MF -> getSubtarget < <ISA_LIT>Subtarget >


<s> static rtx_insn * emit_window_save ( rtx increment ) { rtx_insn * insn = emit_insn ( gen_window_save ( increment ) ) ; RTX_FRAME_RELATED_P ( insn


<s> SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; assert ( BVN -> getOpcode ( ) == <STR_LIT> && BVN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; unsigned LowElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize


<s> unsigned Limit = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! I -> getOperand ( i ) . isFI ( ) ) continue ; const TargetInstrDesc & Desc = TII . get ( I -> getOpcode ( ) ) ; unsigned AddrMode = ( Desc . TSFlags & <STR_LIT> ) ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; if ( AddrMode == <STR_LIT> && hasFP ( MF ) )


<s> YamlIO . mapOptional ( <STR_LIT> , MFI . LDSSize , <NUM_LIT> ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . IsEntryFunction , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . NoSignedZerosFPMath , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . MemoryBound , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . WaveLimiter , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchRSrcReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchWaveOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . FrameOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . StackPtrOffsetReg , StringValue ( <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isCommutativeBinOp ( unsigned


<s> SDValue <ISA_LIT>TargetLowering :: SaveC0 ( SDValue Chain , const SDLoc & DL , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue GetC0Ops [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue GetC0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GetC0Ops ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned C0VirtReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue C0VirtRegNode = DAG . getCopyToReg ( Chain , DL , C0VirtReg , GetC0 ) ; FI -> setC0VirtReg ( C0VirtReg ) ; C0VirtRegNode . getNode ( ) ->

setNodeId ( PUSH_C0_FUNCTION_UNIQUE_ID ) ;


<s> unsigned getShaderType ( ) const { return ShaderType


<s> SDValue <ISA_LIT>TargetLowering :: Lower<ISA_LIT>NT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> &&


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( & DAG


<s> auto II = MI -> getIterator ( ) ; ++ II ; while ( II -> isInsideBundle ( ) ) { if ( II -> getOpcode ( ) == Opcode ) return & * II ; II ++ ; } return <NUM_LIT> ; } else { return MI -> getOpcode ( ) == Opcode ? MI :


<s> case 'A' : return InlineAsm :: Constraint_A ; default : break ; } } return TargetLowering :: getInlineAsmMemConstraint


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectMUBUFScratchOffset ( MachineOperand & Root ) const { MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; int64_t Offset = <NUM_LIT> ; if ( ! mi_match ( Root . getReg ( ) , * MRI , m_ICst ( Offset ) ) || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo (


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; bool DoesNotReturn = CLI . DoesNotReturn ; bool IsStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; unsigned NumParams = CLI . CS . getInstruction ( ) ? CLI . CS . getFunctionType ( ) -> getNumParams ( ) : <NUM_LIT> ; if ( GlobalAddressSDNode * GAN = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( GAN -> getGlobal ( ) , dl , <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) , NumParams ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; auto Attr = MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) ; if ( Attr . getValueAsString ( ) == <STR_LIT> ) CLI . IsTailCall = false ; if ( CLI . IsTailCall ) { bool StructAttrFlag = MF . getFunction ( ) . hasStructRetAttr ( ) ; CLI . IsTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , IsVarArg , IsStructRet , StructAttrFlag , Outs , OutVals , Ins , DAG ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isMemLoc ( ) ) { CLI . IsTailCall = false ; break ; } } LLVM_DEBUG ( dbgs ( ) << ( CLI . IsTailCall ? <STR_LIT> : <STR_LIT> <STR_LIT> ) ) ; } unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , HRI . getStackRegister ( ) , PtrVT ) ; bool NeedsArgAlign = false ; unsigned LargestAlignSeen = <NUM_LIT>


<s> } unsigned Op2Reg = <NUM_LIT> ; if ( ! UseImm ) { Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; } unsigned CmpOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CondReg = constrainOperandRegClass ( TII . get ( CmpOpc ) , CondReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ) ; unsigned MovCCOpc ; const TargetRegisterClass * RC ; if ( ! UseImm ) { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; if ( ! isNegativeImm ) MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; if ( ! UseImm ) { Op2Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op2Reg , <NUM_LIT> ) ; Op1Reg = constrainOperandRegClass ( TII . get ( MovCCOpc ) , Op1Reg , <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovCCOpc ) , ResultReg ) . addReg ( Op2Reg ) . addReg ( Op1Reg ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; }


<s> if ( reload_completed && rs6000_sched_groups ) { if ( sel_sched_p ( ) ) return ; if ( rs6000_sched_insert_nops == sched_finish_none ) return ; if ( rs6000_sched_insert_nops == sched_finish_pad_groups ) n_groups = pad_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; else n_groups = redefine_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ; if ( sched_verbose >= <NUM_LIT> ) { fprintf ( dump , <STR_LIT> , n_groups


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value <<= Info . TargetOffset ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; unsigned Offset = Fixup .


<s> return ( __m512i ) __builtin_ia32_pmovsxwd512_mask ( ( __v16hi ) __A , ( __v16si ) _mm512_setzero_si512 ( ) ,


<s> for ( auto & AssociatedAndMore : PriorityAndMore . second ) { Constant * Associated = AssociatedAndMore . first ; Function * CallDtors = Function :: Create ( AtExitFuncTy , Function :: PrivateLinkage , <STR_LIT> + ( Priority != UINT16_MAX ? ( Twine ( <STR_LIT> ) + Twine ( Priority ) ) : Twine ( ) ) + ( ! Associated -> isNullValue ( ) ? ( Twine ( <STR_LIT> ) + Associated -> getName ( ) ) : Twine ( ) ) , & M ) ; BasicBlock * BB = BasicBlock :: Create ( C , <STR_LIT> , CallDtors ) ; for ( auto Dtor : AssociatedAndMore . second ) CallInst :: Create ( Dtor , <STR_LIT> , BB ) ; ReturnInst :: Create ( C , BB ) ; FunctionType * VoidVoid = FunctionType :: get ( Type :: getVoidTy ( C ) , false ) ; Function * RegisterCallDtors = Function :: Create ( VoidVoid , Function :: PrivateLinkage , <STR_LIT> + ( Priority != UINT16_MAX ? ( Twine ( <STR_LIT> ) + Twine ( Priority ) ) : Twine ( ) ) + ( ! Associated -> isNullValue ( ) ? ( Twine ( <STR_LIT> ) + Associated -> getName ( ) ) : Twine ( ) ) , & M ) ; BasicBlock * EntryBB = BasicBlock :: Create ( C , <STR_LIT> , RegisterCallDtors ) ; BasicBlock * FailBB = BasicBlock :: Create ( C , <STR_LIT> , RegisterCallDtors ) ; BasicBlock * RetBB = BasicBlock :: Create ( C , <STR_LIT> , RegisterCallDtors ) ; Value * Null = ConstantPointerNull :: get ( VoidStar ) ; Value * Args [ ] = { CallDtors , Null , DsoHandle } ; Value * Res = CallInst :: Create ( AtExit , Args , <STR_LIT> , EntryBB ) ; Value * Cmp = new ICmpInst ( * EntryBB , ICmpInst :: ICMP_NE , Res , Constant :: getNullValue ( Res -> getType ( ) ) ) ; BranchInst :: Create ( FailBB , RetBB , Cmp , EntryBB ) ; CallInst :: Create ( <STR_LIT> ( & M , <STR_LIT> ) , <STR_LIT> , FailBB ) ; new UnreachableInst ( C , FailBB )


<s> OperandMatchResultTy parseBDAddr32 ( OperandVector & Operands


<s> auto DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; return addOperand ( Inst , DAsm -> decodeSrcOp ( <ISA_LIT>Disassembler ::


<s> auto TheReg = <STR_LIT> ( RegString .


<s> -- I ; const int opcode = I -> getOpcode ( ) ; if ( opcode == <STR_LIT> ) continue ; if ( ! I -> getDesc ( ) . isBranch ( ) || opcode == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_VectorCall ) return CSR_<ISA_LIT>_AAVPCS_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF

-> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ;


<s> <STR_LIT> CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str =


<s> unspec = XEXP ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) , <NUM_LIT> ) ; return ( GET_CODE ( unspec ) == UNSPEC && XINT

( unspec , <NUM_LIT> ) == UNSPEC_PCREL_SYM ) ;


<s> return ( uint32_t ) __builtin_neon_vget_laneuv2si ( ( int32x2_t )


<s> static const uint16_t CtrlReg64DecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> switch ( mode ) { case E_SFmode : index = <NUM_LIT> ; break ; case E_DFmode : index = <NUM_LIT> ; break ; case E_XFmode : index = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> fp_load [ index ] , ix86_cost -> fp_store [ index ] ) ; return in ? ix86_cost -> fp_load [ index ] : ix86_cost -> fp_store [ index ] ; } if ( SSE_CLASS_P ( regclass ) ) { int index = sse_store_index ( mode ) ; if ( index == - <NUM_LIT> ) return <NUM_LIT> ; if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> sse_load [ index ] , ix86_cost -> sse_store [ index ] ) ; return in ? ix86_cost -> sse_load [ index ] : ix86_cost -> sse_store [ index ] ; } if ( MMX_CLASS_P ( regclass ) ) { int index


<s> MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand =

MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - <NUM_LIT> ) ; return NULL ; } switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) { return CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( )


<s> PreAnalyzeFormalArgumentsForF128 ( Ins ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloatVector . clear (


<s> if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( needsStackRealignment ( MF ) ) { if ( CSSize ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; MBBI = prior ( LastCSPop ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else if ( MFI -> hasVarSizedObjects ( ) ) { if ( CSSize ) { unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = addLeaRegOffset ( BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; MBB . insert ( MBBI , MI ) ; } else BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( FramePtr ) ; } else { if ( NumBytes ) emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = prior ( MBB . end ( ) ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; int MaxTCDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; int Offset = <NUM_LIT> ; assert ( MaxTCDelta <= <NUM_LIT> && <STR_LIT> ) ; Offset = StackAdj - MaxTCDelta ; assert ( Offset >= <NUM_LIT> && <STR_LIT> ) ; if ( Offset ) { Offset += mergeSPUpdates ( MBB , MBBI , StackPtr , true ) ; emitSPUpdate ( MBB , MBBI , StackPtr , Offset , Is64Bit , TII ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) ) ; else if ( RetOpcode == <STR_LIT> ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , JumpTarget . getReg ( ) ) ; else BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , JumpTarget .


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) ,


<s> static inline bool is_float128_p ( tree t ) { return ( t == float128_type_node || ( t && t == float128t_type_node ) || ( TARGET_IEEEQUAD &&

TARGET_LONG_DOUBLE_128 && t == long_double_type_node ) ) ;


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ; return


<s> <ISA_LIT>MCExpr :: VariantKind ExprKind = McExpr -> getKind ( ) ; switch ( ExprKind ) { case <ISA_LIT>MCExpr :: VK_None : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_ABS_HI : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_ABS_LO


, op1 ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ;


<s> case <STR_LIT> : case <STR_LIT> : return true ; default : return false


<s> auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; TM . resetSubtarget ( & MF ) ; return


<s> Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , FPtr , Addr ,


<s> CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = isThumb ? <STR_LIT> : <STR_LIT> ; break ; } CmpInst :: Predicate Predicate = CI -> getPredicate ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; Predicate = CmpInst :: getInversePredicate ( Predicate ) ; } <STR_LIT> <ISA_LIT>Pred = getComparePred ( Predicate ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; unsigned Arg1 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg1 == <NUM_LIT> ) return false ; unsigned Arg2 = getRegForValue ( CI -> getOperand ( <NUM_LIT> ) ) ; if ( Arg2 == <NUM_LIT> ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( Arg1 ) . addReg ( Arg2 ) ) ; if ( isFloat ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ) ; unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return


) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get (


<s> int SlotSize = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; int NewRetAddrLoc = SPDiff + <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewRetAddr = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewRetAddrLoc , true ) ; EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , PseudoSourceValue :: getFixedStack ( NewRetAddr ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( isDarwinABI ) { int NewFPLoc = SPDiff + <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx , VT ) ; Chain = DAG . getStore ( Chain , dl , OldFP , NewFramePtrIdx , PseudoSourceValue :: getFixedStack ( NewFPIdx ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } } return


<s> void <ISA_LIT>PostRASchedStrategy :: leaveMBB ( ) { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; ) ; advanceTo ( MBB -> getFirstTerminator ( ) )


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return Success


<s> for ( MachineOperand & Use : MI . implicit_operands ( ) ) { if ( Use . isUse ( ) && Use .


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT>


<s> if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT>


<s> BOOL DllMain ( HINSTANCE libraryId __attribute__ ( ( __unused__ ) ) , DWORD reason , void * hModule ) { switch ( reason ) { case DLL_NLM_STARTUP : allocRTag = AllocateResourceTag ( hModule , <STR_LIT> , AllocSignature ) ; return allocRTag != NULL ; case DLL_NLM_SHUTDOWN : break ; } return <NUM_LIT>


<s> int size = s390_function_arg_size ( mode , type ) ; if ( s390_function_arg_vector ( mode , type ) ) return false ; if ( size > <NUM_LIT> ) return true ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) && exact_log2 ( size ) < <NUM_LIT> ) return true ; if ( TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE


<s> void printAMIndexed16WB ( const MCInst * MI , unsigned OpNum , raw_ostream &


<s> typedef std :: pair < unsigned , RegisterBump > RegisterInduction ; typedef std :: set < RegisterInduction > RegisterInductionSet ; RegisterInductionSet IndRegs ; typedef MachineBasicBlock :: instr_iterator instr_iterator ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * Phi = & * I ; for ( unsigned i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { if ( Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) != Latch ) continue ; unsigned PhiReg = Phi -> getOperand ( i ) . getReg ( ) ; MachineInstr * DI = MRI -> getVRegDef ( PhiReg ) ; unsigned UpdOpc = DI -> getOpcode ( ) ; bool isAdd = ( UpdOpc == <STR_LIT> ) ; if ( isAdd ) { unsigned IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getVRegDef ( IndReg ) == Phi ) { unsigned UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t V = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; IndRegs . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } if ( IndRegs . empty ( ) ) return false ; MachineBasicBlock * TB = <NUM_LIT> , * FB = <NUM_LIT> ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool NotAnalyzed = TII -> AnalyzeBranch ( * Latch , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return false ; if ( Cond . empty ( ) ) return false ; if ( TB != Header && FB != Header ) return false ; unsigned CSz = Cond . size ( ) ; if ( CSz != <NUM_LIT> && CSz != <NUM_LIT> ) return false ; unsigned P = Cond [ CSz - <NUM_LIT> ] . getReg ( ) ; MachineInstr * PredDef = MRI -> getVRegDef (


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins


<s> if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P (

next ) && NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION ) insn = next ;


<s> Function * F = getAssociatedFunction ( ) ; auto & InfoCache = static_cast < <ISA_LIT>InformationCache & > ( A . getInfoCache ( ) ) ; unsigned MinGroupSize , MaxGroupSize ; std :: tie ( MinGroupSize , MaxGroupSize ) = InfoCache . getFlatWorkGroupSizes ( * F ) ; intersectKnown ( ConstantRange ( APInt ( <NUM_LIT> , MinGroupSize ) , APInt

( <NUM_LIT> , MaxGroupSize + <NUM_LIT> ) ) ) ;


<s>
case
Match_InvalidOperand
:
WasOriginallyInvalidOperand
=
true
;
break
;
case
Match_MnemonicFail
:
break
;
}
StringRef
Base
=
Op
->
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
->
setTokenValue
(
Tmp
.
str
(
)
)
;
const
char
*
Suffixes
=
Base
[
<NUM_LIT>
]
!=
'f'
<STR_LIT>
:
<STR_LIT>
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
unsigned
ErrorInfoIgnore
;
MatchResultTy
Match1
,
Match2
,
Match3
,
Match4
;
Match1
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match2
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match3
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Tmp
[
Base
.
size
(
)
]
=
Suffixes
[
<NUM_LIT>
]
;
Match4
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfoIgnore
)
;
Op
->
setTokenValue
(
Base
)
;
unsigned
NumSuccessfulMatches
=
(
Match1
==
Match_Success
)
+
(
Match2
==
Match_Success
)
+
(
Match3
==
Match_Success
)
+
(
Match4
==
Match_Success
)
;
if
(
NumSuccessfulMatches
==
<NUM_LIT>
)
{
Out
.
EmitInstruction
(
Inst
)
;
return
false
;
}
if
(
NumSuccessfulMatches
>
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>
]
;
unsigned
NumMatches
=
<NUM_LIT>
;
if
(
Match1
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match2
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match3
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
if
(
Match4
==
Match_Success
)
MatchChars
[
NumMatches
++
]
=
Suffixes
[
<NUM_LIT>
]
;
SmallString
<
<NUM_LIT>
>
Msg
;
raw_svector_ostream
OS
(
Msg
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
!=
NumMatches
;
++
i
)
{
if
(
i
!=
<NUM_LIT>
)
OS
<<
<STR_LIT>
;
if
(
i
+
<NUM_LIT>
==
NumMatches
)
OS
<<
<STR_LIT>
;
OS
<<
<STR_LIT>
<<
Base
<<
MatchChars
[
i
]
<<
<STR_LIT>
;
}
OS
<<
<STR_LIT>
;
Error
(
IDLoc
,
OS
.
str
(
)
)
;
return
true
;
}
if
(
(
Match1
==
Match_MnemonicFail
)
&&
(
Match2
==
Match_MnemonicFail
)
&&
(
Match3
==
Match_MnemonicFail
)
&&
(
Match4
==
Match_MnemonicFail
)
)
{
if
(
!
WasOriginallyInvalidOperand
)
{
Error
(
IDLoc
,
<STR_LIT>
+
Base
+
<STR_LIT>
)
;
return
true
;
}
SMLoc
ErrorLoc
=
IDLoc
;
if
(
OrigErrorInfo
!=
~
<NUM_LIT>
)
{
if
(
OrigErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
<STR_LIT>
)
;
ErrorLoc
=
(
(
<ISA_LIT>Operand
*
)
Operands
[
OrigErrorInfo
]
)
->
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=


<s> if ( is_critical_func ( ) ) fprintf ( outfile , <STR_LIT> ) ; if ( is_wakeup_func ( ) ) fprintf ( outfile , <STR_LIT> ) ; fprintf ( outfile , <STR_LIT> ) ; } fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize_regs ) ; fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize_locals ) ; fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize_outgoing ) ; fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize ) ; fprintf ( outfile , <STR_LIT> , msp430_initial_elimination_offset ( ARG_POINTER_REGNUM , FRAME_POINTER_REGNUM ) ) ; fprintf ( outfile , <STR_LIT> , msp430_initial_elimination_offset ( FRAME_POINTER_REGNUM , STACK_POINTER_REGNUM ) ) ; n = <NUM_LIT> ; fprintf ( outfile


<s> if ( Kind != k_VectorIndex ) return false ; return VectorIndex . Val <


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI ->

getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> if ( N -> isOnlyUserOf ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> isOnlyUserOf ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { SDValue N0 = peekThroughOneUseBitcasts ( N . getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughOneUseBitcasts ( N . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpcode = N0 . getOpcode ( ) ; if ( TLI . isBinOp ( SrcOpcode ) && N1 . getOpcode ( ) == SrcOpcode && IsSafeToMoveShuffle ( N0 , SrcOpcode ) && IsSafeToMoveShuffle ( N1 , SrcOpcode ) ) { SDValue Op00 = peekThroughOneUseBitcasts ( N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Op10 = peekThroughOneUseBitcasts ( N1 . getOperand ( <NUM_LIT> ) ) ; SDValue Op01 = peekThroughOneUseBitcasts ( N0 . getOperand ( <NUM_LIT> ) ) ; SDValue Op11 = peekThroughOneUseBitcasts ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ( ( IsMergeableWithShuffle ( Op00 ) && IsMergeableWithShuffle ( Op10 ) ) || ( IsMergeableWithShuffle ( Op01 ) && IsMergeableWithShuffle ( Op11 ) ) ) || ( ( IsMergeableWithShuffle ( Op00 ) || IsMergeableWithShuffle ( Op10 ) ) && ( IsMergeableWithShuffle ( Op01 ) || IsMergeableWithShuffle ( Op11 ) ) ) ) { SDValue LHS , RHS ; Op00 = DAG . getBitcast ( ShuffleVT , Op00 ) ; Op10 = DAG . getBitcast ( ShuffleVT , Op10 ) ; Op01 = DAG . getBitcast ( ShuffleVT , Op01 ) ; Op11 = DAG . getBitcast ( ShuffleVT , Op11 ) ; if ( N . getNumOperands ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( Opc , DL , ShuffleVT , Op00 , Op10 , N . getOperand ( <NUM_LIT> ) ) ; RHS = DAG . getNode ( Opc , DL , ShuffleVT , Op01 , Op11 , N . getOperand ( <NUM_LIT> ) ) ; } else { LHS = DAG . getNode ( Opc , DL , ShuffleVT , Op00 , Op10 ) ; RHS = DAG . getNode ( Opc , DL , ShuffleVT , Op01 , Op11 ) ; } EVT OpVT = N0 . getValueType


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; else { assert ( MO . isImm ( ) && <STR_LIT> ) ; return static_cast < unsigned > ( MO . getImm (


<s> rtx_vector_builder v ( mode , nelts , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < nelts ; i ++ ) { rtx x = builder . elt ( i + nelts_reqd - n_trailing_constants ) ; if ( ! valid_for_const_vector_p ( elem_mode , x ) ) x = const0_rtx ; v . quick_push ( x ) ; } rtx const_vec = v . build ( ) ; emit_move_insn ( target