<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) Suffix = <STR_LIT> ; else if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) Suffix = <STR_LIT> ; std :: string Name = Mang -> getMangledName ( GV , Suffix , Suffix [ <NUM_LIT> ] != '\0' ) ; if ( Subtarget -> isTargetCygMing ( ) ) DecorateCygMingName ( Name , GV ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) Name = <STR_LIT> + Name ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) GVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) HiddenGVStubs [ Name ] = Mang -> getMangledName ( GV ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) FnStubs [ Name ] = Mang -> getMangledName ( GV ) ; if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; printOffset ( MO . getOffset ( ) ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { std :: string Name = Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { FnStubs [ Name + <STR_LIT> ] = Name ; Name += <STR_LIT> ; } if ( Name [ <NUM_LIT> ] == '$' ) O << '(' << Name << ')' ; else O << Name ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT>


<s> I != E ; ) { SDNode * Node = & * I ++ ; unsigned Opcode = Node -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) PreprocessLoad ( Node , I ) ; else if ( Opcode == <STR_LIT> ) PreprocessCopyToReg ( Node ) ; else if ( Opcode == <STR_LIT> )


<s> if ( AddressSpace == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) return AddressSpaceQualifier :: Private ; if ( AddressSpace == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS ) return AddressSpaceQualifier :: Global ; if ( AddressSpace == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) return AddressSpaceQualifier :: Constant ; if ( AddressSpace == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS ) return AddressSpaceQualifier


<s> return ( __m512i ) __builtin_ia32_vcvttph2w512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( ) , ( __mmask32 ) - <NUM_LIT> ,


<s> if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; <ISA_LIT>FI = MF . getInfo <


<s> return ( ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode ( ) == <STR_LIT> ) || ( MI . getOpcode ( )


<s> if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub && isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) ) return true ; auto AddendExpr = dyn_cast < MCConstantExpr > (


<s> CCState CCInfo ( CFlags . CallConv , CFlags . IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; const unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; const bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; const EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const unsigned PtrByteSize = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; CCInfo . AllocateStack ( LinkageSize , PtrByteSize ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_AIX ) ; const unsigned MinParameterSaveAreaSize = <NUM_LIT> * PtrByteSize ; const unsigned NumBytes = std :: max ( LinkageSize + MinParameterSaveAreaSize , CCInfo . getNextStackOffset ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; const SDValue StackPtr = Is<ISA_LIT>64 ? DAG . getRegister ( <STR_LIT> , <STR_LIT> ) : DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ) { CCValAssign & VA = ArgLocs [ I ++ ] ; SDValue Arg = OutVals [ VA . getValNo ( ) ] ; if ( ! VA . isRegLoc ( ) && ! VA . isMemLoc ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { switch ( VA . getLocInfo ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } if ( VA . isMemLoc ( ) ) { SDValue PtrOff = DAG . getConstant ( VA . getLocMemOffset ( ) , dl , StackPtr . getValueType ( ) ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; continue ; } assert ( VA . isRegLoc ( ) && VA . needsCustom ( ) && CFlags . IsVarArg && VA . getValVT ( ) . isFloatingPoint ( ) && VA . getLocVT ( ) . isInteger ( ) && <STR_LIT> ) ; SDValue ArgAsInt = DAG . getBitcast ( <STR_LIT> ( VA . getValVT


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < MemoryDependenceWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass >


<s> } else if ( ST -> hasVector ( ) ) { auto * SrcVecTy = cast < FixedVectorType > ( Src ) ; auto * DstVecTy = cast < FixedVectorType > ( Dst ) ; unsigned VF = SrcVecTy -> getNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits == <NUM_LIT> || ST -> hasVectorEnhancements2 ( ) ) { if ( SrcScalarBits == DstScalarBits ) return NumDstVectors ; if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) + NumDstVectors ; } unsigned ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) , CostKind ) ; unsigned TotCost = VF * ScalarCost ; bool NeedsInserts = true , NeedsExtracts = true ; if ( DstScalarBits == <NUM_LIT> && ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) ) NeedsInserts = false ; if ( SrcScalarBits == <NUM_LIT> && ( Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) ) NeedsExtracts = false ; TotCost += getScalarizationOverhead ( SrcVecTy , false , NeedsExtracts ) ; TotCost += getScalarizationOverhead ( DstVecTy , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ; return TotCost ; } if ( Opcode == Instruction :: FPTrunc ) { if ( SrcScalarBits == <NUM_LIT> ) return VF + getScalarizationOverhead ( DstVecTy , true , false ) ; else return VF / <NUM_LIT> + std :: max ( <NUM_LIT> , VF / <NUM_LIT> ) ; } if ( Opcode == Instruction :: FPExt ) { if ( SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) { return VF * <NUM_LIT> ; } return VF + getScalarizationOverhead ( SrcVecTy , false , true ) ; } } return BaseT :: getCastInstrCost ( Opcode , Dst , Src , CostKind ,


<s> if ( UnsupportedFPMode ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue


<s> unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Load -> getAlignment ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } unsigned NumElements = MemVT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: CONSTANT_ADDRESS : if ( isMemOpUniform ( Load ) ) return SDValue ( ) ; case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <ISA_LIT>AS ::


<s> SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL . getABITypeAlignment ( Ty ) ; <STR_LIT> ExtTy = Signed ? <STR_LIT> : <STR_LIT> ; if ( MemVT . isFloatingPoint ( ) ) ExtTy = <STR_LIT> ; return DAG . getLoad ( <STR_LIT> , ExtTy , VT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemVT


<s> static void rename_fma_node ( fma_forest * forest , fma_node * node ) { node -> rename ( forest


<s> StringRef modName = Parser . getTok ( ) . getString ( ) ; if ( modName == <STR_LIT> || modName == <STR_LIT> || modName == <STR_LIT> ) { Operands . push_back ( <STR_LIT> ( modName , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex (


<s> if ( MEM_VOLATILE_P ( mem [ i ] ) ) return false ; extract_base_offset_in_addr ( mem [ i ] , base + i , offset + i ) ; if ( base [ i ] == NULL_RTX || offset [ i ] == NULL_RTX ) return false ; } rclass = REG_P ( reg [ <NUM_LIT> ] ) && FP_REGNUM_P ( REGNO ( reg [ <NUM_LIT> ] ) ) ? FP_REGS : GENERAL_REGS ; for ( int i = <NUM_LIT> ; i < num_insns ; i ++ ) if ( REG_P ( reg [ i ] ) && FP_REGNUM_P ( REGNO ( reg [ i ] ) ) ) { if ( rclass != FP_REGS ) return false ; } else { if ( rclass != GENERAL_REGS ) return false ; } if ( rclass == GENERAL_REGS && load ) for ( int i = <NUM_LIT> ; i < num_insns - <NUM_LIT> ; i ++ ) if ( reg_mentioned_p ( reg [ i ] , mem [ i ] ) ) return false ; for ( int i = <NUM_LIT> ; i < num_insns - <NUM_LIT> ; i ++ ) if ( ! rtx_equal_p ( base [ i ] , base [ i + <NUM_LIT> ] ) ) return false ; for ( int i = <NUM_LIT> ; i < num_insns ; i ++ ) offvals [ i ] = INTVAL ( offset [ i ] ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; qsort ( offvals , num_insns , sizeof ( HOST_WIDE_INT ) , aarch64_host_wide_int_compare ) ; if ( ! ( offvals [ <NUM_LIT> ] == offvals [ <NUM_LIT> ] + msize && offvals [ <NUM_LIT> ] == offvals [ <NUM_LIT> ] + msize ) ) return false ; if ( offvals [ <NUM_LIT> ] - offvals [ <NUM_LIT> ] >= msize * <NUM_LIT> ) return false ; if ( offvals [ <NUM_LIT> ] % msize != offvals [ <NUM_LIT> ] % msize ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem [ <NUM_LIT> ] ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; return true


<s> NodeList Rel = getRelatedRefs ( IA , DA ) ; NodeAddr < DefNode * > PDA = Rel . front ( ) ; RegisterRef RR = PDA . Addr -> getRegRef ( ) ; if ( ! Defined . insert ( RR ) . second ) { auto * MI = NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; dbgs ( ) << <STR_LIT> << Print < RegisterRef > ( RR , * this ) << <STR_LIT> << * MI << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << '\n' ; llvm_unreachable ( nullptr ) ; } DefM [ RR ] . push


<s> } if ( Subtarget -> isABI_O32 ( ) ) { if ( RegVT == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; if ( RegVT == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { unsigned Reg2 = AddLiveIn ( DAG . getMachineFunction ( ) , VA . getLocReg ( ) + <NUM_LIT> , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , dl , Reg2 , RegVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; ArgRegEnd = <NUM_LIT> ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , <NUM_LIT> , true ) ; <ISA_LIT>FI -> recordLoadArgsFI ( FI , - ( ArgSize + ( FirstStackArgLoc + VA . getLocMemOffset ( ) ) ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , Reg , InVals [ <NUM_LIT> ] ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Copy , Chain ) ; } if ( ( isVarArg ) && ( Subtarget ->


<s> SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( InsertOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } unsigned LaneTmp2 = RegInfo . createVirtualRegister ( GPRRC


<s> LastEMS = LastMappingSymbols . lookup ( Section ) ; MCELFStreamer :: ChangeSection ( Section , Subsection


<s> Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Type * Ty = Input -> getType ( ) ; if ( ! ( Ty -> getVectorNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) { return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) } , { Ptr , Builder . getInt32 ( <NUM_LIT> ) , Input } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) , Input -> getType ( ) , Mask -> getType ( )

} , { Ptr , Builder . getInt32 ( <NUM_LIT> ) , Input , Mask } ) ;


<s> auto BB = R . Begin -> getParent ( ) ; Sch . BaseClass :: startBlock ( BB ) ; Sch . BaseClass :: enterRegion ( BB , R . Begin , R . End , R . NumRegionInstrs ) ; Sch . buildSchedGraph ( Sch . AA , nullptr , nullptr , nullptr , true ) ; Sch . Topo . InitDAGTopologicalSorting ( ) ; SmallVector < SUnit * , <NUM_LIT> > BotRoots ; Sch . findRootsAndBiasEdges ( TopRoots


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int


<s> return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT>


) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT ,

CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) :


<s> static inline unsigned T2Morph2Preload2PCI ( unsigned Opcode ) { switch ( Opcode ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case


<s> bool NeedCFI = MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) -> needsUnwindTableEntry ( ) ; if ( ! NeedCFI )


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 (


<s> default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V4SImode : { rtx t1 , t2 , mask ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv4si3 ( t1 , cop0 , cop1 ) ) ; mask = GEN_INT ( - <NUM_LIT> ) ; mask = gen_rtx_CONST_VECTOR ( mode , gen_rtvec ( <NUM_LIT> , mask , mask , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_andv4si3 ( t2 , cop0 , mask ) ) ; x = gen_reg_rtx ( mode ) ; emit_insn ( gen_xorv4si3 ( x , t1 , t2 ) ) ; code = GT ; } break ; case V16QImode : case V8HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , cop0 , cop1 ) ) ) ; code = EQ ; negate = ! negate ; break ; default : gcc_unreachable (


<s> int unsignedp ; } ; static struct cmp_info info [ ( int ) ITEST_MAX ] = { { EQ , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { NE , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LT , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GE , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LT , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GE , xtensa_b4const_or_zero , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LTU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GEU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { LTU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { GEU , xtensa_b4constu , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; enum internal_test test ; enum machine_mode mode ; struct cmp_info * p_info ; test = map_test_to_internal_test ( test_code ) ; gcc_assert ( test != ITEST_MAX ) ; p_info = & info [ ( int ) test ] ; mode = GET_MODE ( cmp0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( cmp1 ) ; if ( GET_CODE ( cmp1 ) == CONST_INT ) { HOST_WIDE_INT value = INTVAL


<s> std :: pair < std :: string , std :: string > Result ; Result . first = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( CPU


<s> static unsigned int sh_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( XD_REGISTER_P ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , <NUM_LIT> * UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE (


<s> int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) : CurDAG ->

getTargetConstant ( - RHSC , <STR_LIT> ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op .


<s> if ( ! ( ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) || ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) ) { unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ; return DAG . getBitcast ( VT , FPLogic ) ; } if ( VT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> CC0 = cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> CC1 = cast < CondCodeSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( ! Subtarget . hasAVX ( ) && ! ( cheap<ISA_LIT>FSETCC_SSE ( CC0 ) && cheap<ISA_LIT>FSETCC_SSE ( CC1 ) ) ) return SDValue ( ) ; unsigned NumElts = <NUM_LIT> / N00Type . getSizeInBits ( ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , N00Type , NumElts ) ; EVT BoolVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue ZeroIndex = DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 . getOperand ( <NUM_LIT> ) ; SDValue Vec00 = DAG . getNode ( <STR_LIT> , DL , VecVT , N00 ) ; SDValue Vec01 = DAG . getNode ( <STR_LIT> , DL , VecVT , N01 ) ; SDValue Vec10 = DAG . getNode ( <STR_LIT> , DL , VecVT , N10 ) ; SDValue Vec11 = DAG . getNode ( <STR_LIT> , DL , VecVT , N11 ) ; SDValue Setcc0 = DAG . getSetCC ( DL , BoolVecVT , Vec00 , Vec01 , CC0 ) ; SDValue Setcc1 = DAG . getSetCC ( DL , BoolVecVT , Vec10 , Vec11 , CC1 ) ; SDValue Logic = DAG . getNode ( N -> getOpcode ( ) , DL , BoolVecVT , Setcc0 , Setcc1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Logic


<s> StringRef getVType ( SmallString < <NUM_LIT> > & Buf ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ; Buf . append ( getSEWStr ( VType . Sew ) ) ; Buf . append ( <STR_LIT> ) ; Buf . append ( getLMULStr ( VType . Lmul ) ) ; return Buf . str


<s> SDValue <STR_LIT> ( EVT DestVT , SDValue LoVec , SDValue HiVec , SDValue AVL ) const { assert ( getAnnotatedNodeAVL ( AVL ) .


<s> if ( ! <STR_LIT> ( Subtarget . getTargetABI ( ) ) ) return TailPaddingAmount


<s> if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { int FI = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } Register SAddr = AddrDef -> Reg ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef && RHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ; return


<s> { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; assert ( CC <= LAST_VALID_COND &&


<s> RegisterAsmParser < <ISA_LIT>ATTAsmParser > X


<s> if ( ( flags & ( ISA_3_0_MASKS_SERVER & ~ ISA_2_7_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_7_MASKS_SERVER & ~ ISA_2_6_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_6_MASKS_SERVER & ~ ISA_2_5_MASKS_SERVER ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_5_MASKS_SERVER & ~ ISA_2_4_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ( ISA_2_4_MASKS & ~ ISA_2_1_MASKS ) ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & ISA_2_1_MASKS ) != <NUM_LIT> ) return <STR_LIT> ; if ( ( flags & OPTION_MASK_POWERPC64 ) !=


<s> LGKMCnt |= IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : LGKMCnt |= IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( VMCnt || LGKMCnt ) { unsigned WaitCntImmediate = <STR_LIT> ( IV , VMCnt ? <NUM_LIT> : getVmcntBitMask ( IV ) , getExpcntBitMask ( IV ) , LGKMCnt ? <NUM_LIT> : getLgkmcntBitMask ( IV ) ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( WaitCntImmediate ) ; Changed = true ; } if ( VSCnt ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) .

addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) ;


<s> static DecodeStatus DecodeQTripleRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeRegisterClassByID ( Inst , RegNo , <STR_LIT>


<s> static inline machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) ; gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n )


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128ToCall ( Op , DAG , LC


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) .

addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_15 ; } else if ( AMDGPU :: VReg_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_32RegClass . contains ( SrcReg ) || AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_MOV_B32_e32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: VReg_64RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_64RegClass . contains ( SrcReg ) || AMDGPU :: SReg_64RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: V_MOV_B32_e32 ; SubIndices = Sub0_1 ; } else if ( AMDGPU :: VReg_96RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_96RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: V_MOV_B32_e32 ; SubIndices = Sub0_2 ; } else if ( AMDGPU :: VReg_128RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_128RegClass . contains ( SrcReg ) || AMDGPU :: SReg_128RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: V_MOV_B32_e32 ; SubIndices = Sub0_3 ; } else if ( AMDGPU :: VReg_256RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_256RegClass . contains ( SrcReg ) || AMDGPU :: SReg_256RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: V_MOV_B32_e32 ; SubIndices = Sub0_7 ; } else if ( AMDGPU :: VReg_512RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_512RegClass . contains ( SrcReg ) || AMDGPU :: SReg_512RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: V_MOV_B32_e32 ; SubIndices = Sub0_15 ; } else { llvm_unreachable (


<s> switch ( N . getOpcode ( ) ) { default : break ; case <STR_LIT> : { uint64_t Val = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; AM . Disp += Val ; return false ; } case <STR_LIT> : if ( ! MatchWrapper ( N , AM ) ) return false ; break ; case <STR_LIT> : if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == nullptr ) { AM . BaseType = <ISA_LIT>ISelAddressMode :: FrameIndexBase ; AM . Base . FrameIndex = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; return false ; } break ; case <STR_LIT> : { <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; break ; } case <STR_LIT> : if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; uint64_t Offset = CN -> getSExtValue ( ) ; if ( ! MatchAddress ( N . getOperand ( <NUM_LIT> ) , AM ) && AM . GV == nullptr && CurDAG -> MaskedValueIsZero ( N . getOperand ( <NUM_LIT> ) , CN -> getAPIntValue ( ) ) ) { AM . Disp += Offset ; return false


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF ,


<s> unsigned LastOp = TII -> getOperandIdx ( MI -> getOpcode ( ) , AMDGPU


<s> const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget & STI = * static_cast < const <ISA_LIT>Subtarget *


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return false


<s> if ( ! InstDesc . isConditionalBranch ( ) ) return false ; if ( ! isFirstMacroFusibleInst ( Cmp , * MCII ) ) return false ; const <STR_LIT> CmpKind = <STR_LIT> ( Cmp .


<s> if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isLDM ) ; } else O << <STR_LIT> ( Mode ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Mode == <STR_LIT> ) O << <STR_LIT> ; } else { printOperand ( MI , Op ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) )


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && MI -> isCompare ( ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> removeFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; CompleteCCUsers = true ; continue ; } Reference CCRefs ( getRegReferences ( MI , <STR_LIT> ) ) ; if ( CCRefs . Def ) { CCUsers . clear ( ) ; CompleteCCUsers = ! CCRefs .


<s> if ( Is32BitImm ) { if ( isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ) { ImmValue = SignExtend64 < <NUM_LIT> > ( ImmValue ) ; } else { Error ( IDLoc , <STR_LIT> ) ; return true ; } } bool UseSrcReg = false ; if ( SrcReg != <STR_LIT> ) UseSrcReg = true ; unsigned TmpReg = DstReg ; if ( UseSrcReg && ( DstReg == SrcReg ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TmpReg = ATReg ; } if ( isInt < <NUM_LIT> > ( ImmValue ) ) { if ( ! UseSrcReg ) SrcReg = <STR_LIT> ; emitRRI ( <STR_LIT> , DstReg , SrcReg , ImmValue , IDLoc , Instructions ) ; } else if ( isUInt < <NUM_LIT> > ( ImmValue ) ) { unsigned TmpReg = DstReg ; if ( SrcReg == DstReg ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TmpReg = ATReg ; } emitRRI ( <STR_LIT> , TmpReg , <STR_LIT> , ImmValue , IDLoc , Instructions ) ; if ( UseSrcReg ) emitRRR ( <STR_LIT> , DstReg , TmpReg , SrcReg , IDLoc , Instructions ) ; } else if ( isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ) { warnIfNoMacro ( IDLoc ) ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits15To0 = ImmValue & <NUM_LIT> ; if ( ! Is32BitImm && ! isInt < <NUM_LIT> > ( ImmValue ) ) { emitRRI ( <STR_LIT> , TmpReg , <STR_LIT> , Bits31To16 , IDLoc , Instructions ) ; emitRRI ( <STR_LIT> , TmpReg , TmpReg , <NUM_LIT> , IDLoc , Instructions ) ; } else emitRI ( <STR_LIT> , TmpReg , Bits31To16 , IDLoc , Instructions ) ; createLShiftOri < <NUM_LIT> > ( Bits15To0 , TmpReg , IDLoc , Instructions ) ; if ( UseSrcReg ) createAddu ( DstReg , TmpReg , SrcReg , ! Is32BitImm , Instructions ) ; } else if ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> ) { warnIfNoMacro ( IDLoc ) ; uint16_t Bits47To32 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits15To0 = ImmValue & <NUM_LIT> ; emitRI ( <STR_LIT> , TmpReg , Bits47To32 , IDLoc , Instructions ) ; createLShiftOri < <NUM_LIT> > ( Bits31To16 , TmpReg , IDLoc , Instructions ) ; createLShiftOri < <NUM_LIT> > ( Bits15To0 , TmpReg , IDLoc , Instructions ) ; if ( UseSrcReg ) createAddu ( DstReg , TmpReg , SrcReg , ! Is32BitImm , Instructions ) ; } else { warnIfNoMacro ( IDLoc ) ; uint16_t Bits63To48 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits47To32 = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; uint16_t Bits31To16 = ( ImmValue >> <NUM_LIT> )


<s> for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = Mask [ i + l ] ; unsigned RngStart = l + ( ( Commuted == ( i < HalfLaneElems ) ) ? NumElems : <NUM_LIT> ) ; if ( ! isUndefOrInRange ( Idx , RngStart , RngStart + NumLaneElems ) ) return false ; if ( NumElems != <NUM_LIT> || l == <NUM_LIT> || Mask [ i ] < <NUM_LIT> ) continue ; if ( ! isUndefOrEqual ( Idx , Mask [ i


<s> if ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) ) { if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) unroll = <NUM_LIT> ; else { lastbyte = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( optimize_size || INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) unroll = <NUM_LIT> ; else if ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) unroll = <NUM_LIT> ; else unroll = <NUM_LIT> ; } operands [ <NUM_LIT> ] = GEN_INT ( INTVAL ( operands [ <NUM_LIT> ] ) >> unroll ) ; output_asm_insn ( <STR_LIT> , operands ) ; } else { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; if ( TARGET_40_PLUS && INTVAL ( operands [ <NUM_LIT> ] ) > <NUM_LIT> ) { unroll = <NUM_LIT> ; output_asm_insn ( <STR_LIT> , operands ) ; } else { unroll = <NUM_LIT> ; output_asm_insn ( <STR_LIT> , operands ) ; } sprintf ( buf , <STR_LIT> , count + <NUM_LIT> ) ; output_asm_insn ( buf , NULL ) ; } sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , NULL ) ; switch ( unroll ) { case <NUM_LIT> : output_asm_insn ( <STR_LIT> , operands ) ; break ; case <NUM_LIT> : output_asm_insn ( <STR_LIT> , operands ) ; break ; case <NUM_LIT> : output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; default : output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; } if ( TARGET_40_PLUS ) { sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , NULL ) ; } count ++ ; if ( lastbyte ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( ! CONSTANT_P ( operands


<s> raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable (


<s> bool <ISA_LIT>CombinerHelperState :: matchSBCEqual ( MachineInstr & MI , MachineRegisterInfo & MRI ) const { assert ( MI . getOpcode ( ) == <STR_LIT> ) ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CarryIn = MI . getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>InstrInfo :: isEarlySourceInstr ( const MachineInstr * MI ) const { if ( ! MI ) return false ; if ( MI -> mayLoad ( ) || MI -> mayStore ( ) || MI -> isCompare ( )


<s> if ( ! sh_fsca_df2int_rtx ) { REAL_VALUE_TYPE rv ; real_from_string ( & rv , <STR_LIT> ) ; sh_fsca_df2int_rtx = const_double_from_real_value ( rv , DFmode ) ; } return


<s> bool ShortInstrPeephole :: updateNOP ( MachineInstr & MI ) const { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const auto & Imm = MI . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> . contains ( SrcReg ) && Imm . isImm ( ) &&


<s> if ( startswith ( name , lower_prefix ) ) name += strlen ( lower_prefix ) ; else if ( startswith ( name , upper_prefix ) ) name += strlen ( upper_prefix ) ; else if ( startswith ( name , either_prefix ) )


<s> SmallString < <NUM_LIT> > FullFS ( <STR_LIT> ) ; if ( isAmdHsaOS ( ) ) FullFS += <STR_LIT> ; FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) != StringRef :: npos ) { if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos )


<s> unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( MO1 . getReg ( ) ) ; unsigned Rm = CTX . getRegisterInfo ( ) . getEncodingValue


<s> return ( GET_MODE_SIZE ( mode ) . to_constant ( ) / UNITS_PER_VREG )


<s> Register <ISA_LIT>TargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { if ( isFuncletEHPersonality ( classifyEHPersonality ( PersonalityFn ) ) ) return <STR_LIT> ; return Subtarget . isTarget64BitLP64 ( ) ?


<s> if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && SYMBOL_REF_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> )

) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return true ;


<s> static std :: string ustr [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const MachineInstr * MI = SU -> getInstr


<s> bool isValidHwregOffset ( int64_t Offset ) { return <NUM_LIT> <= Offset && isUInt < OFFSET_WIDTH_ > (


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( Base ) . addImm ( <NUM_LIT> ) .


<s> gimple * gimple_folder :: fold_to_pfalse ( ) { return gimple_build_assign ( lhs , build_zero_cst (


<s> unsigned IdxW = <NUM_LIT> ; auto Lo32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; auto Hi32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; SDValue W0 = isUndef ( PredV ) ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PredV ) ; Words [ IdxW ] . push_back ( Hi32 ( W0 ) ) ; Words [ IdxW ] . push_back ( Lo32 ( W0 ) ) ; while ( Bytes < BitBytes ) { IdxW ^= <NUM_LIT> ; Words [ IdxW ] . clear ( ) ; if ( Bytes < <NUM_LIT> ) { for ( const SDValue & W : Words [ IdxW ^ <NUM_LIT> ] ) { SDValue T = expandPredicate ( W , dl , DAG ) ; Words [ IdxW ] . push_back ( Hi32 ( T ) ) ; Words [ IdxW ] . push_back ( Lo32 ( T ) ) ; } } else { for ( const SDValue & W : Words [


<s> unsigned Size = Constraint . size ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 'v' && Constraint [ Size - <NUM_LIT> ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ <NUM_LIT> ] , & Constraint [ Size - <NUM_LIT> ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= <NUM_LIT> && RegNo <= <NUM_LIT> ) { Res . first = <STR_LIT> . getRegister ( RegNo ) ; Res . second = & <STR_LIT> ; } } } return Res


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; }


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) <<


<s> for ( auto Ptr : Switches ) if ( Ptr != SwPtr && Ptr -> fitsTargetFeatures ( Features ) ) if ( Ptr -> Value == SwPtr -> Value && meetsDependencies ( SwSet , Ptr , Switches ) ) { DISASM_DEBUG ( dbgs ( ) << <STR_LIT> << SwPtr -> Name << <STR_LIT> << Ptr -> Name << '\n' ) ; return


<s> emit_insn ( gen_movhi ( scratch_hi , outval ) ) ; outval = scratch_hi ; } } emit_set_insn ( base_plus , base ) ; base = base_plus ; } else if ( GET_CODE ( base ) == PLUS ) { HOST_WIDE_INT hi , lo ; offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; base = XEXP ( base , <NUM_LIT> ) ; lo = ( offset >= <NUM_LIT> ? ( offset & <NUM_LIT> ) : - ( ( - offset ) & <NUM_LIT> ) ) ; if ( lo == <NUM_LIT> ) lo &= <NUM_LIT> ; hi = ( ( ( ( offset - lo ) & ( HOST_WIDE_INT ) <NUM_LIT> ) ^ ( HOST_WIDE_INT ) <NUM_LIT> ) - ( HOST_WIDE_INT ) <NUM_LIT> ) ; gcc_assert ( hi + lo == offset ) ; if ( hi != <NUM_LIT> ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; if ( reg_overlap_mentioned_p ( base_plus , outval ) ) { if ( ! reg_overlap_mentioned_p ( scratch , outval ) ) std :: swap ( scratch , base_plus ) ; else { rtx scratch_hi = gen_rtx_REG ( HImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movhi ( scratch_hi , outval ) ) ; outval = scratch_hi ; } } emit_insn ( gen_addsi3 ( base_plus , base , GEN_INT ( hi ) ) ) ; base = base_plus ; offset = lo ; } } if ( BYTES_BIG_ENDIAN ) { emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , base , offset + <NUM_LIT> ) ) , gen_lowpart ( QImode , outval ) ) ) ; emit_insn ( gen_lshrsi3 ( scratch , gen_rtx_SUBREG ( SImode , outval , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , base , offset ) ) , gen_lowpart ( QImode , scratch ) ) ) ; } else { emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , base , offset ) ) , gen_lowpart ( QImode , outval ) ) ) ; emit_insn ( gen_lshrsi3 ( scratch , gen_rtx_SUBREG ( SImode , outval , <NUM_LIT> ) , GEN_INT


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU


<s> Optional < uint64_t > OffsetVal = getConstantZext32Val ( Root . getReg ( ) , * MRI ) ; if ( ! OffsetVal ) return { } ; Optional < int64_t > EncodedImm = <STR_LIT> ( STI ,


<s> bool isGR128 ( ) const { return isReg ( GR128Reg


<s> rtx op0 = frv_read_argument ( & arglist ) ; op0 = frv_int_to_acc ( icode , <NUM_LIT> , op0 ) ; if ( ! op0 ) return NULL_RTX ; pat = GEN_FCN ( icode ) ( op0 ) ; if ( pat ) emit_insn ( pat


<s> SDValue CCReg ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; assert ( Bytes > <NUM_LIT> && <STR_LIT> ) ; CCReg = emitMemMemImm ( DAG , DL , <STR_LIT> , Chain , Src2 ,


<s> return hasSSE1 ( ) || ( hasPRFCHW ( ) && ! has3DNow ( ) ) ||


<s> return ( hard_regno_mode_classes [ regno ] & sparc_mode_class [ mode ] )


<s> if ( skipFunction ( * F . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return


<s> unsigned Kind = ( unsigned ) Fixup . getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_CALL


<s> static bool isZeroMask ( const ArrayRef < int > & Mask ) { for ( unsigned I = <NUM_LIT> ; I < Mask . size ( ) ; ++ I ) if ( Mask [ I ] != <NUM_LIT> ) return false ; return true


<s> TargetTransformInfo DirectXTargetMachine :: getTargetTransformInfo ( const Function & F


<s> ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex (


<s> ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask


<s> unsigned getSGPRAllocGranule ( ) const { return <NUM_LIT>


<s> if ( ST -> isMClass ( ) && ST -> isThumb2 ( ) && L -> getNumBlocks ( ) == <NUM_LIT> ) return TTI :: AMK_PreIndexed ; return TTI


<s> void <ISA_LIT>PassConfig :: addAddressSpaceInferencePasses ( ) { addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( )


<s> return VT == <STR_LIT> || VT == <STR_LIT> || ( Subtarget -> has16BitInsts ( ) && VT ==

<STR_LIT> ) || ( Subtarget -> hasVOP3PInsts ( ) && VT == <STR_LIT> ) ;


<s> MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } const MCSymbolRefExpr * SRE = MCSymbolRefExpr :: create ( Parser . getTok ( ) . getIdentifier ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ , getContext ( ) ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return


<s> static bool mustPreserveGV ( const GlobalValue & GV ) { if ( const Function * F = dyn_cast < Function > ( & GV ) ) return F -> isDeclaration ( ) || F -> getName ( ) . startswith ( <STR_LIT> ) || F -> getName ( ) . startswith ( <STR_LIT> ) || <STR_LIT> ( F -> getCallingConv ( ) ) ; GV . removeDeadConstantUsers (


<s> if ( Op . isReg ( ) ) addRegUnits ( TRI , Set , Op . getReg


<s> LLT lltTy ; boolTy = GR -> getOrCreate<ISA_LIT>BoolType ( MIRBuilder ) ; if ( resType -> getOpcode ( ) == <STR_LIT> ) { unsigned vecElts = resType -> getOperand ( <NUM_LIT> ) . getImm ( ) ; boolTy = GR -> getOrCreate<ISA_LIT>VectorType ( boolTy , vecElts , MIRBuilder ) ; auto LLVMVecTy = cast < FixedVectorType > ( GR -> getTypeFor<ISA_LIT>Type ( boolTy ) ) ; lltTy = LLT :: vector ( LLVMVecTy -> getElementCount ( ) , <NUM_LIT> ) ; }


<s> } } if ( Stage == UnclusteredReschedule ) SavedMutations . swap ( Mutations ) ; for ( auto Region : Regions ) { if ( Stage == UnclusteredReschedule && ! RescheduleRegions [ RegionIdx ] ) { ++ RegionIdx ; continue ; } RegionBegin = Region . first ; RegionEnd = Region . second ; if ( RegionBegin -> getParent ( ) != MBB ) { if ( MBB ) finishBlock ( ) ; MBB = RegionBegin -> getParent ( ) ; startBlock ( MBB ) ; if ( Stage == InitialSchedule ) computeBlockPressure ( MBB ) ; } unsigned NumRegionInstrs = std :: distance ( begin ( ) , end ( ) ) ; enterRegion ( MBB , begin ( ) , end ( ) , NumRegionInstrs ) ; if ( begin ( ) == end ( ) || begin ( ) == std :: prev ( end ( ) ) ) { exitRegion ( ) ; continue ; } LLVM_DEBUG ( dbgs ( )


<s> int RegNo = matchRegisterName ( RegisterName ) ; if ( RegNo == <NUM_LIT> ) return true ; Operands . push_back ( <STR_LIT> ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex (


<s> void <ISA_LIT>64GOT :: reserveHeader ( ) { createEntry ( <NUM_LIT> , m_SectionData


<s> pat = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , pat ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ; pat = gen_rtx_SET ( VOIDmode , baseptr_rtx


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) return <STR_LIT> ; return <STR_LIT>


<s> if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { if ( RVFI -> getUsedSSR ( ) & ( <NUM_LIT> << n ) ) markSuperRegs ( Reserved , <STR_LIT> + n ) ; } assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return


<s> Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( getBaseRegister ( ) ) ; return


<s> case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned AddrOpIdx = isUpdating ? <NUM_LIT> : <NUM_LIT> ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; std :: vector < EVT > ResTys ; bool is64BitVector = VT . is64BitVector ( ) ; if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( VT ) ; else if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT>


<s> SDValue Chain = MGT -> getChain ( ) ; SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Mask = MGT -> getMask ( ) ; SDValue BasePtr = MGT -> getBasePtr ( ) ; <STR_LIT> ExtTy = MGT -> getExtensionType ( ) ; <STR_LIT> IndexType = MGT -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IdxNeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; bool ResNeedsSignExtend = ExtTy == <STR_LIT> || ExtTy == <STR_LIT> ; EVT VT = PassThru . getSimpleValueType ( ) ; EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { EVT PassThruVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; PassThru = getSVESafeBitCast ( PassThruVT , PassThru , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( PassThru

. getSimpleValueType ( ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; printMemRegReg ( MI ,


<s> virtual bool isCondCode ( ) const { return Kind ==


<s> rtx regs [ <NUM_LIT> ] ; i = <NUM_LIT> ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= <NUM_LIT> ) { rtx mem = gen_frame_mem ( BLKmode , regs


<s> } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr && PI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Offset = PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT>


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) ByteOffset = true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) HalfWordOffset = true ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; if ( ByteOffset ) O << MAI -> getData8bitsDirective ( ) ; else if ( HalfWordOffset ) O << MAI -> getData16bitsDirective ( ) ; if ( ByteOffset || HalfWordOffset ) O << '(' << * MBB -> getSymbol ( OutContext ) << <STR_LIT> << * JTISymbol << <STR_LIT> ; else O << <STR_LIT> << *


<s> MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( * SymbolName ) ; int64_t NewMax = DwordRegIndex + divideCeil ( RegWidth , <NUM_LIT> ) - <NUM_LIT> ; int64_t OldCount ; if ( ! Sym -> isVariable ( ) ) return ! Error ( getLoc ( ) ,


<s> break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <NUM_LIT> : break ; } unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; const MCOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ++ ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp + <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) if ( Match [ I ] == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ I ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRange , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( OriginalError == Match_MnemonicFail ) return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; if ( OriginalError == Match_Unsupported ) return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; assert ( OriginalError == Match_InvalidOperand && <STR_LIT> ) ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; <ISA_LIT>Operand & Operand = ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ; if ( Operand . getStartLoc ( ) . isValid ( ) ) { SMRange OperandRange = Operand . getLocRange ( ) ; return Error ( Operand . getStartLoc ( ) , <STR_LIT> , OperandRange , MatchingInlineAsm ) ; } } return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) ,

std :: end ( Match ) , Match_Unsupported ) == <NUM_LIT> ) {


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveR19R20X ( int


<s> bool <ISA_LIT>AddMissingPrototypes :: runOnModule ( Module & M ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; std :: vector < std :: pair < Function * , Function * >> Replacements ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) || ! F . hasFnAttribute ( <STR_LIT> ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; if ( ! F . isVarArg ( ) ) report_fatal_error ( <STR_LIT> + F . getName ( ) ) ; if ( F . getFunctionType ( ) -> getNumParams ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> + F . getName ( ) ) ; FunctionType * NewType = nullptr ; Function * NewF = nullptr ; for ( Use & U : F . uses ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; if ( auto * BC = dyn_cast < BitCastOperator > ( U . getUser ( ) ) ) { if ( auto * DestType = dyn_cast < FunctionType > ( BC -> getDestTy ( ) -> getPointerElementType ( ) ) ) { if ( ! NewType ) { NewType = DestType ; NewF = Function :: Create ( NewType , F . getLinkage ( ) , F . getName ( ) + <STR_LIT> ) ; NewF -> setAttributes ( F . getAttributes ( ) ) ; NewF -> removeFnAttr ( <STR_LIT> ) ; Replacements . emplace_back ( & F , NewF ) ; } else { if ( NewType != DestType ) { report_fatal_error ( <STR_LIT> <STR_LIT> + F . getName ( ) ) ; } } } } } if ( ! NewType ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> + F . getName ( ) + <STR_LIT> ) ; continue ; } } for ( auto & Pair : Replacements ) { Function * OldF = Pair


<s> static int nvptx_simt_vf ( ) { return


<s> void <ISA_LIT>InstPrinter :: printLogicalImm32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; O <<


<s> SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; if ( CondCode2 != <STR_LIT> ) { SDValue <ISA_LIT>cc2 = DAG . getConstant ( CondCode2 , dl , <STR_LIT> ) ; SDValue Cmp2 = getVFPCmp ( LHS , RHS , DAG , dl ) ; Result = getCMOV ( dl , VT , Result , TrueVal , <ISA_LIT>cc2 ,


<s> Muls . push_back ( make_unique < BinOpChain > (


<s> bool <ISA_LIT>PacketizerList :: canReserveResourcesForConstExt ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; assert ( ( QII -> isExtended ( MI ) || QII -> isConstExtended ( MI ) ) &&


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { if ( Size >= <NUM_LIT> && DstAlign >= <NUM_LIT> ) return


<s> if ( ! inScope ) { for ( auto subscope : Priv -> Subscopes ) { auto inSubscope = subscope ->


<s> if ( ! riscv_vector_chunks . is_constant ( ) && riscv_v_ext_vector_mode_p ( mode ) ) return BYTES_PER_RISCV_VECTOR ; return


<s> } else if ( LocVT == <STR_LIT> ) { unsigned Req = HST . useHVX128BOps ( ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if ( LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return


<s> bool iss4_2Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false


<s> MCInstLowering = make_unique < <ISA_LIT>MCInstLower > ( MF , * this ) ; AsmPrinter :: runOnMachineFunction (


<s> bool <ISA_LIT>BranchRelaxation :: runOnMachineFunction ( MachineFunction & MF ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST .


<s> Offset0 = Load0Offset -> getZExtValue ( ) ; Offset1 = Load1Offset -> getZExtValue ( ) ; return true ; } if ( ( isMUBUF ( Opc0 ) || isMTBUF ( Opc0 ) ) && ( isMUBUF ( Opc1 ) || isMTBUF ( Opc1 ) ) ) { if ( ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: soffset ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: vaddr ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: srsrc ) ) return false ; int OffIdx0 = <STR_LIT> ( Opc0 , <STR_LIT> :: offset ) ; int OffIdx1 = <STR_LIT> ( Opc1 , <STR_LIT> :: offset ) ; if ( OffIdx0 == - <NUM_LIT> || OffIdx1 == - <NUM_LIT> ) return false ; OffIdx0 -= get ( Opc0 ) . NumDefs ; OffIdx1 -= get ( Opc1 ) . NumDefs ; SDValue Off0 = Load0 -> getOperand ( OffIdx0 ) ; SDValue Off1 = Load1 -> getOperand ( OffIdx1 ) ; if ( ! isa < ConstantSDNode > ( Off0 ) || ! isa < ConstantSDNode > ( Off1 ) ) return false ; Offset0 = cast < ConstantSDNode > ( Off0 ) -> getZExtValue ( ) ; Offset1 = cast < ConstantSDNode > ( Off1 ) -> getZExtValue ( ) ; return true ; } return false


<s> bool invalidate ( Function & , const PreservedAnalyses & ) { return false


<s> for ( iterator I = MRI . livein_begin ( ) , E = MRI


<s> MachineOperand VdSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; Register SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand (


<s> inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI , int Offset = <NUM_LIT> ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned Flags =


<s> break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; return ( n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg1 ) || n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg2


<s> void <ISA_LIT>_CCState :: HandleByVal ( unsigned ValNo , EVT ValVT , EVT LocVT , CCValAssign :: LocInfo LocInfo , int MinSize , int MinAlign , <STR_LIT> ArgFlags ) { unsigned Align = ArgFlags . getByValAlign


<s> bool Warning ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Warning ( L , Msg


<s> return true ; case MEM : { int num_words = ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ? <NUM_LIT> : <NUM_LIT> ; if ( memory_address_p ( mode , XEXP ( ( x ) , <NUM_LIT> ) ) ) * total = COSTS_N_INSNS ( num_words ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> * num_words ) ; return true ; } case FFS : case CTZ : * total = COSTS_N_INSNS ( TARGET_NSA ? <NUM_LIT> : <NUM_LIT> ) ; return true ; case CLZ : case CLRSB : * total = COSTS_N_INSNS ( TARGET_NSA ? <NUM_LIT> : <NUM_LIT> ) ; return true ; case BSWAP : * total = COSTS_N_INSNS ( mode == HImode ? <NUM_LIT> : <NUM_LIT> ) ; return true ; case NOT : * total = COSTS_N_INSNS ( mode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; return true ; case AND : case IOR : case XOR : if ( mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case ABS : case NEG : { if ( mode == SFmode ) * total = COSTS_N_INSNS ( TARGET_HARD_FLOAT ? <NUM_LIT> : <NUM_LIT> ) ; else if ( mode == DFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case PLUS : case MINUS : { if ( mode == SFmode ) * total = COSTS_N_INSNS ( TARGET_HARD_FLOAT ? <NUM_LIT> : <NUM_LIT> ) ; else if ( mode == DFmode || mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case MULT : { if ( mode == SFmode ) * total = COSTS_N_INSNS ( TARGET_HARD_FLOAT ? <NUM_LIT> : <NUM_LIT> ) ; else if ( mode == DFmode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( mode == DImode ) * total = COSTS_N_INSNS ( TARGET_MUL32_HIGH ? <NUM_LIT> : <NUM_LIT> ) ; else if ( TARGET_MUL32 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( TARGET_MAC16 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( TARGET_MUL16 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case DIV : case MOD : { if ( mode == SFmode ) { * total = COSTS_N_INSNS ( TARGET_HARD_FLOAT_DIV ? <NUM_LIT> : <NUM_LIT> ) ; return true ; } else if ( mode


<s> bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI )

Changed |= runOnMachineBasicBlock ( * FI ) ;


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc =


<s> State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : State = IES_LT ; IC . pushOperator ( IC_LT )


<s> if ( newElfFlags & llvm :: ELF :: EF_MIPS_PIC ) newElfFlags |= llvm :: ELF :: EF_MIPS_CPIC ; if ( newElfFlags & llvm :: ELF :: EF_MIPS_ARCH_ASE_M16 ) { error ( diag :: error_<ISA_LIT>_m16_unsupported ) << pInput . name ( ) ; return false ; } if ( ! oldElfFlags ) { oldElfFlags = newElfFlags ; return true ; } uint64_t newPic = newElfFlags & ( llvm :: ELF :: EF_MIPS_PIC | llvm :: ELF :: EF_MIPS_CPIC ) ; uint64_t oldPic = oldElfFlags & ( llvm :: ELF :: EF_MIPS_PIC | llvm :: ELF :: EF_MIPS_CPIC ) ; if ( ( newPic != <NUM_LIT> ) != ( oldPic != <NUM_LIT> ) ) warning ( diag :: warn_<ISA_LIT>_abicalls_linking ) << pInput . name ( ) ; if ( ! ( newPic & llvm :: ELF :: EF_MIPS_PIC ) ) oldElfFlags &= ~ llvm :: ELF :: EF_MIPS_PIC ; if ( newPic ) oldElfFlags |= llvm :: ELF :: EF_MIPS_CPIC ; uint64_t newArch = newElfFlags & llvm :: ELF :: EF_MIPS_ARCH ; uint64_t oldArch = oldElfFlags & llvm :: ELF :: EF_MIPS_ARCH ; if ( ! isIsaMatched ( newArch , oldArch )


<s> static void mmix_reorg ( void ) { int regno ; for ( regno = MMIX_LAST_STACK_REGISTER_REGNUM ; regno >= <NUM_LIT> ; regno -- ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( regno == MMIX_FRAME_POINTER_REGNUM &&


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) .

addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> struct s390_frame frame ; s390_frame_info ( & frame ) ; return frame .


<s> for ( insn = get_insns ( ) ; insn ; insn = next_insn ( insn ) ) if ( GET_CODE ( insn ) == CALL_INSN || ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE &&

GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) == CALL_INSN ) ) return <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back ( MIB


<s> MAI -> addInitialFrameState ( Inst ) ; Inst = MCCFIInstruction :: createOffset ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , StackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; return


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { if ( RegSet . count ( Reg ) ) return true ; for ( const uint16_t * Alias = TM . getRegisterInfo ( ) -> getAliasSet (


<s> bool isSmallModel ( ) const { return !


<s> static const uint16_t CalleeSavedRegs [ ] = { <NUM_LIT> } ; return CalleeSavedRegs


<s> bool <ISA_LIT>TargetLowering :: ShouldShrinkFPConstant ( EVT VT ) const { return ! Subtarget . hasSSE2 ( )


<s> } bool CanTailCallOpt = false ; if ( Info . IsMustTailCall && ! CanTailCallOpt ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info . CallConv , TLI ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . addDef ( TRI -> getReturnAddressReg ( MF ) ) ; if ( ! addCallTargetOperands ( MIB , MIRBuilder , Info ) ) return false ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , Info . CallConv ) ; MIB . addRegMask ( Mask ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( Info . CallConv , Info . IsVarArg , MF , ArgLocs , F . getContext ( ) ) ; SmallVector < std :: pair < MCRegister , Register > , <NUM_LIT> > ImplicitArgRegs ; if ( <ISA_LIT>TargetMachine :: EnableFixedFunctionABI ) { if ( ! passSpecialInputs ( MIRBuilder , CCInfo , ImplicitArgRegs , Info ) ) return false ; } SmallVector < Register , <NUM_LIT> > PhysRegs ; <ISA_LIT>OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , false ) ; if ( ! handleAssignments ( CCInfo , ArgLocs , MIRBuilder , OutArgs , Handler ) ) return false ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! ST . enableFlatScratch ( ) ) { auto ScratchRSrcReg = MIRBuilder . buildCopy ( LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) , MFI -> getScratchRSrcReg ( ) ) ; MIRBuilder . buildCopy ( <STR_LIT> , ScratchRSrcReg ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; } for ( std :: pair < MCRegister , Register > ArgReg : ImplicitArgRegs ) { MIRBuilder . buildCopy ( ( Register ) ArgReg . first , ArgReg . second ) ; MIB . addReg ( ArgReg . first , RegState :: Implicit ) ; } unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( MIB -> getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg ,

bool isKill , int FrameIndex , const TargetRegisterClass * RC ) const {


<s> uint64_t MaxIndex = <NUM_LIT> ; uint64_t RetElSize = RetVT . getVectorElementType ( ) . getSimpleVT ( ) . getStoreSize ( ) . getKnownMinSize ( ) ; ConstantSDNode * OffsetConst = dyn_cast < ConstantSDNode > ( Offset . getNode ( ) ) ; if ( nullptr == OffsetConst || OffsetConst -> getZExtValue ( ) > MaxIndex * RetElSize || OffsetConst -> getZExtValue ( ) % RetElSize ) { if ( <STR_LIT> == Base . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; EVT HwRetVt = getSVEContainerType ( RetVT ) ; SDValue OutVT = DAG . getValueType ( RetVT ) ; if ( RetVT . isFloatingPoint ( ) ) OutVT = DAG . getValueType ( HwRetVt ) ; SDVTList VTs = DAG . getVTList ( HwRetVt , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Base , Offset , OutVT } ; SDValue Load = DAG . getNode ( Opcode , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( RetVT . isInteger ( ) && ( RetVT != HwRetVt ) ) Load = DAG . getNode

( <STR_LIT> , DL , RetVT , Load . getValue ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>ALFWriter :: initFrames ( ) { b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) , false ) ; b -> addInit ( <STR_LIT> , <NUM_LIT> , b -> dec_unsigned (


<s> switch ( Opcode ) { default : return DAG . getNode ( Opcode , dl , VT , Ops ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } SmallVector < SDValue , <NUM_LIT> > NewOps = { DAG


<s> return new ( Ctx ) <ISA_LIT>MCExpr (


<s> <ISA_LIT>CommonGEP ( ) : FunctionPass ( ID ) { initialize<ISA_LIT>CommonGEPPass ( * PassRegistry :: getPassRegistry ( )


<s> static unsigned getSPReg ( ) { return <STR_LIT>


<s> if ( loadImmediate ( ImmOp64 , FirstReg , <STR_LIT> , false , false , IDLoc , Out , STI ) ) return true ; } else { if ( loadImmediate ( Hi_32 ( ImmOp64 ) , FirstReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; if ( loadImmediate ( <NUM_LIT> , nextReg ( FirstReg ) , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; } return false ; } MCSection * CS = getStreamer ( ) . getCurrentSectionOnly ( ) ; MCSection * ReadOnlySection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; MCSymbol * Sym = getContext ( ) . createTempSymbol ( ) ; const MCExpr * LoSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , LoSym , getContext ( ) ) ; getStreamer ( ) . SwitchSection ( ReadOnlySection ) ; getStreamer ( ) . EmitLabel ( Sym , IDLoc ) ; getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ; getStreamer ( ) . EmitIntValue ( ImmOp64


<s> return reinterpret_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget (


<s> static void LowerMemOpCallTo ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue Arg , SDValue PtrOff , int SPDiff , unsigned ArgOffset , bool is<ISA_LIT>64 , bool isTailCall , bool isVector , SmallVector < SDValue , <NUM_LIT> > & MemOpChains , SmallVector < TailCallArgumentInfo , <NUM_LIT> > & TailCallArguments , DebugLoc dl ) { MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; if ( ! isTailCall


<s> const MCExpr * Expr ; Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; return MCOperand :: CreateExpr


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> )


<s> const <ISA_LIT>InstrInfo & TII = * MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL ; unsigned MoveReg = <STR_LIT> ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , MoveReg ) , CSI [ CSIIndex ] . getFrameIdx ( ) ) ) ; unsigned RestoreOp = <STR_LIT> ; if ( CR2Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg (

MoveReg , getKillRegState ( ! CR3Spilled && ! CR4Spilled ) ) ) ;


<s> addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return


<s> if ( ! isImm ( ) ) return false ; if ( dyn_cast < MCSymbolRefExpr > ( Imm . Val ) ) return true ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Val = CE -> getValue ( ) ; int64_t Align = <NUM_LIT> << scale ; int64_t Max = Align * ( ( <NUM_LIT> << width


<s> const enum processor_type processor ; const enum processor_flags flags ; } const processor_alias_table [ ] = { { <STR_LIT> , PROCESSOR_9672_G5 , PF_IEEE_FLOAT } , { <STR_LIT> , PROCESSOR_9672_G6 , PF_IEEE_FLOAT } , { <STR_LIT> , PROCESSOR_2064_Z900 , PF_IEEE_FLOAT | PF_ZARCH } , { <STR_LIT> , PROCESSOR_2084_Z990 , PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT } , { <STR_LIT> , PROCESSOR_2094_Z9_109 , PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT | PF_EXTIMM } , } ; size_t i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( processor_alias_table ) ; i ++ ) if ( strcmp ( arg , processor_alias_table [ i ] . name ) == <NUM_LIT> ) { * type = processor_alias_table [ i ] . processor ; * flags = processor_alias_table [ i ] .


<s> YamlIO . mapOptional ( <STR_LIT> , MFI . MaxKernArgAlign , <NUM_LIT> ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . LDSSize , <NUM_LIT> ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . IsEntryFunction , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . NoSignedZerosFPMath , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . MemoryBound , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . WaveLimiter , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchRSrcReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchWaveOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . FrameOffsetReg , StringValue (


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelPLT ( ) const { assert ( m_pRelPlt !=


<s> if ( CbId == - <NUM_LIT> ) return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || N

-> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT ;


<s> case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: FAdd : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: FSub : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: FMul : return SelectBinaryFPOp ( I , <STR_LIT> ) ; case Instruction :: SDiv : return SelectDiv ( I , true ) ; case Instruction :: UDiv : return SelectDiv ( I , false ) ; case Instruction :: SRem : return SelectRem ( I , true ) ; case Instruction :: URem : return SelectRem ( I , false ) ; case Instruction :: Call : if ( const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) return SelectIntrinsicCall ( * II ) ; return SelectCall ( I ) ; case Instruction :: Select : return SelectSelect ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction ::


<s> assert ( LLVMTy ) ; Register Res ; UndefValue * UV = UndefValue :: get ( const_cast < Type * > ( LLVMTy ) ) ; if ( DT . find ( UV , CurMF , Res ) ) return Res ; LLT LLTy = LLT :: scalar ( <NUM_LIT> ) ; Res = CurMF -> getRegInfo ( ) . createGenericVirtualRegister ( LLTy ) ; assign<ISA_LIT>TypeToVReg ( SpvType , Res , * CurMF ) ; DT . add ( UV , CurMF , Res ) ; MachineInstrBuilder MIB


<s> bool <ISA_LIT>PassConfig :: addPreISel


<s> static __inline qword si_ahi ( qword a , short b ) { return ( ( qword ) ( vec_add ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8

) ( si_from_short ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> return ( int16x4_t ) __builtin_aarch64_sqabsv4hi (


<s> bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ; SDValue Res ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ; if ( N1C ) { unsigned Val = N1C -> getZExtValue ( ) ; if ( ( Val & ~ Mask ) != Val ) return SDValue ( ) ; if ( <STR_LIT> ( Mask ) ) { Val >>= countTrailingZeros ( ~ Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Val , DL , <STR_LIT>

) , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ;


<s> if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ; ++ SI ) { for ( BasicBlock :: const_iterator II = SI -> begin ( ) ; ( PN = dyn_cast < PHINode > ( II ) ) ; ++ II ) { if ( PN -> getType ( ) == Type :: get<ISA_LIT>_FP80Ty ( LLVMBB -> getContext ( ) ) || ( ! Subtarget . hasSSE1 ( ) && PN -> getType ( ) -> isFloatingPointTy ( ) ) || ( ! Subtarget . hasSSE2 ( ) && PN -> getType ( ) == Type :: getDoubleTy ( LLVMBB -> getContext ( ) ) ) ) { ContainsFPCode =


<s> case TargetTransformInfo :: CacheLevel :: L1D : LLVM_FALLTHROUGH ; case TargetTransformInfo :: CacheLevel :: L2D : return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load0 , SDNode * Load1 , int64_t Offset0 , int64_t Offset1 , unsigned NumLoads ) const { assert ( Offset1 > Offset0 && <STR_LIT> ) ; return ( NumLoads <= <NUM_LIT> && ( Offset1 - Offset0 )


<s> if ( left ) return aarch64_const_vec_all_same_in_range_p ( x , <NUM_LIT> , bit_width - <NUM_LIT> ) ; else return aarch64_const_vec_all_same_in_range_p ( x ,


<s> align *= <NUM_LIT> * size ; } } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; else if ( Rm


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( TRI -> hasBasePointer ( MF ) ) FrameReg = TRI -> getBaseRegister ( ) ; else if ( TRI -> needsStackRealignment ( MF ) ) FrameReg = TRI -> getStackRegister ( ) ; else FrameReg = TRI -> getFrameRegister ( MF ) ; int Offset = MFI -> getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; bool HasFP = hasFP ( MF ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int64_t FPDelta = <NUM_LIT> ; if ( IsWin64Prologue ) { assert ( ! MFI -> hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return - SEHFrameOffset ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI -> hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! HasFP ) return Offset +


<s> if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( V2IsSplat ) { if ( isUndefOrEqual ( BitI1 , NumElts ) )


<s> bool isCoprocOption ( ) const { return Kind ==


<s> auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg && TheReg -> isInRequiredFeatures ( { <STR_LIT> } ) ) { O << TheReg -> Name ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } } auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } O << SYSm ; return ; } unsigned SpecRegRBit = Op . getImm ( ) >> <NUM_LIT> ; unsigned Mask = Op . getImm ( ) & <NUM_LIT> ; if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : llvm_unreachable ( <STR_LIT>


<s> Value * RetVal = Ret -> getReturnValue ( ) ; assert ( RetVal && <STR_LIT> ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { RetVal -> getType (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned getAlignmentForImplicitArgPtr ( ) const


<s> else ret = <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST


<s> if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( VMask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget


<s> for ( unsigned i = <NUM_LIT> , Dmask = OldDmask ; i <= Lane ; i ++ ) { assert ( Dmask ) ; Comp = countTrailingZeros ( Dmask ) ; Dmask &= ~ ( <NUM_LIT> << Comp ) ; } if ( Users [ Lane ] ) return ; Users [ Lane ] = * I ; NewDmask |= <NUM_LIT> << Comp ; } if ( NewDmask == OldDmask ) return ; std :: vector < SDValue > Ops ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) , Node -> op_begin ( ) + DmaskIdx ) ; Ops . push_back ( DAG . getTargetConstant ( NewDmask , SDLoc ( Node ) , <STR_LIT> ) ) ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) + DmaskIdx + <NUM_LIT> , Node -> op_end ( ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops ) ; if ( NewDmask && ( NewDmask & ( NewDmask - <NUM_LIT> ) ) == <NUM_LIT> ) { SDValue RC = DAG . getTargetConstant ( <STR_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = <STR_LIT> ; i < <NUM_LIT> ; ++ i ) { SDNode * User = Users


<s> } else if ( Fixup . getKind ( ) == FK_Data_4 || Fixup . getKind ( ) == FK_Data_8 ) { unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - <NUM_LIT> ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ; } } else if ( Fixup . getKind ( ) == FK_PCRel_4 ) { Value = ( uint32_t ) ( ( Value - <NUM_LIT> ) / <NUM_LIT> ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( )


<s> if ( ! DCI . isBeforeLegalize ( ) ) break ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || RHS -> getOpcode ( ) == <STR_LIT> || ( RHS -> getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . getSizeInBits ( ) <= <NUM_LIT> ) ) break ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue NewRHS = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , RHS , DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ) ) ; return DCI . CombineTo ( N , DAG . getNode ( N -> getOpcode ( ) , DL , LHS . getValueType ( ) , LHS , NewRHS ) ) ; } case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> || Src . getValueType ( ) != <STR_LIT> ) break ; if ( ! isVariableShift ( Src ) && ! ( Subtarget . hasStdExtM ( ) && isVariableSDivUDivURem ( Src ) ) ) break ; SDLoc DL ( N ) ; return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ) ; } case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> ) break ; return DCI . CombineTo ( N , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT>


<s> bool llvm :: getReqNTIDz ( const Function & F , unsigned &


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( Subtarget . isV9 ( ) ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else llvm_unreachable ( <STR_LIT>


<s> else { HOST_WIDE_INT rounded_size ; rtx r13 = LARCH_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = LARCH_PROLOGUE_TEMP2 ( Pmode ) ; rtx r14 = LARCH_PROLOGUE_TEMP3 ( Pmode ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; if ( first != <NUM_LIT> ) { emit_move_insn ( r14 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( r13 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; } else emit_move_insn ( r13 , stack_pointer_rtx ) ; emit_move_insn ( r14 , GEN_INT ( PROBE_INTERVAL ) ) ; if ( rounded_size == <NUM_LIT> ) emit_move_insn ( r12 , r13 ) ; else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , r13 , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , r13 , r13 , r12 , r14 ) ) ; } if ( size != rounded_size ) { if ( TARGET_64BIT ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; else { HOST_WIDE_INT i ; for ( i = <NUM_LIT> ; i < ( size - rounded_size ) ; i += <NUM_LIT> ) { emit_stack_probe ( plus_constant ( Pmode , r12 , - i ) ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , r12 , - <NUM_LIT> ) ) ) ; } rtx r1 = plus_constant ( Pmode , r12 , - (

size - rounded_size - i + <NUM_LIT> ) ) ;


<s> virtual std :: string getLabelEndName ( ) const { return <STR_LIT>


<s> if ( Width == <NUM_LIT> || Width > <NUM_LIT> ) break ; AttributeSet Attrs = F . getAttributes ( ) ; if ( Attrs . hasAttribute ( AttrIdx , Attribute :: ByVal ) ) continue ; InPhysReg = getNextPhysReg ( InPhysReg , Width ) ; if ( ! InPhysReg ) break ; InVirtReg = getVirtRegFor ( InPhysReg ) ; if ( ! InVirtReg ) continue ; if ( Attrs . hasAttribute ( AttrIdx , Attribute :: SExt ) ) VRX . insert ( std :: make_pair ( InVirtReg ,

ExtType ( ExtType :: SExt , Width ) ) ) ;


<s> llvm :: MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & InstrInfo , const MCRegisterInfo & , MCContext & context ) { return new <ISA_LIT>MCCodeEmitter ( InstrInfo , context


<s> RegisterTarget < Triple :: ppc64 , true > Y (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * WWM ) ; ContainsWWM = true ; break ; } } if ( ! ContainsWWM ) return false ; unsigned Reg = DefOpnd -> getReg ( ) ; for ( auto Pred : Loop -> getHeader ( ) -> predecessors ( ) ) { if ( ! Loop -> contains ( Pred ) ) { auto ImplicitDef = BuildMI ( * Pred , Pred -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , Reg ) ; LLVM_DEBUG ( dbgs ( ) << * ImplicitDef ) ; ( void ) ImplicitDef ; } } DefOpnd -> getParent ( ) -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; LLVM_DEBUG ( dbgs ( ) << * DefOpnd -> getParent ( ) ) ; return


<s> if ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( VT . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( VT ) ) { unsigned Opc = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opc ) ; } if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) ==


<s> Inst . addOperand ( MCOperand :: createImm ( Imm )


<s> assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( CI . EltSize == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; unsigned BaseReg = AddrReg -> getReg ( ) ; unsigned BaseSubReg = AddrReg -> getSubReg ( ) ; unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { unsigned ImmReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , CI . Paired , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Read2 = BuildMI ( * MBB , CI . Paired , DL , Read2Desc , DestReg ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; ( void ) Read2 ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std ::