<s> for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } <STR_LIT> Pred = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CRReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ( Pred ) ) . addReg ( CRReg ) . addImm ( <NUM_LIT> ) ; I = BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Dest ) ; OldBranch -> eraseFromParent ( ) ; BlockSizes [ MBB . getNumber ( ) ] += <NUM_LIT> ; MBBStartOffset += <NUM_LIT> ; ++ NumExpanded ; MadeChange =


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( REG_P ( * iter ) ) { unsigned int regno = REGNO ( * iter ) ; if ( ACC_P ( regno ) ) return ( regno - ACC_FIRST ) & <NUM_LIT> ? ACC_GROUP_ODD : ACC_GROUP_EVEN ; if ( ACCG_P ( regno ) ) return ( regno - ACCG_FIRST


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) ) , AM ) . addImm ( CI -> getSExtValue ( ) ) ; return


<s> return GetNonPseudoCallIndirectOpcode ( MI


<s> void printopaquemem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo


<s> bool <ISA_LIT>CodeGenPrepare :: doInitialization (


<s> return ( __m128i ) __builtin_ia32_vpopcountd_v4si_mask ( ( __v4si ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask16


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { VarArgsFrameIndex = MFI -> CreateFixedObject ( StackSlotSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; unsigned VReg = MF . addLiveIn ( ArgRegs [ ArgRegIdx ] , & <STR_LIT> ) ; SDValue ArgVal = DAG . getRegister ( VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Store . getOperand ( <NUM_LIT> ) ; MemOps . push_back ( Store ) ; ArgOffset += StackSlotSize ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps .


<s> void relaxInstruction ( const MCInst & , llvm :: MCInst & ) const { llvm_unreachable (


<s> return false ; } MCSymbol * Func = getParser ( ) . getContext ( ) . GetOrCreateSymbol ( Tok . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Func ) ; Parser . Lex ( ) ; return false ; } } if ( getLexer ( ) . isNot (


<s> void <ISA_LIT>ScheduleBlock :: tryCandidateTopDown ( <ISA_LIT>SchedCandidate & Cand , <ISA_LIT>SchedCandidate & TryCand ) { if ( ! Cand . isValid ( ) ) { TryCand . Reason = NodeOrder ; return ; } if ( Cand . SGPRUsage > <NUM_LIT> && tryLess ( TryCand . SGPRUsage , Cand . SGPRUsage , TryCand , Cand , RegUsage ) ) return ; if ( tryLess ( TryCand . HasLowLatencyNonWaitedParent , Cand . HasLowLatencyNonWaitedParent , TryCand , Cand , <STR_LIT> ) ) return ; if ( tryGreater ( TryCand . IsLowLatency , Cand . IsLowLatency , TryCand , Cand , <STR_LIT> ) ) return ; if ( TryCand . IsLowLatency && tryLess ( TryCand . LowLatencyOffset , Cand . LowLatencyOffset , TryCand , Cand , <STR_LIT> ) ) return ; if ( tryLess ( TryCand . VGPRUsage , Cand . VGPRUsage , TryCand , Cand , RegUsage ) ) return ; if ( TryCand . SU -> NodeNum < Cand .


<s> void <ISA_LIT>ATTAsmPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const char * Modifier ) { assert ( Modifier == <NUM_LIT> && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << '%' ; unsigned Reg = Op . getReg ( ) ; if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { EVT VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? EVT :: i64 : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? EVT :: i32 : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? EVT :: i16 : EVT :: i8 ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; } O << TRI -> getAsmName ( Reg ) ; return ; } else if ( Op . isImm ( ) ) { O << '$' ; O << Op . getImm ( ) ; return ; } else if ( Op . isMCValue ( ) ) { O << '$' ; Op . getMCValue ( ) . print (


<s> rtx mem = XEXP ( set , opn ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( mem ) !=


<s> SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType (


<s> ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_2 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_24 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_3 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_32 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_4 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_48 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_6 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_64 : ExpectedVal = <NUM_LIT> ; break ; case MCK__HASH_8 : ExpectedVal = <NUM_LIT> ; break ; case MCK_MPR : if ( Op . isTokenEqual ( <STR_LIT> ) ) return Match_Success ; return Match_InvalidOperand ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return


<s> if ( GET_CODE ( pat ) != SET ) return false ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , SET_SRC ( pat ) , NONCONST ) { const_rtx x = * iter ; if ( REG_P ( x ) && REGNO ( x ) != LO_REGNO && REGNO ( x ) != HI_REGNO && reg_set_p ( x , prev ) ) return false ; } return


<s> case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( Symbol && <STR_LIT> ) ; const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create


<s> Register AmtReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto * CstMI = MRI . getVRegDef ( AmtReg ) ; assert ( CstMI && <STR_LIT> ) ; if ( CstMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) return true ; unsigned Amount = CstMI -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; if ( Amount > <NUM_LIT> ) return true ; assert ( MRI . getType ( AmtReg ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ExtCst = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , AmtReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ExtCst . getReg ( <NUM_LIT> ) ) ; return


<s> <ISA_LIT>DisassemblerBase ( STI , Info


<s> auto Cmp = B . buildICmp ( CmpInst :: ICMP_EQ , CCTy , Idx , IC ) ; MRI . setRegBank ( Cmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , CCBank ) ; for ( unsigned L = <NUM_LIT> ; L < NumLanes ; ++ L ) { Register Op0 = constrainRegToBank ( MRI , B , InsRegs [ L ] , DstBank ) ; Register Op1 = UnmergeToEltTy . getReg ( I * NumLanes + L ) ; Op1 = constrainRegToBank ( MRI , B , Op1 , DstBank ) ; Register Select = B . buildSelect ( EltTy , Cmp , Op0 , Op1 ) . getReg ( <NUM_LIT> ) ; MRI . setRegBank ( Select , DstBank ) ; Ops [ I * NumLanes + L ] = Select ; } } LLT MergeTy = LLT :: vector ( Ops . size ( ) , EltTy ) ; if ( MergeTy == MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { B . buildBuildVector ( MI . getOperand ( <NUM_LIT> ) , Ops ) ; } else { auto Vec = B . buildBuildVector ( MergeTy , Ops ) ; MRI . setRegBank ( Vec -> getOperand ( <NUM_LIT> ) . getReg (


<s> Kind = <STR_LIT> ; BTFType . Info = ( ( ComponentId < <NUM_LIT> ) << <NUM_LIT> ) | ( Kind << <NUM_LIT> ) ; BTFType . Type = BaseTypeId ; Info = ComponentId < <NUM_LIT> ?


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM , this

) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> :


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue


<s> else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I ,


<s> static unsigned getNextSVEVectorRegister ( unsigned Reg ) { if ( Reg == <STR_LIT> ) return <STR_LIT> ; else return Reg


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ; return


<s> break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ; } else { for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . cloneMemRefs ( *


<s> assert ( Kind == Memory && <STR_LIT> ) ; return Mem . IndexReg >= LowR &&


<s> auto LHS = matchGREVIPat ( Op . getOperand ( <NUM_LIT> ) ) ; auto RHS = matchGREVIPat ( Op . getOperand ( <NUM_LIT> ) ) ; if ( LHS && RHS && LHS -> formsPairWith ( * RHS ) ) { SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LHS -> Op , DAG . getConstant ( LHS -> ShAmt , DL ,


<s> Value * sliceValue ( IRBuilder < > & IRB , Value * V , int64_t Offset ) { if ( Offset > <NUM_LIT> ) { V = IRB . CreateLShr ( V , Offset * <NUM_LIT> ) ; V = IRB . CreateZExtOrTrunc ( V , IRB . getInt64Ty ( )


<s> Observer . changingInstr ( MI ) ; MI . setDesc ( TII . get ( TargetOpcode :: G_GLOBAL_VALUE ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToGA ( MatchInfo . first -> getGlobal ( ) , MatchInfo . second , MatchInfo . first -> getTargetFlags ( ) ) ; MI . removeOperand ( <NUM_LIT> ) ; Observer . changedInstr (


<s> if ( ! ConstantSDNode :: classof ( node ) ) return false ; ConstantSDNode * CN = cast < ConstantSDNode > ( node ) ; imm = CurDAG -> getTargetConstant ( * CN

-> getConstantIntValue ( ) , <STR_LIT> ) ;


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT ,


<s> unsigned BasePtr ; if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else BasePtr = ( hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT> )


<s> assert ( HaveMask ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { int LaneElts = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N . getOpcode (


<s> MachineInstr * BranchMI = getNormalBlockBranchInstr ( MBB ) ; assert ( BranchMI && isCondBranch ( BranchMI ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; BranchMI -> dump ( ) ; ) ; BranchMI -> eraseFromParent ( ) ; SHOWNEWBLK ( MBB1 , <STR_LIT> ) ; MBB -> removeSuccessor ( MBB1 )


, <NUM_LIT> , ( __mmask16 ) - <NUM_LIT> ) ;


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , GPU , FullFS ) ; if ( Gen == <ISA_LIT>Subtarget :: INVALID ) { Gen = TT . getOS ( ) == Triple :: AMDHSA ? <ISA_LIT>Subtarget :: SEA_ISLANDS : <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ; } assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; assert ( hasAddr64 ( ) || hasFlat ( ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) && ! FlatForGlobal ) { ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = true ; } if ( ! hasFlat ( ) && ! FS . contains ( <STR_LIT> )


<s> return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx

+ <NUM_LIT> ) . getReg ( ) == <STR_LIT> ;


<s> return new ( Ctx ) <ISA_LIT>GenericMCSymbolRefExpr (


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq


<s> Type * FieldTys [ ] = { EHLinkRegistrationTy -> getPointerTo ( <NUM_LIT> ) , Type :: getInt8PtrTy ( Context ) } ; EHLinkRegistrationTy -> setBody ( FieldTys ,


<s> if ( dest_mode == KFmode ) kf_or_tf = <NUM_LIT> ; else if ( dest_mode == TFmode ) kf_or_tf = <NUM_LIT> ; else gcc_unreachable ( ) ; switch ( src_mode ) { case E_DFmode : cvt = sext_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_df ; break ; case E_SFmode : cvt = sext_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_sf ; break ; case E_KFmode : case E_IFmode : case E_TFmode : if ( FLOAT128_IBM_P ( src_mode ) ) cvt = sext_optab ; else do_move = true ; break ; case E_SImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_sign ; } break ; case E_DImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IEEE_P ( src_mode ) ) { if ( src_mode == KFmode ) kf_or_tf = <NUM_LIT> ; else if ( src_mode == TFmode ) kf_or_tf = <NUM_LIT> ; else gcc_unreachable ( ) ; switch ( dest_mode ) { case E_DFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_df ; break ; case E_SFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_sf ; break ; case E_KFmode : case E_IFmode : case E_TFmode : if ( FLOAT128_IBM_P ( dest_mode ) ) cvt = trunc_optab ; else do_move = true ; break ; case E_SImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_uns ; } else { cvt = sfix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_sign ; } break ; case E_DImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_di_uns ; } else { cvt = sfix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IBM_P ( dest_mode ) && FLOAT128_IBM_P ( src_mode ) ) do_move = true ; else gcc_unreachable ( ) ; if ( do_move ) emit_insn ( gen_rtx_SET ( dest , gen_rtx_FLOAT_EXTEND ( dest_mode , src ) ) ) ; else if ( TARGET_FLOAT128_HW && hw_convert ) emit_insn ( ( hw_convert ) ( dest , src ) ) ; else if ( cvt != unknown_optab ) { libfunc = convert_optab_libfunc ( cvt , dest_mode , src_mode ) ; gcc_assert ( libfunc != NULL_RTX ) ; dest2 = emit_library_call_value ( libfunc , dest , LCT_CONST , dest_mode , src , src_mode ) ; gcc_assert ( dest2


<s> if ( XLen == <NUM_LIT> ) { Incr = Builder . CreateSExt ( Incr , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; ShiftAmt = Builder . CreateSExt ( ShiftAmt , Builder . getInt64Ty ( ) ) ; } Value * Result ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Min || AI -> getOperation ( ) == AtomicRMWInst :: Max ) { const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned ValWidth = DL . getTypeStoreSizeInBits ( AI -> getValOperand ( ) -> getType ( ) ) ; Value * SextShamt = Builder . CreateSub ( Builder . getIntN ( XLen , XLen - ValWidth ) , ShiftAmt ) ; Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ; } else


<s> return ( uint16x4_t ) __builtin_neon_vceqv4hi ( __a ,


<s> static bool DisassemblePseudo ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded


<s> return ( __m128i ) __builtin_ia32_vpperm ( ( __v16qi ) __A , (


<s> bool convertSelectOfConstantsToMath ( EVT VT ) const override { return


<s> return MatchOperand_ParseFail ; } auto PRFM = LookupByEncoding ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , PRFM . getValueOr ( <STR_LIT> ) , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = LookupByName ( Tok . getString ( ) ) ; if ( ! PRFM ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( * PRFM , Tok . getString ( ) , S , getContext ( ) ) ) ; Lex (


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val


<s> unsigned Reg = DFPRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str (


<s> assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } assert ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_None ) ; SRE -> getSymbol ( ) . print ( OS ,


<s> const MCExpr * <ISA_LIT>ELFTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MachineModuleInfoELF & ELFMMI = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { MCSymbol * Sym = TM . getSymbol


<s> rtx_insn * sh_peephole_emit_move_insn ( rtx dst , rtx src ) { return sh_check_add_incdec_notes ( emit_move_insn ( dst , sh_remove_overlapping_post_inc ( dst


<s> unsigned MaxSystemSGPRs = <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ; return MaxUserSGPRs


<s> bool <ISA_LIT>TargetMachine :: getEnableTailMergeDefault ( ) const


<s> if ( associated_type ( decl ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( associated_type ( decl ) ) ) ) return i386_pe_type_dllimport_p ( decl ) ; return false


<s> unsigned <ISA_LIT>FastISel :: MaterializeInt ( const Constant * C , MVT VT ) { if ( VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; const ConstantInt * CI = cast < ConstantInt


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << Res << <STR_LIT> << - Res << '\n' ) ; return - Res ; } ) ; if ( Num == <NUM_LIT> ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Num << '\n' ) ; Num = findMax ( Num , [ = ] ( const Candidate & C ) { auto SU = C . SU ; auto Res = getReadySuccessors ( SU ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << Res << <STR_LIT> << Res << '\n' ) ; return Res ; } ) ; if ( Num == <NUM_LIT>


<s> Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; MachineFunction & MF = DAG


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> <<


<s> gcc_assert ( GET_CODE ( x ) == CONST_DOUBLE ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; switch ( mode ) { case SFmode : REAL_VALUE_TO_TARGET_SINGLE ( r , value_long [ <NUM_LIT> ] ) ; if ( HOST_BITS_PER_LONG > <NUM_LIT> ) value_long [ <NUM_LIT> ] &= <NUM_LIT> ; fprintf ( file , <STR_LIT> , value_long [ <NUM_LIT> ] ) ; break ; case DFmode : REAL_VALUE_TO_TARGET_DOUBLE ( r , value_long ) ; if ( HOST_BITS_PER_LONG > <NUM_LIT> ) { value_long [ <NUM_LIT> ] &= <NUM_LIT> ; value_long [ <NUM_LIT> ] &= <NUM_LIT> ; } fprintf ( file , <STR_LIT> , value_long [ <NUM_LIT> ] , value_long [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } break ; case MODE_INT : case MODE_PARTIAL_INT : size = GET_MODE_SIZE ( mode ) ; switch ( size ) { case <NUM_LIT> : output_addr_const ( file , x ) ; fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : split_double ( x , & first , & second ) ; output_addr_const ( file , first ) ; fputs ( <STR_LIT> , file ) ; output_addr_const ( file ,


<s> unsigned NumRegs = Regs . size ( ) ; assert ( NumRegs > <NUM_LIT> ) ; bool SafeToClobberCPSR = ! isThumb1 || ( MBB . computeRegisterLiveness ( TRI , <STR_LIT> , InsertBefore , <NUM_LIT> ) == MachineBasicBlock :: LQR_Dead ) ; bool Writeback = isThumb1 ; if ( isThumb1 && isi32Load ( Opcode ) && ContainsReg ( Regs , Base ) ) { assert ( Base != <STR_LIT> && <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { Writeback = false ; } else if ( Opcode == <STR_LIT> ) { return nullptr ; } } <STR_LIT> Mode = <STR_LIT> ; bool isNotVFP = isi32Load ( Opcode ) || isi32Store ( Opcode ) ; bool haveIBAndDA = isNotVFP && ! isThumb2 && ! isThumb1 ; if ( Offset == <NUM_LIT> && haveIBAndDA ) { Mode = <STR_LIT> ; } else if ( Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> && haveIBAndDA ) { Mode = <STR_LIT> ; } else if ( Offset == - <NUM_LIT> * ( int ) NumRegs && isNotVFP && ! isThumb1 ) { Mode = <STR_LIT> ; } else if ( Offset != <NUM_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( ! getLoadStoreMultipleOpcode ( Opcode , Mode ) ) return nullptr ; if ( NumRegs <= <NUM_LIT> ) return nullptr ; if ( ! SafeToClobberCPSR ) return nullptr ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) { NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; Writeback = false ; } else { moveLiveRegsBefore ( MBB , InsertBefore ) ; if ( ! isLoadSingle ( Opcode ) ) for ( const std :: pair < unsigned , bool > & R : Regs ) LiveRegs . addReg ( R . first ) ; NewBase = findFreeReg ( isThumb1 ? <STR_LIT> : <STR_LIT> ) ; if ( NewBase == <NUM_LIT> ) return nullptr ; } int BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Base == <STR_LIT> ) ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; BaseOpc = isThumb2 ? <STR_LIT> : ( isThumb1 && Offset < <NUM_LIT> && Base != <STR_LIT> ) ? <STR_LIT> : isThumb1 ? <STR_LIT> : <STR_LIT> ; } if ( ! TL -> isLegalAddImmediate ( Offset ) ) return nullptr ; bool KillOldBase = BaseKill && ( ! isi32Store ( Opcode ) || ! ContainsReg ( Regs , Base ) ) ; if ( isThumb1 ) { if ( Base != NewBase && ( BaseOpc == <STR_LIT> || BaseOpc == <STR_LIT> ) ) { if ( is<ISA_LIT>LowRegister ( NewBase ) && is<ISA_LIT>LowRegister ( Base ) && ! STI -> hasV6Ops ( ) ) { if ( Pred != <STR_LIT> ) return nullptr ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym ,


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) return true ; if ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return true ; return false


<s> Value * Base = computeBaseAndAccessKey ( Call , AccessKey , Kind , TypeMeta ) ; if ( ! Base ) return false ; BasicBlock * BB = Call -> getParent ( ) ; GlobalVariable * GV ; if ( GEPGlobals . find ( AccessKey ) == GEPGlobals . end ( ) ) { GV = new GlobalVariable ( M , Type :: getInt64Ty ( BB -> getContext ( ) ) , false , GlobalVariable :: ExternalLinkage , NULL , AccessKey ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , TypeMeta ) ; GEPGlobals [ AccessKey ] = GV ; } else { GV = GEPGlobals [ AccessKey ] ; } auto * LDInst = new LoadInst ( Type :: getInt64Ty ( BB -> getContext ( ) ) , GV ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , LDInst ) ; auto * BCInst = new BitCastInst ( Base , Type :: getInt8PtrTy ( BB -> getContext ( ) ) ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , BCInst ) ; auto * GEP = GetElementPtrInst :: Create ( Type :: getInt8Ty ( BB -> getContext ( ) ) , BCInst , LDInst ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , GEP ) ; auto * BCInst2 = new BitCastInst ( GEP , Call -> getType ( ) ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , BCInst2 ) ; Call -> replaceAllUsesWith (


<s> <ISA_LIT>64Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , bool


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( int I = MFI . getObjectIndexBegin ( ) , E = MFI . getObjectIndexEnd ( ) ; I != E ;


<s> if ( TARGET_Z196 && GET_CODE ( op ) == CONST_DOUBLE && s390_float_const_zero_p


<s> void <ISA_LIT>InstPrinter :: printPCRelImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand


<s> param_size = ( UNITS_PER_WORD - <NUM_LIT> + param_size ) / UNITS_PER_WORD ; if ( cum -> regs_used + param_size > NUM_ARG_REGS ) cum -> regs_used = NUM_ARG_REGS ; else cum ->


<s> if ( ! MaybeBit || ! isPowerOf2_64 ( MaybeBit -> Value ) ) return false ; uint64_t Bit = Log2_64 ( static_cast < uint64_t > ( MaybeBit -> Value ) ) ; Register TestReg = AndInst . getOperand ( <NUM_LIT> ) . getReg


<s> bool <ISA_LIT>BaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( getTargetLowering ( ) ) ) ; return


<s> struct ShuffleSourceInfo { SDValue Vec ; unsigned MinElt ; unsigned MaxElt ; SDValue ShuffleVec ; int WindowBase ; int WindowScale ; bool operator == ( SDValue OtherVec ) { return Vec == OtherVec ; } ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) { } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> ) { return SDValue ( ) ; } else if ( ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getScalarSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ; if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { if ( <NUM_LIT> * SrcVT . getSizeInBits ( ) != VT . getSizeInBits ( ) ) return SDValue ( ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src .

ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ;


<s> Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; uint64_t UImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeUImmOperand < <NUM_LIT> > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success &&


<s> assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm ( ) ; if ( ShAmt ) { assert ( ShAmt <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << ShAmt << markup ( <STR_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT>


<s> return mode == V8QImode || mode == V4HImode || mode


<s> return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond ,


<s> Preferred . pop ( ) ; if ( ! Loops . empty ( ) && ! MDT . dominates ( Loops . back ( ) . Loop -> getHeader ( ) , Next ) ) { Loops . back ( ) . Deferred . push_back ( Next ) ; Next = nullptr ; continue ; } if ( Next -> getNumber ( ) < MBB -> getNumber ( ) && ( ! L || ! L -> contains ( Next ) || L -> getHeader ( ) -> getNumber ( ) < Next -> getNumber ( ) ) ) { Ready . push ( Next ) ; Next = nullptr ; continue ; } break ; } if ( ! Next ) { if ( Ready . empty ( ) ) { MaybeUpdateTerminator ( MBB ) ; break ; } for ( ; ; ) { Next = Ready . top ( ) ; Ready . pop ( ) ; if ( ! Loops . empty ( ) && ! MDT . dominates ( Loops . back ( ) . Loop -> getHeader ( ) , Next ) ) { Loops . back ( ) . Deferred . push_back ( Next ) ; continue ; } break ; } } Next -> moveAfter ( MBB ) ; MaybeUpdateTerminator ( MBB ) ; MBB = Next ; } assert ( Loops . empty ( ) && <STR_LIT> ) ; MF . RenumberBlocks ( ) ; SmallSetVector < MachineLoop * , <NUM_LIT> > OnStack ; OnStack . insert ( nullptr ) ; for ( auto & MBB : MF ) { assert ( MBB . getNumber ( ) >= <NUM_LIT> && <STR_LIT> ) ; MachineLoop * Loop = MLI . getLoopFor ( & MBB ) ; if ( Loop && & MBB == Loop -> getHeader ( ) ) { for ( auto Pred : MBB . predecessors ( ) ) assert ( ( Pred -> getNumber ( ) < MBB . getNumber ( ) || Loop -> contains ( Pred ) ) && <STR_LIT> ) ; assert ( OnStack . insert ( Loop ) && <STR_LIT> ) ; } else { for ( auto Pred : MBB . predecessors ( ) ) assert ( Pred -> getNumber ( ) < MBB . getNumber ( ) && <STR_LIT> ) ; assert ( OnStack . count ( MLI . getLoopFor ( & MBB ) ) && <STR_LIT> ) ; } while ( OnStack . size ( ) > <NUM_LIT> && & MBB == <STR_LIT> ( OnStack . back ( ) ) ) OnStack . pop_back ( ) ; } assert ( OnStack . pop_back_val ( ) == nullptr &&


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI


<s> DEBUG ( errs ( ) << <STR_LIT> << J << <STR_LIT> << BBOffsets [ J ] << <STR_LIT> << BBSizes [


<s> return TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - ( STI . isR9Reserved ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } case


<s> void setCalleeSavedFrameSize ( unsigned Bytes ) { CalleeSavedFrameSize =


<s> static std :: string estr [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( xuse < <STR_LIT> ) ; return estr [ xuse


<s> if ( ! GV -> hasInitializer ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } static const char * Ignored [ ] = { <STR_LIT> , <STR_LIT> } ; for ( const char * I : Ignored ) if ( Name == I ) return ; static const char * Unhandled [ ] = { <STR_LIT> , <STR_LIT> } ; for ( const char * U : Unhandled ) if ( Name == U ) report_fatal_error ( <STR_LIT> ) ; if ( Name . startswith ( <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; if ( GV -> isThreadLocal ( ) ) report_fatal_error ( <STR_LIT> ) ; const DataLayout & DL = getDataLayout ( ) ; const Constant * Init = GV ->


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) .

addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> return LowerVACOPY ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG , Subtarget ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_


<s> return ( ( alpha_tune == PROCESSOR_EV4 || alpha_tune == PROCESSOR_EV5 ) && optimize


<s> if ( Entry -> succ_size ( ) != <NUM_LIT> ) { return false ; } for ( MachineBasicBlock :: const_succ_iterator <ISA_LIT> = Entry -> succ_begin ( ) , E = Entry -> succ_end ( ) ; <ISA_LIT> != E ; ++ <ISA_LIT> ) { MachineBasicBlock * Current = * <ISA_LIT> ; if ( Current ==


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo &


<s> break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; unsigned LongFormBits = <NUM_LIT> ; unsigned LongFormScale = <NUM_LIT> ; unsigned LongFormOpcode = <NUM_LIT> ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; LongFormOpcode = <STR_LIT> ; LongFormBits = <NUM_LIT> ; LongFormScale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; unsigned LongFormMaxOffs = ( ( <NUM_LIT> << LongFormBits


<s> res . as_int [ <NUM_LIT> ] = __i1 ; return ( res . as_m64


<s> if ( TARGET_ES0 && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && TREE_ADDRESSABLE ( decl ) && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_GENERIC ) { tree type = TREE_TYPE ( decl ) ; tree attr = TYPE_ATTRIBUTES ( type ) ; int q = TYPE_QUALS_NO_ADDR_SPACE ( type ) | ENCODE_QUAL_ADDR_SPACE ( ADDR_SPACE_FAR ) ; TREE_TYPE ( decl ) = build_type_attribute_qual_variant ( type


<s> return TARGET_SAFE_DMA && channel >= <NUM_LIT> && channel


<s> static inline bool isSingleUnscheduledSucc ( SUnit * SU , SUnit * SU2 ) { if ( SU -> NumSuccsLeft == <NUM_LIT> ) return false ; for ( auto & Succ : SU -> Succs ) { if ( ! Succ . getSUnit ( ) -> isScheduled && ( Succ . getSUnit ( ) != SU2 ) ) return false ; } return true


<s> if ( CONST_OK_FOR_M ( value ) ) return <NUM_LIT> ; if ( CONST_OK_FOR_N ( value ) && value != - <NUM_LIT>


<s> if ( isLogicOp ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) && N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) WideRes = computeLogicOpInGPR ( N -> getOperand ( <NUM_LIT> ) ) ; else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return nullptr ; else WideRes = getSETCCInGPR ( N -> getOperand ( <NUM_LIT> ) , N -> getOpcode ( ) == <STR_LIT> ? SetccInGPROpts :: SExtOrig : SetccInGPROpts :: ZExtOrig ) ; if ( ! WideRes ) return nullptr ; SDLoc dl ( N ) ; bool Input32Bit = WideRes . getValueType ( ) == <STR_LIT> ; bool Output32Bit = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ; NumSextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; NumZextSetcc += N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue ConvOp = WideRes ; if ( Input32Bit != Output32Bit ) ConvOp = addExtOrTrunc ( WideRes , Input32Bit ? ExtOrTruncConversion :: Ext : ExtOrTruncConversion :: Trunc


<s> const MCExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: CreateAdd ( Expr , OffsetExpr , Ctx ) ; } return MCOperand :: CreateExpr (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase &


<s> for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( ! MO . clobbersPhysReg ( reg


<s> if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( ( Reg - <STR_LIT> ) * <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addImm ( Reg - <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } MachineInstrBuilder VLLDM = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( STI -> fixCMSE_CVE_2021_35465 ( ) ) { auto Bundler = MIBundleBuilder ( MBB , VLLDM ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ) ; Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; if ( STI -> hasFPRegs ( ) ) Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Undef ) . add ( predOps ( <STR_LIT> ) ) ) ; else Bundler . append ( BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addImm ( InlineAsm :: Extra_HasSideEffects ) ) ; finalizeBundle ( MBB , Bundler . begin ( ) , Bundler . end ( ) ) ; } for ( const auto & Regs : ClearedFPRegs ) { unsigned Reg , SaveReg1 , SaveReg2 ; std :: tie ( Reg , SaveReg1 , SaveReg2 ) = Regs ; if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 ) . addReg ( SaveReg2 ) . add ( predOps ( <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( Reg ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( SaveReg1 )


<s> SDValue MaxRHS = Op0 . getOperand ( <NUM_LIT> ) ; if ( MaxLHS == Op1 ) SubusLHS = MaxRHS ; else if ( MaxRHS == Op1 ) SubusLHS = MaxLHS ; else return SDValue ( ) ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SubusLHS = Op0 ; SDValue MinLHS = Op1 . getOperand ( <NUM_LIT> ) ; SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; auto USUBSATBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { SubusLHS , SubusRHS } , USUBSATBuilder ) ; KnownBits Known = DAG . computeKnownBits ( SubusLHS ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( ) ) , SDLoc ( SubusLHS ) , ExtType ) ; SDValue UMin = DAG . getNode ( <STR_LIT> , SDLoc ( SubusLHS ) , ExtType , SubusRHS , SaturationConst ) ; SDValue NewSubusLHS = DAG . getZExtOrTrunc ( SubusLHS , SDLoc ( SubusLHS ) , ShrinkedType ) ; SDValue NewSubusRHS = DAG . getZExtOrTrunc ( UMin , SDLoc


<s> } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) || ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base )


<s> if ( can_issue_more == <NUM_LIT> ) can_issue_more = issue_rate ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; if ( can_issue_more == issue_rate - <NUM_LIT> ) end = false ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } n_nops -- ; } can_issue_more ++ ; * group_end = ( end || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ; if ( * group_end && end ) ( * group_count


<s> void <ISA_LIT>ConstantPoolValue :: dump ( ) const { errs ( ) << <STR_LIT> << *


<s> else if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Imm , S , E , getContext ( ) ) ) ; return MatchOperand_Success ; } Parser . Lex ( ) ; if ( ! Parser . getTok ( ) . is ( AsmToken :: Identifier ) || ! Parser . getTok ( ) . getIdentifier ( ) . equals_lower ( <STR_LIT> ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; parseOptionalToken ( AsmToken :: Hash ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal


<s> Blocks . push_back ( P ) ; assert ( ( Blocks . size ( ) < ( ( size_t ) <NUM_LIT> << ( <NUM_LIT> * sizeof ( NodeId ) - BitsPerIndex


<s> return ( MCInstD . TSFlags >> HasSrcCStart ) & <ISA_LIT>II


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { Value = adjustFixupValue ( Fixup , Value , & Asm . getContext ( ) ) ; if ( ! Value


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( )


<s> offset = cfun -> machine -> frame . acc_sp_offset - sp_offset ; if ( BITSET_P ( cfun -> machine -> frame . acc_mask , <NUM_LIT> ) ) { mips_save_restore_reg ( word_mode , LO_REGNUM , offset , fn ) ; offset -= UNITS_PER_WORD ; mips_save_restore_reg ( word_mode , HI_REGNUM , offset ,


<s> if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; typedef DenseMap < VNInfo * , VNInfo * > ValueInfoMap ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I -> start , I -> end , NewVN ) ) ; } while ( L2 . begin ( ) != L2 . end ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; updateKillFlags ( R1 . Reg ) ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> if ( MDT . dominates ( From , To ) ) return true ; const MachineBasicBlock * MBBFrom = From -> getParent ( ) ; const MachineBasicBlock * MBBTo = To -> getParent (


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned PtrIdx = getBasePtrIndex ( N ) ; SDValue Ptr = N -> getOperand ( PtrIdx ) ; if ( Ptr . getOpcode ( ) == <STR_LIT> ) { SDValue NewPtr = performSHLPtrCombine ( Ptr . getNode ( ) , N -> getAddressSpace ( ) , N -> getMemoryVT ( ) , DCI ) ; if ( NewPtr ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ PtrIdx ] = NewPtr ; return SDValue ( DAG . UpdateNodeOperands ( N , NewOps )


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( ! isIdentityValue ( OrigMI . getOpcode ( ) , OldOpndValue ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } CombOldVGPR = getRegSubRegPair ( * Src1 ) ; if ( ! isOfRegClass ( CombOldVGPR , <STR_LIT> , * MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering


<s> bitmap_clear_bit ( to_clear_bitmap , IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; bitmap_clear_bit ( to_clear_bitmap , <NUM_LIT> ) ; } } for ( regno = NUM_ARG_REGS ; regno <= maxregno ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( ! callee_saved_reg_p ( regno ) && ( ! IN_RANGE ( regno , FIRST_VFP_REGNUM , LAST_VFP_REGNUM ) || TARGET_HARD_FLOAT ) ) bitmap_set_bit ( to_clear_bitmap , regno ) ; } result_type = TREE_TYPE ( DECL_RESULT ( current_function_decl ) ) ; if ( ! VOID_TYPE_P ( result_type ) ) { uint64_t to_clear_return_mask ; result_rtl = arm_function_value ( result_type , current_function_decl , <NUM_LIT> ) ; gcc_assert ( REG_P ( result_rtl ) ) ; to_clear_return_mask = compute_not_to_clear_mask ( result_type , result_rtl , <NUM_LIT> , & padding_bits_to_clear ) ; if ( to_clear_return_mask ) { gcc_assert ( ( unsigned ) maxregno < sizeof ( long long ) * __CHAR_BIT__ ) ; for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_return_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap


<s> std :: unique_ptr < const MCInstrInfo > MCII ( T . createMCInstrInfo (


<s> <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; unsigned TargetFlags = get ( Opcode ) . TSFlags ; unsigned OpTableIdx ; if ( ! HAS_NATIVE_OPERANDS ( TargetFlags ) ) { switch ( Op ) { case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default : assert ( ! <STR_LIT> ) ; return - <NUM_LIT> ; } } if ( TargetFlags


<s> int GCNHazardRecognizer :: checkDPPHazards ( MachineInstr * DPP ) { const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; int DppVgprWaitStates = <NUM_LIT> ; int WaitStatesNeeded = <NUM_LIT> ; for ( const MachineOperand & Use : DPP -> uses ( ) ) { if ( ! Use . isReg ( ) || ! TRI -> isVGPR ( MF . getRegInfo ( ) , Use . getReg ( ) ) ) continue ; int WaitStatesNeededForUse = DppVgprWaitStates - getWaitStatesSinceDef ( Use .


<s> void <ISA_LIT>CopyElision :: ExitScope ( MachineBasicBlock * MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName (


<s> Value * RVal = RI -> getReturnValue ( ) ; if ( ! RVal ) continue ; Type * T = RVal -> getType ( ) ; FPReturnVariant RV = whichFPReturnVariant ( T ) ; if ( RV == NoFPRet ) continue ; static const char * Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeSet A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , NULL ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { if ( Subtarget . getRelocationModel ( ) != Reloc :: PIC_


<s> std :: vector < <ISA_LIT>FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlign ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == <NUM_LIT> ) SortingObjects [ Obj ] . ObjectSize = <NUM_LIT> ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB :


<s> count = exact_log2 ( - val ) ; if ( count < <NUM_LIT> ) return <NUM_LIT> ; if ( count > ( optimize_insn_for_speed_p ( ) ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; return count ; } else { count = exact_log2 ( val +


<s> vmlsq_s32 ( int32x4_t a , int32x4_t b , int32x4_t c ) { int32x4_t result


<s> MachineSDNode * <ISA_LIT>DAGToDAGISel :: buildSMovImm64 ( SDLoc & DL , uint64_t Imm , EVT VT ) const { SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ; SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm >> <NUM_LIT> , DL , <STR_LIT> ) ) ; const SDValue Ops [ ]


<s> unsigned <ISA_LIT>16SPAliasReg = MF -> getInfo < <ISA_LIT>FunctionInfo >


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MCFixupKind Fixup = MCFixupKind ( <STR_LIT>


<s> else CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; return OptLevel >=


<s> if ( ! Op . isReg ( ) || Op . isImplicit ( ) || ! Op . isUse ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ; if ( ! Def ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: INLINEASM ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: PHI ) continue ; if ( Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> ) continue ; if ( ! MRI . hasOneUse ( Reg ) ) continue ; if ( Def -> getParent ( ) != & MBB ) continue ; if ( ! IsSafeToMove ( Def , Insert , AA , LIS , MRI ) ) continue ; Changed = true ; AnyStackified = true ; MBB . splice ( Insert , & MBB , Def ) ; LIS . handleMove ( Def ) ; MFI . stackifyVReg ( Reg ) ; ImposeStackOrdering ( Def ) ; Insert = Def ; } if ( AnyStackified ) ImposeStackOrdering ( & MI ) ; } } if ( Changed ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) MBB . addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > Stack ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI :


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ?


<s> ColPHI . addReg ( InColReg ) . addMBB ( InMBB ) ; AddrPHI . addReg ( InStackAddrReg ) . addMBB ( InMBB ) ; } } else { InsertPos = TileDefMI -> getIterator ( ) ; ShapeT Shape = getShape ( MRI , InTileReg ) ; Shape . getRow ( ) -> setIsKill ( false ) ; Shape . getCol ( ) -> setIsKill ( false ) ; RowPHI . addReg ( Shape . getRow ( ) -> getReg ( ) ) . addMBB ( InMBB ) ; ColPHI . addReg ( Shape . getCol ( ) -> getReg ( ) ) . addMBB ( InMBB ) ; int FI = getStackSpaceFor ( InTileReg ) ; Register InStackAddrReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; addOffset ( BuildMI ( * TileDefMI -> getParent ( ) , InsertPos , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , InStackAddrReg ) . addFrameIndex ( FI ) , <NUM_LIT> ) ; AddrPHI . addReg ( InStackAddrReg ) . addMBB ( InMBB ) ; } } MachineBasicBlock :: iterator InsertPos = MBB -> getFirstNonPHI ( ) ; Register StrideReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , InsertPos , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , StrideReg ) . addImm ( <NUM_LIT> ) ; Register TileReg = PHI . getOperand ( <NUM_LIT> ) . getReg


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode2OffsetImmPre ( SDNode * Op , SDValue N , SDValue & Offset , SDValue &


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitMove ( MI , <STR_LIT> ) ; return true ; case <STR_LIT> : splitAdjDynAlloc ( MI


<s> SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , Mask , Src , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl ,


<s> return gen_rtx_REG ( TYPE_MODE ( valtype ) ,


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( SDValue V = combineShiftToPMULH ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT>


<s> static SDValue LowerSDIV ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; EVT EltTy = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; BuildVectorSDNode * C = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) || EltTy . getSizeInBits ( ) < SplatBitSize ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned Lg2 = SplatValue . countTrailingZeros ( ) ; SmallVector < SDValue , <NUM_LIT> > Sz ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , EltTy ) ) ; SDValue SGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getNode ( <STR_LIT> , dl , VT , & Sz [ <NUM_LIT> ] , NumElts ) ) ; SmallVector < SDValue , <NUM_LIT> > Amt ( NumElts , DAG . getConstant ( EltTy . getSizeInBits ( ) - Lg2 , EltTy ) ) ; SDValue SRL = DAG . getNode ( <STR_LIT> , dl , VT , SGN , DAG . getNode ( <STR_LIT> , dl , VT , & Amt [ <NUM_LIT> ] , NumElts ) ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectFrameIndex ( SDNode * Node ) { int FI = cast < FrameIndexSDNode > ( Node )


<s> if ( OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) { bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( Pred [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) ; } else { MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; } return true ; } else if ( OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) { bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( Pred [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) ; } else { MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( MBB ) ; } return true ; } else if ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool setLR = OpC == <STR_LIT> || OpC == <STR_LIT> ; bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; MI -> setDesc ( get ( is<ISA_LIT>64 ? ( setLR ? <STR_LIT> : <STR_LIT> ) : ( setLR ? <STR_LIT> :


<s> unsigned A15SDOptimizer :: createRegSequence ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL , unsigned Reg1 , unsigned Reg2 ) { Register Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , Out ) . addReg ( Reg1 ) . addImm ( <STR_LIT> ) . addReg ( Reg2 ) . addImm ( <STR_LIT> ) ; return Out


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return


<s> if ( M -> definesRegister ( SReg , TRI ) ) break ; if ( M -> modifiesRegister ( SReg , TRI ) ) return Changed ; ReadsSreg |= M -> readsRegister ( SReg , TRI ) ; } if ( M == E || ! M -> isMoveImmediate ( ) || ! M -> getOperand ( <NUM_LIT> ) . isImm ( ) || M -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return Changed ; if ( ! ReadsSreg && Op2 . isKill ( ) ) { A -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( - <NUM_LIT> ) ; M -> eraseFromParent ( ) ; } } if ( ! ReadsCond && A -> registerDefIsDead ( <STR_LIT> ) && MI . killsRegister ( CondReg , TRI ) ) A -> eraseFromParent ( ) ; bool IsVCCZ = MI . getOpcode ( ) == <STR_LIT> ; if ( SReg == ExecReg ) { if ( IsVCCZ ) { MI . eraseFromParent ( ) ; return true ; } MI . setDesc ( TII -> get (


<s> void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = nullptr ) ; void printRegisterList ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void EmitStartOfAsmFile ( Module & M ) override ; void EmitEndOfAsmFile ( Module & M ) override ; void PrintDebugValueComment ( const MachineInstr * MI , raw_ostream


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget

( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {


<s> return ( __m512i ) __builtin_ia32_vcvttph2dq512_mask_round ( __A , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16

) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst *


<s> rtx_code code = GET_CODE ( scan ) ; if ( INSN_P ( scan ) ) { used |= regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; if ( code == CALL_INSN ) used |= regs_used ( CALL_INSN_FUNCTION_USAGE ( scan ) , <NUM_LIT> ) ; dead |= ( used >> <NUM_LIT> ) & ~ used ; if ( dead & attempt ) { dead &= attempt ; break ; } if ( code == JUMP_INSN ) { if ( jump_left -- && simplejump_p ( scan ) ) scan = JUMP_LABEL_AS_INSN ( scan ) ; else break ; } } } dead &= <NUM_LIT> ; } else if ( optimize && need_block >= <NUM_LIT> ) { rtx_insn * next = next_active_insn ( as_a < rtx_insn * > ( dest ) ) ; next = next_active_insn ( next ) ; if ( next && JUMP_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SET && recog_memoized ( next ) == CODE_FOR_jump_compact ) { dest = JUMP_LABEL ( next ) ; if ( dest && ( INSN_ADDRESSES ( INSN_UID ( dest ) ) - addr + ( unsigned ) <NUM_LIT> > <NUM_LIT> + <NUM_LIT> ) ) gen_block_redirect ( next , INSN_ADDRESSES ( INSN_UID ( next ) ) , - <NUM_LIT> ) ; } } if ( dead


<s> Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( DestVT . bitsGT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub ) ; return Sub


<s> for ( auto * MI : C . instructions ( ) ) Cost += Converters . find ( { DstDomain , MI -> getOpcode ( ) } ) -> second -> getExtraCost ( MI , MRI ) ; return


<s> switch ( ShaderType ) { default : case ShaderType :: COMPUTE : return R_00B848_COMPUTE_PGM_RSRC1 ; case ShaderType :: GEOMETRY : return


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind (


<s> unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr ::


<s> static scalar_int_mode spu_libgcc_cmp_return_mode ( void ) { return SImode


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; int D8SpillFI = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) if ( CSI [ i ] . getReg ( ) == <STR_LIT> ) { D8SpillFI = CSI [ i ] . getFrameIdx ( ) ; break ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addFrameIndex ( D8SpillFI ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT>


<s> else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT ,

<NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ;


<s> TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCCodeEmitter ( getTheGCNTarget ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getTheGCNTarget ( ) , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getTheGCNTarget ( )


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ; return


<s> return ! riscv_naked_function_p ( decl


<s> bool isMSACtrlAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind &

RegKind_MSACtrl && RegIdx . Index <= <NUM_LIT> ;


<s> bool <ISA_LIT>AsmParser :: isOperandModifier ( const AsmToken &

Token , const AsmToken & NextToken ) const {


<s> void <ISA_LIT>TargetStreamer :: changeSection ( const MCSection * CurSection , MCSection * Section , const MCExpr * SubSection , raw_ostream & OS ) { assert ( ! SubSection && <STR_LIT> ) ; const MCObjectFileInfo * FI = getStreamer ( ) . getContext ( ) . getObjectFileInfo ( ) ; if ( isDwarfSection ( FI , CurSection ) ) OS << <STR_LIT> ; if ( isDwarfSection ( FI , Section ) ) { outputDwarfFileDirectives ( ) ; OS << <STR_LIT>


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( )


<s> static const char * s390_invalid_binary_op ( int op ATTRIBUTE_UNUSED , const_tree type1 , const_tree type2 ) { bool bool1_p , bool2_p ; bool plusminus_p ; bool muldiv_p ; bool compare_p ; machine_mode mode1 , mode2 ; if ( ! TARGET_ZVECTOR ) return NULL ; if ( ! VECTOR_TYPE_P ( type1 ) || ! VECTOR_TYPE_P ( type2 ) ) return NULL ; bool1_p = s390_vector_bool_type_p ( type1 ) ; bool2_p = s390_vector_bool_type_p ( type2 ) ; if ( ! bool1_p && ! bool2_p && TYPE_UNSIGNED ( type1 ) != TYPE_UNSIGNED ( type2 ) ) return N_ ( <STR_LIT> ) ; plusminus_p = ( op == PLUS_EXPR || op == MINUS_EXPR ) ; muldiv_p = ( op == MULT_EXPR || op == RDIV_EXPR || op == TRUNC_DIV_EXPR || op == CEIL_DIV_EXPR || op == FLOOR_DIV_EXPR || op == ROUND_DIV_EXPR ) ; compare_p = ( op == LT_EXPR || op == LE_EXPR || op == GT_EXPR || op == GE_EXPR || op == EQ_EXPR || op == NE_EXPR ) ; if ( bool1_p && bool2_p && ( plusminus_p || muldiv_p


<s> unsigned TwoXLenInBytes = ( <NUM_LIT> * XLen ) / <NUM_LIT> ; if ( ! IsFixed && ArgFlags . getOrigAlign ( ) == TwoXLenInBytes && DL . getTypeAllocSize ( OrigTy ) == TwoXLenInBytes ) { unsigned RegIdx = State . getFirstUnallocated ( ArgGPRs ) ; if ( RegIdx != array_lengthof ( ArgGPRs ) && RegIdx % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgGPRs ) ; } SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ; PendingArgFlags . clear


<s> static void translateFPRegister ( MCInst & mcInst , uint8_t stackPos ) { assert ( stackPos <


<s> TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo


<s> Optional < ParamLoadedValue > <ISA_LIT>InstrInfo :: describeLoadedValue ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) .


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; SmallPtrSet < const MachineBasicBlock * , <NUM_LIT> > JumpTableTargets ; if ( const MachineJumpTableInfo * JTI = MF . getJumpTableInfo ( ) ) for ( const MachineJumpTableEntry & JTE : JTI -> getJumpTables ( ) ) for ( const MachineBasicBlock * MBB : JTE . MBBs ) JumpTableTargets . insert ( MBB ) ; bool MadeChange = false ; for ( MachineBasicBlock & MBB :


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = std :: string ( FS ) ; } ParseSubtargetFeatures ( CPUString , CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) && ! hasMinSize ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : case CortexX1 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && Val . hasOneUse ( ) ) if ( auto Const = dyn_cast < ConstantSDNode > ( N -> getOperand (

<NUM_LIT> ) ) ) if ( ( Const -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return implicitlyClearTop ( Val , DAG ) ;


<s> <ISA_LIT>Gfx6CacheControl ( const <ISA_LIT>Subtarget & ST )


<s> for ( const auto & MO : MI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT>

&& MO . isDef ( ) && ! MO . isDead ( ) ) return true ;


<s> AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective =


<s> bool hasAddressTaken ( ) const { if ( MBB ) return MBB -> hasAddressTaken ( ) ; return false


<s> DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { auto * EE = dyn_cast < ExtractElementInst > ( & I ) ; if ( ! EE ) continue ; Value * Root = matchAddReduction ( * EE ) ; if ( ! Root )


<s> OS << MI -> getDebugVariable ( ) -> getName ( ) ; OS << <STR_LIT> ; assert ( MI -> getDebugOperand ( <NUM_LIT> ) . isReg ( ) && MI -> isDebugOffsetImm ( ) ) ; OS << '['


<s> case <STR_LIT> : { StructType * ST = dyn_cast < StructType > ( ExpectedType ) ; if ( ! ST ) return nullptr ; unsigned NumElts = Inst -> arg_size ( ) - <NUM_LIT> ; if ( ST -> getNumElements ( ) != NumElts ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { if ( Inst -> getArgOperand ( i ) -> getType ( ) != ST -> getElementType ( i ) ) return nullptr ; } Value * Res = UndefValue :: get ( ExpectedType ) ; IRBuilder < > Builder ( Inst ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { Value * L = Inst -> getArgOperand ( i ) ; Res = Builder . CreateInsertValue ( Res , L , i ) ; } return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst -> getType ( ) == ExpectedType )


<s> } if ( Tok . is ( AsmToken :: Integer ) && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { if ( Tok . getIntVal ( ) > <NUM_LIT> || isNegative ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } APFloat F ( ( double ) <STR_LIT> ( Tok . getIntVal ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( F , true , S , getContext ( ) ) ) ; } else { APFloat RealVal ( APFloat :: IEEEdouble ( ) ) ; auto StatusOrErr = RealVal . convertFromString ( Tok . getString ( ) , APFloat :: rmTowardZero ) ; if ( errorToBool ( StatusOrErr . takeError ( ) ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( isNegative ) RealVal . changeSign ( ) ; if ( AddFPZeroAsLiteral && RealVal . isPosZero ( ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S , getContext ( ) ) ) ; } else Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( RealVal , * StatusOrErr == APFloat :: opOK , S , getContext ( ) ) ) ; } Lex ( ) ; return


<s> if ( Amount >= N . getValueType ( ) . getSizeInBits ( ) ) return false ; ShiftVal = Amount ; return


<s> if ( cond_code == NE ) emit_insn ( gen_e500_flip_gt_bit ( t , t ) ) ; emit_insn ( gen_move_from_CR_gt_bit ( result , t ) ) ; return ; } if ( cond_code == NE || cond_code == GE || cond_code == LE || cond_code == GEU || cond_code == LEU || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE ) { rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , <NUM_LIT> ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , <NUM_LIT> ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , <NUM_LIT> ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result , condition_rtx )


<s> SDValue Mag = Op . getOperand ( <NUM_LIT> ) ; SDValue Sign = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( Sign . getSimpleValueType ( ) . bitsLT ( VT ) ) Sign = DAG . getNode ( <STR_LIT> , dl , VT , Sign ) ; if ( Sign . getSimpleValueType ( ) . bitsGT ( VT ) ) Sign = DAG . getNode ( <STR_LIT> , dl , VT , Sign , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; bool IsF128 = ( VT == <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; SDValue SignMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignMask ( EltSizeInBits ) ) , dl , LogicVT ) ; SDValue MagMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignedMaxValue ( EltSizeInBits ) ) , dl , LogicVT ) ; if ( IsFakeVector ) Sign = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign , SignMask ) ; SDValue MagBits ; if ( ConstantFPSDNode * Op0CN = isConstOrConstSplatFP ( Mag ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; APF . clearSign ( ) ; MagBits = DAG . getConstantFP ( APF , dl , LogicVT ) ; } else { if ( IsFakeVector ) Mag = DAG . getNode ( <STR_LIT> , dl , LogicVT , Mag ) ; MagBits = DAG . getNode ( <STR_LIT> , dl , LogicVT , Mag , MagMask ) ; } SDValue Or = DAG . getNode ( <STR_LIT> , dl , LogicVT , MagBits , SignBit ) ; return ! IsFakeVector ? Or : DAG . getNode ( <STR_LIT> , dl , VT , Or , DAG . getIntPtrConstant


<s> bool <ISA_LIT>CondBrFoldingPass :: runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget <


<s> rtx split_small_symbolic_operand ( rtx x ) { x = copy_insn ( x ) ; for_each_rtx ( & x , split_small_symbolic_operand_1 , NULL ) ; return


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { report_fatal_error (


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) )


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective =


<s> SDValue IndexNodes [ <STR_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) if ( Bytes [ I ] >= <NUM_LIT> ) IndexNodes [ I ] = DAG . getConstant ( Bytes [ I ] , DL , <STR_LIT> ) ; else IndexNodes [ I ] = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IndexNodes ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [

<NUM_LIT> ] , Ops [ <NUM_LIT> ] , Op2 ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( create<ISA_LIT>PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows (


<s> t = __ev_mwhsmf ( a , b ) ; return __ev_addsmiaaw (


<s> if ( NeedsDwarfCFI ) { assert ( StackSize ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> * stackGrowth ) ) ; int DwarfFramePtr = TRI -> getDwarfRegNum ( MachineFramePtr , true ) ; assert ( DwarfFramePtr > <NUM_LIT> ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createOffset ( nullptr , DwarfFramePtr , <NUM_LIT> * stackGrowth ) ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , FramePtr ) . addReg ( StackPtr ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsDwarfCFI ) { unsigned DwarfFramePtr = TRI -> getDwarfRegNum ( MachineFramePtr , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfaRegister ( nullptr , DwarfFramePtr ) ) ; } for ( MachineBasicBlock & EveryMBB : MF ) EveryMBB . addLiveIn ( MachineFramePtr ) ; } else { NumBytes = StackSize - MMFI -> getCalleeSavedFrameSize ( ) ; } bool PushedRegs = false ; int StackOffset = <NUM_LIT> * stackGrowth ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { PushedRegs = true ; ++ MBBI ; if ( ! HasFP && NeedsDwarfCFI ) { assert ( StackSize ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackOffset ) ) ; StackOffset += stackGrowth


<s> rtx rval , mem , oldval , newval , neg_bval ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ <NUM_LIT> ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ <NUM_LIT> ] ) ) ; neg_bval = TARGET_THUMB1 ? operands [ <NUM_LIT> ] : operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_release ( mod_s ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_acquire ( mod_s ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx (


<s> sysctlbyname ( <STR_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ; l1_sizekb = <NUM_LIT>


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) ) continue ; if ( ! MI -> isPHI ( ) && ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; Register R = Op . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) || ! isDead ( R ) ) { AllDead = false


<s> Value * Pair = concat ( Builder , { Lo , Hi } ) ; Value * Shift = Builder . CreateLShr ( Builder . CreateShl ( Pair , Amt ) , <NUM_LIT> ) ; Value * Trunc = Builder . CreateTrunc ( Shift , Type :: getInt32Ty ( F . getContext ( ) ) ) ; return Builder . CreateBitCast ( Trunc , Hi -> getType ( ) ) ; } if ( VecLen == <NUM_LIT> ) { Value * Sub = Builder . CreateSub ( getConstInt ( VecLen ) , Amt ) ; return vralignb ( Builder , Lo , Hi , Sub ) ; } llvm_unreachable ( <STR_LIT>


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : case 'f' : case 'e'


<s> MCE . processDebugLoc ( MI . getDebugLoc ( ) , true ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return ; emitWordLE ( getBinaryCodeForInstr ( MI ) ) ; ++ NumEmitted ; MCE . processDebugLoc ( MI .


<s> case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; break ; default : llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>TargetStreamer :: AnnotateTLSDescriptorSequence ( const MCSymbolRefExpr * SRE ) { llvm_unreachable ( <STR_LIT>


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; TargetPassConfig :: addIRPasses (


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>Target , mcld ::


<s> } switch ( Kind ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR8 : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR16_LO : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR24_SEGMENT_LO : Value &= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR16_HI : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR24_SEGMENT_HI : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR24_BANK : Value &= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR24_SEGMENT : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_IMM16 : Value &= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR_ASCIZ : llvm_unreachable ( <STR_LIT>


<s> OW -> write8 ( <NUM_LIT> ) ; } while ( Count ) { Count -= HEXAGON_INSTR_SIZE ; uint32_t ParseBits = ( Count % ( HEXAGON_PACKET_SIZE *

HEXAGON_INSTR_SIZE ) ) ? ParseIn : ParseEnd ;


<s> else if ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) && ix86_notrack_prefixed_insn_p (


<s> if ( reg >= NPARM_REGS ) return <NUM_LIT> ; if ( reg + mcore_num_arg_regs ( mode , type ) <= NPARM_REGS ) return <NUM_LIT> ; reg = NPARM_REGS - reg ; return reg


<s> MachineBasicBlock * PredMBB = nullptr ; if ( MBB -> pred_size ( ) == <NUM_LIT> ) PredMBB = * MBB -> pred_begin ( ) ; if ( MBB -> pred_size ( ) == <NUM_LIT> && Loop != nullptr &&


<s> bool isGPRZeroAsmReg ( ) const { return isRegIdx ( ) && RegIdx . Kind & RegKind_GPR


<s> SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , Not ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( VT

. getSizeInBits ( ) , DL , <STR_LIT> ) ) ;


<s> default : printRegOperand ( Op . getReg ( ) , O , MRI ) ; break ; } } else if ( Op . isImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; if ( RCID != - <NUM_LIT> ) { const MCRegisterClass & ImmRC = MRI . getRegClass ( RCID ) ; if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate32 ( Op . getImm ( ) , O ) ; else if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate64 ( Op . getImm ( ) , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( Desc . OpInfo [ OpNo ] . OperandType ==


<s> const LDSymbol * getGpDispSymbol ( ) const { return m_pGpDispSymbol


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned Reg = MO


<s> static reg_class_t xtensa_preferred_output_reload_class ( rtx x ATTRIBUTE_UNUSED , reg_class_t rclass ) { if ( rclass == AR_REGS ||


<s> if ( parseRegister ( Reg ) ) return true ; if ( Reg . Group != Group ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Regs && Regs [ Reg . Num ] == <NUM_LIT> ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Reg . Num == <NUM_LIT> && IsAddress ) return Error ( Reg . StartLoc , <STR_LIT> ) ; if ( Regs ) Reg . Num = Regs [ Reg . Num ] ; return


<s> static bool h8300_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '#'


<s> unsigned Register = DPairDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg (


<s> int Idx = OpIndices [ i ] ; if ( Idx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; const TargetRegisterClass * OpRC = RI . getRegClass ( Desc . OpInfo [ Idx ] . RegClass ) ; bool IsRequiredSGPR = RI . isSGPRClass ( OpRC ) ; if ( IsRequiredSGPR ) return MO . getReg ( ) ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RegRC = MRI . getRegClass ( Reg ) ; if ( RI . isSGPRClass ( RegRC ) ) UsedSGPRs [ i ] =


<s> void addVectorRegLoOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> for ( unsigned Op : { G_UADDE } ) { setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; setAction ( { G_ZEXT , s32 } , Legal ) ; setAction ( { G_SEXT , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> LLT ValTy = MRI . getType ( Dst ) ; uint64_t ValSize = ValTy . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValTy , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , PtrTy , PtrAlign ) ) ; MI . eraseFromParent


<s> case <STR_LIT> : { MultOpc = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ; } case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> : { const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ; unsigned Size = CN -> getValueSizeInBits ( <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) break ; } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG )