<s> const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg (

DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;


<s> if ( Disable<ISA_LIT>IntABS ) return NULL ; if ( Subtarget -> isThumb1Only ( ) ) return NULL ; if ( XORSrc0 . getOpcode ( ) != <STR_LIT> || XORSrc1 . getOpcode ( ) != <STR_LIT> ) return NULL ; SDValue ADDSrc0 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue ADDSrc1 = XORSrc0 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc0 = XORSrc1 . getOperand ( <NUM_LIT> ) ; SDValue SRASrc1 = XORSrc1 . getOperand (


<s> PN = B . CreatePHI ( F . getReturnType ( ) , ReturningBlocks . size ( ) , <STR_LIT> ) ; assert ( ! InsertExport ) ; B . CreateRet ( PN ) ; } std :: vector < DominatorTree :: UpdateType > Updates ; Updates . reserve ( ReturningBlocks . size ( ) ) ; for ( BasicBlock * BB : ReturningBlocks ) { if ( PN ) PN -> addIncoming ( BB -> getTerminator ( ) -> getOperand ( <NUM_LIT> ) , BB ) ; BB -> getTerminator ( ) -> eraseFromParent ( ) ; BranchInst :: Create ( NewRetBlock , BB ) ; Updates . push_back ( { DominatorTree :: Insert , BB , NewRetBlock } ) ; } if ( RequireAndPreserveDomTree ) DTU . applyUpdates ( Updates ) ; Updates . clear ( ) ; for ( BasicBlock * BB : ReturningBlocks ) { simplifyCFG ( BB , TTI , RequireAndPreserveDomTree ? & DTU : nullptr , SimplifyCFGOptions ( ) . bonusInstThreshold ( <NUM_LIT> ) ) ; } return


<s> Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getGlobalReg ( DAG , Ty ) ) ; SDValue Wrapper = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getLoad ( Ty , DL


<s> Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; return OptLevel >= CodeGenOpt


<s> setBooleanContents ( ZeroOrOneBooleanContent ) ; setUsesGlobalOffsetTable ( true ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCT ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> ST = TM . getSubtargetImpl ( ) ; GR = ST -> get<ISA_LIT>GlobalRegistry ( ) ; TII = ST -> getInstrInfo ( ) ; MMI = & getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; setBaseInfo ( M ) ; numberRegistersGlobally ( M ) ; processOtherInstrs ( M ) ; return false


<s> break ; } case <STR_LIT> : { DstDivReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstRemReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } } const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const unsigned FirstSrcOpIdx = MI . getNumExplicitDefs ( ) ; Register Num = MI . getOperand ( FirstSrcOpIdx ) . getReg ( ) ; Register Den = MI . getOperand ( FirstSrcOpIdx + <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> )


<s> return ( __m128i ) __builtin_ia32_vphsubdq ( (


, const int __imm , mve_pred16_t __p ) {


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr *


<s> std :: string formatString ( const std :: string & format , ... ) { va_list args ; va_start ( args , format ) ; size_t len = std :: vsnprintf ( NULL , <NUM_LIT> , format . c_str ( ) , args ) ; va_end ( args ) ; std :: vector < char > vec ( len + <NUM_LIT> ) ; va_start ( args , format


<s> printThumbAddrModeRI5Operand ( MI , Op , O , <NUM_LIT>


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> EncodedBytes = <NUM_LIT> ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; int TOCSaveOffset = Subtarget -> getFrameLowering ( ) -> getTOCSaveOffset ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( TOCSaveOffset ) . addReg ( <STR_LIT> ) ) ; ++ EncodedBytes ; if ( ! Subtarget -> isELFv2ABI ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes ; } EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; ++ EncodedBytes


<s> Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = FnAttrs . getAttribute ( AttributeSet


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) ->


<s> Function * Callee = CB . getCalledFunction ( ) ; if ( ! Callee || Callee -> size ( ) != <NUM_LIT> ) return false ; const BasicBlock & BB = Callee -> getEntryBlock (


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> PM . add ( create<ISA_LIT>NopFillerPass ( * this


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange ( Mask [ i ] , NumOps , NumOps * <NUM_LIT> ) ) || ( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ; return


<s> int64_t Value = CE -> getValue ( ) ; return Value >= MinValue && Value <= MaxValue ; } return false


<s> case US_PLUS : case EQ : case NE : case LE : case LEU : case GT : case GTU : return simm5_p ( x ) ; case LT : case LTU


<s> SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> return DecodeMemAS ( Inst , insn , Address , Decoder , true ,


<s> void \ sdata2_section ( void ) \ { \ if ( in_section != in_sdata2 ) \ { \ in_section =

in_sdata2 ; \ fprintf ( asm_out_file , <STR_LIT> , SDATA2_SECTION_ASM_OP ) ; \ } \ }


<s> rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = <NUM_LIT> ; data -> cost [ vect_body ] = <NUM_LIT> ; data -> cost [ vect_epilogue ] =


<s> ModulePass * llvm :: create<ISA_LIT>LowerEmscriptenEHSjLj ( ) { return new <ISA_LIT>LowerEmscriptenEHSjLj


<s> MachineInstr * <ISA_LIT>ExpandCondsets :: genCondTfrFor ( MachineOperand & SrcOp , MachineBasicBlock :: iterator At , unsigned DstR , unsigned DstSR , const MachineOperand & PredOp , bool PredSense , bool ReadUndef , bool ImpUse ) { MachineInstr * MI = SrcOp . getParent ( ) ; MachineBasicBlock & B = * At -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( Subtarget . is64Bit ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } if ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr *


<s> assert ( false && <STR_LIT> ) ; return NULL ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , true , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , true , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , false , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ExpandCondMov ( MI , BB , dl , Subtarget , TII , false , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case


<s> static void vr4130_reorder ( rtx * ready , int nready ) { if ( vr4130_swap_insns_p ( ready [ nready - <NUM_LIT> ] , ready [ nready - <NUM_LIT> ] )

) mips_promote_ready ( ready , nready - <NUM_LIT> , nready - <NUM_LIT> ) ;


<s> int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ; uint64_t encoding = <STR_LIT> (


<s>
assert
(
!
Operands
.
empty
(
)
&&
<STR_LIT>
)
;
<ISA_LIT>Operand
*
Op
=
static_cast
<
<ISA_LIT>Operand
*
>
(
Operands
[
<NUM_LIT>
]
)
;
assert
(
Op
->
isToken
(
)
&&
<STR_LIT>
)
;
if
(
!
MatchInstructionImpl
(
Operands
,
Inst
)
)
return
false
;
StringRef
Base
=
Op
->
getToken
(
)
;
SmallString
<
<NUM_LIT>
>
Tmp
;
Tmp
+=
Base
;
Tmp
+=
' '
;
Op
->
setTokenValue
(
Tmp
.
str
(
)
)
;
Tmp
[
Base
.
size
(
)
]
=
'b'
;
bool
MatchB
=
MatchInstructionImpl
(
Operands
,
Inst
)
;
Tmp
[
Base
.
size
(
)
]
=
'w'
;
bool
MatchW
=
MatchInstructionImpl
(
Operands
,
Inst
)
;
Tmp
[
Base
.
size
(
)
]
=
'l'
;
bool
MatchL
=
MatchInstructionImpl
(
Operands
,
Inst
)
;
Tmp
[
Base
.
size
(
)
]
=
'q'
;
bool
MatchQ
=
MatchInstructionImpl
(
Operands
,
Inst
)
;
Op
->
setTokenValue
(
Base
)
;
if
(
MatchB
+
MatchW
+
MatchL
+
MatchQ
==
<NUM_LIT>
)
return
false
;
if
(
MatchB
+
MatchW
+
MatchL
+
MatchQ
!=
<NUM_LIT>
)
{
char
MatchChars
[
<NUM_LIT>
]
;
unsigned
NumMatches
=
<NUM_LIT>
;
if
(
!
MatchB
)
MatchChars
[
NumMatches
++
]
=
'b'
;
if
(
!
MatchW
)
MatchChars
[
NumMatches
++
]
=
'w'
;
if
(
!
MatchL
)
MatchChars
[
NumMatches
++
]
=
'l'
;
if
(
!
MatchQ
)
MatchChars
[
NumMatches
++
]
=
'q'
;
SmallString
<
<NUM_LIT>
>
Msg
;
raw_svector_ostream
OS
(
Msg
)
;
OS
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
!=
NumMatches
;
++
i
)
{
if
(
i
!=
<NUM_LIT>
)
OS
<<
<STR_LIT>
;
if
(
i
+
<NUM_LIT>
==
NumMatches
)
OS
<<
<STR_LIT>
;
OS
<<
<STR_LIT>
<<
Base
<<
MatchChars
[
i
]
<<
<STR_LIT>
;
}
OS
<<
<STR_LIT>
;
Error
(
IDLoc
,
OS
.
str
(
)


<s> if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GENERAL_REGS ; else if ( regno > AC3_REGNUM ) return NO_LOAD_FPU_REGS ; else if ( regno >= AC0_REGNUM ) return LOAD_FPU_REGS ; else if ( regno & <NUM_LIT> ) return MUL_REGS ; else return GENERAL_REGS


<s> return false ; case H8SX_SHIFT_NONE : break ; } emit_move_insn ( copy_rtx ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , copy_rtx ( operands [ <NUM_LIT> ] ) , gen_rtx_fmt_ee ( code , mode , copy_rtx ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( QImode ) ) ) ) ) ; return true


<s> if ( ! II ) return false ; if ( isAMXCast ( II ) ) return false ; if ( II -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) return true ; for ( Value * V : II -> args ( ) ) { if ( V -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) return true ; } return false


<s> resetUnwindDirectiveParserState ( ) ; getTargetStreamer ( ) . emitFnEnd ( ) ; return false


<s> <ISA_LIT>FixupHwLoops ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>FixupHwLoopsPass ( * PassRegistry ::


<s> unsigned getThumbBLTargetOpValue ( const MachineInstr & MI ,


<s> if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAES ( ) && isAESPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAddress ( ) && isAddressLdStPair ( FirstMI


<s> static MCStreamer * createWinCOFFStreamer ( MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && TAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > &&

Emitter , bool RelaxAll , bool IncrementalLinkerCompatible ) {


<s> static DecodeStatus DecodeLoadFP ( MCInst & Inst , unsigned insn , uint64_t Address


<s> raw_string_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr ::


<s> return ( __m512 ) __builtin_ia32_cvtdq2ps512_mask ( ( __v16si ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , ( __mmask16


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > (


<s> void <ISA_LIT>InstPrinter :: printCoprocOptionImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI


<s> case CONST : op = XEXP ( op , <NUM_LIT> ) ; return ( ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == LABEL_REF ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ; default : return <NUM_LIT>


<s> } if ( entity == EPIPHANY_MSW_ENTITY_CONFIG && NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) == SET && SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) == frame_pointer_rtx ) { gcc_assert ( cfun -> has_nonlocal_label ) ; return <NUM_LIT> ; } if ( recog_memoized ( insn ) < <NUM_LIT> ) return last_mode ; if ( get_attr_fp_mode ( insn ) == FP_MODE_ROUND_UNKNOWN && last_mode != FP_MODE_ROUND_NEAREST && last_mode != FP_MODE_ROUND_TRUNC ) { if ( entity == EPIPHANY_MSW_ENTITY_NEAREST ) return FP_MODE_ROUND_NEAREST ; if ( entity == EPIPHANY_MSW_ENTITY_TRUNC ) return FP_MODE_ROUND_TRUNC ; } if ( recog_memoized ( insn )


<s> MVT <ISA_LIT>TargetLowering :: getTypeForExtArgOrReturn ( MVT VT , <STR_LIT> ExtendKind ) const { MVT ReturnMVT ; if ( Subtarget -> is64Bit ( ) && VT == <STR_LIT> && ExtendKind == <STR_LIT> ) ReturnMVT = <STR_LIT> ; else ReturnMVT = <STR_LIT> ; MVT MinVT = getRegisterType ( ReturnMVT ) ; return VT . bitsLT ( MinVT ) ? MinVT


<s> uint64_t SupportedMask = <NUM_LIT> ; if ( ( ImmVal & SupportedMask ) != ImmVal ) { SelectCode ( N ) ; } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT>


<s> return ( CONST_INT_P ( x ) && INT16_P ( INTVAL ( x


<s> bool <ISA_LIT>FrameInfo :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( )


<s> return D ( <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> static bool get<ISA_LIT>StoreDeprecationInfo ( MCInst & MI , const MCSubtargetInfo & STI , std :: string & Info ) { assert ( ! STI . getFeatureBits ( ) [ llvm ::


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( )


<s> Term -> setCondition ( ExtractValueInst :: Create ( Ret , <NUM_LIT> , <STR_LIT> , Term ) ) ; push ( Term -> getSuccessor ( <NUM_LIT> ) , ExtractValueInst :: Create ( Ret , <NUM_LIT> , <STR_LIT> , Term


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt

:: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) {


<s> unsigned tmpReg = GuardsReg ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg ) . addImm ( bitpos ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; InsertedInstrs ++ ; uint32_t or_bitmask = <NUM_LIT> << bitpos ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , PRTmp ) ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; unsigned or_opcode = ( isUInt < <NUM_LIT> > ( or_bitmask


<s> <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TStreamer . emitMachine ( CPUDirectives [ Directive ] ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer -> SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( )


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false ,


<s> case GK_GFX700 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 ; case GK_GFX701 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 ; case GK_GFX702 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 ; case GK_GFX703 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 ; case GK_GFX704 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 ; case GK_GFX801 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 ; case GK_GFX802 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 ; case GK_GFX803 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 ; case GK_GFX810 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 ; case GK_GFX900 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 ; case GK_GFX902 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 ; case GK_GFX904 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 ; case GK_GFX906 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 ; case GK_GFX908 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 ; case GK_GFX909 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX909 ; case GK_GFX1010 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1010 ; case GK_GFX1011 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1011 ; case GK_GFX1012 : return ELF


<s> std :: vector < std :: string > mov_pc ( Bx


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const { const DataLayout * DL = Printer . TM . getDataLayout ( ) ; SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( )


<s> Inst . addOperand ( MCOperand :: createReg ( FCCRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler


<s> rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; if ( aarch64_bti_enabled ( ) ) emit_insn ( gen_bti_c ( ) ) ; reload_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( vcall_offset == <NUM_LIT> ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - <NUM_LIT> ) ) == <NUM_LIT> ) ; addr = this_rtx ; if ( delta != <NUM_LIT> ) { if ( delta >= - <NUM_LIT> && delta < <NUM_LIT> ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - <NUM_LIT> && vcall_offset < <NUM_LIT> * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM


<s> MCI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; MCI . addOperand ( MCOperand :: CreateInst (


<s> _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_EXCEPT_MASK )


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) ,


<s> return new <ISA_LIT>ControlFlowFinalizer


<s> operand = reg_equiv_memory_loc [ REGNO ( operand ) ] ; operand = eliminate_regs ( operand , <NUM_LIT> , NULL_RTX ) ; } if ( GET_CODE ( operand ) != MEM ) return <NUM_LIT> ; operand = XEXP ( operand , <NUM_LIT> ) ; addr_mode = m68hc11_addr_mode | ( reload_completed ? ADDR_STRICT


<s> auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; Optional < unsigned > MaxNumVScale = getMaxVScale ( ) ; assert ( MaxNumVScale && <STR_LIT> ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , <NUM_LIT> , CostKind , I ) ; unsigned MaxNumElementsPerGather = MaxNumVScale . getValue ( ) * LegalVF . getKnownMinValue ( ) ; return LT . first *


<s> static const uint16_t * lookupAVX512 ( unsigned opcode , unsigned domain , ArrayRef < uint16_t [ <NUM_LIT> ] > Table ) { for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : Table ) if ( Row [ domain - <NUM_LIT> ] == opcode

|| ( domain == <NUM_LIT> && Row [ <NUM_LIT> ] == opcode ) ) return Row ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ; ( void


<s> bool <ISA_LIT>Subtarget :: isVGPRSpillingEnabled ( const Function & F


<s> if ( TREE_READONLY ( node ) ) return false ; do node = TREE_TYPE ( node ) ; while ( ARRAY_TYPE == TREE_CODE (


<s> MachineInstr & i = bb . back ( ) ; if ( i . getOpcode ( ) == <STR_LIT> || i . getOpcode ( ) == <STR_LIT> ) { i . eraseFromParent ( ) ; n ++


<s> bool <ISA_LIT>TargetLowering :: shouldScalarizeBinop ( SDValue VecOp ) const { EVT VecVT = VecOp . getValueType


<s> Value * <ISA_LIT>IREmitter :: visitFILD_FLAG ( const


<s> DenseMap < unsigned , unsigned > :: const_iterator I = MLxEntryMap . find ( Opcode ) ; if ( I == MLxEntryMap . end ( ) ) return false ; const <ISA_LIT>_MLxEntry & Entry = <ISA_LIT>_MLxTable


<s> void <ISA_LIT>ConstantIslands :: computeBlockSize ( MachineBasicBlock * MBB ) { BasicBlockInfo & BBI = BBInfo [ MBB -> getNumber ( ) ] ; BBI . Size =


<s> for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( ! <STR_LIT> ( * MI ) ) continue ; if ( ! ( MI -> mayRaiseFPException ( ) || MI -> mayLoadOrStore ( ) ) || isX87ControlInstruction ( * MI ) ) continue ; MachineBasicBlock :: iterator AfterMI = std :: next ( MI ) ; if ( AfterMI != MBB . end ( ) && <STR_LIT> ( * AfterMI ) && ! isX87NonWaitingControlInstruction ( * AfterMI ) ) continue ; BuildMI ( MBB , AfterMI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; ++ MI ; Changed =


<s> unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg ( ) != IdxReg ) { OptOk = false ; break ; } } if ( ! OptOk ) continue ; for ( -- PrevI ; PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ; -- PrevI ) ; MachineInstr * LeaMI = PrevI ; if ( ( LeaMI -> getOpcode ( ) != <STR_LIT> && LeaMI -> getOpcode ( ) != <STR_LIT> ) || LeaMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) OptOk = false ; if ( ! OptOk ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> << * AddrMI << <STR_LIT> << * LeaMI ) ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewJTMI = BuildMI ( MBB , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( MI -> getOperand ( JTOpIdx + <NUM_LIT> ) . getImm ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << * NewJTMI ) ; unsigned NewSize = TII ->


<s> int NumOps = getNumMemOps ( cast < IntrinsicInst > ( I )


<s> if ( Subtarget . isDarwinABI ( ) ) return nullptr ; if ( ! TM . is<ISA_LIT>64 ( ) ) return nullptr ; if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: CXX_FAST_TLS ) return nullptr ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return nullptr ; bool SaveR2 = ! getReservedRegs ( * MF ) . test ( <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList : CSR_SVR464_Altivec_ViaCopy_SaveList ; else return SaveR2 ?


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask ,


<s> SDLoc DL ( N ) ; SDValue Data = N -> getOperand ( <NUM_LIT> ) ; EVT DataVT = Data . getValueType ( ) ; EVT HwSrcVt = getSVEContainerType ( DataVT ) ; SDValue InputVT = DAG . getValueType ( DataVT ) ; if ( DataVT == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( DataVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDValue SrcNew ; if ( Data . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SrcNew , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , InputVT } ; return DAG . getNode ( <STR_LIT> , DL , N


<s> else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , <STR_LIT> + FuncName ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ; return SDValue


<s> if ( ! TLI . isTypeLegal ( VT ) || ! TLI . isTypeLegal ( Concat0Op1 . getValueType ( ) ) || ! TLI . isTypeLegal ( Concat1Op1 . getValueType ( ) ) ) return SDValue ( ) ; SDValue NewConcat = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > NewMask ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned HalfElts = NumElts / <NUM_LIT> ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned n = <NUM_LIT> ; n < NumElts ; ++ n ) { int MaskElt = SVN -> getMaskElt ( n ) ; int NewElt =


<s> if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm

( MI -> getOperand ( <NUM_LIT> ) ) ) ) {


<s> SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType (


<s> if ( getFlags ( ) & MCSection<ISA_LIT>


<s> static void s300_set_up_by_prologue ( hard_reg_set_container * regs ) { if ( cfun -> machine -> base_reg && ! call_used_regs [ REGNO ( cfun -> machine -> base_reg ) ] ) SET_HARD_REG_BIT ( regs

-> set , REGNO ( cfun -> machine -> base_reg ) ) ;


<s> } if ( const NamedMDNode * Named = M . getNamedMetadata ( <STR_LIT> ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const auto * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != <NUM_LIT> ) continue ; const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; const MDString * Contents = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; if ( ! Name || ! Contents ) continue ; OutStreamer -> PushSection ( ) ; std :: string SectionName = ( <STR_LIT> + Name -> getString ( ) ) . str ( ) ; MCSectionWasm * MySection = OutContext . getWasmSection ( SectionName , SectionKind ::


<s> Value * <ISA_LIT>InstrSema :: translatePop ( unsigned OpSize ) { Value * OldSP = getReg ( <STR_LIT> ) ; Type * OpTy = IntegerType :: get ( * Ctx , OpSize * <NUM_LIT> ) ; Value * OpSizeVal = ConstantInt :: get ( IntegerType :: get ( * Ctx , OldSP -> getType ( ) ->


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetGlobalAddressSymbol ( const MachineOperand & MO ) const { assert ( ! MO . getTargetFlags ( ) && <STR_LIT> ) ; return AsmPrinter . getSymbol ( MO


<s> static DecodeStatus DecodeSORegImmOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift =


<s> return __builtin_mve_vrev32q_sv16qi ( __a )


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI ) const { if ( MI . mayStore ( ) && ! Subtarget . useNewValueStores ( ) ) return false ; const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> )


<s> if ( Subtarget -> hasInt256 ( ) && ( Bits == <NUM_LIT> || Bits == <NUM_LIT> ) ) return false ; return


<s> EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned InsNumElts = InsVT . getVectorNumElements ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDLoc SL ( Op ) ; for ( unsigned I = <NUM_LIT> ; I != InsNumElts ; ++ I ) { SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Ins , DAG . getConstant ( I , SL , <STR_LIT> ) ) ; Vec = DAG . getNode ( <STR_LIT> , SL , VecVT , Vec , Elt , DAG . getConstant ( IdxVal + I ,


<s> using MISet = std :: set < MachineInstr * > ; const TargetRegisterClass * IntRC = & <STR_LIT> ; bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Part , * TRI ) ; dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DR , TRI ) << <STR_LIT> << PrintReg ( HiR , TRI ) << ':' << PrintReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent ( ) ; B -> erase ( MI ) ; } return Changed


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( SelectDirectAddr ( Addr . getOperand ( <NUM_LIT> ) , Addr ) ) { return false ; } if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) )

) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , mvt ) ;


<s> const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , Width ) ; if ( ! BaseOp || ! BaseOp -> isReg ( ) )


<s> for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize (


<s> int nregs ; if ( arg . mode == BLKmode && arg . type ) size = int_size_in_bytes ( arg . type ) ; else size = GET_MODE_SIZE ( arg . mode ) . to_constant ( ) ; if ( arg . aggregate_type_p ( ) ) size = int_size_in_bytes ( arg . type ) ; if ( size < <NUM_LIT>


<s> static MCDisassembler :: DecodeStatus DecodeBranchTargetS21 ( MCInst & Inst , unsigned S , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( S


<s> Chain , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VT . getStoreSize ( ) , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , VT , MMO ) ; } case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( const ConstantFPSDNode * K = dyn_cast < ConstantFPSDNode > ( Src ) ) { if ( ! K -> isNegative ( ) ) return Chain ; SDValue NegOne = DAG . getTargetConstant ( FloatToBits ( - <NUM_LIT> ) , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ,


<s> if ( ! isLoadStoreTypeLegal ( I -> getType ( ) , VT ) || cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; Address Addr ; if ( ! ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! EmitLoad ( VT , ResultReg , Addr ) ) return false ; UpdateValueMap ( I ,


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; int BccOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; } BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; BuildMI ( & MBB , dl , get ( BOpc


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>FastEmitExtend ( <STR_LIT> Opc , EVT DstVT , unsigned Src , EVT SrcVT , unsigned & ResultReg ) { unsigned RR = fastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src , false ) ; if ( RR == <NUM_LIT> )


<s> bool <ISA_LIT>16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFOffset ( SDValue Addr , SDValue & SRsrc , SDValue

& Soffset , SDValue & Offset , SDValue & SLC ) const {


<s> BB -> updateTerminator ( ) ; MF . RenumberBlocks ( ) ; ++ NumJTMoved ; return NULL ; } MachineBasicBlock * NewBB = MF . CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF . insert ( MBBI , NewBB ) ; assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) ; MF . RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> removeSuccessor ( BB ) ; JTBB -> addSuccessor ( NewBB ) ; ++ NumJTInserted


<s> emit_insn ( gen_rtx_SET ( gen_rtx_REG ( BImode , SR_F_REGNUM ) , gen_rtx_fmt_ee ( code , BImode , a


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; IsThumb = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF


<s> bool isVecListFourQWordIndexed ( ) const { if ( ! isDoubleSpacedVectorIndexed ( ) ) return


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target32 ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y (


<s> MachineFunctionPass ( ID ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( tm . getInstrInfo ( ) ) ) , TRI ( TII ->


<s> FunctionPass * llvm :: create<ISA_LIT>TLSDynamicCallPass


<s> DAG -> addMutation ( make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG ->


<s> if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FP ) . addImm ( <NUM_LIT> ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> && <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Tmp ) ; BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MI -> eraseFromParent (


<s> if ( insn . mode == MODE_64BIT ) baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; else if ( insn . mode == MODE_32BIT ) baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; else { assert ( insn . mode == MODE_16BIT ) ; baseRegNo = insn . prefixPresent [ <NUM_LIT> ] ? <STR_LIT> : <STR_LIT> ; } MCOperand baseReg = MCOperand :: CreateReg (


<s> bool hasExtXfauxquarter ( ) const { return HasExtXfauxquarter


<s> int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> if ( TARGET_AVX512ER ) { emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP28 ) ) ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_MULT ( mode , a , x0 ) ) ) ; return ; } else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP14 ) ) ) ; } else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , e0 )


<s> int pa_is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , <NUM_LIT> ) , VOIDmode )

&& GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ;


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_LONGJMP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> static bool IsComment ( MachineInstr * I ) { return I -> getNumOperands ( ) == <NUM_LIT> && I ->

getOperand ( <NUM_LIT> ) . isMetadata ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned BrOpc = Cond [ <NUM_LIT> ] . getImm (


<s> if ( ! FixupBWInsts ) return false ; this -> MF = & MF ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; OptForSize = MF . getFunction ( ) -> optForSize ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( auto & MBB : MF ) processBasicBlock ( MF , MBB ) ; DEBUG ( dbgs ( )


<s> unsigned BlackfinIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { return <NUM_LIT>


<s> if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT VecVT = EVT :: getEVT ( VecTy ) ; if ( ! VecVT . isSimple ( ) || VecVT

. getSizeInBits ( ) <= <NUM_LIT> ) return false ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned GPRSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; unsigned NumRegs = LastReg - FirstReg ; unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) , ABI . StackAddrSpace ( ) ) ; int FI = MFI . CreateFixedObject ( FrameObjSize , FrameObjOffset , false


<s> bool IsShuf0 = getTargetShuffleInputs ( BC0 , Ops0 , Mask0 , DAG ) && ! isAnyZero ( Mask0 ) && scaleShuffleElements ( Mask0 , <NUM_LIT> , ScaledMask0 ) && all_of ( Ops0 , [ ] ( SDValue Op ) { return Op . getValueSizeInBits ( ) == <NUM_LIT> ; } ) ; bool IsShuf1 = getTargetShuffleInputs ( BC1 , Ops1 , Mask1 , DAG ) && ! isAnyZero ( Mask1 ) && scaleShuffleElements ( Mask1 , <NUM_LIT> , ScaledMask1 ) && all_of ( Ops1 , [ ] ( SDValue Op ) { return Op . getValueSizeInBits ( ) == <NUM_LIT> ; } ) ; if ( IsShuf0 || IsShuf1 ) { if ( ! IsShuf0 ) { Ops0 . assign ( { BC0 } ) ; ScaledMask0 . assign ( { <NUM_LIT> , <NUM_LIT> } ) ; } if ( ! IsShuf1 ) { Ops1 . assign ( { BC1 } ) ; ScaledMask1 . assign ( { <NUM_LIT> , <NUM_LIT> } ) ; } SDValue LHS , RHS ; int PostShuffle [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; auto FindShuffleOpAndIdx = [ & ] ( int M , int & Idx , ArrayRef < SDValue > Ops ) { if ( M < <NUM_LIT> ) return true ; Idx = M % <NUM_LIT> ; SDValue Src = Ops [ M / <NUM_LIT> ] ; if ( ! LHS || LHS == Src ) { LHS = Src ; return true ; } if ( ! RHS || RHS == Src ) { Idx += <NUM_LIT> ; RHS = Src ; return true ; } return false ; } ; if ( FindShuffleOpAndIdx ( ScaledMask0 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops0 ) && FindShuffleOpAndIdx ( ScaledMask0 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops0 ) && FindShuffleOpAndIdx ( ScaledMask1 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops1 ) && FindShuffleOpAndIdx ( ScaledMask1 [ <NUM_LIT> ] , PostShuffle [ <NUM_LIT> ] , Ops1 ) ) { LHS = DAG . getBitcast ( SrcVT , LHS ) ; RHS = DAG . getBitcast ( SrcVT , RHS ? RHS : LHS ) ; MVT ShufVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Res = DAG . getNode ( Opcode , DL , VT , LHS , RHS ) ; Res = DAG . getBitcast ( ShufVT , Res ) ; Res = DAG . getVectorShuffle ( ShufVT , DL , Res , Res , PostShuffle ) ; return DAG . getBitcast ( VT , Res ) ; } } } if ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) { SmallVector < int > Mask0 , Mask1 ; SmallVector < SDValue > Ops0 , Ops1 ; SmallVector < int , <NUM_LIT>


<s> return N0 -> hasOneUse ( ) && N1 -> hasOneUse ( ) && isZeroExtended ( N0 , DAG ) && isZeroExtended ( N1 , DAG ) ; } return


<s> static DecodeStatus decodeGPRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > (

LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ;


<s> { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = const_double_from_real_value ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; } case IA64_BUILTIN_FABSQ : case IA64_BUILTIN_COPYSIGNQ


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > ( Imm


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , TII , dl , * this , - NumBytes ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; } AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize


<s> static SDValue LowerREADCYCLECOUNTER ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SmallVector < SDValue , <NUM_LIT> > Results ; SDLoc DL ( Op ) ; getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case X86_DIRFLAG : return mode ; case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn )


<s> const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) .

addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ;


<s> resetSubtargetFeatures ( CPU , FS ) ; return *


<s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT


<s> insn = NEXT_INSN ( insn ) ; if ( insn == <NUM_LIT> || ! NOTE_P ( insn ) ) break ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) return NULL ; } return insn


<s> auto CreateLoad = [ & DAG , & DL , & Loads ] ( EVT VT , LoadSDNode * LDBase ) { auto MMOFlags = LDBase -> getMemOperand ( ) -> getFlags ( ) ; assert ( ! ( MMOFlags & MachineMemOperand :: MOVolatile ) && <STR_LIT> ) ; SDValue NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , MMOFlags ) ; for ( auto * LD : Loads ) DAG . makeEquivalentMemoryOrdering ( LD , NewLd ) ; return NewLd ; } ; if ( FirstLoadedElt == <NUM_LIT> && LastLoadedElt == ( int ) ( NumElems - <NUM_LIT> ) && ( IsConsecutiveLoad || IsConsecutiveLoadWithZeros ) ) { assert ( LDBase && <STR_LIT> ) ; EVT EltVT = LDBase -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != EltVT . getSizeInBits ( ) * NumElems ) return SDValue ( ) ; if ( isAfterLegalize && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; if ( LDBase -> isNonTemporal ( ) && LDBase -> getAlignment ( ) >= <NUM_LIT> && VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return SDValue ( ) ; if ( IsConsecutiveLoad ) return CreateLoad ( VT , LDBase ) ; if ( ! isAfterLegalize && NumElems == VT . getVectorNumElements ( ) ) { SmallVector < int , <NUM_LIT> > ClearMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { if ( ZeroMask [ i ] ) ClearMask [ i ] = i + NumElems ; else if ( LoadMask [ i ] ) ClearMask [ i ] = i ; } SDValue V = CreateLoad ( VT , LDBase ) ; SDValue Z = VT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , DL , VT ) : DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getVectorShuffle ( VT , DL , V , Z , ClearMask ) ; } } int LoadSize = ( <NUM_LIT> + LastLoadedElt - FirstLoadedElt ) * LDBaseVT . getStoreSizeInBits ( ) ; if ( IsConsecutiveLoad && FirstLoadedElt == <NUM_LIT> && ( LoadSize == <NUM_LIT> || LoadSize == <NUM_LIT> ) && ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) || VT . is512BitVector ( ) ) ) ) { MVT VecSVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( LoadSize ) : <STR_LIT> ( LoadSize ) ; MVT VecVT = <STR_LIT> ( VecSVT , VT . getSizeInBits ( ) / LoadSize ) ; if ( TLI . isTypeLegal


<s> const <ISA_LIT>Z80TargetLowering * getTargetLowering ( ) const override


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { return


<s> vmla_n_f32 ( float32x2_t a , float32x2_t b , float32_t c ) { float32x2_t result ; float32x2_t t1 ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) , <STR_LIT> ( t1 ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result


<s> return ( uint8x16_t ) __builtin_neon_vqsubuv16qi ( ( int8x16_t )


<s> unsigned CallOpc = PrepareCall ( DAG , Callee , InFlag , Chain , CallSeqStart , dl , SPDiff , isTailCall , isPatchPoint , hasNest , RegsToPass , Ops , NodeTys , CS , Subtarget ) ; if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! isPatchPoint ) { if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( ( CallOpc == <STR_LIT> ) && ( ! isLocalCall ( Callee ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) CallOpc = <STR_LIT> ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( BytesCalleePops


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , bool * Fast ) const { if ( Disable<ISA_LIT>Unaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) return false ; if ( VT == <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return


<s> static reg_class_t mmix_preferred_reload_class ( rtx x , reg_class_t rclass ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ?


<s> if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; if ( BranchRelaxation ) addPass (


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) )


<s> case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std


<s> if ( Src == <STR_LIT> ) return Dest == <STR_LIT> || Dest == <STR_LIT> ; return Src == <STR_LIT> && Dest


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand ::

MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntrinsicEXT ( N , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case


<s> std :: string OriginalName ; raw_string_ostream OriginalNameStream ( OriginalName ) ; Sym -> print ( OriginalNameStream ) ; OriginalNameStream . flush ( ) ; std :: string CleanName ; raw_string_ostream CleanNameStream ( CleanName ) ; for ( unsigned I = <NUM_LIT> , E = OriginalName . size ( ) ; I != E ; ++ I ) { char C = OriginalName [ I ] ; if ( C == '.' ) { CleanNameStream << <STR_LIT> ; } else if ( C == '@'


<s> return ( __m256 ) __builtin_ia32_addps256_mask ( ( __v8sf ) __A , ( __v8sf )


<s> auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject (


<s> Func = & F ; return ProcessFunction (


<s> bool ix86_hardreg_mov_ok ( rtx dst , rtx src ) { if ( REG_P ( dst ) && HARD_REGISTER_P ( dst ) && ! REG_P ( src ) && ! MEM_P ( src ) && ! x86_64_immediate_operand ( src , GET_MODE ( dst ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS (

REGNO ( dst ) ) ) && ! reload_completed ) return false ;


<s> Value |= ( ( insn & <NUM_LIT> ) << <NUM_LIT> ) ; MI . setOpcode ( <STR_LIT> ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , Value


<s> unsigned RetOpc = RetI ? RetI -> getOpcode ( ) : <NUM_LIT> ; if ( RetOpc == <STR_LIT> ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( <STR_LIT> ) ; return ; } if ( RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> || RetOpc == <STR_LIT> ) { MachineBasicBlock :: iterator It = RetI ; ++ It ; while ( It != MBB . end ( ) ) { if ( ! It -> isLabel ( ) ) It = MBB . erase ( It ) ; else ++ It ; } return ; } bool NeedsDeallocframe = true ; if ( ! MBB . empty ( ) && InsertPt != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevIt = std :: prev ( InsertPt ) ; unsigned COpc = PrevIt -> getOpcode ( ) ; if ( COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> || COpc == <STR_LIT> ) NeedsDeallocframe = false ; } if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isEnvironmentMusl ( ) || ! MF . getFunction ( ) . isVarArg ( ) ) { if ( ! NeedsDeallocframe ) return ; if ( RetOpc != <STR_LIT> || DisableDeallocRet ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } unsigned NewOpc = <STR_LIT> ; MachineInstr * NewI = BuildMI ( MBB , RetI , dl , HII . get ( NewOpc ) ) . addDef ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; NewI -> copyImplicitOps ( MF , * RetI ) ; MBB . erase ( RetI ) ; } else { int NumVarArgRegs = <NUM_LIT> - FirstVarArgSavedReg ; int RegisterSavedAreaSizePlusPadding = ( NumVarArgRegs % <NUM_LIT> == <NUM_LIT> ) ? ( NumVarArgRegs * <NUM_LIT> ) : ( NumVarArgRegs * <NUM_LIT> + <NUM_LIT> ) ; MachineBasicBlock :: iterator Term = MBB


<s> void recordReplacement ( int OFI , int NFI ) { FIReplacements . insert ( std :: make_pair


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; X -> InitMCCodeGenInfo ( RM ,


<s> O << ( unsigned ) MI -> getOperand ( OpNo


<s> if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; } if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> ) return DAG . getConstant


<s> llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> else cum -> nbytes += ( ( ( arg . type && int_size_in_bytes ( arg . type ) > <NUM_LIT> ? GET_MODE_SIZE ( Pmode ) :

( HOST_WIDE_INT ) arg . promoted_size_in_bytes ( ) ) + UNITS_PER_WORD - <NUM_LIT> ) & - UNITS_PER_WORD ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( RC == <STR_LIT>


<s> bool <ISA_LIT>EarlyIfConversion :: visitBlock ( MachineBasicBlock * B , MachineLoop * L ) { bool Changed = false ; MachineDomTreeNode * N = MDT -> getNode ( B ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) !=


<s> bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Changed |= ST . makeLIDRangeMetadata ( CI ) ; } return


<s> MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr ::


<s> bool <ISA_LIT>TargetLowering :: areJTsAllowed ( const Function


<s> assert ( Ty . isScalableVector ( ) && <STR_LIT> ) ; Optional < unsigned > PredPattern ; if ( Ty . isScalableVector ( ) && IdxVal < <NUM_LIT> && ( PredPattern = getSVEPredPatternFromNumElements ( std :: abs ( IdxVal ) ) ) != None ) { SDLoc DL ( Op ) ; EVT PredVT = Ty . changeVectorElementType ( <STR_LIT> ) ; SDValue Pred = getPTrue ( DAG , DL , PredVT , * PredPattern ) ; Pred = DAG . getNode ( <STR_LIT> , DL , PredVT , Pred ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Pred , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } if ( IdxVal >= <NUM_LIT> && IdxVal < int64_t ( <NUM_LIT> / Ty . getVectorElementType ( ) . getSizeInBits


<s> static void single_move_for_strmov ( rtx dst , rtx src , enum machine_mode mode , HOST_WIDE_INT offset ) { rtx scratch = gen_reg_rtx ( mode ) ; rtx srcmem , dstmem ; srcmem = adjust_address_nv ( src , mode , offset ) ; dstmem = adjust_address_nv ( dst , mode , offset


<s> if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; else if ( REG_FUNCTION_VALUE_P ( DF_REF_REG ( mention ) ) ) insn_entry [ uid ] . is_live_out = <NUM_LIT> ; union_uses ( insn_entry , insn , mention ) ; } } if ( insn_entry [ uid ] . is_relevant ) { insn_entry [ uid ] . is_load = insn_is_load_p ( insn ) ; insn_entry [ uid ] . is_store = insn_is_store_p ( insn ) ; if ( insn_is_swap_p ( insn ) ) insn_entry [ uid ] . is_swap = <NUM_LIT> ; else { unsigned int special = SH_NONE ; insn_entry [ uid ] . is_swappable = insn_is_swappable_p ( insn_entry , insn , & special ) ; if ( special != SH_NONE && insn_entry [ uid ] . contains_subreg ) insn_entry [ uid ] . is_swappable = <NUM_LIT> ; else if ( special != SH_NONE ) insn_entry [


<s> getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0 } ) ; computeTables ( ) ; verify ( * ST . getInstrInfo ( )


<s> Register ScratchExecCopy ; if ( FuncInfo -> SGPRForFPSaveRestoreCopy ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FuncInfo -> SGPRForFPSaveRestoreCopy ) . addReg ( FramePtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineBasicBlock & MBB : MF ) MBB . addLiveIn ( FuncInfo -> SGPRForFPSaveRestoreCopy ) ; } for ( const <ISA_LIT>MachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; if ( ! ScratchExecCopy ) { if ( LiveRegs . empty ( ) ) { LiveRegs . init ( TRI ) ; LiveRegs . addLiveIns ( MBB ) ; if ( FuncInfo -> SGPRForFPSaveRestoreCopy ) LiveRegs . removeReg ( FuncInfo -> SGPRForFPSaveRestoreCopy ) ; } ScratchExecCopy = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , * TRI . getWaveMaskRegClass ( ) ) ; assert ( FuncInfo -> SGPRForFPSaveRestoreCopy != ScratchExecCopy ) ; const unsigned OrSaveExec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( OrSaveExec ) , ScratchExecCopy ) . addImm ( - <NUM_LIT> ) ; } buildPrologSpill ( LiveRegs , MBB , MBBI , TII , Reg . VGPR , FuncInfo -> getScratchRSrcReg ( ) , StackPtrReg , Reg . FI . getValue ( ) ) ; } if ( ScratchExecCopy != <STR_LIT> ) { unsigned ExecMov = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; MCRegister Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( ExecMov ) , Exec ) . addReg ( ScratchExecCopy , RegState :: Kill ) ; LiveRegs . addReg ( ScratchExecCopy ) ; } if ( FuncInfo -> FramePointerSaveIndex ) { const int FI = FuncInfo -> FramePointerSaveIndex . getValue (


<s> DebugLoc dl = Op . getDebugLoc ( ) ; MVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] =


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MII , unsigned SrcReg , bool isKill ,

int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState ::


<s> ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > <NUM_LIT> && ninsns <= <NUM_LIT> && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 ) ) return <NUM_LIT> ; else return


<s> MachineOperand oper = Instr -> getOperand ( i ) ; if ( ! oper . isReg ( ) ) continue ; if ( ! oper . isDef ( ) ) continue ; def = i ; numDefs ++ ; } assert ( ( numDefs <= <NUM_LIT> ) && <STR_LIT> ) ; if ( numDefs == <NUM_LIT> ) { unsigned regnum = Instr -> getOperand ( def ) . getReg ( ) ; if ( ISVECEXTRACT ( Instr ) ) regnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return get<ISA_LIT>VectorSize ( MRI -> getRegClass ( regnum ) ) ; } else if ( numDefs == <NUM_LIT> ) { assert ( ISVECSTORE ( Instr


<s> if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstHi = HRI . getSubReg ( DstR , <STR_LIT> ) ; Register DstLo = HRI . getSubReg ( DstR , <STR_LIT> ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg

( SrcReg , getKillRegState ( isKill ) ) ;


<s> return Ty . getSimpleVT ( ) ; } return <STR_LIT> ( DL .


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Changed


<s> SMLoc Start = Lex ( ) . getLoc ( ) ; ID = getTok ( ) . getString ( ) ; if ( ! isParsingMSInlineAsm ( ) ) { if ( ( getTok ( ) . isNot ( AsmToken :: Identifier ) && getTok ( ) . isNot ( AsmToken :: String ) ) ||

getParser ( ) . parsePrimaryExpr ( Val , End , nullptr ) ) return Error ( Start , <STR_LIT> ) ;


<s> void addRegListOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ;

I != E ; ++ I ) Inst . addOperand ( MCOperand :: CreateReg ( * I ) ) ;


<s> fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; mips_start_function_definition ( fnname , TARGET_MIPS16 ) ; if ( ! flag_inhibit_size_directive ) { const struct mips_frame_info * frame ; frame = & cfun -> machine -> frame ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , reg_names [ frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ] , ( frame_pointer_needed ? frame -> total_size - frame -> hard_frame_pointer_offset : frame -> total_size ) , reg_names [ RETURN_ADDR_REGNUM ] , frame -> var_size , frame -> num_gp , frame -> num_fp , frame -> args_size , frame -> cprestore_size ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , frame -> mask , frame -> gp_save_offset ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , frame -> fmask , frame -> fp_save_offset ) ; } if ( mips_must_initialize_gp_p ( ) && mips_current_loadgp_style ( ) == LOADGP_OLDABI ) { if ( TARGET_MIPS16 ) { output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { mips_push_asm_switch ( & mips_noreorder ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; if ( ! cfun -> machine -> all_noreorder_p ) mips_pop_asm_switch ( & mips_noreorder ) ; else mips_push_asm_switch ( & mips_nomacro ) ; } } else if ( cfun -> machine -> all_noreorder_p ) { mips_push_asm_switch ( & mips_noreorder ) ; mips_push_asm_switch ( & mips_nomacro )


<s> ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , getPointerTy ( ) , CP -> getAlignment ( ) , CP -> getOffset ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( )


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << TRI -> getAsmName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum ) ; return false ; case 'P' : printOperand ( MI , OpNum


<s> emit_insn ( gen_lshrsi3 ( tmp2 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; tmp3 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_xorsi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp4 , tmp3 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorsi3 ( tmp , tmp3 , tmp4 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_andsi3 ( dst , tmp , const1_rtx ) ) ; } else { if ( rs6000_cost -> muldi >= COSTS_N_INSNS ( <NUM_LIT> ) ) { rtx tmp1 , tmp2 , tmp3 , tmp4 , tmp5 , tmp6 ; tmp1 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_popcntbdi2 ( tmp1 , src ) ) ; tmp2 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp2 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; tmp3 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp4 , tmp3 , GEN_INT ( <NUM_LIT> ) ) ) ; tmp5 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp5 , tmp3 , tmp4 ) ) ; tmp6 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp6 , tmp5 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xordi3 ( tmp , tmp5 , tmp6 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_anddi3 ( dst , tmp , const1_rtx )


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; emitDemotedVars ( & MF -> getFunction (


<s> bool hasAnyFloatExt ( ) const { return hasFPUv2


<s> int named_parm_regs , anon_parm_regs ; named_parm_regs = ( ROUND_REG ( * ca , mode ) + ( mode == BLKmode ? ROUND_ADVANCE ( int_size_in_bytes (

type ) ) : ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) ) ) ;


<s> int n_patterns = d -> perm . encoding ( ) . npatterns ( ) ; poly_int64 vec_len = d -> perm . length ( ) ; for ( int i = <NUM_LIT> ; i < n_patterns ; ++ i ) if ( ! known_eq ( d -> perm [ i ] , i ) && ! known_eq ( d -> perm [ i ] , vec_len + i ) ) return false ; for ( int i = n_patterns ; i < n_patterns * <NUM_LIT> ; i ++ ) if ( ! d -> perm . series_p ( i , n_patterns , i , n_patterns ) && ! d -> perm . series_p ( i , n_patterns , vec_len + i , n_patterns ) ) return false ; if ( d -> testing_p ) return true ; machine_mode pred_mode = aarch64_sve_pred_mode ( vmode ) ; rtx_vector_builder builder ( pred_mode , n_patterns , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < n_patterns * <NUM_LIT> ; i ++ ) { rtx elem = known_eq ( d -> perm [ i ] , i ) ? CONST1_RTX ( BImode ) : CONST0_RTX ( BImode ) ; builder . quick_push ( elem ) ; } rtx const_vec = builder . build


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { return CI -> isTailCall ( )


<s> if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger (


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> float res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( fg )

, <STR_LIT> ( fh ) , <STR_LIT> ( fq ) ) ;


<s> MCAsmParser & getParser ( ) const { return Parser


<s> SDValue SrcReg = Op . getOperand ( <NUM_LIT> ) ; SDValue ZeroUndef = LowerCTTZ_ZERO_UNDEF ( Op , DAG ) ; SDValue CC = DAG . getCondCode ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SrcReg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , DAG . getConstant ( VT . getSizeInBits

( ) , dl , <STR_LIT> ) , ZeroUndef , CC ) ;


<s> RegisterTarget < Triple :: arc > X ( getThe<ISA_LIT>Target (

) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> return new <ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move (


<s> default : break ; case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) return DCI . CombineTo ( N , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; if ( ! ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) || ! Op0 . getNode ( ) -> hasOneUse ( ) ) break ; SDValue NewSplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; SDValue Lo = NewSplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = NewSplitF64 . getValue ( <NUM_LIT> ) ; APInt SignBit = APInt :: getSignMask ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } assert ( Op0 . getOpcode ( ) == <STR_LIT> ) ; SDValue NewHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( ~ SignBit , DL , <STR_LIT> ) ) ; return DCI . CombineTo ( N , Lo , NewHi ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned GCNRegPressure :: getRegKind ( unsigned Reg , const MachineRegisterInfo & MRI ) { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; const auto RC = MRI . getRegClass ( Reg ) ; auto STI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI .


<s> for ( MachineBasicBlock & MBB : MF ) OutOffset [ & MBB ] = INT32_MAX ; ReversePostOrderTraversal < MachineFunction * > RPO ( & MF ) ; for ( MachineBasicBlock * MBB : RPO ) { int64_t Offset = - <NUM_LIT> ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) Offset = std :: max ( Offset , OutOffset [ Pred ] ) ; if ( Offset == - <NUM_LIT> ) Offset = INT32_MAX ; for ( MachineInstr & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { int64_t Amount = getWinAllocaAmount ( & MI , MRI ) ; Lowering L = getLowering ( Offset , Amount ) ; Lowerings [ & MI ] = L ; switch ( L ) { case Sub : Offset += Amount ; break ; case TouchAndSub : Offset = Amount ; break ; case Probe : Offset = <NUM_LIT> ; break ; } } else if ( MI . isCall ( ) || isPushPop ( MI ) ) { Offset =


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( Op2 . isReg ( ) && ( Op2 . getReg ( ) == <STR_LIT> || TargetRegisterInfo :: isPhysicalRegister ( Op2 . getReg ( ) ) ) ) ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Ops ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) ) { Op = & Op1 ; } else if ( Op1 . isFI ( )


<s> static DecodeStatus DecodeVRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t

Address , const MCDisassembler * Decoder ) {


<s> } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , <NUM_LIT> ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; rtx pcvr1 = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_pcvr1 ( pcvr1 , tmp ) ) ; rtx sub_target = simplify_gen_subreg ( V16QImode , target , mode , <NUM_LIT> ) ; rtx perm1 = gen_altivec_vperm_v8hiv16qi ( sub_target , sub_target , sub_target , pcvr1 ) ; emit_insn ( perm1 ) ; rs6000_expand_vector_set ( target , val , const0_rtx ) ; rtx pcvr2 = gen_reg_rtx


<s> assert ( CI . Width >= <NUM_LIT> && CI . Width <= <NUM_LIT> ) ; assert ( Paired . Width >= <NUM_LIT> && Paired . Width <= <NUM_LIT> ) ; if ( Paired < CI ) { Idx1 = Idxs [ <NUM_LIT> ] [ Paired . Width - <NUM_LIT> ] ; Idx0 = Idxs [ Paired . Width ] [ CI . Width - <NUM_LIT> ] ; } else { Idx0 = Idxs [ <NUM_LIT> ] [ CI . Width -


<s> static SDValue getTruncateOrZeroExtend ( SDValue V , SelectionDAG & DAG , MVT ToVT ) { SDNodeTreeBuilder b ( V , & DAG ) ; MVT VT = V . getSimpleValueType


<s> unsigned <ISA_LIT>16InstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL


<s> if ( ! FirstElt ) return false ; EVT VT = Bvec -> getValueType ( <NUM_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) if ( dyn_cast < ConstantSDNode > ( Bvec -> getOperand ( i ) ) != FirstElt ) return false ; ConstVal = FirstElt -> getZExtValue ( ) ; return


<s> if ( TARGET_ZARCH && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) == INTVAL ( op ) && s390_single_part ( op , word_mode , HImode , <NUM_LIT> ) >= <NUM_LIT> ) return true ; if ( TARGET_EXTIMM && GET_CODE ( op ) == CONST_INT && trunc_int_for_mode ( INTVAL ( op ) , word_mode ) ==

INTVAL ( op ) && s390_single_part ( op , word_mode , SImode , <NUM_LIT> ) >= <NUM_LIT> ) return true ;


<s> static bool isSource ( Value * V ) { if ( ! isa < IntegerType > ( V -> getType ( ) ) ) return false ; if ( isa < Argument > ( V ) ) return true ; else if ( isa < LoadInst >


<s> return ( __m128i ) __builtin_ia32_extracti64x2_256_mask ( ( __v4di ) __A , __imm , ( __v2di ) _mm_setzero_di ( ) ,


<s> if ( can_create_pseudo && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode ,


<s> switch ( MO . getType ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand ::


<s> if ( optimize > <NUM_LIT> && selected_cpu -> tune -> max_case_values != <NUM_LIT> ) return selected_cpu -> tune


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expand_SELECTCC ( MF , MBBI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return