<s> Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { unsigned NumOps = LoadMI -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i )

MOs . push_back ( LoadMI -> getOperand ( i ) ) ;


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return createWinCOFFStreamer ( Ctx , MAB , * _Emitter , _OS , RelaxAll ) ; return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll


<s> MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , <NUM_LIT> > WorkList ( <NUM_LIT> , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode (


<s> bool changed = false ; if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSinglePath ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getFunction ( ) . getName ( ) << <STR_LIT> ) ; doReduceFunction ( MF )


<s> TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter


<s> bool mep_return_in_memory ( const_tree type , const_tree decl ATTRIBUTE_UNUSED ) { int size = bytesize ( type


<s> case <STR_LIT> : Streamer . EmitRawText ( StringRef ( <STR_LIT> ) + String . lower ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Streamer . EmitRawText ( StringRef ( <STR_LIT> ) + String .


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if (


<s> void <ISA_LIT>LoadStoreOptimizer :: updateBaseAndOffset ( MachineInstr & MI , Register NewBase , int32_t NewOffset ) const { auto Base = TII -> getNamedOperand ( MI ,


<s> unsigned AccessSize = <NUM_LIT> ; OffsetIsScalable = false ; const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ; if ( ! BaseOp || ! BaseOp -> isReg


<s> void AMDGPURegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned

FIOperandNum , RegScavenger * RS ) const {


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrMode3OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( <STR_LIT> ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; return ( Rn << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm = MO2 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO1 . getReg ( ) == <NUM_LIT> ; uint32_t Imm8 = <STR_LIT> ( Imm ) ; if ( ! isImm ) Imm8 = CTX . getRegisterInfo ( ) . getEncodingValue ( MO1 . getReg ( ) ) ; return ( Rn << <NUM_LIT> ) | Imm8 | ( isAdd << <NUM_LIT> )


<s> void addModImmNotOperands ( MCInst & Inst , unsigned N ) const { assert ( N ==


<s> unsigned Align = TFI -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm


<s> bool dumpCode ( ) const { return DumpCode


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return


<s> XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( Pmode ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx dwarf ; rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , reg ) ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( Pmode ) ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) { insn = emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( layout . locals_size ) { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( layout . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( frame_pointer_needed && layout . sp_minus_fp


<s> case <STR_LIT> : \ return <STR_LIT> ; case <STR_LIT> : \ case <STR_LIT> : \


<s> bool <ISA_LIT>CallLowering :: isTypeIsValidForThisReturn ( EVT Ty ) const { return Ty . getSizeInBits (


<s> emit_move_insn ( reg , offset_rtx ) ; emit_insn ( gen_addsi3 ( reg , reg , stack_pointer_rtx ) ) ; return reg


<s> unsigned PredDefs = <NUM_LIT> ; for ( auto & MI : * B ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || !


<s> MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getTarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> &&


<s> MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( LabelOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SP ) . addImm ( SPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } else { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , BP ) . addImm ( BPOffset ) . addReg ( BufReg ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; if ( PVT == <STR_LIT> && Subtarget . isSVR4ABI ( ) ) { MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Tmp ) ; BuildMI ( * MBB , MI , DL , TII -> get ( PVT == <STR_LIT> ?


<s> if ( regno == HARD_FRAME_POINTER_REGNUM ) regno = current_frame_info . reg_fp ; else if ( regno == current_frame_info . reg_fp ) regno = HARD_FRAME_POINTER_REGNUM ; } if ( IN_REGNO_P ( regno ) ) return <NUM_LIT> + regno - IN_REG ( <NUM_LIT> ) ; else if ( LOC_REGNO_P ( regno ) ) return <NUM_LIT> + current_frame_info . n_input_regs + regno - LOC_REG ( <NUM_LIT> ) ; else if ( OUT_REGNO_P ( regno ) ) return ( <NUM_LIT> + current_frame_info . n_input_regs

+ current_frame_info . n_local_regs + regno - OUT_REG ( <NUM_LIT> ) ) ;


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT>

] . OperandType != MCOI :: OPERAND_PCREL ) return - <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Dest = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Mask = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Index = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ) ; if ( Dest == Mask || Dest == Index || Mask == Index ) return Warning ( Ops [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT

&& code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ;


<s> tree id ; if ( deferred_plabels == <NUM_LIT> ) deferred_plabels = ( struct deferred_plabel * ) ggc_alloc ( sizeof ( struct deferred_plabel ) ) ; else deferred_plabels = ( struct deferred_plabel * ) ggc_realloc ( deferred_plabels , ( ( n_deferred_plabels + <NUM_LIT> ) * sizeof ( struct deferred_plabel ) ) ) ; i = n_deferred_plabels ++ ; deferred_plabels [ i ] . internal_label = gen_label_rtx ( ) ; deferred_plabels [ i ] . symbol = symbol ; id = maybe_get_identifier ( targetm . strip_name_encoding ( fname ) ) ; if ( id ) mark_referenced ( id


<s> SDValue Num_S_Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , Den ) ; SDValue Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Num , Num_S_Remainder ) ; SDValue Remainder_GE_Den = DAG . getSelectCC ( DL , Remainder , Den , DAG . getConstant ( - <NUM_LIT> , VT ) , DAG . getConstant ( <NUM_LIT> , VT ) , <STR_LIT> ) ; SDValue Remainder_GE_Zero = DAG . getSelectCC ( DL , Num , Num_S_Remainder , DAG . getConstant ( - <NUM_LIT> , VT ) , DAG . getConstant ( <NUM_LIT> , VT ) , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue Div = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , VT ) , Quotient , Quotient_A_One , <STR_LIT> ) ; Div = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , VT ) , Quotient_S_One , Div , <STR_LIT> ) ; SDValue Remainder_S_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Remainder_A_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Rem = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , VT ) , Remainder , Remainder_S_Den , <STR_LIT> ) ; Rem = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , VT ) , Remainder_A_Den , Rem , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] ; Ops [ <NUM_LIT> ] = Div ; Ops [ <NUM_LIT> ] = Rem ; return DAG . getMergeValues ( Ops ,


<s> V16QImode , V8QImode , V4HImode , V2SImode } ; unsigned int sve_i = TARGET_SVE ? <NUM_LIT> : ARRAY_SIZE ( sve_modes ) ; unsigned int advsimd_i = <NUM_LIT> ; while ( advsimd_i < ARRAY_SIZE ( advsimd_modes ) ) { if ( sve_i < ARRAY_SIZE ( sve_modes ) && maybe_gt ( GET_MODE_NUNITS ( sve_modes [ sve_i ] ) , GET_MODE_NUNITS ( advsimd_modes [ advsimd_i ] ) ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; else modes -> safe_push ( advsimd_modes [ advsimd_i ++ ] ) ; } while ( sve_i < ARRAY_SIZE ( sve_modes ) ) modes -> safe_push ( sve_modes [ sve_i ++ ] ) ; unsigned int flags =


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; unsigned Start , End ; return analyzeFPImm ( Imm , VT . getSizeInBits ( ) , Start , End ,


<s>
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
<ISA_LIT>MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
<ISA_LIT>MachineFunctionInfo
>
(
)
;
OutStreamer
->
emitRawComment
(
Twine
(
<STR_LIT>
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
OutStreamer
->
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
<STR_LIT>
+
HexLines
[
i
]
+
<STR_LIT>
;
OutStreamer
->
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
->
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
return


<s> return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : return legalizeLoad ( MI , MRI , B , Observer ) ; case TargetOpcode :: G_FMAD : return legalizeFMad ( MI , MRI , B ) ; case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : return legalizeUDIV_UREM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : return legalizeSDIV_SREM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ; case TargetOpcode :: G_FLOG : return legalizeFlog ( MI , B , <NUM_LIT> / numbers :: log2ef ) ; case TargetOpcode :: G_FLOG10 : return legalizeFlog ( MI , B , numbers :: ln2f / numbers :: ln10f ) ; case TargetOpcode :: G_FEXP : return legalizeFExp ( MI , B ) ; case TargetOpcode :: G_FPOW : return legalizeFPow ( MI , B ) ; case TargetOpcode :: G_FFLOOR : return legalizeFFloor ( MI ,


<s> OriginalArgWasF128 . push_back ( originalTypeIsF128 ( FuncArgs [ Outs [ i ] . OrigArgIndex ] . Ty , CallNode ) ) ; OriginalArgWasFloat . push_back ( FuncArgs [ Outs [ i ] . OrigArgIndex ] . Ty -> isFloatingPointTy ( ) ) ; CallOperandIsFixed . push_back ( Outs [


<s> switch ( F . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( expandMemIntrinsicUses ( F ) ) Changed = true ; break ; case <STR_LIT> : case <STR_LIT> : case


<s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) )


<s> auto ArchSTI = create<ISA_LIT>MCSubtargetInfo ( STI -> getTargetTriple ( ) , STI -> getCPU ( ) . substr ( <NUM_LIT> , STI -> getCPU ( ) . size ( ) - <NUM_LIT> ) , FS ) ; std :: lock_guard < std :: mutex > Lock ( ArchSubtargetMutex ) ; ArchSubtarget [ std :: string ( STI -> getCPU ( ) ) ] = std :: unique_ptr < MCSubtargetInfo const


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BimmX16MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( isBBInRange ( MI , DestBB , BimmX16MaxDisp ) ) { Br . MaxDisp = BimmX16MaxDisp ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } else { DestBB -> setAlignment ( Align ( <NUM_LIT> ) ) ; Br . MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; HasFarJump = true ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return true


<s> const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( ! Src0 -> isReg ( ) && ! Src0 -> isImm ( ) ) return nullptr ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; MachineInstrBuilder MIB ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ! IsF64 && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB . getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { int64_t Imm ; if ( getFoldableImm ( Src2 , Imm ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; return MIB ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( getFoldableImm ( Src1 , Imm ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; return MIB ; } } if ( getFoldableImm ( Src0 , Imm )


<s> auto DenormMode = RMW -> getParent ( ) -> getParent ( ) -> getDenormalMode ( Flt ) ; if ( & Flt == & APFloat :: IEEEsingle ( ) ) return DenormMode == DenormalMode ::


<s> if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else { auto ext = std :: find_if ( std :: begin ( ExtensionMap ) , std :: end ( ExtensionMap ) , [ & ] ( const Extension & e ) { return ( FBS & e . Features ) !=


<s> static bool m32c_hard_regno_mode_ok ( unsigned int regno , machine_mode


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , <STR_LIT> ) ; SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( TGA , DAG ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , PtrVT


<s> EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { if ( DestVT == <STR_LIT> ) return Op ; SDLoc DL ( Op ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , DestVT , Ext ) ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget -> has16BitInsts ( ) && DestVT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue IntToFp32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ; SDValue FPRoundFlag = DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( Op ) ) ; SDValue FPRound = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IntToFp32 , FPRoundFlag ) ; return FPRound ; } if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op , DAG , false ) ; assert ( DestVT == <STR_LIT> ) ; return LowerINT_TO_FP64 ( Op ,


<s> if ( TREE_CODE ( arg_mask ) != INTEGER_CST ) return false ; unsigned HOST_WIDE_INT mask = TREE_INT_CST_LOW ( arg_mask ) ; if ( ( mask | ( HOST_WIDE_INT_M1U <<

elems ) ) != HOST_WIDE_INT_M1U ) return false ;


<s> OutStreamer -> EmitIntValue ( S_00B860_WAVE<ISA_LIT>ZE ( KernelInfo . ScratchBlocks ) , <NUM_LIT> ) ; } else { OutStreamer -> EmitIntValue ( RsrcReg , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_00B028_VGPRS ( KernelInfo . VGPRBlocks ) | S_00B028_SGPRS ( KernelInfo . SGPRBlocks ) , <NUM_LIT> ) ; if ( STM . isVGPRSpillingEnabled ( * MF . getFunction ( ) ) ) { OutStreamer -> EmitIntValue ( R_0286E8_SPI_TMPRING_<ISA_LIT>ZE , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_0286E8_WAVE<ISA_LIT>ZE ( KernelInfo . ScratchBlocks ) , <NUM_LIT> ) ; } } if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ) { OutStreamer -> EmitIntValue ( R_00B02C_SPI_SHADER_PGM_RSRC2_PS , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_00B02C_EXTRA_LDS_<ISA_LIT>ZE ( KernelInfo . LDSBlocks )


<s> unsigned <ISA_LIT>RegisterInfo :: getPhysRegSubReg ( unsigned Reg , const TargetRegisterClass *


<s> machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true ; rtx x ; int i ; if ( GET_CODE ( vals ) != CONST_VECTOR ) return NULL_RTX ; for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { x = CONST_VECTOR_ELT ( vals , i ) ; if ( ! rtx_equal_p ( x , CONST_VECTOR_ELT ( vals , <NUM_LIT> ) ) ) all_same = false ; } if ( ! all_same ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , CONST_VECTOR_ELT ( vals , <NUM_LIT> ) ) ; return gen_rtx_VEC_DUPLICATE ( mode


<s> unsigned Flavour = is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; unsigned RA = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCRegisterInfo * X = new


<s> bool <ISA_LIT>InstrInfo :: isAlwaysGDS ( uint16_t Opcode ) const { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT>

|| Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> static bool fitsIntoFixup ( const int64_t SignedValue , const


<s> bool function_checker :: argument_exists_p ( unsigned int argno ) { gcc_assert ( argno < ( unsigned int


<s> unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveRegPX ( Reg , Offset ) ; return false


<s> unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; bool StoreF16x2 = false ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; Opcode = <STR_LIT> ; StoreF16x2 = true ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; if ( StoreF16x2 ) { NumElts /= <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue E0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getIntPtrConstant ( i * <NUM_LIT> , DL ) ) ; SDValue E1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getIntPtrConstant ( i * <NUM_LIT> + <NUM_LIT> , DL ) ) ; SDValue V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> return create<ISA_LIT>ELFObjectWriter (


<s> assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; Value &= ~ ( <NUM_LIT> << QBitShift ) ; if ( LPAC :: modifiesOp ( AluCode ) && ( ( Op2 . isImm ( ) && Op2 . getImm ( ) != <NUM_LIT> ) || ( Op2 . isReg ( ) && Op2 . getReg ( ) != <STR_LIT> ) ) ) Value |= ( <NUM_LIT> << QBitShift ) ; return Value


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; unsigned MaxNumSGPRs = getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg (


<s> for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> PointerSize = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false


<s> if ( arg . type && ( cum -> nargs_prototype <= <NUM_LIT> || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_XL_COMPAT && align_words >= GP_ARG_NUM_REG ) ) ) return <NUM_LIT> ; passed_in_gprs = false ; if ( cum -> fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + <NUM_LIT> ) { int fpr = ( ( FP_ARG_MAX_REG + <NUM_LIT> - cum -> fregno ) * MIN ( <NUM_LIT> , GET_MODE_SIZE ( elt_mode ) ) ) ; int fpr_words = fpr / ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( align_words + fpr_words < GP_ARG_NUM_REG ) passed_in_gprs = true ; else ret = fpr ; } } if ( passed_in_gprs && align_words < GP_ARG_NUM_REG && GP_ARG_NUM_REG < align_words + rs6000_arg_size ( arg . mode , arg . type ) ) ret = ( GP_ARG_NUM_REG


<s> I . setOpcode ( Opcode ) ; I . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; OutStreamer . EmitInstruction ( I ,


<s> SDLoc DL ( N ) ; SDValue Val0 ( N , <NUM_LIT> ) ; if ( Val0 . use_empty ( ) ) return DCI . CombineTo ( N , Val0 , DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return SDValue (


<s> return hasAnyDataBarrier ( ) && ( ! isThumb ( ) || hasV8MBaselineOps (


<s> bool closeParen = printVariantKind ( OS , Kind ) ; const MCExpr * Expr = getSubExpr ( ) ; Expr -> print ( OS


<s> It = std :: find_if ( It , End , [ ] ( Instruction & I ) { return static_cast < bool > ( I . hasOneUse ( ) && storeConstCallSite ( & I ) ) ; } ) ; if ( It == End ) break ; auto Next = std :: next ( It ) ; It = tryCombine ( It , End ) ; if ( It != Next )


<s> return false ; } insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return true


<s> return ( __m512i ) __builtin_ia32_pshuflw512_mask ( ( __v32hi ) __A , __imm , ( __v32hi ) _mm512_setzero_si512 ( ) ,


<s> static void compile_for_target ( struct obstack * argv_obstack ) { switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( argv_obstack , NULL ) ; char * * argv = XOBFINISH ( argv_obstack , char * * ) ; const char * epath = getenv ( <STR_LIT> ) ; const char * cpath = getenv ( <STR_LIT> ) ; const char * lpath = getenv ( <STR_LIT> ) ; const char * rpath = getenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT>


<s> if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = &


<s> switch ( CallConv ) { default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : break ; } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , getHasAlu32 ( ) ? CC_<ISA_LIT>32 : CC_<ISA_LIT>64 ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( Outs . size ( ) > MaxArgs ) fail ( CLI . DL , DAG , <STR_LIT> , Callee ) ; for ( auto & Arg : Outs ) { <STR_LIT> Flags = Arg . Flags ; if ( ! Flags . isByVal ( ) ) continue ; fail ( CLI . DL , DAG , <STR_LIT> , Callee ) ; } auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , MaxArgs > RegsToPass ; for ( unsigned i = <NUM_LIT> , e = std :: min ( static_cast < unsigned > ( ArgLocs . size ( ) ) , MaxArgs ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , CLI . DL , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , CLI . DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode


<s> SDLoc dl ( GA ) ; SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , Align ( <NUM_LIT> ) ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT


<s> char __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __iocsrrd_b ( unsigned int _1 ) { return ( unsigned char ) __builtin_loongarch_iocsrrd_b ( ( unsigned int ) _1


<s> } assert ( ( Condition . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ConditionalCode = Condition [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TrueBlock ) . addImm ( ConditionalCode ) ; if ( ! FalseBlock )


<s> auto MI = MBB . begin ( ) ; if ( MI == MBB . end ( ) || EndbrOpcode != MI -> getOpcode ( ) ) { BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , TII ->


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Start , End ; unsigned Size ; if ( ParseIntelMemoryOperandSize ( Size ) ) return true ; bool PtrInOperand = bool ( Size ) ; Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , Operands ) ; unsigned RegNo = <NUM_LIT> ; if ( Tok . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return Error ( Start , <STR_LIT> ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) return Error ( Start , <STR_LIT> <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , Start , End ) ) ; return false ; } if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return Error ( Start , <STR_LIT> ) ; Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return true ; if ( isParsingMSInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) { if ( isParsingMSInlineAsm ( ) && SM . isOffsetOperator ( ) ) { const InlineAsmIdentifierInfo Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Operands . push_back ( <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ) ; return false ; } } Operands . push_back ( <STR_LIT> ( Disp , Start , End ) ) ; return false ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM .


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const <ISA_LIT>FrameLowering * AFI = static_cast < const <ISA_LIT>FrameLowering * > ( TFI ) ; return AFI -> useFPForAddressing ( MF )


<s> if ( Subtarget . hasSSE41 ( ) || PackSVT == <STR_LIT> ) { APInt ZeroMask = APInt :: getHighBitsSet ( BitSize * <NUM_LIT> , BitSize ) ; if ( ( N1 . isUndef ( ) || DAG . MaskedValueIsZero ( VV1 , ZeroMask ) ) && ( N2 . isUndef ( ) || DAG . MaskedValueIsZero ( VV2 , ZeroMask ) ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } } if ( ( N1 . isUndef ( ) || DAG . ComputeNumSignBits ( VV1 ) > BitSize ) && ( N2 . isUndef ( ) || DAG . ComputeNumSignBits ( VV2 ) > BitSize ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( )


<s> bool useNEONForSinglePrecisionFP ( ) const { return hasNEON ( )


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSORegMemOperand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> if ( ! <STR_LIT> ( GV -> getAddressSpace ( ) ) ) { AsmPrinter :: emitGlobalVariable ( GV ) ; return ; } assert ( ! GV -> isThreadLocal ( ) ) ; MCSymbolWasm * Sym = cast < MCSymbolWasm > ( getSymbol ( GV ) ) ; if ( ! Sym -> getType ( ) ) { const <ISA_LIT>TargetLowering & TLI = * Subtarget -> getTargetLowering ( ) ; SmallVector < EVT , <NUM_LIT> > VTs ; ComputeValueVTs ( TLI , GV -> getParent ( ) -> getDataLayout ( ) , GV -> getValueType ( ) , VTs ) ; if ( VTs . size ( ) != <NUM_LIT> || TLI . getNumRegisters ( GV -> getParent ( ) -> getContext ( ) , VTs [ <NUM_LIT> ] ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; MVT VT = TLI . getRegisterType ( GV -> getParent ( ) -> getContext ( ) , VTs [ <NUM_LIT> ] ) ; bool Mutable = true


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _clui ( void ) { __builtin_ia32_clui ( )


<s> assert ( HasInv2Pi ) ; if ( isInt < <NUM_LIT> > ( Literal ) || isUInt < <NUM_LIT> > ( Literal ) ) { int16_t Trunc = static_cast < int16_t


<s> iq2000_va_start ( valist , nextarg ) { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ if ( Pmode == DImode ) \ { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ } \ else \ { \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ } \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT>

) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ fprintf ( STREAM , <STR_LIT> ) ; \ }


<s> const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; } else { O << * Op . getExpr (


<s> } else jump = emit_jump_insn_after ( gen_return ( ) , insn ) ; if ( optimize ) emit_barrier_after ( jump ) ; emit_label_after ( bp -> near_label , insn ) ; JUMP_LABEL ( jump ) = bp -> far_label ; ok = invert_jump ( insn , label , <NUM_LIT> ) ; gcc_assert ( ok


<s> unsigned int rv = m32c_hard_regno_nregs_1 ( regno , mode ) ; return rv ?


<s> case FK_Data_4 : return ELF :: R_<ISA_LIT>_TLS_TPREL32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_TLS_TPREL64 ; } llvm_unreachable (


<s> unsigned CondReg = getRegForI1Value ( Select -> getCondition ( ) , I -> getParent ( ) , Not ) ; if ( CondReg == <NUM_LIT> ) return false ; Register TrueReg = getRegForValue ( Select -> getTrueValue ( ) ) ; if ( TrueReg == <NUM_LIT> ) return false ; Register FalseReg = getRegForValue ( Select -> getFalseValue ( ) ) ; if ( FalseReg == <NUM_LIT> ) return false ; if ( Not ) std :: swap ( TrueReg , FalseReg ) ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( Select -> getType ( ) ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT>


<s> return ( uint32x4_t ) __builtin_aarch64_lbtruncuv4sfv4si


<s> for ( auto T : SLSBLRThunks ) createThunkFunction ( MMI


<s> bool hasFP32Denormals ( const Function & F )


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> void ExpandPseudo :: expandStoreACC ( MachineBasicBlock & MBB , Iter I , unsigned MFHiOpc , unsigned MFLoOpc , unsigned RegSize ) { assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( RegSize ) ; unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> )


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForNode ( unsigned CC , bool Return , bool isVarArg ) const { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: <ISA_LIT>_AAPCS : return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; case CallingConv :: <ISA_LIT>_APCS : return ( Return ? RetCC_<ISA_LIT>_APCS :


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; uint64_t Binary = getBinaryCodeForInstr ( MI ,


<s> assert ( Arg -> getRegister ( ) . isPhysical ( ) ) ; MachineRegisterInfo & MRI = * B . getMRI ( ) ; LLT Ty = MRI . getType ( DstReg ) ; Register LiveIn = getLiveInRegister ( MRI , Arg -> getRegister ( ) , Ty ) ; if ( Arg -> isMasked ( ) ) { const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const unsigned Mask = Arg -> getMask ( ) ; const unsigned Shift = countTrailingZeros < unsigned > ( Mask ) ; Register AndMaskSrc = LiveIn ; if ( Shift != <NUM_LIT> ) { auto ShiftAmt = B . buildConstant ( S32 , Shift ) ; AndMaskSrc = B . buildLShr ( S32 , LiveIn , ShiftAmt ) . getReg ( <NUM_LIT> ) ; } B . buildAnd ( DstReg , AndMaskSrc , B . buildConstant ( S32 , Mask >> Shift ) ) ; } else B . buildCopy ( DstReg , LiveIn ) ; if ( ! MRI . getVRegDef ( LiveIn ) ) { MachineBasicBlock & OrigInsBB = B . getMBB ( ) ; auto OrigInsPt = B . getInsertPt ( ) ; MachineBasicBlock & EntryMBB = B . getMF ( ) . front ( ) ; EntryMBB . addLiveIn ( Arg -> getRegister ( ) ) ; B . setInsertPt ( EntryMBB , EntryMBB . begin ( ) ) ; B . buildCopy ( LiveIn , Arg -> getRegister ( ) ) ; B . setInsertPt ( OrigInsBB , OrigInsPt ) ; } return


<s> unsigned Width = countTrailingOnes < unsigned > ( InstrMode . Mask >> Offset ) ; unsigned Value = ( InstrMode . Mode >> Offset ) & ( ( <NUM_LIT> << Width ) - <NUM_LIT> ) ; BuildMI ( MBB , MI , <NUM_LIT> , TII -> get ( <STR_LIT> ) ) . addImm ( Value ) . addImm ( ( ( Width - <NUM_LIT> ) << <STR_LIT> :: WIDTH_M1_SHIFT_ ) | ( Offset << <STR_LIT> :: OFFSET_SHIFT_ ) | ( <STR_LIT> :: ID_MODE << <STR_LIT> :: ID_SHIFT_ ) ) ; ++ NumSetregInserted


<s> if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } bool Result = AsmPrinter :: doInitialization ( M ) ; GlobalsEmitted = false ; return Result


<s> CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( ! isTailCall && CLI . CS && CLI . CS -> isMustTailCall ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { if ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; int64_t result ; Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; FragmentRef & target_fragref = pReloc . targetRef ( ) ; Fragment * target_frag = target_fragref . frag ( ) ; LDSection & target_sect = target_frag -> getParent ( ) -> getSection ( ) ; result = ( int64_t ) ( S + A - P ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == <NUM_LIT> ) { return applyRel ( pReloc , result ) ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator ::


<s> mips_output_ascii ( STREAM , STRING , LEN ) { \ const char * p = STRING ; \ int size =

strlen ( p ) + <NUM_LIT> ; \ rdata_section ( ) ; \ assemble_string ( p , size ) ; \ }


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_ANDN2_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct riscv_arg_info info ; riscv_get_arg_info ( & info , cum , mode , type , named , false ) ; cum -> num_fprs = info .


<s> if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ; assert ( ( Kind . isReadOnly ( ) || Kind . isReadOnlyWithRel ( ) ) && <STR_LIT> ) ; return ReadOnlySection


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt


<s> if ( ! isSingleSpacedVectorAllLanes ( ) ) return false ; return VectorList . Count ==


<s> printOperand ( MI , opNum , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; return ; } const MCOperand & MO = MI ->


<s> void AMDGPUAsmPrinter :: EmitProgramInfo<ISA_LIT> ( MachineFunction & MF , const <ISA_LIT>ProgramInfo & KernelInfo ) { const AMDGPUSubtarget & STM = TM . getSubtarget < AMDGPUSubtarget > ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned RsrcReg ; switch ( MFI -> ShaderType ) { default : case ShaderType :: COMPUTE : RsrcReg = R_00B848_COMPUTE_PGM_RSRC1 ; break ; case ShaderType :: GEOMETRY : RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS ; break ; case ShaderType :: PIXEL : RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS ; break ; case ShaderType :: VERTEX : RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS ; break ; } unsigned LDSAlignShift ; if ( STM . getGeneration ( ) < AMDGPUSubtarget :: SEA_ISLANDS ) { LDSAlignShift = <NUM_LIT> ; } else { LDSAlignShift = <NUM_LIT>


<s> switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_VANILLA : Type = A -> isExternal ( ) ? ( unsigned ) MachO :: <ISA_LIT>_RELOC_SECTDIFF : ( unsigned ) MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_HI16 : dbgs ( ) << <STR_LIT> ; Type = MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_HA16 : Type = MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_LO16 : Type = MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF ; break ; case MachO :: <ISA_LIT>_RELOC_LO14 : Type = MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF ; break ; default : dbgs ( ) << <STR_LIT> ; break ; } Value2 = Writer -> getSymbolAddress ( * SB , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; return ; } uint32_t OtherHalf = <NUM_LIT> ; switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_SECTDIFF : case MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF : break ; case MachO :: <ISA_LIT>_RELOC_LO14_SECTDIFF : if ( FixedValue & <NUM_LIT> ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> ) ) ; case MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF : OtherHalf = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; FixedValue &= <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF : OtherHalf = FixedValue & <NUM_LIT> ; FixedValue = ( ( FixedValue >> <NUM_LIT> ) + ( ( FixedValue & <NUM_LIT> ) ?


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const

MCRegisterInfo & MRI , MCContext & Ctx ) {


<s> uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; bool hasAVX2 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX2 ( ) ; uint16_t validDomains = <NUM_LIT> ; if ( domain && lookup ( MI -> getOpcode ( ) , domain ) ) validDomains = <NUM_LIT> ; else if ( domain && lookupAVX2 ( MI -> getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? <NUM_LIT> : <NUM_LIT> ; return std :: make_pair ( domain


<s> MCAsmParser & getParser ( ) const { return


<s> unsigned int align ; unsigned int parm_offset ; align = function_arg_boundary ( mode , type ) / PARM_BOUNDARY - <NUM_LIT> ; parm_offset = DEFAULT_ABI == ABI_V4 ? <NUM_LIT> :


<s> bool isLegalToPruneDependencies ( SUnit * SUI , SUnit * SUJ )


<s> if ( TypeNo != <STR_LIT> ) { OS . EmitRawText ( <STR_LIT> + Twine ( VarName ) + <STR_LIT> + Twine ( TypeNo ) ) ; short ClassNo = getStorageClass ( DIGV ) ; OS . EmitRawText ( <STR_LIT> + Twine ( VarName ) + <STR_LIT> + Twine ( ClassNo ) ) ; if ( HasAux ) EmitAuxEntry ( VarName , Aux , <STR_LIT> , TagName


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI


<s> MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++


<s> if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - <NUM_LIT> ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + <NUM_LIT> ; else * cost = insn_default_latency ( dep ) ; } return false


<s> if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( <STR_LIT> )


<s> static SDValue getVectorMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeSelect =


<s> <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI


<s> bool isTargetWin32 ( ) const { return ! Is64Bit && ( isTargetMingw ( ) || isTargetWindows (


<s> } else output_addr_const ( file , x ) ; return ; case 'P' : { HOST_WIDE_INT i ; if ( ! CONST_INT_P ( x ) ) { output_operand_lossage ( <STR_LIT> ) ; return ; } i = trunc_int_for_mode ( INTVAL ( x ) + <NUM_LIT> , SImode ) ; fprintf ( file , HOST_WIDE_INT_PRINT_DEC , i ) ; return ; } case 'M' : { int first_bit , last_bit ; if ( ! CONST_INT_P ( x ) || ! tilepro_bitfield_operand_p ( INTVAL ( x ) , & first_bit , & last_bit ) ) { output_operand_lossage ( <STR_LIT> ) ; return ; } fprintf ( file , <STR_LIT> , first_bit , last_bit ) ; return ; } case 'N' : { const char * reg = NULL ; if ( ! CONST_INT_P ( x ) ) { output_operand_lossage ( <STR_LIT> ) ; return ; } switch ( INTVAL ( x ) ) { case TILEPRO_NETREG_IDN0 : reg = <STR_LIT> ; break ; case TILEPRO_NETREG_IDN1 : reg = <STR_LIT> ; break ; case TILEPRO_NETREG_SN : reg = <STR_LIT> ; break ; case TILEPRO_NETREG_UDN0 : reg = <STR_LIT> ; break ; case TILEPRO_NETREG_UDN1 : reg = <STR_LIT> ; break ; case TILEPRO_NETREG_UDN2 : reg = <STR_LIT> ; break ; case TILEPRO_NETREG_UDN3 : reg = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } fprintf ( file , reg ) ; return ; } case 't' : { HOST_WIDE_INT i ; HOST_WIDE_INT n ; if ( ! CONST_INT_P ( x ) ) { output_operand_lossage ( <STR_LIT> ) ; return ; } n = trunc_int_for_mode ( INTVAL ( x ) , SImode ) ; i = exact_log2 ( n ) ; if ( i < <NUM_LIT> ) { output_operand_lossage ( <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , n ) ; return ; } fprintf ( file , HOST_WIDE_INT_PRINT_DEC , i ) ; return ; } break ; case 'r' : if ( x == const0_rtx || ( GET_MODE ( x ) != VOIDmode && x == CONST0_RTX ( GET_MODE ( x ) ) ) ) { fputs ( <STR_LIT> , file ) ; return ; } else if ( ! REG_P ( x ) ) { output_operand_lossage ( <STR_LIT> ) ; return ; } case <NUM_LIT> : if ( REG_P ( x ) ) { fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; return ; } else if ( MEM_P ( x ) ) { output_address ( VOIDmode , XEXP ( x , <NUM_LIT> ) ) ; return ; } else { output_addr_const ( file , x ) ; return ; } break ; } debug_rtx ( x


<s> memset ( rws_insn , <NUM_LIT> , sizeof ( rws_insn ) ) ; return <NUM_LIT> ; case CALL_INSN : flags . is_branch = <NUM_LIT> ; flags . is_sibcall = SIBLING_CALL_P ( insn ) ; memset ( rws_insn , <NUM_LIT> , sizeof ( rws_insn ) ) ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = <NUM_LIT> ; break ; } need_barrier = rtx_needs_barrier ( PATTERN ( insn ) , flags , <NUM_LIT> ) ; break ; case JUMP_INSN : if ( ! ia64_spec_check_p ( insn ) ) flags . is_branch = <NUM_LIT> ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = <NUM_LIT> ; break ; } case INSN : if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) break ; pat = PATTERN ( insn ) ; switch ( recog_memoized ( insn )


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Frame , DAG . getIntPtrConstant ( TD -> getPointerSize ( ) ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false ,


<s> i2 = prev_nonnote_insn ( i3 ) ; if ( i2 == NULL ) return <NUM_LIT> ; i1 = prev_nonnote_insn ( i2 ) ; if ( i1 == NULL ) return


<s> if ( IntImm . getActiveBits ( ) > <NUM_LIT> ) return false ; bool Success = TII -> isRxSBGMask ( IntImm . getZExtValue ( ) , BitWidth , Start , End ) ; if ( ! Success ) return false ; Start -= <NUM_LIT> - BitWidth ; End -= <NUM_LIT>


<s> rtx def_set = single_set ( insn ) ; if ( def_set && REG_P ( SET_DEST ( def_set ) ) && ! HARD_REGISTER_P ( SET_DEST ( def_set ) ) ) bitmap_set_bit ( defs , REGNO ( SET_DEST ( def_set ) ) ) ; df_ref ref ; for ( ref = DF_INSN_UID_DEFS ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! HARD_REGISTER_P ( DF_REF_REG ( ref ) ) ) if ( ! analyze_register_chain ( candidates , ref , disallowed ) ) return false ; if ( def_set && GET_CODE ( SET_SRC ( def_set ) ) == VEC_SELECT ) return true ; for ( ref = DF_INSN_UID_USES ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! DF_REF_REG_MEM_P ( ref ) ) if ( ! analyze_register_chain ( candidates , ref , disallowed ) ) return false ; return


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG


<s> if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( int_size_in_bytes ( type ) < <NUM_LIT> ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( TARGET_32BIT && ! TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) { if ( TARGET_DEBUG_ARG ) fprintf


<s> ready_set :: iterator fttarget = ready . end ( ) ; for ( ready_set :: iterator i ( ready . begin ( ) ) , ie ( ready . end ( ) ) ; i != ie ; i ++ ) { if ( i -> block -> MBB == fallthrough ) { fttarget = i


<s> } else if ( Name . equals_insensitive ( <STR_LIT> ) ) { SM . onAnd ( ) ; } else if ( Name . equals_insensitive ( <STR_LIT> ) ) { SM . onMod ( ) ; } else if ( Name . equals_insensitive ( <STR_LIT> ) ) { SMLoc OffsetLoc = getTok ( ) . getLoc ( ) ; const MCExpr * Val = nullptr ; StringRef ID ; InlineAsmIdentifierInfo Info ; ParseError = ParseIntelOffsetOperator ( Val , ID , Info , End ) ; if ( ParseError ) return true ; StringRef ErrMsg ; ParseError = SM . onOffset ( Val , OffsetLoc , ID , Info , isParsingMSInlineAsm ( ) , ErrMsg ) ; if ( ParseError ) return Error ( SMLoc :: getFromPointer ( Name . data ( ) ) , ErrMsg ) ; } else { return false ; } if ( ! Name . equals_insensitive ( <STR_LIT> ) ) End = consumeToken


<s> O << <STR_LIT> ; if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { print<ISA_LIT>ImmOperand ( MI , OpNo , O ) ; } else { printOp ( MI -> getOperand ( OpNo ) , O ) ; } O <<


<s> Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; case 'U' : if ( constraint [ <NUM_LIT> ] == 'p' && ( constraint [ <NUM_LIT> ] == 'l' || constraint [ <NUM_LIT> ]


<s> MIB . addReg ( <STR_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT>


<s> } else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) != <NUM_LIT> ) { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGEOFF ; else llvm_unreachable ( <STR_LIT> ) ; } else { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> )

RefKind = MCSymbolRefExpr :: VK_PAGEOFF ;


<s> SDLoc dl ( St ) ; SDValue StoredVal = St -> getValue ( ) ; if ( StoredVal . getValueType ( ) . isVector ( ) && StoredVal . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { assert ( StoredVal . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( DAG . getTargetLoweringInfo ( ) . getTypeAction ( * DAG . getContext ( ) , StoreVT ) != TargetLowering :: TypeWidenVector ) return SDValue ( ) ; MVT WideVT = <STR_LIT> ( StoreVT . getVectorElementType ( ) , StoreVT . getVectorNumElements ( ) * <NUM_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2 ( ) ) { MVT StVT = Subtarget . is64Bit ( ) && StoreVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; MVT CastVT = <STR_LIT> ( StVT ,


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Inst . getOpcode ( ) == <STR_LIT> && Val == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Val != <STR_LIT> && ! <ISA_LIT>Insts [ Inst . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , MCDisassembler :: SoftFail ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; if ( Val == <STR_LIT> ) { Inst . addOperand ( MCOperand ::


<s> bool isAISrc_256B64 ( ) const { return isRegOrInlineNoMods ( <STR_LIT>


<s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned


<s> SDNodeTreeBuilder b ( Op , & DAG ) ; assert ( EltVT . isInteger ( ) && Val . getValueType ( ) . bitsGE ( EltVT ) && <STR_LIT> ) ; if ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , FullVT , Trunc ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , Ext ) ; } else { assert ( Val . getSimpleValueType ( ) . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; MVT I32VecType = <STR_LIT> ( <STR_LIT> , VecVT . getSizeInBits ( ) / <NUM_LIT> ) ; int mask = ( <NUM_LIT> << EltVT . getSizeInBits ( ) ) - <NUM_LIT> ; SDValue R1 = b . ANY_EXTEND ( b . AND ( b . TRUNCATE ( Val , <STR_LIT> ) , b . Constant ( mask , <STR_LIT> ) ) , <STR_LIT> ) ; SDValue R2 = DAG . getNode ( <STR_LIT> , dl , I32VecType , R1 ) ; return b . BITCAST ( R2 , VecVT ) ; } llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> int Addend = <NUM_LIT> ; switch ( getMnemonicFromOpcode ( MI . getOpcode ( ) ) ) { case FlagArithMnemonic :: ADC : case FlagArithMnemonic :: ADCX : case FlagArithMnemonic :: RCL : case FlagArithMnemonic :: RCR : case FlagArithMnemonic :: SBB : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; case FlagArithMnemonic :: ADOX : Cond = <STR_LIT> ; Addend = <NUM_LIT> ; break ; } unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; Register TmpReg = MRI -> createVirtualRegister ( PromoteRC ) ; auto AddI = BuildMI ( MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( TmpReg , RegState :: Dead ) . addReg ( CondReg ) . addImm ( Addend ) ; ( void ) AddI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; AddI


<s> unsigned getWavesPerWorkGroup ( const MCSubtargetInfo *


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MCPhysReg Reg = MFI -> getVGPRToAGPRSpill ( Index , Lane ) ; if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ; unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg ) ) ? <STR_LIT> : <STR_LIT> ; return BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( Opc ) , Dst ) . addReg ( Src


<s> int i ; for ( i = <NUM_LIT> ; i < argc ; i ++ ) { if ( startswith ( argv [ i ] , <STR_LIT> ) ) { search_dirs = XRESIZEVEC ( const char * , search_dirs , search_dirs_len + <NUM_LIT> ) ; search_dirs [ search_dirs_len ++ ] = & argv [ i ] [ <NUM_LIT> ] ; } else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) verbose ++ ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) { fprintf ( stdout , <STR_LIT> ) ; exit ( EXIT_SUCCESS ) ; } else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) { fprintf ( stdout , <STR_LIT> ) ; exit ( EXIT_SUCCESS ) ; } else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) addarg ( <STR_LIT> ) ; else if ( startswith ( argv [ i ] , <STR_LIT> ) ) { addarg ( <STR_LIT> ) ; debug = <NUM_LIT> ; } else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) staticp = <NUM_LIT> ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) { char * buff , * ptr ; buff = ( char * ) xstrdup


<s> Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SetCC ) ; return Sum ; } } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Cond , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SetCC ) ; return Sum


<s> unsigned <ISA_LIT>InstrInfo :: insertNE ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned SrcReg , int Value ) const { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( RI . getBoolRC


<s> * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; * ( ( intptr_t * ) RelocPos ) |= get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { * ( ( intptr_t * ) RelocPos ) |= ( intptr_t ) ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; ResultPtr = ( ResultPtr & <NUM_LIT> ) >> <NUM_LIT> ; assert ( ResultPtr >= - <NUM_LIT> && ResultPtr <= <NUM_LIT> ) ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; break ; } case <STR_LIT> : { ResultPtr = ResultPtr & <NUM_LIT> ; * ( ( intptr_t * ) RelocPos


<s> if ( ! Subtarget -> hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ; SDVTList VTs = DAG . getVTList ( N -> getMask ( ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Index } ; SDValue NewScatter = DAG . getMaskedScatter ( VTs , VT , dl , Ops , N -> getMemOperand (


<s> init_machine_status = c6x_init_machine_status ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( c6x_unit_names ) ; i ++ ) c6x_unit_codes [ i ] = get_cpu_unit_code ( c6x_unit_names [ i ] ) ; if ( flag_pic && ! TARGET_DSBT ) { error ( <STR_LIT> <STR_LIT> ) ; flag_pic = <NUM_LIT>


<s> while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - <NUM_LIT> ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size ; formal_type = TREE_CHAIN ( formal_type ) ; } } newsym = alloca ( <NUM_LIT> + strlen ( asmname ) + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) ; return get_identifier_with_length ( newsym , sprintf ( newsym , <STR_LIT> , prefix


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == LABEL_REF ) { label = SET_SRC ( pat ) ; } else if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) == <NUM_LIT> )


<s> case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx ( <NUM_LIT> ) ; case <NUM_LIT> : return __builtin_arm_getwcx


<s> } if ( ! isUInt < <NUM_LIT> > ( Imm ) ) { Error ( OffsetLoc , <STR_LIT> ) ; return false ; } return true


<s> return <NUM_LIT> ; } else if ( FBB == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( int i = <NUM_LIT> , e = Cond . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Cond [ i ] ) ; MIB . addMBB ( TBB ) ; return <NUM_LIT> ; } MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( int i = <NUM_LIT> , e = Cond . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Cond [ i ] ) ; MIB . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) .


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) || spillsCR ( MF ) || hasNonRISpills ( MF ) || ( hasSpills ( MF ) && ! isInt < <NUM_LIT> > ( StackSize ) ) ) { const TargetRegisterClass & GPRC = <STR_LIT> ; const TargetRegisterClass & G8RC = <STR_LIT> ; const TargetRegisterClass & RC = Subtarget . is<ISA_LIT>64 ( ) ? G8RC : GPRC ; const TargetRegisterInfo & TRI = * Subtarget . getRegisterInfo (


<s> case <STR_LIT> : return LowerLOAD ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT == <STR_LIT> ) return LowerI8Math ( Op , DAG , Opc , * this ) ; break ; } case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , * this ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerByteImmed ( Op


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( ( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( tm . getTargetTriple ( ) , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( tm . getTargetTriple ( ) , true ) , ( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) , TM ( tm ) , TII ( tii ) { <ISA_LIT>_MC :: InitLLVM2SEHRegisterMapping ( this ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Is64Bit = Subtarget -> is64Bit


<s> unsigned OpNum = ( PFEntry >> <NUM_LIT> ) & <NUM_LIT> ; unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case


<s> MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineInstr * MemMI = I ; MachineBasicBlock :: iterator MBBI = I ; const MachineFunction & MF = * MemMI -> getParent ( ) -> getParent ( ) ; unsigned DestReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = MemMI -> getOperand ( <NUM_LIT> ) . getImm ( ) * TII -> getRegClass ( MemMI -> getDesc ( ) , <NUM_LIT> , TRI ,


<s> x = m68k_wrap_symbol ( x , reloc , m68k_get_gp ( ) , temp_reg ) ; x = gen_rtx_MEM ( Pmode , x


<s> return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR0 , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR1 , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR2 , VT ) ; case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , VT . getSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , VT , MMO ) ; } case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerSampleIntrinsic ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } } case <STR_LIT> : SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : { SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VT . getSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Ops , VT , MMO ) ; } default : break ; } } return SDValue (


<s> Handlers . emplace_back ( llvm :: make_unique < BTFDebug > ( this ) , <STR_LIT> ,


<s> for ( i = probe_interval ; i < size ; i += probe_interval ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { gcc_assert ( int_registers_saved ) ; HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , probe_interval ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( gen_probe_stack_range ( Pmode , sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) ,


<s> SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * Root . getParent ( ) , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! isUInt < <NUM_LIT> > ( EncodedImm ) ) return None ; return {


<s> for ( auto & MBB : MF ) { if ( ! MBB . isEHPad ( ) ) continue ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * EHPadLayoutPred = MBB . getPrevNode ( ) ; MachineBasicBlock * Cont = & MBB ; while ( Cont -> isEHPad ( ) ) { MachineInstr * Try = EHPadToTry [ Cont ] ; MachineInstr * EndTry = BeginToEnd [ Try ] ; Cont = EndTry -> getParent ( ) ; } bool Analyzable = ! TII . analyzeBranch ( * EHPadLayoutPred , TBB , FBB , Cond ) ; if ( Analyzable && ( ( Cond . empty ( ) && TBB && TBB == Cont ) || ( ! Cond . empty ( ) && FBB && FBB == Cont ) ) ) { bool ErasedUncondBr = false ; ( void ) ErasedUncondBr ; for ( auto I = EHPadLayoutPred -> end ( ) , E = EHPadLayoutPred -> begin ( ) ; I != E ; -- I ) { auto PrevI = std :: prev


<s> if ( ! optimize_size && optimize > <NUM_LIT> ) return nds32_expand_movmemsi_loop ( dstmem , srcmem , total_bytes , alignment ) ; return false


<s> void <ISA_LIT>DebugValueManager :: move ( MachineInstr * Insert ) { MachineBasicBlock * MBB = Insert -> getParent (


<s> TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>ELFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T ,


<s> bool runOnFunction ( Function & F ) override { Func = & F ; return ProcessFunction (


<s> SDValue Chain = DAG . getStore ( St -> getChain ( ) , dl , Val , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) , St -> getAAInfo ( ) ) ; return Chain ; } return SDValue


<s> AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < LiveVariables > ( ) ; AU . addRequired < LiveIntervals >


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF


<s> return __builtin_ia32_vcvttph2uqq256_mask ( __A , _mm256_setzero_si256 ( ) , ( __mmask8 )


<s> rtx addr = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == LO_SUM && XEXP ( addr , <NUM_LIT> ) == pic_offset_table_rtx ) { rtx inner = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( inner ) == UNSPEC && XINT ( inner , <NUM_LIT> ) == UNSPEC_GOT ) return XVECEXP ( inner , <NUM_LIT>


<s> basic_block * bbs = get_loop_body ( loop ) ; int nbbs = loop -> num_nodes ; int vec_cost = data -> cost [ vect_body ] , not_vec_cost = <NUM_LIT> ; int i , density_pct ; for ( i = <NUM_LIT> ; i < nbbs ; i ++ ) { basic_block bb = bbs [ i ] ; gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = vinfo_for_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } } free ( bbs )


<s> static DecodeStatus DecodePCRelLabel19 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { int64_t ImmVal = Imm ; if ( ImmVal & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ImmVal |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , ImmVal * <NUM_LIT> , Addr , Inst . getOpcode ( ) != <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm


<s> EmitConstantPool ( ) ; const Function * F = MF -> getFunction ( ) ; OutStreamer . SwitchSectionNoChange ( getObjFileLowering ( ) . SectionForGlobal ( F , Mang , TM ) ) ; EmitFunctionEntryLabel ( ) ; if ( F -> hasPrefixData ( ) ) EmitGlobalConstant ( F -> getPrefixData ( )


<s> MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * XFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool emitFrameMoves = <ISA_LIT>RegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { MBB . addLiveIn ( it -> getReg ( )


<s> if ( AfterMI != MBB . end ( ) && isX87Instruction ( * AfterMI ) && ! isX87NonWaitingControlInstruction ( * AfterMI ) ) continue ; BuildMI ( MBB , AfterMI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; ++ MI ; Changed =


<s> bool enablePostRAScheduler ( ) const { return DoILP


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS << char ( <STR_LIT> ) ; return true


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> const char * arg_regs [ <NUM_LIT> ] ; enum machine_mode arg_mode ; rtx link ; int i , output_flag = <NUM_LIT> ; int regno ; if ( TARGET_64BIT || TARGET_ELF32 ) return ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) arg_regs [ i ] = <NUM_LIT> ; if ( TARGET_PORTABLE_RUNTIME ) { fputs ( <STR_LIT> , asm_out_file ) ; return ; } gcc_assert ( GET_CODE ( call_insn ) == CALL_INSN ) ; for ( link = CALL_INSN_FUNCTION_USAGE ( call_insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { rtx use = XEXP ( link , <NUM_LIT> ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , <NUM_LIT> ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , <NUM_LIT> ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> )


<s> auto & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } MachineInstrBuilder MIB { MF , I } ; using namespace TargetOpcode ; switch ( I . getOpcode ( ) ) { case G_ADD : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; AddDefaultCC ( AddDefaultPred ( MIB . addImm ( <NUM_LIT> ) ) ) ; break ; case G_LOAD : I . setDesc ( TII . get ( <STR_LIT>


<s> } assert ( Op . isImm ( ) ) ; OptionalIdx [ Op . getImmTy ( ) ] = i ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOffset ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDFMT ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyNFMT ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Op . dump ( ) ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerPOT ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT>


<s> PI != PE ; ++ PI ) { if ( ! DT -> dominates ( A


<s> if ( MI -> getOperand ( Op + <NUM_LIT> ) . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } printLeaMemReference ( MI , Op ,


<s> MIB . addImm ( MI . getOperand ( OpIdx ) . getImm (


<s> Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( & Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = & F . getEntryBlock ( ) . front ( ) ; SI -> insertBefore ( First ) ; Use -> eraseFromParent ( ) ; } else { ++ UI ; } } } } ++ Idx ; } for ( auto & B : F ) { for ( auto & I : B ) { BinaryOperator * Ashr = dyn_cast < BinaryOperator > ( & I ) ; if ( ! ( Ashr && Ashr -> getOpcode ( ) == Instruction :: AShr ) ) continue ; Value * AshrOp1 = Ashr -> getOperand ( <NUM_LIT> ) ; ConstantInt * C = dyn_cast < ConstantInt > ( AshrOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; Instruction * Shl = dyn_cast < Instruction > ( Ashr -> getOperand ( <NUM_LIT> ) ) ; if ( ! ( Shl && Shl -> getOpcode ( ) == Instruction :: Shl ) ) continue ; Value * Intr = Shl -> getOperand ( <NUM_LIT> ) ; Value * ShlOp1 = Shl -> getOperand ( <NUM_LIT> ) ; C = dyn_cast < ConstantInt > ( ShlOp1 ) ; if ( ! ( C && C -> getSExtValue ( ) == <NUM_LIT> ) ) continue ; if ( IntrinsicInst * I = dyn_cast < IntrinsicInst > ( Intr ) ) { if ( ! intrinsicAlreadySextended ( I -> getIntrinsicID ( ) ) ) continue ; for ( auto UI = Ashr -> user_begin ( ) , UE = Ashr -> user_end ( ) ; UI != UE ; ++ UI ) { const Use & TheUse =


<s> rtx reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_return_addr_mask ( reg ) ) ; return reg


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { unsigned Opcode = <NUM_LIT> ; switch ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) { case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; MachineInstr * NewMI ; if ( TRI -> isVGPR ( MBB . getParent ( ) -> getRegInfo ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Opcode = <STR_LIT> ( Opcode ) ; NewMI = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { NewMI = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; } if ( NewMI -> hasExtraSrcRegAllocReq ( ) ) for ( MachineOperand & NewMO : NewMI -> uses ( ) ) if ( NewMO . isReg ( ) && NewMO . isUse ( ) ) NewMO . setIsRenamable ( false ) ; break ; } case <STR_LIT> : { const MachineOperand & Op = MI . getOperand


<s> } ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( N ) -> getMask ( ) ; int ParitySrc [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned Size = Mask . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( M % Size ) != i ) return false ; int Src = M / Size ; if ( ParitySrc [ i % <NUM_LIT> ] >= <NUM_LIT> && ParitySrc [ i % <NUM_LIT> ] != Src ) return false ; ParitySrc [ i % <NUM_LIT> ] = Src ; } if ( ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] == ParitySrc [ <NUM_LIT> ] ) return false ; IsSubAdd = ParitySrc [ <NUM_LIT> ] == <NUM_LIT> ? V1 -> getOpcode ( ) == <STR_LIT> : V2 ->


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS4 ( SDValue Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base ,


<s> rtx canon ; rtx addr = XEXP ( align , <NUM_LIT> ) ; if ( REG_P ( addr ) ) canon = addr ; else if ( GET_CODE ( addr ) == PLUS ) { rtx addrop0 = XEXP ( addr , <NUM_LIT> ) ; rtx addrop1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! REG_P ( addrop0 ) ) addrop0 = force_reg ( GET_MODE ( addrop0 ) ,


<s> if ( auto * C = dyn_cast < ConstantSDNode > ( N ) ) { int64_t ImmVal = SignExtend64 ( C -> getSExtValue ( )


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & NextTok = Parser . getTok ( ) ; if ( NextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += NextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ; Res = evaluateRelocExpr ( IdVal , Str


<s> rtx op0 , op1 ; const struct cpu_cost_table * extra_cost = aarch64_tune_params -> insn_extra_cost ; int cost = <NUM_LIT> ; bool maybe_fma = ( outer == PLUS || outer == MINUS ) ; machine_mode mode = GET_MODE ( x ) ; gcc_checking_assert ( code == MULT ) ; op0 = XEXP ( x , <NUM_LIT> ) ; op1 = XEXP ( x , <NUM_LIT> ) ; if ( VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( CONST_INT_P ( op1 ) && exact_log2 ( INTVAL ( op1 ) ) > <NUM_LIT> ) { if ( speed ) { if ( maybe_fma ) cost += extra_cost -> alu . arith_shift ; else cost += extra_cost -> alu . shift ; } cost += rtx_cost ( op0 , GET_CODE ( op0 ) , <NUM_LIT> , speed ) ; return cost ; } if ( ( GET_CODE ( op0 ) == ZERO_EXTEND && GET_CODE ( op1 ) == ZERO_EXTEND ) || ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( op1 ) == SIGN_EXTEND ) ) { cost += rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( op1 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ <NUM_LIT> ] . extend_add ; else cost += extra_cost -> mult [ <NUM_LIT> ] . extend ; } return cost ; } cost += rtx_cost ( op0 , MULT , <NUM_LIT> , speed ) + rtx_cost ( op1 , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ mode == DImode ] . add ; else cost += extra_cost -> mult [ mode == DImode ]


<s> unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; if ( RPI . IsGPR ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg2 ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII


<s> bool <ISA_LIT>FrameLowering :: shouldCombineCSRLocalStackBump ( MachineFunction & MF , unsigned StackBumpBytes ) const { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI . hasVarSizedObjects (