<s> if ( TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; long TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator II = U -> op_begin ( ) + <NUM_LIT> , IE = U -> op_end ( ) ; II != IE ; ++ II , ++ GTI ) { const Value * Op = * II ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op )


<s> ValueList VL ; if ( IsNarrowSequence < <NUM_LIT> > ( MulOp0 , VL ) && IsNarrowSequence < <NUM_LIT> > ( MulOp1 , VL ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Mul -> dump ( ) ) ; Candidates . push_back ( ParallelMAC ( Mul


<s> OS << printReg ( Contents . R . Reg , TRI , Contents .


<s> elt_size |= GET_MODE_SIZE ( elt_mode ) ; elt_size &= - elt_size ; init_frag . size = elt_size ; init_frag . mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( elt_size * BITS_PER_UNIT - <NUM_LIT> ) ) - <NUM_LIT> ; init_frag . val = <NUM_LIT> ; init_frag . offset = <NUM_LIT> ; init_frag . started = false ; init_frag . remaining = ( size + elt_size - <NUM_LIT> ) / elt_size ; fprintf ( file , <STR_LIT> , section , align / BITS_PER_UNIT , elt_size * BITS_PER_UNIT ) ; assemble_name ( file , name ) ; if ( size ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC


<s> unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( featureBits [ <STR_LIT> ] && ! featureBits [ <STR_LIT> ] ) { if ( Rt == <NUM_LIT> || Rt == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ; } else Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg (


<s> if ( SDValue T = WidenHvxExtend ( Op , DAG ) ) Results . push_back ( T ) ; } break ; case <STR_LIT> : if ( shouldWidenToHvx ( ty ( Op ) , DAG ) ) { if ( SDValue T = WidenHvxSetCC ( Op , DAG ) ) Results . push_back ( T ) ; } break ; case <STR_LIT> : if ( shouldWidenToHvx ( ty ( Op ) , DAG ) ) { if ( SDValue T = WidenHvxTruncate ( Op , DAG ) )


<s> if ( RegIndex != <NUM_LIT> && AssemblerOptions . back ( ) -> getATRegIndex ( ) == RegIndex ) Warning (

Loc , <STR_LIT> + Twine ( RegIndex ) + <STR_LIT> ) ;


<s> LRU . addLiveOuts ( MBB ) ; std :: for_each ( MBB . rbegin ( ) , MBB . rend ( ) , [ & LRU ] ( MachineInstr & MI ) { LRU . accumulate ( MI ) ; } ) ; if ( ! LRU . available ( <STR_LIT> ) ) Flags |= MachineOutlinerMBBFlags


<s> XMI . setOpcode ( ( Desc . isBranch ( ) || Desc . isCall ( ) || <ISA_LIT>MCInstrInfo :: getType ( MCII , Inst ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; if ( MO . isImm ( ) ) XMI . addOperand ( MCOperand :: createImm ( MO . getImm ( ) & ( ~ <NUM_LIT> ) ) ) ; else if ( MO . isExpr ( ) ) XMI . addOperand ( MCOperand ::


<s> unsigned <ISA_LIT>FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return


<s> eltno ++ ; } src = replace_equiv_address ( src , srcreg ) ; RTVEC_ELT ( vec , nprefix ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , src ) ; regno += regno_inc ; for ( i = <NUM_LIT> ; i < nregs ; i ++ , eltno ++ ) { RTVEC_ELT ( vec , nprefix + eltno ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , adjust_address_nv ( src , SImode , i * <NUM_LIT> ) ) ; regno +=


<s> return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> )

|| ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : Negated = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SimpleBranch = true ; break ; case <STR_LIT> : Targets . insert ( BI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : return false ; } if ( ! SimpleBranch ) return false ; RegisterRef PR = BI . getOperand ( <NUM_LIT> ) ; RegisterCell PC = getCell ( PR , Inputs ) ; const BT :: BitValue & Test = PC [ <NUM_LIT> ] ; if ( ! Test . is ( <NUM_LIT> ) && ! Test . is ( <NUM_LIT> ) ) return false ; if ( ! Test . is ( ! Negated ) ) { FallsThru = true ; return true ; } Targets . insert ( BI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; FallsThru = false ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O ,


<s> case <STR_LIT> : case <STR_LIT> : UseOp = MI . findRegisterUseOperandIdx ( Reg , false , TRI ) ; break ; case <STR_LIT> : UseOp = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI . getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned DReg = TRI -> getMatchingSuperReg ( Reg ,


<s> if ( TLOF . IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , Ty , DAG ) ; return getAddrNonPIC ( N , Ty , DAG ) ; } return getAddrLocal ( N , Ty , DAG , Subtarget . isABI_N32


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADD ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSUB ( Op , DAG ) ; case <STR_LIT> : return ExpandLoad ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return ExpandStore ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op


<s> vst3_p16 ( poly16_t * __a , poly16x4x3_t val ) { __builtin_aarch64_simd_ci __o ; poly16x8x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo (


<s> gcc_assert ( GET_CODE ( addr ) != AND ) ; if ( ! address_needs_split ( ops [ <NUM_LIT> ] ) ) { reg = gen_reg_rtx ( TImode ) ; emit_insn ( gen_spu_convert ( reg , ops [ <NUM_LIT> ] ) ) ; ops [ <NUM_LIT> ] = change_address ( ops [ <NUM_LIT> ] , TImode , addr ) ; emit_move_insn ( ops [ <NUM_LIT> ] , reg ) ; return <NUM_LIT> ; } if ( GET_CODE ( addr ) == PLUS ) { aform = <NUM_LIT> ; p0 = XEXP ( addr , <NUM_LIT> ) ; p1 = p1_lo = XEXP ( addr , <NUM_LIT> ) ; if ( REG_P ( p0 ) && GET_CODE ( p1 ) == CONST_INT ) { p1_lo = GEN_INT ( INTVAL ( p1 ) & <NUM_LIT> ) ; if ( reg_aligned_for_addr ( p0 ) ) { p1 = GEN_INT ( INTVAL ( p1 ) & - <NUM_LIT> ) ; if ( p1 == const0_rtx ) addr = p0 ; else addr = gen_rtx_PLUS ( SImode , p0 , p1 ) ; } else { rtx x = gen_reg_rtx ( SImode ) ; emit_move_insn ( x , p1 ) ; addr = gen_rtx_PLUS ( SImode , p0 , x ) ; } } } else if ( REG_P ( addr ) ) { aform = <NUM_LIT> ; p0 = addr ; p1 = p1_lo = const0_rtx ; } else { aform =


<s> EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal << <NUM_LIT> ) ; EncVal |= ( EncVal <<


<s> SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle (


<s> } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT


<s> if ( LHSDef && RHSDef ) { int64_t RHSC = ( int64_t ) RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { if ( LHSDef -> getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHSDef -> getOperand ( <NUM_LIT> ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( RHSC >> Scale ) ; } , } } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> if ( vcall_offset != <NUM_LIT> ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } rtx funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; insn = get_insns ( ) ; shorten_branches (


<s> unsigned GCNSubtarget :: getOccupancyWithNumVGPRs ( unsigned VGPRs ) const { unsigned MaxWaves = getMaxWavesPerEU ( ) ; unsigned Granule = getVGPRAllocGranule ( ) ; if ( VGPRs < Granule


<s> __inline__ static unsigned long long sh_media_MSUBS_W ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm


<s> bool <ISA_LIT>TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask ) return false ; return Mask -> getValue ( ) . isPowerOf2


<s> return SelectThumbAddrModeImm5S ( N , <NUM_LIT>


<s> bool <ISA_LIT>AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind >=

FirstLiteralRelocationKind ) return true ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerUINT_TO_FP_vec ( SDValue Op , SelectionDAG & DAG ) const { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = N0 . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; switch ( SVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT>


<s> Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( Ty -> getContext ( ) ) ; unsigned MinMaxOpcode = Ty -> isFPOrFPVectorTy ( ) ? <STR_LIT> : ( IsUnsigned ? <STR_LIT> : <STR_LIT> ) ; IntrinsicCostAttributes Attrs ( MinMaxOpcode , LegalVTy , { LegalVTy , LegalVTy } ) ; LegalizationCost = getIntrinsicInstrCost ( Attrs , CostKind ) * ( LT . first - <NUM_LIT> ) ; } return LegalizationCost + <NUM_LIT>


<s> const <ISA_LIT>RegisterInfo * LRI = static_cast < const <ISA_LIT>RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; int Offset = - <NUM_LIT> ; MFI . CreateFixedObject ( <NUM_LIT> , Offset , true ) ; Offset -= <NUM_LIT> ; MFI . CreateFixedObject ( <NUM_LIT>


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set (


<s> unsigned int i , fcode = ARM_BUILTIN_CDE_PATTERN_START ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( cde_builtin_data ) ; i ++ , fcode ++ ) { if ( ! TARGET_MAYBE_HARD_FLOAT && fcode >= ARM_BUILTIN_vcx1si ) break ; if ( ! TARGET_HAVE_MVE && fcode >= ARM_BUILTIN_vcx1qv16qi ) break ; arm_builtin_cde_datum * cde = & cde_builtin_data [ i


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= - <NUM_LIT> ) { if ( ! Offset || Offset == MI -> getOperand ( <NUM_LIT> ) . getImm


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( LoadSDNode * ChainLD = dyn_cast < LoadSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( SDNode :: op_iterator O = ChainNext -> op_begin ( ) , OE = ChainNext -> op_end ( ) ; O != OE ; ++ O ) if ( ! Visited . count ( O -> getNode ( ) ) ) Queue . push_back ( O -> getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; } Visited . clear ( ) ; Queue . clear


<s> if ( ! MI ) return nullptr ; if ( ! isPredicable ( * MI ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( nullptr , DontMoveAcrossStores ) ) return nullptr ; return


<s> switch ( <STR_LIT> ( Imm ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return


<s> unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( MFI -> getShaderType ( ) == ShaderType :: COMPUTE && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( & Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; } BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm


<s> bool isPacketEnd ( ) const { return ( packetEnd


<s> if ( UI . getUse ( ) . getResNo ( ) != Flags . getResNo ( ) ) continue ; if ( UI -> getOpcode ( ) != <STR_LIT> || cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; <STR_LIT> CC = getCondFromNode ( * FlagUI ) ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : continue ; default : return false


<s> } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( <NUM_LIT> ) ; RegisterSubReg PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; if ( Props & ConstantProperties :: Zero ) CFalse = true ; else if ( Props & ConstantProperties :: NonZero ) CTrue = true ; if ( ! CTrue && ! CFalse ) goto Undetermined ; const MachineBasicBlock * BranchTarget = BrI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; FallsThru = false ; if ( ( ! Negated && CTrue ) || ( Negated && CFalse ) ) Targets . insert ( BranchTarget ) ; else if ( ( ! Negated && CFalse ) || ( Negated &&


<s> unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , DL ) ; SDValue Result ; if ( SplitStack ) { auto & MRI = MF . getRegInfo ( ) ; auto SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; auto * ARClass = getRegClassFor ( SPTy ) ; Register Vreg = MRI . createVirtualRegister ( ARClass ) ; Chain = DAG . getCopyToReg ( Chain , DL , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , DL , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { auto & TLI = DAG . getTargetLoweringInfo ( ) ; Register SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , DL , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , SP , Size ) ; if ( Align > StackAlign ) Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( - ( uint64_t ) Align , DL , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , Result ) ; } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> ,


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) { if ( ! OpRegCstraints -> contains ( Reg ) ) return false ; } else if ( ! OpRegCstraints -> hasSubClassEq ( MRI -> getRegClass ( Reg ) ) && ! MRI -> constrainRegClass ( Reg , OpRegCstraints ) ) return false ; } return true


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { llvm_unreachable ( <STR_LIT> ) ; return


<s> for ( auto * DBI : DbgValues ) DBI -> getOperand ( <NUM_LIT> ) . setReg (


<s> if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ; else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream

& OS , MCCodeEmitter * Emitter , bool RelaxAll ) {


<s> static void emitLEAzzi ( MCStreamer & OutStreamer , MCOperand & Imm , MCOperand & RD , const MCSubtargetInfo & STI ) { MCInst LEAInst ; LEAInst . setOpcode ( <STR_LIT> ) ; LEAInst . addOperand ( RD


<s> if ( getFrameLowering ( MF ) -> hasFP ( MF ) ) return <STR_LIT> ; return <STR_LIT>


<s> bool AMDGPUDAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const { if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; unsigned DWordOffset0 = C1 -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isDSOffsetLegal ( N0 , DWordOffset1 , <NUM_LIT> )


<s> unsigned getCalleeSavedXMMFrameInfo ( int & origin


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ; return MCDisassembler


<s> static void rs6000_print_isa_options ( FILE * file , int indent , const char * string , HOST_WIDE_INT flags ) { rs6000_print_options_internal ( file , indent , string , flags , <STR_LIT> , & rs6000_opt_masks [ <NUM_LIT> ] , ARRAY_SIZE ( rs6000_opt_masks


<s> Value = <STR_LIT> ( ~ Value & <NUM_LIT> ) ; Inst . addOperand ( MCOperand ::


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return performAddSubLongCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI


<s> O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getPointerElementType ( ) ; if ( isABI || isKernelFunc ) { Align align = DL . getValueOrABITypeAlignment ( PAL . getParamAlignment ( paramIndex ) , ETy ) ; if ( ! isKernelFunc && align < Align ( <NUM_LIT> ) ) align = Align ( <NUM_LIT> ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , ETy , vtparts ) ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i


<s> if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Argument > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ; const Instruction * I = dyn_cast


<s> if ( FP_REG_P ( src ) || FP_REG_P ( dst ) ) return false ; if ( s_operand ( src , mode ) || s_operand ( dst , mode ) ) return false ; if ( ( GET_CODE ( src ) == MEM && ! offsettable_memref_p ( src ) ) || ( GET_CODE ( dst ) == MEM && ! offsettable_memref_p ( dst ) ) ) return false ; if ( register_operand ( dst , mode ) ) { rtx subreg = operand_subword ( dst , first_subword , <NUM_LIT> , mode ) ; if ( reg_overlap_mentioned_p ( subreg , src )


<s> Field ( unsigned _startBin , unsigned _startLLVM , unsigned _size ) : startBin ( _startBin ) , startLLVM


<s> if ( skipFunction ( F ) ) return false ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; bool Changed = false ; for ( auto & BB : F ) for ( Instruction & I : llvm :: make_early_inc_range ( BB ) ) Changed |= visit ( I ) ; return


<s> if ( UA . Addr -> getRegRef ( ) != DR0 ) continue ; NodeAddr < InstrNode * > IA = UA . Addr -> getOwner ( DFG ) ; assert ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) ; MachineInstr * MI = NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; if ( RDefMap [ UR0 ] [ IA . Id ] != RD0 ) continue ; MachineOperand & Op = UA . Addr -> getOp ( ) ; if ( Op . isTied ( ) ) continue ; if ( trace ( ) ) { dbgs ( ) << <STR_LIT> << Print < RegisterRef > ( DR0 , DFG ) << <STR_LIT> << Print < RegisterRef > ( UR0 , DFG ) << <STR_LIT> << * NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; } Op . setReg ( UR0 . Reg ) ; Op . setSubReg ( UR0 . Sub ) ; Changed = true ; if ( HasLimit && CpCount >= CpLimit ) break ; CpCount ++ ; if ( MI -> isCopy


<s> static rtx mips16_local_alias ( rtx func ) { if ( mips16_local_aliases == NULL ) mips16_local_aliases = hash_map < rtx , rtx , local_alias_traits > :: create_ggc ( <NUM_LIT> ) ; bool existed ; rtx * slot = & mips16_local_aliases -> get_or_insert ( func , & existed ) ; gcc_assert ( slot != NULL ) ; if ( !


<s> if ( TRI -> isVGPR ( * MRI , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . VGPR0 && Reg <= RegisterEncoding . VGPRL ) ; Result . first = Reg - RegisterEncoding . VGPR0 ; assert ( Result . first >= <NUM_LIT> && Result . first < SQ_MAX_PGM_VGPRS ) ; } else if ( TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . SGPR0 && Reg < SQ_MAX_PGM_SGPRS ) ; Result . first = Reg -

RegisterEncoding . SGPR0 + NUM_ALL_VGPRS ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned SGPRLimit = getNumSGPRsAllowed ( STI ,


<s> SDLoc DL ( Op ) ; EVT Ty = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isExpr ( ) ) return <NUM_LIT> ; errs ( ) << MO


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return <STR_LIT> ( static_cast < int32_t > ( FPLiteral . bitcastToAPInt ( ) . getZExtValue ( ) ) , AsmParser -> hasInv2PiInlineImm ( ) ) ; } return <STR_LIT> ( static_cast < int32_t > ( FPLiteral . bitcastToAPInt ( ) . getZExtValue ( ) ) , AsmParser -> hasInv2PiInlineImm ( ) ) ; } if ( type == <STR_LIT> || type == <STR_LIT> ) { return <STR_LIT> ( Imm . Val , AsmParser -> hasInv2PiInlineImm ( ) ) ; } if ( type . getScalarSizeInBits ( ) == <NUM_LIT> ) { return <STR_LIT> ( static_cast < int16_t > ( Literal . getLoBits ( <NUM_LIT> ) . getSExtValue ( ) ) , AsmParser -> hasInv2PiInlineImm ( ) ) ; } return <STR_LIT> ( static_cast < int32_t > ( Literal . getLoBits ( <NUM_LIT> ) . getZExtValue ( )


<s> if ( ! SN -> isSimple ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; unsigned Align = SN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue (


<s> unsigned Major , Minor , Micro ; TT . getOSVersion ( Major , Minor , Micro ) ; switch ( TT . getOS ( ) ) { default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple


<s> int single_const_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( big_const_operand ( op , mode ) || GET_CODE ( op ) == CONST || GET_CODE ( op )

== LABEL_REF || GET_CODE ( op ) == SYMBOL_REF ) return <NUM_LIT> ;


<s> return ( bool ) ( get_prefer_tail_policy ( ) & <NUM_LIT> || ( get_prefer_tail_policy ( ) >>


const __m128i __B [ <NUM_LIT> ] , const void * __P ) {


<s> return ( int ) __builtin_ia32_vcvttsd2si32 ( ( __v2df


<s> return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && !


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( )


<s> if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return false ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( ArrayRef < EVT > ( Tys , NumVecs + <NUM_LIT> ) ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( VLD ) , SDTys , Ops , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI ; DCI . CombineTo ( User , SDValue ( VLDDup . getNode ( ) , ResNo ) ) ; } std :: vector < SDValue > VLDDupResults ; for ( unsigned n = <NUM_LIT> ; n < NumVecs ; ++ n ) VLDDupResults . push_back ( SDValue ( VLDDup . getNode ( ) , n ) ) ; VLDDupResults . push_back ( SDValue ( VLDDup . getNode ( ) , NumVecs ) ) ; DCI . CombineTo ( VLD , VLDDupResults


<ISA_LIT>AS :: MAX_<ISA_LIT>_ADDRESS ) return MayAlias ;


<s> const std :: vector < MVT > & getParams ( ) const { return Params


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) , Streamer ( S ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; EFlags &= ~ ELF :: EF_<ISA_LIT>_MACH ; EFlags |= getElfMach ( STI . getCPU ( ) ) ; EFlags &= ~ ELF :: EF_<ISA_LIT>_XNACK ; if ( <STR_LIT> ( STI ) ) EFlags |= ELF :: EF_<ISA_LIT>_XNACK ; EFlags &= ~ ELF


<s> auto NamedMD = M . getNamedMetadata ( <STR_LIT> ) ; if ( ! NamedMD || ! NamedMD -> getNumOperands ( ) ) return ; auto Tuple = dyn_cast < MDTuple > ( NamedMD -> getOperand ( <NUM_LIT> ) ) ; if ( ! Tuple ) return ; for ( unsigned I = <NUM_LIT> , E = Tuple -> getNumOperands ( ) & - <NUM_LIT> ; I != E ; I += <NUM_LIT> ) { auto Key = mdconst :: dyn_extract < ConstantInt > ( Tuple -> getOperand ( I ) ) ; auto Val = mdconst :: dyn_extract < ConstantInt > ( Tuple -> getOperand ( I + <NUM_LIT> ) ) ; if ( ! Key || !


<s> if ( EltSize == <NUM_LIT> ) { unsigned MfvsrdIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrdIndex ) return <NUM_LIT> ; } else if ( EltSize == <NUM_LIT> ) { unsigned MfvsrwzIndex = ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( Index == MfvsrwzIndex ) return <NUM_LIT> ; } return vectorCostAdjustment ( <NUM_LIT> , Opcode , Val , nullptr ) ; } else if ( ST -> hasDirectMove ( ) ) return <NUM_LIT> ; } unsigned LHSPenalty = <NUM_LIT> ; if ( ISD == <STR_LIT> ) LHSPenalty += <NUM_LIT> ; if ( ISD == <STR_LIT> || ISD == <STR_LIT> ) return LHSPenalty + Cost ; return


<s> } else if ( ! parseExpr ( Msg . Id , <STR_LIT> ) ) { return false ; } if ( trySkipToken ( AsmToken :: Comma ) ) { Op . IsDefined = true ; Op . Loc = getLoc ( ) ; if ( isToken ( AsmToken :: Identifier ) && ( Op . Id = getMsgOpId ( Msg . Id , getTokenStr ( ) ) )


<s> FuncLen += <STR_LIT> ; FuncLen += FuncSec . second . size ( ) * <STR_LIT> ; } for ( const auto & LineSec : LineInfoTable ) { LineLen += <STR_LIT> ; LineLen += LineSec . second . size ( ) * <STR_LIT> ; } for ( const auto & FieldRelocSec : FieldRelocTable ) { FieldRelocLen += <STR_LIT> ; FieldRelocLen += FieldRelocSec . second . size ( ) * <STR_LIT> ; } for ( const auto & ExternRelocSec : ExternRelocTable ) { ExternRelocLen += <STR_LIT> ; ExternRelocLen += ExternRelocSec . second . size ( ) * <STR_LIT> ; } if ( FieldRelocLen ) FieldRelocLen += <NUM_LIT> ; if ( ExternRelocLen ) ExternRelocLen += <NUM_LIT> ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen , <NUM_LIT> ) ; OS . EmitIntValue ( LineLen , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen + LineLen , <NUM_LIT> ) ; OS . EmitIntValue ( FieldRelocLen , <NUM_LIT> ) ; OS . EmitIntValue ( FuncLen + LineLen + FieldRelocLen , <NUM_LIT> ) ; OS . EmitIntValue ( ExternRelocLen , <NUM_LIT> ) ; OS . AddComment ( <STR_LIT> ) ; OS . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; for ( const auto & FuncSec : FuncInfoTable ) { OS . AddComment ( <STR_LIT> + std :: to_string ( FuncSec . first ) ) ; OS . EmitIntValue ( FuncSec . first , <NUM_LIT> ) ; OS . EmitIntValue ( FuncSec . second . size ( ) , <NUM_LIT> ) ; for ( const auto & FuncInfo : FuncSec . second ) { Asm -> EmitLabelReference ( FuncInfo . Label , <NUM_LIT> ) ; OS . EmitIntValue ( FuncInfo . TypeId , <NUM_LIT> ) ; } } OS . AddComment ( <STR_LIT> ) ; OS . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; for ( const auto & LineSec : LineInfoTable ) { OS . AddComment ( <STR_LIT> + std :: to_string ( LineSec . first ) ) ; OS . EmitIntValue ( LineSec . first , <NUM_LIT> ) ; OS . EmitIntValue ( LineSec . second . size ( ) , <NUM_LIT>


<s> MachineBasicBlock * MBB = CI . I -> getParent ( ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; const unsigned Opcode = getNewOpcode ( CI , Paired ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg ,


<s> const TargetMachine & TM = getTargetMachine ( ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) return <NUM_LIT> ; return


<s> if ( dep_type != <NUM_LIT> ) return <NUM_LIT> ; dep_insn_code_number = recog_memoized ( dep_insn ) ; if ( dep_insn_code_number < <NUM_LIT> || recog_memoized ( insn ) < <NUM_LIT> ) return cost ; insn_type = get_attr_type ( insn ) ; dep_insn_type = get_attr_type ( dep_insn ) ; switch ( ix86_tune ) { case PROCESSOR_PENTIUM : case PROCESSOR_LAKEMONT : if ( insn_type == TYPE_LEA ) { rtx addr = PATTERN ( insn ) ; if ( GET_CODE ( addr ) == PARALLEL ) addr = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( addr ) == SET ) ; addr = SET_SRC ( addr ) ; if ( modified_in_p ( addr , dep_insn ) ) cost += <NUM_LIT> ; } else if ( ix86_agi_dependent ( dep_insn , insn ) ) cost += <NUM_LIT> ; if ( ix86_flags_dependent ( insn , dep_insn , insn_type ) ) cost = <NUM_LIT> ; if ( insn_type == TYPE_FMOV && get_attr_memory ( insn ) == MEMORY_STORE && ! ix86_agi_dependent ( dep_insn , insn ) ) cost += <NUM_LIT> ; break ; case PROCESSOR_PENTIUMPRO : if ( get_attr_fp_int_src ( dep_insn ) ) cost += <NUM_LIT> ; if ( insn_type == TYPE_FMOV && ( set = single_set ( dep_insn ) ) != NULL_RTX && ( set2 = single_set ( insn ) ) != NULL_RTX && rtx_equal_p ( SET_DEST ( set ) , SET_SRC ( set2 ) ) && MEM_P ( SET_DEST ( set2 ) ) ) cost += <NUM_LIT> ; memory = get_attr_memory ( insn ) ; if ( ( memory == MEMORY_LOAD || memory == MEMORY_BOTH ) && !

ix86_agi_dependent ( dep_insn , insn ) ) {


<s> static void tSUBspi_customALF ( const MachineInstr & MI , ALFStatementGroup & alfbb , ALFContext * ctx , string label ) { const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string SP = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto I = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SExpr * offset = ctx -> dec_unsigned ( <NUM_LIT> , I


<s> static rtx sh_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , BASE_RETURN_VALUE_REG


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeFP ( const ConstantFP * CFP , EVT VT ) { const APFloat Val = CFP -> getValueAPF ( ) ; bool is64bit = VT == <STR_LIT> ; if ( TLI . isFPImmLegal ( Val , VT ) ) { unsigned Opc = is64bit ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addFPImm ( CFP ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Align = TD . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP )


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI


<s> void DecodeBLENDMask ( MVT VT , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { int ElementBits = VT . getScalarSizeInBits ( ) ; int NumElements = VT . getVectorNumElements ( ) ; for ( int i = <NUM_LIT> ; i < NumElements ;


<s> SDNode * UpperHalfSignMask = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSign , <NUM_LIT> ) ) ; SDNode * UpperLowerMask = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDNode * UpperLowerSelect = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSignMask , <NUM_LIT> ) , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( UpperLowerMask , <NUM_LIT> ) ) ; SDNode * Shift = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { bytes = <NUM_LIT> - bytes ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { bits = <NUM_LIT> - bits ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : UpperLowerSelect ) , <NUM_LIT> ) ,

CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ;


<s> std :: vector < <ISA_LIT>FrameSortingObject > SortingObjects ( MFI -> getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI -> getObjectAlignment ( Obj ) ; int ObjectSize = MFI -> getObjectSize ( Obj ) ; if ( ObjectSize == <NUM_LIT> ) SortingObjects [ Obj ] . ObjectSize = <NUM_LIT> ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= <NUM_LIT> && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , <ISA_LIT>FrameSortingComparator ( ) ) ; int i = <NUM_LIT> ; for ( auto & Obj : SortingObjects )


<s> return false ; case ELF :: R_<ISA_LIT>_REL24 : unsigned Other = cast < MCSymbolELF > ( Sym ) . getOther ( ) << <NUM_LIT> ; return ( Other & ELF :: STO_<ISA_LIT>64_LOCAL_MASK )


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Glue ) ; CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , N -> getVTList ( ) , Ops ) ; return N


<s> addPass ( createMicro<ISA_LIT>SizeReductionPass ( ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass (


<s> SDValue Avg = detectAVGPattern ( N -> getOperand ( <NUM_LIT> ) , N -> getValueType (

<NUM_LIT> ) , DAG , Subtarget , SDLoc ( N ) ) ;


<s> std :: tie ( DstIsLarger , SrcIsLarger ) = compareOpndSize ( CvtOpc , * MBB . getParent ( ) ) ; if ( DstIsLarger ) TmpReg = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; if ( SrcIsLarger ) DstReg = getRegisterInfo ( ) . getSubReg ( DstReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , MovDesc , TmpReg ) . addReg ( SrcReg , KillSrc ) ; BuildMI ( MBB , I , DL , CvtDesc , DstReg

) . addReg ( TmpReg , RegState :: Kill ) ;


<s> MachineBasicBlock :: reverse_iterator It = MBB -> rbegin ( ) ; MachineInstr * MI = & * It ; if ( MI && ( isCondBranch ( MI ) || isUncondBranch ( MI ) ) ) return MI ; return nullptr


<s> return ( __m128i ) __builtin_ia32_vpdpwssds_v4si ( ( __v4si ) __A , ( __v4si )


<s> const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ) return

new <ISA_LIT>FastISel ( funcInfo , libInfo ) ;


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM512 : \ return prefix ## _ZMM0 + index ; \ case TYPE_XMM256 : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK1 : \ case TYPE_VK2 : \ case TYPE_VK4 : \ case TYPE_VK8 : \ case TYPE_VK16 : \ case TYPE_VK32 : \ case TYPE_VK64 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if (

index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index ; \ } \ }


<s> return ( __mmask8 ) __builtin_ia32_ucmpw256_mask ( ( __v16hi ) __X , (


<s> MInstToMCSymbol :: iterator LabelIt = LOHInstToLabel . find ( MI ) ; assert ( LabelIt != LOHInstToLabel . end ( ) && <STR_LIT> ) ; MCArgs . push_back ( LabelIt -> second ) ; } OutStreamer -> emitLOHDirective ( D . getKind ( )


<s> bool isCSRSystemRegister ( ) const { return isSystemRegister (


<s> MachineFunction :: iterator It = MBB ; ++ It ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IfTrueReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned IfFalseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CondCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool NZCVKilled = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; int ScratchFI = MF -> getFrameInfo ( ) -> CreateSpillStackObject ( <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfFalseReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB ) ; MBB -> addSuccessor ( EndBB ) ; if ( ! NZCVKilled ) { TrueBB -> addLiveIn ( <STR_LIT> ) ; EndBB -> addLiveIn ( <STR_LIT> ) ; } BuildMI ( TrueBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfTrueReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; TrueBB -> addSuccessor ( EndBB ) ; MachineInstr * StartOfEnd = EndBB -> begin ( ) ; BuildMI ( * EndBB , StartOfEnd , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( ScratchFI )


<s> if ( idx < <NUM_LIT> ) return false ; unsigned Reg = MI . getOperand ( idx ) . getReg ( ) ; switch ( Reg ) { default :


<s> static inline unsigned getSBit ( uint32_t


<s> addPass ( create<ISA_LIT>InsertWaitcntsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( create<ISA_LIT>ModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>InsertHardClausesID ) ; addPass ( & <ISA_LIT>RemoveShortExecBranchesID ) ; addPass ( & <ISA_LIT>InsertSkipsPassID ) ; addPass ( & <ISA_LIT>PreEmitPeepholeID ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( &


<s> DotCurPNum = - <NUM_LIT> ; } UsesLoad = false ; PrefVectorStoreNew = nullptr ; PacketNum ++ ; RegDefs . clear (


<s> rtx legitimize_address ( rtx x ATTRIBUTE_UNUSED , rtx oldx ATTRIBUTE_UNUSED

, enum machine_mode mode ATTRIBUTE_UNUSED ) {


<s> EVT SrcVT ; if ( N . getOpcode ( ) == <STR_LIT> ) SrcVT = cast < VTSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; else SrcVT = N . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! IsLoadStore && SrcVT == <STR_LIT> ) return <STR_LIT> ; else if ( ! IsLoadStore && SrcVT == <STR_LIT> ) return <STR_LIT> ; else if ( SrcVT == <STR_LIT> ) return <STR_LIT> ; else if ( SrcVT == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } else if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { EVT SrcVT = N . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! IsLoadStore && SrcVT == <STR_LIT> ) return <STR_LIT> ; else if ( ! IsLoadStore && SrcVT == <STR_LIT> ) return <STR_LIT> ; else if ( SrcVT ==


<s> StringRef getFunctionParameterAttributeName ( FunctionParameterAttribute e ) { switch ( e ) { CASE ( FunctionParameterAttribute , Zext ) CASE ( FunctionParameterAttribute , Sext ) CASE ( FunctionParameterAttribute , ByVal ) CASE ( FunctionParameterAttribute , Sret ) CASE ( FunctionParameterAttribute , NoAlias ) CASE ( FunctionParameterAttribute , NoCapture ) CASE ( FunctionParameterAttribute , NoWrite ) CASE ( FunctionParameterAttribute , NoReadWrite ) break ; } llvm_unreachable ( <STR_LIT> )


<s> if ( ST . IsIRStructurizerEnabled ( ) ) addPass ( createStructurizeCFGPass ( ) ) ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { addPass ( createSinkingPass ( ) ) ; addPass ( create<ISA_LIT>TypeRewriter (


<s> MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataSection ( ) ) ; unsigned PtrSize = TM . getDataLayout ( ) -> getPointerSize ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i


<s> SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , Align ( <NUM_LIT> ) ) ; const std :: string FuncName = F . getName ( ) . str ( ) ; <ISA_LIT>IncomingValueAssigner Assigner ( TLI . CCAssignFnForCall ( ) , FuncName . c_str ( ) , false ) ; if ( ! determineAssignments ( Assigner , ArgInfos , CCInfo ) ) return false ; <ISA_LIT>IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! handleAssignments ( Handler , ArgInfos , CCInfo , ArgLocs , MIRBuilder ) ) return false ; if ( F . isVarArg ( ) ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetVarArgRegs ( ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; int


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ; if ( offset == INT32_MIN


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , object :: mach :: CPUSubtype<ISA_LIT> st ) :

<ISA_LIT>AsmBackend ( T , TT ) , Subtype ( st ) {


<s> insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return true


<s> if ( Val == OtherOp ) OtherOp = Inst -> getOperand ( OpIdx1 ) ; if ( isa < ConstantPointerNull > ( OtherOp ) ) return true ; Value * OtherObj = getUnderlyingObject


<s> bool <ISA_LIT>InstrInfo :: usesVertexCache ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent (


<s> return __builtin_mve_vmulltq_int_m_sv8hi ( __arm_vuninitializedq_s32 ( ) , __a , __b ,


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10Lsl1 ( SDValue Addr , SDValue & Base , SDValue & Offset


<s> uint8_t getInstMode ( uint64_t Inst ) const { return ( Inst >> <NUM_LIT> )


<s> if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI

-> getFrameOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ) EmitInterruptVectorSection ( MF ) ; SetupMachineFunction ( MF ) ; EmitFunctionBody ( )


<s> case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; case <STR_LIT> : ConvOpc = <STR_LIT> ; break ; default : break ; } if ( ! ConvOpc || ! adjustCCMasksForInstr ( MI , Compare , CCUsers , ConvOpc


<s> unsigned D = <NUM_LIT> ; for ( const <ISA_LIT>Exception * CurException =


<s> if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ; if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested


<s> int arm_early_load_addr_dep_ptr ( rtx producer , rtx consumer ) { rtx value = arm_find_sub_rtx_with_code ( PATTERN ( producer ) , SET , false ) ; rtx addr = arm_find_sub_rtx_with_code ( PATTERN ( consumer ) , SET , false ) ; if ( ! value || ! addr || ! MEM_P (

SET_SRC ( value ) ) ) return <NUM_LIT> ;


<s> char * replaced_dots = NULL ; if ( ! name ) { s << <STR_LIT> ; name = <STR_LIT> ; } else { const char * replacement = nvptx_name_replacement ( name ) ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } write_fn_marker ( s , false , true , name ) ; s << <STR_LIT> ; } if ( result != NULL_RTX ) write_return_mode ( s , true , GET_MODE


<s> bool <ISA_LIT>PacketizerList :: promoteToDotCur ( MachineInstr & MI , SDep :: Kind DepType , MachineBasicBlock :: iterator & MII , const TargetRegisterClass * RC ) { assert ( DepType == SDep :: Data ) ; int CurOpcode = HII -> getDotCurOp ( MI ) ; MI . setDesc ( HII -> get (


<s> return ( __m256i ) __builtin_ia32_packuswb256 ( ( __v16hi ) __A , (


<s> void <ISA_LIT>CmovConverterPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage


<s> void BlackfinDAGToDAGISel :: FixRegisterClasses ( SelectionDAG & DAG ) { const BlackfinInstrInfo & TII = getInstrInfo ( ) ; const BlackfinRegisterInfo * TRI = getRegisterInfo ( ) ; DAG . AssignTopologicalOrder ( ) ; HandleSDNode Dummy ( DAG . getRoot ( ) ) ; for ( SelectionDAG :: allnodes_iterator NI = DAG . allnodes_begin ( ) ; NI != DAG . allnodes_end ( ) ; ++ NI ) { if ( NI -> use_empty ( ) || ! NI -> isMachineOpcode ( ) ) continue ; const TargetInstrDesc & DefTID = TII . get ( NI -> getMachineOpcode ( ) ) ; for ( SDNode :: use_iterator UI = NI -> use_begin ( ) ; ! UI . atEnd ( ) ; ++ UI ) { if ( ! UI -> isMachineOpcode ( ) ) continue ; if ( UI . getUse ( ) . getResNo ( ) >= DefTID . getNumDefs ( )


<s> MachineOperand & Divisor = MI -> getOperand ( <NUM_LIT> ) ; MIB = BuildMI ( MBB , std :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; Divisor . setIsKill (


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) { unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL , <NUM_LIT>


<s> if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize (


<s> return false ; if ( <ISA_LIT>CCInfo . hasByValArg ( ) || FI . hasByvalArg ( )


<s> } State = ( Name == <STR_LIT> ? EMS_Text : EMS_Data ) ; auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; emitLabel ( Symbol


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> if ( ! OutlineFromLinkOnceODRs && F . hasLinkOnceODRLinkage ( ) ) return false ; if ( F . hasSection (


<s> DECL_ARTIFICIAL ( space ) = <NUM_LIT> ; DECL_IGNORED_P ( space ) = <NUM_LIT> ; ofs = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( ofs ) = record ; TREE_CHAIN ( ofs ) = space ; base = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , ptr_type_node ) ; DECL_FIELD_CONTEXT ( base ) = record ; TREE_CHAIN ( base ) = ofs ; TYPE_FIELDS ( record ) = base ; layout_type ( record ) ; va_list_gpr_counter_field = ofs ; return


<s> } llvm :: sort ( OpRegs ) ; std :: set_difference ( Regs . begin ( ) , Regs . end ( ) , OpRegs . begin ( ) , OpRegs . end

( ) , std :: back_inserter ( ClearRegs ) ) ;


<s> Sched :: Preference <ISA_LIT>TargetLowering :: getSchedulingPreference ( SDNode * N ) const { if ( DisableILPPref || <ISA_LIT>SubTarget . enableMachineScheduler ( ) ) return TargetLowering :: getSchedulingPreference ( N ) ; return Sched


<s> setAction ( { G_PTR_ADD , <NUM_LIT> , s32 } , Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR } ) . legalFor ( { { s8 , s8 } , { s16 , s8 } , { s32 , s8 } } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ; } setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; setAction ( { G_ANYEXT , Ty } , Legal ) ; } setAction ( { G_ANYEXT , s128 } , Legal ) ; getActionDefinitionsBuilder ( G_SEXT_INREG ) . lower ( ) ; setAction ( { G_ICMP , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ; for ( const auto & Ty : { s16 , s32 , s64 } ) { setAction ( { G_MERGE_VALUES , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; } for ( const auto & Ty : { s8 , s16 , s32 } ) { setAction ( { G_MERGE_VALUES , <NUM_LIT> , Ty }


<s> int LoPos = ( i % NumEltsInLane ) / <NUM_LIT> + LaneStart + NumElts * ( i % <NUM_LIT> ) ; int HiPos = LoPos + NumEltsInLane / <NUM_LIT> ; Unpckl . push_back ( LoPos ) ; Unpckh . push_back ( HiPos ) ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckl ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckl


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = Subtarget -> is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( ! TARGET_HARD_FLOAT || ( ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT || GET_MODE_CLASS ( mode1 ) == MODE_COMPLEX_FLOAT ) ==

( GET_MODE_CLASS ( mode2 ) == MODE_FLOAT || GET_MODE_CLASS ( mode2 ) == MODE_COMPLEX_FLOAT ) ) ) ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable (


<s> CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF . getContext ( ) ) ) ; SetupMachineFunction ( MF


<s> break ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op . isFPImm ( ) ) { O << Op . getFPImm ( ) ; } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print (


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { SDValue S0 = Op . getOperand ( <NUM_LIT> ) ; if ( S0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , false ) ; assert ( DestVT == <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FloatLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FloatHi , DAG .

getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> void addVectorIndexBOperands ( MCInst & Inst , unsigned N


<s> Imm = MO . getImm ( ) ; } switch ( OpInfo . OperandType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getLit32Encoding ( static_cast < uint32_t > ( Imm ) , STI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getLit64Encoding ( static_cast < uint64_t > ( Imm ) , STI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getLit16Encoding ( static_cast < uint16_t > ( Imm ) , STI ) ; case <STR_LIT> : case <STR_LIT> : { uint16_t Lo16 = static_cast < uint16_t >


<s> Offset *= - <NUM_LIT> ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; int UpdateOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! IsPairedInsn && ( UpdateOffset > <NUM_LIT> || UpdateOffset < - <NUM_LIT> ) ) break ; if ( IsPairedInsn ) { int Scale = getMemScale ( MemMI ) ; if ( UpdateOffset % Scale != <NUM_LIT> ) break ; int ScaledOffset = UpdateOffset / Scale ; if ( ScaledOffset > <NUM_LIT> || ScaledOffset


<s> setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; static const <STR_LIT> IntTypes [ ] = { <STR_LIT> , <STR_LIT> }


<s> } const GCNSubtarget * ST = static_cast < const GCNSubtarget * > ( Subtarget ) ; const <ISA_LIT>RegisterInfo * TRI = ST -> getRegisterInfo ( ) ; bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; Register CondReg = UseSCCBr ? <STR_LIT> : TRI -> getVCC ( ) ; SDLoc SL ( N ) ; if ( ! UseSCCBr ) { Cond = SDValue ( CurDAG -> getMachineNode ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , CurDAG

-> getRegister ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Cond ) , <NUM_LIT> ) ;


<s> if ( ( GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == ABS ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCAPmode ; if ( GET_CODE ( op0 ) == PLUS && GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_K ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ) ) return CCAPmode ; if ( ( GET_CODE ( op0 ) == PLUS || GET_CODE ( op0 ) == MINUS || GET_CODE ( op1 ) == NEG ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCLmode ; if ( GET_CODE ( op0 ) == AND ) { enum machine_mode ccmode ; ccmode = s390_tm_ccmode ( XEXP ( op0 , <NUM_LIT> ) , op1 , <NUM_LIT> ) ; if ( ccmode != VOIDmode ) { return ccmode == CCTmode ? CCZmode : ccmode ; } } if ( register_operand ( op0 , HImode ) && GET_CODE ( op1 ) == CONST_INT && ( INTVAL ( op1 ) == - <NUM_LIT> || INTVAL ( op1 ) == <NUM_LIT> ) ) return CCT3mode ; if ( register_operand ( op0 , QImode ) && GET_CODE ( op1 ) == CONST_INT && ( INTVAL ( op1 ) == - <NUM_LIT> || INTVAL ( op1 ) == <NUM_LIT> ) ) return CCT3mode ; return CCZmode ; case LE : case LT : case GE : case GT : if ( ( GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == ABS ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCAPmode ; if ( GET_CODE ( op0 ) == PLUS && GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_K ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ) ) { if ( INTVAL ( XEXP ( ( op0 ) , <NUM_LIT> ) ) < <NUM_LIT> ) return CCANmode ; else return CCAPmode ; } case UNORDERED : case ORDERED : case UNEQ : case UNLE : case UNLT : case UNGE : case UNGT : case LTGT


<s> if ( ( ( align & <NUM_LIT> ) != <NUM_LIT> || ( length & <NUM_LIT> ) != <NUM_LIT> ) && ( ! unaligned_access || BYTES_BIG_ENDIAN ) ) return false ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) return arm_block_set_aligned_vect ( dstbase , length , value , align ) ; else return arm_block_set_unaligned_vect ( dstbase , length ,


<s> if ( LdStNInstrDesc * LdStDesc = getLdStNInstrDesc ( Opcode ) ) { O << <STR_LIT> << LdStDesc -> Mnemonic << LdStDesc -> Layout << '\t' ; int OpNum = LdStDesc -> ListOperand ; printVectorList ( MI , OpNum ++ , O , <STR_LIT> ) ; if ( LdStDesc -> HasLane ) O << '[' << MI -> getOperand ( OpNum ++ ) . getImm ( ) << ']' ; unsigned AddrReg = MI -> getOperand ( OpNum ++ ) . getReg ( ) ; O << <STR_LIT> << getRegisterName ( AddrReg ) << ']' ; if ( LdStDesc -> NaturalOffset != <NUM_LIT> ) { unsigned Reg = MI -> getOperand ( OpNum ++ ) . getReg ( ) ; if ( Reg != <STR_LIT> ) O << <STR_LIT> << getRegisterName ( Reg ) ; else { assert ( LdStDesc -> NaturalOffset && <STR_LIT> ) ; O << <STR_LIT> << LdStDesc -> NaturalOffset ; } } printAnnotation ( O


<s> switch ( MatchResult ) { default : break ; case Match_Success : if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; return true ; } while ( processInstruction ( Inst , Operands ) ) ; forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail


<s> static bool sh_ms_bitfield_layout_p ( tree record_type


<s> if ( ! ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReserveGOT ) ) return Relocator :: BadReloc ; Relocator :: Address GOT_S = helper_get_GOT_address ( * pReloc . symInfo ( ) , pParent ) ; Relocator :: DWord A = pReloc . target


<s> unsigned int align ; unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl && DECL_P ( decl ) && VAR_P ( decl ) && bss_initializer_p ( decl ) ) flags |= SECTION_BSS ; if ( ! decl || ! DECL_P ( decl ) ) align = MIN_UNITS_PER_WORD ; else if ( ( flags & SECTION_CODE ) != <NUM_LIT> ) align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , <NUM_LIT> ) ; else align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , int_size_in_bytes ( TREE_TYPE ( decl ) ) > MIN_UNITS_PER_WORD ?


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS


<s> InConstantPool = false ; OutStreamer -> emitDataRegion (


<s> return new <ISA_LIT>PreLegalizerCombiner (


<s> static bool isScalarLoadLegal ( const MachineInstr & MI ) { if ( ! MI . hasOneMemOperand ( ) ) return false ; const MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; const unsigned AS = MMO ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; bool isLittleEndian = Subtarget -> isLittle ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setReturnRegsCount ( RVLocs . size ( ) ) ; if ( AFI -> isCmseNSEntryFunction ( ) && MF . getFunction ( ) . hasStructRetAttr ( ) ) { DiagnosticInfoUnsupported Diag ( DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , SDLoc ( ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( Diag ) ; } for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; bool ReturnF16 = false ; if ( Subtarget -> hasFullFP16 ( ) && Subtarget -> isTargetHardFloat ( ) ) { if ( Arg . getValueType ( ) == <STR_LIT> && Arg . getOpcode ( ) == <STR_LIT> ) { SDValue ZE = Arg . getOperand ( <NUM_LIT> ) ; if ( ZE . getOpcode ( ) == <STR_LIT> && ZE . getValueType ( ) == <STR_LIT> ) { SDValue BC = ZE . getOperand ( <NUM_LIT> ) ; if ( BC . getOpcode ( ) == <STR_LIT> && BC . getValueType ( ) == <STR_LIT> ) { Arg = BC . getOperand ( <NUM_LIT> ) ; ReturnF16 = true ; } } } } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : if ( ! ReturnF16 ) Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT>


<s> UC . recordHandlerData ( L ) ; if ( ! UC . hasFnStart ( ) ) return Error ( L , <STR_LIT> ) ; if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return true ; } getTargetStreamer ( ) . emitHandlerData ( ) ; return


<s> unsigned ElemSize = HwLen / VecLen ; MVT VecTy = <STR_LIT> ( <STR_LIT> ( ElemSize * <NUM_LIT> ) , VecLen ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , VecTy , Op . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , dl , VecTy , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , VecTy , Op . getOperand ( <NUM_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , ResTy


<s> if ( TrueMaskElt < <NUM_LIT> ) return false ; EVT EltVT = MaskedOp -> getMemoryVT ( ) . getVectorElementType ( ) ; Offset = <NUM_LIT> ; Addr = MaskedOp -> getBasePtr ( ) ; if ( TrueMaskElt != <NUM_LIT> ) { Offset = TrueMaskElt * EltVT . getStoreSize ( ) ; Addr = DAG . getMemBasePlusOffset ( Addr , TypeSize :: Fixed ( Offset )


<s> switch ( GET_CODE ( op ) ) { case PLUS : return <STR_LIT> ; case MINUS : return shift_first_arg ? <STR_LIT> : <STR_LIT>


<s> void addMemUImm12OffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( isImm ( ) ) { addExpr ( Inst , getImm ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT>


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm0 ( SDValue & N


<s> REAL_VALUE_TYPE value ; REAL_VALUE_FROM_CONST_DOUBLE ( value , x ) ; if ( GET_MODE ( x ) == DFmode ) { long bits [ <NUM_LIT> ] ; REAL_VALUE_TO_TARGET_DOUBLE ( value , bits ) ; return ( ( unsigned HOST_WIDEST_INT ) ( unsigned long ) bits [ <NUM_LIT> ] << ( unsigned HOST_WIDEST_INT ) <NUM_LIT> ) | ( unsigned HOST_WIDEST_INT ) ( unsigned long ) bits [ <NUM_LIT> ] ; } else if ( GET_MODE ( x ) == SFmode ) { long


-> num_stores >= MAX_STORE ) ) return BIG ;


<s> EVT VT = TLI . getValueType ( DL , Arg . Ty ) ; MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ; unsigned NumRegs = TLI . getNumRegistersForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ; for ( unsigned i = <NUM_LIT> ; i < NumRegs ; ++ i ) { <STR_LIT> Flags = Arg


<s> int ret ; ret = ( ( arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM + <NUM_LIT> ) ? LAST_ARG_REGNUM - arg_num + <NUM_LIT> : <NUM_LIT> ) ; ret *= UNITS_PER_WORD ; if ( TARGET_DEBUG_ARG && ret ) fprintf ( stderr , <STR_LIT> , ret ) ; return ret


<s> if ( ! Header || ! Preheader || ! Latch || ! ExitingBlock ) { return false ; } using RegisterBump = std :: pair < unsigned , int64_t > ; using InductionMap = std :: map < unsigned , RegisterBump > ; InductionMap IndMap ; using instr_iterator = MachineBasicBlock :: instr_iterator ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * Phi = & * I ; for ( unsigned i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { if ( Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) != Latch ) continue ; unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; if ( DI -> getDesc ( ) . getOpcode ( ) == <STR_LIT> ) { unsigned IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Opnd2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V ; if ( MRI -> getVRegDef ( IndReg ) == Phi && checkForImmediate ( Opnd2 , V ) ) { unsigned UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } if ( IndMap . empty ( ) ) { return false ; } MachineBasicBlock * TB = nullptr , * FB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed || Cond . empty ( ) ) { return false ; } MachineInstr * condTerm = & ( * Latch -> getFirstTerminator ( ) ) ; MachineInstr * uncondTerm = & ( * std :: next ( Latch -> getFirstTerminator ( ) ) ) ; if ( ! ( condTerm -> getDesc ( ) . isConditionalBranch ( ) && uncondTerm -> getDesc ( ) . isUnconditionalBranch ( ) ) ) { return false ; } unsigned CmpReg1 = Cond [ <NUM_LIT> ] . isReg ( ) ? ( unsigned ) Cond [ <NUM_LIT> ] . getReg


<s> EmitInitData ( M ) ; EmitUnInitData ( M ) ; EmitRomData ( M )


<s> if ( & * RegionBegin == MI ) ++ RegionBegin ; bool InsideBundle = MI -> isBundledWithPred ( ) && MI -> isBundledWithSucc ( ) ; MachineInstr * PrevMI = InsideBundle ? MI -> getPrevNode ( ) : NULL ; if ( ! InsideBundle && ( ( MI -> isBundledWithPred ( ) && ! MI -> getPrevNode ( ) -> isBundledWithPred ( ) ) || ( MI -> isBundledWithSucc ( ) && ! MI -> getNextNode ( ) -> isBundledWithSucc ( ) ) ) ) { NumBundled -- ; NumNotBundled ++ ; } if ( MI -> isBundledWithPred ( ) ) MI -> unbundleFromPred ( ) ; if ( MI -> isBundledWithSucc ( ) ) MI -> unbundleFromSucc ( ) ; BB -> splice ( InsertPos , BB , MI ) ; if ( InsideBundle ) { PrevMI -> bundleWithSucc ( )


<s> return Error ( Loc , <STR_LIT> ) ; case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT>


<s> if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . BeginCOFFSymbolDef ( S ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF ::


<s> unsigned getPointerSize ( ) const { return <NUM_LIT>


<s> SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand


<s> return Ty == Type :: getInt8Ty ( Ty -> getContext (


<s> uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnesValue ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL

, Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ;


<s> if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeAddrModeImm12Operand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) )


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; StringRef ShiftName = Tok . getString ( ) ; if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> || ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else return Error ( Loc , <STR_LIT> ) ; Parser . Lex ( ) ; Amount = <NUM_LIT>


<s> if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch64_bti_j_insn_p ( next ) ) continue ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn


<s> bool llvm :: getReqNTIDx ( const Function & F , unsigned


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; assert ( insn -> numImmediatesConsumed < <NUM_LIT> && <STR_LIT> ) ; insn -> immediateSize = size ; insn -> immediateOffset = insn -> readerCursor - insn -> startLocation ; switch ( size ) { case <NUM_LIT> : if ( consume ( insn , imm8 ) ) return - <NUM_LIT> ; insn -> immediates [ insn -> numImmediatesConsumed ] = imm8 ; break ; case <NUM_LIT> : if ( consume ( insn , imm16 )


<s> return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > (


<s> if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && TRI -> isSuperOrSubRegisterEq ( MO . getReg ( ) , Candidate ) ) { IsDef = true ; break ; } } if ( IsDef ) continue ; Regs [ FoundRegs ++ ] = Candidate ; if ( FoundRegs == ( unsigned ) NumPops ) break ; } if ( FoundRegs == <NUM_LIT> ) return false ; while ( FoundRegs < ( unsigned ) NumPops ) Regs [ FoundRegs ++ ] =


<s> else VarType = Type :: getInt64Ty ( BB -> getContext ( ) ) ; GV = new GlobalVariable ( M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , AccessKey ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , TypeMeta ) ; GEPGlobals [ AccessKey ] = GV ; } else { GV = GEPGlobals [ AccessKey ] ; } if ( CInfo . Kind == <ISA_LIT>PreserveFieldInfoAI ) { auto * LDInst = new LoadInst ( Type :: getInt32Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ; Call -> replaceAllUsesWith ( LDInst ) ; Call -> eraseFromParent ( ) ; return true ; } auto * LDInst = new LoadInst ( Type :: getInt64Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ; auto * BCInst = new BitCastInst ( Base , Type :: getInt8PtrTy ( BB -> getContext ( ) ) ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , BCInst ) ; auto * GEP = GetElementPtrInst :: Create ( Type :: getInt8Ty ( BB -> getContext ( ) ) , BCInst , LDInst ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , GEP ) ; auto * BCInst2 = new BitCastInst ( GEP , Call -> getType ( ) ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , BCInst2 ) ; Call -> replaceAllUsesWith ( BCInst2 )


<s> <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; addLeaAddress ( BuildMI ( MBB , DL , TII .


<s> bool isRegOrInline ( unsigned RCID , MVT type ) const { return isRegClass ( RCID ) || isInlinableImm (


<s> if ( Changes . empty ( ) ) return ; auto it = std :: next ( Changes . begin ( ) ) ; while ( it != Changes . end ( ) ) { if ( it == Changes . begin ( ) ) { ++ it ; continue ; } auto prevIt = std :: prev ( it ) ; auto cur = it -> first ; auto prev = prevIt ->


<s> if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - <NUM_LIT> ; sign = REAL_VALUE_NEGATIVE ( r ) ? <NUM_LIT> : <NUM_LIT> ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ; mant_hi = w . elt ( <NUM_LIT> ) ; if ( mantissa != <NUM_LIT> ) return - <NUM_LIT> ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( point_pos - <NUM_LIT> ) ) - <NUM_LIT> ; if ( ( mantissa & mask ) != <NUM_LIT> ) return - <NUM_LIT> ; mantissa >>= point_pos - <NUM_LIT> ; if ( mantissa == <NUM_LIT>


<s> ELFFileFormat * file_format = getTarget ( ) . getOutputFormat ( ) ; if ( ResolveInfo :: ThreadLocal == pSym . type ( ) ) bss_sect_hdr = & file_format -> getTBSS ( ) ; else bss_sect_hdr = & file_format -> getBSS ( ) ; SectionData * bss_data = NULL ; if ( bss_sect_hdr -> hasSectionData ( ) ) bss_data = bss_sect_hdr -> getSectionData ( ) ; else bss_data = IRBuilder :: CreateSectionData ( * bss_sect_hdr ) ; uint32_t addralign = config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , pSym . size ( ) ) ; uint64_t size = ObjectBuilder :: AppendFragment ( * frag , * bss_data , addralign ) ; bss_sect_hdr -> setSize ( bss_sect_hdr -> size


<s> fprintf ( file , <STR_LIT> PROFILE_COUNT_REGISTER <STR_LIT> , LPREFIX , labelno ) ; fprintf ( file , <STR_LIT> , mcount_name ) ; } else { fprintf ( file , <STR_LIT> PROFILE_COUNT_REGISTER <STR_LIT> , LPREFIX , labelno ) ; x86_print_call_or_nop ( file , mcount_name ) ; } if ( flag_record_mcount || lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) ) { const char * sname = <STR_LIT> ; if ( current_fentry_section ( & sname ) ) ; else if ( fentry_section ) sname = fentry_section ; fprintf ( file , <STR_LIT> , sname ) ; fprintf ( file , <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; fprintf ( file ,


<s> inline vector unsigned char vec_vrlb ( vector unsigned char a1 , vector


<s> void printAL32Mem ( const MCInst * MI , unsigned opNum , raw_ostream &


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr )


<s> static bool isGreaterThan6BitTFRI ( MachineInstr * I ) { return I -> getOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( I ->

getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> EVT ReqRetVT = ResultTypes [ <NUM_LIT> ] ; EVT ReqRetEltVT = ReqRetVT . isVector ( ) ? ReqRetVT . getVectorElementType ( ) : ReqRetVT ; int ReqRetNumElts = ReqRetVT . isVector ( ) ? ReqRetVT . getVectorNumElements ( ) : <NUM_LIT> ; EVT AdjEltVT = Unpacked && IsD16 ? <STR_LIT> : ReqRetEltVT ; EVT AdjVT = Unpacked ? ReqRetNumElts > <NUM_LIT> ? EVT :: getVectorVT ( Context , AdjEltVT , ReqRetNumElts ) : AdjEltVT : ReqRetVT ; int NumElts ; if ( IsD16 && ! Unpacked ) NumElts = NumVDataDwords << <NUM_LIT> ; else NumElts = NumVDataDwords ; EVT CastVT = NumElts > <NUM_LIT> ? EVT :: getVectorVT ( Context , AdjEltVT , NumElts ) : AdjEltVT ; bool V6F16Special = false ; if ( NumElts == <NUM_LIT> ) { CastVT = EVT :: getVectorVT ( Context , <STR_LIT> , NumElts / <NUM_LIT> ) ; DMaskPop >>= <NUM_LIT> ; ReqRetNumElts >>= <NUM_LIT> ; V6F16Special = true ; AdjVT = <STR_LIT> ; } SDValue N = SDValue ( Result , <NUM_LIT> ) ; SDValue CastRes = DAG . getNode ( <STR_LIT> , DL , CastVT , N ) ; SmallVector < SDValue , <NUM_LIT> > BVElts ; if ( CastVT . isVector ( ) ) { DAG . ExtractVectorElements ( CastRes , BVElts , <NUM_LIT> , DMaskPop ) ; } else { BVElts . push_back ( CastRes ) ; } int ExtraElts = ReqRetNumElts - DMaskPop ; while ( ExtraElts -- ) BVElts . push_back ( DAG . getUNDEF ( AdjEltVT ) ) ; SDValue PreTFCRes ; if ( ReqRetNumElts > <NUM_LIT> ) { SDValue NewVec = DAG . getBuildVector ( AdjVT , DL , BVElts ) ; if ( IsD16 && Unpacked ) PreTFCRes = adjustLoadValueTypeImpl ( NewVec , ReqRetVT , DL , DAG , Unpacked ) ; else PreTFCRes = NewVec ; } else { PreTFCRes = BVElts [ <NUM_LIT> ] ; } if ( V6F16Special ) PreTFCRes = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PreTFCRes ) ; if ( ! IsTexFail ) { if ( Result -> getNumValues ( ) > <NUM_LIT> ) return DAG . getMergeValues ( { PreTFCRes , SDValue ( Result , <NUM_LIT> ) } , DL ) ; else return PreTFCRes ; } SmallVector < SDValue , <NUM_LIT> > TFCElt ; DAG . ExtractVectorElements ( N , TFCElt , DMaskPop , <NUM_LIT> ) ; SDValue TFCRes = DAG . getNode ( <STR_LIT> , DL , ResultTypes

[ <NUM_LIT> ] , TFCElt [ <NUM_LIT> ] ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const auto * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; return MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ||

RegInfo -> needsStackRealignment ( MF ) ;


<s> if ( ! Ld0 || ! Ld1 ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ; if ( ! Ld0 -> hasOneUse ( ) || ! Ld1 -> hasOneUse ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> doFMAF32AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF32 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; doFMAF64AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF64 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; allowFMA = ( FMAContractLevel >= <NUM_LIT> ) || UseFMADInstruction ; UseF32FTZ =


<s> using namespace <ISA_LIT> ; switch ( Val ) { case <NUM_LIT> : return createRegOperand ( FLAT_SCR ) ; case <NUM_LIT> : return createRegOperand ( XNACK_MASK ) ; case <NUM_LIT> : return createRegOperand ( VCC ) ; case <NUM_LIT> : return createRegOperand ( TBA ) ; case <NUM_LIT> : return createRegOperand (


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const TargetFrameLowering * TFI = MF -> getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return


<s> static bool ix86_broadcast ( HOST_WIDE_INT v , unsigned int width , HOST_WIDE_INT & val_broadcast ) { wide_int val = wi :: uhwi ( v , HOST_BITS_PER_WIDE_INT ) ; val_broadcast = wi :: extract_uhwi ( val , <NUM_LIT> , width ) ; for ( unsigned int i = width ; i < HOST_BITS_PER_WIDE_INT ; i += width ) { HOST_WIDE_INT each = wi :: extract_uhwi ( val , i , width ) ; if ( val_broadcast != each ) return false ; } val_broadcast = sext_hwi ( val_broadcast , width ) ; return