<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target32 ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>Target64


<s> <STR_LIT> ( uint32_t SizeInBits , StringRef TypeName ) : Name ( TypeName ) { Kind = <STR_LIT> ; BTFType . Info = Kind << <NUM_LIT> ; BTFType . Size = roundupToBytes ( SizeInBits


<s> } const MCInstrDesc & MovRelDesc = TII -> get ( <STR_LIT> ) ; if ( setM0ToIndexFromSGPR ( TII , MRI , MI , Offset ) ) { MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * MovRel = BuildMI ( MBB , I , DL , MovRelDesc ) . addReg ( SrcVec -> getReg ( ) , RegState :: Undef , SubReg ) . addOperand ( * Val ) . addReg ( Dst , RegState :: ImplicitDefine ) . addReg ( SrcVec -> getReg ( ) , RegState :: Implicit ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MovRel -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; return & MBB ; } if ( Val -> isReg ( ) ) MRI . clearKillFlags ( Val -> getReg ( ) ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned PhiReg = MRI . createVirtualRegister ( VecRC ) ; MachineInstr * MovRel = BuildMI ( * MF , DL , MovRelDesc ) . addReg ( PhiReg , RegState :: Undef , SubReg ) . addOperand ( * Val ) . addReg ( Dst , RegState :: ImplicitDefine ) . addReg ( PhiReg , RegState :: Implicit ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc .


<s> TotCost += getScalarizationOverhead ( Dst , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ; return TotCost ; } if ( Opcode == Instruction :: FPTrunc ) { if ( SrcScalarBits == <NUM_LIT> ) return VF + getScalarizationOverhead ( Dst , true , false ) ; else return VF / <NUM_LIT> + std :: max ( <NUM_LIT> , VF / <NUM_LIT> ) ; } if ( Opcode == Instruction :: FPExt ) { if ( SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) { return VF * <NUM_LIT> ; } return VF + getScalarizationOverhead ( Src , false , true ) ; } } else { assert ( ! Dst -> isVectorTy ( ) ) ; if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) { if ( SrcScalarBits >= <NUM_LIT> || ( I != nullptr && isa < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) return <NUM_LIT> ; return SrcScalarBits > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ?


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand >


<s> ASSERT_EQ ( UNSPEC , GET_CODE ( src ) ) ; ASSERT_EQ ( BLKmode , GET_MODE ( src ) ) ; ASSERT_EQ ( UNSPEC_MEMORY_BLOCKAGE , XINT ( src , <NUM_LIT> ) ) ; rtx v0 = XVECEXP ( src , <NUM_LIT> , <NUM_LIT> ) ; rtx scratch_a = XEXP ( dst , <NUM_LIT> ) ; ASSERT_EQ ( SCRATCH , GET_CODE ( scratch_a ) ) ; rtx scratch_b = XEXP ( v0 , <NUM_LIT> ) ; ASSERT_EQ ( SCRATCH , GET_CODE ( scratch_b ) ) ; ASSERT_EQ ( scratch_a , scratch_b ) ; ASSERT_TRUE ( rtx_equal_p ( dst , v0 ) ) ; ASSERT_NE ( - <NUM_LIT> , recog_memoized ( insn ) ) ; insn = NEXT_INSN ( insn ) ; ASSERT_EQ ( INSN , GET_CODE ( insn ) ) ; set = single_set ( insn ) ; ASSERT_NE ( NULL , set ) ; src = SET_SRC ( set ) ; ASSERT_EQ ( UNSPEC_VOLATILE , GET_CODE ( src ) ) ; ASSERT_EQ ( UNSPECV_RDTSCP , XINT ( src , <NUM_LIT> )


<s> for ( unsigned I = <NUM_LIT> , E = Ret . getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = Ret . getOperand ( I ) ; if ( ! MO . isReg ( ) || ! <STR_LIT> . contains ( MO . getReg ( ) ) ) continue ; unsigned RegNo = TRI -> getEncodingValue ( MO . getReg ( ) ) ; UsedRegMask &= ~ ( <NUM_LIT> << ( <NUM_LIT> - RegNo ) ) ; } } if ( UsedRegMask == <NUM_LIT> ) { RemoveVRSaveCode ( MI ) ; return ; } unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask ) ; } else if ( ( UsedRegMask & <NUM_LIT> ) == UsedRegMask ) { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; } else { if ( DstReg != SrcReg ) BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( UsedRegMask >> <NUM_LIT> ) ; else BuildMI ( * MI . getParent ( ) , MI , dl , TII . get ( <STR_LIT> )


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Op1 || Op1 -> getOpcode ( ) != <STR_LIT>


<s> return TargetTransformInfo :: TCC_Basic ; } if ( Ty -> isDoubleTy ( ) ) { return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo ::


<s> void createdInstr ( MachineInstr & MI


<s> MCContext & Context = getParser ( ) . getContext ( ) ; Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; switch ( E -> getKind ( ) ) { case MCExpr :: Target : case MCExpr :: Constant : return <NUM_LIT> ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( E ) ; switch ( SRE -> getKind ( ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_LO : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; default : return <NUM_LIT> ; } return MCSymbolRefExpr :: Create ( & SRE -> getSymbol ( ) , Context ) ; } case MCExpr :: Unary : { const MCUnaryExpr * UE = cast < MCUnaryExpr > ( E ) ; const MCExpr * Sub = ExtractModifierFromExpr ( UE -> getSubExpr ( ) , Variant ) ; if ( ! Sub ) return <NUM_LIT> ; return MCUnaryExpr :: Create ( UE -> getOpcode ( ) , Sub , Context ) ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ; <ISA_LIT>MCExpr :: VariantKind LHSVariant


<s> void <ISA_LIT>InstPrinter :: printU2ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printUImmOperand < <NUM_LIT> > ( MI , OpNum


<s> return SC ; } if ( VT . isVector ( ) ) return Op ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && ( RHSVT == <STR_LIT> || RHSVT == <STR_LIT> ) && ( LHSVT == <STR_LIT> || LHSVT == <STR_LIT> ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( C && C -> getAPIntValue ( ) . isNegative ( ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ; } if ( isSExtFree ( LHS ) || isSExtFree ( RHS ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( ! UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) ) return DAG . getTargetConstant ( ~ <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . isUndef ( ) ) continue ; if ( ! OpVal . getNode ( ) ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( ! OpVal . getNode ( ) ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) { Value = CN -> getZExtValue ( ) ; } else if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( OpVal ) ) { assert ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; Value = FloatToBits ( CN -> getValueAPF ( ) . convertToFloat ( ) ) ; } if ( ValSizeInBytes < ByteSize ) return SDValue ( ) ; if ( ! APInt ( ValSizeInBytes * <NUM_LIT> , Value ) . isSplat ( ByteSize


<s> StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; } if ( is<ISA_LIT>64 ( ) && ( CPU == <STR_LIT> || CPU == <STR_LIT> ) ) { Error ( L , <STR_LIT> ) ; return


<s> if ( ( ( Subtarget -> hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; return OptimizeConditionalInDecrement ( N ,


<s> static bool applySwapICmpOperands ( MachineInstr & MI , GISelChangeObserver & Observer ) { auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Observer . changedInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate ( CmpInst :: getSwappedPredicate ( Pred ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( RHS ) ; MI . getOperand ( <NUM_LIT> )


<s> case REG : fprintf ( file , ptrreg_to_str ( REGNO ( addr ) ) ) ; break ; case PRE_DEC : fprintf ( file , <STR_LIT> , ptrreg_to_str ( REGNO ( XEXP ( addr , <NUM_LIT> ) ) ) ) ; break ; case POST_INC : fprintf ( file , <STR_LIT> , ptrreg_to_str ( REGNO ( XEXP ( addr , <NUM_LIT> ) ) ) ) ; break ; default : if ( CONSTANT_ADDRESS_P ( addr ) && text_segment_operand ( addr , VOIDmode ) ) { rtx x = addr ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , <NUM_LIT> * INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( AVR_3_BYTE_PC ) if ( warning ( <NUM_LIT> , <STR_LIT> ) ) { output_addr_const ( stderr , addr ) ; fprintf ( stderr , <STR_LIT> ) ; } } else { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , addr ) ; fprintf ( file ,


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & Ctx , const

<ISA_LIT>Subtarget & ST , const AsmPrinter & AP ) :


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return getLit16Encoding ( static_cast < uint16_t > ( Imm ) , STI ) ; case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Imm ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) return getLit32Encoding ( static_cast < uint32_t > ( Imm ) , STI ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { uint16_t Lo16 = static_cast < uint16_t > ( Imm ) ; uint32_t Encoding = getLit16Encoding ( Lo16 , STI ) ; return Encoding ; } default : llvm_unreachable ( <STR_LIT>


<s> uint64_t ExplicitArgOffset = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { const bool IsByRef = Arg . hasByRefAttr ( ) ; Type * ArgTy = IsByRef ? Arg . getParamByRefType ( ) : Arg . getType ( ) ; unsigned AllocSize = DL . getTypeAllocSize ( ArgTy ) ; if ( AllocSize == <NUM_LIT> ) continue ; MaybeAlign ABIAlign = IsByRef ? Arg . getParamAlign ( ) : None ; if ( ! ABIAlign ) ABIAlign = DL . getABITypeAlign ( ArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + BaseOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + AllocSize ; if ( Arg . use_empty ( ) ) { ++ i ; continue ; } Align Alignment = commonAlignment ( KernArgBaseAlign , ArgOffset ) ; if ( IsByRef ) { unsigned ByRefAS = cast < PointerType > ( Arg . getType ( ) ) -> getAddressSpace ( ) ; assert ( VRegs [ i ] . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ByRefAS == <ISA_LIT>AS :: CONSTANT_ADDRESS ) { lowerParameterPtr ( VRegs [ i ] [ <NUM_LIT> ] , B , ArgTy , ArgOffset ) ; } else { const LLT ConstPtrTy = LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ; Register PtrReg = MRI . createGenericVirtualRegister ( ConstPtrTy ) ; lowerParameterPtr ( PtrReg , B , ArgTy , ArgOffset ) ; B . buildAddrSpaceCast ( VRegs [ i ] [ <NUM_LIT> ] , PtrReg ) ; } } else { ArrayRef < Register > OrigArgRegs = VRegs [ i ] ; Register ArgReg = OrigArgRegs . size ( ) == <NUM_LIT> ? OrigArgRegs [ <NUM_LIT> ] : MRI . createGenericVirtualRegister ( getLLTForType (


<s> static Optional < Instruction * > instCombineSVELD1 ( InstCombiner & IC , IntrinsicInst & II , const DataLayout & DL ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; Value * Pred = II . getOperand ( <NUM_LIT> ) ; Value * PtrOp = II . getOperand ( <NUM_LIT> ) ; Type * VecTy = II . getType ( ) ; Value * VecPtr = Builder . CreateBitCast ( PtrOp , VecTy -> getPointerTo ( ) ) ; if ( isAllActivePredicate ( Pred ) ) { LoadInst * Load = Builder . CreateLoad ( VecTy , VecPtr ) ; return IC . replaceInstUsesWith ( II


<s> static rtx rs6000_tls_get_addr ( void ) { if ( ! rs6000_tls_symbol ) rs6000_tls_symbol = init_one_libfunc (


<s> const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [ OpIdx ] . RegClass ; if ( RegClass == - <NUM_LIT> ) return


<s> if ( decl == NULL_TREE ) return false ; return lookup_attribute ( attr , DECL_ATTRIBUTES ( decl ) )


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> bool <ISA_LIT>TargetLowering :: hasAndNot ( SDValue Y ) const { EVT VT = Y . getValueType ( ) ; if ( ! VT . isVector ( ) ) return ! isa < ConstantSDNode > ( Y ) && hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT ==


<s> assert ( TokPercent . is ( AsmToken :: Percent ) && <STR_LIT> ) ; StartLoc = TokPercent . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterName ( LowercaseString ( Tok . getString ( ) ) ) ; if ( ! is64BitMode ( ) ) { if ( RegNo == <STR_LIT> || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) || <STR_LIT> ( RegNo ) || <STR_LIT> ( RegNo ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> + Tok . getString ( ) + <STR_LIT> ) ; } if ( RegNo == <NUM_LIT> && ( Tok . getString ( ) == <STR_LIT> || Tok . getString ( ) == <STR_LIT> ) ) { RegNo = <STR_LIT> ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return false ; getParser ( ) . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo =


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return true ; } if ( isStringOfOnes ( Mask ^ allOnes ( BitSize ) , LSB , Length ) ) { assert ( LSB > <NUM_LIT> && <STR_LIT> ) ; assert ( LSB + Length <


<s> uint8x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a )


<s> Register IndexReg = LeaI -> getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; Register AluDestReg = AluI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator CurInst = std :: next ( LeaI ) ; while ( CurInst != AluI ) { for ( unsigned I = <NUM_LIT> , E = CurInst -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Opnd = CurInst -> getOperand ( I ) ; if ( ! Opnd . isReg ( ) ) continue ; Register Reg = Opnd . getReg ( ) ; if ( TRI -> regsOverlap ( Reg , AluDestReg ) ) AluDestRef = true ; if ( TRI -> regsOverlap ( Reg , BaseReg ) ) { if ( Opnd . isDef ( ) ) BaseIndexDef = true ; else if ( Opnd . isKill ( ) ) * KilledBase = & Opnd ; } if ( TRI -> regsOverlap ( Reg , IndexReg ) ) { if ( Opnd . isDef ( ) ) BaseIndexDef = true ; else if ( Opnd . isKill ( ) ) * KilledIndex = & Opnd ; } } ++


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return FrameLowering . get (


<s> static const std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > Variants [ ] = { { LatenciesAlone , BlockRegUsageLatency } , { LatenciesGrouped , BlockLatencyRegUsage } , { LatenciesAlonePlusConsecutive , BlockLatencyRegUsage } , } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } if ( Best . MaxVGPRUsage > <NUM_LIT> ) { static const std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > Variants [ ] = { { LatenciesAlone , BlockRegUsage } , { LatenciesGrouped , BlockRegUsageLatency } , { LatenciesGrouped , BlockRegUsage } , { LatenciesAlonePlusConsecutive , BlockRegUsageLatency } , { LatenciesAlonePlusConsecutive , BlockRegUsage } } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } ScheduledSUnits = Best . SUs ; ScheduledSUnitsInv . resize ( SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ( unsigned ) SUnits . size ( ) ; i != e ; ++ i ) { ScheduledSUnitsInv [ ScheduledSUnits [ i ] ] = i ; } moveLowLatencies ( ) ; assert ( TopRPTracker . getPos ( ) == RegionBegin && <STR_LIT> ) ; TopRPTracker . setPos ( CurrentTop ) ; for ( std :: vector < unsigned > :: iterator I = ScheduledSUnits . begin ( ) , E = ScheduledSUnits . end ( ) ; I != E ; ++ I ) { SUnit * SU = & SUnits [ * I ] ; scheduleMI ( SU , true ) ; DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << * SU -> getInstr ( ) ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( )


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMVEVPTOptimisationsPass (


<s> SDValue CC = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( ( SetCCOpcode == <STR_LIT> || SetCCOpcode == <STR_LIT> ) && <STR_LIT> ( Op0 . getNode ( ) ) ) std :: swap ( Op0 , Op1 ) ; if ( SetCCOpcode == <STR_LIT> ) { SetCCOpcode = <STR_LIT> ( SetCCOpcode ) ; std :: swap ( Op0 , Op1


<s> uint64_t getPC32DBLTLSEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return getPCRelEncoding ( MI , OpNum , Fixups


<s> switch ( reg ) { case AMDGPU :: VCC : O << <STR_LIT> ; return ; case AMDGPU :: SCC : O << <STR_LIT> ; return ; case AMDGPU :: EXEC : O << <STR_LIT> ; return ; case AMDGPU :: M0 : O << <STR_LIT> ; return ; default : break ; } char Type ; unsigned NumRegs ; if ( MRI . getRegClass ( AMDGPU :: VGPR_32RegClassID ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( AMDGPU :: SGPR_32RegClassID ) . contains ( reg ) ) { Type = 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( AMDGPU :: VReg_64RegClassID ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( AMDGPU :: SReg_64RegClassID ) . contains ( reg ) ) { Type = 's'


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS <<


<s> static bool mips_vector_mode_supported_p ( enum machine_mode mode ) { switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case V2HImode : case V4QImode : return


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( )


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget (


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const override { llvm_unreachable (


<s> case V16HImode : gen = gen_avx2_pbroadcastv16hi_1 ; break ; case V16SImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16si_1 ; break ; case V8SImode : gen = gen_avx2_pbroadcastv8si_1 ; break ; case V16QImode : gen = gen_avx2_pbroadcastv16qi ; break ; case V8HImode : gen = gen_avx2_pbroadcastv8hi ; break ; case V16SFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16sf_1 ; break ; case V8SFmode : gen = gen_avx2_vec_dupv8sf_1 ; break ; case V8DFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8df_1 ; break ; case V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8di_1 ; break ; default : break ; } if ( gen != NULL ) { if ( ! d -> testing_p ) emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } } if ( expand_vselect ( d -> target , d -> op0 , perm2 , nelt , d -> testing_p ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { perm2 [ i ] = d -> perm [ i ] & mask ; perm2 [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , perm2 , nelt , d -> testing_p ) ) return true ; if ( nelt >= <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { perm2 [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; perm2 [ i + <NUM_LIT> ] = d -> perm [ i + <NUM_LIT> ] & mask ; perm2 [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; perm2 [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , perm2 , nelt , d -> testing_p ) ) return true ; } } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt , d -> testing_p ) ) return true ; if ( ! d -> one_operand_p ) { for ( i = <NUM_LIT> ; i <


<s> static machine_mode aarch64_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_SVE && aarch64_cmp_autovec_modes ( VNx16QImode , V16QImode ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ; if ( TARGET_SIMD ) return aarch64_vq_mode ( mode ) . else_mode ( word_mode ) ; return word_mode


<s> assert ( ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( )


<s> if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { return G -> getGlobal ( )


<s> rtx set , clobber ; gcc_assert ( reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX ) ; fprintf ( stderr , <STR_LIT> , line , store_p ? <STR_LIT> : <STR_LIT> ) ; if ( store_p ) set = gen_rtx_SET ( mem , reg ) ; else set = gen_rtx_SET ( reg , mem


<s> return ( __m64 ) __builtin_arm_wabsh (


<s> bool <ISA_LIT>DAGToDAGISel :: selectADDRzri ( SDValue Addr , SDValue & Base , SDValue & Index


<s> is<ISA_LIT>CtrInstruction ( const MachineInstr *


<s> for ( const auto & I : IFMap ) { dbgs ( ) << <STR_LIT> << printReg ( I . first , HRI ) << <STR_LIT> ; const IFListType & LL = I . second ; for ( const auto & J : LL ) dbgs ( ) << <STR_LIT> << PrintIFR ( J . first , HRI ) << <STR_LIT>

<< PrintRegSet ( J . second , HRI ) << '\n' ;


<s> unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , <NUM_LIT> ) . exists ( & mode ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode ,


<s> if ( BasicBlock * PH = L -> getLoopPreheader ( ) ) return PH ; if ( ! OptSpeculate


<s> if ( Op1 . isReg ( ) && Register :: isVirtualRegister ( Op1 . getReg ( ) ) ) { if ( Op1 . isUndef ( ) ) return nullptr ; RSR = getRegSubRegPair ( Op1 ) ; DefInst = MRI . getVRegDef ( RSR . Reg ) ; } break ; } default : if ( followSubRegDef ( * MI , RSR


<s> bool isMemVY64 ( ) const { return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg (


<s> unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack


<s> return getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT> ) ) + getMachineOpValue ( MI , MI


<s> return isImmediate < <NUM_LIT> , <NUM_LIT> > (


<s> SDValue Bitcast = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , SrcVT , Src ) ; SDValue Sext = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DestVT , Bitcast ) ; SDValue ShuffleVec = DAG . getVectorShuffle ( DestVT , SDLoc ( N ) ,

Sext , DAG . getUNDEF ( DestVT ) , Mask ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64Bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM

) , getEffectiveCodeModel ( CM ) , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Is64Bit ( is64Bit ) {


<s> if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return false ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to

) > GET_MODE_SIZE ( from ) ) return false ;


<s> Record . push_back ( VE . getMetadataOrNullID ( N -> getRawName ( ) ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getRawLinkageName ( ) ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getFile ( ) ) ) ; Record . push_back ( N -> getLine ( ) ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getType ( ) ) ) ; Record . push_back ( N -> isLocalToUnit ( ) ) ; Record . push_back ( N -> isDefinition ( ) ) ; Record . push_back ( <NUM_LIT> ) ; Record . push_back ( VE . getMetadataOrNullID ( N -> getStaticDataMemberDeclaration ( ) ) ) ; Stream . EmitRecord ( bitc :: METADATA_GLOBAL_VAR , Record , Abbrev ) ; Record . clear


<s> SDValue Ops [ ] = { Dst , Src , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops ) ; return true ; } uint64_t Mask0Imm , Mask1Imm ; SDValue And0 = N -> getOperand ( <NUM_LIT> ) ; SDValue And1 = N -> getOperand ( <NUM_LIT> ) ; if ( And0 . hasOneUse ( ) && And1 . hasOneUse ( ) && isOpcWithIntImmediate ( And0 . getNode ( ) , <STR_LIT> , Mask0Imm ) && isOpcWithIntImmediate ( And1 . getNode ( ) , <STR_LIT> , Mask1Imm ) && APInt ( BitWidth , Mask0Imm ) == ~ APInt ( BitWidth , Mask1Imm ) && ( isShiftedMask ( Mask0Imm , VT ) || isShiftedMask ( Mask1Imm , VT ) ) ) { if ( isShiftedMask ( Mask0Imm , VT ) ) { std :: swap ( And0 , And1 ) ; std :: swap ( Mask0Imm , Mask1Imm ) ; } SDValue Src = And1 -> getOperand ( <NUM_LIT> ) ; SDValue Dst = And0 -> getOperand ( <NUM_LIT> ) ; unsigned LSB = countTrailingZeros ( Mask1Imm ) ; int Width = BitWidth - APInt ( BitWidth , Mask0Imm ) . countPopulation ( ) ; SDLoc DL ( N ) ; unsigned ShiftOpc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; uint64_t LsrImm = LSB ; if ( Src -> hasOneUse ( ) && isOpcWithIntImmediate ( Src . getNode ( ) , <STR_LIT> , LsrImm ) && ( LsrImm + LSB ) < BitWidth ) { Src = Src -> getOperand ( <NUM_LIT> ) ; LsrImm += LSB ; } SDNode * LSR = CurDAG -> getMachineNode ( ShiftOpc , DL , VT , Src , CurDAG -> getTargetConstant ( LsrImm , DL , VT ) , CurDAG -> getTargetConstant ( BitWidth - <NUM_LIT> , DL , VT ) ) ; unsigned ImmR = ( BitWidth - LSB ) % BitWidth ; unsigned ImmS = Width - <NUM_LIT> ; SDValue Ops [ ] = { Dst , SDValue ( LSR , <NUM_LIT> ) , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops ) ; return true ; } return false


<s> if ( C -> AntiDepMode == TargetSubtargetInfo :: AntiDepBreakMode :: ANTIDEP_ALL ) { AntiDepBreak = createAggressiveAntiDepBreaker ( MF , * C -> RegClassInfo , C -> CriticalPathRCs ) ; } else if ( C -> AntiDepMode == TargetSubtargetInfo :: AntiDepBreakMode :: ANTIDEP_CRITICAL ) { AntiDepBreak = createCriticalAntiDepBreaker ( MF , * C


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <NUM_LIT> ) ; MAI -> addInitialFrameState (


<s> void <ISA_LIT>MCAsmStreamer :: EmitValueWithAlignment ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { const char * Directive = nullptr ; switch ( Size ) { default : break ; case <NUM_LIT> : Directive = MAI -> getData8bitsDirective ( ) ; break ; case <NUM_LIT> : Directive = MAI -> getData16bitsDirective


<s> MachineInstr * Inst = NULL ; if ( stackFrameSize ) { assert ( isUInt < <NUM_LIT> > ( stackFrameSize ) && <STR_LIT> ) ; DebugLoc DL = ( MI != MBB . end ( ) ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; const TargetInstrInfo & TII = * STC . getInstrInfo ( ) ; Inst = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opcode


<s> const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) &&


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass < <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn


<s> bool <ISA_LIT>DagToDagISel :: SelectAddr ( SDNode * Parent , SDValue Addr , SDValue & Base , SDValue & Offset ) { return


<s> FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> addFnAttr ( llvm :: Attribute :: Naked ) ; FStub -> addFnAttr ( llvm :: Attribute :: NoUnwind ) ; FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; InlineAsmHelper IAH ( Context , BB ) ; IAH . Out ( <STR_LIT> ) ; if ( PicMode ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; IAH . Out ( <STR_LIT> + LocalName ) ; } else IAH . Out ( <STR_LIT> + Name ) ; swapFPIntParams ( PV , M , IAH , LE , false ) ; IAH . Out (


<s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; break ; } return


<s> outs ( ) << <STR_LIT> ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBBE = MF . end ( ) ; MBB != MBBE ; ++ MBB ) { for ( MachineBasicBlock :: iterator MI = MBB -> begin ( ) , ME = MBB -> getFirstTerminator ( ) ; MI != ME ; ++ MI ) { outs ( ) << <STR_LIT> ; MI -> print ( outs ( ) , & ( MF . getTarget ( ) )


<s> bool <ISA_LIT>AbstractMemberAccess :: IsValidAIChain ( const MDNode * ParentType , uint32_t ParentAI , const MDNode * ChildType ) { if ( ! ChildType ) return true ; const DIType * PType = stripQualifiers ( cast < DIType > ( ParentType ) ) ; const DIType * CType = stripQualifiers ( cast < DIType > ( ChildType ) ) ; if ( isa < DIDerivedType > ( CType ) ) return false ; if ( const auto * PtrTy = dyn_cast < DIDerivedType > ( PType ) ) { if ( PtrTy -> getTag ( ) != dwarf :: DW_TAG_pointer_type ) return false ; return stripQualifiers ( PtrTy -> getBaseType ( ) ) == CType ; } const auto * PTy = dyn_cast < DICompositeType > ( PType ) ; const auto * CTy = dyn_cast < DICompositeType > ( CType ) ; assert ( PTy && CTy && <STR_LIT> ) ; uint32_t PTyTag = PTy -> getTag ( ) ; assert ( PTyTag == dwarf :: DW_TAG_array_type || PTyTag == dwarf :: DW_TAG_structure_type || PTyTag == dwarf :: DW_TAG_union_type ) ; uint32_t CTyTag = CTy -> getTag ( ) ; assert ( CTyTag == dwarf :: DW_TAG_array_type || CTyTag == dwarf :: DW_TAG_structure_type || CTyTag == dwarf :: DW_TAG_union_type ) ; if ( PTyTag == dwarf :: DW_TAG_array_type && PTyTag == CTyTag ) return PTy -> getBaseType ( ) == CTy -> getBaseType ( ) ; DIType * Ty ; if ( PTyTag == dwarf :: DW_TAG_array_type )


<s> virtual const <ISA_LIT>BaseInstrInfo * getInstrInfo


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget


<s> static rtx gen_gpr_to_xmm_move_src ( enum machine_mode vmode , rtx gpr ) { switch ( GET_MODE_NUNITS ( vmode ) ) { case <NUM_LIT> : return gen_rtx_SUBREG ( vmode , gpr , <NUM_LIT> ) ; case <NUM_LIT> : return gen_rtx_VEC_CONCAT ( vmode , gpr , CONST0_RTX ( GET_MODE_INNER ( vmode ) )


<s> FunctionPass * llvm :: create<ISA_LIT>HWWA2 ( ) { return new <ISA_LIT>HWWA2 (


<s> unsigned Offset0 = TII -> getNamedOperand ( * I , AMDGPU :: OpName :: offset ) -> getImm ( ) & <NUM_LIT> ; unsigned Offset1 = TII -> getNamedOperand ( * Paired , AMDGPU :: OpName :: offset ) -> getImm ( ) & <NUM_LIT> ; unsigned NewOffset0 = Offset0 / EltSize ; unsigned NewOffset1 = Offset1 / EltSize ; unsigned Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_WRITE2_B32 : AMDGPU :: DS_WRITE2_B64 ; bool UseST64 = ( NewOffset0 % <NUM_LIT> == <NUM_LIT> ) && ( NewOffset1 % <NUM_LIT> == <NUM_LIT> ) ; if ( UseST64 ) { NewOffset0 /= <NUM_LIT> ; NewOffset1 /= <NUM_LIT> ; Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_WRITE2ST64_B32 : AMDGPU :: DS_WRITE2ST64_B64 ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Write2Desc = TII -> get


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; return


<s> for ( rn = <NUM_LIT> ; rn < FIRST_PSEUDO_REGISTER ; rn ++ ) if ( class_contents [ rclass ] [ <NUM_LIT> ] & ( <NUM_LIT> << rn ) ) if ( ! m32c_hard_regno_ok ( rn , to ) ) return <NUM_LIT> ; if ( to == QImode ) return ( class_contents [ rclass ] [ <NUM_LIT> ] & <NUM_LIT>


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FeatureDummy ( false ) { ParseSubtargetFeatures ( CPU , CPU


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML ) ) dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ; for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> ; ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA , * TRI , * TII ) ; if ( LoLoop . Preheader ) LoLoop . Start = SearchForStart ( LoLoop . Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = LoLoop . Dec = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> } const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * ( FuncInfo . MF ) ) ; unsigned SrcReg = FramePtr ; unsigned DestReg ; unsigned Depth = cast < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } updateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MTI . getAlignment ( ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len , Alignment ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace


<s> return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G1_NC , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC

, <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC } ) ;


<s> MachineBasicBlock * CmpParent = CmpInstr . getParent ( ) ; if ( MI . getParent ( ) != CmpParent ) return None ; if ( areCFlagsAliveInSuccessors ( CmpParent ) ) return None ; UsedNZCV NZCVUsedAfterCmp ; for ( MachineInstr & Instr : instructionsWithoutDebug ( std :: next ( CmpInstr . getIterator ( ) ) , CmpParent -> instr_end ( ) ) ) { if ( Instr . readsRegister ( <STR_LIT> , & TRI ) ) { <STR_LIT> CC = findCondCodeUsedByInstr ( Instr ) ; if ( CC == <STR_LIT> ) return None ; NZCVUsedAfterCmp |= getUsedNZCV ( CC ) ; if ( CCUseInstrs ) CCUseInstrs -> push_back ( & Instr ) ; } if ( Instr . modifiesRegister ( <STR_LIT> , & TRI


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; Chain = DAG . getCopyToReg ( StackPointer . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , Sub , SDValue ( ) ) ; SDVTList VTLs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ptr = DAG . getFrameIndex ( <ISA_LIT>FI -> getDynAllocFI ( ) , getPointerTy ( ) ) ; SDValue Ops [ ] = { Chain , Ptr , Chain . getValue ( <NUM_LIT>


<s> assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , MaybeAlign

( Alignment ) , AddressSpace , CostKind ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; if ( FlagSfiLoad ) Modified |= SandboxLoadsInBlock ( MBB ) ; if ( FlagSfiStore ) Modified |= SandboxStoresInBlock ( MBB ) ; if ( FlagSfiBranch ) Modified |= SandboxBranchesInBlock


<s> if ( DEBUG_INSN_P ( insn ) ) return more ; rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER ) return more ; if ( get_attr_type ( insn ) == TYPE_NO_INSN


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { int AssemblerDialect = Ctx . getAsmInfo ( ) -> getAssemblerDialect ( ) ; return new ( Ctx ) <ISA_LIT>MCExpr ( Kind


<s> } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal ==


<s> default : return <NUM_LIT> ; case MCCFIInstruction :: OpDefCfaRegister : { HasFP = true ; if ( MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) != ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) return <NUM_LIT> ; memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; StackAdjust = <NUM_LIT> ; SavedRegIdx = <NUM_LIT> ; InstrOffset += MoveInstrSize ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { PrevStackSize = StackSize ; StackSize = std :: abs ( Inst . getOffset ( ) ) / StackDivide ; ++ NumDefCFAOffsets ; break ; } case MCCFIInstruction :: OpOffset : { if ( SavedRegIdx == CU_NUM_SAVED_REGS ) return CU :: UNWIND_MODE_DWARF ; unsigned Reg = MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; SavedRegs [ SavedRegIdx ++ ] = Reg ; StackAdjust += OffsetSize ; InstrOffset += PushInstrSize ( Reg ) ; break ; } } } StackAdjust /= StackDivide ; if ( HasFP ) { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame ( ) ; if ( RegEnc == ~ <NUM_LIT> ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_BP_FRAME ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= RegEnc & CU :: UNWIND_BP_FRAME_REGISTERS ; } else { if ( ( NumDefCFAOffsets == SavedRegIdx + <NUM_LIT> && StackSize - PrevStackSize == <NUM_LIT> ) || ( Instrs . size ( ) == <NUM_LIT> && NumDefCFAOffsets == <NUM_LIT> && StackSize == <NUM_LIT> ) ) return CU :: UNWIND_MODE_DWARF ; SubtractInstrIdx += InstrOffset ; ++ StackAdjust


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF .


<s> case <NUM_LIT> : return in ? <NUM_LIT> : <NUM_LIT> ; default : return ( GET_MODE_SIZE ( mode ) / <NUM_LIT> ) * ( in ?


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! <ISA_LIT>InstrInfo :: hasShiftedReg ( * FirstMI ) ; case <STR_LIT> : return true ; } if ( ST . hasFuseAES ( ) ) switch ( SecondOpcode ) { case <STR_LIT> : case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; } if ( ST . hasFuseLiterals ( ) ) switch ( SecondOpcode ) { case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; case <STR_LIT> : return ( FirstOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || FirstOpcode == <STR_LIT> ; case <STR_LIT> : return FirstOpcode == <STR_LIT> || ( FirstOpcode == <STR_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( FirstOpcode == <STR_LIT> && FirstMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; } if ( ST . hasFuseAddress ( ) ) { if ( ( FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ) && ( ( SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> || SecondOpcode == <STR_LIT> ) && ( FirstOpcode != <STR_LIT> || SecondMI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) ) return true ; } return false


<s> SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , SrcVal ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( SrcVal . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ; if ( Op . getValueType ( ) != <STR_LIT> ) return Op ; return SDValue (


<s> return ( __m512i ) __builtin_ia32_blendmd_512_mask ( ( __v16si ) __A , ( __v16si )


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) , Streamer ( S ) , Os ( STI . getTargetTriple ( ) . getOS ( ) ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; EFlags &= ~ ELF :: EF_<ISA_LIT>_MACH ; EFlags |= getElfMach ( STI . getCPU ( ) ) ; EFlags &= ~ ELF :: EF_<ISA_LIT>_XNACK ; if ( <STR_LIT> ( STI ) ) EFlags |= ELF :: EF_<ISA_LIT>_XNACK ; EFlags &= ~ ELF :: EF_<ISA_LIT>_SRAM_ECC ; if ( <STR_LIT> ( STI ) ) EFlags |= ELF


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; return isExpImmValue < shift > ( CE ->


<s> return ( __m128i ) __builtin_ia32_vpcomgtb ( ( __v16qi ) __A , ( __v16qi )


<s> std :: pair < unsigned , unsigned > getFlatWorkGroupSizes ( )


<s> const MachineOperand ImmOp = AddMI -> getOperand ( <NUM_LIT> ) ; const MachineOperand AddRegOp = AddMI -> getOperand ( <NUM_LIT> ) ; unsigned newReg = AddRegOp . getReg ( ) ; const MCInstrDesc & MID = UseMI -> getDesc ( ) ; MachineOperand & BaseOp = MID . mayLoad ( ) ? UseMI -> getOperand ( <NUM_LIT> ) : UseMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & OffsetOp = MID . mayLoad ( ) ? UseMI -> getOperand ( <NUM_LIT> ) : UseMI -> getOperand ( <NUM_LIT> ) ; BaseOp . setReg ( newReg ) ; BaseOp . setIsUndef ( AddRegOp . isUndef ( )


<s> SMLoc S = getLoc ( ) ; if ( ! parseId ( Str ) ) return MatchOperand_NoMatch ; uint8_t Val ; auto Res = parseExpTgtImpl ( Str , Val ) ; if ( Res !=


<s> std :: string AMDGPUSubtarget :: getDeviceName


<s> auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; assert ( TPC && <STR_LIT> <STR_LIT> ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; TM = & TPC -> getTM < TargetMachine > ( ) ; Is64Bit = TM -> getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ; if ( ! llvm :: any_of ( M , [ & ] ( const Function & F ) { STI = & TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return STI -> useRetpoline ( ) && ! STI -> useRetpolineExternalThunk ( ) ; } ) ) return false ; TII = STI -> getInstrInfo ( ) ; if ( Is64Bit ) { createThunk ( M , <STR_LIT> , <STR_LIT> ) ; } else { createThunk ( M , <STR_LIT> , <STR_LIT> ) ; createThunk ( M , <STR_LIT> , <STR_LIT> ) ; createThunk ( M , <STR_LIT> , <STR_LIT> ) ; createThunk ( M , <STR_LIT> ) ; } return


<s> if ( ! Subtarget -> hasAVX ( ) ) return false ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || NumElts != <NUM_LIT> ) return false ; int LaneSize = NumElts / NumLanes ; for ( int l = <NUM_LIT> ; l < NumLanes ; ++ l ) for ( int i = l * LaneSize ; i < LaneSize * ( l + <NUM_LIT> ) ; ++ i ) { int LaneStart = l * LaneSize ; if ( ! isUndefOrInRange ( Mask [ i ] , LaneStart , LaneStart + LaneSize


<s> bool <ISA_LIT>TargetLowering :: shouldFoldConstantShiftPairToMask ( const SDNode * N , CombineLevel Level ) const { if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( )


<s> return Type :: getInt32Ty ( F . getContext ( )


<s> } if ( MFI -> isEntryFunction ( ) ) { get<ISA_LIT>ProgramInfo ( CurrentProgramInfo , MF ) ; } else { auto I = CallGraphResourceInfo . insert ( std :: make_pair ( & MF . getFunction ( ) , <ISA_LIT>FunctionResourceInfo ( ) ) ) ; <ISA_LIT>FunctionResourceInfo & Info = I . first -> second ; assert ( I . second && <STR_LIT> ) ; Info = analyzeResourceUsage ( MF ) ; } if ( STM . isAmdPalOS ( ) ) EmitPALMetadata ( MF , CurrentProgramInfo ) ; else if ( ! STM . isAmdHsaOS ( ) ) { EmitProgramInfo<ISA_LIT> ( MF , CurrentProgramInfo ) ; } DumpCodeInstEmitter = nullptr ; if ( STM . dumpCode ( ) ) { bool SaveFlag = OutStreamer -> getUseAssemblerInfoForParsing ( ) ; OutStreamer -> setUseAssemblerInfoForParsing ( true ) ; MCAssembler * Assembler = OutStreamer -> getAssemblerPtr ( ) ; OutStreamer -> setUseAssemblerInfoForParsing ( SaveFlag ) ; if ( Assembler ) DumpCodeInstEmitter = Assembler -> getEmitterPtr ( ) ; } DisasmLines . clear ( ) ; HexLines . clear ( ) ; DisasmLineMaxLen = <NUM_LIT> ; EmitFunctionBody ( ) ; if ( isVerbose ( ) ) { MCSectionELF * CommentSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( CommentSection ) ; if ( ! MFI -> isEntryFunction ( ) ) { OutStreamer -> emitRawComment ( <STR_LIT> , false ) ; <ISA_LIT>FunctionResourceInfo & Info = CallGraphResourceInfo [ & MF . getFunction ( ) ] ; emitCommonFunctionComments ( Info . NumVGPR , Info . getTotalNumSGPRs ( MF . getSubtarget < GCNSubtarget > ( ) ) , Info . PrivateSegmentSize , getFunctionCodeSize ( MF ) , MFI ) ; return false ; } OutStreamer -> emitRawComment ( <STR_LIT> ,


<s> return m16_check_op ( op , ( - <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> << <NUM_LIT>


<s> mHWBits . set ( <STR_LIT> ) ; } mSWBits . set ( <STR_LIT> ) ; mHWBits . reset ( <STR_LIT> ) ; mSWBits . set ( <STR_LIT>


<s> if ( FBB == nullptr ) FBB = MBB . getFallThrough ( ) ; if ( TBB == FBB ) return false ; assert ( MBB . succ_size ( ) == <NUM_LIT> ) ; assert ( analyzeBranchCondCode . size ( ) ==


<s> bool <ISA_LIT>InstrInfo :: isTC4x ( const MachineInstr & MI


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint64_t OptimalCount = ( Count < <NUM_LIT> ) ? Count : <NUM_LIT> ; const uint64_t Prefixes = OptimalCount <= <NUM_LIT> ? <NUM_LIT> : OptimalCount - <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> , e = Prefixes ; i != e ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint64_t Rest = OptimalCount - Prefixes ; for ( uint64_t i = <NUM_LIT> , e = Rest ; i != e ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; for ( uint64_t i = OptimalCount , e = Count ; i != e ; ++ i ) OW


<s> } } else { for ( i = low ; i < high ; i += <NUM_LIT> ) { bool reg0 = save_p ( i , leaf_function ) ; bool reg1 = save_p ( i + <NUM_LIT> , leaf_function ) ; machine_mode mode ; int regno ; if ( reg0 && reg1 ) { mode = SPARC_INT_REG_P ( i ) ? E_DImode : E_DFmode ; regno = i ; } else if ( reg0 ) { mode = SPARC_INT_REG_P ( i ) ? E_SImode : E_SFmode ; regno = i ; } else if ( reg1 ) { mode = SPARC_INT_REG_P ( i ) ? E_SImode : E_SFmode ; regno = i + <NUM_LIT> ; offset += <NUM_LIT> ; } else { if ( action_false == SORR_ADVANCE ) offset += <NUM_LIT> ; continue ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base , offset ) ) ; if ( action_true == SORR_SAVE ) { insn = emit_move_insn ( mem , gen_rtx_REG ( mode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( mode == DImode ) { rtx set1 , set2 ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset ) ) ; set1 = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , regno ) ) ; RTX_FRAME_RELATED_P ( set1 )


<s> EVT PtrVT = getPointerTy ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false


<s> Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str . size ( ) ; return Res


<s> static bool ck803_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case SET : if ( MEM_P ( XEXP ( x , <NUM_LIT> ) ) ) { struct csky_address op1 ; bool address_valid = decompose_csky_address ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , & op1 ) ; if ( op1 . index ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else if ( address_valid ) { * total = COSTS_N_INSNS ( <NUM_LIT> )


<s> break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fputs ( reg_names [ REGNO ( x ) + <NUM_LIT> ] , ( stream ) ) ; break ; case MEM : mcore_print_operand_address ( stream , XEXP ( adjust_address ( x , SImode , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; default : gcc_unreachable ( ) ; } break ; case 'U' : fprintf ( asm_out_file , <STR_LIT> , reg_names [ REGNO ( x ) ] , reg_names [ REGNO ( x ) + <NUM_LIT> ] ) ; break ; case 'x' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; break ; case 'X' : fprintf ( asm_out_file , HOST_WIDE_INT_PRINT_DEC , <NUM_LIT> - INTVAL ( x ) /


<s> const <ISA_LIT>ELFAttributeData & <ISA_LIT>GNULDBackend :: getAttributeData ( ) const { assert ( m_pAttrData != NULL &&


<s> } if ( VT . isFloatingPoint ( ) && ! TLI -> isOperationLegalOrCustom ( ISD , VT ) ) return true ; return false ; } ; auto IsHardwareLoopIntrinsic = [ ] ( Instruction & I ) { if ( auto * Call = dyn_cast < IntrinsicInst > ( & I ) ) { switch ( Call -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } return false ; } ; bool hasInnerHardwareLoop = false ; auto ScanLoop = [ & ] ( Loop * L ) { for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : BB -> instructionsWithoutDebug ( ) ) { hasInnerHardwareLoop |= IsHardwareLoopIntrinsic ( I ) ; if ( MaybeCall ( I ) ) { return false ; } } } return true ; } ; for ( auto Inner : * L ) if ( ! ScanLoop ( Inner ) ) return false ; if ( ! ScanLoop ( L ) ) return false ; LLVMContext & C = L -> getHeader ( ) ->


<s> vld1q_dup_p8 ( const poly8_t * __a ) { return vdupq_n_p8 ( *


<s> bool ELF<ISA_LIT>AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == <STR_LIT> ) return true ; return false


<s> return ( int16x4_t ) __builtin_aarch64_sqaddv4hi (


<s> bool <ISA_LIT>TargetLowering :: lowerInterleavedLoad ( LoadInst * LI , ArrayRef < ShuffleVectorInst * > Shuffles , ArrayRef < unsigned > Indices , unsigned Factor ) const { assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * EltTy = VecTy -> getVectorElementType ( ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; unsigned VecSize = DL . getTypeAllocSizeInBits ( VecTy ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( VecSize != <NUM_LIT> && VecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getVectorNumElements ( ) ) ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; IRBuilder < > Builder ( LI ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( LI -> getPointerOperand ( ) , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; CallInst * VldN = Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SV = Shuffles [ i


<s> if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) ,


<s> const unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & Desc = MII . get ( Opc ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <NUM_LIT> ) return true ; int DMaskIdx = <STR_LIT> ( Opc


<s> static void getPackDemandedElts ( EVT VT , const APInt & DemandedElts , APInt & DemandedLHS , APInt & DemandedRHS ) { int NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; int NumElts = DemandedElts . getBitWidth ( ) ; int NumInnerElts = NumElts / <NUM_LIT> ; int NumEltsPerLane = NumElts / NumLanes ; int NumInnerEltsPerLane = NumInnerElts /


<s> bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; assert ( SpillToVGPR || ( SuperReg != MFI -> getStackPtrOffsetReg ( ) && SuperReg != MFI -> getFrameOffsetReg ( ) ) ) ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; assert ( SuperReg != <STR_LIT> && SuperReg != <STR_LIT> && SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; if ( SpillToVGPR ) { for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } } else { Register TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpVGPR ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; unsigned PerVGPR = <NUM_LIT> ; unsigned NumVGPRs = ( NumSubRegs + ( PerVGPR - <NUM_LIT> ) ) / PerVGPR ; int64_t VGPRLanes = ( <NUM_LIT> << std :: min ( PerVGPR , NumSubRegs ) ) - <NUM_LIT> ; for ( unsigned Offset = <NUM_LIT> ; Offset < NumVGPRs ;


<s> <ISA_LIT>PropagateAttributesEarly ( const TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , TM ( TM


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp =


<s> bool hasEnhancedSort ( ) const { return HasEnhancedSort


<s> SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsAllZero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( VT != <STR_LIT> || ! Subtarget -> hasAVX2 ( ) || ( ! V2IsUndef && ! V2IsAllZero && ! V1IsAllZero ) ) return SDValue ( ) ; if ( V1IsAllZero && ! V2IsAllZero ) { CommuteVectorShuffleMask ( MaskVals , <NUM_LIT> ) ; V1 = V2 ; } SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i ++ ) { int EltIdx = MaskVals [ i ] ; if ( EltIdx < <NUM_LIT> || EltIdx >= <NUM_LIT> ) EltIdx


<s> gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode


<s> addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_64RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_128RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_256RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: VReg_512RegClass ) ; computeRegisterProperties ( ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> ,


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>Operand :: createMemOp ( <ISA_LIT>MemOp MemOp ,


<s> return MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> )


<s> } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = DImode ; gen_func . mov = gen_movdi ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } addr = XEXP ( orig_src , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_src = replace_equiv_address ( orig_src , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = SImode ; gen_func . mov = gen_movsi ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = HImode ; gen_func . mov = gen_movhi ; } else { move_bytes = <NUM_LIT> ; mode = QImode ; gen_func . mov = gen_movqi ; } src = adjust_address ( orig_src , mode , offset ) ; dest = adjust_address ( orig_dest , mode , offset ) ; if ( mode != BLKmode ) { rtx tmp_reg = gen_reg_rtx ( mode ) ; emit_insn ( ( * gen_func . mov ) ( tmp_reg , src ) ) ; stores [ num_reg ++ ] = ( * gen_func . mov ) ( dest , tmp_reg ) ; } if ( mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes ) { int i ; for ( i = <NUM_LIT> ; i < num_reg ; i ++ ) emit_insn ( stores [ i ] ) ; num_reg = <NUM_LIT> ; } if ( mode == BLKmode ) { if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) ) { rtx src_reg = copy_addr_to_reg ( XEXP ( src , <NUM_LIT> ) ) ; src = replace_equiv_address ( src , src_reg ) ; } set_mem_size ( src , move_bytes ) ; if ( ! REG_P ( XEXP ( dest , <NUM_LIT> ) ) ) { rtx dest_reg = copy_addr_to_reg ( XEXP ( dest , <NUM_LIT> ) ) ; dest = replace_equiv_address ( dest ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const <ISA_LIT>Z80InstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; assert ( Amount == <NUM_LIT> && <STR_LIT> ) ; if ( Amount != <NUM_LIT> ) { assert ( TFI . getStackAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { fixStackStores ( MBB , MI , TII , true ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT>

) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF )


<s> unsigned Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) ; ++


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_ADDR : case VK_<ISA_LIT>_PCREL : case VK_<ISA_LIT>_GOT


<s> bool hasFineGrainedTraps ( ) const { return


<s> void GCNPassConfig :: addPostRegAlloc ( ) { addPass ( &


<s> static bool isAllActivePredicate ( Value * Pred ) { Value * UncastedPred ; if ( match ( Pred , m_Intrinsic < <STR_LIT> > ( m_Intrinsic < <STR_LIT> > ( m_Value ( UncastedPred ) ) ) ) ) if ( cast < ScalableVectorType > ( Pred -> getType ( ) ) -> getMinNumElements ( ) <= cast < ScalableVectorType > ( UncastedPred -> getType

( ) ) -> getMinNumElements ( ) ) Pred = UncastedPred ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( NumBytes == <NUM_LIT>


<s> assert ( Kind == k_MatrixRegister && <STR_LIT> ) ; return MatrixReg .


<s> if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; else if ( Value > <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> )


<s> return Error ( ErrorLoc , <STR_LIT> ) ; } } if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( Result ) { default : break ; case Match_RequiresMsbNotLessThanLsb : { SMLoc ErrorStart = Operands [ <NUM_LIT> ] -> getStartLoc ( ) ; return Error ( ErrorStart , <STR_LIT> , SMRange ( ErrorStart , Operands [ <NUM_LIT> ] -> getEndLoc ( ) ) ) ; } case Match_RequiresOpnd2NotR0R1 : return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; case Match_InvalidUImm2 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm2plus1 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) ) ; case Match_InvalidUImm3 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; case Match_InvalidUImm15 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> ,


<s> StringRef getPassName ( ) const override { return


<s> void <ISA_LIT>PassConfig :: addOptimizedRegAlloc ( FunctionPass


<s> unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx ; unsigned IncorrectIdx = CorrectIdx ? - <NUM_LIT> : FirstNonZeroIdx ; unsigned IncorrectDst = CorrectIdx ? - <NUM_LIT> : FirstNonZeroDst ; for ( unsigned Idx = FirstNonZeroIdx + <NUM_LIT> ; Idx < NumElems ; ++ Idx ) { SDValue Elem = Op . getOperand ( Idx ) ; if ( Elem . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( Elem ) ) continue ; if ( Elem . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Elem . getOperand ( <NUM_LIT> ) != V ) return SDValue ( ) ; unsigned Dst = cast < ConstantSDNode > ( Elem . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Dst == Idx ) ++ CorrectIdx ; else if ( IncorrectIdx == - <NUM_LIT> ) { IncorrectIdx = Idx ; IncorrectDst = Dst ; } else return SDValue ( )


<s> Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , Chain . getValue (


<s> if ( ! MO1 . isReg ( ) || MO1 . getReg ( ) != <STR_LIT> || MO2 . getReg ( ) || ! MO3 . isImm ( ) ) return None ; unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> Op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( Op == <STR_LIT> ) return Addr


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( val & ( <NUM_LIT> << i ) ) break ; } mask = ( ( <NUM_LIT> >> i ) << <NUM_LIT> ) | <NUM_LIT> ; if ( IS_INT16_CONST ( val & ( <NUM_LIT> << <NUM_LIT> ) ? ( val >> i ) | ~ mask : ( val >> i ) & mask ) ) return i ; return -


<s> Dst = Tmp ; } ) ; if ( Dst != VRegs [ Idx ] ) MIRBuilder . buildCopy ( VRegs [ Idx ] , Dst ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_<ISA_LIT> , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return


<s> for ( unsigned i = <NUM_LIT> ; i < PHI . getNumOperands ( ) ; i += <NUM_LIT> ) { unsigned Reg = PHI . getOperand ( i ) . getReg ( ) ; if ( Visited . count ( Reg ) ) continue ; Visited . insert ( Reg ) ; MachineInstr * DefInstr = MRI . getVRegDef ( Reg ) ; switch ( DefInstr -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>FastISel :: finishCall ( CallLoweringInfo & CLI , MVT RetVT , unsigned NumBytes ) { CallingConv :: ID CC = CLI . CallConv ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackUp ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC ) ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . InRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . ResultReg = ResultReg ; CLI . NumResultRegs


<s> output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; } else if ( TARGET_ELF ) fputs ( <STR_LIT> , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return


<s> bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : <NUM_LIT> ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( isDestroy && blockEndIsUnreachable ( MBB , I ) ) return I ; if ( ! reserveCallFrame ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ; if ( StackAdjustment ) { if ( ! ( F . hasMinSize ( ) && adjustStackWithPops ( MBB , InsertPos , DL , StackAdjustment ) ) ) BuildStackAdjustment ( MBB , InsertPos , DL , StackAdjustment , false ) ; } } if ( DwarfCFI && ! hasFP ( MF ) ) { int64_t CfaAdjustment = - StackAdjustment ; if ( CfaAdjustment ) { BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CfaAdjustment ) ) ; } } return


<s> case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; } return false


<s> addPass ( create<ISA_LIT>SinglePathInfoPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SPPreparePass ( get<ISA_LIT>TargetMachine


<s> static DecodeStatus DecodeQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = QQDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> if ( Cond . size ( ) != <NUM_LIT> ) return ; if ( ! Cond [ <NUM_LIT> ] . isReg ( ) ) return ; unsigned CondReg = Cond [ <NUM_LIT> ] . getReg ( ) ; for ( auto UI = MRI -> use_begin ( CondReg ) , E = MRI -> use_end ( )


<s> int RASI = FI -> getReturnAddrSaveIndex ( ) ; if ( ! RASI ) { int LROffset = <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , true , false ) ; FI -> setReturnAddrSaveIndex ( RASI ) ; } return DAG . getFrameIndex ( RASI , PtrVT


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv8hi ( (


<s> if ( decl && TREE_CODE ( decl ) == VAR_DECL && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) flags |= SECTION_PE_SHARED ; } if ( decl && DECL_P ( decl ) && DECL_ONE_ONLY ( decl ) ) flags |= SECTION_LINKONCE ; return


<s> if ( SavedExec == <STR_LIT> ) return nullptr ; auto SaveExecInst = MRI . getUniqueVRegDef ( SavedExec ) ; if ( ! SaveExecInst || ! isFullExecCopy ( * SaveExecInst


<s> InstructionSelector * llvm :: create<ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , <ISA_LIT>Subtarget & Subtarget , <ISA_LIT>RegisterBankInfo & RBI ) { return new <ISA_LIT>InstructionSelector ( TM


<s> for ( MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; } BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; signed Reg = Available . find_first ( ) ; assert ( Reg != - <NUM_LIT>


<s> while ( curr != t -> rbt_nil ) { int cmp = strcmp ( str , curr -> str ) ; if ( cmp < <NUM_LIT> ) curr = curr ->


<s> static bool IsChild ( const MachineInstr * MI , const <ISA_LIT>FunctionInfo & MFI ) { if ( MI -> getNumOperands ( ) == <NUM_LIT> ) return false ; const MachineOperand & MO = MI ->


<s> SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getVectorElementType ( ) ; unsigned SrcEltBits = SrcSVT . getSizeInBits ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; if ( SrcSVT == <STR_LIT> || ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; const APInt & IdxC = N -> getConstantOperandAPInt ( <NUM_LIT> ) ; if ( IdxC . uge ( NumSrcElts ) ) return SDValue ( ) ; SDValue SrcBC = peekThroughBitcasts ( Src ) ; if ( <STR_LIT> == SrcBC . getOpcode ( ) ) { SDValue SrcOp = SrcBC . getOperand ( <NUM_LIT> ) ; EVT SrcOpVT = SrcOp . getValueType ( ) ; if ( SrcOpVT . isScalarInteger ( ) && VT . isInteger ( ) && ( SrcOpVT . getSizeInBits ( ) % SrcEltBits ) == <NUM_LIT> ) { unsigned Scale = SrcOpVT . getSizeInBits ( ) / SrcEltBits ; unsigned Offset = IdxC . urem ( Scale ) * SrcEltBits ; if ( Offset == <NUM_LIT> ) { SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , SrcVT . getScalarType ( ) ) ; SrcOp = DAG . getZExtOrTrunc ( SrcOp , dl , VT ) ; return SrcOp ; } } } if ( SrcBC . getOpcode ( ) == <STR_LIT> && SrcBC . hasOneUse ( ) ) { auto * MemIntr = cast < MemIntrinsicSDNode > ( SrcBC ) ; unsigned SrcBCWidth = SrcBC . getScalarValueSizeInBits ( ) ; if ( MemIntr -> getMemoryVT ( ) . getSizeInBits ( ) == SrcBCWidth && VT . getSizeInBits ( ) == SrcBCWidth && SrcEltBits == SrcBCWidth ) { SDValue Load = DAG . getLoad ( VT , dl , MemIntr -> getChain ( ) , MemIntr -> getBasePtr ( ) , MemIntr -> getPointerInfo ( ) , MemIntr -> getOriginalAlign ( ) , MemIntr -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( MemIntr , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } if ( SrcBC . getOpcode ( ) == <STR_LIT> && VT . isInteger ( ) && SrcBC . getValueType ( ) . isInteger ( ) && ( SrcBC . getScalarValueSizeInBits ( ) % SrcEltBits ) == <NUM_LIT> && SrcBC . getScalarValueSizeInBits ( ) == SrcBC . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) { unsigned Scale = SrcBC . getScalarValueSizeInBits ( ) / SrcEltBits ; if ( IdxC . ult ( Scale ) ) { unsigned Offset = IdxC . getZExtValue ( ) * SrcVT . getScalarSizeInBits ( ) ; SDValue Scl = SrcBC . getOperand ( <NUM_LIT> ) ; EVT SclVT = Scl . getValueType ( ) ; if ( Offset


<s> bool enableMultipleCopyHints ( ) const override { return true


<s> else if ( Reg == <STR_LIT> ) O << ( useABIName ? <STR_LIT> : <STR_LIT> ) ; else if ( Reg == <STR_LIT> ) O << ( useABIName ? <STR_LIT> : <STR_LIT> ) ; else printRegName ( O , Reg ) ; } else printRegName ( O , Reg ) ; return ; } if ( MO . isImm ( ) ) { uint64_t TSFlags = MII . get ( MI -> getOpcode ( ) ) . TSFlags ; if ( ( ( TSFlags & <STR_LIT> ) != <STR_LIT> ) && PrintBranchImmAsAddress )


<s> Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS ) ; SDValue SetCC = getSETCC ( <STR_LIT> , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) , DL , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Sum , SetCC ) ; } } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; SDValue SetCC = getSETCC ( Cond , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) , DL , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList (


<s> unsigned StackSlotSize = <ISA_LIT>FrameLowering :: stackSlotSize ( ) ; unsigned LRSaveSize = StackSlotSize ; SmallVector < SDValue , <NUM_LIT> > CFRegNode ; SmallVector < ArgDataPair , <NUM_LIT> > ArgData ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgIn ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgIn = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; CFRegNode . push_back ( ArgIn . getValue ( ArgIn -> getNumValues ( ) - <NUM_LIT> ) ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > StackSlotSize ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , LRSaveSize + VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgIn = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } const ArgDataPair ADP = { ArgIn , Ins [ i ] . Flags } ; ArgData . push_back ( ADP ) ; } if ( isVarArg ) { static const uint16_t ArgRegs [


<s> bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { InstOffset = BlockToInstOffset [ & MBB ] ; MachineBasicBlock :: iterator MII = MBB . begin ( ) ; MachineBasicBlock :: iterator MIE = MBB . end ( ) ; while ( MII != MIE ) { InstOffset += HII -> getSize ( & * MII ) ; if ( MII -> isDebugValue ( ) ) { ++ MII ; continue ; } if ( isHardwareLoop ( MII ) ) { assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; int diff = InstOffset - BlockToInstOffset [ MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ] ; if ( ( unsigned ) abs ( diff ) > MaxLoopRange ) { useExtLoopInstr ( MF , MII ) ; MII = MBB . erase ( MII ) ; Changed = true ; }


<s> void makeReady ( ready_set & ready , ablock * block ) { ready_block rb ; rb . block =


<s> PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine


<s> MIB . add ( ImmOp ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } else if ( HII -> getAddrMode ( * OldMI ) == <STR_LIT> ) { short NewOpCode = HII -> getAbsoluteForm ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; int64_t Offset = ImmOp . getOffset ( ) + OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addGlobalAddress ( GV , Offset , ImmOp . getTargetFlags ( ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } Changed = true ; DEBUG ( dbgs ( ) << <STR_LIT> << * OldMI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MIB << <STR_LIT> ) ; } else if ( ImmOpNum == <NUM_LIT> && OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { short NewOpCode = HII -> xformRegToImmOffset ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( ImmOp ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; Changed = true ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , DebugLoc dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , MachinePointerInfo ( ) ,


<s> bool isInstRelaxable ( MCInst const & HMI ) const { const MCInstrDesc & MCID = <ISA_LIT>MCInstrInfo :: getDesc ( * MCII , HMI ) ; bool Relaxable = false ; if ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && HMI . getOpcode ( ) != <STR_LIT> ) ) if ( <ISA_LIT>MCInstrInfo :: isExtendable ( * MCII , HMI ) ) { Relaxable =


<s> vec_uint4 ahi_inf ; vec_uint4 anan ; vec_uint4 iszero ; vec_uint4 result ; union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; biteq = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) a , ( vec_uint4 ) b ) ; biteq = vec_and ( biteq , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) biteq , x . v ) ) ; aabs = vec_and ( ( vec_uint4 ) a , sign_mask ) ; babs = vec_and ( ( vec_uint4 ) b , sign_mask ) ; a_gt = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; ahi_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; anan = ( vec_uint4 ) vec_or ( a_gt , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_gt , x .


<s> if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> )


<s> return getPCRelEncoding ( MI , OpNum , Fixups ,


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT>


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass


<s> RTX_FLAG ( new_mem_exp , jump ) = RTX_FLAG ( original_mem_exp , jump ) ; RTX_FLAG ( new_mem_exp , call ) = RTX_FLAG ( original_mem_exp , call ) ; RTX_FLAG ( new_mem_exp , unchanging ) = RTX_FLAG ( original_mem_exp , unchanging ) ; RTX_FLAG ( new_mem_exp , volatil ) = RTX_FLAG ( original_mem_exp , volatil ) ; RTX_FLAG ( new_mem_exp , frame_related ) = RTX_FLAG ( original_mem_exp , frame_related ) ; RTX_FLAG ( new_mem_exp , in_struct ) = RTX_FLAG ( original_mem_exp , in_struct ) ; RTX_FLAG ( new_mem_exp , return_val ) = RTX_FLAG ( original_mem_exp , return_val ) ; struct mem_attrs original_attrs = * get_mem_attrs ( original_mem_exp ) ; alias_set_type set = original_attrs . alias ; set_mem_alias_set ( new_mem_exp , set ) ; addr_space_t addrspace = original_attrs . addrspace ; set_mem_addr_space ( new_mem_exp , addrspace ) ; unsigned int align = original_attrs . align ; set_mem_align ( new_mem_exp , align ) ; tree expr = original_attrs


<s> MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneUse ( CondDefReg ) ) { for ( auto UI = MRI . use_instr_begin ( CondDefReg ) , UE = MRI . use_instr_end ( ) ; UI != UE ; ++ UI ) { if ( CondDef == & * UI ) continue ; if ( UI -> getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { CondCode = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( ! emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else { <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; unsigned CmpOpc = selectFCMPOpc ( * CondDef


<s> if ( memOpsHaveSameBaseOperands ( BaseOps1 , BaseOps2 ) ) return true ; if ( ! MI1 . hasOneMemOperand ( ) || ! MI2 . hasOneMemOperand ( ) ) return false ; auto MO1 = * MI1 . memoperands_begin ( ) ; auto MO2 = * MI2 . memoperands_begin ( ) ; if ( MO1 -> getAddrSpace ( ) != MO2


<s> MCFixupKind Fixup = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getExpr ( ) , Fixup ) ) ; return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; EmitConstant ( Binary , <NUM_LIT> ,


<s> if ( ! RM . hasValue ( ) ) return Reloc :: PIC_ ; return *


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> static void EmitREST ( const llvm :: MCSubtargetInfo & STI , const MCInst & Inst , unsigned Reg32 , bool IsMem , MCStreamer & Out ) { unsigned Reg64 = get<ISA_LIT>SubSuperRegister_ ( Reg32 , <STR_LIT> ) ; Out . EmitBundleLock ( false ) ; if ( ! IsMem ) { EmitMoveRegReg ( STI , false , Reg32 , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , Out ) ; } else { unsigned IndexOpPosition ; MCInst SandboxedInst = Inst ; if ( SandboxMemoryRef ( & SandboxedInst ,


<s> assert ( Factor >= <NUM_LIT> && <STR_LIT> ) ; auto * VecVTy = cast < VectorType > ( VecTy ) ; if ( ! UseMaskForCond && ! UseMaskForGaps && Factor <= TLI -> getMaxSupportedInterleaveFactor ( ) ) { unsigned NumElts = VecVTy -> getNumElements ( ) ; auto * SubVecTy = VectorType :: get ( VecTy

-> getScalarType ( ) , NumElts / Factor ) ;


<s> return ( __m512 ) __builtin_ia32_vfmaddps512_maskz ( ( __v16sf ) __A , ( __v16sf )


<s> bool isNegInlineImmediate ( const SDNode * N


<s> if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOperand ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOperand ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOperand ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOperand ; return ATReg


<s> if ( GET_CODE ( pattern ) != SET ) return false ; src = SET_SRC ( pattern ) ; return ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) ==

UNSPEC && XINT ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_HW1_LAST_PCREL ) ;


<s> bool gate ( function * ) { return TARGET_RELAX_HINT


<s> for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) )


<s> Cond = Cond -> getOperand ( <NUM_LIT> ) ; } isAnd = false ; SDValue SetCC0 , SetCC1 ; switch ( Cond -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : isAnd = true ; case <STR_LIT> : case <STR_LIT> : SetCC0 = Cond -> getOperand ( <NUM_LIT> ) ; SetCC1 = Cond -> getOperand ( <NUM_LIT> ) ; break ; } ; if ( SetCC0 . getOpcode ( ) != <STR_LIT> || SetCC1 . getOpcode ( ) != <STR_LIT> || SetCC0 -> getOperand ( <NUM_LIT> ) != SetCC1 -> getOperand ( <NUM_LIT> ) ) return false ; CC0 = ( <STR_LIT> ) SetCC0 -> getConstantOperandVal ( <NUM_LIT> ) ; CC1 = ( <STR_LIT> ) SetCC1 -> getConstantOperandVal


<s> static unsigned int rest_of_handle_insert_vzeroupper ( void ) { if ( TARGET_VZEROUPPER && flag_expensive_optimizations && ! optimize_size ) { for ( int i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ] = <NUM_LIT> ; g -> get_passes ( ) -> execute_pass_mode_switching ( ) ; } ix86_add_reg_usage_to_vzerouppers ( ) ; return <NUM_LIT>


<s> if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Val ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ) return CreateTLSReg ( SRE , S , E , Is<ISA_LIT>64 ) ; if ( const <ISA_LIT>MCExpr * TE = dyn_cast < <ISA_LIT>MCExpr > ( Val ) ) { int64_t Res ; if ( TE -> EvaluateAsConstant ( Res ) ) return CreateContextImm ( Res , S , E , Is<ISA_LIT>64 ) ; } return CreateExpr ( Val , S , E


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> << r << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> )


<s> ScheduleDAGInstrs * llvm :: create<ISA_LIT>MachineScheduler ( MachineSchedContext * C ) { return new <ISA_LIT>ScheduleDAGMI (


<s> HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 =


<s> const EDInstInfo * <ISA_LIT>GenericDisassembler :: getEDInfo ( )


<s> static bool isSGPRToVGPRCopy ( const TargetRegisterClass * SrcRC , const TargetRegisterClass * DstRC , const <ISA_LIT>RegisterInfo & TRI ) { return DstRC != & <STR_LIT> && TRI . isSGPRClass ( SrcRC ) && TRI . hasVGPRs (


<s> static const LoadStoreMethod PossibleClasses [ ] = { { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; const unsigned NumClasses = llvm :: array_lengthof (


<s> getDirectBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_802 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_805 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_807 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_810 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_860 ; else EFlags |= ELF :: EF_<ISA_LIT>_810 ; if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_FLOAT ; EFlags |= ELF


<s> static unsigned getWFCountLimitedByGPR ( unsigned GPRCount ) { assert ( GPRCount && <STR_LIT> ) ; return <NUM_LIT> /


<s> if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) return N -> getOperand ( <NUM_LIT> ) ; return N