<s> NonZeros |= ( uint64_t ) <NUM_LIT> << i ; ++ NumNonZero ; } } if ( NumNonZero <= <NUM_LIT> ) { SDValue Vec = NumZero ? getZeroVector ( ResVT , Subtarget , DAG , dl ) : DAG . getUNDEF ( ResVT ) ; if ( ! NumNonZero ) return Vec ; unsigned Idx = countTrailingZeros ( NonZeros ) ; SDValue SubVec = Op . getOperand ( Idx ) ; unsigned SubVecNumElts = SubVec . getSimpleValueType ( ) . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , SubVec , DAG . getIntPtrConstant ( Idx * SubVecNumElts , dl ) ) ; } if ( NumOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; ArrayRef < SDUse > Ops = Op -> ops ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( <NUM_LIT> , NumOperands / <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( NumOperands / <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } assert ( NumNonZero == <NUM_LIT> && <STR_LIT> ) ; if ( ResVT . getVectorNumElements ( ) >= <NUM_LIT> ) return Op ; SDValue Vec = DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getUNDEF ( ResVT ) , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( NumElems / <NUM_LIT> ,


<s> unsigned SrcRegNum = <ISA_LIT>_MC :: get<ISA_LIT>RegNum ( MI . getOperand ( OpNum ) . getReg ( ) ) ; if ( <STR_LIT> ( SrcReg


<s> bool isImmUnsignedi8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return true ; return isImmUnsignedi8Value ( CE ->


<s> EmitImmediate ( const MCOperand & DispOp , unsigned Size , MCFixupKind FixupKind , unsigned & CurByte , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , int ImmOffset ) const { if ( DispOp . isImm ( ) ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } const MCExpr * Expr = DispOp . getExpr ( ) ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( ImmOffset , Ctx ) ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isMovDGAll ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm


<s> } static const CostTblEntry < <STR_LIT> > SSE2CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , } ; if ( ST -> hasSSE2 ( ) ) { int Idx = CostTableLookup ( SSE2CostTable , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE2CostTable [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > AVX1CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX ( ) && ! ST -> hasAVX2 ( ) ) { EVT VT = LT . second ; if ( ISD == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) && Op2Info == TargetTransformInfo :: OK_NonUniformConstantValue ) ISD = <STR_LIT> ; int Idx = CostTableLookup ( AVX1CostTable , ISD , VT ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTable [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > CustomLowered


<s> void <ISA_LIT>TargetELFStreamer :: EmitDirectiveHSACodeObjectVersion ( uint32_t Major , uint32_t Minor ) { EmitNote ( ElfNote :: NoteNameV2 , MCConstantExpr :: create ( <NUM_LIT> , getContext ( )

) , ELF :: NT_AMD_HSA_CODE_OBJECT_VER<ISA_LIT>ON , [ & ] ( MCELFStreamer & OS ) {


<s> SDValue <ISA_LIT>TargetLowering :: opJoin ( const VectorPair & Ops , const

SDLoc & dl , SelectionDAG & DAG ) const {


<s> unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const Register Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ; } RVFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ; } if ( ! OutChains . empty ( ) ) { OutChains . push_back ( Chain ) ; Chain = DAG . getNode ( <STR_LIT> , DL ,


<s> return ( uint64x1_t ) __builtin_neon_vreinterpretdiv4hi


<s> const MCOperand & Cm = MI -> getOperand ( <NUM_LIT> ) ; const MCOperand & Op2 = MI -> getOperand ( <NUM_LIT> ) ; unsigned Op1Val = Op1 . getImm ( ) ; unsigned CnVal = Cn . getImm ( ) ; unsigned CmVal = Cm . getImm ( ) ; unsigned Op2Val = Op2 . getImm ( ) ; uint16_t Encoding = Op2Val ; Encoding |= CmVal << <NUM_LIT> ; Encoding |= CnVal << <NUM_LIT> ; Encoding |= Op1Val << <NUM_LIT> ; bool NeedsReg ; std :: string Ins ; std :: string Name ; if ( CnVal == <NUM_LIT> ) { switch ( CmVal ) { default : return false ; case <NUM_LIT> : case <NUM_LIT> : { const <STR_LIT> * IC = <STR_LIT> ( Encoding ) ; if ( ! IC || ! IC -> haveFeatures ( STI . getFeatureBits ( ) ) ) return false ; NeedsReg = IC -> NeedsReg ; Ins = <STR_LIT> ; Name = std :: string ( IC -> Name ) ; } break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : { const <STR_LIT> * DC = <STR_LIT> ( Encoding ) ; if ( ! DC || ! DC -> haveFeatures ( STI . getFeatureBits ( ) ) ) return false ; NeedsReg = true


<s> if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } BitVector


<s> Op = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } } if ( Op . getOpcode ( ) == <STR_LIT> && onlyZeroFlagUsed ( SDValue ( N , <NUM_LIT> ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . getScalarSizeInBits ( ) >= <NUM_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SrcVT ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( <NUM_LIT> , dl , SrcVT ) ) ; } if ( Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Trunc = Op ; Op = Op . getOperand ( <NUM_LIT> ) ; EVT OpVT = Op . getValueType ( ) ; APInt UpperBits = APInt :: getBitsSetFrom ( OpVT . getSizeInBits ( ) , VT . getSizeInBits ( ) ) ; if ( OpVT == <STR_LIT> && DAG . MaskedValueIsZero ( Op , UpperBits ) && onlyZeroFlagUsed ( SDValue ( N , <NUM_LIT> ) ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , OpVT ) ) ; } if ( ! Trunc . hasOneUse ( ) || ! Op . hasOneUse ( ) ) return SDValue ( ) ; unsigned NewOpc ; switch ( Op . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( needCarryOrOverflowFlag ( SDValue ( N , <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; case <STR_LIT> : if ( needCarryOrOverflowFlag ( SDValue ( N , <NUM_LIT> ) ) ) return SDValue ( ) ; NewOpc = <STR_LIT> ; break ; } SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , VT , Op .


<s> SrcSubIdx = DstSubIdx = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { DestReg = MI . getOperand ( <NUM_LIT> )


<s> assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int


<s> MD_FALLBACK_FRAME_STATE_FOR ( context , fs , success ) ; if ( context -> br_loc [ <NUM_LIT> ] && * context -> br_loc [ <NUM_LIT> ] != context -> rp ) { fs -> curr . reg [ UNW_REG_RP ] . where = UNW_WHERE_BR ; fs -> curr . reg [ UNW_REG_RP ] . when = - <NUM_LIT> ; fs -> curr . reg [ UNW_REG_RP ] . val = <NUM_LIT> ; goto success ; } return _URC_END_OF_STACK ; success : return _URC_NO_REASON ; return _URC_END_OF_STACK ; } context -> region_start = ent -> start_offset + segment_base ; fs -> when_target = ( context -> rp - context -> region_start ) / <NUM_LIT> * <NUM_LIT> ; unw = ( unsigned long * ) ( ent -> info_offset + segment_base ) ; header = * unw ; length = UNW_LENGTH ( header ) ; if ( UNW_FLAG_EHANDLER ( header ) | UNW_FLAG_UHANDLER ( header ) ) { fs -> personality = * ( _Unwind_Personality_Fn * ) ( unw [ length + <NUM_LIT> ] + context -> gp ) ; context -> lsda = unw


<s> long tv [ <NUM_LIT> ] ; REAL_VALUE_TYPE rv ; gcc_assert ( mode == SFmode || mode == DFmode ) ; if ( mode == SFmode ) tv [ <NUM_LIT> ] = ( v << <NUM_LIT> ) >> <NUM_LIT> ; else if ( mode ==


<s> FunctionPass * llvm :: createMOVToLEAPass ( ) { return new MOVToLEAPass (


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerRET ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG


<s> int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? <NUM_LIT> : <NUM_LIT> ; booth_unit_size = <NUM_LIT> ; for ( j = <NUM_LIT> ; i && j < <NUM_LIT> ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; * total += rtx_cost ( XEXP ( x , <NUM_LIT> ) , mode , code , <NUM_LIT> , speed ) ; return true ; } * total = COSTS_N_INSNS


<s> const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , BaseAlign ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , HiAlign ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoStore ,


<s> return hasHWROT32 ( ) || hasSWROT32 (


<s> static DecodeStatus DecodeMemoryValue ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Register + <NUM_LIT> ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler ::


<s> Op = ParseRegister ( ) ; if ( ! Op ) Op = ParseFsl ( ) ; if ( ! Op ) Op = ParseImmediate ( ) ; if ( ! Op ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Operands . push_back ( Op ) ; return Op


<s> LLVMContext & C = CI -> getModule ( ) -> getContext ( ) ; if ( CI -> doesNotReturn ( ) ) { if ( auto * F = dyn_cast < Function > ( CI -> getCalledValue ( ) ) ) F -> removeFnAttr ( Attribute :: NoReturn ) ; CI -> removeAttribute ( AttributeList :: FunctionIndex , Attribute :: NoReturn ) ; } IRBuilder < > IRB ( C ) ; IRB . SetInsertPoint ( CI ) ; IRB . CreateStore ( IRB . getInt32 ( <NUM_LIT> ) , ThrewGV ) ; SmallVector < Value * , <NUM_LIT> > Args ; Args . push_back ( CI -> getCalledValue ( ) ) ; Args . append ( CI -> arg_begin ( ) , CI -> arg_end ( ) ) ; CallInst * NewCall = IRB . CreateCall ( getInvokeWrapper ( CI ) , Args ) ; NewCall -> takeName ( CI ) ; NewCall -> setCallingConv ( CI -> getCallingConv ( ) ) ; NewCall -> setDebugLoc ( CI -> getDebugLoc ( ) ) ; SmallVector < AttributeSet ,


<s> unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned RegNum = RegLst


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> )


<s> EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) !=

<NUM_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , Ty , IsPairwise ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { llvm :: RegisterTarget < llvm :: Triple :: stackpu2 > X ( llvm :: getThe<ISA_LIT>Target ( ) ,


<s> return ( __m128i ) __builtin_ia32_pmullw128 ( ( __v8hi ) __A ,


<s> EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && <ISA_LIT>SubTarget . hasFRES ( ) ) || ( VT == <STR_LIT> && <ISA_LIT>SubTarget . hasFRE ( ) ) || ( VT == <STR_LIT> && <ISA_LIT>SubTarget . hasAltivec ( ) ) ) { int Iterations = <ISA_LIT>SubTarget . hasRecipPrec ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( VT . getScalarType ( ) == <STR_LIT> ) ++ Iterations ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( Op ) ; SDValue FPOne = DAG . getConstantFP ( <NUM_LIT> , VT . getScalarType ( ) ) ; if ( VT . isVector ( ) ) { assert ( VT . getVectorNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; FPOne = DAG . getNode ( <STR_LIT> , dl , VT


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } unsigned Opc = ( CallConv == CallingConv :: <ISA_LIT>_INTR ? <STR_LIT> : <STR_LIT> ) ; if ( Flag . getNode ( ) ) return DAG . getNode ( Opc , dl , <STR_LIT> , Chain , Flag ) ; return DAG . getNode ( Opc , dl , <STR_LIT> ,


<s> else if ( RegClass == AMDGPU :: VSrc_64RegClassID ) RegClass = AMDGPU :: VReg_64RegClassID ; else return ; if ( fitsRegClass ( DAG , Operand , RegClass ) ) return ; if ( ! ScalarSlotUsed ) { ScalarSlotUsed = true ; return ; } SDNode * Node ; if ( isa < FrameIndexSDNode > ( Operand ) || isa < GlobalAddressSDNode > ( Operand ) ) { unsigned Opcode = Operand . getValueType ( ) == <STR_LIT> ? AMDGPU :: S_MOV_B32 :


<s> case FK_Data_4 : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32NB : COFF :: IMAGE_REL_I386_DIR32NB ; return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32 : COFF :: IMAGE_REL_I386_DIR32 ; case FK_Data_8 : if ( Is64Bit ) return COFF :: IMAGE_REL_AMD64_ADDR64 ; llvm_unreachable ( <STR_LIT>


<s> bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; isTailCall = false ; bool needsRegArgSlots = isVarArg ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering & TFI = * MF . getTarget ( ) . getFrameLowering ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( isVarArg && NumBytes < <NUM_LIT> ) NumBytes = <NUM_LIT> ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , dl ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; MVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , RegVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; needsRegArgSlots = false ; unsigned ArgSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned StackLoc = VA . getLocMemOffset ( ) + <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , StackLoc , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff

, MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ;


<s> static tree arm_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == <NUM_LIT> )


<s> const auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; bool IsVarArg = false ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) IsVarArg = true ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder


<s> void <ISA_LIT>BaseInstrInfo :: copyToCPSR ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool KillSrc , const <ISA_LIT>Subtarget & Subtarget ) const { unsigned Opc = Subtarget . isThumb ( ) ? ( Subtarget . isMClass ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , I , I -> getDebugLoc ( )


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue (


<s> N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N1 , N2 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; EVT VVT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VVT . getVectorElementType ( ) . getSizeInBits ( ) >> <NUM_LIT> ; int Val = <NUM_LIT> ; unsigned i , e ; for ( i = <NUM_LIT> , e = VVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Val = SVOp -> getMaskElt


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol (


<s> virtual const char * getPassName ( ) const { return


<s> for ( unsigned i = <NUM_LIT> ; i < ArgLocs . size ( ) ; ++ i ) { const CCValAssign & VA = ArgLocs [ i ] ; CCValAssign :: LocInfo LocInfo = determineLocInfo ( Arguments [ i ] . VT , Arguments [ i ] . ArgVT , Arguments [ i ] . Flags ) ; if ( VA . isMemLoc ( ) ) ArgLocs [ i ] = CCValAssign :: getMem ( VA . getValNo ( ) , VA . getValVT ( ) , VA . getLocMemOffset ( ) , VA . getLocVT ( ) , LocInfo ) ; else ArgLocs [ i ] = CCValAssign :: getReg ( VA . getValNo ( ) , VA . getValVT ( ) , VA . getLocReg ( ) , VA .


<s> inline tree tuple_type_field ( tree type ) { for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE

( field ) == FIELD_DECL ) return field ;


<s> tree io_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( io_low_attr && TREE_VALUE ( io_low_attr ) && TREE_VALUE ( TREE_VALUE ( io_low_attr ) ) ) addr_attr = io_attr ; else if ( io_attr && TREE_VALUE ( io_attr ) && TREE_VALUE ( TREE_VALUE ( io_attr ) ) ) addr_attr = io_attr ; else addr_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( io_low_attr || ( io_attr && addr_attr && low_io_address_operand ( GEN_INT ( TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( addr_attr ) ) ) ) , QImode ) ) ) SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_IO_LOW ; if ( io_attr || io_low_attr ) SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_IO ; if ( addr_attr && ! DECL_EXTERNAL ( decl ) ) SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_ADDRESS ; } if ( AVR_TINY && decl && VAR_DECL == TREE_CODE ( decl ) && MEM_P ( rtl ) && SYMBOL_REF_P ( XEXP ( rtl , <NUM_LIT> ) ) ) { rtx sym = XEXP ( rtl , <NUM_LIT> ) ; bool progmem_p = avr_progmem_p ( decl , DECL_ATTRIBUTES ( decl ) ) == - <NUM_LIT> ; if ( progmem_p ) { SYMBOL_REF_FLAGS ( sym ) |= AVR_SYMBOL_FLAG_TINY_PM ; } if ( avr_decl_absdata_p ( decl , DECL_ATTRIBUTES ( decl ) ) || ( TARGET_ABSDATA && ! progmem_p && ! addr_attr && avr_decl_maybe_lds_p ( decl ) ) || ( addr_attr && TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( addr_attr ) ) ) < <NUM_LIT> ) ) { SYMBOL_REF_FLAGS ( sym ) |= AVR_SYMBOL_FLAG_TINY_ABSDATA ; } if ( progmem_p && avr_decl_absdata_p ( decl ,


<s> gcc_assert ( MEM_P ( mem_rtx ) ) ; rtx addr_rtx = XEXP ( mem_rtx , <NUM_LIT> ) ; if ( REG_P ( addr_rtx ) ) return true ; if ( GET_CODE ( addr_rtx ) == PLUS && GET_CODE ( XEXP ( addr_rtx , <NUM_LIT> )


<s> case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_ZNVER2 : case PROCESSOR_ZNVER3 : case PROCESSOR_ZNVER4 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_TREMONT : case PROCESSOR_SKYLAKE : case PROCESSOR_SKYLAKE_AVX512 : case PROCESSOR_CASCADELAKE : case PROCESSOR_CANNONLAKE : case PROCESSOR_ALDERLAKE : case PROCESSOR_GENERIC : return <NUM_LIT> ; case PROCESSOR_ICELAKE_CLIENT : case PROCESSOR_ICELAKE_SERVER : case PROCESSOR_TIGERLAKE : case PROCESSOR_COOPERLAKE : case


<s> if ( ! cfun -> machine -> axis_dim_init_p ) init_axis_dim (


<s> bool system_reg_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { switch ( REGNO ( op ) ) { case PR_REG : case MACL_REG : case MACH_REG : return


<s> } else { const char * replacement = nvptx_name_replacement ( name ) ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } write_fn_marker ( s , false , true , name ) ; s << <STR_LIT> ; } if ( result != NULL_RTX ) write_return_mode ( s , true , GET_MODE ( result ) ) ; s << name ; if ( replaced_dots ) XDELETE ( replaced_dots ) ; int arg_end = XVECLEN ( pat , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < arg_end ; i ++


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { static const MCPhysReg CalleeSavedRegs [ ]


<s> bool <ISA_LIT>LegalizerInfo :: selectIndirectIndexedAddressing ( LegalizerHelper & Helper , MachineRegisterInfo & MRI , MachineInstr & MI ) const { MachineIRBuilder & Builder = Helper . MIRBuilder ; bool IsLoad = MI . getOpcode ( ) == G_LOAD ; assert ( IsLoad || MI . getOpcode ( ) == G_STORE ) ; Register Addr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Index = <NUM_LIT> ; unsigned Opcode = IsLoad ? <STR_LIT> : <STR_LIT> ; if ( const MachineInstr * PtrAddAddr = getOpcodeDef ( G_PTR_ADD , Addr , MRI ) ) { Register Base = PtrAddAddr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewOffset = PtrAddAddr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( auto ConstOffset = getIConstantVRegValWithLookThrough ( NewOffset , MRI ) ) { if ( ConstOffset -> Value . getActiveBits ( ) <= <NUM_LIT> ) { Index = Builder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , ConstOffset -> Value . getSExtValue ( ) ) . getReg ( <NUM_LIT> ) ; Addr = Base ; } } else if ( MachineInstr * ZExtOffset = getOpcodeDef ( G_ZEXT , NewOffset , MRI ) ) { Register Src = ZExtOffset -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT SrcTy = MRI . getType ( Src ) ; if ( SrcTy . getSizeInBits ( ) <= <NUM_LIT> ) { if ( SrcTy . getSizeInBits ( ) < <NUM_LIT> ) Src = Builder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , Src ) . getReg ( <NUM_LIT> ) ; assert ( MRI . getType ( Src ) == LLT :: scalar ( <NUM_LIT> ) ) ; Index =


<s> assert ( std :: is_sorted ( MI -> begin ( ) + OpNum , MI -> end ( ) , [ & ] ( const MCOperand & LHS , const MCOperand & RHS ) { return MRI . getEncodingValue ( LHS . getReg ( ) ) < MRI . getEncodingValue ( RHS . getReg ( ) ) ; } ) ) ; } O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum )


<s> unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) ==


<s> if ( ( unsigned ) CC != ABI . GetDefaultDataCapability ( ) ) { ErrorIfNotPending ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> ) ; return - <NUM_LIT> ; } } if ( CC == - <NUM_LIT> ) { if ( Name [ <NUM_LIT> ] == 'c' ) { if ( Name == <STR_LIT> ) { CC = <STR_LIT> ; } else { StringRef NumString = Name . substr ( <NUM_LIT> ) ; int IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal < <NUM_LIT> || IntVal > <NUM_LIT> ) return - <NUM_LIT> ; if ( IntVal == <NUM_LIT> ) CC = <NUM_LIT> ; else CC = <STR_LIT> + IntVal - <NUM_LIT> ; } } else { int InvalidReg = StringSwitch < int > ( Name ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; if ( InvalidReg ) { ErrorIfNotPending ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> <STR_LIT> + Name + <STR_LIT> + Twine ( InvalidReg ) + <STR_LIT> <STR_LIT> , Parser . getTok ( ) . getLocRange ( ) ) ; return - <NUM_LIT> ; } CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( - <NUM_LIT> ) ; } } if ( CC ==


<s> std :: vector < std :: string > moda3 ( Moda3 op , Bx a , Cond cond ) { return D ( op , R ( a )


<s> OperandMatchResultTy parseVF128 ( OperandVector &


<s> if ( RM == Reloc :: Default ) RM = Reloc :: Static ; if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; X -> InitMCCodeGenInfo ( RM , CM ) ; return X


<s> <ISA_LIT>GenPostLegalizerLoweringHelper Generated ( GeneratedRuleCfg ) ; return Generated . tryCombineAll ( Observer , MI , B ,


<s> rtx opfalse = op_false ? op_false : CONST0_RTX ( data_mode ) ; if ( * negate ) std :: swap ( optrue , opfalse ) ; if ( ( code != EQ && GET_MODE_SIZE ( mode ) != <NUM_LIT> && vector_all_ones_operand ( opfalse , data_mode ) && optrue == CONST0_RTX ( data_mode ) ) || ( code == GTU && GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) >= <NUM_LIT> && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || ! vector_all_ones_operand ( optrue , data_mode ) || opfalse != CONST0_RTX ( data_mode ) ) ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) = NULL ; switch ( mode ) { case E_V16SImode : gen = ( code == GTU ) ? gen_uminv16si3 : gen_sminv16si3 ; break ; case E_V8DImode : gen = ( code == GTU ) ? gen_uminv8di3 : gen_sminv8di3 ; cop0 = force_reg ( mode , cop0 ) ; cop1 = force_reg ( mode , cop1 ) ; break ; case E_V32QImode : if ( TARGET_AVX2 ) gen = ( code == GTU ) ? gen_uminv32qi3 : gen_sminv32qi3 ; break ; case E_V16HImode : if ( TARGET_AVX2 ) gen = ( code == GTU ) ? gen_uminv16hi3 : gen_sminv16hi3 ; break ; case E_V8SImode : if ( TARGET_AVX2 ) gen = ( code == GTU ) ? gen_uminv8si3 : gen_sminv8si3 ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) { gen = ( code == GTU ) ? gen_uminv4di3 : gen_sminv4di3 ; cop0 = force_reg ( mode , cop0 ) ; cop1 = force_reg ( mode , cop1 ) ; } break ; case E_V16QImode : if ( code == GTU && TARGET_SSE2 ) gen = gen_uminv16qi3 ; else if ( code == GT && TARGET_SSE4_1 ) gen = gen_sminv16qi3 ; break ; case E_V8HImode : if ( code == GTU && TARGET_SSE4_1 ) gen = gen_uminv8hi3 ; else if ( code == GT && TARGET_SSE2 ) gen = gen_sminv8hi3 ; break ; case E_V4SImode : if ( TARGET_SSE4_1 ) gen = ( code == GTU ) ? gen_uminv4si3 : gen_sminv4si3 ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) { gen = ( code == GTU ) ? gen_uminv2di3 : gen_sminv2di3 ; cop0 = force_reg ( mode , cop0 ) ; cop1 = force_reg ( mode , cop1 ) ; } break ; default : break ; } if ( gen ) { rtx tem = gen_reg_rtx ( mode ) ; if ( ! vector_operand ( cop0 , mode ) ) cop0 = force_reg ( mode , cop0 ) ; if ( ! vector_operand ( cop1 , mode ) ) cop1 = force_reg ( mode , cop1 ) ; * negate = ! * negate ; emit_insn ( gen ( tem , cop0 , cop1 )


<s> static MCDisassembler * create<ISA_LIT>_32Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler (


<s> ScratchRSrcReg = <STR_LIT> ; ScratchWaveOffsetReg = <STR_LIT> ; FrameOffsetReg = <STR_LIT> ; StackPtrOffsetReg = <STR_LIT> ; ArgInfo . PrivateSegmentBuffer = ArgDescriptor :: createRegister ( ScratchRSrcReg ) ; ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( ScratchWaveOffsetReg ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) ImplicitArgPtr = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) { KernargSegmentPtr = true ; MaxKernArgAlign = std :: max ( ST . getAlignmentForImplicitArgPtr ( ) , MaxKernArgAlign ) ; } } if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDZ = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDZ = true ; const MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( isEntryFunction ( ) ) { if ( WorkItemIDZ ) WorkItemIDY = true ; PrivateSegmentWaveByteOffset = true ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 && ( CC == CallingConv :: <ISA_LIT>_HS || CC == CallingConv :: <ISA_LIT>_GS ) ) ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( <STR_LIT> ) ; } bool isAmdHsaOrMesa = ST . isAmdHsaOrMesa ( F ) ; if ( isAmdHsaOrMesa ) { PrivateSegmentBuffer = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchID = true ; } else if ( ST .


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! MI . findRegisterDefOperand ( <STR_LIT> ) -> isDead ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT>


<s> enum resolver_ident arm_describe_resolver ( tree fndecl ) { if ( DECL_MD_FUNCTION_CODE ( fndecl ) >= ARM_BUILTIN_vcx1qv16qi && DECL_MD_FUNCTION_CODE ( fndecl ) < ARM_BUILTIN_MVE_BASE ) return arm_cde_resolver ; return


<s> } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { int16_t SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( SImm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> hasSPE (


<s> case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerExtendedLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op ,


<s> BitVector getReservedRegs ( const MachineFunction & MF ) const


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; bool is<ISA_LIT>64 = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = <ISA_LIT>SubTarget . isDarwinABI ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int RASI = FI -> getReturnAddrSaveIndex ( ) ; if ( ! RASI ) { int LROffset = <ISA_LIT>FrameLowering :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ,


<s> for ( auto & F : M ) replaceFeatures ( F , FeatureStr ) ; bool Stripped = false ; if ( ! Features [ <STR_LIT> ] ) { Stripped |= stripAtomics ( M ) ; Stripped |= stripThreadLocals ( M ) ; } recordFeatures ( M , Features , Stripped


<s> vec_perm_builder builder ( nelts , <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts


<s> tmpInst . addOperand ( MCOperand :: createImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( DstRegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( SrcRegOp . getReg ( ) ) ) ; Instructions . push_back ( tmpInst


<s> Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( !


<s> CreateTargetScheduleState ( const TargetMachine * TM , const ScheduleDAG


<s> static SDValue performSUBCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) { if ( Subtarget . has<ISA_LIT>32 ( ) && ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . in<ISA_LIT>16Mode ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return performMADD_MSUBCombine ( N , DAG , Subtarget ) ; return SDValue


<s> return ( uint32x4_t ) __builtin_aarch64_lfrintnuv4sfv4si


<s> int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; DOUT << <STR_LIT> ; MI . print ( DOUT ) ; DOUT << <STR_LIT> << FrameIndex << <STR_LIT> ; DOUT << <STR_LIT> << Offset << <STR_LIT> ; DOUT << <STR_LIT> << StackSize << <STR_LIT> ; Offset += StackSize ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; DOUT << <STR_LIT> << Offset << <STR_LIT> ; DOUT << <STR_LIT> ; Offset /= <NUM_LIT> ; bool FP = hasFP ( MF ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( <STR_LIT> -> contains ( Reg ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( FP ) { bool isUs = isImmUs ( Offset ) ; unsigned FramePtr = <STR_LIT> ; MachineInstr * New = <NUM_LIT> ; if ( ! isUs ) { if ( ! RS ) { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << Offset ; llvm_report_error ( Msg . str ( ) ) ; } unsigned ScratchReg = RS -> scavengeRegister ( <STR_LIT> , II , SPAdj ) ; loadConstant ( MBB , II , ScratchReg , Offset , dl ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : New = BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; case <STR_LIT> : New = BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; case <STR_LIT> : New = BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : New = BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; case


<s> assert ( ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) && <STR_LIT> ) ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; return getI8Imm ( ( Index * VecVT . getScalarSizeInBits


<s> unsigned HOST_WIDE_INT len ; HOST_WIDE_INT align ; rtx src , dst , base ; rtx reg0 ; bool src_aligned , dst_aligned ; bool src_volatile , dst_volatile ; gcc_assert ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( CONST_INT_P ( operands [ <NUM_LIT> ] ) ) ; len = UINTVAL ( operands [ <NUM_LIT> ] ) ; if ( len > <NUM_LIT> ) return false ; align = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( ! unaligned_access ) && ( len >= <NUM_LIT> ) && ( ( align & <NUM_LIT> ) != <NUM_LIT> ) ) return false ; dst = operands [ <NUM_LIT> ] ; dst_volatile = MEM_VOLATILE_P ( dst ) ; dst_aligned = MEM_ALIGN ( dst ) >= BITS_PER_WORD ; base = copy_to_mode_reg ( SImode , XEXP ( dst , <NUM_LIT> ) ) ; dst = adjust_automodify_address ( dst , VOIDmode , base , <NUM_LIT> ) ; src = operands [ <NUM_LIT> ] ; src_volatile = MEM_VOLATILE_P ( src ) ; src_aligned = MEM_ALIGN ( src ) >= BITS_PER_WORD ; base = copy_to_mode_reg ( SImode , XEXP ( src , <NUM_LIT> ) ) ; src = adjust_automodify_address ( src , VOIDmode , base , <NUM_LIT> ) ; if ( ! unaligned_access && ! ( src_aligned && dst_aligned ) ) return false ; if ( src_volatile || dst_volatile ) return false ; if ( ! ( dst_aligned || src_aligned ) ) return arm_gen_cpymemqi ( operands ) ; src = adjust_address ( src , src_aligned ? DImode : SImode , <NUM_LIT> ) ; dst = adjust_address ( dst , dst_aligned ? DImode : SImode , <NUM_LIT> ) ; while ( len >= <NUM_LIT> ) { len -= <NUM_LIT>


<s> machine_mode new_mode = VOIDmode ; if ( type ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > <NUM_LIT> && ag_count <= <NUM_LIT> ) * count = ag_count ; else return false ; } else if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) { * count = <NUM_LIT> ; new_mode = mode ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { * count = <NUM_LIT> ; new_mode = ( mode == DCmode ? DFmode : SFmode ) ; } else return


<s> <ISA_LIT>LibFunc nf = FInfo ; nf . setPrefix ( <ISA_LIT>LibFunc :: NATIVE ) ; if ( Constant * FPExpr = getFunction ( M , nf ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * CI << <STR_LIT> ) ; CI -> setCalledFunction ( FPExpr )


<s> void DataFlowGraph :: reset ( ) { Memory . clear ( )


<s> unsigned int nelts_per_vq ; if ( ! aarch64_sve_inc_dec_immediate_p ( x , & factor , & nelts_per_vq )


<s> return __builtin_mve_vcmpltq_m_fv8hf ( __a ,


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { return true


<s> PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumVectorRegs ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumVectorRegs ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += <NUM_LIT> ; return Cost


<s> return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder

) : DecodeVSTInstruction ( Inst , Insn , Address , Decoder ) ;


<s> static void mips_dfa_post_advance_cycle ( void ) { if ( TUNE_LOONGSON_2EF ) mips_ls2_dfa_post_advance_cycle ( curr_state


<s> split_const ( op , & sym , & addend ) ; if ( SYMBOL_REF_P ( sym ) ) return SYMBOL_REF_TLS_MODEL ( sym ) ; return TLS_MODEL_NONE


<s> if ( TARGET_ARM ) lowbit &= ~ <NUM_LIT> ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) << lowbit ) ) == <NUM_LIT> ) return TRUE ; if ( TARGET_ARM ) { if ( lowbit <= <NUM_LIT> && ( ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> || ( i & ~ <NUM_LIT> ) == <NUM_LIT> ) ) return TRUE ; } else if ( TARGET_THUMB2 ) { HOST_WIDE_INT v ; v = i & <NUM_LIT> ; v |= v << <NUM_LIT> ; if ( i == v || i == ( v | ( v << <NUM_LIT> ) ) ) return TRUE ; v = i & <NUM_LIT> ; v |= v << <NUM_LIT> ; if ( i == v


<s> DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( *


<s> if ( GET_CODE ( dst ) == REG ) { int rdst = REGNO ( dst ) ; rtx dst_msw = gen_rtx_REG ( SImode , rdst + <NUM_LIT> ) ; if ( GET_CODE ( src ) ==


<s> <STR_LIT> Cond = <STR_LIT> ( CMovI ) ; unsigned CondReg ; bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) ,


<s> ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; break ; case <STR_LIT> : Opc = ( IsZExt ? ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) : ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( ( Addr . Offset & <NUM_LIT> ) != <NUM_LIT> ) ) UseOffset = false ; break ; case <STR_LIT> : Opc = <STR_LIT> ; assert ( UseRC -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = FP64LoadOpc ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg (

Addr . Base . Reg ) . addReg ( IndexReg ) ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> std :: string getNextCallSiteMagicPrivate ( ) { sgx_callsite_magic_index_private ++


<s> return Token . endswith ( <STR_LIT> ) ||


<s> O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> (


<s> bool isAliased ( const MachineFrameInfo * )


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , bool


<s> if ( ! isGPRMem ( ) || ! Memory . OffsetRegNum || Memory . Alignment != <NUM_LIT> ) return false ; return true


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent (


<s> if ( RepPrefix ) EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; InstrumentMOV ( Inst , Operands , Ctx , MII , Out ) ; RepPrefix = ( Inst . getOpcode (


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( ( CE -> getValue ( ) - <NUM_LIT> )


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; return getAddr ( N


<s> static ArrayRef < MCPhysReg > getAllSGPRs ( const MachineFunction & MF , const <ISA_LIT>RegisterInfo * TRI ) { return makeArrayRef ( <STR_LIT> . begin ( ) , TRI


<s> unsigned LiteralPair0 = Literals [ i ] ; unsigned LiteralPair1 = ( i + <NUM_LIT> < e ) ? Literals [ i + <NUM_LIT> ] : <NUM_LIT> ; InsertPos = BuildMI ( MBB , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm (

LiteralPair0 ) . addImm ( LiteralPair1 ) ;


<s> arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ; arc_punct_chars [ '+' ] = <NUM_LIT> ; arc_punct_chars [ '_' ] = <NUM_LIT> ; if ( optimize > <NUM_LIT> && ! TARGET_NO_COND_EXEC ) { opt_pass * pass_arc_ifcvt_4 = make_pass_arc_ifcvt ( g ) ; struct register_pass_info arc_ifcvt4_info = { pass_arc_ifcvt_4 , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ; struct register_pass_info arc_ifcvt5_info = { pass_arc_ifcvt_4 -> clone ( ) , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_BEFORE } ; register_pass ( & arc_ifcvt4_info ) ; register_pass ( & arc_ifcvt5_info


<s> OS << <STR_LIT> << Sew ; switch ( VLMUL ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned LMul = <NUM_LIT> << static_cast < unsigned > ( VLMUL ) ; OS << <STR_LIT> << LMul ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType )


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ; if ( ! CE ) { addExpr ( Inst , Imm . Val ) ; return ; } int64_t Val = CE -> getValue ( ) ; assert ( Val % scale == <NUM_LIT> && <STR_LIT> ) ; Val /=


<s> switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> if ( checkInFPOPrologue ( L ) ) return true ; FPOInstruction Inst ; Inst . Label = emitFPOLabel ( ) ; Inst . Op =


<s> static bool MayFoldVectorLoad ( SDValue V ) { if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> && V . getNumOperands ( ) == <NUM_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( V ) ) return true ; return false


<s> <ISA_LIT>TTI :: PopcntSupportKind <ISA_LIT>TTI :: getPopcntSupport


<s> void <ISA_LIT>Operand :: print ( raw_ostream & OS ) const { switch ( Kind ) { break ; case KindToken : OS << <STR_LIT> << getToken ( ) ; break ; case KindReg : OS << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( getReg ( ) ) ; break ; case KindImm : OS << <STR_LIT> ; printMCExpr ( getImm ( ) , OS ) ; break ; case KindImmTLS : OS << <STR_LIT> ; printMCExpr ( getImmTLS ( ) . Imm , OS ) ; if ( getImmTLS ( ) . Sym ) { OS << <STR_LIT> ; printMCExpr ( getImmTLS ( ) . Sym , OS ) ; } break ; case KindMem : { const MemOp & Op = getMem ( ) ; OS << <STR_LIT> << * cast < MCConstantExpr > ( Op . Disp ) ; if ( Op . Base ) { OS << <STR_LIT> ; if ( Op . MemKind == BDLMem ) OS << * cast < MCConstantExpr > ( Op .


<s> if ( insn_entry [ i ] . is_load ) { if ( GET_CODE ( body ) == SET ) { rtx rhs = SET_SRC ( body ) ; if ( GET_CODE ( rhs ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_LD ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC ) { rtx lhs = SET_DEST ( body ) ; if ( GET_CODE ( lhs ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( lhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_ST ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VSX_CVDPSPN ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET


<s> bool FoldAsMAD = tryAddToFoldList ( FoldList , MI , OpNo , OpToFold , TII ) ; if ( FoldAsMAD ) { MI -> untieRegOperand ( OpNo ) ; return true ; } MI -> setDesc ( TII -> get ( Opc ) ) ; } if ( OpToFold -> isImm ( ) ) { unsigned ImmOpc = <NUM_LIT> ; if ( Opc == <STR_LIT> ) ImmOpc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) ImmOpc = <STR_LIT> ; if ( ImmOpc ) { MI -> setDesc ( TII -> get ( ImmOpc ) ) ; appendFoldCandidate ( FoldList , MI , OpNo , OpToFold ) ; return true ; } } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteOpNo = OpNo ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( * MI , CommuteOpNo , OpToFold ) ) { if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( OpToFold -> isImm ( ) || OpToFold -> isFI ( ) || OpToFold -> isGlobal ( ) ) ) { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0 ; MachineOperand & OtherOp = MI -> getOperand ( OtherIdx ) ; if ( ! OtherOp . isReg ( ) || ! TII -> getRegisterInfo ( ) . isVGPR ( MRI , OtherOp . getReg ( ) ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isDef ( ) ) ; unsigned MaybeCommutedOpc = MI -> getOpcode ( ) ; int Op32 = <STR_LIT> (


<s> bool isVecListOneDAllLanes ( ) const { if ( ! isSingleSpacedVectorAllLanes ( ) ) return false ; return VectorList . Count ==


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! <ISA_LIT>FI || <ISA_LIT>FI -> getUsesRedZone ( ) ) return false ; } if ( ! OutlineFromLinkOnceODRs && F .

hasLinkOnceODRLinkage ( ) ) return false ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; unsigned Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . value_op_begin ( ) , I . value_op_end ( ) ) ; Cost += getUserCost ( & I , Operands ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UnrollRemainder =


<s> bool isCheapToSpeculateCtlz ( ) const


<s> MachineInstrBuilder MIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; ++ NumCopiesInserted


<s> void <ISA_LIT>RegisterBankInfo :: constrainOpWithReadfirstlane ( MachineInstr & MI , MachineRegisterInfo & MRI , unsigned OpIdx ) const { Register Reg = MI . getOperand ( OpIdx ) . getReg ( ) ; const RegisterBank * Bank = getRegBank ( Reg , MRI , * TRI ) ; if ( Bank != & <STR_LIT> ) return ; MachineIRBuilder B ( MI ) ; Register SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( SGPR ) . addReg ( Reg ) ; const TargetRegisterClass * Constrained = constrainGenericRegister ( Reg , <STR_LIT> ,


<s> SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) ) , VT


<s> case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( isa < ConstantFP > ( CallOperandVal )


<s> void <ISA_LIT>GenInsert :: dump_map ( ) const { using iterator = IFMapType :: const_iterator ; for ( iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { dbgs ( ) << <STR_LIT> << printReg ( I -> first , HRI ) << <STR_LIT> ; const IFListType & LL = I


<s> return ( ( vec_pixel8 ) ( spu_shuffle ( spu_sel ( spu_sel ( spu_sl ( a , <NUM_LIT> ) , spu_sl ( a , <NUM_LIT> ) , x03FF ) , spu_sl ( a , <NUM_LIT> ) , x001F ) , spu_sel ( spu_sel ( spu_sl ( b , <NUM_LIT> ) , spu_sl ( b , <NUM_LIT> ) , x03FF ) , spu_sl ( b , <NUM_LIT> ) , x001F ) , (


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsr_u64 ( unsigned long long __X ) { return ( __X & (


<s> void <ISA_LIT>32CompilationCallback ( ) { assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( )


<s> return VectorType :: get ( ArrayTy -> getArrayElementType (

) , ArrayTy -> getArrayNumElements ( ) ) ;


<s> if ( generateSignBits ( V ) ) return false ; auto * I = cast < Instruction > ( V ) ; if ( I -> hasOneUse ( ) && isSink ( * I -> use_begin ( ) ) ) return true ; if ( isa < OverflowingBinaryOperator > ( I )


<s> static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Type * Ty = arg -> getType ( ) ; auto * PTy = dyn_cast < PointerType > ( Ty ) ; if ( ! PTy


<s> for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ; bool UseVarArgCC = false ; if ( IsVarArg ) { if ( IsCalleeWin64 ) { UseVarArgCC = true ; } else { UseVarArgCC = ! Outs [ i ] . IsFixed ; } } else { EVT ActualVT = TLI . getValueType ( DAG . getDataLayout ( ) , CLI . Args [ Outs [ i ] . OrigArgIndex ] . Ty , true ) ; MVT ActualMVT = ActualVT . isSimple ( ) ? ActualVT . getSimpleVT ( ) : ArgVT ; if ( ActualMVT == <STR_LIT> || ActualMVT == <STR_LIT> ) ArgVT = <STR_LIT> ; else if ( ActualMVT == <STR_LIT> ) ArgVT = <STR_LIT> ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( CalleeCC , UseVarArgCC ) ; bool Res = AssignFn ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ; assert ( ! Res && <STR_LIT> ) ; ( void )


<s> } case <ISA_LIT>InstrInfo :: SCC_FALSE : { Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCNZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: EXECNZ : { Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; Register SReg2 = MRI . createVirtualRegister ( RI . getBoolRC


<s> return ! isReservedReg ( MF , PhysReg


<s> void addAlignedMemory64or128Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst , N )


<s> unsigned getNumFixupKinds ( ) const { return <NUM_LIT>


<s> <STR_LIT> <STR_LIT> ( ) const { return


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ; for ( unsigned I = <NUM_LIT> , E = Res -> getNumValues ( ) ; I != E ; ++

I ) Results . push_back ( Res . getValue ( I ) ) ;


<s> std :: vector < std :: string > mov_pc (


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; unsigned i ; for ( i = <NUM_LIT> ; i != <NUM_LIT> && SVOp -> getMaskElt ( i ) < <NUM_LIT> ; ++ i ) ; if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; bool isLE = DAG . getDataLayout ( ) . isLittleEndian ( ) ; if ( ( ShuffleKind == <NUM_LIT> && ! isLE ) || ( ShuffleKind == <NUM_LIT> && isLE ) ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else if ( ShuffleKind == <NUM_LIT> ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ( ShiftAmt + i ) & <NUM_LIT> ) ) return - <NUM_LIT> ; } else return - <NUM_LIT> ; if ( isLE ) ShiftAmt = <NUM_LIT> - ShiftAmt ; return ShiftAmt


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: addFullAddress ( const MachineInstrBuilder & MIB , <ISA_LIT>AddressMode & AM ) { AM . IndexReg = constrainOperandRegClass ( MIB -> getDesc ( ) , AM . IndexReg , MIB -> getNumOperands ( )


<s> if ( Chain == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; InputChain = LoadNode -> getChain ( ) ; } else if ( Chain . getOpcode ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > ChainOps ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) { SDValue Op = Chain . getOperand ( i ) ; if ( Op == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; ChainOps . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; continue ; } int LoadId = LoadNode -> getNodeId ( ) ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = UI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getNodeId ( ) > LoadId ) return false ; } ChainOps . push_back ( Op ) ; } if ( ChainCheck ) InputChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Chain ) , <STR_LIT> , ChainOps ) ; } if ( ! ChainCheck ) return false ; return


<s> else op [ o ] = args [ ( int ) hex_value ( ao ) ] ; if ( ! ( * insn_data [ code ] . operand [ o ] . predicate ) ( op [ o ] , GET_MODE ( op [ o ] ) ) ) { if ( c == '+' || c == '=' ) { copyto [ o ] = op [ o ] ; op [ o ] = gen_reg_rtx ( omode ) ; } else op [ o ] = copy_to_mode_reg ( omode , op [ o ] ) ; } if ( ao == 'r' ) retval = op [ o ] ; } pat = GEN_FCN ( code ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; emit_insn ( pat ) ; for ( o = <NUM_LIT> ; s16builtins [ i ] . arg_ops [ o ] ; o ++ ) if ( copyto [ o ] ) { emit_move_insn ( copyto [ o ] , op [ o ] ) ; if ( op [ o ] == retval ) retval = copyto [ o ] ; } return retval


<s> int64_t Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt )


<s> int64_t Val = Memory . OffsetImm ? ( Memory . OffsetImm -> getValue ( ) / <NUM_LIT> ) : <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateImm (


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , <NUM_LIT> , CostKind , I ) ; MemOpCost *= getSVEGatherScatterOverhead ( Opcode ) ; return LT . first * MemOpCost * getMaxNumElements


<s> for ( const auto & S : SchedSU -> Succs ) { if ( S . getSUnit ( ) -> isBoundaryNode ( ) || isScheduled ( S . getSUnit ( ) ) || S . getKind ( ) != SDep :: Data ) continue ; for ( const auto & P : S . getSUnit ( ) -> Preds ) { auto PSU = P . getSUnit ( ) ; assert ( ! PSU -> isBoundaryNode ( ) ) ; if ( PSU != SchedSU && ! isScheduled ( PSU ) ) { Set . insert ( PSU ) ; } } } SmallVector < const SUnit * , <NUM_LIT> > Worklist ( Set . begin ( ) , Set . end ( ) ) ; while ( ! Worklist . empty (


<s> void <ISA_LIT>InstPrinter :: printSVEPattern ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( auto Pat = <STR_LIT> ( Val ) ) O << Pat -> Name ; else O << '#' << formatImm (


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst


<s> updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! SrcVT . isSimple ( ) || ! DstVT . isSimple ( ) ) return false ; if ( ! SrcVT . is128BitVector ( ) && ! ( Subtarget -> hasAVX ( ) && SrcVT . is256BitVector ( ) ) ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return true


<s> void printS22ImmOperand ( const MachineInstr * MI , unsigned OpNo ) { int val = ( unsigned int ) MI -> getOperand ( OpNo ) . getImm ( ) ; if ( val >= <NUM_LIT> )


<s> void fma_node :: set_head ( du_head * head ) { gcc_assert ( ! this


<s> Value * Op1 = II . getArgOperand ( <NUM_LIT> ) ; Value * Op2 = II . getArgOperand ( <NUM_LIT> ) ; Type * RetTy = II . getType ( ) ; Type * OpTy = Op1 -> getType ( ) ; assert ( RetTy -> getStructElementType ( <NUM_LIT> ) -> isIntegerTy ( <NUM_LIT> ) && RetTy -> getStructElementType ( <NUM_LIT> ) == OpTy && OpTy == Op2 -> getType ( ) && <STR_LIT> ) ; if ( match ( CarryIn , PatternMatch :: m_ZeroInt ( ) ) ) { Value * UAdd = Builder . CreateIntrinsic ( <STR_LIT> , OpTy , { Op1 , Op2 } ) ; Value * UAddResult = Builder . CreateExtractValue ( UAdd , <NUM_LIT> ) ; Value * UAddOV = Builder . CreateZExt ( Builder . CreateExtractValue ( UAdd , <NUM_LIT> ) , Builder . getInt8Ty ( ) ) ; Value * Res = UndefValue :: get ( RetTy ) ; Res = Builder . CreateInsertValue ( Res , UAddOV


<s> } else ReverseOrder = CI . Offset0 > CI . Offset1 ; static const unsigned Idxs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; unsigned Idx0 ; unsigned Idx1 ; assert ( CI . Width0 >= <NUM_LIT> && CI . Width0 <= <NUM_LIT> ) ; assert ( CI . Width1 >= <NUM_LIT> && CI . Width1 <= <NUM_LIT> ) ; if ( ReverseOrder ) { Idx1 = Idxs [ <NUM_LIT> ] [ CI . Width1 - <NUM_LIT> ] ; Idx0 = Idxs [ CI . Width1 ] [ CI . Width0 - <NUM_LIT> ] ; } else { Idx0 = Idxs [ <NUM_LIT> ] [ CI . Width0 - <NUM_LIT> ] ; Idx1 = Idxs [ CI . Width0 ] [ CI .


<s> ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( AndOp1 . getNode ( ) ) ; if ( ! Mask ) return ; uint64_t MaskVal = Mask -> getZExtValue ( ) ; unsigned BitSize = CmpOp0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( ICmpType != <STR_LIT> && AndOp0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( AndOp0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { AndOp0 = AndOp0 . getOperand ( <NUM_LIT> ) ; AndOp1 = DAG . getConstant ( MaskVal >> ShiftVal ,


<s> } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregcidi_pss ( __o


<s> if ( Pred1 . size ( ) > <NUM_LIT> || Pred2 . size ( ) > <NUM_LIT> ) { return false ; } <STR_LIT> CC1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( CC1 == CC2 ) { return true ; } switch ( CC1 ) { case <STR_LIT> : return true ; case <STR_LIT>


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI ,


<s> return decodeBDRAddr12Operand ( Inst , Field ,


<s> Type * Ty = STy -> getTypeAtIndex ( i ) ; Elems . push_back ( cast < Constant > ( PrepareValueForMemSet ( IRB , Val , Ty ) ) ) ; } return ConstantStruct :: get ( STy , Elems ) ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( ToType ) ) { Type * Ty = ATy -> getElementType


<s> PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; AllowNameToStartWithDigit =


<s> int Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , I ) ; return vectorCostAdjustment ( Cost , Opcode


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Or = BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * Or ) ; MI . eraseFromParent


<s> void <ISA_LIT>InstPrinter :: printV3U64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << '(' ; printU64 ( MI , OpNo + <NUM_LIT> ,


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getImm ( ) ; addExpr ( Inst ,


<s> SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem ; const char * RestoreFn = getSpillFunctionFor ( MaxR , Kind ) ; auto & HTM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; bool IsPIC = HTM . getRelocationModel ( ) == Reloc :: PIC_ ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : MBB . getLastNonDebugInstr ( ) -> getDebugLoc ( ) ; MachineInstr * DeallocCall = nullptr ; if ( HasTC ) { unsigned ROpc = IsPIC ? <STR_LIT> : <STR_LIT> ; DeallocCall = BuildMI ( MBB , MI , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; } else { MachineBasicBlock :: iterator It = MBB . getFirstTerminator ( ) ; assert ( It -> isReturn ( ) && std :: next ( It ) == MBB . end ( ) ) ; unsigned ROpc = IsPIC ? <STR_LIT> : <STR_LIT> ; DeallocCall = BuildMI ( MBB , It , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; DeallocCall -> copyImplicitOps ( MF


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; auto V = ( MO . getImm ( ) <= <NUM_LIT> ) ? <NUM_LIT> : MO . getImm ( ) ; return V


<s> } if ( eop0 . ext_code != UNKNOWN && eop1 . ext_code == UNKNOWN ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = simplify_gen_subreg ( subreg_mode , operands [ <NUM_LIT> ] , GET_MODE ( operands [ <NUM_LIT> ] ) , subreg_offset ) ; emit_insn ( subreg_mode == QImode ? gen_zero_extendqisi2 ( tmp0 , tmp1 ) : gen_zero_extendhisi2 ( tmp0 , tmp1 ) ) ; emit_insn ( gen_tstsi_t ( tmp0 , operands


<s> } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override ; void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override ; bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT>


<s> add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , <NUM_LIT> ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> if ( group == disp_jcc || group == disp_cmp ) return false ; if ( group == disp_no_group || group == disp_branch ) return true ; if ( window_list_next ) window_list = window_list_next ; if ( window_list -> window_num == <NUM_LIT> ) { sum = window_list -> prev -> window_size + window_list -> window_size ; if ( sum == <NUM_LIT> || ( ix86_min_insn_size ( insn ) + sum ) >= <NUM_LIT> ) return true ; } num_restrict = count_num_restricted ( insn , window_list ) ; if ( num_restrict > num_allowable_groups [ group ]


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable (


<s> static void GetMemOperands ( const MachineInstr * MI , unsigned long & baseReg , unsigned long & indexReg ) { if ( ! MI -> memoperands_empty ( ) && ! ( ( MI -> getFlags ( ) & MachineInstr :: FrameSetup ) || ( MI -> getFlags ( ) & MachineInstr :: FrameDestroy ) ) ) { int index = getMemLocation ( MI ) ; baseReg = MI -> getOperand ( index ) . getReg ( ) ; indexReg = MI -> getOperand ( index + <NUM_LIT> ) . getReg ( ) ; } else { baseReg = <STR_LIT> ; indexReg =


<s> static void csky_asm_trampoline_template ( FILE * f ) { if ( CSKY_ISA_FEATURE ( <NUM_LIT> ) ) { fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ; fprintf ( f , <STR_LIT> ) ; } else if ( CSKY_TARGET_ARCH ( CK801 ) ) { sorry ( <STR_LIT> ) ; } else { fprintf ( f , <STR_LIT> , reg_names [ CSKY_T1_REGNUM ] ) ; fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ; fprintf ( f , <STR_LIT> , reg_names [ CSKY_T1_REGNUM ] ) ; fprintf ( f , <STR_LIT> ) ; } fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f


<s> return __builtin_mve_vmovltq_m_sv8hi ( __arm_vuninitializedq_s32 ( )


<s> unsigned Intr = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Intr ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( IsCMN ( LHSDef , CC ) ) { I . getOperand ( <NUM_LIT> ) . setReg ( LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DidFold = true ; } else if ( IsCMN ( RHSDef , CC ) ) { I . getOperand ( <NUM_LIT> ) . setReg ( RHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DidFold = true ; } if ( DidFold ) { static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is32Bit = ( MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ImmFns = selectArithImmed ( I . getOperand ( <NUM_LIT> ) ) ; unsigned Opc = OpcTable [ Is32Bit ] [ ImmFns . hasValue ( ) ] ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; emitCSetForICMP ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , MIRBuilder ) ; I . eraseFromParent


<s> O << <STR_LIT> ; if ( Opcode == <STR_LIT> ) O << '-' ; printOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << '+' ; break ; case <STR_LIT> : O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; break ; case <STR_LIT> : case <STR_LIT> : O << <STR_LIT> ; if ( Opcode == <STR_LIT> ) O << '-' ; printOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O <<


<s> TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; TRI = ST . getRegisterInfo ( ) ; bool Changed = false ; for ( unsigned I = <NUM_LIT> , E = MRI -> getNumVirtRegs ( ) ; I != E ; ++ I ) { Register Reg = Register :: index2VirtReg ( I ) ; if ( ! LIS -> hasInterval ( Reg ) ) continue ; const TargetRegisterClass * RC = MRI -> getRegClass ( Reg ) ; if ( ( RC -> MC -> getSizeInBits ( ) != <NUM_LIT> || ! TRI -> isSGPRClass ( RC ) ) && (

ST . hasGFX90AInsts ( ) || ! TRI -> isAGPRClass ( RC ) ) ) continue ;


<s> Vec = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , SingleTy , Vec ) ; } else { Vec = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , SingleTy , Vec ) ; M -= HwLen ; } } SDValue Idx = DAG . getConstant ( M , dl , <STR_LIT> ) ; SDValue Ex = DAG . getNode ( <STR_LIT> , dl , LegalTy , { Vec , Idx } ) ; SDValue L = Lower . LowerOperation ( Ex , DAG ) ; assert ( L . getNode ( ) ) ; Ops . push_back ( L ) ; } SDValue LV ; if ( <NUM_LIT> * HwLen == VecLen ) { SDValue B0 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) , HwLen } ) ; SDValue L0 = Lower . LowerOperation ( B0 , DAG ) ; SDValue B1 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) + HwLen , HwLen } ) ; SDValue L1 = Lower . LowerOperation ( B1 , DAG ) ; LV = DAG . getNode ( <STR_LIT> , dl , ResTy , { L0 , L1 } ) ; } else { SDValue BV = DAG . getBuildVector ( ResTy , dl , Ops ) ; LV = Lower . LowerOperation ( BV , DAG ) ; } assert ( ! N -> use_empty ( ) ) ; SDValue IS = DAG . getNode ( <STR_LIT> , dl , ResTy , LV ) ; ISel . ReplaceNode ( N , IS . getNode ( )


<s> return ( uint64x2_t ) ( __a == __AARCH64_INT64_C


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG


<s> if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg , RC ) ; } if ( ! R . second ) return std :: make_pair ( ( unsigned ) <NUM_LIT> , ( const TargetRegisterClass * ) <NUM_LIT> ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget -> isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; if ( RC == & <STR_LIT> ) { assert ( Reg % <NUM_LIT> == <NUM_LIT> ) ; Reg >>= <NUM_LIT> ; } } else if ( Prefix == <STR_LIT> ) RC = TRI -> getRegClass ( <STR_LIT> ) ; else if ( Prefix == <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( Subtarget -> isTargetEnvMacho ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( Subtarget -> isTargetCOFF ( ) ) { if ( ! Subtarget -> is64Bit ( ) ) { MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> )


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level


<s> static bool CC_<ISA_LIT>_Intr ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { const MachineFunction & MF = State . getMachineFunction ( ) ; size_t ArgCount = State . getMachineFunction ( ) . getFunction ( ) . arg_size ( ) ; bool Is64Bit = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; unsigned SlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned Offset ; if ( ArgCount == <NUM_LIT> && ValNo == <NUM_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> * SlotSize , Align ( <NUM_LIT> ) ) ; } else if ( ArgCount == <NUM_LIT> && ValNo == <NUM_LIT> ) { Offset = SlotSize ; } else if ( ArgCount == <NUM_LIT> && ValNo == <NUM_LIT> ) { Offset = <NUM_LIT> ; ( void ) State . AllocateStack ( <NUM_LIT> * SlotSize , Align


<s> MachineOperand & CalleeOp = MI . getOperand ( <NUM_LIT> ) ; if ( ! CalleeOp . isGlobal ( ) || CalleeOp . getGlobal ( ) -> getName ( ) != <STR_LIT> ) continue ; Changed = true ; auto InsertPt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; while ( InsertPt != MBB . end ( ) && InsertPt -> isLabel ( ) ) ++ InsertPt ; MachineInstr * Rethrow = nullptr ; if ( EHInfo -> hasThrowUnwindDest ( & MBB ) ) Rethrow = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( EHInfo -> getThrowUnwindDest ( & MBB ) ) ; else Rethrow = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; MBB . erase ( std :: next ( MachineBasicBlock :: iterator ( Rethrow ) ) , MBB . end ( ) ) ; for ( auto * Succ : MBB . successors ( ) ) if ( ! Succ -> isEHPad ( ) ) EraseBBAndChildren ( Succ ) ; } return


<s> assert ( Zeros < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( CRRegs [ <NUM_LIT>


<s> for ( const auto & LI : Succ -> liveins ( ) ) { int RegIdx = mapRegToGPRIndex ( LI . PhysReg ) ; if ( RegIdx >= <NUM_LIT> ) LOHInfos [ RegIdx ] . OneUser = true ; } } for ( const MachineInstr & MI : make_range ( MBB . rbegin ( ) , MBB . rend ( ) ) ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( canDefBePartOfLOH ( MI ) ) { const MachineOperand & Def = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Def . isReg ( ) && Def . isDef ( ) && <STR_LIT> ) ; assert ( Op . isReg ( ) && Op . isUse ( ) && <STR_LIT> ) ; int DefIdx = mapRegToGPRIndex ( Def . getReg ( ) ) ; int OpIdx = mapRegToGPRIndex ( Op


<s> else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ; return RegImmPair { MI . getOperand ( <NUM_LIT> )


<s> for ( regno = first_reg ; regno < NPARM_REGS ( word_mode ) ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( <NUM_LIT> ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , BASE_INCOMING_ARG_REG ( word_mode ) + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( <NUM_LIT> ) + UNITS_PER_WORD * first_reg ) ) ; return address


<s> const <ISA_LIT>TargetMachine & RTM = static_cast < const <ISA_LIT>TargetMachine &


<s> const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; unsigned TempReg = Materialize32BitInt ( Imm , & <STR_LIT> ) ; EmitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) ; return DestReg ; } else if ( VT == <STR_LIT> ) { const TargetRegisterClass * RC


<s> return ( uint32x2_t ) __builtin_neon_vreinterpretv2sidi (


<s> <ISA_LIT>SectionType getType ( ) const { return Type


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIRBuilder ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ; auto TBL1 = MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ; auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { } ) . addReg ( TBL1 . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; RBI . constrainGenericRegister ( Copy . getReg ( <NUM_LIT> ) , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return true


<s> HasLEB128 = true ; PrivateGlobalPrefix = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; UsesELFSectionDirectiveForBSS = true


<s> if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return splitVectorIntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return splitVectorIntUnary ( Op , DAG ) ; assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ; return LowerVectorCTLZInRegLUT ( Op , DL


<s> for ( MVT LegalVecVT : AllVectorVTs ) { setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalVecVT , Custom


<s> bool isReadOnlySegment ( const GlobalValue * GV , <ISA_LIT>AS AS ) { return GV -> getType ( ) -> getAddressSpace ( ) == AS


<s> Units . reset ( RG . Units ) ; return *


<s> return true ; } IndexReg = TmpReg ; Scale = TmpInt ; if ( checkScale ( Scale , ErrMsg ) ) return true ; IC . popOperator ( ) ; } else { IC . pushOperand ( IC_IMM , TmpInt ) ; } break ; } PrevState =


<s> void setSGPRSpillVGPRs ( Register NewVGPR , Optional < int > newFI , int Index ) { SpillVGPRs [ Index ] . VGPR


<s> static unsigned getMultiplicity ( EVT VT ) { unsigned TypeSize = VT . getSizeInBits ( ) ; switch ( TypeSize )


<s> MachineOperand & OldOp1 = OldMI1 . getOperand ( <NUM_LIT> ) ; MachineOperand & OldOp2 = OldMI2 . getOperand ( <NUM_LIT> ) ; MachineOperand & NewOp1 = NewMI1 . getOperand ( <NUM_LIT> ) ; MachineOperand & NewOp2 = NewMI2 . getOperand ( <NUM_LIT> ) ; assert ( OldOp1 . isReg ( ) && OldOp1 . getReg ( ) == <STR_LIT> && OldOp1 . isDead ( ) && <STR_LIT> ) ; assert ( OldOp2 . isReg ( ) && OldOp2 . getReg ( ) == <STR_LIT> && OldOp2 . isDead ( ) && <STR_LIT> ) ; ( void )


<s> virtual const <ISA_LIT>65816InstrInfo * getInstrInfo