<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; bool CallsEHReturn = MF -> callsEHReturn ( ) ; CallingConv :: ID CC = MF -> getFunction ( ) -> getCallingConv ( ) ; if ( MF -> getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) CC = CallingConv :: <ISA_LIT>_INTR ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return


<s> if ( T -> isFloatingPointTy ( ) ) return true ; return


<s> MaxStackSize = std :: max ( CurrentStackSize , MaxStackSize


<s> void <ISA_LIT>Symbolizer :: tryAddingPcLoadReferenceComment ( raw_ostream & cStream , int64_t Value , uint64_t


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Cond = CreateFPCmp ( DAG , Op ) ; assert ( Cond . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return CreateCMovFP ( DAG , Cond , True , False , Op . getDebugLoc


<s> return try_constant_tricks ( value , & x , & y )


<s> getTargetStreamer ( ) . emit<ISA_LIT>WinCFISaveLR ( Offset ) ; return


<s> bool IsHash = TokE . is ( AsmToken :: Hash ) ; if ( ! IsHash && TokE . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int64_t Pattern ; if ( IsHash ) { Parser . Lex ( ) ; const MCExpr * ImmVal ; SS = getLoc ( ) ; if ( Parser . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; auto * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return MatchOperand_ParseFail ; Pattern = MCE -> getValue ( ) ; } else { auto Pat = <STR_LIT> ( TokE . getString ( ) ) ; if ( ! Pat ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Pattern = Pat -> Encoding ; assert ( Pattern >= <NUM_LIT> && Pattern < <NUM_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Pattern , getContext ( ) ) , SS , getLoc ( ) ,


<s> void <ISA_LIT>AsmParser :: getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode =


<s> std :: string featureString ; OwningPtr < const TargetMachine > targetMachine ( T . createTargetMachine ( tripleString , featureString ) ) ; InitRegisterMap ( targetMachine -> getRegisterInfo


<s> int16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> unsigned <ISA_LIT>FastISel :: emitASR_ri ( MVT RetVT , MVT SrcVT , unsigned Op0 , bool Op0IsKill , uint64_t Shift , bool IsZExt ) { assert ( RetVT . SimpleTy >= SrcVT . SimpleTy && <STR_LIT> ) ; assert ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return <ISA_LIT>MaterializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ; Op0 = TmpReg ; Op0IsKill = true ; } return FastEmitInst_rii ( Opc , RC , Op0 ,


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != <NUM_LIT> || isOpSuitableForLDPSTP ( LI ) ) return


<s> unsigned <ISA_LIT>TTIImpl :: getMaxInterleaveFactor ( unsigned VF


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget >


<s> static const char * avr_out_movqi_mr_r_reg_disp_tiny ( rtx_insn * insn , rtx op [ ] , int * plen ) { rtx dest = op [ <NUM_LIT> ] ; rtx src = op [ <NUM_LIT> ] ; rtx x = XEXP ( dest , <NUM_LIT> ) ; if ( reg_overlap_mentioned_p ( src , XEXP ( x , <NUM_LIT> ) ) ) { avr_asm_len ( <STR_LIT> CR_TAB TINY_ADIW ( % I0 , % J0 , % o0 ) CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else { avr_asm_len ( TINY_ADIW ( % I0 , % J0 , % o0 ) CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } if ( ! reg_unused_after ( insn , XEXP ( x , <NUM_LIT> ) ) ) avr_asm_len ( TINY_SBIW ( % I0 , % J0


<s> if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ; SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; unsigned IdxIn128 = IdxVal - ( IdxVal / NumEltsIn128 ) * NumEltsIn128 ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 ,


<s> I != E ; I ++ ) { if ( ! Limit ) return false ; -- Limit ; bool isDef = any_of ( I -> operands ( ) , [ DefReg , TRI ] ( MachineOperand & MOP ) { return MOP . isReg ( ) && MOP . isDef ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && TRI -> regsOverlap ( MOP . getReg ( ) , DefReg ) ; }


<s> MVT DstVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( ! IsSigned && ! <ISA_LIT>SubTarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! <ISA_LIT>SubTarget -> hasFPCVT


<s> else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSBinFormatELF ( ) ) { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) || TheTriple . isWindowsItaniumEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; unsigned InstPtr = is64Bit


<s> return ( global ? DW_EH_PE_indirect : <NUM_LIT> ) | DW_EH_PE_pcrel


<s> if ( GET_CODE ( x ) == CONST_VECTOR && ! neon_make_constant ( x , false ) )


<s> static bool IsMulWideOperandDemotable ( SDValue Op , unsigned OptSize , OperandSignedness & S ) { S = Unknown ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) { EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) == OptSize ) { S = Signed ; return true ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) { EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) == OptSize ) { S = Unsigned ; return


<s> if ( OddSPReg ) Value |= ( uint32_t ) <STR_LIT> ; return Value


<s> inline vector unsigned char vec_vpkuhum ( vector unsigned short a1 , vector unsigned short a2 ) { return ( vector unsigned char ) __builtin_altivec_vpkuhum ( ( vector signed short


<s> if ( ! isDwordAligned ( ByteOffset ) && ! hasSMEMByteOffset ( ST ) ) return None ; assert ( isCI ( ST ) ) ; int64_t EncodedOffset = convertSMRDOffsetUnits ( ST


<s> bool hasCarry ( ) const { return HasCarry


<s> const TargetInstrDesc & TID = get ( Opc ) ; const TargetOperandInfo & TOI = TID . OpInfo [ Index ] ; const TargetRegisterClass * RC = TOI . isLookupPtrRegClass ( ) ? RI . getPointerRegClass ( ) : RI . getRegClass ( TOI . RegClass ) ; unsigned NumDefs = TID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <NUM_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( FoldedLoad ) { MVT VT = * RC -> vt_begin ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; Load = DAG . getTargetNode ( getLoadRegOpcode ( RC , isAligned ) , dl , VT , <STR_LIT> , & AddrOps [ <NUM_LIT> ] , AddrOps . size ( ) ) ; NewNodes . push_back ( Load ) ; } std :: vector < MVT > VTs ; const TargetRegisterClass * DstRC = <NUM_LIT> ; if ( TID . getNumDefs ( ) > <NUM_LIT> ) { const TargetOperandInfo & DstTOI = TID . OpInfo [ <NUM_LIT> ] ; DstRC = DstTOI . isLookupPtrRegClass ( ) ? RI . getPointerRegClass ( ) : RI . getRegClass ( DstTOI . RegClass ) ; VTs . push_back ( * DstRC -> vt_begin ( ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues (


<s> MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( ! Result ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result


<s> if ( LD -> getMemoryVT ( ) != MemVT ) return false ; RLI . Ptr = LD -> getBasePtr ( ) ; if ( LD -> isIndexed ( ) && ! LD -> getOffset ( ) . isUndef ( ) ) { assert ( LD -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; RLI . Ptr = DAG . getNode ( <STR_LIT> , dl , RLI . Ptr . getValueType ( ) , RLI . Ptr , LD -> getOffset ( ) ) ; } RLI . Chain = LD -> getChain ( ) ; RLI . MPI = LD -> getPointerInfo ( ) ; RLI . IsInvariant = LD -> isInvariant ( ) ; RLI . Alignment = LD -> getAlignment ( ) ; RLI . AAInfo = LD -> getAAInfo ( ) ; RLI . Ranges = LD -> getRanges (


<s> static void emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE /


<s> return ( __m256i ) __builtin_ia32_cvttpd2uqq256_mask ( ( __v4df ) __A , ( __v4di ) __W , (


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return


<s> return ( __m256 ) __builtin_ia32_cvtqq2ps512_mask ( ( __v8di ) __A , ( __v8sf ) _mm256_setzero_ps ( ) ,


<s> static bool xtensa_uimm8 ( HOST_WIDE_INT v ) { return v >= <NUM_LIT> && v


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCSetForICMP ( unsigned DefReg , unsigned Pred , MachineIRBuilder & MIRBuilder ) const { const <STR_LIT> InvCC = changeICMPPredTo<ISA_LIT>CC ( CmpInst :: getInversePredicate (


<s> bool <ISA_LIT>AdjustOptImpl :: run ( ) { for ( Function & F : * M ) for ( auto & BB : F ) { adjustBasicBlock ( BB ) ; for ( auto & I : BB ) adjustInst ( I ) ; } return insertPassThrough (


<s> if ( ( ( MaskVT . getScalarSizeInBits ( ) == <NUM_LIT> ) || ( MaskVT . getScalarSizeInBits ( ) == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && FloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX512 ( )


<s> bool GenerateTBB = isThumb2 || ( isThumb1 && SynthesizeThumb1TBB ) ; if ( STI -> hardenSlsRetBr ( ) ) GenerateTBB = false ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } MadeChange |= AlignBlocks ( MF ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( Align ( <NUM_LIT> ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true


<s> case VK_<ISA_LIT>_None : closeParen = false ; break ; case VK_<ISA_LIT>_LO12 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI20 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PCREL_LO12 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PCREL_HI20 : OS << <STR_LIT>


<s> if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , NULL , <NUM_LIT> , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , DstVT , dl , Store , MemTmp , NULL , <NUM_LIT> , MemVT , false , false , <NUM_LIT> ) ; --


<s> while ( ! MI -> getOperand ( FIOperandNum ) . isFI ( ) ) { ++ FIOperandNum ; assert ( FIOperandNum < MI -> getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = getOffsetONFromFION ( * MI , FIOperandNum ) ; Offset += MI -> getOperand ( OffsetOperandNo )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS || Load -> getPointerAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa

< AtomicCmpXchgInst > ( V ) ) return true ;


<s> int main ( void ) { for ( const avr_mcu_t * mcu = avr_mcu_types ; mcu -> name ; mcu ++ ) print_mcu ( mcu ) ; return


<s> createSysAlias ( IC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * DC = <STR_LIT> ( Op ) ; if ( ! DC ) return TokError ( <STR_LIT> ) ; else if ( ! DC -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( DC -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( DC -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( DC -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * AT = <STR_LIT> ( Op ) ; if ( ! AT ) return TokError ( <STR_LIT> ) ; else if ( ! AT -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( AT -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( AT -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( AT -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str . c_str ( ) ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) .


<s> auto Prepare = [ & ] ( ) { AllocaAddr = CreateAllocaInst ( Builder , Bitcast -> getParent ( ) ) ; I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( Bitcast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II )


<s> if ( I -> isDebugValue ( ) ) continue ; if ( Triple ( TM . getTargetTriple ( ) ) . isOSNaCl ( ) ) { int Dummy ; Iter FI ( llvm :: next ( I ) . base ( ) ) ; if ( terminateSearch ( * I ) || ( IsDangerousLoad ( * FI , & Dummy ) || IsDangerousStore ( * FI , & Dummy ) || FI -> modifiesRegister ( <STR_LIT> , TM . getRegisterInfo ( ) ) ) ) break ; } else { if ( terminateSearch ( * I )


<s> if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ||


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL (

computeDataLayout ( Subtarget ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> setSchedulingPreference ( Sched :: Source ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) )


<s> PM . add ( create<ISA_LIT>ExpandPseudoPass ( * this


<s> if ( ! HII -> isExtendable ( & MI ) && ! HII -> isExtended ( & MI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { int ExtOpNum = HII -> getCExtOpNum ( & MI ) ; MachineOperand & MO = MI . getOperand (


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int Offset = MFI -> getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { Offset += getExtraSlotsForProtection ( MF ) ; return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( RegInfo -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { Offset += getExtraSlotsForProtection ( MF ) ; return Offset + RegInfo -> getSlotSize ( ) ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI -> getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! hasFP ( MF ) ) return Offset + StackSize ; Offset += getExtraSlotsForProtection ( MF ) ; Offset += RegInfo -> getSlotSize ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) Offset -=


<s> MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; if ( ! Def ) return std :: make_pair ( Reg , <NUM_LIT> ) ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ) { unsigned Offset ; const MachineOperand & Op = Def -> getOperand ( <NUM_LIT> ) ; if ( Op . isImm ( ) ) Offset = Op . getImm ( ) ; else Offset = Op . getCImm ( ) -> getZExtValue ( ) ; return std :: make_pair ( Register ( ) , Offset ) ; } int64_t Offset ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_ADD ) { if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Offset ) ) ) return std :: make_pair ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset ) ; if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_Copy ( m_ICst ( Offset ) ) ) ) return std :: make_pair ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset ) ; } if ( Def -> getOpcode ( ) == TargetOpcode :: G_PTRTOINT ) { MachineInstr * Base ; if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_GPtrAdd ( m_MInstr ( Base ) , m_ICst ( Offset ) ) ) ) { if ( Base -> getOpcode ( ) == TargetOpcode :: G_INTTOPTR ) return std :: make_pair ( Base -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset ) ; return std :: make_pair ( Base -> getOperand ( <NUM_LIT> ) . getReg (


<s> if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ) if ( auto * AmtConst = AmtBV -> getConstantSplatNode ( ) ) SraAmt = AmtConst -> getZExtValue ( ) ; } else if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; } if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { assert ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) ; SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1 , SubOp2 ) ) ; } } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast ( BlendVT


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ExecBranchStack . push_back ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case <STR_LIT> : if ( MBB . isLayoutSuccessor ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : MadeChange = true ; kill ( MI ) ; if ( ExecBranchStack . empty ( ) ) { if ( skipIfDead ( MI , * NextBB ) ) { HaveSkipBlock = true ; NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else { HaveKill = true ; } MI . eraseFromParent ( ) ; break ; case <STR_LIT> : assert ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end


<s> APInt UndefBits ( CstSizeInBits , <NUM_LIT> ) ; APInt MaskBits ( CstSizeInBits , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumCstElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return false ; unsigned BitOffset = i * CstEltSizeInBits ; if ( isa < UndefValue > ( COp ) ) { UndefBits . setBits ( BitOffset , BitOffset + CstEltSizeInBits ) ; continue ; } MaskBits . insertBits ( cast < ConstantInt > ( COp ) -> getValue ( ) , BitOffset ) ; } for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { unsigned BitOffset = i * MaskEltSizeInBits


<s> const SDValue NegOne = DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ; const SDValue FiftyOne = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , One ) ; SDValue Exp = extractF64Exponent ( Hi , SL , DAG ) ; const SDValue Mask = DAG . getConstant ( INT64_C ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue M = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mask , Exp ) ; SDValue D = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( INT64_C ( <NUM_LIT> ) , <STR_LIT> ) , Exp ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , L , M ) ; SDValue Tmp1 = DAG . getSetCC ( SL , SetCCVT , DAG .

getConstant ( <NUM_LIT> , <STR_LIT> ) , Tmp0 , <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT>


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( OffsetReg


<s> printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT>


<s> return ( uint64x2_t ) __builtin_neon_vmlalu_nv2si ( ( int64x2_t ) __a ,


<s> calculate_dominance_info ( CDI_DOMINATORS ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_md_add_problem ( ) ; df_analyze ( ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( scalar_to_vector_candidate_p ( insn ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) ) ; bitmap_set_bit ( candidates , INSN_UID ( insn ) ) ; } } remove_non_convertible_regs ( candidates ) ; if ( bitmap_empty_p ( candidates ) ) if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; while ( ! bitmap_empty_p ( candidates ) ) { unsigned uid = bitmap_first_set_bit ( candidates ) ; scalar_chain chain ; chain . build ( candidates , uid ) ; if ( chain . compute_convert_gain ( ) > <NUM_LIT> ) converted_insns += chain . convert ( ) ; else if ( dump_file ) fprintf ( dump_file , <STR_LIT> , chain . chain_id ) ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , converted_insns ) ; BITMAP_FREE ( candidates ) ; bitmap_obstack_release ( NULL


<s> return MI -> getOpcode ( ) == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) &&

( ! usesIXAddr ( * MI ) || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> if ( Subtarget -> hasXMMInt ( ) ) return <STR_LIT> ; if ( Subtarget -> hasXMM ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> && Subtarget -> hasXMMInt ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return


<s> return & InstrInfo . getRegisterInfo (


<s> unsigned getNumFixupKinds ( ) const override


<s> void <ISA_LIT>TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ; if ( ! Res . getNode ( ) ) return ; assert ( ( N -> getNumValues ( ) <= Res -> getNumValues (


<s> if ( isSingleInputShuffleMask ( Mask ) ) { if ( Subtarget -> hasSSE3 ( ) ) if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask

[ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) {


<s> <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc (


<s> static inline const MachineInstrBuilder & addDirectMem ( const MachineInstrBuilder & MIB , unsigned


<s> auto MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = Op . getConstantOperandVal (


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateExpr ( getTLSReg (


<s> Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasFnAttr ( Attribute :: Naked ) ) { return Chain ; } const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned RetOpc = AFI -> isInterruptOrSignalHandler ( ) ? <STR_LIT> : <STR_LIT> ; RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode (


<s> else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity += <NUM_LIT> ; } if ( AM . Disp && ( AM . Base_Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity ++ ; if ( Complexity <= <NUM_LIT> ) return


<s> MachineInstr * MI = & * I ; RegisterSet Undefs ; for ( unsigned i = MI -> getNumOperands ( ) ; i > <NUM_LIT> ; -- i ) { MachineOperand & MO = MI -> getOperand ( i - <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . isImplicit ( ) && MO . isUndef ( ) ) { MI -> RemoveOperand ( i - <NUM_LIT> ) ; Undefs . insert ( MO .


<s> bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; if ( TLI . isNegatibleForFree ( N2 , DAG , LegalOperations , CodeSize ) != <NUM_LIT> ) return SDValue ( ) ; SDValue NegN2 = TLI . getNegatedExpression ( N2 , DAG , LegalOperations , CodeSize ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , false , true , false ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegN2 , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> )


<s> } RegisterRef NR = PRI . normalize ( RR ) ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) { if ( ( F -> second & NR . Mask ) . any ( ) ) return true ; } if ( CheckUnits || PRI . hasPartialOverlaps ( NR . Reg ) ) { for ( MCRegUnitMaskIterator U ( RR . Reg , & PRI . getTRI ( ) ) ; U . isValid ( ) ; ++ U ) { std :: pair < RegisterId , LaneBitmask


<s> bool <ISA_LIT>BaseInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) || ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT>


<s> bool getReqNTIDx ( const Function & F , unsigned & x ) { return findOneNVVMAnnotation ( & F , <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MIOpIdx = getImmOperandIndex ( Instr , Bead ) ; assert ( ( ( OpType [ MIOpIdx ] == OperandType :: Invalid ) || ( OpType [ MIOpIdx ] == OperandType :: Imm ) ) && <STR_LIT> ) ; OpType [ MIOpIdx ] = OperandType :: Imm ; decodeImm ( Instr , Bead , Reader , Scratch [ MIOpIdx ] ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } for ( unsigned DstMIOpIdx = <NUM_LIT> ; DstMIOpIdx < NumOperands ; ++ DstMIOpIdx ) { int TiedTo = Desc . getOperandConstraint ( DstMIOpIdx , MCOI :: TIED_TO ) ; if ( TiedTo < <NUM_LIT> ) continue ; unsigned SrcMIOpIdx = TiedTo ; unsigned OpCount = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; ; ++ I ) { unsigned Offset = <STR_LIT> ( Instr . getOpcode ( ) , I ) ; assert ( Offset <= SrcMIOpIdx && <STR_LIT> ) ; if ( Offset == SrcMIOpIdx ) { OpCount = <STR_LIT> ( Instr . getOpcode ( ) , I ) ; break ; } } assert ( OpCount != <NUM_LIT> && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < OpCount ; ++ I ) { assert ( OpType [ DstMIOpIdx + I ] == OperandType :: Invalid && <STR_LIT> ) ; OpType [ DstMIOpIdx + I ] = OpType [ SrcMIOpIdx + I ] ; Scratch [ DstMIOpIdx + I ] = Scratch [ SrcMIOpIdx + I ] ; } } for ( unsigned O = <NUM_LIT> ; O < NumOperands ; ++ O ) { switch ( OpType [ O ] ) { case OperandType :: Invalid : assert ( false &&


<s> default : gcc_unreachable ( ) ; } } if ( y == const0_rtx && ( REG_P ( x ) || SUBREG_P ( x ) ) && ( code == EQ || code == NE ) && ( mode_x == HImode || mode_x == QImode ) ) return CC_NZmode ; if ( y == const0_rtx && code_x == ZERO_EXTEND && ( mode_x == SImode || mode_x == DImode ) && ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == HImode || GET_MODE ( XEXP ( x , <NUM_LIT> ) ) == QImode ) && ( code == EQ || code == NE ) ) return CC_NZmode ; if ( ( mode_x == SImode || mode_x == DImode ) && y == const0_rtx && ( code == EQ || code == NE || code == LT || code == GE ) && ( code_x == PLUS || code_x == MINUS || code_x == AND || code_x == NEG || ( code_x == ZERO_EXTRACT && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) ) ) return CC_NZmode ; if ( ( mode_x == SImode || mode_x == DImode ) && ( REG_P ( y ) || SUBREG_P ( y ) || y == const0_rtx ) && ( code_x == ASHIFT || code_x == ASHIFTRT || code_x == LSHIFTRT || code_x == ZERO_EXTEND || code_x == SIGN_EXTEND ) ) return CC_SWPmode ; if ( ( mode_x == SImode || mode_x == DImode ) && ( REG_P ( y ) || SUBREG_P ( y ) ) && ( code == EQ

|| code == NE ) && code_x == NEG ) return CC_Zmode ;


<s> uint32_t Value = <NUM_LIT> ; if ( OddSPReg ) Value |= ( uint32_t ) AFL_FLAGS1_ODDSPREG ; return Value


<s> assert ( index < <ISA_LIT>Samplers . size ( ) && <STR_LIT> ) ; return <ISA_LIT>Samplers [ index ] -> getVal (


<s> unsigned Align = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; Register List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; Register DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; auto ListTmp = MIRBuilder . buildGEP ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits


<s> return TFI -> hasFP ( MF ) ? <STR_LIT> :


<s> if ( NumElts < <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ConcatMask ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ConcatMask [ i ] = i ; for ( unsigned i = NumElts ; i != <NUM_LIT> ; ++ i ) ConcatMask [ i ] = ( i % NumElts ) + NumElts ; Value * Zero = Constant :: getNullValue ( Op0 -> getType ( ) ) ; Op0 = Builder . CreateShuffleVector ( Op0 , Zero , ConcatMask ) ; Op1 = Builder . CreateShuffleVector ( Op1 , Zero , ConcatMask ) ; NumElts = <NUM_LIT> ; } Type * I32Ty = VectorType :: get ( Builder . getInt32Ty ( ) , IntrinsicNumElts / <NUM_LIT> ) ; assert ( NumElts % IntrinsicNumElts == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSplits = NumElts / IntrinsicNumElts ; SmallVector < Value * , <NUM_LIT> > Ops ( NumSplits ) ; for ( unsigned i = <NUM_LIT> ; i != NumSplits ; ++ i ) { SmallVector < int , <NUM_LIT> > ExtractMask ( IntrinsicNumElts ) ; std :: iota ( ExtractMask . begin ( ) , ExtractMask . end ( ) , i * IntrinsicNumElts ) ; Value * ExtractOp0 = Builder . CreateShuffleVector ( Op0 , Op0 , ExtractMask ) ; Value * ExtractOp1 = Builder . CreateShuffleVector ( Op1 , Op0 , ExtractMask ) ; Ops [ i ] = Builder . CreateCall ( PSADBWFn , { ExtractOp0 , ExtractOp1 } ) ; Ops [ i ] = Builder . CreateBitCast ( Ops [ i ] , I32Ty ) ; } assert ( isPowerOf2_32 ( NumSplits ) && <STR_LIT> ) ; unsigned Stages = Log2_32 ( NumSplits ) ; for ( unsigned s = Stages ; s > <NUM_LIT> ; -- s ) { unsigned NumConcatElts = cast < VectorType > ( Ops [ <NUM_LIT> ] -> getType ( ) ) -> getNumElements ( ) * <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> << ( s - <NUM_LIT> ) ; ++ i ) { SmallVector < int , <NUM_LIT> > ConcatMask ( NumConcatElts ) ; std :: iota ( ConcatMask . begin ( ) , ConcatMask . end ( ) , <NUM_LIT> ) ; Ops [ i ] = Builder . CreateShuffleVector ( Ops [ i * <NUM_LIT> ] , Ops [ i * <NUM_LIT> + <NUM_LIT> ] , ConcatMask ) ; } } NumElts = cast < VectorType > ( OpTy ) -> getNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { Ops [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , ArrayRef < int > { <NUM_LIT> , <NUM_LIT> } ) ; } else if ( NumElts >= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> >


<s> static bool memOpAlign ( unsigned DstAlign , unsigned SrcAlign ,


<s> VNPair <ISA_LIT>Z80PostPEI :: getVNsAfter ( MachineInstr * MI , unsigned Reg ) { VNPair P = { nullptr , nullptr } ; bool FirstSet = false ; SlotIndex Idx = LI -> getInstructionIndex ( * MI ) ; for ( MCRegUnitIterator Units ( Reg , TRI ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LI -> getRegUnit ( * Units ) ; VNInfo * VN = LR . getVNInfoAt ( Idx ) ; if ( ! FirstSet ) { P . first = VN ; FirstSet =


<s> unsigned Align = std :: max ( TargetAlign , MFI -> getMaxAlignment ( ) ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; unsigned AlignMask = Align - <NUM_LIT> ; unsigned maxCallFrameSize = MFI ->


<s> if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true ,


<s> const unsigned UB = getScoreUB ( T ) ; if ( ( UB >= ScoreToWait ) && ( ScoreToWait > LB ) ) { if ( ( T == VM_CNT || T == LGKM_CNT ) && hasPendingFlat ( ) && ! ST -> hasFlatLgkmVMemCountInOrder ( ) ) { addWait ( Wait , T


<s> if ( ArgFlags . isHva ( ) ) return true ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; } if ( ! ValVT . isFloatingPoint ( ) ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: Indirect ; ArgFlags . setInReg (


<s> case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , <STR_LIT> ) ; break ; } if ( Subtarget -> isPICStyleGOT ( ) || Subtarget -> isPICStyleStubPIC ( )


<s> DEBUG ( { unsigned Block = MI -> getParent ( ) -> getNumber ( ) ; const BasicBlockInfo & BBI = BBInfo [ Block ] ; dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << Block << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ; } )


<s> case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; } return MI .


<s> static DecodeStatus DecodeTS1AMI64 ( MCInst & MI , uint64_t insn , uint64_t Address , const void * Decoder ) { return DecodeCAS ( MI , insn , Address , Decoder , false


<s> unsigned HiLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; const RegisterBank * Bank = getRegBank ( Reg , * MRI , * TRI ) ; MRI -> setRegBank ( LoLHS , * Bank ) ; MRI -> setRegBank ( HiLHS , * Bank ) ; Regs . push_back ( LoLHS ) ; Regs . push_back ( HiLHS ) ; B . buildInstr ( <STR_LIT> ) . addDef ( LoLHS ) .


<s> if ( TARGET_C3X || ! c4x_immed_int_constant ( op ) ) return <NUM_LIT> ; return IS_INT5_CONST ( INTVAL (


<s> unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT>


<s> HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS


<s> MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> isThreadLocal ( ) ? MMIMachO . getThreadLocalGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; return MCSym ; } else if ( Subtarget -> isTargetCOFF ( ) ) { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & <STR_LIT> ) ; if ( ! IsIndirect ) return getSymbol ( GV


<s> return ( __m128i ) __builtin_ia32_vcvtph2w128_mask ( __B , ( __v8hi ) _mm_setzero_si128 ( ) ,


<s> assert ( NarrowTy . isScalar ( ) && <STR_LIT> ) ; MachineOperand & LaneIdxOp = I . getOperand ( <NUM_LIT> ) ; assert ( LaneIdxOp . isReg ( ) && <STR_LIT> ) ; if ( RBI . getRegBank ( DstReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto VRegAndVal = getConstantVRegValWithLookThrough ( LaneIdxOp . getReg ( ) , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value ; MachineIRBuilder MIRBuilder ( I ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; MachineInstr * Extract = emitExtractVectorElt ( DstReg , DstRB , NarrowTy , SrcReg , LaneIdx , MIRBuilder ) ; if ( ! Extract


<s> int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn ,

& num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCLIPU ( SDValue Dest , SDValue & SRC1 , SDValue


<s> bool mergeStoresAfterLegalization ( ) const


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry (


<s> vmode = vmode_ ; chain_id = ++ max_id ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , chain_id ) ; bitmap_obstack_initialize ( NULL ) ; insns = BITMAP_ALLOC ( NULL ) ; defs = BITMAP_ALLOC ( NULL ) ; defs_conv = BITMAP_ALLOC ( NULL ) ; queue =


<s> static DecodeStatus DecodeSysRegOperand ( const <STR_LIT> & Mapper , llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { bool ValidNamed ; Mapper . toString ( Val


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , MO

. getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> bool FoldAsMAD = tryAddToFoldList ( FoldList , MI , OpNo , OpToFold , TII ) ; if ( FoldAsMAD ) { MI -> untieRegOperand ( OpNo ) ; return true ; } MI -> setDesc ( TII -> get ( Opc ) ) ; } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) OpNo =


<s> <ISA_LIT>PreAllocateWWMRegs ( ) : MachineFunctionPass (


<s> unsigned Opcode = <NUM_LIT> ; if ( F -> getIntrinsicID ( ) != <STR_LIT> ) { switch ( F -> getIntrinsicID ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : return true ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc_copysign : case LibFunc_copysignf : continue ; case LibFunc_copysignl : return true ; case LibFunc_fabs : case LibFunc_fabsf : case LibFunc_fabsl : continue ; case LibFunc_sqrt : case LibFunc_sqrtf : case LibFunc_sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc_floor : case LibFunc_floorf : case LibFunc_floorl : Opcode = <STR_LIT> ; break ; case LibFunc_nearbyint : case LibFunc_nearbyintf : case LibFunc_nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc_ceil : case LibFunc_ceilf : case LibFunc_ceill : Opcode = <STR_LIT> ; break ; case LibFunc_rint : case LibFunc_rintf : case LibFunc_rintl : Opcode = <STR_LIT> ; break ; case LibFunc_round : case LibFunc_roundf : case LibFunc_roundl : Opcode = <STR_LIT> ; break ; case LibFunc_trunc : case LibFunc_truncf : case LibFunc_truncl : Opcode = <STR_LIT> ; break ; case LibFunc_fmin : case LibFunc_fminf : case LibFunc_fminl : Opcode = <STR_LIT> ; break ; case LibFunc_fmax : case LibFunc_fmaxf


<s> bool <ISA_LIT>AsmParser :: mnemonicIsValid ( StringRef Mnemonic , unsigned VariantID ) { const MatchEntry * Start , * End ; switch ( VariantID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : Start = std :: begin ( MatchTable0 ) ; End = std :: end ( MatchTable0 ) ; break ; } auto MnemonicRange = std :: equal_range ( Start , End , Mnemonic , LessOpcode ( ) ) ; return MnemonicRange . first != MnemonicRange . second


<s> RtMI = Paired ; Rt2MI = I ; } else { RtMI = I ; Rt2MI = Paired ; } int OffsetImm = RtMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp ) OffsetImm /= OffsetStride ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , InsertionPoint , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( RtMI -> getOperand ( <NUM_LIT> ) ) . addOperand ( Rt2MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( BaseRegOp ) . addImm ( OffsetImm ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Paired -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs (


<s> return Subtarget -> hasVFP2Base ( ) ; case <STR_LIT> : return Subtarget -> hasVFP2Base ( ) ; case <STR_LIT> : return Subtarget -> hasFP64 ( ) ; case <STR_LIT> : case <STR_LIT> : return Subtarget -> hasMVEFloatOps ( ) ; default : return false


<s> Register NewReg = MRI . createGenericVirtualRegister ( Ty ) ; MRI . addLiveIn (


<s> static inline AddrOpc getAM3Op ( unsigned AM3Opc ) { return ( ( AM3Opc >> <NUM_LIT> ) & <NUM_LIT> ) ? sub


<s> return ( vec_adds ( a , ( vec_int4 ) (


<s> void <ISA_LIT>InstPrinter :: printVPTPredicateOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream &


<s> ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) { if ( NMask [ i ] > <NUM_LIT> && OpMask [ NMask [ i ] ] > <NUM_LIT> && OpMask [ NMask [ i ] ] != i ) return SDValue ( ) ; } return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , Op . getValueType ( ) ,

Op0 -> getOperand ( <NUM_LIT> ) , Op1 -> getOperand ( <NUM_LIT> ) ) ;


<s> assert ( pParent . getSymGOTPLTMap ( ) . lookUp ( * rsym ) == NULL && <STR_LIT> ) ; <ISA_LIT>GOTEntry * gotplt_entry = ld_backend . getGOT ( ) . createGOTPLT ( ) ; pParent . getSymGOTPLTMap ( ) . record ( * rsym , * gotplt_entry ) ; Relocation & rel_entry = * ld_backend . getRelPLT ( ) . create ( ) ; rel_entry . setType ( llvm :: ELF :: R_<ISA_LIT>_JUMP_SLOT


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . use<ISA_LIT>PostRASchedStrategy ( ) ) return create<ISA_LIT>PostMachineScheduler (


<s> if ( SrcSC == SC :: Generic && isGenericCastablePtr ( DstSC ) ) return selectUnOp ( ResVReg , ResType , I , <STR_LIT> ) ; if ( isGenericCastablePtr ( SrcSC ) && isGenericCastablePtr ( DstSC ) ) { Register Tmp = MRI -> createVirtualRegister ( & <STR_LIT> ) ; <ISA_LIT>Type * GenericPtrTy = GR . getOrCreate<ISA_LIT>PointerType ( SrcPtrTy , I , TII , StorageClass :: Generic ) ; MachineBasicBlock & BB = * I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; bool Success = BuildMI ( BB , I , DL , TII . get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( GR . get<ISA_LIT>TypeID ( GenericPtrTy ) ) . addUse ( SrcPtr ) . constrainAllUses ( TII , TRI , RBI ) ; return Success && BuildMI ( BB , I , DL , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse (

Tmp ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> bool invert = invertFPCondCodeUser ( ( <STR_LIT> ) CC -> getSExtValue ( ) ) ; return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL , True .

getValueType ( ) , True , False , Cond ) ;


<s> if ( regno >= FIRST_PSEUDO_REGISTER ) return INVALID_REGNUM ; if ( ! TEST_HARD_REG_BIT ( reg_class_contents [ CR_REGS ] , regno


<s> assert ( BB && <STR_LIT> ) ; BasicBlock :: iterator ItNew = BB -> begin ( ) ; return


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT>


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT>


<s> CASE ( AccessQualifier , ReadOnly ) CASE ( AccessQualifier , WriteOnly ) CASE (


<s> ComplexRendererFns selectAddrModeUnscaled128 ( MachineOperand & Root ) const { return selectAddrModeUnscaled ( Root


<s> TargetJITInfo :: StubLayout <ISA_LIT>JITInfo ::


<s> uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; const unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; int NewOpcode = - <NUM_LIT> ; if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back (


<s> void <ISA_LIT>AsmPrinter :: NaClAlignIndirectJumpTargets ( MachineFunction & MF ) { if ( MachineJumpTableInfo * JtInfo = MF . getJumpTableInfo ( ) ) { const std :: vector < MachineJumpTableEntry > & JT = JtInfo -> getJumpTables ( ) ; for ( unsigned I = <NUM_LIT> ; I < JT . size ( ) ; ++


<s> static bool nios2_rtx_costs ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : if ( INTVAL ( x ) == <NUM_LIT> ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else if ( nios2_simple_const_p ( x ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case LABEL_REF : case SYMBOL_REF : case CONST : case CONST_DOUBLE : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case AND : { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == NOT && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == NOT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; } case MULT : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case SIGN_EXTEND : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false


<s> return Op ; } } if ( <STR_LIT> ( SVOp , false ) || <STR_LIT> ( SVOp , false ) || <STR_LIT> ( SVOp , false ) != - <NUM_LIT> || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) ) return Op ; SmallVector < int , <NUM_LIT> > PermMask ; SVOp -> getMask ( PermMask ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo


<s> void pass_vsetvl :: cleanup_insns ( void ) const { for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { for ( insn_info * insn : bb -> real_nondebug_insns ( ) ) { rtx_insn * rinsn = insn -> rtl ( ) ; if ( vlmax_avl_insn_p ( rinsn ) ) { eliminate_insn ( rinsn ) ; continue ; } if ( ! has_vl_op ( rinsn ) || ! REG_P ( get_vl ( rinsn ) ) ) continue ; rtx avl = get_vl ( rinsn ) ; if ( count_occurrences ( PATTERN ( rinsn ) , avl , <NUM_LIT> ) == <NUM_LIT> ) { auto attempt = crtl -> ssa -> new_change_attempt ( ) ; insn_change change ( insn ) ; access_array_builder uses_builder ( attempt ) ; uses_builder . reserve ( insn -> num_uses ( ) - <NUM_LIT> ) ; for ( use_info * use : insn -> uses ( ) ) if ( use != find_access ( insn -> uses ( ) , REGNO ( avl ) ) ) uses_builder . quick_push ( use ) ; use_array new_uses = use_array ( uses_builder . finish ( ) ) ; change . new_uses = new_uses ; change . move_range = insn -> ebb ( ) -> insn_range ( ) ; rtx pat


<s> static tree arm_lookup_simd_builtin_type ( machine_mode mode , enum arm_type_qualifiers q ) { int i ; int nelts = ARRAY_SIZE ( arm_simd_types ) ; if ( q != qualifier_poly && ! VECTOR_MODE_P ( mode

) ) return arm_simd_builtin_std_type ( mode , q ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerToVVP ( SDValue Op , SelectionDAG & DAG ) const { auto OCOpt = getVVPOpcode ( Op -> getOpcode ( ) ) ; if ( ! OCOpt . hasValue ( ) ) return SDValue ( ) ; unsigned VVPOC = OCOpt . getValue ( ) ; EVT OpVecVT = Op . getValueType ( ) ; EVT LegalVecVT = getTypeToTransformTo ( * DAG . getContext ( ) , OpVecVT ) ; SDLoc DL ( Op ) ; SDValue AVL = DAG . getConstant ( OpVecVT . getVectorNumElements ( ) , DL , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ; SDValue ConstTrue = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , ConstTrue


<s> if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) )

return ( UnsupportedFPMode ) ? <NUM_LIT> : materializeFP ( CFP , VT ) ;


<s> static tree build_const_pointer ( tree t ) { return build_pointer_type ( build_qualified_type (


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32r632 , Instr , Insn , Address , this , STI ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; } if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( hasCOP3 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result !=


<s> const ConstantSDNode * RotConstant = dyn_cast < ConstantSDNode > ( V ) ; assert ( RotConstant && <STR_LIT>


<s> if ( ! isa < Constant > ( RHS ) || ! cast < Constant > ( RHS ) -> isNullValue ( ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLT ; break ; case CmpInst :: ICMP_SGT : case CmpInst :: ICMP_SLE : if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != APInt ( BW , - <NUM_LIT> , true ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLE ; break ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool IsBitTest = TestBit != - <NUM_LIT> ; bool Is64Bit = BW == <NUM_LIT> ; if ( TestBit < <NUM_LIT> && TestBit >= <NUM_LIT> ) Is64Bit = false ; unsigned Opc = OpcTable [ IsBitTest ] [ IsCmpNE ] [ Is64Bit ] ; const MCInstrDesc & II = TII . get ( Opc ) ; unsigned SrcReg = getRegForValue ( LHS ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( LHS ) ; if ( BW == <NUM_LIT> && ! Is64Bit ) SrcReg = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , SrcIsKill , <STR_LIT> ) ; if ( ( BW < <NUM_LIT> ) && ! IsBitTest ) SrcReg = emitIntExt ( VT , SrcReg , <STR_LIT> , true ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) .

addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ;


<s> if ( Offset <= - <NUM_LIT> ) { const Function & F = MF . getFunction ( ) ; DiagnosticInfoUnsupported DiagStackSize ( F , <STR_LIT> <STR_LIT> , DL ) ; F . getContext ( ) .


<s> RoundedA = DAG . getNode ( <STR_LIT> , SL , VT , IsSmall , DAG . getConstantFP ( <NUM_LIT> , SL , VT ) , RoundedA ) ; RoundedA = DAG . getNode ( <STR_LIT> , SL , VT , RoundedA , A ) ; DAG . getNode ( <STR_LIT> , SL , VT , A ) ; SDValue IsLarge = DAG . getSetCC ( SL , SetCCVT , AbsA , DAG . getConstantFP ( pow ( <NUM_LIT> , <NUM_LIT> ) , SL , VT )


<s> bool isAtomicRet ( uint16_t Opcode )


<s> llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget . useSoftFloat ( ) && ! ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget . hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ; Chain = VAARG . getValue (


<s> const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; unsigned Size = TRI -> getSpillSize ( <STR_LIT> ) ; Align Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int TileSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Size = TRI -> getSpillSize ( <STR_LIT> ) ; Alignment = TRI -> getSpillAlign ( <STR_LIT> ) ; int StrideSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Register GR64Cand = <STR_LIT> ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) , StrideSS ) . addReg ( GR64Cand ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , GR64Cand ) . addImm ( <NUM_LIT> ) ; unsigned Opc = <STR_LIT>


<s> return ( __m256i ) __builtin_ia32_vpshrd_v4di ( ( __v4di ) __A ,


<s> for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { s8 , s16 , s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } )


<s> Instruction * MVEGatherScatterLowering :: tryCreateMaskedScatterBaseWB ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ptr -> getType ( ) ,

Input -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) , Input } ) ;


<s> if ( TARGET_64BIT ) for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( regs_live ,

i ) && ! call_used_regs [ i ] ) return ;


<s> FrameReg = TL . getZeroReg ( ) ; if ( static_cast < unsigned > ( FI ) < FrameObjects . size ( ) && ! FrameObjects [ FI ] . isEmpty ( ) ) return getFrameObjectOffset ( FI ) ; const MachineFrameInfo & MFI = MF


<s> x = orig_x ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) == PIC_OFFSET_TABLE_REGNUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST ) { HOST_WIDE_INT offset = <NUM_LIT> ; y = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( y ) == PLUS && GET_CODE ( XEXP ( y , <NUM_LIT> ) ) == CONST_INT ) { offset = INTVAL ( XEXP ( y , <NUM_LIT> ) ) ; y = XEXP ( y , <NUM_LIT> ) ; } if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , <NUM_LIT> ) == UNSPEC_GOTOFF || XINT ( y , <NUM_LIT> ) == UNSPEC_PLTOFF ) ) return plus_constant ( Pmode

, XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) , offset ) ;


<s> case <STR_LIT> : return SDValue ( SVOp , <NUM_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; Scale = <NUM_LIT> ; break ; } SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . Scale ) return false ; if ( AM . BaseGV && AM . HasBaseReg ) return false ; if ( AM . BaseGV ) return


<s> Mask . clear ( ) ; Ops . clear ( ) ; MVT VT = N . getSimpleValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumSizeInBits = VT . getSizeInBits ( ) ; unsigned NumBitsPerElt = VT . getScalarSizeInBits ( ) ; assert ( ( NumBitsPerElt % <NUM_LIT> ) == <NUM_LIT> && ( NumSizeInBits % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode = N . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue N1 = N . getOperand ( <NUM_LIT> ) ; bool IsAndN = ( <STR_LIT> == Opcode ) ; uint64_t ZeroMask = IsAndN ? <NUM_LIT> : <NUM_LIT> ; if ( ! getTargetConstantBitsFromNode ( IsAndN ? N0 : N1 , <NUM_LIT> , UndefElts , EltBits ) ) return false ; for ( int i = <NUM_LIT> , e = ( int ) EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) { Mask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t ByteBits = EltBits [ i ] . getZExtValue ( ) ; if ( ByteBits != <NUM_LIT> && ByteBits != <NUM_LIT> ) return false ; Mask . push_back ( ByteBits == ZeroMask ? SM_SentinelZero : i ) ; } Ops . push_back ( IsAndN ? N1 : N0 ) ; return true ; } case <STR_LIT> : { SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue SrcExtract ; if ( ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) || ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) || ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ) { SrcExtract = N0 ; } if ( ! SrcExtract || ! isa < ConstantSDNode > ( SrcExtract . getOperand ( <NUM_LIT> ) ) ) return false ; SDValue SrcVec = SrcExtract . getOperand ( <NUM_LIT> ) ; EVT SrcVT = SrcVec . getValueType ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; unsigned NumZeros = ( NumBitsPerElt / SrcVT . getScalarSizeInBits ( ) ) - <NUM_LIT> ; unsigned SrcIdx = SrcExtract . getConstantOperandVal ( <NUM_LIT> ) ; if ( NumSrcElts <= SrcIdx ) return false ; Ops . push_back ( SrcVec ) ; Mask . push_back ( SrcIdx ) ; Mask . append ( NumZeros


<s> unsigned VecLen = VT . getVectorMinNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == <NUM_LIT> || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ <NUM_LIT> ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == <STR_LIT> ) return TargetLoweringBase :: TypeWidenVector ; if ( ! isPowerOf2_32 ( VecLen ) ) return TargetLoweringBase ::


<s> DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = Is64BitTarget ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64BitTarget ) : getADDrrOpcode ( Is64BitTarget ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) .


<s> unsigned short base_mode_size = GET_MODE_SIZE ( base_mode ) ; int nregs = size / base_mode_size , i ; rtx regs ; regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( base_mode , regno ) , GEN_INT ( base_mode_size * i ) ) ; regno += base_mode_size / <NUM_LIT>


<s> default : break ; case Instruction :: FPToSI : case Instruction :: FPToUI : case Instruction :: SIToFP : case Instruction :: UIToFP : case Instruction :: FPTrunc : case Instruction :: FPExt : return ! ST -> hasFP<ISA_LIT>v8Base ( ) ; } if ( VT . isInteger ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) { switch ( ISD ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } if ( ! VT . isFloatingPoint ( ) ) return false ; if ( TLI -> useSoftFloat ( ) ) { switch ( I . getOpcode ( ) ) { default : return true ; case Instruction :: Alloca : case Instruction :: Load : case Instruction :: Store : case Instruction :: Select : case Instruction :: PHI : return false ; } } if ( I . getType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( I . getType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return false ; } ; auto IsHardwareLoopIntrinsic = [ ] ( Instruction &


<s> e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; bool is_inthandler = fkind != SUBROUTINE ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE || ( is_inthandler && ! crtl -> is_leaf ) ) ; int ndregs = all ? <NUM_LIT> : n_dregs_to_save ( is_inthandler , false ) ; int npregs = all ? <NUM_LIT> : n_pregs_to_save ( is_inthandler , false ) ; int n = ndregs + npregs ; int i ; if ( all || stack_frame_needed_p ( ) ) n += <NUM_LIT> ; else { if ( must_save_fp_p ( ) ) n ++ ; if ( must_save_rets_p ( ) ) n ++ ; } if ( fkind != SUBROUTINE ||


<s> static bool getRegSeqInit ( SmallVectorImpl < std :: pair < MachineOperand * , unsigned >> & Defs , Register UseReg , uint8_t OpTy , const <ISA_LIT>InstrInfo * TII , const MachineRegisterInfo & MRI ) { MachineInstr * Def = MRI . getVRegDef ( UseReg ) ; if ( ! Def || ! Def -> isRegSequence ( ) ) return false ; for ( unsigned I = <NUM_LIT> , E = Def -> getNumExplicitOperands ( ) ; I < E ; I += <NUM_LIT> ) { MachineOperand * Sub = & Def -> getOperand ( I ) ; assert ( Sub -> isReg ( ) ) ; for ( MachineInstr * SubDef = MRI . getVRegDef ( Sub -> getReg ( ) ) ; SubDef && Sub -> isReg ( ) && Sub -> getReg ( ) . isVirtual ( ) && ! Sub ->

getSubReg ( ) && TII -> isFoldableCopy ( * SubDef ) ;


<s> NodeAllocator ( uint32_t NPB = <NUM_LIT> ) : NodesPerBlock ( NPB ) , BitsPerIndex ( Log2_32 ( NPB ) ) , IndexMask ( ( <NUM_LIT> << BitsPerIndex ) -


<s> MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( <NUM_LIT> < NumElems ) return LowerVectorIntUnary ( Op , DAG ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; assert ( ( NewVT . is256BitVector ( ) || NewVT . is512BitVector ( ) ) && <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CtlzNode = DAG . getNode ( <STR_LIT> , dl , NewVT , Op ) ; SDValue TruncNode = DAG . getNode ( <STR_LIT> , dl , VT , CtlzNode ) ; SDValue Delta = DAG . getConstant ( <NUM_LIT> - EltVT . getSizeInBits ( ) , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , TruncNode


<s> if ( Required . Array [ i ] <= WaitedOn . Array [ i ] ) continue ; NeedWait = true ; if ( Ordered [ i ] ) { unsigned Value = LastIssued . Array [ i ] - Required . Array [ i ] ; Counts . Array [ i ] = std :: min ( Value , HardwareLimits . Array [ i ] ) ; } else Counts . Array [ i ] = <NUM_LIT> ; WaitedOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; } if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( encodeWaitcnt ( IV , Counts . Named . VM ,

Counts . Named . EXP , Counts . Named . LGKM ) ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable (


<s> if ( pic_address_needs_scratch ( x ) ) return false ; if ( sparc_tls_referenced_p ( x ) ) return false ; return


<s> if ( Type == <STR_LIT> ) { unsigned subInst0Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; unsigned subInst1Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; Result += ! isDuplexAGroup (


<s> stmt_cost += rs6000_adjust_vect_cost_per_stmt ( kind , stmt_info ) ; unsigned int orig_count = count ; retval = adjust_cost_for_freq ( stmt_info , where , count * stmt_cost ) ; m_costs [ where ] += retval ; update_target_cost_per_stmt ( kind , stmt_info , where , orig_count ) ; } return retval


<s> return ( int32x4_t ) __builtin_aarch64_srhaddv4si ( __a ,


<s> machine_mode opmode = GET_MODE ( op ) ; machine_mode mode = insn_data [ icode ] . operand [ n + <NUM_LIT> ] . mode ; if ( ( opmode == SImode || opmode == VOIDmode ) && mode == HImode ) { opmode = HImode ; op = gen_lowpart ( HImode , op ) ; } gcc_assert ( opmode == mode || opmode == VOIDmode ) ; if ( ! insn_data [ icode ] . operand [ n + <NUM_LIT> ] . predicate ( op , mode ) ) op = copy_to_mode_reg ( mode , op ) ; xop [ n ] = op ; } switch ( n_args ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , xop [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( pat == NULL_RTX


<s> paddb_s ( int8x8_t s , int8x8_t t ) { return __builtin_loongson_paddb_s ( s ,


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O


<s> using LoopVector = std :: vector < MachineLoop * > ; LoopVector WorkQ ; append_range ( WorkQ , * MLI ) ; for ( unsigned i = <NUM_LIT> ; i < WorkQ . size ( ) ; ++ i ) append_range ( WorkQ , * WorkQ [ i ] ) ; USet Rs ; for ( unsigned i = <NUM_LIT> , n = WorkQ . size ( ) ; i < n ; ++ i ) { MachineLoop * L = WorkQ [ i ] ; Rs . clear ( ) ; collectIndRegsForLoop ( L , Rs )


<s> const __v4si vzero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __asm__ ( <STR_LIT> : <STR_LIT> ( temp ) : <STR_LIT> ( rounded ) : ) ; temp = vec_mergeo ( temp , temp ) ; temp = vec_mergee ( temp , temp ) ; result = ( __v4si ) vec_vpkudum ( ( __vector long long ) temp , ( __vector long long ) vzero ) ; { const __v16qu pkperm = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; result = ( __v4si ) vec_perm ( ( __v16qu ) temp , ( __v16qu ) vzero , pkperm ) ; } return ( __m128i


<s> ValueVec RemoveInstrs ; auto GetRootValue = [ & ] ( Value * V ) -> Value * { while ( isa < CastInst > ( V ) ) { RemoveInstrs . push_back ( V ) ; V = cast < User > ( V ) -> getOperand ( <NUM_LIT> ) ; } return V ; } ; Value * Dst = CI -> getOperand ( <NUM_LIT> ) ; Value * Src = CI -> getOperand ( <NUM_LIT> ) ; Value * Size = CI -> getOperand ( <NUM_LIT> ) ; Dst = GetRootValue


<s> inline bool isU10Constant ( uint64_t Value ) { return ( Value == ( Value & <NUM_LIT> )


<s> print_reg ( gen_rtx_REG ( DImode , regno ) , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , alloc_offset - seh -> reg_offset [ regno ] ) ; } if ( seh -> cfa_reg != stack_pointer_rtx ) { offset = alloc_offset - seh -> cfa_offset ; gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; gcc_assert ( IN_RANGE ( offset , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , f ) ; print_reg ( seh -> cfa_reg , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; } if ( crtl -> accesses_prior_frames ) { offset = seh -> sp_offset - alloc_offset ; if ( offset > <NUM_LIT> && offset < SEH_MAX_FRAME_SIZE ) fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; } fputs ( <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , getDataLayoutString ( TT ) , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , getEffectiveRelocModel ( TT , RM ) , getEffective<ISA_LIT>CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , TargetABI ( computeTargetABI ( TT , Options ) ) { initAsmInfo (


<s> errs ( ) << <STR_LIT> << <STR_LIT> << MI -> getOpcode ( ) << <STR_LIT> << Value ; if ( ShiftBy ) errs ( ) << <STR_LIT> << ( <NUM_LIT> << ShiftBy ) << <STR_LIT> ; assert ( false && <STR_LIT> ) ; } } printOperand ( MI , OpNum ,


<s> bool isSMRD ( uint16_t Opcode ) const { return get ( Opcode ) .


<s> HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; LCOMMDirective = <STR_LIT> ; DwarfRequiresFrameSection = false


<s> static inline uint8_t encodeAdvSIMDModImmType6 ( uint64_t Imm ) { return ( Imm & <NUM_LIT>


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg


<s> static void reservePrivateMemoryRegs ( const TargetMachine & TM , MachineFunction & MF , const <ISA_LIT>RegisterInfo & TRI , <ISA_LIT>MachineFunctionInfo & Info ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; bool HasStackObjects = MFI . hasStackObjects ( ) ; if ( HasStackObjects ) Info . setHasNonSpillStackObjects ( true ) ; if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) HasStackObjects = true ; bool RequiresStackAccess = HasStackObjects || MFI . hasCalls ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ST . isAmdCodeObjectV2 ( MF . getFunction ( ) ) ) { if ( RequiresStackAccess ) { unsigned PrivateSegmentBufferReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; if ( MFI . hasCalls ( ) ) { unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } else


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { llvm_unreachable ( <STR_LIT>


<s> if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { addPass ( & LiveVariablesID , false ) ; addPass ( create<ISA_LIT>TLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( create<ISA_LIT>TOCRegDepsPass


<s> Metadata * LowAndHigh [ ] = { ConstantAsMetadata :: get ( ConstantInt :: get ( I32Ty , Lower -> getValue ( ) . zext ( <NUM_LIT> ) ) ) , ConstantAsMetadata :: get ( ConstantInt :: get ( I32Ty , <NUM_LIT> ) ) } ; WidenLoad -> setMetadata ( LLVMContext :: MD_range , MDNode :: get ( Mod -> getContext ( ) , LowAndHigh ) ) ; } } int TySize = Mod -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) ; Type * IntNTy = Builder . getIntNTy ( TySize ) ; Value * ValTrunc = Builder . CreateTrunc ( WidenLoad , IntNTy ) ; Value * ValOrig = Builder . CreateBitCast ( ValTrunc , I . getType ( )


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>FastEmitExtend ( <STR_LIT> Opc , MVT DstVT , unsigned Src , MVT SrcVT , unsigned & ResultReg ) { unsigned RR = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Opc , Src ) ; if ( RR !=


<s> bool <ISA_LIT>DAGToDAGISel :: SelectARIPI ( SDNode * Parent , SDValue N , SDValue & Base ) { LLVM_DEBUG ( dbgs ( )


<s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { auto * Load = cast < LoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ; return DAG . getMergeValues ( { Result , Load -> getChain ( )


<s> static int mips_fpr_return_fields ( const_tree valtype , tree * fields , bool * has_cxx_zero_width_bf , bool * has_cxx17_empty_base ) { tree field ; int i ; if ( ! TARGET_NEWABI ) return <NUM_LIT> ; if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return <NUM_LIT> ; i = <NUM_LIT> ; for ( field = TYPE_FIELDS ( valtype ) ; field != <NUM_LIT> ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( cxx17_empty_base_field_p ( field ) ) { * has_cxx17_empty_base = true ; continue ; } if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) { * has_cxx_zero_width_bf = true ; continue ; } if ( ! SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field ) )


<s> if ( First ) First = false ; else OS << <STR_LIT> ; OS << <STR_LIT> (


<s> } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) continue ; MI2 = MRI -> getVRegDef ( SrcReg ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI2 || MI2 -> getOpcode ( ) != <STR_LIT> || MI2 -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; SrcReg = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( DefMI ) TruncSize = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( ! DefMI ) continue ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; else if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; } if ( TruncSize == - <NUM_LIT> ) continue ; if ( DefMI ->


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst )


<s> sawStore = true ; if ( sawLoad ) return true ; } for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses


<s> if ( ! F . hasFnAttribute ( <STR_LIT> ) ) ImplicitArgPtr = true ; } else { ImplicitArgPtr = false ; MaxKernArgAlign = std :: max ( ST . getAlignmentForImplicitArgPtr ( ) , MaxKernArgAlign ) ; } bool isAmdHsaOrMesa = ST . isAmdHsaOrMesa ( F ) ; if ( isAmdHsaOrMesa && ! ST . enableFlatScratch ( ) ) PrivateSegmentBuffer = true ; else if ( ST . isMesaGfxShader ( F ) ) ImplicitBufferPtr = true ; if ( ! <STR_LIT> ( CC ) ) { if ( IsKernel || ! F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDX = true ; if ( ! F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDY = true ; if ( ! F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDZ = true ; if ( IsKernel || ! F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDX = true ; if ( ! F . hasFnAttribute ( <STR_LIT> ) && ST . getMaxWorkitemID ( F , <NUM_LIT> ) != <NUM_LIT> ) WorkItemIDY = true ; if ( ! F . hasFnAttribute ( <STR_LIT> ) && ST . getMaxWorkitemID ( F , <NUM_LIT> ) != <NUM_LIT> ) WorkItemIDZ = true ; if ( ! F . hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ; if ( ! F . hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ; if ( ! F . hasFnAttribute ( <STR_LIT> ) ) DispatchID = true ; } bool HasStackObjects = F . hasFnAttribute ( <STR_LIT> ) ; if ( ST . hasFlatAddressSpace ( ) && isEntryFunction ( ) && ( isAmdHsaOrMesa || ST . enableFlatScratch ( ) ) && ( HasCalls || HasStackObjects || ST . enableFlatScratch ( ) ) && ! ST . flatScratchIsArchitected ( ) ) { FlatScratchInit = true ; } if ( isEntryFunction ( ) ) { if ( WorkItemIDZ ) WorkItemIDY = true ; if ( ! ST . flatScratchIsArchitected ( ) ) { PrivateSegmentWaveByteOffset = true ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 && ( CC == CallingConv :: <ISA_LIT>_HS ||

CC == CallingConv :: <ISA_LIT>_GS ) ) ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( <STR_LIT> ) ;


<s> return get ( Opcode ) . TSFlags & ( <STR_LIT> |


<s> static void output_btfext_core_sections ( void ) { size_t i ; bpf_core_section_ref sec ; dw2_asm_output_data ( <NUM_LIT> , sizeof ( struct btf_ext_reloc ) , <STR_LIT> ) ; FOR_EACH_VEC_ELT ( * bpf_core_sections , i , sec ) { sec -> name_offset += ctfc_get_strtab_len ( ctf_get_tu_ctfc ( ) , CTF_STRTAB ) ; dw2_asm_output_data ( <NUM_LIT> , sec -> name_offset , <STR_LIT> ) ; dw2_asm_output_data ( <NUM_LIT> , vec_safe_length ( sec -> relocs ) , <STR_LIT> ) ; output_btfext_core_relocs ( sec


<s> SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewRes = DAG . getNode ( WOpcode , DL ,


<s> bool isLegalMaskedGather ( Type * DataType , Align Alignment ) { return isLegalMaskedGatherScatter ( DataType , Alignment )


<s> for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; if ( regno - start_reg >= <NUM_LIT> - ( crtl -> is_leaf == <NUM_LIT> ) ) { frame -> millicode_start_reg = <NUM_LIT> ; frame -> millicode_end_reg = regno - <NUM_LIT> ; return <NUM_LIT> ; } return <NUM_LIT>


<s> case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: CreateUpper16 ( Expr , OutContext ) ; break ; } break ; } case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_PLT , OutContext ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , OutContext ) , OutContext ) ; return MCOperand :: CreateExpr


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg