<s> case G_CONSTANT : { int Imm = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getValue ( ) . getLimitedValue ( ) ; unsigned LUiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * LUi , * ORi ; LUi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( LUiReg ) . addImm ( Imm >> <NUM_LIT> ) ; ORi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( LUiReg ) . addImm ( Imm & <NUM_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * LUi , TII , TRI , RBI ) ) return false ; if ( ! constrainSelectedInstRegOperands ( * ORi , TII , TRI , RBI ) ) return false ; I . eraseFromParent ( ) ; return true ; } case G_GLOBAL_VALUE : { if ( MF . getTarget ( ) . isPositionIndependent ( ) ) return false ; const llvm :: GlobalValue * GVal = I . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; unsigned LUiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * LUi , * ADDiu ; LUi = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) .

addDef ( LUiReg ) . addGlobalAddress ( GVal ) ;


<s> Triple TheTriple ( TT ) ; bool isV9 = ( TheTriple . getArch ( ) == Triple :: sparcv9 ) ; if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = ( isV9 ) ? <STR_LIT> : <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 =


<s> if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; if ( RVVT == <STR_LIT> && UnsupportedFPMode ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT , IsZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DestReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } MachineInstrBuilder MIB = emitInst ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [ i ] , RegState :: Implicit ) ; return true


<s> } emit_insn ( insn ) ; if ( TARGET_64BIT ) insn = gen_tls_tprel_lo_64 ( dest , tmp , addr ) ; else insn = gen_tls_tprel_lo_32 ( dest , tmp , addr ) ; emit_insn ( insn ) ; } else { rtx got , tga , tmp1 , tmp2 ; if ( TARGET_64BIT ) got = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else { if ( flag_pic == <NUM_LIT> ) got = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; else { rtx gsym = rs6000_got_sym ( ) ; got = gen_reg_rtx ( Pmode ) ; if ( flag_pic == <NUM_LIT> ) rs6000_emit_move ( got , gsym , Pmode ) ; else { rtx mem , lab ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { rtx arg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr , got ) , UNSPEC_TLSGD ) ; tga = rs6000_tls_get_addr ( ) ; global_tlsarg = arg ; if ( TARGET_TLS_MARKERS ) { rtx argreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( argreg , arg ) ) ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , argreg , Pmode ) ; } else emit_library_call_value ( tga , dest ,


<s> static std :: vector < Constant * > createAString ( std :: string input , Type * & Int8Ty ) { std :: vector < Constant


<s> MachineInstrBuilder MIB ; if ( ! isPairedLdSt ( I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( Update ) ) . addOperand ( getLdStRegOp ( I ) ) . addOperand ( getLdStBaseOp ( I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( Update ) ) . addOperand ( getLdStRegOp ( I , <NUM_LIT> ) ) . addOperand ( getLdStRegOp ( I , <NUM_LIT> ) ) . addOperand ( getLdStBaseOp ( I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ; if ( IsPreIdx ) DEBUG ( dbgs ( ) << <STR_LIT> ) ; else DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Update -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( )


<s> FunctionPass * llvm :: create<ISA_LIT>RI5CYIRPass ( ) { return new <ISA_LIT>RI5CYIR (


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setMinFunctionAlignment ( <NUM_LIT> )


<s> StringRef WinEHParentName = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( WinEHParentName != F . getName ( ) && ! WinEHParentName . empty ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isMSVCEHPersonality ( Personality ) ) return false ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; auto * MMIPtr = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; assert ( MMIPtr && <STR_LIT> ) ; MachineModuleInfo & MMI = * MMIPtr ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality :: MSVC_CXX : addCXXStateStores ( F , MMI ) ; break ; case EHPersonality :: MSVC_<ISA_LIT>SEH : addSEHStateStores ( F , MMI ) ; break ; } PersonalityFn = nullptr ; Personality = EHPersonality


<s> rtx op0 , op1 ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; mips_emit_compare ( & code , & op0 , & op1 , true ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , gen_rtx_IF_THEN_ELSE ( GET_MODE ( operands [ <NUM_LIT> ] ) , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , operands [ <NUM_LIT> ]


<s> if ( <STR_LIT> . contains ( Reg ) ) return false ; if ( <STR_LIT> . contains ( Reg ) ) { RegToUseForCFI = getSubReg ( Reg , <STR_LIT> ) ; for ( int I = <NUM_LIT> ; CSR_<ISA_LIT>_AAPCS_SaveList [ I ] ; ++ I ) { if ( CSR_<ISA_LIT>_AAPCS_SaveList [ I ] ==


<s> <ISA_LIT>ConstantPoolValue * CPV = ( <ISA_LIT>ConstantPoolValue * ) Constants [ i ] . Val . MachineCPVal ; if ( CPV -> GV == GV && CPV -> S == S && CPV -> LabelId

== LabelId && CPV -> PCAdjust == PCAdjust ) return i ;


<s> EVT VT = Op . getValueType ( ) ; ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; assert ( ST -> hasMVEIntegerOps ( ) && <STR_LIT> ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isReverseMask ( ShuffleMask , VT ) ) { SDValue cast = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; SDValue rbit = DAG . getNode ( <STR_LIT>


<s> assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; return true ; } } return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : break ; } return nullptr


<s>
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
<NUM_LIT>
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_PROGBITS
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
<STR_LIT>
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
<STR_LIT>
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
&&
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
<STR_LIT>
+
HexLines
[
i
]
+
<STR_LIT>
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[


<s> if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == <NUM_LIT> ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) + <NUM_LIT> ) ; return mep_expand_setcc_1 ( LT , dest , op1 , op2 ) ; case LEU : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == - <NUM_LIT> ) return false ; op2 = GEN_INT ( trunc_int_for_mode ( INTVAL ( op2 ) + <NUM_LIT> , SImode ) ) ; return mep_expand_setcc_1 ( LTU , dest , op1 , op2 ) ; case GE : if ( GET_CODE ( op2 ) != CONST_INT || INTVAL ( op2 ) == trunc_int_for_mode ( <NUM_LIT> , SImode ) ) return false ; op2 = GEN_INT ( INTVAL ( op2 ) -


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int64_t Offset = <NUM_LIT> ; AMDGPUAsmParser :: OperandMatchResultTy Res = parseIntWithPrefix ( Prefix , Offset ) ; if ( Res != MatchOperand_Success ) return Res ; Operands . push_back ( AMDGPUOperand :: CreateImm ( Offset , S , ImmTy ) ) ; return MatchOperand_Success


<s> case <STR_LIT> : switch ( kind ) { case MCSymbolRefExpr :: VK_GOT : return <STR_LIT> ; case MCSymbolRefExpr :: VK_GOTREL : return <STR_LIT> ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT : return <STR_LIT> ; case MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT : return <STR_LIT> ; case MCSymbolRefExpr :: VK_<ISA_LIT>_IE : return <STR_LIT> ; case MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT : return <STR_LIT> ; case MCSymbolRefExpr :: VK_TPREL : return <STR_LIT> ; case MCSymbolRefExpr :: VK_DTPREL : return <STR_LIT> ; case MCSymbolRefExpr :: VK_None : return <STR_LIT> ; default : raise_relocation_error ( <NUM_LIT> , kind ) ; } default : if ( MCID . mayStore ( ) || MCID . mayLoad ( ) ) { for ( const MCPhysReg * ImpUses = MCID . getImplicitUses ( ) ; * ImpUses ; ++ ImpUses ) { if ( * ImpUses != <STR_LIT> ) continue ; switch ( <ISA_LIT>MCInstrInfo :: getAccessSize ( MCII , MI ) ) { case <STR_LIT> :: ByteAccess : return fixup_<ISA_LIT>_GPREL16_0 ; case <STR_LIT> :: HalfWordAccess : return fixup_<ISA_LIT>_GPREL16_1 ; case <STR_LIT> :: WordAccess : return fixup_<ISA_LIT>_GPREL16_2 ; case <STR_LIT> :: DoubleWordAccess : return fixup_<ISA_LIT>_GPREL16_3


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { for ( MCRegAliasIterator AI ( Reg , Subtarget -> getRegisterInfo ( ) , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return


<s> bool isTargetELF ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple ::

ELF || TargetTriple . isOSBinFormatELF ( ) ) ;


<s> unsigned A15SDOptimizer :: getDPRLaneFromSPR ( unsigned SReg ) { unsigned DReg = TRI -> getMatchingSuperReg ( SReg , <STR_LIT> , & <STR_LIT> ) ; if ( DReg != <STR_LIT> ) return <STR_LIT> ; return


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b )


<s> Cond = Cond -> getOperand ( <NUM_LIT> ) ; } isAnd = false ; SDValue SetCC0 , SetCC1 ; switch ( Cond -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : isAnd = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : SetCC0 = Cond -> getOperand ( <NUM_LIT> ) ; SetCC1 = Cond -> getOperand ( <NUM_LIT> ) ; break ; } ; if ( SetCC0 . getOpcode ( ) != <STR_LIT> || SetCC1 . getOpcode ( ) != <STR_LIT> || SetCC0 -> getOperand ( <NUM_LIT> ) != SetCC1 -> getOperand ( <NUM_LIT> ) ) return false ; CC0 = ( <STR_LIT> ) SetCC0 -> getConstantOperandVal ( <NUM_LIT> ) ; CC1 = ( <STR_LIT> ) SetCC1 -> getConstantOperandVal


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch (


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . addOperand ( Base ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; return


<s> rtx_insn * tmp ; enum attr_type type , type2 ; type = get_attr_type ( last_scheduled_insn ) ; if ( type == TYPE_DIV && divide_cnt == <NUM_LIT> ) { divide_cnt = <NUM_LIT> ; pos = lastpos ; while ( pos >= <NUM_LIT> ) { if ( recog_memoized ( ready [ pos ] ) >= <NUM_LIT> && get_attr_type ( ready [ pos ] ) == TYPE_DIV ) { tmp = ready [ pos ] ; for ( i = pos ; i < lastpos ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ lastpos ] = tmp ; break ; } pos -- ; } } else { divide_cnt = <NUM_LIT> ; if ( type == TYPE_VECLOAD ) { if ( vec_pairing == <NUM_LIT> ) { int vecload_pos = - <NUM_LIT> ; pos = lastpos ; while ( pos >= <NUM_LIT> ) { if ( recog_memoized ( ready [ pos ] ) >= <NUM_LIT> ) { type2 = get_attr_type ( ready [ pos ] ) ; if ( is_power9_pairable_vec_type ( type2 ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < lastpos ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ lastpos ] = tmp ; vec_pairing = <NUM_LIT> ; return cached_can_issue_more ; } else if ( type2 == TYPE_VECLOAD && vecload_pos == - <NUM_LIT> ) vecload_pos = pos ; } pos -- ; } if ( vecload_pos >= <NUM_LIT> ) { tmp = ready [ vecload_pos ] ; for ( i = vecload_pos ; i < lastpos ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ lastpos ] = tmp ; vec_pairing = <NUM_LIT> ; return cached_can_issue_more ; } } } else if ( is_power9_pairable_vec_type ( type ) ) { if ( vec_pairing == <NUM_LIT> ) { int vec_pos = - <NUM_LIT> ; pos = lastpos ; while ( pos >= <NUM_LIT>


<s> if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx (


<s> rtx rperm [ MAX_VECT_LEN ] , x ; rtx_insn * insn ; unsigned i ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; insn = emit_insn ( x


<s> ModulePass * llvm :: create<ISA_LIT>WriterPass ( raw_ostream & Str


<s> unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned oldval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned newval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * TRCsp ; TRCsp = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , ldrOpc , strOpc ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT>


<s> SDLoc DL ( N ) ; MVT Type = N -> getSimpleValueType ( <NUM_LIT> ) ; assert ( Type == <STR_LIT> && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned MachineOp = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Lhs = N -> getOperand ( <NUM_LIT> ) ; SDValue Rhs = N -> getOperand ( <NUM_LIT> ) ; SDNode * Mul = CurDAG -> getMachineNode ( MachineOp , DL , <STR_LIT> , Lhs , Rhs ) ; SDValue InChain = CurDAG ->


<s> { <STR_LIT> , cygwin_d_handle_target_object_format } , { NULL ,


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( )


<s> auto & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { if ( RC -> getID ( ) != <STR_LIT> ) return false ; const LLT Ty = MRI . getType ( Reg ) ; return Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID ( ) ==


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back (


<s> return ( reload_completed && cfun -> machine -> frame . total_size == <NUM_LIT> &&

! cfun -> machine -> interrupt_handler_p ) ;


<s> if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) . hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand (

<NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ;


<s> return ( poly8x8_t ) __builtin_neon_vbslv8qi ( ( int8x8_t ) __a ,


<s> SDLoc DL ( N ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue EFLAGS = N -> getOperand (


<s> off = INTVAL ( offset ) ; if ( GET_CODE ( base ) != REG || off < <NUM_LIT> ) continue ; if ( cfun_frame_layout . first_save_gpr != - <NUM_LIT> && ( cfun_frame_layout . first_save_gpr < first || cfun_frame_layout . last_save_gpr > last ) ) continue ; if ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO ( base ) != HARD_FRAME_POINTER_REGNUM ) continue ; if ( first > BASE_REGNUM || last < BASE_REGNUM ) continue ; if ( cfun_frame_layout . first_save_gpr != - <NUM_LIT> ) { rtx s_pat = save_gprs ( base , off + ( cfun_frame_layout . first_save_gpr - first ) * UNITS_PER_LONG , cfun_frame_layout . first_save_gpr , cfun_frame_layout . last_save_gpr ) ; new_insn = emit_insn_before ( s_pat , insn ) ; INSN_ADDRESSES_NEW ( new_insn , - <NUM_LIT> ) ; } remove_insn ( insn ) ; continue ; } if ( cfun_frame_layout . first_save_gpr == - <NUM_LIT> && GET_CODE ( pat ) == SET && GENERAL_REG_P ( SET_SRC ( pat ) ) && GET_CODE ( SET_DEST ( pat ) ) == MEM ) { set = pat ; first = REGNO ( SET_SRC ( set ) ) ; offset = const0_rtx ; base = eliminate_constant_term ( XEXP ( SET_DEST ( set ) , <NUM_LIT> ) , & offset ) ; off = INTVAL ( offset ) ; if ( GET_CODE ( base ) != REG || off < <NUM_LIT> ) continue ; if ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO ( base ) != HARD_FRAME_POINTER_REGNUM ) continue ; remove_insn ( insn ) ; continue ; } if ( GET_CODE ( pat ) == PARALLEL && load_multiple_operation ( pat , VOIDmode ) ) { set = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; first = REGNO ( SET_DEST ( set ) ) ; last = first + XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ; offset = const0_rtx ; base = eliminate_constant_term ( XEXP ( SET_SRC ( set ) , <NUM_LIT> ) , & offset ) ; off = INTVAL ( offset ) ; if ( GET_CODE ( base ) != REG || off < <NUM_LIT> ) continue ; if ( cfun_frame_layout . first_restore_gpr != - <NUM_LIT> && ( cfun_frame_layout . first_restore_gpr < first || cfun_frame_layout . last_restore_gpr > last ) ) continue ; if ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO ( base ) != HARD_FRAME_POINTER_REGNUM ) continue ; if ( first > BASE_REGNUM || last < BASE_REGNUM ) continue ; if ( cfun_frame_layout . first_restore_gpr


<s> case <NUM_LIT> : case 'c' : case 'C' : case <NUM_LIT> : case 'z' : case 'Z' : case <NUM_LIT> : case 's' : case 'S' : case <NUM_LIT> : case 'o' : case 'O' : case <NUM_LIT> : case 'i' : case


<s> return ( ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) || ( RegNo >= <STR_LIT> &&

RegNo <= <STR_LIT> ) || ( RegNo >= <STR_LIT> && RegNo <= <STR_LIT> ) ) ;


<s> DFAPacketizer * R600InstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const { const InstrItineraryData * II = STI


<s> if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>FunctionInfo * XFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool emitFrameMoves = <ISA_LIT>RegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; assert ( Reg != <STR_LIT> && ! ( Reg == <STR_LIT> && hasFP ( * MF ) ) && <STR_LIT> ) ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , I . getFrameIdx ( ) , RC , TRI ) ; if ( emitFrameMoves ) { auto Store = MI ; -- Store ; XFI -> getSpillLabels ( ) . push_back ( std :: make_pair


<s> static bool mips_refers_to_kernel_reg_p ( const_rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( REG_P ( * iter ) && KERNEL_REG_P ( REGNO ( * iter ) ) ) return true ; return


<s> if ( ! reload_in_progress && ! reload_completed && ! ia64_move_ok ( op0 , op1 ) ) op1 = force_reg ( mode , op1 ) ; if ( ( mode == Pmode || mode == ptr_mode ) && symbolic_operand ( op1 , VOIDmode ) ) { HOST_WIDE_INT addend = <NUM_LIT> ; enum tls_model tls_kind ; rtx sym = op1 ; if ( GET_CODE ( op1 ) == CONST && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { addend = INTVAL ( XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ) ; sym = XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ; } tls_kind = tls_symbolic_operand_type ( sym ) ; if ( tls_kind ) return ia64_expand_tls_address ( tls_kind , op0 , sym , op1 , addend ) ; if ( any_offset_symbol_operand ( sym , mode ) ) addend = <NUM_LIT> ; else if ( aligned_offset_symbol_operand ( sym , mode ) ) { HOST_WIDE_INT addend_lo , addend_hi


<s> unsigned Chan = MI -> getOperand ( OpNum ) . getImm ( ) ; O << '.' << <STR_LIT> [ Chan &


<s> if ( I == MBB . begin ( ) ) break ; -- I ; TargetInstrDesc desc = I -> getDesc ( ) ; if ( desc . hasDelaySlot ( ) || desc . isBranch ( ) || isDelayFiller ( MBB , I ) || desc . isCall ( ) || desc . isReturn ( ) || desc . isBarrier ( ) || desc . hasUnmodeledSideEffects ( ) ) break ; if ( hasImmInstruction ( I ) || delayHasHazard ( I , slot ) ) continue ; return I ; } return MBB . end


<s> if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = nullptr ; if ( FoldedLoad ) { EVT VT = * TRI . legalclasstypes_begin ( * RC ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( ) >= Alignment ; Load = DAG . getMachineNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , Subtarget ) , dl , VT , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Load ) ; cast < MachineSDNode > ( Load ) -> setMemRefs ( MMOs . first , MMOs . second ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ; VTs . push_back ( * TRI . legalclasstypes_begin ( * DstRC ) ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { EVT VT = N -> getValueType ( i ) ; if ( VT != <STR_LIT> && i >= ( unsigned ) MCID . getNumDefs (


<s> MachineBasicBlock :: reverse_iterator It = MBB -> rbegin ( ) ; if ( It != MBB -> rend ( ) ) { MachineInstr * MI = & ( * It ) ; if ( MI -> getOpcode ( ) == AMDGPU :: CONTINUE ) return MI ; } return nullptr


<s> int getSEHRegNum ( unsigned i ) const { return getEncodingValue (


<s> static __inline__ double __fnmadd ( double x , double y


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBaseOffsetValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & RegMO = MI . getOperand ( OpIdx ) ; const MCOperand & ImmMO = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Reg = getMachineOpValue ( MI , RegMO ,


<s> if ( pConfig . targets ( ) . triple ( ) . isOSDarwin ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; } if ( pConfig . targets ( ) . triple (


<s> return ( ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> &&


<s> assert ( m_pGOT != NULL && <STR_LIT> ) ; return * m_pGOT


<s> if ( ! InstrExec . count ( UseI ) ) continue ; if ( UseI -> isPHI ( ) ) visitPHI ( * UseI ) ; else if ( ! UseI -> isBranch ( ) ) visitNonBranch


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue ResNode = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode (


<s> int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ; if ( isa < UndefValue > ( COp ) ) { Indexes [ I ] = - <NUM_LIT> ; continue ; } APInt Index = cast < ConstantInt > ( COp ) -> getValue ( ) ; Index = Index . zextOrTrunc ( <NUM_LIT> ) . getLoBits ( <NUM_LIT> ) ; if ( IsPD ) Index . lshrInPlace ( <NUM_LIT> ) ; Index += APInt ( <NUM_LIT> , ( I / NumLaneElts ) * NumLaneElts ) ; Indexes [ I ] = Index . getZExtValue ( ) ; } auto V1 = II . getArgOperand (


<s> const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) ) return false ; unsigned GPRCnt = <NUM_LIT> ; unsigned FPRCnt = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftAsync ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : ++ GPRCnt


<s> std :: string FuncName = fInfo . mangle ( ) ; Function * F = dyn_cast_or_null < Function > ( M -> getValueSymbolTable ( ) . lookup ( FuncName ) ) ; if ( F && ! F -> isDeclaration ( ) && ! F -> isVarArg ( ) && F -> arg_size ( ) == fInfo . getNumArgs ( ) ) { return F


<s> const std :: string & getCPUString (


<s> return true ; } if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) { * base = XEXP ( addr ,


<s> void <ISA_LIT>ScheduleBlockCreator :: fillStats ( ) { unsigned DAGSize = CurrentBlocks . size ( ) ; for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { int BlockIndice = TopDownIndex2Block [ i ] ; <ISA_LIT>ScheduleBlock * Block = CurrentBlocks [ BlockIndice ] ; if ( Block -> getPreds ( ) . empty ( ) ) Block -> Depth = <NUM_LIT> ; else { unsigned Depth = <NUM_LIT> ; for ( <ISA_LIT>ScheduleBlock * Pred : Block -> getPreds ( ) ) { if ( Depth < Pred -> Depth + <NUM_LIT> ) Depth = Pred -> Depth + <NUM_LIT> ; } Block -> Depth = Depth ; } } for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { int BlockIndice = BottomUpIndex2Block [


<s> std :: unique_ptr < ScheduleDAGMutation > create<ISA_LIT>MacroFusionDAGMutation ( ) { return createBranchMacroFusionDAGMutation ( shouldScheduleAdjacent


<s> SmallVector < SDValue , <NUM_LIT> > Opnds ; Opnds . push_back ( Zero ) ; Opnds . push_back ( Addr . getOperand ( <NUM_LIT> ) ) ; unsigned SubOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { SubOp = <STR_LIT> ; Opnds . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) ) ; } MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Opnds ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ByteOffset , DL , <STR_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isDSOffsetLegal ( SDValue ( ) , CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } Base =


<s> if ( ! CNum ) return false ; return UnsafeDiv || CNum -> isExactlyValue ( +


<s> return ( __m512 ) __builtin_ia32_rndscaleps_mask ( ( __v16sf ) __C , __imm , (


<s> SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ]


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ; } return


<s> case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4


<s> Op . addRegOrImmWithFPInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isDPPCtrl ( ) ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDppRowMask , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDppBankMask , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands ,

OptionalIdx , <ISA_LIT>Operand :: ImmTyDppBoundCtrl ) ;


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - <NUM_LIT> : <NUM_LIT> ) ; splat_val = val ; msb_val = val >= <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= copies


<s> RegisterTarget < Triple :: lanai > X ( getThe<ISA_LIT>Target ( ) ,


<s> bool isCtlzFast ( ) const override { return


<s> return ImplicitItMode == ImplicitItModeTy :: Always

|| ImplicitItMode == ImplicitItModeTy :: ThumbOnly ;


<s> rtx result = <NUM_LIT> ; int i ; if ( ! can_create_pseudo_p ( ) && mode == SImode && REG_P ( target ) && REGNO ( target ) < FIRST_PSEUDO_REGISTER ) { result = alpha_emit_set_const_1 ( target , mode , c , <NUM_LIT> , no_output ) ; if ( result ) return result ; target = no_output ? NULL : gen_lowpart ( DImode , target ) ; mode = DImode ; } else if ( mode == V8QImode || mode == V4HImode || mode == V2SImode ) { target = no_output ? NULL : gen_lowpart ( DImode , target ) ; mode = DImode ; } for ( i = <NUM_LIT> ; i <= n ; i ++ ) { result = alpha_emit_set_const_1 ( target , mode , c , i , no_output ) ; if ( result ) { rtx_insn * insn ; rtx set ; if ( no_output ) return result ; insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , GEN_INT ( c ) ) ; break ; } } if ( result )


<s> printOperand ( MI , opNum , O ) ; O <<


<s> static __inline vec_int4 spu_xor ( vec_int4 a , signed int b ) { return ( ( vec_int4 ) ( si_xori ( ( qword ) ( a ) , (


<s> static SDValue combineMulToPMULDQ ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> || VT . getVectorNumElements ( ) < <NUM_LIT> || ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget . hasSSE41 ( ) && DAG . ComputeNumSignBits ( N0 ) > <NUM_LIT> && DAG . ComputeNumSignBits ( N1 ) > <NUM_LIT> ) { auto PMULDQBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { N0 , N1 } , PMULDQBuilder , false ) ; } APInt Mask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( N0 , Mask ) && DAG . MaskedValueIsZero ( N1 , Mask ) ) { auto PMULUDQBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { N0 , N1 } , PMULUDQBuilder , false ) ; } return SDValue (


<s> const char * getModifier ( ) const { return Modifier


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>LETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>BETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getTheThumbLETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getTheThumbBETarget (


<s> return MAX ( GET_MODE_ALIGNMENT ( mode )


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X


<s> return ( <NUM_LIT> << getLgkmcntBitWidth ( ) ) -


<s> return ( __m256i ) __builtin_ia32_cvttps2dq256 ( ( __v8sf )


<s> for ( unsigned i = <NUM_LIT> , e = Operands . size ( ) ; i != e ; ++ i ) { const AMDGPUOperand & Op = ( ( AMDGPUOperand & ) * Operands [ i ] ) ; if ( Op . isRegWithInputMods ( )


<s> SmallVector < std :: pair < MachineInstr * , MachineInstr * > , <NUM_LIT> > MIReplacements ; LiveRegs . clear ( ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = MBB . rbegin ( ) ; I != MBB . rend ( ) ; ++ I ) { MachineInstr * NewMI = nullptr ; MachineInstr * MI = & * I ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) { if ( ML -> begin ( ) == ML -> end ( ) &&

! OptForSize ) NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( bool

Is64Bit , uint8_t OSABI , bool HasRelocationAddend , uint8_t ABIVersion ) {


<s> __extension__ static __inline void vst2_u64 ( uint64_t * __a , uint64x1x2_t val ) { __builtin_aarch64_simd_oi __o ; uint64x2x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp .


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum , O ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ; return false


<s> unsigned getVGPRSetID ( ) const { return


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , X , Y ) ; case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getNOT ( dl , Y , VT ) ) ; } } if ( VT . is128BitVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetCCResultType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDLoc DL ( Op ) ; if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Add , <STR_LIT> ) ; return DAG . getSelect ( DL , VT , Cmp , DAG . getAllOnesConstant ( DL , VT ) , Add ) ; } if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Y , <STR_LIT> ) ; return DAG . getSelect ( DL , VT , Cmp , Sub , DAG . getConstant (


<s> auto * CompareVal = dyn_cast < ConstantSDNode > ( ICmp -> getOperand ( <NUM_LIT> ) ) ; if ( ! CompareVal ) return false ; auto * TrueVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! TrueVal ) return false ; auto * FalseVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! FalseVal ) return false ; if ( CompareVal -> getZExtValue ( ) == FalseVal -> getZExtValue ( ) ) Invert = ! Invert ; else if ( CompareVal -> getZExtValue ( ) != TrueVal -> getZExtValue ( ) ) return false ; auto * NewCCValid = dyn_cast < ConstantSDNode > ( Select -> getOperand


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo & tri ,

const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) :


<s> case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Call : return selectCall (


<s> if ( ! poly_int_rtx_p ( x , & offset ) ) return - <NUM_LIT> ; return aarch64_offset_temporaries ( true ,


<s> return MBB . isEHPad ( ) || MBB . hasAddressTaken ( ) || & MBB == & MBB . getParent


<s> int <ISA_LIT>AsmParser :: matchRegisterName ( StringRef Name ) { int CC = StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) .

Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> return ( TM . getRelocationModel ( ) != Reloc :: Static ? Reloc ::


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , false ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32 ( Op ,


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> ) )

. addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ;


<s> if ( ! Resolved && ! WasForced ) return true ; int64_t Offset = int64_t ( Value ) ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; case <STR_LIT> : return Offset > <NUM_LIT> || Offset


<s> case <STR_LIT> : case <STR_LIT> : if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; } return


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Equal ) ) return reportParseError ( <STR_LIT> ) ; Parser . Lex ( ) ; StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; if ( Arch . empty ( ) ) return reportParseError ( <STR_LIT> ) ; StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ArchFeatureName . empty ( ) ) return reportParseError ( <STR_LIT> ) ; if ( ArchFeatureName == <STR_LIT> && inMicro<ISA_LIT>Mode ( ) ) return reportParseError ( <STR_LIT> ) ; selectArch ( ArchFeatureName ) ; getTargetStreamer ( ) . emitDirectiveSetArch


<s> if ( isUnknown ( ) || hasSEWLMULRatioOnly ( ) ) return false ; if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( TailAgnostic != InstrInfo . TailAgnostic || MaskAgnostic != InstrInfo . MaskAgnostic ) return false ; return getSEWLMULRatio ( ) == getSEWLMULRatio ( EEW , InstrInfo


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV


<s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MCInstrDesc & MovRelDesc = get ( <STR_LIT> ) ; Register VecReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsUndef = MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ; unsigned SubReg = <STR_LIT> + MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( VecReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * MovRel = BuildMI ( MBB , MI , DL , MovRelDesc ) . addReg ( RI . getSubReg ( VecReg , SubReg ) , RegState :: Undef ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( VecReg , RegState :: ImplicitDefine ) . addReg ( VecReg , RegState :: Implicit | ( IsUndef ? RegState :: Undef : <NUM_LIT> ) ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MovRel -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RegLo = RI . getSubReg ( Reg , <STR_LIT> ) ; Register RegHi = RI . getSubReg ( Reg , <STR_LIT> ) ; MIBundleBuilder Bundler ( MBB , MI ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , Reg ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegLo ) . addReg ( RegLo ) . add ( MI . getOperand ( <NUM_LIT> ) ) ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) , RegHi ) . addReg ( RegHi ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; Bundler . append ( MIB ) ; finalizeBundle ( MBB , Bundler . begin ( ) ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MI . setDesc ( get ( ST . isWave32 ( ) ?


<s> if ( ! Type ) return error ( <STR_LIT> , TypeTok ) ; auto WasmSym = cast < MCSymbolWasm > ( TOut . getStreamer ( ) . getContext ( ) . getOrCreateSymbol ( SymName ) ) ; WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setGlobalType ( <STR_LIT> { uint8_t ( Type . getValue ( ) ) , true } ) ; TOut . emitGlobalType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( TOut . getStreamer ( ) . getContext ( ) . getOrCreateSymbol ( SymName ) ) ; if ( CurrentState == Label && WasmSym == LastLabel ) { CurrentState = FunctionStart ; } auto Signature = make_unique < <STR_LIT> > ( ) ; if ( parseSignature ( Signature . get ( ) ) ) return true ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; TOut . emitFunctionType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( TOut . getStreamer ( ) . getContext ( ) . getOrCreateSymbol ( SymName ) ) ; auto Signature = make_unique < <STR_LIT> > ( ) ; if ( parseRegTypeList ( Signature -> Params ) ) return true ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; TOut . emitEventType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { if ( CurrentState != FunctionStart ) return error ( <STR_LIT> , Lexer . getTok ( ) ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Locals ; if ( parseRegTypeList ( Locals ) ) return true ; TOut . emitLocal (


<s> return ( __m64 ) __builtin_arm_wslldi (


<s> } else { MinValue = APInt :: getZero ( SrcScalarSizeInBits ) ; MaxValue = APInt :: getLowBitsSet ( SrcScalarSizeInBits , DstScalarSizeInBits ) ; } auto * MinC = Constant :: getIntegerValue ( ArgTy , MinValue ) ; auto * MaxC = Constant :: getIntegerValue ( ArgTy , MaxValue ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg0 , MinC ) , MinC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg1 , MinC ) , MinC , Arg1 ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg0 , MaxC ) , MaxC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg1 , MaxC ) , MaxC , Arg1 ) ; SmallVector < int , <NUM_LIT> > PackMask ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( unsigned Elt = <NUM_LIT> ; Elt != NumSrcEltsPerLane ; ++ Elt ) PackMask . push_back ( Elt + ( Lane * NumSrcEltsPerLane ) ) ; for ( unsigned Elt = <NUM_LIT> ; Elt != NumSrcEltsPerLane ; ++ Elt ) PackMask . push_back ( Elt + ( Lane * NumSrcEltsPerLane ) + NumSrcElts ) ; } auto * Shuffle = Builder . CreateShuffleVector (


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) { addExpr ( Inst ,


<s> if ( isThumb2 ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT>


<s> if ( SYMBOL_REF_P ( x ) && ! TARGET_MACHO ) { enum tls_model model = SYMBOL_REF_TLS_MODEL ( x ) ; if ( model != <NUM_LIT> ) return rs6000_legitimize_tls_address ( x , model ) ; } extra = <NUM_LIT> ; switch ( mode ) { case E_TFmode : case E_TDmode : case E_TImode : case E_PTImode : case E_IFmode : case E_KFmode : extra = <NUM_LIT> ; break ; default : break ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( ( unsigned HOST_WIDE_INT ) ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + <NUM_LIT> ) >= <NUM_LIT> - extra ) ) { HOST_WIDE_INT high_int , low_int ; rtx sum ; low_int = sext_hwi ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( low_int >= <NUM_LIT> - extra ) low_int = <NUM_LIT> ; high_int = INTVAL ( XEXP ( x , <NUM_LIT> ) ) - low_int ; sum = force_operand ( gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , gen_int_mode ( high_int , Pmode ) ) , <NUM_LIT> ) ; return plus_constant ( Pmode , sum , low_int ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) && ! avoiding_indexed_address_p ( mode ) ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( ( TARGET_ELF || ! MACHO_DYNAMIC_NO_PIC_P ) && TARGET_32BIT && TARGET_NO_TOC_OR_PCREL && ! flag_pic && ! CONST_INT_P ( x ) && ! CONST_WIDE_INT_P ( x ) && ! CONST_DOUBLE_P ( x ) && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( TARGET_HARD_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) ) { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_ELF ) emit_insn ( gen_elf_high ( reg , x


<s> case POST_MODIFY : switch ( GET_CODE ( XEXP ( XEXP ( code , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case REG : case SUBREG : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; break ; case CONST_INT : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; break ; default : abort ( ) ; } break ; case PLUS : switch ( GET_CODE ( XEXP ( code , <NUM_LIT> ) ) ) { case REG : case SUBREG : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; break ; case CONST_INT


<s> case AsmToken :: String : break ; } const MCExpr * IdVal ; SMLoc S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return MatchOperand_Success


<s> PreservedAnalyses <ISA_LIT>AlwaysInlinePass :: run ( Module & M , ModuleAnalysisManager & AM ) { alwaysInlineImpl ( M , GlobalOpt ) ; return PreservedAnalyses ::


<s> MachineInstr * PHIInput = MRI -> getVRegDef ( RegOp ) ; unsigned Opcode = PHIInput -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; if ( Opcode == <STR_LIT> ) { assert ( MRI -> getRegClass ( PHIInput -> getOperand ( <NUM_LIT> ) . getReg ( ) ) == & <STR_LIT> && <STR_LIT> ) ; PHIOps . push_back ( { PHIInput -> getOperand ( <NUM_LIT> ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { Register AccReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * PHIInput -> getParent ( ) , PHIInput , PHIInput -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , AccReg ) ; PHIOps . push_back ( { MachineOperand :: CreateReg ( AccReg , false ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { assert ( ChangedPHIMap . count ( PHIInput ) == <NUM_LIT> && <STR_LIT>


<s> Offset *= - <NUM_LIT> ; case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == BaseReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= - <NUM_LIT> ) { if ( ! Offset || Offset == MI -> getOperand ( <NUM_LIT> ) . getImm (


<s> AU . addRequired < <ISA_LIT>SinglePathInfo > ( ) ; AU . addRequired < MachinePostDominatorTree > (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , bool little , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>Default ) , IsLittle ( little ) , IsSoftFloat ( false ) , IsSingleFloat ( false ) , IsFPXX ( false ) , NoABICalls ( false ) , IsFP64bit ( false ) , UseOddSPReg ( true ) , IsNaN2008bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , HasCn<ISA_LIT> ( false ) , Has<ISA_LIT>3_32 ( false ) , Has<ISA_LIT>3_32r2 ( false ) , Has<ISA_LIT>4_32 ( false ) , Has<ISA_LIT>4_32r2 ( false ) , Has<ISA_LIT>5_32r2 ( false ) , In<ISA_LIT>16Mode ( false ) , In<ISA_LIT>16HardFloat ( <ISA_LIT>16HardFloat ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , HasDSPR3 ( false ) , AllowMixed16_32 ( Mixed16_32 | <ISA_LIT>_Os16 ) , Os16 ( <ISA_LIT>_Os16 ) , HasMSA ( false ) , UseTCCInDIV ( false ) , HasEVA ( false ) , TM ( TM ) , TargetTriple ( TT ) , TSInfo ( ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( initializeSubtargetDependencies ( CPU , FS , TM ) ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( TM , * this ) ) { PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>Default ) <ISA_LIT>ArchVersion = <ISA_LIT>32 ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error (


<s> int symbolic_operand ( register rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( op ) ) { case SYMBOL_REF : case LABEL_REF : return <NUM_LIT>


<s> ParseSubtargetFeatures ( CPUName , FullFS ) ; InitCPUSchedModel ( CPUName ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment


<s> const char * getPassName ( ) const override { return


<s> void setDefaultLatency ( uint32_t val


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addDefaultPred ( BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( dstReg , RegState :: Define ) . addReg ( srcReg ) ) ; return


<s> static MachineOperand & getBaseOperand ( MachineInstr * MI


<s> if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false


<s> DataSection = MCSection<ISA_LIT> :: Create ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSection<ISA_LIT> :: SHF_DP_SECTION , SectionKind :: getDataRel ( ) , false , getContext ( ) ) ; BSSSection = MCSection<ISA_LIT> :: Create ( <STR_LIT> , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_WRITE | MCSection<ISA_LIT> :: SHF_DP_SECTION , SectionKind :: getBSS ( ) , false , getContext ( ) ) ; MergeableConst4Section = MCSection<ISA_LIT> :: Create ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSection<ISA_LIT> :: SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) , false , getContext ( ) ) ; MergeableConst8Section = MCSection<ISA_LIT> :: Create ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSection<ISA_LIT> :: SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) , false , getContext ( ) ) ; MergeableConst16Section = MCSection<ISA_LIT> :: Create ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSectionELF :: SHF_MERGE | MCSection<ISA_LIT> :: SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) , false , getContext ( ) ) ; TLSDataSection = DataSection ; TLSBSSSection = BSSSection ; ReadOnlySection = MCSection<ISA_LIT> :: Create ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_ALLOC | MCSection<ISA_LIT> :: SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) , false , getContext ( ) ) ; DataRelSection = DataRelLocalSection


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) , false ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false ) ; } return false


<s> if ( ! Worthy ) continue ; Value * TDCFunc = <STR_LIT> ( & M , <STR_LIT> , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I ->

user_empty ( ) ) I -> eraseFromParent ( ) ;


<s> unsigned Ws = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Lane == <NUM_LIT> ) { unsigned Wt = Ws ; if ( ! Subtarget . useOddSPReg ( ) ) { Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } else { unsigned Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( Lane ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } MI -> eraseFromParent (


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum


<s> } } if ( ! returnEmitted ) { errs ( ) << <STR_LIT> << MF . getName ( ) . str ( ) << <STR_LIT> ; if ( noSuccessorFound ) { MachineBasicBlock :: iterator lastMI = noSuccessorBlock -> begin ( ) ; BuildMI ( * noSuccessorBlock , noSuccessorBlock -> end ( ) , ( * lastMI ) . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; } else { errs ( ) <<


<s> if ( AddOpIdx != <NUM_LIT> ) { AdjustOperandOrder ( MINewB , RegX , KillX , RegM21 , KillM21 , RegM22 , KillM22 ) ; AdjustOperandOrder ( MINewA , RegY , KillY , RegM31 , KillM31 , RegM32 , KillM32 ) ; } MachineInstrBuilder MINewC = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFAddInst ] ) , RegC ) . addReg ( NewVRB , getKillRegState ( true ) ) . addReg ( NewVRA , getKillRegState ( true ) ) ; setSpecialOperandAttr ( * MINewA , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewB , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewC , IntersectedFlags ) ; InsInstrs . push_back ( MINewA ) ; InsInstrs . push_back ( MINewB ) ; InsInstrs . push_back ( MINewC ) ; } else if ( Pattern == MachineCombinerPattern :: REASSOC_XMM_AMM_BMM ) { assert ( NewVRD && <STR_LIT> ) ; MachineInstrBuilder MINewA = BuildMI ( * MF , Leaf -> getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFMULInst ] ) , NewVRA ) . addReg ( RegM11 , getKillRegState ( KillM11 ) ) . addReg ( RegM12 , getKillRegState ( KillM12 ) ) ; MachineInstrBuilder MINewB = BuildMI ( * MF , Prev -> getDebugLoc ( ) , get ( FmaOp ) , NewVRB ) . addReg ( RegX , getKillRegState ( KillX ) ) . addReg ( RegM21 , getKillRegState ( KillM21 ) ) . addReg ( RegM22 , getKillRegState ( KillM22 ) ) ; MachineInstrBuilder MINewD = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FmaOp ) , NewVRD ) . addReg ( NewVRA , getKillRegState ( true ) ) . addReg ( RegM31 , getKillRegState ( KillM31 ) ) . addReg ( RegM32 , getKillRegState ( KillM32 ) ) ; if ( AddOpIdx != <NUM_LIT> ) { AdjustOperandOrder ( MINewB , RegX , KillX , RegM21 , KillM21 , RegM22 , KillM22 ) ; AdjustOperandOrder ( MINewD , NewVRA , true , RegM31 , KillM31 , RegM32 , KillM32 ) ; } MachineInstrBuilder MINewC = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFAddInst ] ) , RegC ) . addReg ( NewVRB , getKillRegState ( true ) ) . addReg ( NewVRD , getKillRegState ( true ) ) ; setSpecialOperandAttr ( * MINewA , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewB , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewD , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewC , IntersectedFlags ) ; InsInstrs . push_back ( MINewA ) ; InsInstrs . push_back ( MINewB ) ; InsInstrs . push_back ( MINewD ) ; InsInstrs . push_back ( MINewC ) ; } assert ( ! InsInstrs . empty ( ) && <STR_LIT> ) ; DelInstrs . push_back ( Leaf ) ; DelInstrs . push_back


<s> static Type * getCmpOpsType ( const Instruction * I , unsigned VF = <NUM_LIT> ) { Type * OpTy = nullptr ; if ( CmpInst * CI = dyn_cast < CmpInst > ( I -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ; else if ( Instruction * LogicI = dyn_cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( CmpInst * CI0 = dyn_cast < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) if ( isa < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI0 -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy != nullptr ) { if ( VF == <NUM_LIT> ) { assert ( ! OpTy -> isVectorTy ( ) &&


<s> AMDGPUAsmParser ( MCSubtargetInfo & STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( STI ) , MII ( MII ) , Parser ( _Parser ) , ForcedEncodingSize ( <NUM_LIT> ) { if ( ! STI . getFeatureBits ( ) ) { STI . ToggleFeature ( <STR_LIT>


<s> bool <ISA_LIT>LoadStoreOpt :: MergeBaseUpdateLoadStore ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const TargetInstrInfo * TII , bool & Advance , MachineBasicBlock :: iterator & I ) { MachineInstr * MI = MBBI ; unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned Bytes = getLSMultipleTransferSize ( MI ) ; int Opcode = MI -> getOpcode ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isAM5 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool isAM2 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( isAM2 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; if ( isAM5 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; if ( isT2i32Load ( Opcode ) || isT2i32Store ( Opcode ) ) if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; bool isLd = isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( isLd && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base ) return false ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; bool DoMerge = false ; <STR_LIT> AddSub = <STR_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned Limit = isAM5 ? <NUM_LIT> : ( isAM2 ? <NUM_LIT> : <NUM_LIT> ) ; if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( isMatchingDecrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( ! isAM5 && isMatchingIncrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode ) ; MBB . erase ( PrevMBBI ) ; } } if ( ! DoMerge && MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( ! isAM5 && isMatchingDecrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; } else if ( isMatchingIncrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { NewOpc = getPostIndexedLoadStoreOpcode (


<s> sp_copy_regno = HARD_FRAME_POINTER_REGNUM ; } else if ( ! tilegx_current_function_is_leaf ( ) ) { sp_copy_regno = next_scratch_regno -- ; emit_move_insn ( gen_rtx_REG ( Pmode , sp_copy_regno ) , stack_pointer_rtx ) ; } if ( tilegx_current_function_is_leaf ( ) ) { emit_sp_adjust ( - total_size , & next_scratch_regno , ! frame_pointer_needed , NULL_RTX ) ; } else { rtx chain_addr = gen_rtx_REG ( Pmode , next_scratch_regno -- ) ; rtx size_rtx = GEN_INT ( - ( total_size - UNITS_PER_WORD ) ) ; if ( add_operand ( size_rtx , Pmode ) ) { rtx p = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , size_rtx ) ; emit_insn ( gen_rtx_SET ( chain_addr , p ) ) ; emit_sp_adjust ( - total_size , & next_scratch_regno , ! frame_pointer_needed , NULL_RTX ) ; } else { rtx p ; emit_sp_adjust ( - total_size , & next_scratch_regno , ! frame_pointer_needed , NULL_RTX ) ; p = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( UNITS_PER_WORD ) ) ; emit_insn ( gen_rtx_SET ( chain_addr , p ) ) ; } emit_insn ( gen_movdi ( gen_frame_mem ( DImode , chain_addr ) , gen_rtx_REG ( DImode , sp_copy_regno ) ) ) ; } start_offset = - crtl -> args . pretend_args_size - UNITS_PER_WORD ; offset = start_offset ; which_scratch = <NUM_LIT> ; for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( need_to_save_reg ( regno ) ) { rtx r = reg_save_addr [ which_scratch ] ; int from_regno ; int cfa_offset = frame_pointer_needed ? offset : total_size + offset ; if ( r == NULL_RTX ) { int prev_scratch_regno = next_scratch_regno ; r = compute_frame_addr ( offset , & next_scratch_regno ) ; if ( prev_scratch_regno != next_scratch_regno ) reg_save_addr [ which_scratch ] = r ; } else { int stride = ROUND_ROBIN_SIZE * - UNITS_PER_WORD ; rtx p = gen_rtx_PLUS ( Pmode , r , GEN_INT ( stride ) ) ; emit_insn ( gen_rtx_SET ( r , p ) ) ; } from_regno = ( fp_copy_regno >= <NUM_LIT> && regno == HARD_FRAME_POINTER_REGNUM ) ? fp_copy_regno : regno ; FRP ( frame_emit_store ( from_regno , regno , r , cfa , cfa_offset ) ) ; offset -= UNITS_PER_WORD ; which_scratch = ( which_scratch + <NUM_LIT> ) % ROUND_ROBIN_SIZE ; } if ( crtl -> profile ) emit_insn ( gen_blockage ( ) ) ; if ( flag_pic && crtl -> uses_pic_offset_table


<s> static inline bool is_fast_interrupt_func ( const_tree decl ) { return has_func_attr ( decl ,


<s> Streamer . emitIntValue ( uint8_t ( Type )


<s> SDNode * N = Use -> getOperand ( i ) . getNode ( ) ; if ( N == Def ) { if ( Use == ImmedUse || Use == Root ) continue ; assert ( N != Root ) ; return true ; } if ( findNonImmUse ( N , Def , ImmedUse , Root , Visited )


<s> NewF -> setLinkage ( GlobalValue :: InternalLinkage ) ; if ( F . hasName ( ) && F . hasLocalLinkage ( ) ) { std :: string NewName = std :: string ( NewF -> getName ( ) ) ; NewF -> takeName ( &


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM


<s> if ( I -> isDebugValue ( ) ) continue ; if ( isUnsafeToMoveAcross ( & * I , I2UseReg , I2DestReg , TRI ) ) { isSafe = false ; break ; } if ( ! KillingInstr && KilledOperand && I -> readsRegister ( KilledOperand , TRI ) ) KillingInstr = & * I ; } if ( isSafe ) { if ( KillingInstr ) { bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( I -> isDebugValue ( ) ) { if ( I -> readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( I ) ; continue ; } if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) &&

I -> killsRegister ( I1UseReg , TRI ) ) ) return false ;


<s> DebugLoc DL = II -> getDebugLoc ( ) ; const TargetRegisterClass * PtrRC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register Reg = RegInfo . createVirtualRegister ( PtrRC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAddiuOp ( ) ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm = <NUM_LIT> ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned Reg = TII . loadImmediate ( Offset , MBB , II , DL , OffsetBitSize == <NUM_LIT> ? & NewImm : nullptr ) ; BuildMI ( MBB , II , DL , TII . get ( ABI . GetPtrAdduOp ( ) ) , Reg ) . addReg

( FrameReg ) . addReg ( Reg , RegState :: Kill ) ;


<s> case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return MIDefinesZeroReg ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( STI -> isTargetDarwin ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> unsigned Alignment = IntrAlign -> getLimitedValue ( ) < MemAlign ? MemAlign : IntrAlign -> getLimitedValue ( ) ; if ( ! isPowerOf2_32 ( Alignment ) ) return nullptr ; auto * BCastInst = Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , PointerType :: get ( II . getType ( ) , <NUM_LIT> ) ) ; return Builder . CreateAlignedLoad ( II . getType ( ) , BCastInst ,


<s> UseMI = elideCopies ( UseMI , MRI ) ; if ( UseMI && UseMI -> isImplicitDef ( ) ) TailAgnostic = true ; } } if ( <STR_LIT> ( TSFlags ) ) { const MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; if ( VLOp . isImm ( ) ) InstrInfo . setAVLImm ( VLOp . getImm ( ) ) ; else InstrInfo . setAVLReg ( VLOp . getReg ( ) ) ; } else InstrInfo . setAVLReg ( <STR_LIT> ) ; InstrInfo . setVTYPE ( VLMul , SEW , TailAgnostic , false ) ; return InstrInfo


<s> case <STR_LIT> : return getBoolRC ( ) ; case <STR_LIT> : return isWave32 ? & <STR_LIT> : & <STR_LIT> ; case - <NUM_LIT>


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseRegWithFPInputMods ( OperandVector & Operands ) { return parseRegOrImmWithFPInputMods ( Operands


<s> return ( __m128i ) __builtin_ia32_broadcasti32x2_128_mask ( ( __v4si ) __A , ( __v4si )

_mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE


<s> __r = ( __vector unsigned short ) vec_splats ( __m ) ; __c = ( __vector unsigned short ) vec_splats ( ( unsigned short ) __count ) ; __r = vec_sr ( __r , ( __vector unsigned short ) __c ) ; return ( __m64 ) ( ( __vector long long


<s> } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> || SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return


<s> case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_MUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_SREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UDIV , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_UREM , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FADD , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSUB , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FMUL , MIRBuilder , ST ) ; case <STR_LIT> : case <STR_LIT> : return MSA3OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FDIV , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return SelectMSA3OpIntrinsic ( MI , <STR_LIT> , MIRBuilder , ST ) ; case <STR_LIT> : return MSA2OpIntrinsicToGeneric ( MI , TargetOpcode :: G_FSQRT , MIRBuilder ,


<s> unsigned NumRegs = ( MI . getNumOperands ( ) - Op ) & <NUM_LIT> ; Binary |= ( RegNo & <NUM_LIT> ) << <NUM_LIT> ; if ( SPRRegs ) Binary |= NumRegs ; else Binary |= NumRegs * <NUM_LIT> ; } else { for ( unsigned I = Op , E = MI . getNumOperands ( ) ; I < E ; ++ I ) { unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( MI . getOperand ( I ) . getReg ( ) ) ; Binary |= <NUM_LIT> <<


<s> mt_compute_frame_size ( get_frame_size ( ) ) ; if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return <NUM_LIT> ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return


<s> if ( ABI == <STR_LIT> && ( Type == <STR_LIT> )


<s> const MachineBasicBlock * MBB = MBBI -> getParent ( ) ; while ( MBBI == MBB -> begin ( ) ) { if ( MBB == & MBB -> getParent ( ) ->

front ( ) ) return MachineBasicBlock :: const_iterator ( ) ;


<s> return getTM < <ISA_LIT>TargetMachine > (


<s> SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UaddLV ) ; return UaddLV ; } else if ( VT == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UaddLV ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; EVT VT8Bit = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; Val = DAG . getBitcast ( VT8Bit , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , VT8Bit , Val ) ; unsigned EltSize = <NUM_LIT> ; unsigned NumElts = VT . is64BitVector ( ) ? <NUM_LIT> : <NUM_LIT> ; while ( EltSize != VT . getScalarSizeInBits ( ) ) { EltSize *= <NUM_LIT> ; NumElts /= <NUM_LIT> ; MVT WidenVT = <STR_LIT> ( <STR_LIT> ( EltSize ) , NumElts ) ; Val = DAG . getNode ( <STR_LIT> , DL , WidenVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Val ) ; } return Val


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFOffset ( SDValue Addr , SDValue & SRsrc , SDValue & Soffset , SDValue & Offset , SDValue & SLC ) const { SDValue GLC , TFE ; return SelectMUBUFOffset ( Addr , SRsrc , Soffset , Offset , GLC , SLC


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rdf ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregoidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t )


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size ,


<s> SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode (


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value


<s> static DecodeStatus DecodeT2AddrModeImm8s4 ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT>


<s> unsigned getVmcntBitWidthLo ( unsigned VersionMajor ) { return VersionMajor >= <NUM_LIT> ?


<s> void <ISA_LIT>WholeQuadMode :: toExact ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Before , unsigned SaveWQM , unsigned LiveMaskReg ) { MachineInstr * MI ; if ( SaveWQM ) { MI = BuildMI ( MBB , Before , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , SaveWQM ) . addReg


<s> unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( <STR_LIT> -> contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( TFI -> hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> adjustsStack ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) )


<s> MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer ,


<s> static SDValue replaceSplatVectorStore ( SelectionDAG & DAG , StoreSDNode * St ) { SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( VT . isFloatingPoint ( ) ) return SDValue ( ) ; if ( StVal . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumVecElts = VT . getVectorNumElements ( ) ; if ( NumVecElts != <NUM_LIT> && NumVecElts != <NUM_LIT> ) return SDValue ( ) ; SDValue SplatVal = StVal . getOperand ( <NUM_LIT> ) ; unsigned RemainInsertElts = NumVecElts - <NUM_LIT> ; while ( -- RemainInsertElts ) { SDValue NextInsertElt = StVal . getOperand ( <NUM_LIT> ) ; if ( NextInsertElt . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( NextInsertElt . getOperand ( <NUM_LIT> ) != SplatVal ) return SDValue ( ) ; StVal = NextInsertElt ; } unsigned OrigAlignment = St -> getAlignment ( ) ; unsigned EltOffset = NumVecElts == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Alignment = std :: min ( OrigAlignment , EltOffset ) ; SDLoc DL ( St


<s> assert ( isFIBase ( ) && <STR_LIT> ) ; Base . FI


<s> void <ISA_LIT>BitSimplify :: getInstrDefs ( const MachineInstr & MI , RegisterSet & Defs ) { for ( auto & Op : MI . operands


<s> bool <ISA_LIT>MCInst :: isOperandExtended ( const unsigned short OperandNum ) const { const uint64_t F = MCID


<s> if ( ! ScopeTops [ EndNo ] || ScopeTops [ EndNo ] -> getNumber ( ) > Begin -> getNumber ( ) ) ScopeTops [


<s> static rtx xtensa_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; switch ( fcode ) { case


<s> case <STR_LIT> : return expandLoadAddressImm ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandLoadAddressReg ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : return expandUncondBranchMMPseudo ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandLoadStoreMultiple ( Inst , IDLoc , Instructions ) ; case <STR_LIT> : case <STR_LIT> : return expandJalWithRegs ( Inst , IDLoc


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; return


<s> return __builtin_mve_vsubq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a


<s> bool <ISA_LIT>TargetLowering :: enableAggressiveFMAFusion ( EVT VT


<s> void setSRetReturnReg ( unsigned Reg


<s> if ( Subtarget . has<ISA_LIT>3 ( ) && Subtarget


<s> if ( mips_dangerous_for_la25_p ( x ) ) return reg_class_subset_p ( rclass , LEA_REGS ) ? NO_REGS : LEA_REGS ; regno = true_regnum ( x ) ; if ( TARGET_MIPS16 ) { if ( ! reg_class_subset_p ( rclass , M16_REGS ) && ! M16_REG_P ( regno ) ) return M16_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , ACC_REGS ) ) return GP_REG_P ( regno ) ? NO_REGS : GR_REGS ; if ( ACC_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < <NUM_LIT> || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x ) )


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian )

: LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) {


<s> SDValue Chain = OrigChain . getOperand ( <NUM_LIT> ) ; if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } Ops . append ( OrigChain -> op_begin ( ) + <NUM_LIT> , OrigChain -> op_end ( ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , Ops ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load


<s> bool <ISA_LIT>PacketizerList :: ignorePseudoInstruction ( const MachineInstr & MI , const MachineBasicBlock * ) { if ( MI . isDebugInstr ( ) ) return true ; if ( MI . isCFIInstruction ( ) ) return false ; if ( MI . isInlineAsm ( ) ) return false ; if ( MI . isImplicitDef ( ) ) return false ; const MCInstrDesc & TID = MI . getDesc ( ) ; auto * IS = ResourceTracker -> getInstrItins ( ) -> beginStage ( TID . getSchedClass ( ) ) ; return ! IS -> getUnits ( )


<s> if ( NewByte < <NUM_LIT> ) { addUndef ( ) ; return true ; } Op = Op . getOperand ( unsigned ( NewByte ) / <STR_LIT> ) ; Byte = unsigned ( NewByte ) % <STR_LIT> ; } else if ( Op . isUndef ( ) ) { addUndef ( ) ; return true ; } else break ; } unsigned OpNo = <NUM_LIT> ; for ( ; OpNo < Ops . size ( ) ; ++ OpNo ) if ( Ops [ OpNo ] == Op ) break ; if ( OpNo == Ops . size ( ) ) Ops . push_back ( Op ) ; unsigned Base = OpNo * <STR_LIT> + Byte ; for ( unsigned I = <NUM_LIT> ; I < BytesPerElement ; ++ I ) Bytes .


<s> } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set (


<s> if ( start == nbits ) return start ; gcc_assert ( start < nbits ) ; for ( unsigned int i = start ; i < nbits ; i ++ ) if ( bitmap_bit_p ( bmp , i ) ) return i ; return nbits


<s> Op -> Mem . Base = Base . release ( ) ; Op -> Mem . Off = Off ; Op -> StartLoc =


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol (


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode


<s> } else if ( Advance ) { ++ Position ; ++ MBBI ; if ( MBBI == E ) TryMerge = true ; } else { TryMerge = true ; } if ( TryMerge ) { if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( isThumb1 ? & <STR_LIT> : & <STR_LIT> ) ; RS -> forward ( std :: prev ( MBBI ) ) ; Merges . clear ( ) ; MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps , Merges ) ; for ( unsigned i = <NUM_LIT> , e = Merges . size ( ) ; i < e ; ++ i ) if ( MergeBaseUpdateLSMultiple ( MBB , Merges [ i ] , Advance , MBBI ) ) ++ NumMerges ; NumMerges += Merges . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) ++ NumMerges ; RS -> skipTo ( std :: prev ( MBBI ) ) ; } else if ( NumMemOps == <NUM_LIT> ) { if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ <NUM_LIT> ] . MBBI , TII , Advance , MBBI ) ) { ++ NumMerges ; RS -> forward ( std :: prev ( MBBI ) ) ; } } CurrBase = <NUM_LIT> ; CurrOpc = - <NUM_LIT> ; CurrSize = <NUM_LIT> ; CurrPred = <STR_LIT> ; CurrPredReg = <NUM_LIT> ; if ( NumMemOps ) { MemOps . clear ( ) ; NumMemOps =


<s> HARD_REG_SET mof_set ; tree clobbers ; tree t ; CLEAR_HARD_REG_SET ( mof_set ) ; SET_HARD_REG_BIT ( mof_set , CRIS_MOF_REGNUM ) ; clobbers = tree_cons ( NULL_TREE , build_string ( strlen ( reg_names [ CRIS_CC0_REGNUM ] ) , reg_names [ CRIS_CC0_REGNUM ] ) , in_clobbers ) ; for ( t = outputs ; t != NULL ; t = TREE_CHAIN ( t ) ) { tree val = TREE_VALUE ( t ) ; if ( strchr ( TREE_STRING_POINTER ( TREE_VALUE ( TREE_PURPOSE ( t ) ) ) , 'h' ) != NULL || tree_overlaps_hard_reg_set ( val , & mof_set ) != NULL_TREE ) return clobbers ; } for ( t = inputs ; t != NULL ; t = TREE_CHAIN ( t ) ) { tree val = TREE_VALUE (


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new


<s> return ( __m512i ) __builtin_ia32_pbroadcastd512_gpr_mask ( __A ,


<s> default : break ; } } Register XRegFromAlias = StringSwitch < Register > ( Constraint . lower ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( XRegFromAlias != <STR_LIT> ) return std

:: make_pair ( XRegFromAlias , & <STR_LIT> ) ;