<s> op_true = force_reg ( mode , op_true ) ; if ( ! nonimmediate_operand ( op_false , mode ) ) op_false = force_reg ( mode , op_false ) ; emit_insn ( gen_rtx_SET ( mode , dest , gen_rtx_IF_THEN_ELSE ( mode , cmp , op_true , op_false ) ) ) ; } else { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) = NULL ; rtx d = dest ; if ( ! nonimmediate_operand ( op_true , mode ) ) op_true = force_reg ( mode , op_true ) ; op_false = force_reg ( mode , op_false ) ; switch ( mode ) { case V4SFmode : if ( TARGET_SSE4_1 ) gen = gen_sse4_1_blendvps ; break ; case V2DFmode : if ( TARGET_SSE4_1 ) gen = gen_sse4_1_blendvpd ; break ; case V16QImode : case V8HImode : case V4SImode : case V2DImode : if ( TARGET_SSE4_1 ) { gen = gen_sse4_1_pblendvb ; if ( mode != V16QImode ) d = gen_reg_rtx ( V16QImode ) ; op_false = gen_lowpart ( V16QImode , op_false ) ; op_true = gen_lowpart ( V16QImode , op_true ) ; cmp = gen_lowpart ( V16QImode , cmp ) ; } break ; case V8SFmode : if ( TARGET_AVX ) gen = gen_avx_blendvps256 ; break ; case V4DFmode : if ( TARGET_AVX ) gen = gen_avx_blendvpd256 ; break ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( TARGET_AVX2 ) { gen = gen_avx2_pblendvb ; if ( mode != V32QImode ) d = gen_reg_rtx ( V32QImode ) ; op_false = gen_lowpart ( V32QImode , op_false ) ; op_true = gen_lowpart ( V32QImode , op_true ) ; cmp = gen_lowpart ( V32QImode , cmp ) ; } break ; case V64QImode : gen = gen_avx512bw_blendmv64qi ; break ; case V32HImode : gen = gen_avx512bw_blendmv32hi ; break ; case V16SImode : gen = gen_avx512f_blendmv16si ; break ; case V8DImode : gen = gen_avx512f_blendmv8di ; break ; case V8DFmode : gen = gen_avx512f_blendmv8df ; break ; case V16SFmode : gen = gen_avx512f_blendmv16sf ; break ; default : break ; } if ( gen != NULL ) { emit_insn ( gen ( d , op_false , op_true , cmp ) ) ; if ( d != dest ) emit_move_insn ( dest , gen_lowpart ( GET_MODE ( dest ) , d ) ) ; } else { op_true = force_reg ( mode , op_true ) ; t2 = gen_reg_rtx ( mode ) ; if ( optimize ) t3 = gen_reg_rtx ( mode


<s> auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( MF -> getSubtarget ( ) ) ; auto & HFI = * HST . getFrameLowering ( ) ; if ( ! HFI . needsAligna ( * MF ) ) return ; MachineFrameInfo * MFI = MF -> getFrameInfo (


<s> } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , Ops ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; unsigned NumOps = Call . getNode ( ) -> getNumOperands ( ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load .


<s> BuildMI ( MBB , MI . getIterator ( ) , DL , TII -> get ( <STR_LIT> ) , Reg ) . addOperand ( * Val ) ; MI . eraseFromParent ( ) ; return false ; } MachineInstr * MovRel = BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( Val -> getReg ( ) , getUndefRegState ( Val -> isUndef (

) ) ) . addReg ( Dst , RegState :: Implicit ) ;


<s> SDValue Hi = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , In ) ; SDValue Lo = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , In ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( <STR_LIT> ) ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI . CreateFixedObject ( - <NUM_LIT> * TCSPDelta


<s> for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( Imm % NElts + NElts ) ; Imm /=


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( DisableFramePointerElim ( MF ) || MF . getFrameInfo ( )

-> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> unsigned getVGPRUsage ( ) { return maxVregUsage


<s> else if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTPC ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E )


<s> static DecodeStatus DecodeBITInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus status ; unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pos2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pos1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; status = DecodeDataRegsRegisterClass ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( pos1 ) ) ; status = DecodeDataRegsRegisterClass ( Inst , s2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( pos2 ) ) ; return MCDisassembler


<s> assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs


<s> AU . addRequired < DominatorTreeWrapperPass >


<s> APInt MaskInt64 ( <NUM_LIT> , I64String , <NUM_LIT> ) ; SDValue MaskNode64 = DAG -> getConstant ( MaskInt64 , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Pool ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) Pool . push_back ( MaskNode64 ) ; return BUILD_VECTOR ( NumType , Pool


<s> SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , InFlag ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; InFlag = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; } MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , makeArrayRef ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back ( Chain ) ; CallOpc = <STR_LIT> ; Callee . setNode ( nullptr ) ; if ( isSVR4ABI && is<ISA_LIT>64 && ! isELFv2ABI && ! hasNest ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; if ( isTailCall ) Ops . push_back ( DAG . getRegister ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , PtrVT ) ) ; } if ( Callee . getNode ( ) ) { Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; } if ( isTailCall ) Ops . push_back ( DAG . getConstant ( SPDiff , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( isSVR4ABI && is<ISA_LIT>64 && ! isPatchPoint ) { setUsesTOCBasePtr ( DAG )


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return


<s> MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator It = ++ MBB -> getIterator ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IfTrueReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IfFalseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool NZCVKilled = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock * TrueBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It ,


<s> MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: create ( SSym , Ctx ) , Ctx ) ; } return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI ,


<s> return LowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , AsmPrinter . GetBlockAddressSymbol ( MO .


<s> int NumInterestingAllocas = <NUM_LIT> ; for ( auto & I : Allocas ) { AllocaInfo & Info = I . second ; assert ( Info . AI ) ; if ( ! isInterestingAlloca ( * Info . AI ) ) { Info . Tag = - <NUM_LIT> ; continue ; } alignAndPadAlloca ( Info ) ; NumInterestingAllocas ++ ; Info . Tag = NextTag ; NextTag = ( NextTag + <NUM_LIT> ) % <NUM_LIT> ; } if ( NumInterestingAllocas == <NUM_LIT> ) return true ; SetTagFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base ; if ( NumInterestingAllocas > <NUM_LIT> ) { auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; if ( DTWP ) { Base = insertBaseTaggedPointer ( Allocas , & DTWP -> getDomTree ( ) ) ; } else { DominatorTree DT ( * F ) ; Base = insertBaseTaggedPointer ( Allocas , & DT ) ; } } else { Base = insertBaseTaggedPointer ( Allocas , nullptr ) ; } for ( auto & I : Allocas ) { const AllocaInfo & Info = I . second ; AllocaInst * AI = Info . AI ; if ( Info . Tag < <NUM_LIT> ) continue ; IRBuilder < > IRB ( Info . AI -> getNextNode ( ) ) ; Function * TagP = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> , { Info . AI -> getType ( ) } ) ; Instruction * TagPCall = IRB . CreateCall ( TagP , { Constant :: getNullValue ( Info . AI -> getType ( ) ) , Base , ConstantInt :: get ( IRB . getInt64Ty ( ) , Info . Tag ) } ) ; if ( Info . AI -> hasName ( ) ) TagPCall -> setName ( Info . AI -> getName ( ) + <STR_LIT> ) ; Info . AI -> replaceAllUsesWith ( TagPCall ) ; TagPCall -> setOperand ( <NUM_LIT> , Info . AI ) ; if ( UnrecognizedLifetimes . empty ( ) && Info . LifetimeStart . size ( ) == <NUM_LIT> && Info . LifetimeEnd . size ( ) == <NUM_LIT> ) { IntrinsicInst * Start = Info . LifetimeStart [ <NUM_LIT> ] ; uint64_t Size = dyn_cast < ConstantInt > ( Start -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Size = alignTo ( Size , kTagGranuleSize ) ; tagAlloca ( AI , Start -> getNextNode ( ) , Start -> getArgOperand ( <NUM_LIT> ) , Size ) ; untagAlloca ( AI , Info . LifetimeEnd [ <NUM_LIT> ] , Size ) ; } else { uint64_t Size = Info . AI -> getAllocationSizeInBits ( * DL ) . getValue ( ) / <NUM_LIT> ; Value * Ptr = IRB . CreatePointerCast ( TagPCall , IRB . getInt8PtrTy ( ) ) ; tagAlloca ( AI , & * IRB . GetInsertPoint ( ) , Ptr , Size ) ; for ( auto & RI : RetVec ) { untagAlloca ( AI , RI ,


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode *


<s> MVT VecVT = Src . getSimpleValueType ( ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT ,


<s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) { uint64_t nextAddress = Address


<s> <ISA_LIT>TargetAsmInfo :: <ISA_LIT>TargetAsmInfo ( const <ISA_LIT>TargetMachine & TM ) : ELFTargetAsmInfo ( TM ) { AlignmentIsInBytes =


<s> float F = BitsToFloat ( Imm . Val ) ; return isImm ( ) && ( ( Imm . Val <= <NUM_LIT> && Imm . Val >= - <NUM_LIT> ) || ( F == <NUM_LIT> || F == <NUM_LIT> || F == - <NUM_LIT> || F ==


<s> const TargetFrameLowering * TFI = MF .


<s> bool <ISA_LIT>AAResult :: pointsToConstantMemory ( const MemoryLocation & Loc

, AAQueryInfo & QInfo , bool OrLocal ) {


<s> if ( getParser ( ) . ParseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , <NUM_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken ::

Comma ) ) return Error ( L , <STR_LIT> ) ;


<s> a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_add ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64 =


<s> return ( uint32x4_t ) __builtin_aarch64_subhn2v2di ( ( int32x2_t ) __a , ( int64x2_t ) __b , (


<s> if ( ! to_reg ) return tp ; reg = gen_reg_rtx ( Pmode ) ; insn = gen_rtx_SET ( VOIDmode , reg , tp ) ; insn = emit_insn ( insn ) ; return reg


<s> if ( Flags . isDefined ( ) ) return Flags . hasNoSignedZeros ( ) ; return false


<s> if ( ( unsigned long ) LARCH_ACTUAL_TUNE < N_TUNE_TYPES

) return loongarch_cpu_issue_rate [ LARCH_ACTUAL_TUNE ] ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10Lsl2 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable (


<s> start_offset = - crtl -> args . pretend_args_size - UNITS_PER_WORD ; offset = start_offset ; which_scratch = <NUM_LIT> ; for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( need_to_save_reg ( regno ) ) { rtx r = reg_save_addr [ which_scratch ] ; int from_regno ; int cfa_offset = frame_pointer_needed ? offset : total_size + offset ; if ( r == NULL_RTX ) { rtx p = compute_frame_addr ( offset , & next_scratch_regno ) ; r = gen_rtx_REG ( word_mode , next_scratch_regno -- ) ; reg_save_addr [ which_scratch ] = r ; emit_insn ( gen_rtx_SET ( r , p ) ) ; } else { int stride = ROUND_ROBIN_SIZE * - UNITS_PER_WORD ; rtx p = gen_rtx_PLUS ( Pmode , r , GEN_INT ( stride ) ) ; emit_insn ( gen_rtx_SET ( r , p ) ) ; } from_regno = ( fp_copy_regno >= <NUM_LIT> && regno == HARD_FRAME_POINTER_REGNUM ) ? fp_copy_regno : regno ; FRP ( frame_emit_store ( from_regno , regno , r , cfa , cfa_offset ) ) ; offset -= UNITS_PER_WORD ; which_scratch = ( which_scratch +


<s> static bool sh_pass_in_reg_p ( const CUMULATIVE_ARGS & cum , machine_mode mode , const_tree type ) { return ( ( type == <NUM_LIT> || ( ! TREE_ADDRESSABLE ( type ) && ( ! ( TARGET_HITACHI || cum . renesas_abi ) || ! ( AGGREGATE_TYPE_P ( type ) || ( ! TARGET_FPU_ANY && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SFmode ) ) ) ) ) ) ) && ! cum . force_mem && ( TARGET_SH2E ? ( ( mode ) == BLKmode ? ( ( cum . arg_count [ ( int ) SH_ARG_INT ] * UNITS_PER_WORD + int_size_in_bytes ( type ) ) <= NPARM_REGS ( SImode ) * UNITS_PER_WORD ) : ( ( sh_round_reg ( cum , mode ) + HARD_REGNO_NREGS ( BASE_ARG_REG

( mode ) , mode ) ) <= NPARM_REGS ( mode ) ) ) : sh_round_reg ( cum , mode ) < NPARM_REGS ( mode ) ) ) ;


<s> if ( LoadBase . isReg ( ) != StoreBase . isReg ( ) ) return false ; if ( LoadBase . isReg ( ) ) return LoadBase . getReg ( ) == StoreBase . getReg


<s> TRI -> getPhysRegClass ( Reg ) ; RC = TRI -> getSubRegClass ( RC , SubReg ) ; for ( MachineRegisterInfo :: use_instr_iterator I = MRI . use_instr_begin ( Reg ) , E = MRI . use_instr_end ( ) ; I != E ; ++ I ) { switch ( I -> getOpcode (


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr


<s> llvm :: FunctionPass * llvm :: createR600EmitClauseMarkers ( ) { return new R600EmitClauseMarkers (


<s> if ( ScaleLog <= <NUM_LIT> || ScaleLog >= <NUM_LIT> || Mask != ( <NUM_LIT> << ScaleLog ) ) return true ; EVT VT = N . getValueType ( ) ; SDLoc DL ( N ) ; SDValue Eight = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue NewMask = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , DL , VT , X , Eight ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , Srl , NewMask ) ; SDValue ShlCount = DAG . getConstant ( ScaleLog , <STR_LIT> ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , And , ShlCount ) ; InsertDAGNode ( DAG , N , Eight ) ; InsertDAGNode ( DAG , N , Srl ) ; InsertDAGNode ( DAG , N , NewMask


<s> bool fixupNeedsRelaxation ( const MCFixup & , uint64_t , const MCRelaxableFragment *

, const MCAsmLayout & ) const override {


<s> <ISA_LIT>BaseRegisterInfo :: <ISA_LIT>BaseRegisterInfo ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , STI ( sti ) ,


<s> unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( FP ) ; if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; else { MRI . setPhysRegUnused ( <STR_LIT> ) ; MRI . setPhysRegUnused (


<s> return ( __m128i ) __builtin_ia32_cvtpd2dq128_mask ( ( __v2df ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8 )


<s> case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) && isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue N000 = N0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue FPConst = DAG . getBitcast ( VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( FPOpcode , SDLoc ( N0 ) , VT , N000 , FPConst ) ; } return SDValue (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI

, const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_LOAD_OP ( SDValue Op , SelectionDAG & DAG , unsigned Opcode ) const { auto * Node = cast < AtomicSDNode > ( Op . getNode ( ) ) ; EVT NarrowVT = Node -> getMemoryVT ( ) ; EVT WideVT = <STR_LIT> ; if ( NarrowVT == WideVT ) return Op ; int64_t BitSize = NarrowVT . getSizeInBits ( ) ; SDValue ChainIn = Node -> getChain ( ) ; SDValue Addr = Node -> getBasePtr ( ) ; SDValue Src2 = Node -> getVal ( ) ; MachineMemOperand * MMO = Node -> getMemOperand ( ) ; SDLoc DL ( Node ) ; EVT PtrVT = Addr . getValueType ( ) ; if ( Opcode == <STR_LIT> ) if ( auto * Const = dyn_cast < ConstantSDNode > ( Src2 ) ) { Opcode = <STR_LIT> ; Src2 = DAG . getConstant ( - Const -> getSExtValue ( ) , Src2 . getValueType ( ) ) ; } SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> ,


<s> Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysCR ( Num , S , getLoc ( ) , getContext ( ) ) ) ; return


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) .


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) )


<s> <ISA_LIT>MCShuffler ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst & MCB , const MCInst * AddMI , bool bInsertAtFront = false ) : <ISA_LIT>Shuffler ( MCII , STI ) { init ( MCB , AddMI ,


<s> int <ISA_LIT>VSXSwapRemoval :: addSwapEntry ( MachineInstr * MI , <ISA_LIT>VSXSwapEntry & SwapEntry ) { SwapEntry . VSEMI = MI ; SwapEntry . VSEId = SwapVector .


<s> return ( __m128d ) __builtin_ia32_loadupd128_mask ( ( __v2df * ) __P , ( __v2df ) __W ,


<s> O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; }


<s> assert ( getStubFactory ( ) != NULL && getBRIslandFactory ( ) != NULL ) ; size_t num_new_stubs = <NUM_LIT> ; size_t stubs_strlen = <NUM_LIT> ; if ( config ( ) . targets ( ) . fixCA53Erratum835769 ( ) || config ( ) . targets ( ) . fixCA53Erratum843419 ( ) ) { scanErrata ( pModule , pBuilder , num_new_stubs , stubs_strlen ) ; } ELFFileFormat * file_format = getOutputFormat ( ) ; Module :: obj_iterator input , inEnd = pModule . obj_end ( ) ; for ( input = pModule . obj_begin ( ) ; input != inEnd ; ++ input ) { LDContext :: sect_iterator rs , rsEnd = ( * input ) -> context ( ) -> relocSectEnd ( ) ; for ( rs = ( * input ) -> context ( ) -> relocSectBegin ( ) ; rs != rsEnd ; ++ rs ) { if ( LDFileFormat :: Ignore == ( * rs ) -> kind ( ) || ! ( * rs ) -> hasRelocData ( ) ) continue ; RelocData :: iterator reloc , rEnd = ( * rs ) -> getRelocData ( ) -> end ( ) ; for ( reloc = ( * rs ) -> getRelocData ( ) -> begin ( ) ; reloc != rEnd ; ++ reloc ) { Relocation * relocation = llvm :: cast < Relocation > ( reloc ) ; switch ( relocation -> type ( ) ) { case llvm :: ELF :: R_AARCH64_CALL26 : case llvm :: ELF :: R_AARCH64_JUMP26 : { uint64_t sym_value = <NUM_LIT> ; LDSymbol * symbol = relocation -> symInfo ( ) -> outSymbol ( ) ; if ( symbol -> hasFragRef ( ) ) { uint64_t value = symbol -> fragRef ( ) -> getOutputOffset ( ) ; uint64_t addr = symbol -> fragRef ( ) -> frag ( ) -> getParent (


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ; } else printOperand ( MI


<s> machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == <NUM_LIT> ) { unsigned int nbits = GET_MODE_NUNITS ( cmp_ops_mode ) ; cmp_mode = int_mode_for_size ( nbits , <NUM_LIT> ) . require ( ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case E_V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case E_V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case E_V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case E_V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode


<s> riscv_emit_stack_tie ( ) ; } if ( known_gt ( size , <NUM_LIT> ) ) { poly_int64 scalable_frame ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! size . is_constant ( ) ) { poly_int64 scalable_frame = size ; scalable_frame . coeffs [ <NUM_LIT> ] = size . coeffs [ <NUM_LIT> ] ; riscv_v_adjust_scalable_frame ( stack_pointer_rtx , scalable_frame , false ) ; size -= scalable_frame ; } HOST_WIDE_INT constant_frame = size . to_constant ( ) ; if ( constant_frame == <NUM_LIT> ) return ; if ( SMALL_OPERAND ( - constant_frame ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - constant_frame ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - constant_frame ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode ,


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; bool Valid ; auto Mapper = <STR_LIT> ( getAvailableFeatures ( ) ) ; std :: string Name = Mapper . toString ( Val , Valid ) ; if ( Valid ) O << StringRef ( Name )


<s> if ( Opcode == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success


<s> if ( Op . isReg ( ) ) { O << '%' << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << '$' << Op .


elt_mode ( elt_mode_in ) , insn ( PTRUE ) {


<s> for ( const MachineInstr & MI : MBB . terminators ( ) ) for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . isMBB ( ) && MO . getMBB (


<s> void <ISA_LIT>InstPrinter :: printD16 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printNamedBit ( MI , OpNo , O ,


<s> static bool isCallOrRealInstruction ( MachineInstr & MI ) { return MI . isCall ( ) || ( ! MI . isPseudo ( ) && !


<s> case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ; if ( ! MI )


<s> const MachineOperand & Src2 = MI . getOperand ( <NUM_LIT> ) ; RegisterSubReg R1 ( Src1 ) ; bool Eval = false ; LatticeCell RC ; switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Eval = evaluateANDrr ( R1 , RegisterSubReg ( Src2 ) , Inputs , RC ) ; break ; case <STR_LIT> : { if ( ! Src2 . isImm ( ) ) return false ; APInt A ( <NUM_LIT> , Src2 . getImm ( ) , true ) ; Eval = evaluateANDri ( R1 , A , Inputs , RC ) ; break ; } case <STR_LIT> : case <STR_LIT> : Eval = evaluateORrr ( R1 , RegisterSubReg ( Src2 ) , Inputs , RC ) ; break ; case <STR_LIT> : { if ( ! Src2 . isImm ( ) ) return false ; APInt A ( <NUM_LIT> , Src2 . getImm ( ) , true ) ; Eval = evaluateORri ( R1 , A , Inputs , RC ) ; break ; } case <STR_LIT> : case <STR_LIT> : Eval = evaluateXORrr ( R1 , RegisterSubReg ( Src2 ) , Inputs ,


<s> return RegNo ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> * RegNo ; } } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isDFPImm (


<s> unsigned CurrentSubReg = * SubRegIt ; unsigned EncVal = MCRegInfo -> getEncodingValue ( CurrentSubReg ) ; Value |= <NUM_LIT> << EncVal ; if ( GPR32RegClass -> contains ( CurrentSubReg ) || GPR64RegClass -> contains ( CurrentSubReg ) ) ri_gprmask |= Value ; else if ( FGR32RegClass -> contains ( CurrentSubReg ) || FGR64RegClass -> contains ( CurrentSubReg ) || AFGR64RegClass -> contains ( CurrentSubReg )

|| MSA128BRegClass -> contains ( CurrentSubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ;


<s> AssemblerDialect = AsmWriterVariant == Default ? <NUM_LIT> : AsmWriterVariant ; PointerSize = <NUM_LIT> ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective =


<s> case Others : break ; case CortexA35 : break ; case CortexA53 : PrefFunctionAlignment = <NUM_LIT> ; break ; case CortexA55 : break ; case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : PrefFunctionAlignment = <NUM_LIT> ; break ; case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM1 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT>


<s> switch ( getLexer ( ) . getKind ( ) ) { default : break ; case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; unsigned RegKind ; if ( matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) { StringRef name = Parser . getTok ( ) . getString ( ) ; Parser . Lex ( ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; switch ( RegNo ) { default : Op = <STR_LIT> ( RegNo , RegKind , S , E ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : if ( name == <STR_LIT> ) Op = <STR_LIT> ( <STR_LIT> , S ) ; else Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; } break ; } if ( match<ISA_LIT>AsmModifiers ( EVal , E ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Op = <STR_LIT> ( EVal , S , E ) ; } break ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: LParen : if ( ! getParser ( ) . parseExpression ( EVal , E ) ) Op = <STR_LIT> ( EVal , S , E ) ; break ; case AsmToken :: Identifier


<s> break ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; DEBUG ( CRI . MI -> getParent ( ) -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; SplitBefore -> dump ( ) ) ; MachineInstr * Branch = MRI -> use_nodbg_begin ( CRI . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getParent ( ) ; MachineBasicBlock * MBB = SplitBefore -> getParent ( ) ; auto FirstTerminator = MBB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator FirstInstrToMove = UsingDef1 ? CRI . TrueDefs . first : CRI . TrueDefs . second ; MachineBasicBlock :: iterator SecondInstrToMove = UsingDef1 ? CRI . CopyDefs . first : CRI . CopyDefs . second ; MBB -> splice ( FirstTerminator , MBB , FirstInstrToMove ) ; if ( FirstInstrToMove != SecondInstrToMove ) MBB -> splice ( FirstTerminator , MBB , SecondInstrToMove ) ; MBB -> splice ( FirstTerminator , MBB , CRI . MI ) ; unsigned Opc = CRI . MI -> getOpcode ( ) ; bool InvertOrigBranch , InvertNewBranch , TargetIsFallThrough ; computeBranchTargetAndInversion ( Opc , Branch -> getOpcode ( ) , UsingDef1 , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough ) ; MachineInstr * SplitCond = UsingDef1 ? CRI . CopyDefs . second : CRI . CopyDefs . first ; DEBUG ( dbgs ( ) << <STR_LIT> << ( InvertNewBranch ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( TargetIsFallThrough ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Branch -> dump ( ) ) ; BlockSplitInfo BSI { Branch , SplitBefore , SplitCond , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough , MBPI , CRI . MI , UsingDef1 ? CRI . CopyDefs . first : CRI . CopyDefs . second } ; bool Changed = splitMBB ( BSI ) ; if ( Changed ) { bool Input1CRlogical = CRI . TrueDefs . first && isCRLogical ( * CRI . TrueDefs . first ) ; bool Input2CRlogical = CRI . TrueDefs . second && isCRLogical ( * CRI . TrueDefs . second ) ; if ( Input1CRlogical ) AllCRLogicalOps . push_back ( createCRLogicalOpInfo ( * CRI . TrueDefs . first ) ) ; if ( Input2CRlogical ) AllCRLogicalOps . push_back ( createCRLogicalOpInfo ( * CRI


<s> static bool v850_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( ! TARGET_GCC_ABI ) return <NUM_LIT> ; unsigned HOST_WIDE_INT size = arg .


<s> void printS32ImmOperand ( const MachineInstr * MI , int OpNum , raw_ostream


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Basereg , <NUM_LIT> , <NUM_LIT> , Loc


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { for ( unsigned i = <NUM_LIT> , e = LegalFPImmediates . size ( ) ; i != e ; ++ i ) { if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; } return false


<s> if ( TARGET_ELF && ( TARGET_64BIT || DEFAULT_ABI == ABI_V4 ) && cum -> escapes ) { if ( SCALAR_FLOAT_MODE_P ( mode ) ) { rs6000_passes_float = true ; if ( ( HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT ) && ( FLOAT128_IBM_P ( mode ) || FLOAT128_IEEE_P ( mode ) || ( type != NULL && TYPE_MAIN_VARIANT ( type ) == long_double_type_node ) ) ) rs6000_passes_long_double = true ; } if ( named && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) rs6000_passes_vector = true ; } if ( TARGET_ALTIVEC_ABI && ( ALTIVEC_OR_VSX_VECTOR_MODE ( elt_mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) == <NUM_LIT> ) ) ) { bool stack = false ; if ( USE_ALTIVEC_FOR_ARG_P ( cum , elt_mode , named ) ) { cum -> vregno += n_elts ; if ( ! targetm . calls . split_complex_arg && type && TREE_CODE ( type ) == COMPLEX_TYPE && elt_mode == KCmode ) cum -> vregno ++ ; if ( ! TARGET_ALTIVEC ) error ( <STR_LIT> <STR_LIT> <STR_LIT> , <STR_LIT> ) ; if ( ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_64BIT ) || ( cum -> stdarg && DEFAULT_ABI != ABI_V4 ) ) stack = true ; } else stack = true ; if ( stack ) { int align ; if ( TARGET_32BIT ) align = - ( rs6000_parm_offset ( ) + cum -> words ) & <NUM_LIT> ; else align = cum -> words & <NUM_LIT> ; cum -> words += align + rs6000_arg_size ( mode , type ) ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , cum -> words , align ) ; fprintf ( stderr , <STR_LIT> , cum -> nargs_prototype , cum -> prototype , GET_MODE_NAME ( mode ) ) ; } } } else if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( mode , type


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue & Imm


<s> uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || ( NumLanes != <NUM_LIT> && NumLanes != <NUM_LIT> ) ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ; return FixConv


<s> case VK_<ISA_LIT>_HIGH : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHER : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHERA : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case VK_<ISA_LIT>_HIGHEST


<s> if ( CPEs [ J ] . RefCount == <NUM_LIT> && CPEs [ J ] . CPEMI ) { removeDeadCPEMI ( CPEs [ J ] . CPEMI ) ; CPEs [ J ] . CPEMI = nullptr ; MadeChange =


<s> const <ISA_LIT>TargetLowering * TL = ( <ISA_LIT>TargetLowering * ) getTargetLowering ( ) ; return TL -> allowFMA ( * MF ,


<s> static SDValue LowerMEMBARRIER ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op5 = Op . getOperand ( <NUM_LIT> ) ; unsigned isDeviceBarrier = cast < ConstantSDNode > ( Op5 ) -> getZExtValue


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; return SDValue (


<s> const unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const unsigned Imm12 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; const unsigned TypeT3 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sign1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sign2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned S = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( sign1 != sign2 ) return MCDisassembler :: Fail ; DecodeStatus DS = MCDisassembler :: Success ; if ( ( ! Check ( DS , DecodeGPRspRegisterClass ( Inst , Rd , Address , Decoder ) ) ) || ( ! Check ( DS , DecodeGPRspRegisterClass ( Inst , Rn , Address , Decoder ) ) ) ) return MCDisassembler :: Fail ; if ( TypeT3 ) { Inst . setOpcode ( sign1 ? <STR_LIT> : <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Imm12 ) ) ; } else { Inst . setOpcode ( sign1 ? <STR_LIT>


<s> case AUTOS_LABEL : return <STR_LIT> ; case FRAME_LABEL : return <STR_LIT> ; case TEMPS_LABEL : return <STR_LIT> ; case ARGS_LABEL : return <STR_LIT> ; case RET_LABEL : return <STR_LIT> ; case LIBCALL : return


<s> } if ( ! OperandChanged ) { return C ; } Value * NewValue = UndefValue :: get ( C -> getType ( ) ) ; if ( isa < ConstantVector > ( C ) ) { for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Value * Idx = ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , i ) ; NewValue = Builder . CreateInsertElement ( NewValue , NewOperands [ i ] , Idx ) ; } } else { for ( unsigned i = <NUM_LIT> ; i < NumOperands ;


<s> return RR ; } ; RegisterSet MaxDF ; for ( RegisterRef I : HasDF -> second ) MaxDF . insert ( MaxCoverIn ( I , HasDF -> second ) ) ; std :: vector < RegisterRef > MaxRefs ; for ( RegisterRef I : MaxDF ) MaxRefs . push_back ( MaxCoverIn ( I , AllRefs ) ) ; llvm :: sort ( MaxRefs . begin ( ) , MaxRefs . end ( ) ) ; auto NewEnd = std :: unique ( MaxRefs . begin ( ) , MaxRefs . end ( ) ) ; MaxRefs . erase ( NewEnd , MaxRefs . end ( ) ) ; auto Aliased = [ this , & MaxRefs ] ( RegisterRef RR , std :: vector < unsigned > & Closure ) -> bool { for ( unsigned I : Closure ) if ( PRI . alias ( RR , MaxRefs [ I ] ) ) return true ; return false ; } ; NodeList Preds ; const MachineBasicBlock * MBB = BA . Addr -> getCode ( ) ; for ( MachineBasicBlock * PB : MBB -> predecessors ( ) ) Preds . push_back ( findBlock ( PB ) ) ; while ( ! MaxRefs . empty ( ) ) { std :: vector < unsigned > ClosureIdx = { <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i != MaxRefs . size ( ) ; ++ i ) if ( Aliased ( MaxRefs [ i ] , ClosureIdx ) ) ClosureIdx . push_back ( i ) ; unsigned CS = ClosureIdx . size ( ) ; NodeAddr < PhiNode * > PA = newPhi ( BA ) ; for ( unsigned X = <NUM_LIT> ; X != CS ; ++ X ) { RegisterRef RR = MaxRefs [ ClosureIdx [ X ] ] ; uint16_t PhiFlags = NodeAttrs :: PhiRef | NodeAttrs :: Preserving ; NodeAddr < DefNode * > DA = newDef ( PA , RR , PhiFlags ) ; PA . Addr -> addMember ( DA , * this ) ; } for ( NodeAddr < BlockNode * > PBA : Preds ) { for ( unsigned X = <NUM_LIT> ; X != CS ; ++ X ) { RegisterRef RR = MaxRefs [ ClosureIdx [ X ] ] ; NodeAddr < PhiUseNode * > PUA = newPhiUse ( PA , RR , PBA ) ; PA . Addr -> addMember ( PUA , * this ) ; } } auto Begin = MaxRefs . begin (


<s> const LLT v32s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v64s8 , v32s16 } ) setAction ( { BinOp , Ty } , Legal ) ; setAction ( { G_MUL , v32s16 } , Legal ) ; if ( ! Subtarget . hasVLX ( )


<s> rtx_insn * i0 ; if ( from_mode == QImode ) i0 = emit_insn_after ( gen_extendqisi2 ( r , set_src ) , insn ) ; else if ( from_mode == HImode ) i0 = emit_insn_after ( gen_extendhisi2 ( r , set_src ) , insn ) ; else gcc_unreachable ( ) ; emit_insn_after ( gen_move_insn ( XEXP ( set_rtx , <NUM_LIT> ) , gen_lowpart ( GET_MODE ( set_src ) , r ) ) , i0 ) ; set_insn_deleted ( insn ) ; return r ; } else { rtx extension_dst = XEXP ( set_rtx , <NUM_LIT> ) ; if ( GET_MODE ( extension_dst ) != SImode ) extension_dst = simplify_gen_subreg ( SImode , extension_dst , GET_MODE ( extension_dst ) , <NUM_LIT> ) ; if ( modified_between_p ( extension_dst , insn , use_at_insn ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , REGNO ( extension_dst ) , INSN_UID ( insn ) ) ; rtx r = gen_reg_rtx ( SImode ) ; emit_insn_after ( gen_move_insn ( r , extension_dst )


<s> switch ( IID ) { case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } APInt Demanded = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; SDValue DemandedLHS = TLI . SimplifyMultipleUseDemandedBits ( LHS , Demanded , DAG ) ; SDValue DemandedRHS = TLI . SimplifyMultipleUseDemandedBits ( RHS , Demanded , DAG ) ; if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( NewOpcode , SDLoc ( Node24 ) , Node24 -> getVTList ( ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ?


<s> return decodeRegisterClass ( Inst , RegNo


<s> } else { SDValue Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HalfIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue PackedElt = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { Vec , HalfIdx } ) , <NUM_LIT> ) ; SDValue AndIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Idx , Const1 } ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { AndIdx , Const1 } ) ; SDValue Const5 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Shift , Const5 } ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Mask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Mask , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Mask } ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Val , Shift } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT>


<s> bool <ISA_LIT>ModuleInfo :: isReadOnlyImage ( StringRef name , uint32_t iID ) const { const StringMap < <ISA_LIT>Kernel * > :: const_iterator kiter = mKernels . find ( name ) ; if ( kiter == mKernels . end ( ) ) { return false ; } return kiter -> second -> readOnly . count (


<s> if ( auto ErrMsg = validateMIMGDataSize ( Inst ) ) { Error ( IDLoc , * ErrMsg ) ; return false ; } if ( ! validateMIMGAddrSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAtomicDMask ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDMask , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMIMGGatherDMask ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDMask , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMovrels ( Inst , Operands ) ) { return false ; } if ( ! validateFlatOffset ( Inst , Operands ) ) { return false ; } if ( ! validateSMEMOffset ( Inst , Operands ) ) { return false ; } if ( ! validateMAIAccWrite ( Inst , Operands ) ) { return false ; } if ( ! validateMFMA ( Inst , Operands ) ) { return false ; } if ( ! validateCoherencyBits ( Inst , Operands , IDLoc ) ) { return false


<s> bool hasMSA ( ) const { return STI . getFeatureBits (


<s> UseHVX64BOps = false ; UseAudioOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; if ( isTinyCore ( ) ) { if ( ! EnableBSBSched . getPosition ( ) ) UseBSBScheduling = false ; } FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features .


<s> MVT InVT = In . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; EVT ExtVT = ( NumElts == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , ExtVT . getScalarType ( ) ) ; const Constant * C = cast < ConstantSDNode > ( Cst ) -> getConstantIntValue ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; SDValue Ld = DAG . getLoad ( Cst . getValueType ( ) , DL , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; SDValue Brcst = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ,


<s> if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpDWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDataDirective ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return false ; } if ( IDVal == <STR_LIT> ) return parseDirectiveOption ( ) ; if ( IDVal == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveAbiCalls ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( )


<s> static bool CC_<ISA_LIT>32_VarArgs ( unsigned ValNo , EVT ValVT , EVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , <ISA_LIT>_CCState & State , int NonVarArgsParams , int CurrentParam , bool ForceMem ) { unsigned ByValSize = <NUM_LIT> ; if ( ArgFlags . isByVal ( ) && ( ( ByValSize = ArgFlags . getByValSize ( ) ) > ( MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ) ) ) { ForceMem = true ; } if ( ! ForceMem && ( ( NonVarArgsParams == - <NUM_LIT> ) || ( CurrentParam <= NonVarArgsParams ) ) ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const unsigned RegList1 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT . getSimpleVT ( ) , Reg , LocVT . getSimpleVT ( ) , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const unsigned RegList2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList2 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT . getSimpleVT ( ) , Reg , LocVT . getSimpleVT ( ) , LocInfo ) ) ; return false ; } } } const Type * ArgTy = LocVT . getTypeForEVT ( State . getContext ( ) ) ; unsigned Alignment = State . getTarget ( ) . getDataLayout ( ) -> getABITypeAlignment ( ArgTy ) ; unsigned Size = State . getTarget ( ) . getDataLayout ( ) -> getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; if ( ArgFlags . isByVal ( ) ) { Size = ByValSize ; Alignment = <NUM_LIT> ; } unsigned Offset3 = State . AllocateStack ( Size , Alignment


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return MatchOperand_NoMatch ; StringRef NumString = Tok . getIdentifier ( ) . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal )


<s> void <ISA_LIT>ExpandISEL :: populateBlocks ( BlockISELList & BIL ) { for ( auto & MI : BIL ) { assert ( isISEL ( * MI ) && <STR_LIT> ) ; MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & ConditionRegister = MI -> getOperand ( <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Dest << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueValue << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FalseValue << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ConditionRegister << <STR_LIT> ) ; bool IsADDIInstRequired = ! useSameRegister ( Dest , TrueValue ) ; bool IsORIInstRequired = ! useSameRegister ( Dest , FalseValue ) ; if ( IsADDIInstRequired ) { BuildMI ( * TrueBlock , TrueBlockI , dl , TII -> get ( isISEL8 ( * MI ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; TrueBlock -> addLiveIn ( TrueValue . getReg ( ) ) ; } if ( IsORIInstRequired ) { FalseBlock -> addLiveIn ( FalseValue . getReg ( ) ) ; } if ( NewSuccessor ) { NewSuccessor -> addLiveIn ( Dest . getReg ( ) ) ; NewSuccessor -> addLiveIn ( TrueValue . getReg ( ) ) ; NewSuccessor -> addLiveIn ( FalseValue . getReg ( ) ) ; NewSuccessor -> addLiveIn ( ConditionRegister . getReg ( ) ) ; } if ( IsORIInstRequired ) BuildMI ( * FalseBlock , FalseBlockI , dl , TII -> get ( isISEL8 ( * MI ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( FalseValue ) . add ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> eraseFromParent


<s> return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op


<s> sparc_emit_set_symbolic_const64 ( temp1 , XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) , NULL_RTX ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_PLUS ( DImode , temp1 , temp2 ) ) ) ; return ; } if ( temp && GET_MODE ( temp ) == TImode ) { ti_temp = temp ; temp = gen_rtx_REG ( DImode , REGNO ( temp ) ) ; } switch ( sparc_cmodel ) { case CM_MEDLOW : if ( temp ) temp1 = temp ; else temp1 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_rtx_SET ( temp1 , gen_rtx_HIGH ( DImode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_LO_SUM ( DImode , temp1 , op1 ) ) ) ; break ; case CM_MEDMID : if ( temp ) { temp1 = op0 ; temp2 = op0 ; temp3 = temp ; } else { temp1 = gen_reg_rtx ( DImode ) ; temp2 = gen_reg_rtx ( DImode ) ; temp3 = gen_reg_rtx ( DImode ) ; } emit_insn ( gen_seth44 ( temp1 , op1 ) ) ; emit_insn ( gen_setm44 ( temp2 , temp1 , op1 ) ) ; emit_insn ( gen_rtx_SET ( temp3 , gen_rtx_ASHIFT ( DImode , temp2 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_insn ( gen_setl44 ( op0 , temp3 , op1 ) ) ; break ; case CM_MEDANY : if ( temp ) { if ( rtx_equal_p ( temp , op0 ) ) { gcc_assert ( ti_temp ) ; temp = gen_rtx_REG ( DImode , REGNO ( temp ) + <NUM_LIT> ) ; } temp1 = op0 ; temp2 = temp ; temp3 = op0 ; temp4 = op0 ; temp5 = op0 ; } else { temp1 = gen_reg_rtx ( DImode ) ; temp2 = gen_reg_rtx ( DImode ) ; temp3 = gen_reg_rtx ( DImode ) ; temp4 = gen_reg_rtx ( DImode ) ; temp5 = gen_reg_rtx ( DImode ) ; } emit_insn ( gen_sethh ( temp1 , op1 ) ) ; emit_insn ( gen_setlm ( temp2 , op1 ) ) ; emit_insn ( gen_sethm ( temp3 , temp1 , op1 ) ) ; emit_insn ( gen_rtx_SET ( temp4 , gen_rtx_ASHIFT ( DImode , temp3 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_insn ( gen_rtx_SET ( temp5 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; emit_insn ( gen_setlo ( op0 , temp5 , op1 ) ) ; break ; case CM_EMBMEDANY : if ( data_segment_operand ( op1 , GET_MODE ( op1 ) ) ) { if ( temp ) { temp1 = temp ; temp2 = op0 ; } else { temp1 = gen_reg_rtx ( DImode


<s> if ( IsBFI && ! <STR_LIT> ( BFIImm , BitWidth ) ) { unsigned OrChunks = <NUM_LIT> , BFIChunks = <NUM_LIT> ; for ( unsigned Shift = <NUM_LIT> ; Shift < BitWidth ; Shift += <NUM_LIT> ) { if ( ( ( OrImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ OrChunks ; if ( ( ( BFIImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ BFIChunks ; } if ( BFIChunks > OrChunks ) return false ; } SDLoc DL ( N ) ; unsigned MOVIOpc = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * MOVI = CurDAG -> getMachineNode ( MOVIOpc , DL , VT , CurDAG -> getTargetConstant ( BFIImm , DL , VT ) ) ; SDValue Ops [ ] = { And . getOperand ( <NUM_LIT> ) , SDValue ( MOVI , <NUM_LIT> ) , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , VT , Ops


<s> bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; bool SrcIsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( SrcReg != <STR_LIT> ) { const TargetRegisterClass * RC = MF -> getRegInfo ( ) . getRegClass ( SrcReg ) ; unsigned CopyOpc = ( RC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , dl , TII -> get ( CopyOpc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ; } unsigned OpOpc = <NUM_LIT> ; bool NeedPred = false , NeedCC = false , NeedOp3 = false ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; NeedCC = true ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; break ; case <STR_LIT> : OpOpc = <STR_LIT> ; NeedPred = true ; NeedCC = true ; NeedOp3 = true ; break ; } MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( OpOpc ) , <STR_LIT> ) ; if ( OpOpc == <STR_LIT> ) AddDefaultT1CC ( MIB ) ; MIB . addReg ( <STR_LIT> ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NeedOp3 ) MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NeedPred ) AddDefaultPred ( MIB ) ; if ( NeedCC ) AddDefaultCC


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target


<s> return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask


<s> switch ( MI -> getOpcode ( ) ) { default : return <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case <STR_LIT> : return emitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSel16 ( <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSeliT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitSelT16 ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I816_ins ( <STR_LIT> , <STR_LIT> , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , false , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT> , true , MI , BB ) ; case <STR_LIT> : return emitFEXT_T8I8I16_ins ( <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes >


<s> for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default : return false ; case <STR_LIT> : expandRetRA ( MBB , MI ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB ,


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == <ISA_LIT>MCExpr

:: VK_<ISA_LIT>_CALL || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ) ;


<s> short NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( )


<s> return ( __mmask32 ) __builtin_ia32_kxorsi ( ( __mmask32 ) __A ,


<s> snprintf ( buf , sizeof buf , <STR_LIT> , src -> mode , src -> predicate , src -> constraint ) ; printf ( src -> rtl , buf ) ; fputs ( <STR_LIT> , stdout ) ; fputs ( template , stdout


<s> if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ; Cond . push_back ( MachineOperand :: CreateImm (


<s> PreAnalyzeReturnForF128 ( Outs ) ; CCState :: AnalyzeReturn (


<s> unsigned MaxElt ; SDValue ShuffleVec ; int WindowBase ; int WindowScale ; bool operator == ( SDValue OtherVec ) { return Vec == OtherVec ; } ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) { } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) { SmallestEltTy = SrcEltTy ; } } unsigned ResMultiplier = VT . getVectorElementType ( ) . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT .


<s> store_string = <STR_LIT> ; break ; case E_SImode : case E_SFmode : store_string = <STR_LIT> ; break ; case E_DImode : case E_DFmode : if ( ! TARGET_POWERPC64 ) gcc_unreachable ( ) ; store_string = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } else fatal_insn ( <STR_LIT> , reg ) ; if ( ! MEM_P ( mem ) ) fatal_insn ( <STR_LIT> , mem ) ; addr = XEXP ( mem , <NUM_LIT> ) ; fusion_split_address ( addr , & hi , & lo ) ; emit_fusion_addis ( tmp_reg , hi ) ; emit_fusion_load_store ( reg , tmp_reg , lo , store_string ) ; return <STR_LIT>


<s> UsedRegs [ Reg / <NUM_LIT> ] |= <NUM_LIT> << ( Reg & <NUM_LIT> ) ; if ( const unsigned * RegAliases = TRI . getAliasSet ( Reg ) ) for ( ; ( Reg = * RegAliases ) ;

++ RegAliases ) UsedRegs [ Reg / <NUM_LIT> ] |= <NUM_LIT> << ( Reg & <NUM_LIT> ) ;


<s> switch ( F -> getIntrinsicID ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : return true ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc :: Func Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc :: copysign : case LibFunc :: copysignf : continue ; case LibFunc :: copysignl : return true ; case LibFunc :: fabs : case LibFunc :: fabsf : case LibFunc :: fabsl : continue ; case LibFunc :: sqrt : case LibFunc :: sqrtf : case LibFunc :: sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc :: floor : case LibFunc :: floorf : case LibFunc :: floorl : Opcode = <STR_LIT> ; break ; case LibFunc :: nearbyint : case LibFunc :: nearbyintf : case LibFunc :: nearbyintl : Opcode = <STR_LIT> ; break ; case LibFunc :: ceil : case LibFunc :: ceilf : case LibFunc :: ceill : Opcode = <STR_LIT> ; break ; case LibFunc :: rint : case LibFunc :: rintf : case LibFunc :: rintl : Opcode = <STR_LIT> ; break ; case LibFunc :: round : case LibFunc :: roundf : case LibFunc :: roundl : Opcode = <STR_LIT> ; break ; case LibFunc :: trunc : case LibFunc ::


<s> insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || FLOAT128_2REG_P ( mode ) ) ) return true ; } } } return


<s> Register FrameReg = FrameInfo . isFixedObjectIndex ( Index ) && hasBasePointer ( SB . MF ) ? getBaseRegister ( ) : getFrameRegister ( SB . MF ) ; Align Alignment = FrameInfo . getObjectAlign ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( SB . MF , Index ) ; MachineMemOperand * MMO = SB . MF . getMachineMemOperand ( PtrInfo , IsLoad ? MachineMemOperand :: MOLoad : MachineMemOperand :: MOStore , SB . EltSize , Alignment ) ; if ( IsLoad ) { unsigned Opc = ST . enableFlatScratch ( ) ? <STR_LIT> :


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI ::

TargetCostKind CostKind , const Instruction * I ) {


<s> void <ISA_LIT>TargetStreamer :: emitSetFP ( unsigned FpReg , unsigned SpReg


<s> bool mayNeedRelaxation ( const MCInst & Inst ,

const MCSubtargetInfo & STI ) const override {


<s> const Function & F = MF -> getFunction ( ) ; if ( ! F . hasFnAttribute ( <STR_LIT> ) || F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) return false ; for ( const auto & Info : MF -> getFrameInfo ( ) . getCalleeSavedInfo ( ) ) { const auto Reg = Info . getReg ( ) ; if ( Reg == <STR_LIT> || Reg ==


<s> return __builtin_mve_vmvnq_m_sv4si ( __arm_vuninitializedq_s32 ( )


<s> static DecodeStatus decodeOperand_AReg_512 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { auto DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; return addOperand ( Inst , DAsm -> decodeSrcOp (

<ISA_LIT>Disassembler :: OPW512 , Imm | <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg )


<s> MachineBasicBlock * <ISA_LIT>ConstantIslands :: splitBlockBeforeInstr ( MachineInstr & MI ) { MachineBasicBlock * OrigBB = MI . getParent ( ) ; MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) ,


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent


<s> MCInst mci ; LowerMachineInstrToMCInst ( mi , mci , * this


<s> unsigned Op = i ; for ( unsigned e = MI . getNumOperands ( ) ; i != e ; ++ i ) MI . removeOperand


<s> ( * PI ) -> insert ( J , MI ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugInstr ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB , true ) ; if ( Changed && ! ReturnMBB . hasAddressTaken ( ) ) { if ( ReturnMBB . pred_size ( ) == <NUM_LIT> ) { MachineBasicBlock & PrevMBB = * * ReturnMBB . pred_begin ( ) ; if ( PrevMBB . isLayoutSuccessor ( & ReturnMBB ) && PrevMBB . canFallThrough ( ) ) { PrevMBB . splice ( PrevMBB . end ( ) , &


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallConv ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign


<s> if ( ST -> hasMVEFloatOps ( ) ) continue ; break ; default : break ; } if ( IsMasked ( & I ) ) { auto * VecTy = getVectorType ( Int ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; continue ; } for ( const Use & U : Int -> args ( ) ) { if ( isa < VectorType > ( U -> getType ( ) ) ) return false ; } } } if ( ! ActiveLaneMask )


<s> bool <ISA_LIT>ExpandPseudo :: expandASRW15Rd ( Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack , bool IsThumb ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , IsThumb ) ; new <ISA_LIT>TargetELFStreamer ( * S ) ; S -> getAssembler ( ) . setELFHeaderEFlags


<s> static unsigned toCallerWindow ( unsigned Reg ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> )


<s> HOST_WIDE_INT toffset ; int len = <NUM_LIT> , tlen ; if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( m -> fs . drap_valid ) { toffset = <NUM_LIT> - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( m -> fs . fp_valid ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; len =


<s> } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic !=


<s> if ( DecodeGPR8RegisterClass ( Inst , r , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return


<s> if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , true ) ; return SDValue ( )


<s> return ( __m64 ) __builtin_ia32_pmaddwd ( ( __v4hi )


<s> const __v4su shmax = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4su result ; rshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v4su )


<s> inline int get64BitInstrCost ( ) const { return ST -> hasHalfRate64Ops ( ) ? getHalfRateInstrCost


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerCopyToReg ( Op , DAG ) ; case


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int Lower , int Upper , Twine Msg = <STR_LIT> ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , Msg + <STR_LIT> + Twine ( Lower ) + <STR_LIT> + Twine ( Upper )


<s> bool SelectAddrIdxX16 ( SDValue N , SDValue & Base , SDValue & Index ) { return <ISA_LIT>Lowering -> SelectAddressRegReg ( N , Base , Index ,


<s> unsigned ArgSize = NextVA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( ArgSize , NextVA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; }


<s> if ( cfun -> static_chain_decl != NULL ) size += ( <NUM_LIT> * UNITS_PER_WORD ) ; cfun -> machine -> callee_save_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) cfun -> machine -> callee_save_size += UNITS_PER_WORD ; } cfun -> machine -> current_frame_size = XTENSA_STACK_ALIGN ( size + cfun -> machine -> callee_save_size + crtl -> outgoing_args_size + ( WINDOW_SIZE *


<s> static bool f64AssignAPCS ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , CCState & State , bool CanFail ) { static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else { if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; } if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT


<s> return AMDGPU :: VSrc_32RegClassID == RegClass ||

AMDGPU :: VSrc_64RegClassID == RegClass ;


<s> return ; } unsigned Opcode = Node -> getOpcode ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) )


<s> void AMDGPUTargetLowering :: AnalyzeFormalArguments ( CCState & State , const SmallVectorImpl


<s> if ( ! FI ) return ; const MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; unsigned FrameIndexAlign = MFI . getObjectAlign ( FI -> getIndex ( ) ) . value ( ) ; if ( ( FrameIndexAlign % <NUM_LIT> ) != <NUM_LIT> ) FlagSet &= ~ <STR_LIT> ; if ( ( FrameIndexAlign % <NUM_LIT> ) != <NUM_LIT> )


<s> return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return <NUM_LIT> ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT>


<s> if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } StringRef ArchName = has<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! has<ISA_LIT>32r5 ( ) && hasMSA ( ) && ! MSAWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; MSAWarningPrinted = true ; } if ( ! has<ISA_LIT>32r5 ( ) && hasVirt ( ) && ! VirtWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; VirtWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasCRC ( ) && ! CRCWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; CRCWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasGINV ( ) && ! GINVWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; GINVWarningPrinted = true ; } CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultBLGP (


<s> bool HasDef = false ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isUse ( ) ) continue ; if ( MO . getReg (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << V . getNode ( ) <<

<STR_LIT> << R << <STR_LIT> << S << <STR_LIT> << E << <STR_LIT> ) ;


<s> bool hasV5TEOps ( ) const { return <ISA_LIT>ArchVersion >=


<s> SDValue ABS = VecReduceOp0 ; if ( ABS -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || ABS -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDValue SUB = ABS -> getOperand ( <NUM_LIT> ) ; unsigned Opcode0 = SUB -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; unsigned Opcode1 = SUB -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( SUB -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> || SUB -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; bool IsZExt = false ; if ( Opcode0 == <STR_LIT> && Opcode1 == <STR_LIT> ) { IsZExt = true ; } else if ( Opcode0 == <STR_LIT> && Opcode1 == <STR_LIT> ) { IsZExt = false ; } else return SDValue ( ) ; SDValue EXT0 = SUB -> getOperand ( <NUM_LIT> ) ; SDValue EXT1 = SUB -> getOperand ( <NUM_LIT> ) ; if ( EXT0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> || EXT1 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue UABDHigh8Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , EXT0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue UABDHigh8Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , EXT1 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue UABDHigh8 = DAG . getNode ( IsZExt ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , UABDHigh8Op0 , UABDHigh8Op1 ) ; SDValue UABDL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> static void mips_code_end ( void ) { mips_finish_stub ( & mips16_rdhwr_stub


<s> default : output_operand_lossage ( <STR_LIT> ) ; } } if ( code == 'M' ) { const struct cgen_insn * insn ; mep_print_operand ( file , x , <NUM_LIT> ) ; if ( mep_get_move_insn ( mep_cmov , & insn ) && insn_data [ insn -> icode ] . n_operands == <NUM_LIT> ) { fputs ( <STR_LIT> , file ) ; if ( insn_data [ insn -> icode ] . operand [ <NUM_LIT> ] . predicate ( x , VOIDmode ) ) mep_print_operand ( file , x , <NUM_LIT> ) ; else mep_print_operand ( file , const0_rtx , <NUM_LIT> ) ; } return ; } encode_pattern ( x ) ; for ( i = <NUM_LIT> ; conversions [ i ] . pattern ; i ++ ) if ( conversions [ i ] . code == code && strcmp ( conversions [ i ] . pattern , pattern ) == <NUM_LIT> ) { for ( j = <NUM_LIT> ; conversions [ i ] . format [ j ] ; j ++ ) if ( conversions [ i ] . format [ j ] == '\\' ) { fputc ( conversions [ i ] . format [ j + <NUM_LIT> ] , file ) ; j ++ ; } else if ( ISDIGIT ( conversions [ i ] . format [ j ] ) ) { rtx r = patternr [ conversions [ i ] . format [ j ] - '0' ] ; switch ( GET_CODE ( r ) ) { case REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( r ) ] ) ; break ; case


<s> assert ( Dim < <NUM_LIT> ) ; DebuggerWorkItemIDStackObjectIndices [ Dim ]


<s> PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumberOfParts ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumberOfParts ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost =


<s> CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling ::


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG


<s> CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { MVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; Register ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; updateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; const TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; Register ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; updateValueMap ( I , ResultReg


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) ,

FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> bool <ISA_LIT>Subtarget :: isGVIndirectSymbol ( const GlobalValue * GV ) const { if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode


<s> for ( i = <NUM_LIT> ; i < sizeof ( avr_texinfo ) / sizeof ( * avr_texinfo ) ; i ++ ) if ( arch_id == avr_texinfo [ i ] . arch_id ) printf ( <STR_LIT> , mcu -> name , avr_texinfo [ i ] . texinfo ) ; } else if ( arch_id == ( enum avr_arch_id ) mcu -> arch_id ) { mcus [ n_mcus ++ ] = mcu


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target


<s> if ( ! isa < ExtractValueInst > ( Cond ) ) return false ; const auto * EV = cast < ExtractValueInst > ( Cond ) ; if ( ! isa < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ) return false ; const auto * II = cast < IntrinsicInst > ( EV -> getAggregateOperand ( ) ) ; MVT RetVT ; const Function * Callee = II -> getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( <NUM_LIT> ) ; if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; <STR_LIT> TmpCC ; switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; } if ( II -> getParent ( ) != I -> getParent ( ) ) return false ; BasicBlock :: const_iterator Start = I ; BasicBlock :: const_iterator End = II ; for ( auto Itr = std :: prev ( Start ) ; Itr != End ; -- Itr ) { if ( ! isa < ExtractValueInst > ( Itr ) ) return false ; const auto * EVI = cast < ExtractValueInst > ( Itr ) ; if ( EVI -> getAggregateOperand ( ) != II ) return


<s> } } const int AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy .

getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue ( ) ; Value = <STR_LIT> ( Value ) ; Inst . addOperand ( MCOperand :: createImm


<s> inline void function_expander :: add_input_operand ( machine_mode mode , rtx op ) { create_input_operand ( & m_ops [ opno ++ ] ,


<s> { <STR_LIT> , AARCH64_LS64_BUILTIN_LD64B , build_function_type_list ( ls64_arm_data_t , const_ptr_type_node , NULL_TREE ) } , { <STR_LIT> , AARCH64_LS64_BUILTIN_ST64B , build_function_type_list ( void_type_node , ptr_type_node , ls64_arm_data_t , NULL_TREE ) } , { <STR_LIT> , AARCH64_LS64_BUILTIN_ST64BV , build_function_type_list ( uint64_type_node , ptr_type_node , ls64_arm_data_t , NULL_TREE ) } , { <STR_LIT> , AARCH64_LS64_BUILTIN_ST64BV0 , build_function_type_list ( uint64_type_node , ptr_type_node , ls64_arm_data_t , NULL_TREE ) } , } ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( data ) ; ++ i ) aarch64_builtin_decls [ data [ i ] . code ] = aarch64_general_add_builtin ( data [ i ]

. name , data [ i ] . type , data [ i ] . code ) ;


<s> case AMDGPU :: VS_32RegClassID : case AMDGPU ::


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc


<s> unsigned Op1 , Op2 ; DecodeStatus S = Decode2OpInstruction ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Op1 , Op2 ) ; if ( S != MCDisassembler :: Success ) return DecodeL2OpInstructionFail ( Inst , Insn


<s> MCSymbolRefExpr :: VariantKind <ISA_LIT>AsmParser :: getVariantKind ( StringRef Symbol ) { MCSymbolRefExpr :: VariantKind VK = StringSwitch < MCSymbolRefExpr :: VariantKind > ( Symbol ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_IJMP_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_IJMP_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ) . Case ( <STR_LIT> , MCSymbolRefExpr

:: VK_<ISA_LIT>_GOT_OFST ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 ) . Case ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 ) . Default ( MCSymbolRefExpr :: VK_None ) ;