<s> <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned ATReg = <STR_LIT> ; unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TmpReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TOut . emitRR ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , SrcReg , TmpReg , IDLoc , STI ) ; TOut . emitR ( <STR_LIT> , ATReg , IDLoc , STI ) ; TOut . emitR ( <STR_LIT> , DstReg , IDLoc


<s> static rtx get_vector_offset ( rtx mem , rtx element , rtx base_tmp , unsigned scalar_size ) { if ( CONST_INT_P ( element ) ) return GEN_INT ( INTVAL ( element ) * scalar_size ) ; gcc_assert ( satisfies_constraint_Q ( mem ) ) ; rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( GET_MODE ( mem ) ) - <NUM_LIT> ) ; rtx and_op = gen_rtx_AND ( Pmode , element , num_ele_m1 ) ; emit_insn ( gen_rtx_SET ( base_tmp , and_op ) ) ; int shift = exact_log2 ( scalar_size ) ; gcc_assert ( shift >= <NUM_LIT> ) ; if ( shift > <NUM_LIT> ) { rtx shift_op = gen_rtx_ASHIFT ( Pmode , base_tmp


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo


<s> dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tlsoff_hilo ( tmp , addr , GEN_INT ( R_FRV_GOTTLSOFF_HI ) ) ) ; emit_insn ( gen_tls_tlsoff_ld ( dest , picreg , tmp , addr ) ) ; dest = gen_rtx_PLUS ( Pmode , tp , dest ) ; } break ; case TLS_MODEL_LOCAL_DYNAMIC : { rtx reg , retval ; if ( TARGET_INLINE_PLT ) retval = gen_inlined_tls_plt ( GEN_INT ( <NUM_LIT> ) ) ; else { retval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_call_gettlsoff ( retval , GEN_INT ( <NUM_LIT> ) , picreg ) ) ; } reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , gen_rtx_PLUS ( Pmode , retval , tp ) ) ) ; dest = gen_tlsmoff ( addr , reg ) ; break ; } case TLS_MODEL_LOCAL_EXEC


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue


<s> return ( type != NULL_TREE ? ( TYPE_ALIGN ( type ) <= PARM_BOUNDARY ? PARM_BOUNDARY : TYPE_ALIGN ( type ) )

: ( GET_MODE_ALIGNMENT ( mode ) <= PARM_BOUNDARY ? PARM_BOUNDARY : GET_MODE_ALIGNMENT ( mode ) ) ) ;


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG .

getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ;


<s> rtx base ; unsigned int regno ; if ( GET_CODE ( x ) == PLUS ) { if ( ! rtx_ok_for_offset_p ( mode , XEXP ( x , <NUM_LIT> ) ) ) return false ; base = XEXP ( x , <NUM_LIT> ) ; } else base = x ; if ( GET_CODE ( base ) == SUBREG ) base = SUBREG_REG ( base ) ; if ( ! REG_P ( base ) ) return false ; regno = REGNO ( base ) ; if ( strict ) return REGNO_OK_FOR_BASE_P ( regno ) ; return BASE_REGISTER_P ( regno ) || regno >=


<s> static rtx warp_prop_gen ( rtx reg , propagate_mask pm , unsigned ARG_UNUSED ( count ) , void * ARG_UNUSED ( data ) , bool ARG_UNUSED ( vector ) ) { if ( ! ( pm & PM_read_write


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasAVX ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && N -> getOpcode ( )

== <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ;


<s> if ( hasModifiersSet ( * UseMI , <STR_LIT> :: src0_modifiers ) || hasModifiersSet ( * UseMI , <STR_LIT> :: src1_modifiers ) || hasModifiersSet ( * UseMI , <STR_LIT> :: src2_modifiers ) ) { return false ; } MachineOperand * Src0 = getNamedOperand ( * UseMI , <STR_LIT> :: src0 ) ; MachineOperand * Src1 = getNamedOperand ( * UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( * UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; unsigned Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI ->


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveCpsetup ( unsigned RegNo , int RegOrOffset , const MCSymbol & Sym , bool IsReg ) { if ( ! Pic || ! ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return ; MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCInst Inst ; if ( IsReg ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegOrOffset ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg (


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = <NUM_LIT> , unsigned Align = <NUM_LIT> , MachineMemOperand :: Flags Flags = MachineMemOperand

:: MONone , bool * Fast = nullptr ) const {


<s> if ( Vec . empty ( ) ) { unsigned MaxNumParts = <NUM_LIT> / Size ; Vec . resize ( MaxNumParts ) ; } Vec [ Pos ] = Idx ; } } ; static llvm :: once_flag InitializeSubRegFromChannelTableFlag ; static auto InitializeSubRegFromChannelTableOnce = [ this ] ( ) { for ( auto & Row : SubRegFromChannelTable ) Row . fill ( <STR_LIT> ) ; for ( uint16_t Idx = <NUM_LIT> ; Idx < getNumSubRegIndices ( ) ; ++ Idx ) { unsigned Width = <ISA_LIT>SubRegIdxRanges [ Idx ] . Size / <NUM_LIT> ; unsigned Offset = <ISA_LIT>SubRegIdxRanges [ Idx ] . Offset / <NUM_LIT> ; assert ( Width < SubRegFromChannelTableWidthMap . size ( ) ) ; Width = SubRegFromChannelTableWidthMap [ Width ] ; if ( Width == <NUM_LIT> ) continue ; unsigned TableIdx = Width - <NUM_LIT> ; assert ( TableIdx < SubRegFromChannelTable . size ( ) ) ; assert ( Offset < SubRegFromChannelTable [ TableIdx


<s> unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue


<s> if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return Opc ; if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? Opcodes . SEXT8 : Opcodes


<s> Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; if ( MFI . hasCalls ( ) ) { unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } else { unsigned PrivateSegmentWaveByteOffsetReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchWaveOffsetReg ( PrivateSegmentWaveByteOffsetReg ) ; } } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; Info . setScratchWaveOffsetReg


<s> RDA = & getAnalysis < ReachingDefAnalysis > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n' ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= InsertVPTBlocks ( MBB ) ; LLVM_DEBUG ( dbgs ( ) <<


<s> if ( JTInDiffSection ) { MCSection * ReadOnlySec = TLOF . getSectionForJumpTable ( F , TM ) ; OutStreamer -> SwitchSection ( ReadOnlySec ) ; } auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( unsigned JTI = <NUM_LIT> , e = JT . size ( ) ; JTI != e ; ++ JTI ) { const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; if ( JTBBs . empty ( ) ) continue ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; emitAlignment ( Align ( Size ) ) ; OutStreamer -> emitLabel ( GetJTISymbol ( JTI ) ) ; for ( auto * JTBB : JTBBs ) emitJumpTableEntry ( MJTI , JTBB


<s> void adds11_2ExtOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst ,


<s> bool isMachineBasicBlock ( ) const { return Kind ==


<s> MVT PredTy = ty ( PredV ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; if ( Subtarget . isHVXVectorType ( PredTy , true ) ) { SDValue T = DAG . getNode ( <STR_LIT> , dl , ByteTy , PredV ) ; SmallVector < int , <NUM_LIT> > Mask ( HwLen ) ; unsigned Scale = HwLen / ( PredTy . getVectorNumElements ( ) * BitBytes ) ; unsigned BlockLen = PredTy . getVectorNumElements ( ) * BitBytes ; for ( unsigned i = <NUM_LIT> ; i != HwLen ; ++ i ) { unsigned Num = i % Scale ; unsigned Off = i / Scale ; Mask [ BlockLen * Num + Off ] = i ; } SDValue S = DAG . getVectorShuffle ( ByteTy , dl , T , DAG . getUNDEF ( ByteTy ) , Mask ) ; if ( ! ZeroFill ) return S ; MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue Q = getNode ( <STR_LIT> , dl , BoolTy , { DAG . getConstant ( BlockLen , dl , <STR_LIT> ) } , DAG ) ; SDValue M = DAG . getNode ( <STR_LIT> , dl , ByteTy , Q ) ; return DAG . getNode ( <STR_LIT> , dl , ByteTy , S , M ) ; } assert ( PredTy == <STR_LIT> || PredTy == <STR_LIT> || PredTy == <STR_LIT> ) ; unsigned Bytes = <NUM_LIT> / PredTy . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Words [ <NUM_LIT> ] ; unsigned IdxW = <NUM_LIT> ; auto Lo32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; auto Hi32 = [ & DAG , & dl ] ( SDValue P ) { return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , P ) ; } ; SDValue W0 = isUndef ( PredV ) ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PredV ) ; Words [ IdxW ] . push_back ( Hi32 ( W0 ) ) ; Words [ IdxW ] . push_back ( Lo32 ( W0 ) ) ; while ( Bytes < BitBytes ) { IdxW ^= <NUM_LIT> ; Words [ IdxW ] . clear ( ) ; if ( Bytes < <NUM_LIT> ) { for ( const SDValue & W : Words [ IdxW ^ <NUM_LIT> ] ) { SDValue T = expandPredicate ( W , dl , DAG ) ; Words [ IdxW ] . push_back ( Hi32 ( T ) ) ; Words [ IdxW ] . push_back ( Lo32 ( T ) ) ; } } else


<s> SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; isTailCall = false


<s> if ( VT == <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Mask ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; else Tmp0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp0 ) ; if ( SrcVT == <STR_LIT> ) { Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) ; if ( VT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else if ( VT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Tmp0 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) ; SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue MaskNot = DAG . getNode ( <STR_LIT> , dl , OpVT , Mask , DAG . getNode ( <STR_LIT> , dl , OpVT , AllOnes ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 , Mask ) , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 , MaskNot ) ) ; if ( VT == <STR_LIT> ) { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } return


<s> SlotIndex PairedIndex = LIS -> getInstructionIndex ( * Paired ) ; LiveRange & M0Range = LIS -> getRegUnit ( * MCRegUnitIterator ( <STR_LIT> , TRI ) ) ; LiveRange :: Segment * M0Segment = M0Range . getSegmentContaining ( PairedIndex ) ; bool UpdateM0Range = M0Segment -> end == PairedIndex . getRegSlot ( ) ; MachineInstrBuilder Write2 = BuildMI ( * MBB , I , DL , Write2Desc ) . addOperand ( * Addr ) . addOperand ( * Data0 ) . addOperand ( * Data1 ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . addMemOperand ( * I -> memoperands_begin ( ) ) . addMemOperand ( * Paired -> memoperands_begin ( ) ) ; unsigned OrigRegs [ ] = { Data0 -> getReg ( ) , Data1 -> getReg ( ) , Addr -> getReg ( ) } ; LIS -> RemoveMachineInstrFromMaps ( * I ) ; LIS -> RemoveMachineInstrFromMaps ( * Paired ) ; I -> eraseFromParent ( ) ; Paired -> eraseFromParent ( ) ; LIS -> repairIntervalsInRange ( MBB , Write2 , Write2 , OrigRegs ) ; if ( UpdateM0Range ) { SlotIndex Write2Index = LIS -> getInstructionIndex ( * Write2 ) ; M0Segment -> end = Write2Index . getRegSlot ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << * Write2 << '\n' ) ; return Write2 . getInstr (


<s> void LLVMInitialize<ISA_LIT>MCInstrInfo (


<s> addPass ( create<ISA_LIT>CopyToCombine ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; addPass ( create<ISA_LIT>SplitConst32AndConst64 ( )


<s> return ( ( CC == CallingConv :: <ISA_LIT>_INTR || CC == CallingConv :: <ISA_LIT>_SIGNAL ) ? CSR_Interrupts_RegMask :


<s> PM . add ( createBasicAliasAnalysisPass ( ) ) ; if ( ! DisableVerify ) PM . add ( createVerifierPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { PM . add ( createLoopStrengthReducePass ( getTargetLowering ( ) ) ) ; } PM . add ( createGCLoweringPass ( ) ) ; PM . add ( createUnreachableBlockEliminationPass ( ) ) ; PM . add ( createLowerInvokePass ( getTargetLowering ( ) ) ) ; PM . add ( createUnreachableBlockEliminationPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) PM . add ( createCodeGenPreparePass ( getTargetLowering ( ) ) ) ; PM . add ( createStackProtectorPass ( getTargetLowering ( ) ) ) ; addPreISel ( PM ) ; if ( ! DisableVerify ) PM . add ( createVerifierPass ( ) ) ; MachineModuleInfo * MMI = new MachineModuleInfo ( * getMCAsmInfo ( ) , * getRegisterInfo ( ) , & getTargetLowering ( ) -> getObjFileLowering ( ) ) ; PM . add ( MMI ) ; OutContext = & MMI -> getContext ( ) ; PM . add ( new MachineFunctionAnalysis ( * this ) ) ; if ( addInstSelector ( PM ) ) return true ; printAndVerify ( PM , <STR_LIT> ) ; PM . add ( createExpandISelPseudosPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { PM . add ( createTailDuplicatePass ( true ) ) ; printAndVerify ( PM , <STR_LIT> ) ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) PM . add ( createOptimizePHIsPass ( ) ) ; PM . add ( createLocalStackSlotAllocationPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { PM . add ( createDeadMachineInstructionElimPass ( ) ) ; printAndVerify ( PM , <STR_LIT> ) ; PM . add ( createMachineLICMPass ( ) ) ; PM . add ( createMachineCSEPass ( ) ) ; PM . add ( createMachineSinkingPass ( ) ) ; printAndVerify ( PM , <STR_LIT> ) ; PM . add ( createPeepholeOptimizerPass ( ) ) ; printAndVerify ( PM , <STR_LIT> ) ; } if ( addPreRegAlloc ( PM ) ) printAndVerify ( PM , <STR_LIT> ) ; PM . add ( create<ISA_LIT>RegisterAllocator ( ) ) ; printAndVerify ( PM , <STR_LIT> ) ; if ( getOptLevel ( ) != CodeGenOpt ::


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false


<s> if ( ! sparc_got_symbol ) sparc_got_symbol = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; return


<s> BasicBlock * Latch = L -> getLoopLatch ( ) ; for ( Instruction & I : reverse ( * Latch ) ) { if ( I . getOpcode ( ) != Instruction :: Add ) continue ; if ( AllAdds . count ( & I ) ) continue ; const auto * Ty = I . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; Reduction R ( & I ) ; if ( ! Search ( & I , R ) ) continue ; if ( ! CreateParallelPairs ( R ) ) continue ; InsertParallelMACs ( R ) ; Changed = true ; AllAdds . insert ( R . getAdds ( ) . begin ( ) , R . getAdds ( ) . end ( ) ) ; } return Changed


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! hasFP ( MF ) ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) { I -> addLiveIn ( <STR_LIT> ) ; } if ( ! FrameSize )


<s> Lexer . Lex ( ) ; } SMLoc RegLoc = Lexer . getLoc ( ) ; if ( ParseRegister ( Operands ) ) { return true ; } if ( checkClass ) { <ISA_LIT>Operand * Op = ( <ISA_LIT>Operand * ) Operands . back ( ) ; if ( ! Op -> isReg ( ) ) return Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; if ( <ISA_LIT>InstPrinter :: getRegisterName ( Op -> getReg ( ) ) [ <NUM_LIT> ] != 'p' ) { if ( flag ) { Error ( StartLoc , <STR_LIT> ) ; } return false


<s> for ( unsigned Reg : { RegA , RegB } ) { if ( RI . isSubRegisterEq ( <STR_LIT> , Reg ) ) DE = true ; else if ( RI . isSubRegisterEq ( <STR_LIT> , Reg


<s> static unsigned int msp430_function_arg_boundary ( machine_mode mode , const_tree type ) { if ( mode == BLKmode && int_size_in_bytes ( type ) > <NUM_LIT> ) return <NUM_LIT> ; if ( GET_MODE_BITSIZE ( mode )


<s> Pass * llvm :: createMVETailPredicationPass ( ) { return new MVETailPredication (


<s> rtx s390_function_value ( tree type , enum machine_mode mode ) { if ( type ) { int unsignedp = TYPE_UNSIGNED ( type ) ; mode = promote_mode ( type , TYPE_MODE ( type ) , & unsignedp , <NUM_LIT> ) ; } gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ; if ( TARGET_HARD_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return gen_rtx_REG ( mode , <NUM_LIT> ) ; else return gen_rtx_REG ( mode


<s> unsigned M0 = MRI . createVirtualRegister ( & AMDGPU :: M0RegRegClass ) ; BuildMI ( BB , I , BB . findDebugLoc ( I ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , M0 ) . addOperand ( params ) ; BuildMI ( BB , I , BB . findDebugLoc ( I ) , TII -> get ( AMDGPU :: V_INTERP_MOV_F32 ) ) . addOperand ( dst ) . addOperand ( attr_chan ) . addOperand ( attr ) . addReg ( M0 ) ; MI -> eraseFromParent


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) || df_regs_ever_live_p ( LR_REGNUM


<s> SDValue <ISA_LIT>TargetLowering :: get<ISA_LIT>Cmp ( SDValue LHS , SDValue RHS , <STR_LIT> CC , SDValue & <ISA_LIT>cc , SelectionDAG & DAG , const SDLoc & dl ) const { if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS . getNode ( ) ) ) { unsigned C = RHSC -> getZExtValue ( ) ; if ( ! isLegalICmpImmediate ( ( int32_t ) C ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; } } } else if ( ( <STR_LIT> ( LHS . getOpcode ( ) ) != <STR_LIT> ) && ( <STR_LIT> ( RHS . getOpcode ( ) ) == <STR_LIT> ) ) { CC = <STR_LIT> (


<s> uf = <NUM_LIT> << ceil_log2 ( uf ) ; if ( LOOP_VINFO_NITERS_KNOWN_P ( loop_vinfo ) ) return uf ; if ( reduc_factor > ( unsigned int ) rs6000_vect_unroll_reduc_threshold || m_gather_load ) return uf ; HOST_WIDE_INT est_niter = get_estimated_loop_iterations_int ( loop ) ; unsigned int vf = vect_vf_for_cost ( loop_vinfo ) ; unsigned int unrolled_vf = vf * uf ; if ( est_niter == - <NUM_LIT> || est_niter < unrolled_vf ) return <NUM_LIT> ; else { unsigned int epil_niter_unr = est_niter % unrolled_vf ; unsigned int epil_niter = est_niter % vf ; if ( LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P ( loop_vinfo ) && epil_niter_unr <= vf ) return


<s> bool isMemDisp12Len4 ( RegisterKind RegKind ) const { return isMemDisp12 ( BDLMem , RegKind ) && inRange ( Mem . Length . Imm , <NUM_LIT>


<s> TargetLoweringObjectFile * getObjFileLowering ( )


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned FP = <STR_LIT> ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( )

) <ISA_LIT>FI -> createEhDataRegsFI ( ) ;


<s> if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . hasMuxedUnits ( ) && LastMI -> mayLoadOrStore ( ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = std :: prev ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII . getRegisterInfo ( ) ) ) ) { if ( FpMLxStalls == <NUM_LIT> ) FpMLxStalls = <NUM_LIT> ; return Hazard


<s> return ( getGeneration ( ) >= SOUTHERN_ISLANDS || hasCaymanISA


<s> const <ISA_LIT>Subtarget * STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified


<s> if ( P . isValid ( ) ) dbgs ( ) << DAG -> TRI -> getRegPressureSetName ( P . getPSet ( ) ) << <STR_LIT> << P . getUnitInc ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ; DAG -> dumpNode ( *


<s> op = ro ; } else { rtx tem , mem , rm , ro ; gcc_assert ( ! no_new_pseudos ) ; current_function_uses_pic_offset_table = <NUM_LIT> ; tem = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , op ) , CRIS_UNSPEC_PLTGOTREAD ) ; rm = gen_reg_rtx ( Pmode ) ; emit_move_insn ( rm , gen_rtx_CONST ( Pmode , tem ) ) ; ro = gen_reg_rtx ( Pmode ) ; if ( expand_binop ( Pmode , add_optab , rm , pic_offset_table_rtx , ro , <NUM_LIT> , OPTAB_LIB_WIDEN ) != ro ) internal_error ( <STR_LIT> ) ; mem = gen_rtx_MEM ( Pmode ,


<s> return __builtin_loongson_pandn_ud ( s , t


<s> void <ISA_LIT>StaticStackAlloc :: getAnalysisUsage (


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> )

. Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> <ISA_LIT>TargetStreamer & <ISA_LIT>AsmPrinter :: getTargetStreamer ( ) { return static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer . getTargetStreamer ( )


<s> int64_t Size ; if ( getParser ( ) . parseAbsoluteExpression ( Size ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) . Lex ( ) ; getStreamer ( ) . EmitWinCFIAllocStack ( Size , Loc ) ; return false


<s> const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; { auto Op = MI . getOpcode ( ) ; if ( Op == <STR_LIT> || Op == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; } if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; const MCInstrDesc & Desc = MI . getDesc ( ) ; switch ( Desc . getOpcode ( ) ) { default : NumBytes = <NUM_LIT> ; break ; case TargetOpcode :: STACKMAP : NumBytes = StackMapOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case TargetOpcode :: PATCHPOINT : NumBytes = PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case


<s> bool <ISA_LIT>AsmParser :: parseDirectiveGpDWord ( ) { const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitGPRel64Value


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; assert ( CstVal && <STR_LIT>


<s> assert ( NumSystemSGPRs == <NUM_LIT> &&


<s> bool isGP64 ( ) const { return STI . getFeatureBits (


<s> const std :: vector < <ISA_LIT>Section * > & getROSections (


<s> Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> || SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> , true ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> || SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) || ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( DisableCTRLoopAnal ) return


<s> bool <ISA_LIT>BaseInstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( isCondBranchOpcode ( SecondLastOpc )


<s> return true ; } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { uint32_t Imm = CN -> getZExtValue ( ) ; Disp = CurDAG -> getTargetConstant ( Imm , CN -> getValueType ( <NUM_LIT> ) ) ; Base = CurDAG -> getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; return true ; } Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , TM . getTargetLowering ( ) -> getPointerTy ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) Base = CurDAG -> getTargetFrameIndex (

FI -> getIndex ( ) , N . getValueType ( ) ) ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> ,


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return


<s> MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( I ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const TargetRegisterClass * RC = TII -> getRegClass ( Desc , I , TRI , MF ) ; unsigned NewReg ; if ( RC == nullptr ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } DEBUG ( dbgs ( )


<s> return llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit , CPUType


<s> dbgs ( ) << format ( <STR_LIT> , MBB . getNumber ( ) , BBI . Offset ) <<


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast <


<s> return ( __m128 ) __builtin_ia32_sqrtss ( ( __v4sf


<s> if ( ! UCB_FORCED_STOP_FN ( ucbp ) ) return __gnu_Unwind_RaiseException ( ucbp , entry_vrs ) ; entry_vrs -> core . r [ R_PC ] = entry_vrs -> core . r [ R_LR ] ; return unwind_phase2_forced ( ucbp , entry_vrs


<s> void FPS :: handleCall ( MachineBasicBlock :: iterator & I ) { MachineInstr & MI = * I ; unsigned STReturns = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isImplicit ( ) && <STR_LIT> ) ; if ( Op . isDef ( ) ) STReturns |= <NUM_LIT> << getFPReg ( Op ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <=


<s> GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ; <ISA_LIT>RegBankCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , LI , KB


<s> OpRef L = vmuxs ( Bytes . take_front ( S ) , OpRef :: lo ( Va ) , OpRef :: lo ( Vb ) , Results ) ; OpRef H = vmuxs ( Bytes . drop_front ( S ) , OpRef :: hi ( Va ) , OpRef :: hi ( Vb ) , Results ) ; return concats ( L , H


<s> llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : switch ( DestDataWidth ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : OpCode = VectorPredicate ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : OpCode = VectorPredicate ? <STR_LIT> : <STR_LIT> ; break ; } break ; case <NUM_LIT> : switch ( DestDataWidth ) { default : llvm_unreachable ( <STR_LIT>


<s> static DecodeStatus DecodeShiftRight64Imm ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler


<s> std :: string Ret = <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; return Ret


<s> rtx reg = gen_rtx_REG ( V4SImode , regno ) ; rtx mem = gen_frame_mem ( V4SImode , gen_rtx_PLUS ( Pmode , addr ,


<s> static void pa_som_asm_init_sections ( void ) { text_section = get_unnamed_section ( <NUM_LIT> , som_output_text_section_asm_op , NULL ) ; som_readonly_data_section = get_unnamed_section ( <NUM_LIT> ,


<s> mips_va_start ( valist , nextarg ) { \ if ( TARGET_MIPS16 ) \ sorry ( <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> , \ reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; \ if ( ! TARGET_NEWABI ) \ { \ fprintf ( FILE

, \ <STR_LIT> , \ TARGET_64BIT ? <STR_LIT> : <STR_LIT> , \ reg_names [ STACK_POINTER_REGNUM ] , \ reg_names [ STACK_POINTER_REGNUM ] , \ Pmode == DImode ? <NUM_LIT> : <NUM_LIT> ) ; \ } \ fprintf ( FILE , <STR_LIT> ) ; \ fprintf ( FILE , <STR_LIT> ) ; \ }


<s> rtx operand = x ; switch ( code ) { case <NUM_LIT> : break ; case 'h' : if ( GET_CODE ( operand ) != REG ) internal_error ( <STR_LIT> ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( operand ) + <NUM_LIT> ] ) ; return ; case 'm' : fprintf ( file , <STR_LIT> , ( long ) ( - INTVAL ( x ) ) ) ; return ; case 'd' : { int i = INTVAL ( x ) ; char dwspec ; switch ( i ) { case <NUM_LIT> : dwspec = 'b' ; break ; case <NUM_LIT> : dwspec = 's' ; break ; case <NUM_LIT> : dwspec = 'l' ; break ; default : if ( ( i % <NUM_LIT> ) != <NUM_LIT> ) internal_error ( <STR_LIT> , i ) ; else dwspec = 'l' ; break ; } fprintf ( file , <STR_LIT> , dwspec ) ; return ; } case 'f' : { int bf = ft32_as_bitfield ( INTVAL ( x ) ) ; fprintf ( file , <STR_LIT> , bf >> <NUM_LIT> , bf & <NUM_LIT> ) ; return ; } case 'g' : { int bf = ft32_as_bitfield ( <NUM_LIT> ^ INTVAL ( x ) ) ; fprintf ( file , <STR_LIT> , bf >> <NUM_LIT> , bf & <NUM_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT>


<s> unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] =


<s> bool <ISA_LIT>InstructionSelector :: selectG_CONSTANT ( MachineInstr & I ) const { MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineOperand & ImmOp = I . getOperand ( <NUM_LIT> ) ; if ( ImmOp . isFPImm ( ) ) { const APInt & Imm = ImmOp . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) ; ImmOp . ChangeToImmediate ( Imm . getZExtValue ( ) ) ; } else if ( ImmOp . isCImm ( ) ) { ImmOp . ChangeToImmediate ( ImmOp . getCImm ( ) -> getZExtValue ( ) ) ; } unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size ; bool IsSgpr ; const RegisterBank * RB = MRI . getRegBankOrNull ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( RB ) { IsSgpr = RB -> getID ( ) == <STR_LIT> ; Size = MRI . getType ( DstReg ) . getSizeInBits ( ) ; } else { const TargetRegisterClass * RC = TRI . getRegClassForReg ( MRI , DstReg ) ; IsSgpr = TRI . isSGPRClass ( RC ) ; Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } DebugLoc DL = I . getDebugLoc ( ) ; const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; unsigned LoReg = MRI . createVirtualRegister ( RC ) ; unsigned HiReg = MRI . createVirtualRegister ( RC ) ; const APInt & Imm = APInt ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; const MachineInstr * RS = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; I . eraseFromParent ( ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand (

RS -> getOperand ( <NUM_LIT> ) , MRI ) ;


<s> ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( ) . getOperandNo ( ) ; User = * User -> use_begin ( ) ; } if ( User -> getOpcode ( ) != <STR_LIT> && User -> getOpcode ( ) != <STR_LIT> && ! ( User

-> getOpcode ( ) == <STR_LIT> && UOpNo == <NUM_LIT> ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: addLatencyToSchedule ( const MachineInstr & MI1 , const


<s> static void init_idents ( void ) { if ( small_ident1 == <NUM_LIT> ) { small_ident1 = get_identifier (


<s> continue ; } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count


<s> void <ISA_LIT>ELFStreamer :: EmitPersonality ( const MCSymbol * Per ) { Personality = Per


<s> void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const


<s> NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> emitBytes ( <STR_LIT> ) ; emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; OutStreamer -> emitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL , <NUM_LIT> ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; OpCode = convertTailJumpOpcode ( OpCode ) ; MCInst TC ; TC . setOpcode ( OpCode ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI ,

MO ) ) TC . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( L , <STR_LIT> ) ; StringRef Mode = Tok . getString ( ) ; if ( Mode == <STR_LIT> || Mode == <STR_LIT> ) Parser . Lex ( ) ; else if ( Mode == <STR_LIT> || Mode == <STR_LIT> ) return Error ( L , <STR_LIT> ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { const Function & F = * L -> getHeader ( ) -> getParent ( ) ; UP . Threshold = <STR_LIT> ( F , <STR_LIT> , <NUM_LIT> ) ; UP . MaxCount = std :: numeric_limits < unsigned > :: max ( ) ; UP . Partial = true ; const unsigned MaxAlloca = ( <NUM_LIT> - <NUM_LIT> ) * <NUM_LIT> ; unsigned ThresholdPrivate = UnrollThresholdPrivate ; unsigned ThresholdLocal = UnrollThresholdLocal ; unsigned MaxBoost = std :: max ( ThresholdPrivate , ThresholdLocal ) ; for ( const BasicBlock * BB : L -> getBlocks ( ) ) { const DataLayout & DL = BB -> getModule ( ) -> getDataLayout ( ) ; unsigned LocalGEPsSeen = <NUM_LIT> ; if ( llvm :: any_of ( L -> getSubLoops ( ) , [ BB ] ( const Loop * SubLoop ) { return SubLoop -> contains ( BB ) ; } ) ) continue ; for ( const Instruction & I : * BB ) { if ( const BranchInst * Br = dyn_cast < BranchInst > ( & I ) ) { if ( UP . Threshold < MaxBoost && Br -> isConditional ( ) ) { BasicBlock * Succ0 = Br -> getSuccessor ( <NUM_LIT> ) ; BasicBlock * Succ1 = Br -> getSuccessor ( <NUM_LIT> ) ; if ( ( L -> contains ( Succ0 ) && L -> isLoopExiting ( Succ0 ) ) || ( L -> contains ( Succ1 ) && L -> isLoopExiting ( Succ1 ) ) ) continue ; if ( dependsOnLocalPhi ( L , Br -> getCondition ( ) ) ) { UP . Threshold += UnrollThresholdIf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << UP . Threshold << <STR_LIT> << * L << <STR_LIT> << * Br << '\n' ) ; if ( UP . Threshold >= MaxBoost ) return ; } } continue ; } const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP ) continue ; unsigned AS = GEP -> getAddressSpace ( ) ; unsigned Threshold = <NUM_LIT> ; if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) Threshold = ThresholdPrivate ; else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) Threshold = ThresholdLocal ; else continue ; if ( UP . Threshold >= Threshold ) continue ; if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > (


<s> int <ISA_LIT>MCInstrInfo :: getMaxValue ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; bool S = ( F >> <STR_LIT> ) & <STR_LIT> ; assert ( <ISA_LIT>MCInstrInfo :: isExtendable ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isExtended ( MCII , MCI ) ) ; if ( S ) return ( <NUM_LIT> << ( <ISA_LIT>MCInstrInfo :: getExtentBits ( MCII , MCI ) - <NUM_LIT> ) ) - <NUM_LIT> ; return ( <NUM_LIT> << <ISA_LIT>MCInstrInfo :: getExtentBits ( MCII , MCI ) ) -


<s> return getTM < <ISA_LIT>65816TargetMachine > (


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) { if ( Size == <NUM_LIT> ) return & <STR_LIT> ; else if ( Size == <NUM_LIT> ) return


<s> SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; if ( CCOpcode == <STR_LIT> && isCtlzOpc ( RHS . getOpcode ( ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { return getFFBH_U32 ( DAG , CmpLHS , SL ) ; } if ( CCOpcode == <STR_LIT> && isCtlzOpc ( LHS . getOpcode ( ) ) && LHS . getOperand ( <NUM_LIT>

) == CmpLHS && isNegativeOne ( RHS ) ) {


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int fi , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc dl = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( fi ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( fi ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( fi ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( fi ) ; else llvm_unreachable ( <STR_LIT> )


<s> SmallVector < const User * , <NUM_LIT> > worklist ; worklist . append ( GV -> user_begin ( ) , GV -> user_end ( ) ) ; while ( ! worklist . empty ( ) ) { const User * user = worklist . pop_back_val ( ) ; if ( const GlobalValue * GUser = dyn_cast <


<s> OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } else if ( GVar && ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == <STR_LIT> ) { const IntegerType * IntTy = dyn_cast < IntegerType > ( GVar -> getValueType ( ) ) ; assert ( IntTy ) ; if ( IntTy -> getBitWidth ( ) == <NUM_LIT>


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; const unsigned NumFields = <NUM_LIT> ; SDValue Fields [ NumFields ] = { DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , DL , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , DL , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo


<s> * _TEXASR_PTR ( TM_buff ) = __builtin_get_texasr ( ) ; * _TEXASRU_PTR ( TM_buff ) = __builtin_get_texasru ( ) ; * _TEXASRL_PTR ( TM_buff ) = __builtin_get_texasr


<s> SDValue LoadFuncPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , Callee , MPI , <NUM_LIT> , MMOFlags ) ; SDValue TOCOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , TOCOff ) ; SDValue TOCPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddTOC , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddPtr , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , Glue ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; Glue = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , Glue ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; Glue = EnvVal . getValue (


<s> unsigned StackAlignment = TFI . getStackAlignment ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> :


<s> SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , dl , <STR_LIT> ) } ; EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; } Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> - ( <NUM_LIT> - BitNo ) , dl , <STR_LIT> ) ) ; Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( InvertBit ) Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flags , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return Flags


<s> SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return CombineFMinMaxLegacy ( DL , VT , LHS , RHS , True , False , CC , DCI ) ; if ( VT == <STR_LIT> && Subtarget -> getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { return CombineIMinMax ( DL , VT , LHS , RHS , True , False , CC , DAG ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr

, DAG . getIntPtrConstant ( Offset , DL ) ) ;


<s> Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RTLIB :: Libcall LC = ( ArgVT == <STR_LIT> ) ? RTLIB :: SINCOS_F64 : RTLIB :: SINCOS_F32 ; CallingConv :: ID CC = getLibcallCallingConv ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CC , RetTy , Callee , std :: move ( Args ) ) . setDiscardResult ( ShouldUseSRet ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; if ( ! ShouldUseSRet ) return CallResult . first ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( )


<s> static DecodeStatus decodeU3ImmOperand ( MCInst & Inst , uint64_t Imm ,

uint64_t Address , const void * Decoder ) {


<s> void <ISA_LIT>DAGToDAGISel :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < <ISA_LIT>ArgumentUsageInfo


<s> switch ( c ) { case 'Q' : return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == POST_INC && XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == stack_pointer_rtx ) ; case 'R' : return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PRE_DEC && XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) == stack_pointer_rtx ) ; case 'S' : return ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && xstormy16_legitimate_address_p ( VOIDmode , XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; case 'T' : return <NUM_LIT> ; case 'U'


<s> if ( <STR_LIT> ( Paired . I -> getOpcode ( ) , op ) != Idx ) return false ; if ( Idx != - <NUM_LIT> && CI . I -> getOperand ( Idx ) . getImm ( ) != Paired . I -> getOperand ( Idx ) . getImm ( ) ) return false ; } unsigned MaxMask = std :: max ( CI . DMask , Paired . DMask ) ; unsigned MinMask = std :: min ( CI . DMask , Paired . DMask ) ; unsigned AllowedBitsForMin = llvm ::


<s> return create<ISA_LIT>ELFStreamer ( Ctx , std :: move ( TAB ) , OS , std ::


<s> <ISA_LIT>MCExpr :: VariantKind Kind = ( <ISA_LIT>MCExpr :: VariantKind ) MO . getTargetFlags ( ) ; const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol


<s> if ( Depth ) { report_fatal_error ( <STR_LIT> + DAG . getMachineFunction ( ) . getName ( ) ) ; } SDValue RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , VT ) ; return RetAddr


<s> CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) ) { CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) )

CanAcceptPredicationCode = Mnemonic != <STR_LIT> ;


<s> void rs6000_asm_output_dwarf_datarel ( FILE * file , int size , const


<s> void GCNPassConfig :: addFastRegAlloc ( ) { insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID


<s> SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = <STR_LIT> ; if ( N1 . getValueType ( ) . bitsGT ( ShiftVT ) ) N1Opc = <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT>


<s> SelectRoot ( * CurDAG ) ; CurDAG -> RemoveDeadNodes


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned VARegSaveSize = AFI -> getVarArgsRegSaveSize ( ) ; unsigned NumBytes = MFI -> getStackSize ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> )


<s> void <ISA_LIT>DAGToDAGISel :: SelectConstantFP ( SDNode * N ) { SDLoc dl ( N ) ; auto * CN = cast < ConstantFPSDNode > ( N ) ; APInt A = CN -> getValueAPF ( ) . bitcastToAPInt ( ) ; if ( N -> getValueType ( <NUM_LIT> ) ==


<s> void <ISA_LIT>FrameLowering :: layoutStackRegions ( MachineFunction & MF ) const { const SmallVectorImpl < StackRegion * > & StackRegions = MF . getFrameInfo ( ) -> getStackRegions ( ) ; assert ( StackRegions . size ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; SVEVecStackRegion * Pred = static_cast < SVEVecStackRegion * > ( StackRegions [ <NUM_LIT> ] ) ; SVEVecStackRegion * Vec = static_cast < SVEVecStackRegion * > ( StackRegions [ <NUM_LIT> ] ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; bool HasFP = TFI -> hasFP ( MF ) ; uint64_t Offset = HasFP ? <NUM_LIT> : <NUM_LIT> ; Offset = Pred -> layoutRegion ( MF , Offset , <NUM_LIT> ) ; if ( HasFP && ( Pred -> getRegionSize ( ) > <NUM_LIT> ) ) { Pred -> setRegionSize ( Pred -> getRegionSize


<s> const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = MEMORY_IMM ; Op -> Mem . BaseReg = <NUM_LIT> ; Op -> Mem . AluOp = LPAC :: ADD ; Op -> Mem . OffsetReg = <NUM_LIT> ; Op -> Mem . Offset =


<s> uint64_t ArgOffset = alignTo ( MFI -> getExplicitKernArgSize ( ) , Alignment ) + ExplicitArgOffset ; switch ( Param ) { case GRID_DIM : return ArgOffset ; case GRID_OFFSET : return ArgOffset +


<s> virtual const char * getPassName ( ) const { return


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool

isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> bool PBlock = false ; PBlock |= Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( isYMMLoadOpcode ( LoadOpcode ) ) PBlock |= Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS ,


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; InstrumentMOVSBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , AccessSize , Ctx , Out ) ; EmitLabel ( Out , DoneSym


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return


<s> unsigned UnusedCarry = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MRI . setRegAllocationHint ( UnusedCarry , <NUM_LIT> , RI . getVCC ( ) ) ; return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg

( UnusedCarry , RegState :: Define | RegState :: Dead ) ;


( unsigned long int _1 , unsigned int _2 ) {


<s> case TYPE_DMAC : case TYPE_DALUROUND : case TYPE_DBPICK : case TYPE_DWEXT : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; return ( gw_consumed_by_ex_dep_p ( consumer , def_reg1 ) || gw_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable (


<s> bool IsSmallMemAccess ( unsigned AccessSize ) { return AccessSize


<s> if ( <STR_LIT> ( AsmParser -> getMII ( ) -> get ( Inst . getOpcode ( ) ) , Inst . getNumOperands ( ) ) ) { addLiteralImmOperand ( Inst , Imm . Val , ApplyModifiers & isImmTy ( ImmTyNone ) && Imm . Mods . hasFPModifiers ( ) ) ; } else { assert ( ! isImmTy ( ImmTyNone ) || ! hasModifiers (


<s> unsigned TyAlign = DL . getABITypeAlignment ( Ty ) ; if ( TyAlign > <NUM_LIT> ) return TyAlign ; return <NUM_LIT> ; } unsigned Align = <NUM_LIT> ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty


<s> inline bool isImmSExti64i8Value ( uint64_t


<s> if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ; return false


<s> if ( Classification == Skip ) { ++ I ; continue ; } if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ; assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ; if ( StackDisp % <NUM_LIT> ) return ; StackDisp /= <NUM_LIT> ; assert ( ( size_t ) StackDisp < Context . MovVector . size ( ) && <STR_LIT> ) ; if ( Context . MovVector [ StackDisp ] != nullptr ) return ; Context . MovVector [ StackDisp ]


<s> __inline__ static unsigned long long sh_media_MSHFLO_W ( unsigned long long mm , unsigned long


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ,


<s> if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> || A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A ==


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( AddBuildAttributes ) getTargetStreamer ( ) . emitTargetAttributes ( STI ) ; ITState . CurPosition = ~ <NUM_LIT> ; NextSymbolIsThumb = false


<s> rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( reg_offset ) ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } } else if ( frame_pointer_needed ) { unsigned int reg_offset = var_size + args_size ; if ( reg_offset == <NUM_LIT> ) emit_insn ( gen_movsi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; else if ( reg_offset < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , frame_pointer_rtx , GEN_INT ( reg_offset ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( reg_offset ) ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } } else gcc_unreachable ( ) ; if ( current_frame_info . save_lr ) pop ( RETURN_ADDR_REGNUM ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK


<s> if ( parseSignature ( Signature . get ( ) ) ) return true ; WasmSym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; TOut . emitFunctionType ( WasmSym ) ; return expect ( AsmToken :: EndOfStatement , <STR_LIT> ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; if ( expect ( AsmToken :: Comma , <STR_LIT> ) ) return true ; auto ExportName = expectIdent ( ) ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; WasmSym -> setExportName ( storeName ( ExportName ) ) ; TOut . emitExportName ( WasmSym , ExportName ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; if ( expect ( AsmToken :: Comma , <STR_LIT> ) ) return true ; auto ImportModule = expectIdent ( ) ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; WasmSym -> setImportModule ( storeName ( ImportModule ) ) ; TOut . emitImportModule ( WasmSym , ImportModule ) ; } if ( DirectiveID . getString ( ) == <STR_LIT> ) { auto SymName = expectIdent ( ) ; if ( SymName . empty ( ) ) return true ; if ( expect ( AsmToken :: Comma , <STR_LIT> ) ) return true ; auto ImportName = expectIdent ( ) ; auto WasmSym = cast < MCSymbolWasm > ( Ctx . getOrCreateSymbol ( SymName ) ) ; WasmSym -> setImportName ( storeName ( ImportName )


<s> lm32_block_move_inline ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , INTVAL ( operands [ <NUM_LIT> ] ) , INTVAL ( operands [ <NUM_LIT> ] ) ) ; return


<s> return __builtin_mve_vorrq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) ,


<s> if ( isa < ConstantInt > ( V ) || isa < Argument > ( V ) ) return true ; if ( isa < StoreInst > ( V ) || isa < LoadInst > ( V ) || isa < GetElementPtrInst > ( V ) ) return true ; if ( auto * ICmp = dyn_cast < ICmpInst > ( V ) ) return ICmp -> isEquality ( ) || ! ICmp -> isSigned ( ) ; if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) ) return true ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; else if ( auto * Cast = dyn_cast < CastInst > ( V ) ) { if ( isa < ZExtInst > ( Cast ) ) return Cast -> getDestTy ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ; else if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return Trunc -> getDestTy ( ) -> getScalarSizeInBits ( ) <= TypeSize ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> case GT_S_I64 : Def -> setDesc ( TII . get ( LE_S_I64 ) ) ; Inverted = true ; break ; case GE_S_I64 : Def -> setDesc ( TII . get ( LT_S_I64 ) ) ; Inverted = true ; break ; case LT_S_I64 : Def -> setDesc ( TII . get ( GE_S_I64 ) ) ; Inverted = true ; break ; case LE_S_I64 : Def -> setDesc ( TII . get ( GT_S_I64 ) ) ; Inverted = true ; break ; case GT_U_I64 : Def -> setDesc ( TII . get ( LE_U_I64 ) ) ; Inverted = true ; break ; case GE_U_I64 : Def -> setDesc ( TII . get ( LT_U_I64 ) ) ; Inverted = true ; break ; case LT_U_I64 : Def -> setDesc ( TII . get ( GE_U_I64 ) ) ; Inverted = true ; break ; case LE_U_I64 : Def -> setDesc ( TII . get ( GT_U_I64 ) ) ; Inverted = true ; break ; case EQ_F32 : Def -> setDesc ( TII . get ( NE_F32 ) ) ; Inverted = true ; break ; case NE_F32 : Def -> setDesc ( TII . get ( EQ_F32 ) ) ; Inverted = true ; break ; case EQ_F64 : Def -> setDesc ( TII . get ( NE_F64 ) ) ; Inverted = true ; break ; case NE_F64 : Def -> setDesc ( TII . get ( EQ_F64 ) ) ; Inverted = true ; break ; default : break ; } } if ( ! Inverted ) { unsigned Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Tmp ) . addReg ( Cond ) ; MFI . stackifyVReg ( Tmp ) ; Cond = Tmp ; Inverted =


<s> APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op1 , Op1 . getScalarValueSizeInBits ( ) , UndefElts , EltBits , false , false ) ) if ( llvm :: all_of ( EltBits , [ ] ( APInt & I ) { return I . isSignMask ( ) ; } ) ) return peekThroughBitcasts ( Op . getOperand ( <NUM_LIT> ) ) ; return SDValue ( )


<s> struct machine_function * machine ; current_frame_info = zero_frame_info ; machine = ggc_cleared_alloc < machine_function_t > ( ) ; return


<s> assert ( MI . mayLoad ( ) ) ; return MI . getOperand


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O

, StringRef Annot , const MCSubtargetInfo & STI ) {


<s> return isUImm < <NUM_LIT> , <NUM_LIT>


<s> unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( MulOpc , SL , <STR_LIT> , N0 , N1 ) ; } unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Mul = DAG . getNode ( MulOpc , SL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N0 , N1 ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mul . getValue

( <NUM_LIT> ) , Mul . getValue ( <NUM_LIT> ) ) ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand * SrcVec = TII -> getNamedOperand ( MI , <STR_LIT> :: src ) ; int Offset = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) -> getImm ( ) ; unsigned Reg ; std :: tie ( Reg , Offset ) = computeIndirectRegAndOffset ( SrcVec -> getReg


<s> EVT CopyVT = VA . getLocVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget . hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { if ( ! Subtarget . hasX87 ( ) ) report_fatal_error ( <STR_LIT> ) ; CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg (

) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> || A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { return A ; } break ; case <NUM_LIT> : if ( B == & <STR_LIT> || B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT>


<s> if ( need_prefix == indirect_thunk_prefix_bnd ) { indirect_return_bnd_needed |= need_thunk ; fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; } else { indirect_return_needed |= need_thunk ; fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; } } else output_indirect_thunk ( need_prefix


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; MachineMemOperand * MMO = LD -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewLD ) ; SDValue Ops [ ] = { Result , SDValue ( NewLD . getNode ( ) , <NUM_LIT> ) } ; return DAG . getMergeValues (


<s> case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT>


<s> unsigned AS = GV -> getType ( ) -> getAddressSpace ( ) ; NameStr += getSymbolPrefixForAddressSpace ( AS ) ; } SmallString < <NUM_LIT> > Mangled ; SmallString < <NUM_LIT> > Sanitized ; getNameWithPrefix ( Mangled , GV ) ; NameStr += Mangled ; if ( <STR_LIT> ( Mangled , Sanitized ) ) NameStr +=


<s> } else base = XEXP ( ref , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PLUS ) disp = INTVAL ( XEXP ( base , <NUM_LIT> ) ) , base = XEXP ( base , <NUM_LIT> ) ; else disp = <NUM_LIT> ; if ( MEM_ALIGN ( ref ) >= <NUM_LIT> ) offset = <NUM_LIT> ; else offset = disp & <NUM_LIT> ; gcc_assert ( offset + GET_MODE_SIZE ( GET_MODE ( ref ) ) <= GET_MODE_SIZE ( SImode ) ) ; * paligned_mem = widen_memory_access ( ref , SImode , - offset ) ; offset *= BITS_PER_UNIT


<s> int LaneSize = Size / <NUM_LIT> ; bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ; unsigned PERMMask = <NUM_LIT> | <NUM_LIT> <<


<s> if ( M . getPICLevel ( ) == PICLevel :: Small ) return AsmPrinter :: EmitStartOfAsmFile ( M ) ; OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ) ; MCSymbol * TOCSym = OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; MCSymbol * CurrentPos = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel


<s> if ( NumNonZero > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( Op ) ; SDValue V ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool isNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( isNonZero ) { if ( First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First =


<s> unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = mips_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ; else if ( result ) si_op = generator . fn_5 ( res , memsi , mask , inverted_mask


<s> assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; unsigned Imm = <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] == - <NUM_LIT> ? <NUM_LIT>


<s> SDNode * N = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , elemType , reg , NIndex ) ; return SDValue ( N ,


<s> if ( Counter >= CTRLoopLimit ) return false ; Counter ++ ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I ) ) return MadeChange ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = <NUM_LIT> , FalseWeight = <NUM_LIT> ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( <NUM_LIT> ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return MadeChange ; } } BasicBlock * CountedExitBlock = nullptr ; const SCEV * ExitCount = nullptr ; BranchInst * CountedExitBranch = nullptr ; for ( SmallVectorImpl < BasicBlock * > :: iterator I = ExitingBlocks . begin ( ) , IE = ExitingBlocks . end ( ) ; I != IE ; ++ I ) { const SCEV * EC = SE -> getExitCount ( L , * I ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> << ( * I ) -> getName ( ) << <STR_LIT> << * EC << <STR_LIT> ) ; if ( isa < SCEVCouldNotCompute > ( EC ) ) continue ; if ( const SCEVConstant * ConstEC = dyn_cast < SCEVConstant > ( EC ) ) { if ( ConstEC -> getValue ( ) -> isZero ( ) ) continue ; } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TM -> is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ; if ( LI -> getLoopFor ( * I ) != L ) continue ; bool NotAlways = false ; for ( pred_iterator PI = pred_begin ( L -> getHeader ( ) ) , PIE = pred_end ( L -> getHeader ( ) ) ; PI != PIE ; ++ PI ) { if ( ! L -> contains ( * PI ) ) continue ; if ( ! DT -> dominates ( * I , * PI ) ) { NotAlways = true ; break ; } } if ( NotAlways ) continue ; Instruction * TI = ( * I ) -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast <


<s> return ( uint64x1_t ) { __a [ <NUM_LIT> ] ==


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( LoadVT ) } ; SDValue L = DAG . getNode ( <STR_LIT> , DL , { LoadVT , <STR_LIT>


<s> SmallVector < unsigned , <NUM_LIT> > src2 = getScalarRegisters ( src2regnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> + i ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; int src = which . getImm ( ) ; int elem = src % numcopies ; if ( which . getImm ( ) < numcopies ) copy -> addOperand ( MachineOperand :: CreateReg ( src1 [ elem ] , false ) ) ; else copy -> addOperand ( MachineOperand :: CreateReg ( src2 [ elem ] , false


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveFPLR ( int Offset )


<s> if ( Pmode == DImode ) ASSERT_RTL_DUMP_EQ_WITH_REUSE ( <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , pat ,


<s> bool UseBuildVector = false ; int InputUsed [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned LaneStart = l * NumLaneElems ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { Mask . push_back ( - <NUM_LIT> ) ; continue ; } int Input = Idx / NumLaneElems ; Idx -= Input * NumLaneElems ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; OpNo < array_lengthof ( InputUsed ) ; ++ OpNo ) { if ( InputUsed [ OpNo ] == Input ) break ; if ( InputUsed [ OpNo ] < <NUM_LIT> ) { InputUsed [ OpNo ] = Input ; break ; } } if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT )


<s> else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) ) { SmallVector < int , <STR_LIT> > Bytes ; if ( ! getVPermMask ( Op , Bytes ) ) break ; int First ; if ( ! getShuffleInput ( Bytes , Index * BytesPerElement , BytesPerElement , First ) ) break ; if ( First < <NUM_LIT> ) return DAG . getUNDEF ( ResVT ) ; unsigned Byte = unsigned ( First ) % Bytes . size ( ) ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Index = Byte / BytesPerElement ; Op = Op . getOperand ( unsigned ( First ) / Bytes . size ( ) ) ; Force = true ; } else if ( Opcode == <STR_LIT> && canTreatAsByteVector ( Op . getValueType ( ) ) ) { EVT OpVT = Op . getValueType ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( OpBytesPerElement < BytesPerElement ) break ; unsigned End = ( Index + <NUM_LIT> ) * BytesPerElement ; if ( End % OpBytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( End / OpBytesPerElement - <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isInteger ( ) ) { EVT VT = <STR_LIT> ( Op . getValueSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; } EVT VT = <STR_LIT> ( ResVT . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; if ( VT != ResVT ) { DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , ResVT , Op ) ; } return Op ; } else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) && canTreatAsByteVector ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { EVT ExtVT = Op . getValueType ( ) ; EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned ExtBytesPerElement = ExtVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned Byte = Index * BytesPerElement ; unsigned SubByte =


<s> TRI = & TII -> getRegisterInfo ( ) ; LIS = getAnalysisIfAvailable < LiveIntervals > ( ) ; assert ( SaveBlocks . empty ( ) && RestoreBlocks . empty ( ) ) ; calculateSaveRestoreBlocks ( MF ) ; bool HasCSRs = spillCalleeSavedRegs ( MF ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! MFI . hasStackObjects ( ) && ! HasCSRs ) { SaveBlocks . clear ( ) ; RestoreBlocks . clear ( ) ; if ( FuncInfo -> VGPRReservedForSGPRSpill ) { FuncInfo -> removeVGPRForSGPRSpill ( FuncInfo -> VGPRReservedForSGPRSpill , MF ) ; MRI . freezeReservedRegs ( MF ) ; } return false ; } bool MadeChange = false ; bool NewReservedRegs = false ; const bool HasSGPRSpillToVGPR = TRI -> spillSGPRToVGPR ( ) && ( HasCSRs || FuncInfo -> hasSpilledSGPRs ( ) ) ; if ( HasSGPRSpillToVGPR


<s> static bool IsUnconditionalJump ( int Opc ) { return ( Opc ==


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; unsigned i ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; rtx_insn * insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < <NUM_LIT> ) { remove_insn ( insn ) ; return false ; } return


<s> void <ISA_LIT>CallLowering :: lowerParameter ( MachineIRBuilder & B , Type * ParamTy , uint64_t Offset , unsigned Align , Register DstReg ) const { MachineFunction & MF = B . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = PointerType :: get ( ParamTy , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned TypeSize = DL . getTypeStoreSize ( ParamTy ) ; Register PtrReg = lowerParameterPtr ( B , ParamTy , Offset ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , TypeSize , Align ) ; B . buildLoad ( DstReg , PtrReg , *


<s> static rtx nvptx_gen_pack ( rtx dst , rtx src0 , rtx src1 ) { rtx res ; switch ( GET_MODE ( dst ) ) { case E_DImode


<s> bool isOffsetOfLocal ( ) const override { return isImm ( ) && Imm .


<s> if ( Src -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; assert ( Dst -> isVectorTy ( ) ) ; unsigned VF = Src -> getVectorNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits ==


<s> return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG


<s> bool useFPVFMx16 ( ) const { return useFPVFMx ( ) && hasFullFP16 (


<s> SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( OpVT , dl , Op , DAG . getUNDEF ( OpVT ) , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( OpVT , dl , Op , DAG . getUNDEF ( OpVT ) , & ShufMask2 [ <NUM_LIT> ] ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ; } return SDValue (


<s> bool isReg ( ) const override { return Kind == k_Register


<s> if ( ! cmp ) return false ; if ( negate ) cmp = ix86_expand_int_sse_cmp ( operands [ <NUM_LIT> ] , EQ , cmp , CONST0_RTX ( GET_MODE ( cmp ) ) , NULL , NULL , & negate ) ; gcc_assert ( ! negate ) ; if ( operands [ <NUM_LIT> ] != cmp ) emit_move_insn ( operands [ <NUM_LIT> ] , cmp ) ; return true


<s> MCSymbol * const Sym = Ctx -> getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( AgprIndexUnusedMin , * Ctx ) ) ; MCSymbol * const vSym = Ctx -> getOrCreateSymbol ( Twine ( <STR_LIT>


<s> static struct machine_function * loongarch_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function >


<s> void <ISA_LIT>RegisterInfo :: lowerCRBitRestore ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( Subtarget . hasVPOPCNTDQ ( ) ) { if ( VT == <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Op = DAG . getNode ( <STR_LIT> , DL ,


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo


<s> void setError ( unsigned e , unsigned r = <STR_LIT> ) { s . Error =


<s> static inline float __ev_get_fs_internal ( __ev64_opaque__ a , uint32_t pos ) { union { __ev64_opaque__ v ; float f [ <NUM_LIT> ] ; } u


<s> const Function & F = MF . getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) return false ; return F . hasFnAttribute ( <STR_LIT> ) || F


<s> assert ( V . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; SDLoc DL ( V ) ; switch ( V . getValueType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : { auto SubReg = DAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; auto Container = DAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , VT ) ; return DAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , VT , SDValue ( Container , <NUM_LIT> ) , V , SubReg ) ; } case <NUM_LIT> : { auto SubReg = DAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; auto Container = DAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , VT ) ; return DAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , VT , SDValue ( Container , <NUM_LIT> ) , V , SubReg ) ; } default : { auto RC = DAG -> getTargetConstant ( <STR_LIT> , DL ,


<s> TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op . getOperand ( i ) . getValueType ( ) ; const Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back


<s> if ( Op . isReg ( ) && Op . getReg ( ) == AMDGPU :: SCC ) Inst -> RemoveOperand ( i ) ; } if ( NewDesc . ImplicitUses ) { for ( unsigned i = <NUM_LIT> ; NewDesc . ImplicitUses [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitUses [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; } } if ( NewDesc . ImplicitDefs ) { for ( unsigned i = <NUM_LIT> ; NewDesc . ImplicitDefs [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitDefs [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } } legalizeOperands ( Inst


<s> bool isTargetNetBSD ( ) const { return TargetTriple . getOS ( ) ==