<s> else opts -> x_target_flags &= ~ MASK_HARD_DFP ; } if ( TARGET_SOFT_FLOAT_P ( opts_set -> x_target_flags ) && TARGET_SOFT_FLOAT_P ( opts -> x_target_flags ) ) { if ( TARGET_HARD_DFP_P ( opts_set -> x_target_flags ) && TARGET_HARD_DFP_P ( opts -> x_target_flags ) ) error ( <STR_LIT> ) ; opts -> x_target_flags &= ~ MASK_HARD_DFP ; } if ( TARGET_BACKCHAIN_P ( opts -> x_target_flags ) && TARGET_PACKED_STACK_P ( opts -> x_target_flags ) && TARGET_HARD_FLOAT_P ( opts -> x_target_flags ) ) error ( <STR_LIT> <STR_LIT> ) ; if ( opts -> x_s390_stack_size ) { if ( opts -> x_s390_stack_guard >= opts -> x_s390_stack_size ) error ( <STR_LIT> ) ; else if ( opts -> x_s390_stack_size > <NUM_LIT> << <NUM_LIT> ) error ( <STR_LIT> ) ; } else if ( opts -> x_s390_stack_guard ) error ( <STR_LIT> ) ; if ( ! TARGET_LONG_DOUBLE_128_P ( opts_set -> x_target_flags ) ) opts -> x_target_flags |= MASK_LONG_DOUBLE_128 ; if ( opts -> x_s390_tune >= PROCESSOR_2097_Z10 ) { maybe_set_param_value ( PARAM_MAX_UNROLLED_INSNS , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_MAX_UNROLL_TIMES , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_MAX_COMPLETELY_PEELED_INSNS , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_MAX_COMPLETELY_PEEL_TIMES , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; } maybe_set_param_value ( PARAM_MAX_PENDING_LIST_LENGTH , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_L1_CACHE_LINE_SIZE , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_L1_CACHE_SIZE , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_L2_CACHE_SIZE , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO , <NUM_LIT> , opts -> x_param_values , opts_set -> x_param_values ) ; maybe_set_param_value ( PARAM_SIMULTANEOUS_PREFETCHES , <NUM_LIT> , opts -> x_param_values , opts_set ->


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseOffs < <NUM_LIT> ) return false ; if ( AM . Scale != <NUM_LIT> )


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else report_fatal_error (


<s> return ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) ||

( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf32 ) ;


<s> if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , true ) ) return Med3 ; } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , false ) ) return Med3 ; } if ( ( ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) && ( VT == <STR_LIT> || VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> has16BitInsts ( ) ) ) && Op0 . hasOneUse ( ) ) { if ( SDValue Res = performFPMed3ImmCombine ( DAG , SDLoc ( N )


<s> return pParent . getTarget ( ) . getGOT ( ) . addr ( ) +


<s> assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasAVX2 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT . isScalableVector ( ) ) return performSVEAndCombine ( N , DCI ) ; if ( ! ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) ) return SDValue ( ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT>


<s> return false ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = ( IndexMode == <STR_LIT> ) ? <NUM_LIT> : ( IndexMode == <STR_LIT> || IndexMode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : BaseOp = & MI . getOperand ( <NUM_LIT> ) ; Offset = ( IndexMode == <STR_LIT> ) ? <NUM_LIT> : ( IndexMode == <STR_LIT> || IndexMode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT>


<s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & BMI = * MII ; if ( isVpuInstrWithSrcCD ( BMI ) ) return false ; if ( isSrcCIsStoreSrcC ( BMI ) ) return false ; if ( BMI . isTerminator ( ) ) { return false ; } if ( ! isNopInstr ( & BMI ) ) { if ( <ISA_LIT>II :: isVPUInst ( BMI . getDesc ( ) ) ) hasVPU = true ; else if ( <ISA_LIT>II :: isSPUInst ( BMI . getDesc ( ) ) ) hasSPU = true ; else if ( <ISA_LIT>II :: isLoadInst ( BMI . getDesc ( ) ) ) hasLD = true ; else if ( <ISA_LIT>II :: isStoreInst ( BMI . getDesc ( ) ) ) hasST = true ; } } if ( ( hasVPU || hasSPU ) && ( hasLD || hasST ) ) { return false ; } if ( doCompress ) { if ( hasVPU || hasSPU ) { rmOpcodeFromBundle ( MI , <STR_LIT> ) ; rmOpcodeFromBundle ( MI , <STR_LIT> ) ; } else { rmOpcodeFromBundle ( MI , <STR_LIT> ) ; rmOpcodeFromBundle ( MI


<s> MCSymbol * EndOfTextLabel = OutContext . getOrCreateSymbol ( StringRef ( END_OF_TEXT_LABEL_NAME ) ) ; OutStreamer -> EmitLabel ( EndOfTextLabel


<s> void LLVMInitialize<ISA_LIT>Target (


<s> int NumEltsPerLane = NumElts / NumLanes ; SmallVector < int , <NUM_LIT> > SrcLaneMask ( NumLanes , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ; LaneMask [ i ] = ( SrcLane * NumEltsPerLane ) + ( i % NumEltsPerLane ) ; PermMask [ i ] = ( DstLane *

NumEltsPerLane ) + ( M % NumEltsPerLane ) ;


<s> case E_V8HFmode : case E_V4SFmode : case E_V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case E_OImode : case E_XImode : gcc_unreachable ( ) ; case E_V64QImode : case E_V32HImode : case E_V16SImode : case E_V8DImode : case E_V32HFmode : case E_V16SFmode : case E_V8DFmode : case E_V16HFmode : case E_V8SFmode : case E_V8SImode : case E_V32QImode : case E_V16HImode : case E_V4DFmode : case E_V4DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> sse_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> sse_regno + FIRST_SSE_REG ) ; } break ; case E_V8QImode : case E_V4HImode : case E_V4HFmode : case E_V2SImode : case E_V2SFmode : case E_V1TImode : case E_V1DImode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { if ( cum -> mmx_nregs ) return gen_reg_or_parallel ( mode , orig_mode , cum -> mmx_regno + FIRST_MMX_REG ) ; } break ; } if ( error_p ) { cum -> float_in_sse


<s> return SelectAddrModeIndexed7S ( N , <NUM_LIT> , Base


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { TargetPassConfig :: addPreRegAlloc ( )


<s> return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || ( Src1 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; const int64_t Imm = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI -> RemoveOperand ( AMDGPU :: getNamedOperandIdx ( AMDGPU :: V_MAD_F32 , AMDGPU :: OpName :: omod ) ) ; UseMI -> RemoveOperand ( AMDGPU :: getNamedOperandIdx ( AMDGPU :: V_MAD_F32 , AMDGPU :: OpName :: clamp ) ) ; Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( AMDGPU :: V_MADAK_F32 ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ; } } return false


<s> if ( IDVal == <STR_LIT> ) parseDirectiveArch ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> )


<s> * hw_after = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_CHAIN ( args ) ) ) ; } else { * hw_before = s390_hotpatch_hw_before_label ; * hw_after = s390_hotpatch_hw_after_label


<s> int <STR_LIT> ( SDNode * N , unsigned ShuffleKind , SelectionDAG & DAG ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return - <NUM_LIT> ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; unsigned i ; for ( i = <NUM_LIT> ; i != <NUM_LIT> && SVOp -> getMaskElt ( i ) < <NUM_LIT> ; ++ i ) ; if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; bool isLE = DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ; if ( ( ShuffleKind == <NUM_LIT> && ! isLE ) || ( ShuffleKind == <NUM_LIT> && isLE ) ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else if ( ShuffleKind == <NUM_LIT> ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp ->

getMaskElt ( i ) , ( ShiftAmt + i ) & <NUM_LIT> ) ) return - <NUM_LIT> ;


<s> bool cy = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sy = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <ISA_LIT>ValToCondCode ( cf , isIntegerBCKind ( MI ) ) ) ) ; DecodeStatus status ; if ( cy ) { status = DecodeI64RegisterClass ( MI , sy , Address , Decoder ) ; if ( status != MCDisassembler :: Success


<s> void addu32_0ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst


<s> if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; unsigned EltSize = InputVector . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint64_t Offset = EltSize * cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue OffsetVal = DAG . getConstant ( Offset , TLI . getPointerTy ( ) ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , Idx . getValueType ( ) , StackPtr , OffsetVal ) ; SDValue LoadScalar = DAG . getLoad ( Extract -> getValueType ( <NUM_LIT> ) , dl , Ch , ScalarAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Extract , <NUM_LIT> ) , LoadScalar


<s> EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) ) { unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ; return DAG . getBitcast ( VT , FPLogic ) ; } if ( ! Subtarget . hasAVX ( ) || VT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; unsigned NumElts = <NUM_LIT> / N00Type . getSizeInBits ( ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , N00Type , NumElts ) ; EVT BoolVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue ZeroIndex = DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 . getOperand ( <NUM_LIT> ) ; SDValue Vec00 = DAG . getNode ( <STR_LIT> , DL , VecVT , N00 ) ; SDValue Vec01 = DAG . getNode ( <STR_LIT> , DL , VecVT , N01 ) ; SDValue Vec10 = DAG . getNode ( <STR_LIT> , DL , VecVT , N10 ) ; SDValue Vec11 = DAG . getNode ( <STR_LIT> , DL , VecVT , N11 ) ; SDValue Setcc0 = DAG . getSetCC ( DL , BoolVecVT , Vec00 , Vec01 , cast < CondCodeSDNode > (

N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ) ;


<s> static bool virt_or_elim_regno_p ( unsigned regno ) { return ( ( regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_POINTER_REGISTER ) || regno ==

FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ;


<s> if ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; if ( DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && Subtarget -> useSVEForFixedLengthVectors ( ) && VT . isFixedLengthVector ( ) && VT . getFixedSizeInBits ( ) >= Subtarget -> getMinSVEVectorSizeInBits ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue ExtLoad = DAG . getExtLoad ( <STR_LIT> , SDLoc ( N ) , VT , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , N0 . getValueType ( ) , LN0 -> getMemOperand ( ) ) ; DCI . CombineTo ( N , ExtLoad ) ; DCI . CombineTo ( N0 . getNode ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , ExtLoad , DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( N0 ) ) ) , ExtLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT>


<s> inline int vec_any_ngt ( vector float a1 , vector


<s> static int aarch64_sched_adjust_priority ( rtx_insn * insn , int priority ) { rtx x = PATTERN ( insn ) ; if ( GET_CODE ( x ) == SET ) { x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_SHA1H )


<s> copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstrBuilder copy ( F , copies [ <NUM_LIT> ] ) ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ; unsigned regnum = dest . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy -> RemoveOperand (


<s> MachineInstr * MI = MBBI ; unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned Bytes = getLSMultipleTransferSize ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; int Opcode = MI -> getOpcode ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isAM4 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool DoMerge = false ; <STR_LIT> Mode = <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( isAM4 ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; } assert ( ! <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { assert ( ! <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Offset = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( isAM4 ) { if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; Mode = <STR_LIT> ; } else if ( isAM4 && Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; Mode = <STR_LIT> ; } } else { if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } } if ( DoMerge ) MBB . erase ( PrevMBBI ) ; } if ( ! DoMerge && MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( isAM4 ) { if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge =


<s> void <ISA_LIT>InstPrinter :: printPostIncOperand2 ( const MCInst * MI ,


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const <ISA_LIT>TargetMachine & >


<s> MachineInstrBuilder ( MF , EarlierMI ) . addReg ( Reg128 , Reg128UndefImpl ) ; MachineInstrBuilder ( MF , MI ) . addReg ( Reg128 , ( Reg128UndefImpl | Reg128Killed ) ) ; } MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; if ( EarlierMI -> getOperand ( <NUM_LIT> ) . isReg ( ) && EarlierMI -> getOperand ( <NUM_LIT> ) . isUse ( ) ) EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ; unsigned LowOpcode = getOpcodeForOffset ( NewOpcode , LowOffsetOp . getImm ( )


<s> int tr0_used ; if ( ! current_function_is_leaf ) return - <NUM_LIT> ; tr0_used = flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_used_regs [ regno ] &&

! regs_ever_live [ regno ] ) return regno ;


<s> inline static unsigned decodeVSEW ( unsigned VSEW ) { assert ( VSEW < <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> << ( VSEW


<s> inline vector unsigned int vec_splat_u32 (


<s> const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) << ']' ; if ( <STR_LIT> ( MO3 . getImm ( ) ) ) { if ( MO2 . getReg ( ) == <NUM_LIT> ) O << '!' ; else O << <STR_LIT> << getRegisterName ( MO2


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( size <= <NUM_LIT> * PROBE_INTERVAL ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( sr . reg ,


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; int UpdateOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) UpdateOffset = - UpdateOffset ; int Scale , MinOffset , MaxOffset ; getPrePostIndexedMemOpInfo ( MemMI , Scale , MinOffset , MaxOffset ) ; if ( UpdateOffset % Scale != <NUM_LIT> ) break ; int ScaledOffset = UpdateOffset / Scale ; if ( ScaledOffset > MaxOffset || ScaledOffset < MinOffset ) break ; if ( ! Offset || Offset == UpdateOffset ) return


<s> ShuffleMask . push_back ( <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++


<s> if ( CV -> isNullValue ( ) || isa < UndefValue > ( CV ) ) return MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) return MCConstantExpr :: Create ( CI -> getZExtValue ( ) , Ctx ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) return MCSymbolRefExpr :: Create ( AP . getSymbol ( GV ) , Ctx ) ; if ( const BlockAddress * BA = dyn_cast < BlockAddress > ( CV ) ) return MCSymbolRefExpr :: Create ( AP . GetBlockAddressSymbol ( BA ) , Ctx ) ; const ConstantExpr * CE = dyn_cast < ConstantExpr > ( CV ) ; if ( ! CE ) llvm_unreachable ( <STR_LIT> ) ; switch ( CE -> getOpcode ( ) ) { default : if ( Constant * C = ConstantFoldConstantExpression ( CE , AP . TM . getDataLayout ( ) ) ) if ( C != CE ) return LowerConstant ( C , AP ) ; { std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! AP . MF ? nullptr : AP . MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; PointerType * SrcTy = cast < PointerType > ( CE -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcTy -> getAddressSpace ( ) == <NUM_LIT> && DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return LowerConstant ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , AP ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! AP . MF ? nullptr : AP . MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr :


<s> Relocation :: Type type = pRelocation . type ( ) ; if ( type >= sizeof ( <ISA_LIT>_64ApplyFunctions ) / sizeof ( <ISA_LIT>_64ApplyFunctions [ <NUM_LIT>


<s> const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FK_PCRel_4 ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } unsigned OpNo = <NUM_LIT> ; for ( unsigned e = MI . getNumOperands ( ) ; OpNo < e ; ++ OpNo ) { if ( & MO == & MI . getOperand ( OpNo )


<s> void <ISA_LIT>CCState :: PreAnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const SDNode * CallNode ) { for ( unsigned i = <NUM_LIT> ; i < Outs . size ( ) ; ++ i ) { OriginalArgWasF128 . push_back ( originalTypeIsF128 ( FuncArgs [ Outs [ i ] . OrigArgIndex ]


<s> case VK_<ISA_LIT>_PC22 : return <STR_LIT> ; case VK_<ISA_LIT>_PC10 : return <STR_LIT> ; case VK_<ISA_LIT>_GOT22 : return <STR_LIT> ; case VK_<ISA_LIT>_GOT10 : return <STR_LIT> ; case VK_<ISA_LIT>_GOT13 : return <STR_LIT> ; case VK_<ISA_LIT>_13 : return <STR_LIT> ; case VK_<ISA_LIT>_WPLT30 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_HI22 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_LO10 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_ADD : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_CALL : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_LDM_HI22 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_LDM_LO10 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_LDM_ADD : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_LDM_CALL : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_LDO_HIX22 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_LDO_LOX10 : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_LDO_ADD : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_IE_HI22 : return


<s> MachineInstr * OldMI = & ( * I ) ; MachineBasicBlock * MBB = OldMI -> getParent ( ) ; MachineInstr * NewMBB = MBB -> getParent ( ) -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DebugLoc ( ) ) ; MBB -> insert ( I , NewMBB ) ; SHOWNEWINSTR ( NewMBB ) ; return NewMBB


<s> static bool isLiveOut ( const MachineBasicBlock & MBB , unsigned Reg ) { for ( MachineBasicBlock * Succ : MBB


<s> uint64x1_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> static unsigned getCallOpcode ( const MachineFunction & CallerF , bool IsIndirect


<s> const TargetRegisterInfo * TRI = MI -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI -> getFlags ( ) & MachineInstr :: FrameDestroy ) return <NUM_LIT> ; if ( MI -> register_sgx_type != <NUM_LIT> ) return MI -> register_sgx_type ; if ( MI -> mayLoad ( ) && MI -> sgx_type == <NUM_LIT> ) { MI -> dump ( ) ; errs ( ) << ( void * ) MI << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; } if ( MI -> isCall ( ) ) { if ( MI -> getFlags ( ) & MachineInstr :: FrameSetup ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> uses ( ) . begin ( ) -> getReg ( ) == ( MI -> uses ( ) . begin ( ) + <NUM_LIT> ) -> getReg ( ) ) return <NUM_LIT> ; } if ( MI -> mayLoad ( ) && MI -> sgx_type == <NUM_LIT> ) return <NUM_LIT> ; for ( auto OP = MI -> uses ( ) . begin ( ) ; OP != MI -> uses ( ) . end ( ) ; OP ++ ) { if ( OP -> isReg ( ) && OP -> getReg ( ) != <STR_LIT> && OP -> getReg ( ) != <STR_LIT> && OP -> getReg ( ) != <STR_LIT> && MI -> readsRegister ( OP -> getReg ( ) , TRI ) ) { if ( private_set . find ( OP -> getReg ( ) ) != private_set . end ( ) ) { return <NUM_LIT> ; } } } return <NUM_LIT>


<s> return <NUM_LIT> ; case AVR_BUILTIN_DELAY_CYCLES : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) error ( <STR_LIT> , bname ) ; else avr_expand_delay_cycles ( op0 ) ; return NULL_RTX ; } case AVR_BUILTIN_INSERT_BITS : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) { error ( <STR_LIT> <STR_LIT> , bname ) ; return target ; } break ; } case AVR_BUILTIN_ROUNDHR : case AVR_BUILTIN_ROUNDUHR : case AVR_BUILTIN_ROUNDR : case AVR_BUILTIN_ROUNDUR : case AVR_BUILTIN_ROUNDLR : case AVR_BUILTIN_ROUNDULR : case AVR_BUILTIN_ROUNDLLR : case AVR_BUILTIN_ROUNDULLR : case AVR_BUILTIN_ROUNDHK : case AVR_BUILTIN_ROUNDUHK : case AVR_BUILTIN_ROUNDK : case AVR_BUILTIN_ROUNDUK : case AVR_BUILTIN_ROUNDLK : case AVR_BUILTIN_ROUNDULK : case AVR_BUILTIN_ROUNDLLK : case AVR_BUILTIN_ROUNDULLK : if ( TREE_CODE ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) != INTEGER_CST ) break ; int rbit = ( int ) TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( rbit >= ( int ) GET_MODE_FBIT ( mode ) ) { warning ( OPT_Wextra , <STR_LIT> <STR_LIT> , rbit ,


<s> NodeList UNodeList ; getAllRealUses ( SA , UNodeList ) ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseUN = * I ; assert ( ! ( UseUN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > UseIA = UseUN . Addr -> getOwner ( * DFG ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Print < NodeAddr < InstrNode * >> ( UseIA , * DFG ) << <STR_LIT> ) ; MachineInstr * UseMI = UseIA . Addr -> getCode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << UseMI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; const MCInstrDesc & UseMID = UseMI -> getDesc ( ) ; assert ( HII -> getAddrMode ( * UseMI ) == <STR_LIT> ) ; auto UsePos = MachineBasicBlock :: iterator ( UseMI ) ; MachineBasicBlock :: instr_iterator InsertPt = UsePos


<s> SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64 . getNode ( ) , <NUM_LIT> ) } ; SDValue OutChain = DAG . getNode ( <STR_LIT>


<s> else move = - <NUM_LIT> ; } if ( move < <NUM_LIT> ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; scratch = operands [ move < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ] ; emit_insn ( ( * operation ) ( scratch , high_bit , operands [ <NUM_LIT> ] ) ) ; if ( move > <NUM_LIT>


<s> bool isDSOffset0 ( ) const { assert ( isImm ( ) ) ; return Imm . Type ==


<s> MachineOperand & Src1 = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , *


<s> uint64_t OriginalValue = CE -> getValue ( ) ; uint64_t InvertedValue = OriginalValue ^ ( ( ( uint64_t ) <NUM_LIT> << size


consumer_src , <NUM_LIT> ) == UNSPEC_AESMC ) || ( XINT ( producer_src , <NUM_LIT> ) == UNSPEC_AESD && XINT ( consumer_src , <NUM_LIT> ) == UNSPEC_AESIMC ) ) ) {


<s> if ( op_const & <NUM_LIT> ) return build_int_cst ( long_integer_type_node , opint [ <NUM_LIT> ] & mask ) ; if ( op ) return fold ( build2 ( BIT_AND_EXPR , long_integer_type_node , op [ <NUM_LIT> ] , build_int_cst ( long_integer_type_node , mask ) ) ) ; } else if ( ( op_const & <NUM_LIT> ) && opint [ <NUM_LIT> ]


<s> Value * NewOperand = hoistAddrSpaceCastFrom ( BC -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( NewOperand == nullptr ) return nullptr ; assert ( isEliminableAddrSpaceCast ( NewOperand ) ) ; Operator * Cast = cast < Operator > ( NewOperand ) ; Value * Src = Cast -> getOperand ( <NUM_LIT> ) ; Type * TypeOfNewCast = PointerType :: get ( BC -> getType ( ) -> getPointerElementType ( ) , Src -> getType ( ) -> getPointerAddressSpace ( ) ) ; Value * NewBC ; if ( BitCastInst * BCI = dyn_cast < BitCastInst > ( BC ) ) { Value * NewCast = new BitCastInst ( Src , TypeOfNewCast , <STR_LIT> , BCI ) ; NewBC = new AddrSpaceCastInst ( NewCast , BC -> getType ( ) , <STR_LIT> , BCI ) ; NewBC -> takeName ( BC ) ; BC -> replaceAllUsesWith ( NewBC ) ; } else { Constant * NewCast = ConstantExpr :: getBitCast ( cast < Constant > ( Src ) ,


<s> return ( uint16x4_t ) __builtin_neon_vshluv4hi ( ( int16x4_t )


<s> MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; MFI -> setReturnAddressIsTaken ( true ) ; unsigned Reg = MF . addLiveIn ( RA ,


<s> if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( GET_MODE ( op0 ) == mode0 && GET_MODE ( op1 ) == mode1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat


<s> a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_add ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_short [ <NUM_LIT> ] = m1 . as_short [ <NUM_LIT> ] + m2 . as_short [ <NUM_LIT> ] ; res . as_short [ <NUM_LIT> ] = m1 . as_short [ <NUM_LIT> ] +


<s> } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg


<s> return MI . getOperand ( Op ) . getImm ( ) -


<s> bool NeedStub = false ; MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES , RelocCST , <NUM_LIT> , NeedStub ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( <NUM_LIT> ) ; else MCE . emitWordLE ( <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printCPInstOperand ( const MCInst * MI , unsigned OpNum , const char *


<s> SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; DCI . RemoveFromWorklist ( LD ) ; DAG . DeleteNode


<s> } bool Changed = false ; NumHWLoopsInternal = <NUM_LIT> ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = HST . getInstrInfo ( ) ; TRI = HST . getRegisterInfo ( ) ; for ( auto & L : * MLI ) if ( ! L -> getParentLoop ( ) ) { bool L0Used = false ; bool L1Used = false ; KnownHardwareLoops . clear ( ) ; Changed |= convertToHardwareLoop ( L , L0Used , L1Used ) ; } if ( Changed )


<s> unsigned InstOffset = BlockToInstOffset [ & B ] ; unsigned Distance = <NUM_LIT> ; InstOffset += HII -> nonDbgBBSize ( & B ) * HEXAGON_INSTR_SIZE ; MachineBasicBlock * TBB = NULL , * FBB = NULL ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; if ( HII -> analyzeBranch ( B , TBB , FBB , Cond , false ) ) { if ( HII -> isNewValueJump ( & * FirstTerm ) ) TBB = FirstTerm -> getOperand ( HII -> getCExtOpNum ( & * FirstTerm ) ) . getMBB ( ) ; } if ( TBB && & MI == & * FirstTerm ) { Distance = std :: abs ( ( long long ) InstOffset -

BlockToInstOffset [ TBB ] ) + BranchRelaxSafetyBuffer ;


<s> static inline void vec_st ( vec_float4 a , int b , vec_float4 * c ) { * ( ( vec_float4 * ) ( ( unsigned char * ) ( c )


<s> int div = <NUM_LIT> ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return <NUM_LIT> ; if ( TARGET_AVX512_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; width = ( width + div - <NUM_LIT>


<s> if ( hasLoadFromStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return MI . getOperand ( <NUM_LIT>


<s> std :: string Name = Mapper . toString ( Val , STI . getFeatureBits ( ) ) ; O << StringRef ( Name ) . upper


<s> switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> unsigned OffsetBytes = <NUM_LIT> * ( getStackWidth ( MF ) * <NUM_LIT> ) ; int UpperBound = FI == - <NUM_LIT> ? MFI -> getNumObjects ( ) : FI ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = RoundUpToAlignment ( OffsetBytes , MFI -> getObjectAlignment ( i ) ) ; OffsetBytes += MFI -> getObjectSize ( i ) ; OffsetBytes = RoundUpToAlignment ( OffsetBytes , <NUM_LIT> ) ; } if ( FI != - <NUM_LIT> ) OffsetBytes = RoundUpToAlignment ( OffsetBytes , MFI -> getObjectAlignment ( FI ) ) ; return OffsetBytes / ( getStackWidth ( MF )


<s> bool runOnFunction ( Function & F ) override { visit (


<s> bool is64Bit = TheTriple . getArch ( ) == Triple :: x86_64 ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . getOS ( ) == Triple :: Win32 ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . getOS ( ) == Triple :: MinGW32 || TheTriple . getOS ( ) == Triple :: Cygwin ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; MachineLocation Dst ( MachineLocation


<s> Addr . setReg ( Reg ) ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { auto * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } if ( int64_t ( TmpOffset ) >= <NUM_LIT> ) { Addr . setOffset ( TmpOffset ) ; if ( computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; } Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const auto * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { if ( Addr . isSet ( ) ) { return false ; } Addr . setKind ( Address :: FrameIndexBase ) ; Addr . setFI ( SI -> second ) ; return true ; } break ; } case Instruction :: Add : { const Value * LHS = U -> getOperand ( <NUM_LIT> ) ; const Value * RHS = U -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantInt > ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t TmpOffset = Addr . getOffset ( ) + CI -> getSExtValue ( ) ; if ( int64_t ( TmpOffset ) >= <NUM_LIT> ) { Addr . setOffset ( TmpOffset ) ; return computeAddress ( LHS , Addr ) ; } } Address Backup = Addr ; if ( computeAddress ( LHS , Addr ) && computeAddress ( RHS , Addr ) ) return true ; Addr = Backup ; break ; } case Instruction :: Sub : { const Value * LHS = U -> getOperand ( <NUM_LIT> ) ; const Value * RHS = U -> getOperand ( <NUM_LIT> ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( RHS ) ) { int64_t TmpOffset = Addr . getOffset ( ) - CI -> getSExtValue ( ) ; if ( TmpOffset >= <NUM_LIT> ) { Addr . setOffset ( TmpOffset ) ; return computeAddress ( LHS , Addr ) ; } } break ; } } if ( Addr .


<s> if ( ! Src2 . isImm ( ) ) return false ; APInt A ( <NUM_LIT> , Src2 . getImm ( ) , true ) ; Eval = evaluateANDri ( R1 , A , Inputs , RC ) ; break ; } case <STR_LIT> : case <STR_LIT> : Eval = evaluateORrr ( R1 , Register ( Src2 ) , Inputs , RC ) ; break ; case <STR_LIT> : { if ( ! Src2 . isImm ( ) ) return false ; APInt A ( <NUM_LIT> , Src2 . getImm ( ) , true ) ; Eval = evaluateORri ( R1 , A , Inputs , RC ) ; break ; } case <STR_LIT> : case <STR_LIT> : Eval = evaluateXORrr ( R1 , Register ( Src2 )


<s> SDValue Flag = EmitCMP ( LHS , RHS , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op .

getValueType ( ) , Chain , Dest , Flag ) ;


<s> { edge_iterator ei ; edge e1 , e2 ; ei = ei_start ( bb -> succs ) ; e1 = ei_safe_edge ( ei ) ; ei_next ( & ei ) ; e2 = ei_safe_edge ( ei ) ; if ( e2 -> flags & EDGE_FALLTHRU ) { e2 = e1 ; e1 = ei_safe_edge ( ei ) ; } if ( ! ( e1 -> flags & EDGE_FALLTHRU ) ) return ; tbegin_bb = ( target == pc_rtx ) ? e1 -> dest : e2 -> dest ; } if ( tmp == BB_END ( bb ) ) break ; } } if ( XINT ( SET_SRC ( pat ) , <NUM_LIT> ) == UNSPECV_TEND ) { if ( tend_bb != NULL ) return ; tend_bb = bb ; } } } cfun -> machine -> tbegin_p = false ; if ( tbegin_bb == NULL || tend_bb == NULL ) return ; calculate_dominance_info ( CDI_POST_DOMINATORS ) ; result = dominated_by_p ( CDI_POST_DOMINATORS , tbegin_bb , tend_bb ) ; free_dominance_info ( CDI_POST_DOMINATORS ) ; if ( ! result ) return ; PATTERN ( tbegin_insn ) = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , XVECEXP ( PATTERN ( tbegin_insn ) , <NUM_LIT> , <NUM_LIT> ) , XVECEXP ( PATTERN ( tbegin_insn ) , <NUM_LIT> , <NUM_LIT> ) ) ) ; INSN_CODE ( tbegin_insn ) = - <NUM_LIT> ; df_insn_rescan ( tbegin_insn


<s> setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( OrigArg . Ty -> isIntegerTy ( <NUM_LIT> ) ) { assert ( OrigArg . Regs . size ( ) == <NUM_LIT> && MRI . getType ( OrigArg . Regs [ <NUM_LIT> ] ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! OrigArg . Flags [ <NUM_LIT> ] . isZExt ( ) ) { Register OrigReg = OrigArg . Regs [ <NUM_LIT> ] ; Register WideReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; OrigArg . Regs [ <NUM_LIT> ] = WideReg ; BoolArgs . push_back ( { OrigReg , WideReg } ) ; } } if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; <ISA_LIT>IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; if ( ! BoolArgs . empty ( ) ) { for ( auto & KV : BoolArgs ) { Register OrigReg = KV . first ; Register WideReg = KV . second ; LLT WideTy = MRI . getType ( WideReg ) ; assert ( MRI . getType ( OrigReg ) . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildTrunc ( OrigReg , MIRBuilder . buildAssertZExt ( WideTy , WideReg , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ) ; } } <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F .


<s> rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_SImode : gen = gen_and_one_cmpl_lshrsi3 ; break ; case E_DImode : gen = gen_and_one_cmpl_lshrdi3 ; break ; default : gcc_unreachable (


<s> void addImm0_31Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> static inline bool isTOCSaveRestoreRequired ( const


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> assert ( VT . isFixedLengthVector ( ) && <STR_LIT> ) ; assert ( V . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; SDLoc DL (


<s> return * ( getContext ( ) . getRegisterInfo ( ) . getRegClass ( RC ) . begin ( )


<s> case Type :: DoubleTyID : return <STR_LIT> ; case Type :: VectorTyID : { auto VecTy = cast < VectorType > ( Ty ) ; auto ElTy = VecTy -> getElementType ( ) ; auto NumElements = VecTy -> getVectorNumElements ( ) ; return ( Twine ( getTypeName ( ElTy , Signed ) ) + Twine ( NumElements ) ) . str ( ) ; } default : return <STR_LIT>


<s> void writeDIGlobalVariableExpression ( const DIGlobalVariableExpression * N , SmallVectorImpl < uint64_t > & Record , unsigned Abbrev


<s> bool <STR_LIT> ( SDValue Elt ) { return ( ( isa < ConstantSDNode > ( Elt ) && cast < ConstantSDNode > ( Elt ) -> isNullValue ( ) ) || ( isa < ConstantFPSDNode

> ( Elt ) && cast < ConstantFPSDNode > ( Elt ) -> getValueAPF ( ) . isPosZero ( ) ) ) ;


<s> assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; int ShufIdxs [ <NUM_LIT> ] ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VMRGHW : ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VMRGLW : ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT>


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter

( TM , Streamer ) , MCInstLowering ( * this ) {


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegD ) ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; if ( ! isSPVFP ) { Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegD &


<s> assert ( Kind == k_ShiftExtend && <STR_LIT> ) ; return ShiftExtend .


<s> else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveNops ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlign ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_lower ( <STR_LIT> ) ) ) return parseDirectiveSEHPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || ( Parser . isParsingMasm ( ) && IDVal . equals_lower ( <STR_LIT> ) ) ) return

parseDirectiveSEHSetFrame ( DirectiveID . getLoc ( ) ) ;


<s> auto N = cast < GlobalAddressSDNode > ( Op ) ; assert ( N -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = N


<s> if ( ! Scope ) return ; StringRef fileName ( Scope -> getFilename ( ) ) ; StringRef dirName ( Scope -> getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName ; } if ( filenameMap . find ( fileName ) == filenameMap . end ( ) ) return ; if ( InterleaveSrc ) this -> emitSrcInText ( fileName ,


<s> Value * <ISA_LIT>IREmitter :: visitFMADDSUB ( const SDNode *


<s> SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; Offset = G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > (


<s> sema_iterator sema_begin ( ) { return mSemaphore . begin


<s> initialize<ISA_LIT>GenInsertPass ( * PassRegistry ::


<s> } return ; } if ( frame_pointer_needed ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> use_eh_return_p ) { Rb = cfun -> machine -> eh_return_data_first_regno ; Re = cfun -> machine ->


<s> return ( ( vec_double2 ) ( si_dfnms ( ( qword ) ( a ) , ( qword ) ( b )


<s> assert ( ( ( ! Subtarget . hasAVX512 ( ) && VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isOneConstant ( Op1


<s> return Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp ,


<s> using RegAndKill = std :: pair < unsigned , bool > ; SmallVector < RegAndKill , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn && ! MRI . isReserved ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , !


<s> std :: vector < MachineBasicBlock * > & getBlocksVector (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , RM , CM , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( TT ) , CPU , Options . MCOptions ) ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , * this ) { Subtarget = & DefaultSubtarget ; initAsmInfo ( )


<s> int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) ||


<s> bool <ISA_LIT>TargetLowering :: canLoadStoreByteSwapped ( EVT VT ) const { if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT>


<s> if ( GET_CODE ( op1 ) != CONST_INT ) { sparc_emit_set_symbolic_const64 ( op0 , op1 , temp ) ; return ; } if ( ! temp ) temp = gen_reg_rtx ( DImode ) ; high_bits = ( ( INTVAL ( op1 ) >> <NUM_LIT> ) & <NUM_LIT> ) ; low_bits = ( INTVAL ( op1 ) & <NUM_LIT> ) ; analyze_64bit_constant ( high_bits , low_bits , & highest_bit_set , & lowest_bit_set , & all_bits_between_are_set ) ; if ( ( ( highest_bit_set == <NUM_LIT> || lowest_bit_set == <NUM_LIT> ) && all_bits_between_are_set != <NUM_LIT> ) || ( ( highest_bit_set - lowest_bit_set ) < <NUM_LIT> ) ) { HOST_WIDE_INT the_const = - <NUM_LIT> ; int shift = lowest_bit_set ; if ( ( highest_bit_set != <NUM_LIT> && lowest_bit_set != <NUM_LIT> ) || all_bits_between_are_set == <NUM_LIT> ) { the_const = create_simple_focus_bits ( high_bits , low_bits , lowest_bit_set , <NUM_LIT> ) ; } else if ( lowest_bit_set == <NUM_LIT> ) shift = - ( <NUM_LIT> - highest_bit_set ) ; gcc_assert ( SPARC_SIMM13_P ( the_const ) ) ; gcc_assert ( shift != <NUM_LIT> ) ; emit_insn ( gen_safe_SET64 ( temp , the_const ) ) ; if ( shift > <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , temp , GEN_INT ( shift ) ) ) ) ; else if ( shift < <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_LSHIFTRT ( DImode , temp , GEN_INT ( - shift ) ) ) ) ; return ; } if ( ( highest_bit_set - lowest_bit_set ) < <NUM_LIT> ) { unsigned HOST_WIDE_INT focus_bits = create_simple_focus_bits ( high_bits , low_bits , lowest_bit_set , <NUM_LIT> ) ; gcc_assert ( SPARC_SETHI_P ( focus_bits ) ) ; gcc_assert ( lowest_bit_set != <NUM_LIT> ) ; emit_insn ( gen_safe_HIGH64 ( temp , focus_bits ) ) ; if ( lowest_bit_set < <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_LSHIFTRT ( DImode , temp , GEN_INT ( <NUM_LIT> - lowest_bit_set ) ) ) ) ; else if ( lowest_bit_set > <NUM_LIT> ) emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_ASHIFT ( DImode , temp

, GEN_INT ( lowest_bit_set - <NUM_LIT> ) ) ) ) ;


<s> APInt Mask = WidenedDemandedElts . getBitsSet ( NumElts , I , I + Scale ) ; APInt MaskedDE = Mask & WidenedDemandedElts ; unsigned Population = MaskedDE . countPopulation ( ) ; Cost += ( Population > <NUM_LIT> && Population != Scale && I % LT . second . getVectorNumElements ( ) != <NUM_LIT> ) ; Cost += Population > <NUM_LIT> ; } Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == <STR_LIT> ) for ( unsigned i = <NUM_LIT> , e = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; i < e ; i += <NUM_LIT> ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( cast < FixedVectorType >


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>MIPeepholeOptPass (


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> uint32_t encodeStackAdjustment ( uint32_t StackSize )


<s> vqmovn_high_u16 ( uint8x8_t a , uint16x8_t b ) { uint8x16_t result = vcombine_u8 ( a , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) )


<s> const BlackfinRegisterInfo * getRegisterInfo (


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultUNorm ( ) const { return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyUNorm


<s> Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : if ( name == <STR_LIT> ) Op = <STR_LIT> ( <STR_LIT> , S ) ; else Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; } break ; } if ( match<ISA_LIT>AsmModifiers ( EVal , E ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Op = <STR_LIT> ( EVal , S , E ) ; } break ; case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: LParen : case AsmToken :: Dot : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( EVal , E ) ) break ; int64_t Res ; if ( ! EVal -> evaluateAsAbsolute ( Res ) ) { <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_13 ; if ( getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ) { if ( isCall ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_WPLT30 ; else Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT13 ; } EVal = <ISA_LIT>MCExpr :: create ( Kind , EVal , getContext ( ) ) ; } Op = <STR_LIT> ( EVal , S , E ) ; break ; } return ( Op ) ? MatchOperand_Success :


<s> addPass ( createMicro<ISA_LIT>SizeReductionPass ( ) ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( ) ) ; addPass ( create<ISA_LIT>LongBranchPass ( ) ) ; addPass ( create<ISA_LIT>HazardSchedule ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( )


<s> if ( ! isInt < <NUM_LIT> > ( Addr . getOffset ( ) ) ) { unsigned TempReg = materialize32BitInt ( Addr . getOffset ( ) ,


<s> if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; Stack . push_back ( Type ) ; } else if ( Name == <STR_LIT> ) { if ( getTable ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , Type ) ) return true ; if ( popType ( ErrorLoc , Type ) ) return true ; if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; } else if ( Name == <STR_LIT> ) { if ( getTable ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , Type ) ) return true ; if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; if ( popType ( ErrorLoc , Type ) ) return true ; if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; } else if ( Name == <STR_LIT> ) { if ( popType ( ErrorLoc , { } ) ) return true ; } else if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) { if ( checkEnd ( ErrorLoc , Name == <STR_LIT> ) ) return true ; if ( Name == <STR_LIT> ) Unreachable = false ; } else if ( Name == <STR_LIT> ) { if ( endOfFunction ( ErrorLoc ) ) return true ; } else if ( Name == <STR_LIT> || Name == <STR_LIT> ) { if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; if ( checkSig ( ErrorLoc , LastSig ) ) return true ; if ( Name == <STR_LIT> && endOfFunction ( ErrorLoc ) ) return true ; } else if ( Name == <STR_LIT> || Name == <STR_LIT> ) { const MCSymbolRefExpr * SymRef ; if ( getSymRef ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , SymRef ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( & SymRef -> getSymbol ( ) ) ; auto Sig = WasmSym -> getSignature ( ) ; if ( ! Sig || WasmSym -> getType ( ) != <STR_LIT> ) return typeError ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , StringRef ( <STR_LIT> ) + WasmSym -> getName ( ) + <STR_LIT> ) ; if ( checkSig ( ErrorLoc , * Sig ) ) return true ; if ( Name == <STR_LIT> && endOfFunction ( ErrorLoc ) ) return true ; } else if ( Name == <STR_LIT> ) { const MCSymbolRefExpr * SymRef ; if ( getSymRef ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , SymRef ) ) return true ; const auto * WasmSym = cast < MCSymbolWasm > ( & SymRef -> getSymbol ( ) ) ; const auto * Sig = WasmSym -> getSignature


<s> void DecodeUNPCKHMask ( MVT VT , SmallVectorImpl < int > & ShuffleMask ) { unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; if ( NumLanes == <NUM_LIT> ) NumLanes = <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = l + NumLaneElts / <NUM_LIT> , e = l + NumLaneElts


<s> gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( )


<s> IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( ContainerVT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; } else VL = DAG . getRegister ( <STR_LIT> , XLenVT ) ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { MGN -> getChain ( ) , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; if ( ! IsUnmasked ) Ops . push_back ( PassThru ) ; Ops . push_back ( MGN -> getBasePtr ( ) ) ; Ops . push_back ( Index ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , MGN -> getMemoryVT (


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI


<s> return <ISA_LIT>Operand :: CreateImm ( this , <NUM_LIT> , SMLoc

( ) , <ISA_LIT>Operand :: ImmTyOffset ) ;


<s> return ( vector signed int ) __builtin_altivec_vcmpgtfp ( ( vector float )


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( VarArgsNumGPR , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( VarArgsNumFPR , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( VarArgsStackOffset , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant


<s> Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isSingleFloat ( ) ) for ( unsigned FReg = ( <STR_LIT> ) + <NUM_LIT> ; FReg < <STR_LIT> ; FReg += <NUM_LIT> )


<s> static bool allocateStack ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { unsigned Offset = State . AllocateStack ( ValVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S


<s> __arm_vld1q_s32 ( int32_t const * __base ) { return __builtin_mve_vld1q_sv4si ( ( __builtin_neon_si *


<s> MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: BCvt : { llvm_unreachable ( <STR_LIT> ) ; break ; } } unsigned ArgReg ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { ArgReg = NextFPR ++ ; if ( CC != CallingConv :: Fast ) ++ NextGPR ; } else ArgReg = NextGPR ++ ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ArgReg


<s> static unsigned maxLongNopLength ( const <ISA_LIT>Subtarget * Subtarget ) { if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] || Subtarget -> is64Bit ( ) ) return <NUM_LIT> ; if ( Subtarget -> is32Bit ( ) ) return <NUM_LIT> ; return


<s> if ( ! MF . getName ( ) . startswith ( getDerived ( ) . getThunkPrefix ( ) ) ) { if ( InsertedThunks ) return false ; if ( ! getDerived ( ) . mayUseThunk ( MF ) ) return false ; getDerived ( ) . insertThunks ( MMI ) ; InsertedThunks = true ; return true ; } getDerived ( ) .


<s> enum machine_mode mode = TYPE_MODE ( valtype ) ; if ( ! POINTER_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , FIRST_DATA_REGNUM ) ; else if ( ! TARGET_PTR_A0D0 || ! outgoing || current_function_returns_struct ) return gen_rtx_REG ( mode , FIRST_ADDRESS_REGNUM ) ; rv = gen_rtx_PARALLEL ( mode , rtvec_alloc (


<s> } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != - <NUM_LIT> && <STR_LIT> ) ; const MachineConstantPoolEntry & CPE = MCP -> getConstants ( ) [ CPI ] ; assert ( ! CPE . isMachineConstantPoolEntry ( ) && <STR_LIT> ) ; Offset = - cast < ConstantInt > ( CPE . Val . ConstVal ) -> getSExtValue ( ) ; break ; } } if ( DstReg == FramePtr && FramePtr != <STR_LIT> ) ATS . emitSetFP ( FramePtr , <STR_LIT> , - Offset ) ; else if ( DstReg == <STR_LIT> ) { ATS . emitPad ( Offset ) ; } else { MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; } } else if ( DstReg == <STR_LIT> ) { MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; } else { MI -> dump ( )


<s> init_edge -> probability = profile_probability :: even ( ) ; gimple_seq init_seq = NULL ; tree init_var = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( init_var , init , & init_seq ) ; gsi = gsi_start_bb ( init_bb ) ; gsi_insert_seq_before ( & gsi , init_seq , GSI_SAME_STMT ) ; gsi_prev ( & gsi ) ; edge inited_edge = split_block ( gsi_bb ( gsi ) , gsi_stmt ( gsi ) ) ; basic_block dst_bb = inited_edge -> dest ; edge nop_edge = make_edge ( call_bb , dst_bb , EDGE_FALSE_VALUE ) ; nop_edge -> probability = profile_probability :: even ( ) ; gphi * phi = create_phi_node ( lhs , dst_bb ) ; add_phi_arg ( phi , init_var , inited_edge , gimple_location ( call ) ) ; add_phi_arg ( phi , var , nop_edge , gimple_location ( call ) ) ; set_immediate_dominator ( CDI_DOMINATORS , dst_bb , call_bb ) ; gsi = gsi_for_stmt ( call ) ; } else { if ( level == GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; if ( integer_zerop ( ref_to_res ) ) init = var ; } if ( lhs != NULL_TREE ) gimplify_assign ( lhs , init , & seq ) ; } pop_gimplify_context ( NULL


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> } if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return total_auto_space ; } if ( from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) { return total_saved_regs_space ; } if ( from == RETURN_ADDRESS_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return total_saved_regs_space + total_auto_space


<s> return new <ISA_LIT>MCCodeEmitter ( MCII ,


<s> const TargetRegisterClass * TRC = TargetRegisterInfo :: isVirtualRegister ( RegNo ) ? MRI -> getRegClass ( RegNo ) : MRI -> getTargetRegisterInfo ( ) -> getMinimalPhysRegClass ( RegNo ) ; for ( MVT T : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( TRC -> hasType ( T ) ) return T ; DEBUG ( errs ( ) << <STR_LIT> << RegNo ) ; llvm_unreachable ( <STR_LIT> ) ; return <STR_LIT>


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ; Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics >


<s> MachineFunction * MF = MBB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DenseSet < unsigned > SGPRSpillVGPRDefinedSet ; ArrayRef < <ISA_LIT>MachineFunctionInfo :: SpilledReg > VGPRSpills = MFI -> getSGPRToVGPRSpills ( Index ) ; bool SpillToVGPR = ! VGPRSpills . empty ( ) ; if ( OnlyToVGPR && ! SpillToVGPR ) return false ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; Register SuperReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; assert ( SpillToVGPR || ( SuperReg != MFI -> getStackPtrOffsetReg ( ) && SuperReg != MFI -> getFrameOffsetReg ( ) ) ) ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; Register TmpVGPR ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; if ( ! TmpVGPR . isValid ( ) ) TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( SubReg , SubKillState ) ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == e ) SuperKillState |= getKillRegState ( IsKill


, ( unsigned char ) __imm , ( __mmask8 ) __U ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isImm ( ) ) O << formatImm ( Op . getImm ( ) ) ; else if ( Op . isExpr ( ) ) printExpr ( Op . getExpr ( )


<s> <STR_LIT> ExtType = LD -> getExtensionType ( ) ; SDValue Chain = LD -> getChain ( ) , Undef = DAG . getUNDEF ( VT ) ; assert ( ( VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) ; if ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) { SDValue LDL = CreateLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return CreateLoadLR ( <STR_LIT> , DAG , LD , LDL . getValue ( <NUM_LIT> ) , LDL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } SDValue LWL = CreateLoadLR ( <STR_LIT> , DAG , LD , Chain , Undef , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; SDValue LWR = CreateLoadLR ( <STR_LIT> , DAG , LD , LWL . getValue ( <NUM_LIT> ) , LWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( VT == <STR_LIT> ) || ( ExtType == <STR_LIT> ) || ( ExtType == <STR_LIT> ) ) return LWR ; assert ( ( VT == <STR_LIT> ) && ( ExtType == <STR_LIT> ) ) ; DebugLoc DL = LD -> getDebugLoc ( ) ; SDValue Const32 = DAG . getConstant (


<s> PHINode * PhiInst = dyn_cast < PHINode > ( * Use ) ; Instruction * InsertionPoint ; if ( PhiInst ) InsertionPoint = PhiInst -> getIncomingBlock (

Use . getOperandNo ( ) ) -> getTerminator ( ) ;


<s> setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To ,


<s> CallGraphSCC CurSCC ( CG , & CGI ) ; bool Changed = false ; for ( ; ! CGI . isAtEnd ( ) ; ++ CGI ) { CurSCC . initialize ( * CGI ) ; Changed |= runOnSCC ( CurSCC ) ; } for ( Function & F : M . functions ( ) ) { if ( F . hasFnAttribute ( <STR_LIT> ) ) { HasInterrupts = true ; markReachableFromMultipleInterrupts ( * CG [ & F ] ) ; } } for ( Function & F : M . functions ( ) ) { if ( F . hasFnAttribute ( <STR_LIT> ) || F . getName ( ) == <STR_LIT> ) { if ( F . hasFnAttribute ( <STR_LIT> ) ) HasInterrupts = true ; visitNorecurseInterrupt ( * CG [ & F ] ) ; for ( const auto * CGN : ReachableFromCurrentNorecurseInterrupt ) ReachableFromOtherNorecurseInterrupt . insert ( CGN ) ; ReachableFromCurrentNorecurseInterrupt . clear ( ) ; } } if ( HasInterrupts ) { Changed = true ; for ( const char * LibcallName : lto :: LTO :: getRuntimeLibcallSymbols ( ) ) { Function * Libcall = M . getFunction ( LibcallName ) ; if ( Libcall && ! Libcall -> isDeclaration ( ) && Libcall -> doesNotRecurse ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Libcall


<s> const MachineOperand & Disp = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( Base . isGlobal ( ) ) printOperand ( MI , OpNum , <STR_LIT> ) ; else if ( Disp . isImm ( ) && ! Base . getReg ( ) ) printOperand ( MI , OpNum ) ; else if ( Base . getReg ( ) ) { if ( Disp . getImm ( ) ) { printOperand ( MI , OpNum + <NUM_LIT> ,


<s> bool <ISA_LIT>LegalizerInfo :: legalizeUDIV_UREM32 ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { const bool IsDiv = MI . getOpcode ( ) == <STR_LIT> ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Num = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Den = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; legalizeUDIV_UREM32Impl ( B , DstReg , Num , Den , IsDiv ) ; MI . eraseFromParent ( ) ; return true


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O


<s> if ( X . getValueType ( ) == VT ) return X ; } if ( Op0 . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue BV = Op0 . getOperand ( <NUM_LIT> ) ; unsigned Offset = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue MOV = BV . getOperand ( Offset < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( MOV . getOpcode ( ) == <STR_LIT> ) return MOV . getOperand ( ST -> isLittle ( ) ? Offset % <NUM_LIT> : <NUM_LIT> - Offset % <NUM_LIT> ) ; } if ( SDValue R = PerformExtractEltToVMOVRRD ( N , DCI ) ) return R ; return SDValue (


<s> QST = & Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; QRI = QST -> getRegisterInfo ( ) ; QII = QST -> getInstrInfo ( ) ; std :: vector < MachineInstr * > VecPrintList ; for ( auto & MBB : Fn ) for ( auto & MI : MBB ) { if ( MI . isBundle ( ) ) { MachineBasicBlock :: instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB . instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getNumOperands ( ) < <NUM_LIT> ) continue ; unsigned Reg = <NUM_LIT> ; if ( getInstrVecReg ( * MII , Reg ) ) { VecPrintList . push_back ( ( & * MII ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; MII -> dump ( ) ) ; } } } else { unsigned Reg = <NUM_LIT> ; if ( getInstrVecReg ( MI , Reg ) ) { VecPrintList . push_back ( & MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; } } } Changed = ! VecPrintList . empty ( ) ; if ( ! Changed ) return Changed ; for ( auto * I : VecPrintList ) { DebugLoc DL = I -> getDebugLoc ( ) ; MachineBasicBlock * MBB = I -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; unsigned Reg = <NUM_LIT> ; if ( ! getInstrVecReg ( * I , Reg ) ) llvm_unreachable ( <STR_LIT> ) ; MachineBasicBlock :: instr_iterator MII = I -> getIterator ( ) ; if ( I -> isInsideBundle ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; while ( MBB -> instr_end ( ) != MII && MII -> isInsideBundle ( ) ) MII ++ ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : return false ; case <STR_LIT> : case <STR_LIT> : return false ; } const MachineOperand & MO = I ->


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * CFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; CFI -> setSpillsCR ( ) ; } else if ( v2sf && <STR_LIT> . hasSubClassEq ( RC )


<s> MI . eraseFromParent ( ) ; return true ; } assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < Register , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size ( ) != <NUM_LIT> ) { assert ( Results . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildOr ( OriginalResult , Results [ <NUM_LIT> ] , Results [ <NUM_LIT> ] ) ; } break ; } case G_FCONSTANT


<s> FunctionPass * llvm :: create<ISA_LIT>DeadRegisterDefinitions


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg ( SrcReg


<s> return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Mode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } return


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( isKill ) ) . addReg ( TRI -> getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT>


<s> void reset ( ) { TentativelyCommuting =


<s> SDValue AddcOp0 = AddcNode -> getOperand ( <NUM_LIT> ) ; SDValue AddcOp1 = AddcNode -> getOperand ( <NUM_LIT> ) ; if ( AddcOp0 . getNode ( ) == AddcOp1 . getNode ( ) ) return SDValue ( ) ; assert ( AddcNode -> getNumValues ( ) == <NUM_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( AddeNode == NULL ) return SDValue ( ) ; if ( AddeNode -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( AddeNode -> getNumOperands ( ) == <NUM_LIT> && AddeNode -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue AddeOp0 = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue AddeOp1 = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue


<s> case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand


<s> if ( SecName . startswith ( <STR_LIT> ) ) visitMapDefType ( DIGlobal -> getType ( ) , GVTypeId ) ; else visitTypeEntry ( DIGlobal -> getType ( ) , GVTypeId , false , false ) ; break ; } auto Linkage = Global . getLinkage ( ) ; if ( Linkage != GlobalValue :: InternalLinkage && Linkage != GlobalValue :: ExternalLinkage && Linkage != GlobalValue :: WeakAnyLinkage && Linkage != GlobalValue :: WeakODRLinkage && Linkage != GlobalValue :: ExternalWeakLinkage ) continue ; uint32_t GVarInfo ; if ( Linkage == GlobalValue :: InternalLinkage ) { GVarInfo = <STR_LIT> ; } else if ( Global . hasInitializer ( ) ) { GVarInfo = <STR_LIT> ; } else { GVarInfo = <STR_LIT> ; } auto VarEntry = std :: make_unique < BTFKindVar > ( Global . getName ( ) , GVTypeId , GVarInfo ) ; uint32_t VarId = addType ( std :: move ( VarEntry ) ) ; processDeclAnnotations ( DIGlobal -> getAnnotations ( ) , VarId , - <NUM_LIT> ) ; if ( SecName . empty ( ) ) continue ; if ( DataSecEntries . find ( std :: string ( SecName )


<s> if ( allowsUnalignedMemoryAccesses ( ST -> getMemoryVT ( ) ) ) { return SDValue ( ) ; } unsigned ABIAlignment = getDataLayout ( ) -> getABITypeAlignment ( ST -> getMemoryVT ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( ST -> getAlignment ( ) >= ABIAlignment ) { return SDValue ( ) ; } SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ST -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } unsigned AS = ST -> getAddressSpace ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ,


<s> if ( Ext == <STR_LIT> ) IsLSL = true ; else if ( Ext != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; int64_t Imm = MO . getImm ( ) ; if ( ( ! IsLSL || ( IsLSL && isHalf ) ) && Imm != <NUM_LIT> && Imm != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; if ( IsLSL && ( Imm < <NUM_LIT> || Imm > <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; if ( ! IsLSL ) Imm ++ ; Imm *= <NUM_LIT> ; if ( IsLSL ) { if ( Imm == <NUM_LIT> ) return ; O << <STR_LIT> ; } else O << <STR_LIT> ; O << <STR_LIT> <<


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case


<s> bool MachineConstEvaluator :: getCell ( const RegisterSubReg & R , const CellMap & Inputs , LatticeCell & RC ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( R . Reg ) ) return false ; const LatticeCell & L = Inputs . get ( R . Reg ) ; if ( ! R . SubReg ) { RC = L ; return ! RC . isBottom (


<s> imported [ ( int ) code ] = <NUM_LIT> ; strcpy ( str , import_string ) ; memcpy ( str + MILLI_START , milli_names [ ( int


<s> return ComputeMaxSignificantBits ( Op , * DL ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getT2AddrModeSORegOpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO1 = MI . getOperand ( OpNum ) ; const MCOperand & MO2 = MI . getOperand ( OpNum + <NUM_LIT> ) ; const MCOperand & MO3 = MI . getOperand ( OpNum + <NUM_LIT> ) ; unsigned Value = get<ISA_LIT>RegisterNumbering ( MO1 . getReg ( ) ) ; Value <<= <NUM_LIT>


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __A ) ; b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( a , float_exp_mask ) ; d = ( __vector unsigned int ) vec_cmpgt ( b , float_exp_mask ) ; c = vec_or ( c , d ) ; return ( ( __m128 ) vec_sel ( ( __v4sf ) __A ,


<s> else if ( OpNo >= Desc . getNumDefs ( ) && ! IsVariadicDef ) O << <STR_LIT> << <ISA_LIT>FunctionInfo :: getWARegStackId ( WAReg ) ; else if ( WAReg != <ISA_LIT>FunctionInfo :: UnusedReg ) O << <STR_LIT> << <ISA_LIT>FunctionInfo :: getWARegStackId ( WAReg ) ; else O << <STR_LIT> ; if ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumDefs ( ) || IsVariadicDef ) O << '=' ; } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op . isSFPImm ( ) ) { O << :: toString ( APFloat ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , Op . getSFPImm ( ) ) ) ) ; } else if ( Op . isDFPImm (


<s> if ( regno == LO_REGNUM ) return LO_REGS ; if ( regno == HI_REGNUM ) return HI_REGS ; return NO_REGS


<s> static bool isSimpleBD12Move ( const MachineInstr * MI , unsigned Flag ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; return ( ( MCID . TSFlags & Flag ) && isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) )

&& MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) ;


<s> std :: pair < bool , SDNode * > Ret = selectNode ( Node ) ; if ( Ret . first ) return Ret . second ; switch ( Opcode ) { default : break ; case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> : case <STR_LIT> : assert ( cast < MemSDNode > ( Node ) -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> <= cast < MemSDNode > ( Node ) -> getAlignment ( ) && <STR_LIT> ) ; break ; } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT>


<s> static machine_mode msp430_get_raw_arg_mode ( int regno ) { return ( regno == ARG_POINTER_REGNUM ) ? VOIDmode


<s> SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Op . getNumOperands ( ) ; bool IsMasked = NumOps == <NUM_LIT> ; unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue VL = Op . getOperand ( NumOps - <NUM_LIT> ) ; SDValue I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; MVT I32MaskVT = <STR_LIT> ( <STR_LIT> , I32VT . getVectorElementCount ( ) ) ; SDValue I32Mask = DAG . getNode ( <STR_LIT> , DL , I32MaskVT , VL ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec