<s> unsigned StoreSize = VT . getStoreSizeInBits ( ) ; if ( StoreSize <= <NUM_LIT> ) return EVT :: getIntegerVT ( Ctx , StoreSize ) ; assert ( StoreSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; return EVT :: getVectorVT ( Ctx , <STR_LIT> , StoreSize


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> ) && TYPE_VECTOR_SUBPARTS ( type ) > <NUM_LIT> ) { machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) mode = MIN_MODE_VECTOR_FLOAT ; else mode = MIN_MODE_VECTOR_INT ; for ( ; mode != VOIDmode ; mode = GET_MODE_WIDER_MODE ( mode ) ) if ( GET_MODE_NUNITS ( mode ) == TYPE_VECTOR_SUBPARTS ( type ) && GET_MODE_INNER ( mode ) == innermode ) { if ( size == <NUM_LIT> && ! TARGET_AVX512F ) { static bool warnedavx512f ; static bool warnedavx512f_ret ; if ( cum && cum -> warn_avx512f && ! warnedavx512f ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx512f = true ; } else if ( in_return && ! warnedavx512f_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx512f_ret = true ; } return TYPE_MODE ( type ) ; } else if ( size == <NUM_LIT> && ! TARGET_AVX ) { static bool warnedavx ; static bool warnedavx_ret ; if ( cum && cum -> warn_avx && ! warnedavx ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx = true ; } else if ( in_return && ! warnedavx_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedavx_ret = true ; } return TYPE_MODE ( type ) ; } else if ( ( ( size == <NUM_LIT> && TARGET_64BIT ) || size == <NUM_LIT> ) && ! TARGET_SSE ) { static bool warnedsse ; static bool warnedsse_ret ; if ( cum && cum -> warn_sse && ! warnedsse ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse = true ; } else if ( ! TARGET_64BIT && in_return && ! warnedsse_ret ) { if ( warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ) warnedsse_ret = true ; } } else if ( ( size == <NUM_LIT> && ! TARGET_64BIT ) && ! TARGET_MMX ) { static bool


<s> RegisterTarget < Triple :: eclair > X ( getThe<ISA_LIT>Target ( ) ,


<s> if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand ::


<s> for ( int i = <NUM_LIT> , e = std :: min ( MI -> getNumOperands ( ) , ( unsigned ) MI -> getDesc ( ) . NumOperands ) ; i < e ; ++ i ) { const TargetOperandInfo & TOI = MI -> getDesc ( ) . OpInfo [ i ] ; if ( TOI . isPredicate ( ) ) continue ; const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; const TargetRegisterClass * sideRC = MRI . getRegClass ( MO


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , Is64Bit , IsLittleEndian ) ; return createELFObjectWriter ( MOTW , OS


<s> switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Xor = IsRHSZero ? LHS : SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; SDValue Clz = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor ) , <NUM_LIT> ) ; SDValue ShiftOps [ ] = { Clz , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ShiftOps ) , <NUM_LIT> ) ; } case <STR_LIT> :


<s> __inline__ static void sh_media_unaligned_ST_W ( void * p , unsigned int k ) { char * addr = p ; addr [ <NUM_LIT>


<s> if ( const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ( uint32_t ) ImmVal != ( uint64_t ) ImmVal ) return false ; Imm = CurDAG -> getTargetConstant ( ImmVal , <STR_LIT> ) ; return true ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; Imm = N


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveRegX ( unsigned Reg , int Offset


<s> rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return <NUM_LIT> ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; return ( use_ldrd && offset > - <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) || ( TARGET_HAVE_MVE && VALID_MVE_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return <NUM_LIT> ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ; return


<s> if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg

. getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ;


<s> static <ISA_LIT>Operand * CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg


<s> bool <ISA_LIT>ELFAttributeData :: usingThumb ( ) const { int arch = m_Attrs [ Tag_CPU_arch ] . getIntValue ( ) ; if ( ( arch == CPU_Arch_<ISA_LIT>_V6_M ) || ( arch ==

CPU_Arch_<ISA_LIT>_V6S_M ) ) return true ;


<s> static const <ISA_LIT>MCExpr * CreateABS_G0_NC ( const MCExpr * Expr , MCContext


<s> CurType . Size = CurType . ElementSize ; break ; case IES_INIT : case IES_CAST : assert ( ! BracCount && <STR_LIT> ) ; State = IES_LBRAC ; break ; } MemExpr = true ; BracCount ++ ; return false


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return Bottom ; MapType :: const_iterator F = Map . find (


<s> MachineFunction & MF = B . getMF ( ) ; MachineBasicBlock & MBB = B . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const GCNSubtarget & Subtarget = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; if ( ! IsEntryFunc ) { Register ReturnAddrReg = TRI -> getReturnAddressReg ( MF ) ; Register LiveInReturn = MF . addLiveIn ( ReturnAddrReg , & <STR_LIT> ) ; MBB . addLiveIn ( ReturnAddrReg ) ; B . buildCopy ( LiveInReturn , ReturnAddrReg ) ; } if ( Info -> hasImplicitBufferPtr ( ) ) { Register ImplicitBufferPtrReg = Info -> addImplicitBufferPtr ( * TRI ) ; MF . addLiveIn ( ImplicitBufferPtrReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( ImplicitBufferPtrReg ) ; } SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; unsigned P<ISA_LIT>nputNum = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == <NUM_LIT> ) continue ; const bool InReg = Arg . hasAttribute ( Attribute :: InReg ) ; if ( ! IsShader && InReg ) return false ; if ( Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; if ( CC == CallingConv :: <ISA_LIT>_PS && ! InReg && P<ISA_LIT>nputNum <= <NUM_LIT> ) { const bool ArgUsed = ! Arg . use_empty ( ) ; bool SkipArg = ! ArgUsed && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ! SkipArg ) { Info -> markP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ArgUsed ) Info -> markP<ISA_LIT>nputEnabled ( P<ISA_LIT>nputNum ) ; } ++ P<ISA_LIT>nputNum ; if ( SkipArg


<s> bool vector_insn_info :: available_p ( const vector_insn_info & other ) const { return * this


<s> static MCStreamer * create<ISA_LIT>MCAsmStreamer ( MCContext & Ctx , formatted_raw_ostream & OS , bool isVerboseAsm , bool useCFI ,

bool useDwarfDirectory , MCInstPrinter * InstPrint , MCCodeEmitter * CE , MCAsmBackend * TAB , bool ShowInst ) {


<s> if ( ! VA . isRegLoc ( ) ) return false ; if ( TLI . getValueType ( RV -> getType ( ) ) != VA . getValVT ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; MRI . addLiveOut ( VA . getLocReg (


<s> Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> ) Known . Zero = <NUM_LIT> ; break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( MergeBB -> succ_begin ( ) == MergeBB -> succ_end ( ) ) { return ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MergeBB ) << <STR_LIT> << printReg ( DestRegister , TRI ) << <STR_LIT> << printReg ( IfSourceRegister , TRI ) << <STR_LIT> << printMBBReference ( * IfBB ) << printReg ( CodeSourceRegister , TRI ) << <STR_LIT> << printMBBReference ( * CodeBB ) << <STR_LIT> ) ; const DebugLoc & DL = MergeBB -> findDebugLoc ( MergeBB -> begin ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * MergeBB , MergeBB -> instr_begin ( ) , DL , TII -> get ( TargetOpcode :: PHI ) , DestRegister ) ; if ( IsUndefIfSource && false ) { MIB . addReg ( IfSourceRegister , RegState :: Undef ) ; } else { MIB . addReg ( IfSourceRegister ) ; } MIB . addMBB ( IfBB


<s> const <ISA_LIT>InstrInfo * getInstrInfo (


<s> bool hasFuseLiterals ( ) const { return HasFuseLiterals


<s> return insertSubVector ( Result , Vec , IdxVal , DAG , dl ,


<s> return new <ISA_LIT>GatherScatterLowering ( )


<s> * cum = ( ROUND_ADVANCE_CUM ( * cum , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg .


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel


<s> assert ( VA . getValVT ( ) . isVector ( ) ) ; Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Value ) ; return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; case CCValAssign ::


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ; unsigned CopyLen = ConstantSize -> getZExtValue ( ) ; unsigned StoresNumEstimate = alignTo ( CopyLen , Alignment ) >> Log2 ( Alignment ) ; if ( StoresNumEstimate > getCommonMaxStoresPerMemFunc (


<s> auto setVecVal = [ & ] ( int Idx ) { if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> )


<s> void function_expander :: add_mem_operand ( machine_mode mode , rtx addr ) { gcc_assert ( VECTOR_MODE_P ( mode ) || mode == OImode ) ; rtx mem = gen_rtx_MEM ( mode , memory_address (


<s> unsigned <ISA_LIT>MCCodeEmitter :: getEncodingType ( const MCInst & MI )


<s> if ( ! MO . isImm ( ) ) return false ; int64_t Offset = MO . getImm ( ) + Disp ; return isValidLoadStoreOffset ( Offset


<s> case TYPE_DIV : if ( divmod_p ( producer ) ) def_reg = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_LOAD : case TYPE_STORE : case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : if ( ! post_update_insn_p ( producer ) )


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister ( ) const { return


<s> FunctionPass * llvm :: create<ISA_LIT>MakeCompressibleOptPass


<s> unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 )


<s> } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , DoesntNeedLRSave ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT> ; } if ( std :: any_of ( RepeatedSequenceLocs [ <NUM_LIT> ] . first , RepeatedSequenceLocs [ <NUM_LIT> ] . second , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) NumInstrsToCreateFrame += <NUM_LIT> ; else if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isCall ( ) && FrameID != MachineOutlinerTailCall ) NumInstrsToCreateFrame += <NUM_LIT> ; return MachineOutlinerInfo ( NumInstrsForCall , NumInstrsToCreateFrame , CallID ,


<s> void <ISA_LIT>SchedStrategy :: MoveUnits ( std :: vector < SUnit * > & QSrc , std :: vector < SUnit * >


<s> if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; return isTypeLegal ( VT . getSimpleVT


<s> if ( Bits . size ( ) <= Idx ) Bits . resize (

std :: max ( Idx + <NUM_LIT> , <NUM_LIT> ) ) ;


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerToScalableOp


<s> bool is31 = ( getTargetMachine ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl


<s> } else { uint32_t High = ( Imm + <NUM_LIT> ) & ~ <NUM_LIT> ; uint32_t Low = ( Imm + <NUM_LIT> ) & <NUM_LIT> ; Imm = Low ; Overflow = High - <NUM_LIT> ; } } if ( Overflow > <NUM_LIT> && Subtarget -> getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) return false ; ImmOffset = CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ; if ( Overflow <= <NUM_LIT> ) SOffset = CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) ; else SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return true


<s> if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { ImmutableCallSite CS ( & I ) ; if ( const Function * F = CS . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , <NUM_LIT> , <NUM_LIT> ) ; } } unsigned const Max = ( NumStores ? ( <NUM_LIT> / NumStores ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = <NUM_LIT> ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= <NUM_LIT> ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = <NUM_LIT> ; UP . DefaultUnrollRuntimeCount


<s> unsigned <ISA_LIT>Subtarget :: getMaxELENForFixedLengthVectors ( ) const { assert ( hasStdExtV ( ) && <STR_LIT> ) ; assert ( RVVVectorELENMax <= <NUM_LIT> && RVVVectorELENMax >= <NUM_LIT> && isPowerOf2_32 ( RVVVectorELENMax ) && <STR_LIT> ) ; return PowerOf2Floor ( std :: max < unsigned > ( std :: min < unsigned > ( RVVVectorELENMax ,


<s> if ( ! ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReserveGOT ) ) { return Relocator :: BadReloc ; } <ISA_LIT>_32GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * rsym ) ; assert ( got_entry != NULL )


<s> while ( possibleDuplexes . size ( ) > <NUM_LIT> && ( ! doneShuffling ) ) { DuplexCandidate duplexToTry = possibleDuplexes . pop_back_val ( ) ; MCInst Attempt ( MCB ) ; <ISA_LIT>MCInstrInfo :: replaceDuplex ( Context , Attempt , duplexToTry ) ; <ISA_LIT>MCShuffler MCS ( Context , false , MCII , STI , Attempt ) ; if ( MCS . size ( ) == <NUM_LIT> ) { MCS . copyTo ( MCB ) ; return false ; } doneShuffling = MCS . reshuffleTo ( MCB ) ; if ( doneShuffling ) break ; } if ( doneShuffling == false


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( )

? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . is128BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is256BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is512BitVector ( ) && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) || ! isUndefOrEqual ( Mask [ i + <NUM_LIT> ] , i ) ) return false ; return true


<s> HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ; AllowsUnalignedMem = false


<s> if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , Mask , Inputs , DAG ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs , Mask ) ; return


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { <ISA_LIT>SSELevel = NoSSE ; <ISA_LIT>3DNowLevel = NoThreeDNow ; HasX87 = false ; HasNOPL = false ; HasCMov = false ; Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasVAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasVPCLMULQDQ = false ; HasGFNI = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasVBMI2 = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasVNNI = false ; HasBITALG = false ; HasSHA = false ; HasPREFETCHWT1 = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; HasSHSTK = false ; HasIBT = false ; HasSGX = false ; HasCLFLUSHOPT = false ; HasCLWB = false ; HasRDPID = false ; UseRetpoline = false ; UseRetpolineExternalThunk = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b =


<s> int32_t tmp = ( int32_t ) MO1 . getImm ( ) ; if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp & <NUM_LIT> ; return


<s> riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ; if ( step2 > <NUM_LIT> ) { insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( step2 ) ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) { rtx dwarf = riscv_adjust_libcall_cfi_epilogue ( ) ; insn = emit_insn ( gen_gpr_restore ( GEN_INT ( riscv_save_libcall_count ( mask ) ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; emit_jump_insn ( gen_gpr_restore_return (


<s> static unsigned int mcore_function_arg_boundary ( machine_mode mode


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) <<


<s> return <STR_LIT> :: getMaxNumSGPRs ( getFeatureBits ( )


<s> } } else if ( code == IOR || code == XOR ) { if ( value == <NUM_LIT> ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } } if ( code == AND && mode == SImode && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { emit_insn ( gen_andsi3 ( dest , op1 , op2 ) ) ; return ; } if ( complement_op1_p ) op1 = gen_rtx_NOT ( mode , op1 ) ; if ( complement_op2_p ) op2 = gen_rtx_NOT ( mode , op2 ) ; if ( ! complement_op1_p && complement_op2_p ) std ::


<s> while ( I != MBB . instr_begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isTerminator ( ) )


<s> case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex


<s> <STR_LIT> CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( CC == <STR_LIT> && getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; return CC


<s> if ( Trace ) { dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Print < RefMap > ( LiveIn , DFG ) << '\n' ; dbgs ( ) << <STR_LIT> << Print < RegisterAggr > ( LiveMap [ B ] , DFG ) << '\n' ; } for ( auto I : DFG . getFunc ( ) . Addr -> findBlock ( B , DFG ) . Addr -> members ( DFG ) ) { NodeAddr < InstrNode * > IA = I ; if ( IA . Addr -> getKind ( ) != NodeAttrs :: Stmt ) continue ; for ( NodeAddr < UseNode * > UA : IA . Addr -> members_if ( DFG . IsUse , DFG ) ) { if ( UA . Addr -> getFlags ( ) & NodeAttrs :: Undef ) continue ; RegisterRef RR = PRI . normalize ( UA . Addr -> getRegRef ( DFG ) ) ; for ( NodeAddr < DefNode * > D : getAllReachingDefs ( UA ) ) if ( getBlockWithRef ( D . Id ) != B ) LiveIn [ RR . Reg ] . insert ( { D . Id , RR . Mask } ) ; } } if ( Trace ) { dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Print < RefMap > ( LiveIn , DFG ) << '\n' ; dbgs ( ) << <STR_LIT> << Print < RegisterAggr > ( LiveMap [ B ] , DFG ) << '\n' ; } RegisterAggr & Local = LiveMap [ B ] ; RefMap & LON = PhiLON [ B ] ; for ( auto & R : LON ) { LaneBitmask M ; for ( auto P : R . second ) M |= P . second ; Local . insert ( RegisterRef ( R . first , M ) ) ; } if ( Trace ) { dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Print < RefMap > ( LiveIn , DFG


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t Upper , Twine Msg = <STR_LIT> ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] )


<s> } ; SDValue MulOp , OtherOp ; if ( UsePMADDWD ( Op0 ) ) { MulOp = Op0 ; OtherOp = Op1 ; } else if ( UsePMADDWD ( Op1 ) ) { MulOp = Op1 ; OtherOp = Op0 ; } else return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT OpVT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , OpVT , Ops ) ; } ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , Madd


<s> static bool isLegalArithImmed ( uint64_t C ) { return ( C >> <NUM_LIT> == <NUM_LIT> ) || ( ( C & <NUM_LIT> )

== <NUM_LIT> && C >> <NUM_LIT> == <NUM_LIT> ) ;


<s> return DT -> dominates ( BB , EB ) ; } ; if ( ! std :: all_of ( ExitBlocks . begin ( ) , ExitBlocks . end ( ) , DominatedByBB ) ) return false ; bool MadeChange = false ; SmallVector < StoreInst * , <NUM_LIT> > Stores ; collectStores ( CurLoop , BB , Stores ) ; for ( auto & SI : Stores ) MadeChange |= processCopyingStore ( CurLoop , SI , BECount ) ; return


<s> assert ( Inst . mayLoad ( ) || Inst . mayStore ( ) ) ; if ( TII -> usesVM_CNT ( Inst ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; if ( TII -> usesLGKM_CNT ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; if ( mayAccessLDSThroughFlat ( Inst ) ) ScoreBrackets -> setPendingFlat ( ) ; } } else if ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; } else { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SQ_MESSAGE , Inst ) ; break ; case <STR_LIT> : case <STR_LIT> : { int Imm = TII -> getNamedOperand ( Inst , <STR_LIT> :: tgt ) -> getImm ( ) ; if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_PARAM_ACCESS , Inst ) ; else if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_POS_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI ,


<s> EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { NegatibleCost V = getNegatibleCost ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; if ( V == NegatibleCost :: Cheaper ) NewOps [ i ] = getNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; } bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; for ( int i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc


<s> static inline const MachineInstrBuilder & addOffset ( const

MachineInstrBuilder & MIB , int Offset ) {


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; for ( size_t i = <NUM_LIT> ; i <


<s> if ( IID == <STR_LIT> ) { HaveCall = true ; copyFeaturesToFunction ( F , * Callee , NeedQueuePtr ) ; Changed = true ; } else { bool NonKernelOnly = false ; if ( ! IsFunc && IID == <STR_LIT> ) { F . addFnAttr ( <STR_LIT> ) ; } else { StringRef AttrName = intrinsicToAttrName ( IID , NonKernelOnly , NeedQueuePtr ) ; if ( ! AttrName . empty ( ) && ( IsFunc || ! NonKernelOnly ) ) { F . addFnAttr ( AttrName ) ; Changed = true ; } } } } if ( NeedQueuePtr || ( ! IsFunc && HasApertureRegs ) ) continue ; if ( const AddrSpaceCastInst * ASC = dyn_cast < AddrSpaceCastInst > ( & I ) ) { if ( ! HasApertureRegs && castRequiresQueuePtr ( ASC ) ) { NeedQueuePtr = true ; continue ; } } for ( const Use & U : I . operands ( ) ) { const auto * OpC = dyn_cast < Constant > ( U ) ; if ( ! OpC ) continue


<s> const <ISA_LIT>TargetLowering & TLI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) ; const auto & LibInfo = getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( ) ; LiveIntervals & LIS = getAnalysis < LiveIntervals > ( ) ; bool Changed = false ; MRI . leaveSSA ( ) ; assert ( MRI . tracksLiveness ( ) && <STR_LIT> ) ; for ( auto & MBB : MF ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << '\n' ) ; for ( auto & MI : MBB ) switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT>


<s> case PROCESSOR_2964_Z13 : case PROCESSOR_ARCH12 : if ( get_attr_z13_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_z13_expanded ( insn ) ) mask |= S390_SCHED_ATTR_MASK_EXPANDED ; if ( get_attr_z13_endgroup ( insn ) ) mask |= S390_SCHED_ATTR_MASK_ENDGROUP ; if ( get_attr_z13_groupalone ( insn )

) mask |= S390_SCHED_ATTR_MASK_GROUPALONE ;


<s> MachineInstr * MI = MBB -> getParent ( ) -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DL ) ; MBB -> push_back ( MI ) ; SHOWNEWINSTR ( MI


<s> MCInst const & getDesc ( ) const { return * ID


<s> MCOperand ATReg = MCOperand :: CreateReg ( <STR_LIT> ) ; BaseReg = ATReg ; MCInsts . resize ( <NUM_LIT> ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , ATReg , MCOperand :: CreateImm ( Hi ) ) ; CreateMCInst ( MCInsts [ <NUM_LIT> ] , <STR_LIT> , ATReg , ATReg , SPReg ) ; } MCInst


<s> static void c6x_clear_sched_context ( void * _sc ) { c6x_sched_context_t sc = ( c6x_sched_context_t ) _sc ; gcc_assert ( _sc != NULL ) ; free ( sc -> prev_cycle_state_ctx )


<s> <ISA_LIT>Relocator :: Result thm_jump8 ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { Relocator :: DWord P = pReloc . place ( ) ; Relocator :: DWord A = helper_sign_extend ( ( pReloc . target ( ) &

<NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> ) + pReloc . addend ( ) ;


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >>


<s> return ( ( qword ) ( vec_rl ( ( vec_uint4 ) ( a ) , vec_splat ( ( vec_uint4 ) ( si_from_int (


<s> unsigned bytes = Desc . getSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < bytes ; i ++ ) { OS . write ( ( uint8_t ) ( ( Encoding >> ( <NUM_LIT> * i ) ) & <NUM_LIT> ) ) ; } if ( bytes > <NUM_LIT> ) return ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; ++ i ) { if ( ! isSrcOperand ( Desc , i ) ) continue ; const MCOperand & Op = MI . getOperand ( i ) ; if ( getLitEncoding ( Op


<s> int SplatValue = * FirstDefinedIdx ; if ( any_of ( make_range ( std :: next ( FirstDefinedIdx ) , Mask . end ( ) ) , [ & SplatValue ] ( int Elt ) { return Elt >= <NUM_LIT> && Elt != SplatValue ; } ) ) return None ; return SplatValue


<s> MachineBasicBlock * LoopHeader = LoopRep -> getHeader ( ) ; MBBVector ExitingMBBs ; LoopRep -> getExitingBlocks ( ExitingMBBs ) ; assert ( ! ExitingMBBs . empty ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ExitingMBBs . size ( ) << <STR_LIT> ; ) ; MBBVector ExitBlks ; LoopRep -> getExitBlocks ( ExitBlks ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > ExitBlkSet ; for ( unsigned i = <NUM_LIT> , e = ExitBlks . size ( ) ; i < e ; ++ i ) ExitBlkSet . insert ( ExitBlks [ i ] ) ; assert ( ExitBlkSet . size ( ) == <NUM_LIT> ) ; MachineBasicBlock * ExitBlk = * ExitBlks . begin ( ) ; assert ( ExitBlk && <STR_LIT>


<s> MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ; Moves . push_back ( MachineMove ( <NUM_LIT> ,


<s> VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT


<s> } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) { auto HSUBBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HSUBBuilder ) ; } if ( SDValue V = combineIncDecVector ( N , DAG ) ) return V ; if ( SDValue V = combineSubToSubus ( N , DAG , Subtarget ) ) return V ; return combineAddOrSubToADCOrSBB ( N , DAG


<s> static bool s390_return_in_memory ( const_tree type , const_tree fundecl ATTRIBUTE_UNUSED ) { if ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == OFFSET_TYPE || TREE_CODE ( type ) == REAL_TYPE ) return int_size_in_bytes ( type ) > <NUM_LIT> ; if ( TARGET_VX_ABI && VECTOR_TYPE_P ( type ) && int_size_in_bytes (


<s> bool sparc_tls_referenced_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return


<s> machine_mode mode = GET_MODE ( x ) ; int words , cost ; switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : return ( mode == SImode ) ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; case PLUS : case MINUS : if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) || ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; case COMPARE : case NEG : case NOT : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MULT : if ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { int const_size = thumb1_size_rtx_costs ( XEXP ( x , <NUM_LIT> ) , CONST_INT , SET ) ; if ( arm_arch6m && arm_m_profile_small_mul ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else return COSTS_N_INSNS ( <NUM_LIT> ) + const_size ; } return COSTS_N_INSNS ( <NUM_LIT> ) ; case SET : words = ARM_NUM_INTS ( GET_MODE_SIZE ( GET_MODE ( SET_DEST ( x ) ) ) ) ; cost = COSTS_N_INSNS ( words ) ; if ( satisfies_constraint_J ( SET_SRC ( x ) ) || satisfies_constraint_K ( SET_SRC ( x ) ) || ( CONST_INT_P ( SET_SRC ( x ) ) && UINTVAL ( SET_SRC ( x ) ) >= <NUM_LIT> && TARGET_HAVE_MOVT && satisfies_constraint_j ( SET_SRC ( x ) ) ) || ( ( words > <NUM_LIT> ) && MEM_P ( SET_SRC ( x ) ) ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; return cost ; case CONST_INT : if ( outer == SET ) { if ( UINTVAL ( x ) < <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_HAVE_MOVT && ! ( INTVAL ( x ) & <NUM_LIT> ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) <= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( thumb_shiftable_const ( INTVAL ( x ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return arm_disable_literal_pool ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( ( outer == PLUS || outer == COMPARE ) && INTVAL (

x ) < <NUM_LIT> && INTVAL ( x ) > - <NUM_LIT> ) return <NUM_LIT> ;


<s> const unsigned Mask = <NUM_LIT> ; ArgDescriptor Arg ; if ( Info . hasWorkItemIDX ( ) ) { Arg = allocateVGPR32Input ( CCInfo , Mask ) ; Info . setWorkItemIDX ( Arg ) ; } if ( Info . hasWorkItemIDY


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; C = & MF . getFunction ( ) . getContext ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Changed = runOnBasicBlocks (


<s> if ( ! I -> isDeclaration ( ) && ! I -> hasExternalLinkage ( ) ) continue ; MCSymbol * Sym = Mang -> getSymbol ( I ) ; if ( I -> isDeclaration ( ) && PAN :: isMemIntrinsic ( Sym -> getName ( ) ) ) continue ; const char * directive = I -> isDeclaration ( ) ? MAI -> getExternDirective ( ) : MAI -> getGlobalDirective ( ) ; OutStreamer . EmitRawText ( directive + Twine (


<s> rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) =


<s> bool <ISA_LIT>InstrInfo :: isMov ( unsigned Opcode ) const { switch ( Opcode ) { default : return


<s> static bool isSupportedType ( const DataLayout & DL , const <ISA_LIT>TargetLowering & TLI , Type * T ) { EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger ( ) || VT . isFloatingPoint ( ) ) ) return false ; unsigned VTSize = VT . getSimpleVT (


<s> tree fntype = rs6000_builtin_info [ inst -> bifid ] . fntype ; tree parmtype0 = TREE_VALUE ( TYPE_ARG_TYPES ( fntype ) ) ; tree parmtype1 = TREE_VALUE ( TREE_CHAIN ( TYPE_ARG_TYPES ( fntype ) ) ) ; if ( rs6000_builtin_type_compatible ( types [ <NUM_LIT> ] , parmtype0 ) && rs6000_builtin_type_compatible ( types [ <NUM_LIT> ]


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( ! TM . isPositionIndependent ( ) ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA , TGA ) ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue TLSAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA , TGA ) ; SDValue DtvOffsetHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TLSAddr , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> if ( ST -> hasAltivec ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( ST -> is<ISA_LIT>64 ( )


<s> bool <ISA_LIT>ConstantIslands :: fixupConditionalBr ( ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return


<s> <ISA_LIT>VSXSwapRemoval ( ) : MachineFunctionPass


<s> SDValue <ISA_LIT>CC ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>CC , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt


<s> if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT>


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Wd_in = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Fs = MI . getOperand (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ResultTy = Extend -> getType ( ) ; if ( ResultTy -> getPrimitiveSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } } Value * Offsets ; Value * BasePtr = checkGEP ( Offsets , ResultTy , Ptr , Builder ) ; if ( ! BasePtr ) return nullptr ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , OriginalTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; Root = Extend ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( Unsigned ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder .


<s> if ( GET_CODE ( op ) == SUBREG && mode == SImode && REG_P ( SUBREG_REG ( op ) ) && GET_MODE ( SUBREG_REG ( op ) ) == DFmode ) return true ; if ( GET_CODE ( op ) == SUBREG && mode == DFmode && REG_P ( SUBREG_REG ( op ) ) && GET_MODE (

SUBREG_REG ( op ) ) == DImode ) return true ;


<s> static __inline unsigned long long sh_media_MMUL_W ( unsigned long long mm , unsigned long long


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; unsigned CurOp = <NUM_LIT> + NF ; MVT IndexVT ; addVectorLoadStoreOperands ( Node , ScalarSize , DL , CurOp , IsMasked


<s> if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString (


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) { MCAsmParserExtension :: Initialize ( _Parser ) ; MRI = & getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~


<s> static SDValue LowerMUL ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( VT . is128BitVector ( ) && VT . isInteger ( ) && <STR_LIT> ) ; SDNode * N0 = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * N1 = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; unsigned NewOpc = <NUM_LIT> ; bool isMLA = false ; bool isN0SExt = isSignExtended ( N0 , DAG ) ; bool isN1SExt = isSignExtended ( N1 , DAG ) ; if ( isN0SExt && isN1SExt ) NewOpc = <STR_LIT> ; else { bool isN0ZExt = isZeroExtended ( N0 , DAG ) ; bool isN1ZExt = isZeroExtended ( N1 , DAG ) ; if ( isN0ZExt && isN1ZExt ) NewOpc = <STR_LIT> ; else if ( isN1SExt || isN1ZExt ) { if ( isN1SExt && isAddSubSExt ( N0 , DAG )


<s> EVT NarrowVT = Narrow . getValueType ( ) ; if ( Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> && Narrow -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = Narrow -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Narrow -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( Narrow ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ; if ( ! RHSTrunc && ! <STR_LIT> ( N1 . getNode ( ) ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , VT ) ) return SDValue ( ) ; N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( RHSTrunc ) N1 = N1 . getOperand ( <NUM_LIT> ) ; else N1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; SDValue Op = DAG . getNode ( Narrow -> getOpcode ( ) , DL , VT , N0 , N1 ) ; unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return Op


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Src -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( int64x2_t ) __builtin_neon_vqrshlsv2di ( __a ,


<s> if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return


<s> unsigned NumElts = ArgTy -> getNumElements ( ) ; Type * IntegerVecTy = VectorType :: getInteger ( ArgTy ) ; Type * IntegerTy = Builder . getIntNTy ( NumElts ) ; Value * Res = Builder . CreateBitCast ( Arg , IntegerVecTy ) ; Res = Builder . CreateICmpSLT ( Res , Constant :: getNullValue ( IntegerVecTy ) ) ; Res = Builder . CreateBitCast ( Res , IntegerTy


<s> auto MBBStart = MBB -> instr_rend ( ) ; for ( int i = <NUM_LIT> ; ( i < SearchBound ) && ( MI != MBBStart ) ; ++ i , ++ MI ) for ( auto & Op : MI -> implicit_operands ( ) ) if ( ( Op . getReg ( ) == <STR_LIT> ) && ( Op . isDef ( ) ) ) return & * MI ; return


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , VectorType * Tp , ArrayRef < int > Mask , int Index , VectorType * SubTp , ArrayRef < Value * > Args ) { Kind = improveShuffleKindFromMask ( Kind , Mask ) ; if ( ST -> hasVector ( ) ) { unsigned NumVectors = getNumVectorRegs ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) { case TargetTransformInfo :: SK_ExtractSubvector : return ( Index == <NUM_LIT> ? <NUM_LIT> :


<s> TII -> convertNonUniformIfRegion ( CurrentMerge , IfEnd ) ; } DEBUG ( PHIInfo . dump ( MRI ) ) ; } } LRegion -> removeFalseRegisterKills ( MRI ) ; if ( LRegion -> getHasLoop ( ) ) { MachineBasicBlock * NewSucc = splitEntry ( LRegion ) ; if ( isFunctionEntryBlock ( LRegion -> getEntry ( ) ) ) { resolvePHIInfos ( LRegion -> getEntry ( ) ) ; } const DebugLoc & DL = NewSucc -> findDebugLoc ( NewSucc -> getFirstNonPHI ( ) ) ; unsigned InReg = LRegion -> getBBSelectRegIn ( ) ; unsigned InnerSelectReg = MRI -> createVirtualRegister ( MRI -> getRegClass ( InReg ) ) ; unsigned NewInReg = MRI -> createVirtualRegister ( MRI -> getRegClass ( InReg ) ) ; TII -> materializeImmediate ( * ( LRegion -> getEntry ( ) ) , LRegion -> getEntry ( ) -> getFirstTerminator ( ) , DL , NewInReg , Region -> getEntry ( ) -> getNumber ( ) ) ; LRegion -> replaceRegisterInsideRegion ( InReg , InnerSelectReg , false , MRI ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; insertMergePHI ( LRegion -> getEntry ( ) , LRegion -> getExit ( ) , NewSucc , InnerSelectReg , NewInReg , LRegion -> getRegionMRT ( ) -> getInnerOutputRegister ( ) ) ; splitExit ( LRegion ) ; TII -> convertNonUniformLoopRegion ( NewSucc , LastMerge ) ; } if ( Region -> isRoot ( ) ) { TII -> insertReturn ( * LastMerge ) ; } DEBUG ( Region -> getEntry ( ) -> getParent ( ) -> dump ( ) ) ; DEBUG ( LRegion -> print ( dbgs ( ) , TRI ) ) ; DEBUG ( PHIInfo . dump ( MRI ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; Region -> setLinearizedRegion ( LRegion


<s> return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT>


<s> assert ( Align && ( ( Align - <NUM_LIT> ) & Align ) == <NUM_LIT> ) ; StackOffset = ( ( StackOffset + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ) ; unsigned Result = StackOffset ; StackOffset +=


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; bool IsAdd = N -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsAdd || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > PostShuffleMask ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget

. hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG , Subtarget , IsAdd , PostShuffleMask ) ) {


<s> MEM_VOLATILE_P ( memsi ) = MEM_VOLATILE_P ( mem ) ; shift = loongarch_force_binary ( Pmode , AND , orig_addr , GEN_INT ( <NUM_LIT> ) ) ; loongarch_emit_binary ( ASHIFT , shift , shift , GEN_INT ( <NUM_LIT> ) ) ; shiftsi = force_reg ( SImode , gen_lowpart ( SImode , shift ) ) ; unshifted_mask = GEN_INT ( GET_MODE_MASK ( mode ) ) ; unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = loongarch_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = loongarch_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = loongarch_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_7 ( res , memsi , mask , inverted_mask , oldval , newval , model ) ; else if ( result ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , model ) ; else si_op = generator . fn_5 ( memsi , mask , inverted_mask , oldval , model ) ; emit_insn ( si_op ) ; if ( result ) { loongarch_emit_binary ( AND , res , res , mask ) ; loongarch_emit_binary ( LSHIFTRT , res


<s> void <ISA_LIT>RegisterBankInfo :: constrainOpWithReadfirstlane ( MachineInstr & MI , MachineRegisterInfo & MRI , unsigned OpIdx ) const { Register Reg = MI . getOperand ( OpIdx ) . getReg ( ) ; const RegisterBank * Bank = getRegBank ( Reg , MRI , * TRI ) ; if ( Bank != & <STR_LIT> ) return ; MachineIRBuilder B ( MI ) ; Register SGPR = MRI . createVirtualRegister ( & <STR_LIT>


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS

, uint8_t OSABI , bool IsLittleEndian ) {


<s> GCNRegPressure getRegPressure ( const MachineRegisterInfo & MRI , Range && LiveRegs ) { GCNRegPressure Res ; for ( const auto & RM : LiveRegs ) Res . inc ( RM . first , LaneBitmask :: getNone ( ) , RM . second , MRI ) ; return


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT>

|| Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> bool Changed = false ; const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineFunction :: iterator MBBI = MF . begin ( ) ; MachineFunction :: iterator EndMBB = MF . end ( ) ; for ( ; MBBI != EndMBB ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( this , PM , Subtarget .


<s> void emitARM64WinCFISaveFRegX ( unsigned Reg


<s> bool <ISA_LIT>TargetLowering :: useSoftFloat ( )


<s> flags = default_section_type_flags ( decl , name , reloc ) ; if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) flags


<s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { unsigned Align = getStackAlignment ( ) ; int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount = alignTo (


<s> bool hasV4TOps ( ) const { return HasV4TOps


<s> unsigned PCAdj = ( isThumb || isThumb2 ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolMBB :: Create ( F . getContext ( ) , DispatchBB , PCLabelId , PCAdj ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? & <STR_LIT> : & <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) . add ( predOps ( <STR_LIT> ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) .


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSNaCl ( ) ) return new NaCl<ISA_LIT>_32AsmBackend ( T , OSABI


<s> case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue ::


<s> SDNode * OffsetNode = Offset . getNode ( ) ; int32_t Val = cast < ConstantSDNode > ( OffsetNode ) -> getSExtValue ( ) ; EVT StoredVT = ST -> getMemoryVT ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TII -> isValidAutoIncImm ( StoredVT , Val ) ) { SDValue Ops [ ] = { Base , CurDAG -> getTargetConstant ( Val , <STR_LIT> ) , Value , Chain } ; unsigned Opcode = <NUM_LIT> ; if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( ST , Result ) ; ReplaceUses ( SDValue ( ST , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; return Result ; } SDValue Ops [ ] = { Base , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Value , Chain } ; unsigned Opcode = <NUM_LIT> ; if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable (


<s> bool <ISA_LIT>BitSimplify :: replaceRegWithSub ( unsigned OldR , unsigned NewR , unsigned NewSR , MachineRegisterInfo & MRI ) { if ( ! Register :: isVirtualRegister ( OldR ) || ! Register :: isVirtualRegister ( NewR ) ) return false ; if ( hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) ,


<s> const Function * F = MF -> getFunction ( ) ; static const MCPhysReg CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsIntr [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , InterpMov ) . addImm ( <NUM_LIT> ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( <NUM_LIT> ) . addReg ( Src0 ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( <NUM_LIT> ) . addReg ( InterpMov ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return


<s> RegisterTarget < Triple :: upt > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT>


<s> static bool bfin_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to


<s> static bool mcore_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter


<s> V1 = Extract128BitVector ( V1 , EltNo , DAG , dl ) ; if ( EltNo >= NumElems / <NUM_LIT> ) EltNo -= NumElems / <NUM_LIT> ; } EVT EltVT = SrcVT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) V1 = PromoteSplati8i16 ( V1 , DAG , EltNo ) ; if ( Is256BitVec ) { V1 = DAG . getNode ( <STR_LIT> , dl


<s> rtx rs6000_find_base_term ( rtx op ) { rtx base ; base = op ; if ( GET_CODE ( base ) == CONST ) base = XEXP ( base , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PLUS ) base = XEXP ( base , <NUM_LIT> ) ; if ( GET_CODE ( base ) == UNSPEC ) switch ( XINT ( base , <NUM_LIT> ) ) { case UNSPEC_TOCREL : case UNSPEC_MACHOPIC_OFFSET : return XVECEXP ( base , <NUM_LIT> , <NUM_LIT>


<s> return DecodeFPR32RegisterClass ( Inst , RegNo , Address


<s> void printARI32Mem ( const MCInst * MI , int


<s> OffsetToIdMap [ Offset ] = Table . size ( ) ; Table . push_back ( std :: string ( S ) ) ; Size += S . size ( ) + <NUM_LIT> ; return Offset


<s> ShuffleMask . push_back ( ( ( Imm >> Bit ) &


<s> static DecodeStatus DecodeVLDST4Instruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned size = fieldFromInstruction ( Insn ,


<s> TargetLoweringObjectFile :: Initialize ( Ctx , tm ) ; TM = & tm ; BSSSection = get<ISA_LIT>Section ( <STR_LIT> , SectionKind :: getBSS ( ) ) ; ReadOnlySection = get<ISA_LIT>Section ( <STR_LIT> , SectionKind :: getReadOnly ( ) ) ; DataSection = get<ISA_LIT>Section ( <STR_LIT> , SectionKind :: getDataRel ( ) ) ; TextSection = get<ISA_LIT>Section ( <STR_LIT> , SectionKind :: getText ( ) ) ; ROSections . push_back ( new <ISA_LIT>Section ( ( MCSection<ISA_LIT> * ) ReadOnlySection


<s> const llvm :: MachineFunction & MF = * SU -> getInstr ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; const RegPressureTracker & TopRPTracker = DAG -> getTopRPTracker ( ) ; RegPressureTracker & RPTracker = const_cast < RegPressureTracker & > ( TopRPTracker ) ; const int * rcps = TRI . getRegClassPressureSets ( RC ) ; std :: vector < unsigned > pressure ; std :: vector < unsigned > MaxPressure ; RPTracker . getDownwardPressure ( SU -> getInstr ( ) , pressure , MaxPressure ) ; int j = <NUM_LIT> ; while ( rcps [ j ] >= <NUM_LIT> ) { if ( res < pressure [ rcps [ j ] ] ) res = pressure [ rcps [ j ] ] ; j ++ ; } if ( RC == & <STR_LIT> ) { res +=


<s> bool <ISA_LIT>ConstantIslands :: mayOptimizeThumb2Instruction ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> static unsigned getSubOpcode ( bool Is64Bit , int64_t Amount ) { if ( Is64Bit ) return isInt < <NUM_LIT>


<s> O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; return ; } case <STR_LIT> : { Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this , Subtarget . isDarwin ( ) ) ; TmpInst . setOpcode ( <STR_LIT> ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isGlobal ( ) ) ; MCSymbol * & TOCEntry = TOC [ Mang -> getSymbol ( MO . getGlobal ( ) ) ] ; if ( TOCEntry == <NUM_LIT> ) TOCEntry = GetTempSymbol ( <STR_LIT> , TOCLabelID ++ ) ; const MCExpr * Exp = MCSymbolRefExpr :: Create ( TOCEntry , MCSymbolRefExpr :: VK_<ISA_LIT>_TOC , OutContext ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateExpr (


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ) ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT>


<s> void <ISA_LIT>LowerControlFlow :: emitElse ( MachineInstr & MI ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) ; bool ExecModified = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; MachineBasicBlock :: iterator Start = MBB . begin ( ) ; unsigned CopyReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Start , DL , TII -> get ( <STR_LIT> ) , CopyReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; unsigned SaveReg = ExecModified ? MRI -> createVirtualRegister ( & <STR_LIT> ) : DstReg ; MachineInstr * OrSaveExec = BuildMI ( MBB , Start , DL , TII -> get ( <STR_LIT> ) , SaveReg ) . addReg ( CopyReg ) ; MachineBasicBlock * DestBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: iterator ElsePt ( MI ) ; if ( ExecModified ) { MachineInstr * And = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( <STR_LIT> ) . addReg ( SaveReg ) ; if ( LIS ) LIS -> InsertMachineInstrInMaps ( * And ) ; } MachineInstr * Xor = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( DstReg ) ; MachineInstr * Branch = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; if ( ! LIS )


<s> bool <ISA_LIT>TargetLowering :: denormalsEnabledForType ( EVT VT ) const { switch ( VT . getScalarType ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return Subtarget -> hasFP32Denormals ( ) ; case <STR_LIT>


<s> poly_int64 riscv_v_adjust_precision ( machine_mode mode , int scale ) { if ( riscv_v_ext_vector_mode_p ( mode ) )


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty (


<s> unsigned <ISA_LIT>AsmBackend :: getFixupKindContainereSizeInBytes ( unsigned Kind ) const { if ( IsLittleEndian ) return <NUM_LIT> ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4


<s> <ISA_LIT>LowerControlFlowPass ( TargetMachine


<s> assert ( ! FirstMI . hasOrderedMemoryRef ( ) && ! TII -> isLdStPairSuppressed ( FirstMI ) && <STR_LIT> ) ; unsigned OpcA = FirstMI . getOpcode ( ) ; unsigned OpcB = MI . getOpcode ( ) ; if ( OpcA == OpcB ) return true ; bool IsValidLdStrOpc , PairIsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( OpcA , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) { Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) OpcA


<s> auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( DAG . getTarget ( ) . Options . NoNaNsFPMath || N -> getFlags ( ) . hasNoNaNs ( ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op1 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op0 , Op1 , N -> getFlags ( ) ) ; if ( DAG . isKnownNeverNaN ( Op0 ) ) return DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 , N -> getFlags ( ) ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return SDValue ( ) ; EVT SetCCType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT , Op1


<s> for ( unsigned int i = <NUM_LIT> ; i < <ISA_LIT>GOT0Num ; ++ i ) new <ISA_LIT>GOTEntry (


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI ,


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> else if ( size > <NUM_LIT> ) loongarch_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; loongarch_emit_stack_tie ( ) ; } if ( size > <NUM_LIT>


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseSLC


<s> std :: vector < std :: string > retd ( ) { return D ( <STR_LIT>


<s> if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) -> getAttributes

( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_SaveList ;


<s> if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) { Register VSrc = MI . getOperand ( <NUM_LIT>


<s> if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer (


<s> int getMUBUFOpcode ( unsigned BaseOpc , unsigned Elements ) { const MUBUFInfo * Info = getMUBUFInfoFromBaseOpcodeAndElements ( BaseOpc , Elements ) ; return Info ? Info -> Opcode : -


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; bool Swap = false ; unsigned SSECC ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ;


<s> if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveThumb ( DirectiveID . getLoc


<s> llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op ,


<s> static void * mingw32_gt_pch_get_address ( size_t size , int ) { void * res ; size = ( size + va_granularity - <NUM_LIT> ) & ~ ( va_granularity - <NUM_LIT> ) ; if ( size > pch_VA_max_size ) return NULL ; res = VirtualAlloc ( NULL , pch_VA_max_size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , <STR_LIT>


<s> return ( __m64 ) __builtin_ia32_pfcmpeq ( ( __v2sf ) __A , ( __v2sf )


<s> if ( CSI . empty ( ) ) return false ; DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>Z80MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; i -- ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn (


<s> <STR_LIT> getExtendForAtomicOps ( ) const override { return <STR_LIT>


<s> MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; unsigned SecondOpcode = isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; emitAuipcInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI ,


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) ->


<s> bool <ISA_LIT>GlobalRegistry :: isScalarOfType ( Register VReg , unsigned TypeOpcode ) const { <ISA_LIT>Type * Type = get<ISA_LIT>TypeForVReg (


<s> if ( is_naked_func ( ) ) { emit_insn ( gen_rtx_CLOBBER ( VOIDmode , GEN_INT ( <NUM_LIT> ) ) ) ; return ; } emit_insn ( gen_prologue_start_marker ( ) ) ; if ( is_critical_func ( ) ) { emit_insn ( gen_push_intr_state ( ) ) ; emit_insn ( gen_disable_interrupts ( ) ) ; } else if ( is_reentrant_func ( ) ) emit_insn ( gen_disable_interrupts ( ) ) ; if ( ! cfun -> machine -> computed ) msp430_compute_frame_info ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> framesize ; if ( crtl -> args . pretend_args_size ) { rtx note ; gcc_assert ( crtl -> args . pretend_args_size == <NUM_LIT> ) ; p = emit_insn ( gen_grow_and_swap ( ) ) ; note = F ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , GEN_INT ( <NUM_LIT> ) ) ) ) ; add_reg_note ( p , REG_FRAME_RELATED_EXPR , note ) ; note = F ( gen_rtx_SET ( gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ) , pc_rtx ) ) ; add_reg_note ( p , REG_CFA_OFFSET , note ) ; F ( p ) ; } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( cfun -> machine -> need_to_save [ i ] ) { int seq , count ; rtx note ; for ( seq = i - <NUM_LIT> ; seq >= <NUM_LIT> && cfun -> machine -> need_to_save [ seq ] ; seq -- ) ; count = i - seq ; if ( msp430x ) { p = F ( emit_insn ( gen_pushm ( gen_rtx_REG ( Pmode , i ) , GEN_INT ( count ) ) ) ) ; note = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + <NUM_LIT> ) ) ; XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) = F ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( count * ( TARGET_LARGE ? - <NUM_LIT> : - <NUM_LIT> ) ) ) ) ) ; for ( j = <NUM_LIT> ; j < count ; j ++ ) { rtx addr ; int ofs = ( count - j - <NUM_LIT> ) * ( TARGET_LARGE ? <NUM_LIT> : <NUM_LIT> ) ; if ( ofs ) addr = gen_rtx_PLUS ( Pmode , sp , GEN_INT ( ofs ) ) ; else addr = stack_pointer_rtx ; XVECEXP ( note , <NUM_LIT> , j + <NUM_LIT> ) = F ( gen_rtx_SET ( gen_rtx_MEM ( Pmode , addr ) , gen_rtx_REG ( Pmode , i - j ) ) ) ; } add_reg_note ( p , REG_FRAME_RELATED_EXPR , note ) ; i -= count - <NUM_LIT> ; } else F ( emit_insn ( gen_push ( gen_rtx_REG ( Pmode , i ) ) ) ) ; } if ( frame_pointer_needed ) F ( emit_move_insn ( gen_rtx_REG ( Pmode


<s> rtx offset ; split_const ( x , & x ,


<s> if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return (


<s> return getSubtargetImpl ( ) -> getRegisterInfo


<s> return ( __m128i ) __builtin_ia32_vprotd ( ( __v4si ) __A ,


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ; int Adj =


<s> assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = IsN64 ? <STR_LIT> : <STR_LIT> ; MFI -> setReturnAddressIsTaken ( true ) ; unsigned Reg = MF . addLiveIn ( RA


<s> Base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , CurDAG -> getEntryNode ( ) . getDebugLoc ( ) , AMDGPU :: ZERO , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT>


<s> fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , XSTR ( fun ,


<s> LiveRegs . init ( * ST . getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; LiveRegs . stepBackward ( * MBBI ) ; } } ScratchExecCopy = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , * TRI . getWaveMaskRegClass ( ) ) ; if ( ! IsProlog ) LiveRegs . removeReg ( ScratchExecCopy ) ; const unsigned OrSaveExec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( OrSaveExec ) , ScratchExecCopy ) . addImm ( - <NUM_LIT> ) ; return ScratchExecCopy


<s> bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ;

FJ != FE ; ++ FI , ++ FJ ) Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; return getAddr ( N , DAG


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const { return &


<s> virtual const char * getPassName ( ) const { return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = & TII -> getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( MFI -> isEntryFunction ( ) ) ; Register ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ! ScratchRsrcReg || ( ! MRI . isPhysRegUsed ( ScratchRsrcReg ) && allStackObjectsAreDead ( MF . getFrameInfo ( ) ) ) ) return Register ( ) ; if ( ST . hasSGPRInitBug ( ) || ScratchRsrcReg != TRI -> reservedPrivateSegmentBufferReg ( MF ) ) return ScratchRsrcReg ; unsigned NumPreloaded = ( MFI -> getNumPreloadedSGPRs ( ) + <NUM_LIT> ) / <NUM_LIT> ; ArrayRef < MCPhysReg > AllSGPR128s = TRI -> getAllSGPR128 ( MF ) ; AllSGPR128s = AllSGPR128s . slice ( std :: min ( static_cast < unsigned > ( AllSGPR128s . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPR128s ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( Reg , GITPtrLoReg ) ) { MRI . replaceRegWith ( ScratchRsrcReg , Reg ) ; MFI -> setScratchRSrcReg ( Reg ) ; return Reg ; } } return ScratchRsrcReg


<s> TII = STI -> getInstrInfo ( ) ; AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; isThumb1 = AFI -> isThumb1OnlyFunction ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; HasFarJump = false ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( isThumb2 && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( <NUM_LIT> ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) )

Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> unsigned try = <NUM_LIT> , used ; int jump_left = flag_expensive_optimizations + <NUM_LIT> ; for ( scan = jump ; ( scan = PREV_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( INSN_DELETED_P ( scan ) ) continue ; code = GET_CODE ( scan ) ; if ( code == CODE_LABEL || code == JUMP_INSN ) break ; if ( code == INSN && GET_CODE ( PATTERN ( scan ) ) != USE && GET_CODE ( PATTERN ( scan ) ) != CLOBBER && get_attr_in_delay_slot ( scan ) == IN_DELAY_SLOT_YES ) { try &= ~ regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; break ; } } for ( used = dead = <NUM_LIT> , scan = JUMP_LABEL ( jump ) ; ( scan = NEXT_INSN ( scan ) ) ; ) { enum rtx_code code ; if ( INSN_DELETED_P ( scan ) ) continue ; code = GET_CODE ( scan ) ; if ( INSN_P ( scan ) ) { used |= regs_used ( PATTERN ( scan ) , <NUM_LIT> ) ; if ( code == CALL_INSN ) used |= regs_used ( CALL_INSN_FUNCTION_USAGE ( scan ) , <NUM_LIT> ) ; dead |= ( used >> <NUM_LIT>


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM


<s> void <ISA_LIT>AsmPrinter :: outputInstruction (


<s> bool <ISA_LIT>InstrInfo :: isLateInstrFeedsEarlyInstr ( const MachineInstr & LRMI , const MachineInstr & ESMI ) const { bool isLate = isLateResultInstr ( LRMI ) ; bool isEarly = isEarlySourceInstr ( ESMI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( isLate ? <STR_LIT> : <STR_LIT> ) ) ; LLVM_DEBUG ( LRMI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> )


<s> if ( ! CONST_INT_P ( op ) ) return false ; val = INTVAL ( op ) ; return ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT> || val


<s> static bool isSVEDataVectorRegister ( StringRef Name