<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint


<s> bool IsModified = false ; do { IsModified = false ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ++ I ) { SDNode * Node = I ; MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( I ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node )


<s> } if ( scratch != NO_REGS && ! reg_class_subset_p ( test , scratch ) ) return ( mn10300_register_move_cost ( VOIDmode , from , scratch ) + mn10300_register_move_cost ( VOIDmode , scratch , to ) ) ; if ( optimize_size ) { if ( from == to && ( to == ADDRESS_REGS || to == DATA_REGS ) ) return <NUM_LIT> ; if ( from == SP_REGS ) return ( to == ADDRESS_REGS ? <NUM_LIT> : <NUM_LIT> ) ; if ( TARGET_AM33 ) return <NUM_LIT> ; if ( to == SP_REGS ) return ( from == ADDRESS_REGS ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( from == ADDRESS_REGS || from == DATA_REGS ) && ( to == ADDRESS_REGS || to == DATA_REGS ) ) return <NUM_LIT> ; if ( to == EXTENDED_REGS ) return ( to == from ? <NUM_LIT> : <NUM_LIT> ) ; return <NUM_LIT> ; } else { if ( to == FP_REGS ) return <NUM_LIT> ; if ( from == FP_REGS ) return <NUM_LIT> ; return


<s> if ( expand_perm_with_vpdi ( d ) ) return true ; if ( expand_perm_with_rot ( d ) ) return true ; return


<s> unsigned <ISA_LIT>MCAsmBackend :: getNumFixupKinds ( ) const { return <STR_LIT>


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> <STR_LIT> ET = getShiftExtendType ( ) ; if ( ET == <STR_LIT> ) Imm


<s> I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) if ( CallInst * CI = dyn_cast < CallInst > ( J ) ) if ( Function * F = CI -> getCalledFunction ( ) ) if ( F -> getIntrinsicID ( ) == <STR_LIT> ) return MadeChange ; Metrics . analyzeBasicBlock ( * I , * TTI , EphValues ) ; } unsigned LoopSize = Metrics . NumInsts ; if ( ! LoopSize ) LoopSize = <NUM_LIT> ; unsigned ItersAhead = TTI -> getPrefetchDistance ( ) / LoopSize ; if ( ! ItersAhead ) ItersAhead = <NUM_LIT> ; SmallVector < std :: pair < Instruction * , const SCEVAddRecExpr * > , <NUM_LIT> > PrefLoads ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { Value * PtrValue ; Instruction * MemI ; if ( LoadInst * LMemI = dyn_cast < LoadInst > ( J ) ) { MemI = LMemI ; PtrValue = LMemI -> getPointerOperand ( ) ; } else if ( StoreInst * SMemI = dyn_cast < StoreInst > ( J ) ) { if ( ! PrefetchWrites ) continue ; MemI = SMemI ; PtrValue = SMemI -> getPointerOperand ( ) ; } else continue ; unsigned PtrAddrSpace = PtrValue -> getType ( ) -> getPointerAddressSpace ( ) ; if ( PtrAddrSpace ) continue ; if ( L -> isLoopInvariant ( PtrValue ) ) continue ; const SCEV * LSCEV = SE ->


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GAHi = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GAHi , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GALo ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = IsN64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; if ( ! HasGotOfst


<s> for ( GepNode * Root : Roots ) recalculatePlacementRec ( Root , NCM , Loc ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocationAsBlock ( Loc ) ) ; if ( OptEnableInv ) { for ( GepNode * Root : Roots ) adjustForInvariance ( Root , NCM , Loc ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocationAsBlock ( Loc ) ) ; } if ( OptEnableConst ) { for ( GepNode * Root : Roots ) separateConstantChains ( Root , NCM , Loc ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Uses


<s> const Function * F = MF . getFunction ( ) ; SwitchToSection ( TAI -> SectionForGlobal ( F ) ) ; O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName << <STR_LIT> ; switch ( F -> getLinkage ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case Function :: InternalLinkage : case Function :: PrivateLinkage : break ; case Function :: ExternalLinkage : emitGlobalDirective ( CurrentFnName ) ; break ; case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : O << TAI -> getGlobalDirective ( ) << CurrentFnName << <STR_LIT> ; O << TAI -> getWeakDefDirective ( ) << CurrentFnName << <STR_LIT> ; break ; } EmitAlignment ( <NUM_LIT> , F , <NUM_LIT> ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) ) { O << <STR_LIT> <<


<s> FunctionPass * llvm :: create<ISA_LIT>CallFrameOptimization ( ) { return new <ISA_LIT>CallFrameOptimization ( )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) ,

Subtarget ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , Subtarget ) {


<s> FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) && requires_stack_frame_p ( insn , prologue_used , set_up_by_prologue ) ) { crtl -> stack_realign_needed = stack_realign ; crtl -> stack_realign_finalized =


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const TargetFrameLowering * TFI = MF -> getSubtarget


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? <NUM_LIT> : materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( )


<s> MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = & * MBBb ; MachineBasicBlock :: iterator MII = MBB -> getFirstTerminator ( ) ; if ( MII != MBB -> end ( ) ) { MachineInstr & MI = * MII ; int Opc = MI . getOpcode ( ) ; if ( IsConditionalBranch ( Opc ) ) { unsigned NumSuccs = MBB -> succ_size ( ) ; MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) ; MachineBasicBlock * FirstSucc = * SI ; MachineBasicBlock * SecondSucc = * ( ++ SI ) ; MachineBasicBlock * LayoutSucc = nullptr ; MachineBasicBlock * JumpAroundTarget = nullptr ; if ( MBB -> isLayoutSuccessor ( FirstSucc ) ) { LayoutSucc = FirstSucc ; JumpAroundTarget = SecondSucc ; } else if ( MBB -> isLayoutSuccessor ( SecondSucc ) ) { LayoutSucc = SecondSucc ; JumpAroundTarget = FirstSucc ; } else { } MachineBasicBlock * CondBranchTarget = nullptr ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { CondBranchTarget = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; } if ( ! LayoutSucc || ( CondBranchTarget != JumpAroundTarget ) ) { continue ; } if ( ( NumSuccs == <NUM_LIT> ) && LayoutSucc && ( LayoutSucc -> pred_size ( ) == <NUM_LIT> ) ) { if ( ( LayoutSucc -> size ( ) == <NUM_LIT> ) && IsUnconditionalJump ( LayoutSucc -> front ( ) . getOpcode ( ) ) ) { assert ( JumpAroundTarget && <STR_LIT> ) ; MachineBasicBlock * UncondTarget = LayoutSucc -> front ( ) . getOperand ( <NUM_LIT> ) .


<s> if ( VT != SrcOp . getSimpleValueType ( ) ) SrcOp = DAG . getBitcast ( VT , SrcOp ) ; if ( ShiftAmt == <NUM_LIT> ) return SrcOp ; if ( ShiftAmt >= ElementType . getSizeInBits ( ) ) { if ( Opc == <STR_LIT> ) ShiftAmt = ElementType . getSizeInBits ( ) - <NUM_LIT> ; else return DAG . getConstant ( <NUM_LIT> , dl , VT ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; if ( <STR_LIT> ( SrcOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Elts ; unsigned NumElts = SrcOp -> getNumOperands ( ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg )

. addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> MCTargetOptions MCOpts = Options . MCOptions ; if ( MCOpts . getABIName ( ) . empty ( ) ) { _ABI = Call0_ABI ; } else { if ( MCOpts . getABIName ( ) == <STR_LIT> ) _ABI = Window_ABI ; else if ( MCOpts . getABIName ( ) == <STR_LIT> ) _ABI = Call0_ABI ; else { _ABI = Call0_ABI ; errs ( ) << <STR_LIT> << MCOpts


<s> Targets . insert ( BrI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : Undetermined : FallsThru = ! BrI . isUnconditionalBranch ( ) ; return false ; } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( <NUM_LIT> ) ; Register PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; ; if ( Props & ConstantProperties ::


<s> static DecodeStatus DecodeSSRInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , s2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success


<s> return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm & <NUM_LIT> || Imm > <NUM_LIT> ) return false ; if ( ! is<ISA_LIT>LowRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoadOrStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI ,


<s> return NULL ; } switch ( Node -> getOpcode ( ) ) { case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return SelectAtomic ( Node , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT PtrTy = TLI . getPointerTy ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return CurDAG -> SelectNodeTo ( Node , <STR_LIT> , PtrTy , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ) ; } case <STR_LIT> : { ConstantPoolSDNode * CN = cast < ConstantPoolSDNode > ( Node ) ; const Constant * C = CN -> getConstVal ( ) ; SDValue CP = CurDAG -> getTargetConstantPool ( C , CN -> getValueType ( <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , CP ) ; return NULL ; } case <STR_LIT> : { SDNode * ResNode = <NUM_LIT> ; if ( cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) == <NUM_LIT> ) { EVT Ty = Node -> getValueType ( <NUM_LIT> ) ; assert ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && <STR_LIT> ) ; uint16_t Register = Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ResNode = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , Node -> getDebugLoc ( ) , Register , Ty ) . getNode ( ) ; } if ( ! ResNode ) { ResNode = TrySelectToMoveImm ( Node ) ; } if ( ResNode ) return ResNode ; ResNode = SelectToLitPool ( Node ) ; assert ( ResNode && <STR_LIT> ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; Node = ResNode ; break ; } case <STR_LIT> : { if ( A64Imms :: isFPImm ( cast < ConstantFPSDNode > ( Node


<s> if ( mep_section_tag ( DECL_RTL ( cfun -> decl ) ) == 'f' ) return false ; return src_vliw ==


<s> unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( MatchAddress ( N , AM ) ) return false ; if ( Subtarget -> isTargetNaCl64 ( ) ) { LegalizeAddressingModeForNaCl ( N , AM ) ; } EVT VT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister


<s> Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; SupportsDebugInformation = true ; MaxInstLength = <NUM_LIT> ; switch ( TheTriple . getOS ( ) ) { case Triple :: NetBSD : ExceptionsType = ExceptionHandling


<s> char indirectlabel1 [ <NUM_LIT> ] ; char indirectlabel2 [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; ix86_output_jmp_thunk_or_indirect ( thunk_name , regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( <STR_LIT>


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetFrameLowering * TFI = STI . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return getFramePointerReg ( STI ) ; return <STR_LIT>


<s> static Register getFPReg ( const <ISA_LIT>Subtarget & STI


<s> SDValue <ISA_LIT>TargetLowering :: LowerStore ( SDValue Op , SelectionDAG & DAG ) const { const SDLoc & dl ( Op ) ; StoreSDNode * SN = cast < StoreSDNode > ( Op . getNode ( ) ) ; SDValue Val = SN -> getValue ( ) ; MVT Ty = ty ( Val ) ; bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; SDValue NS = DAG . getStore ( SN -> getChain ( ) , dl , TC , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ; if ( SN -> isIndexed ( ) ) { NS = DAG . getIndexedStore ( NS , dl , SN -> getBasePtr ( ) , SN -> getOffset ( )


<s> void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeType :: Text ; Item -> StringValue = std :: string ( Value ) ; return ; } Contents . push_back ( { AttributeType :: Text , Attribute , <NUM_LIT> , std :: string (


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = GPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> static DecodeStatus DecodeExtSize ( MCInst & Inst , uint64_t Insn , uint64_t Address , const void * Decoder ) { int Size = ( int ) Insn + <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > (


<s> } } unsigned FirstRegisterIndex = getRegisterIndex ( FirstRegister ) ; unsigned LastRegisterIndex = getRegisterIndex ( LastRegister ) ; uint16_t NumNewBits = LastRegisterIndex - FirstRegisterIndex + <NUM_LIT> ; uint16_t NewMaskBits = ( ( <NUM_LIT> << NumNewBits ) - <NUM_LIT> ) << FirstRegisterIndex ; if ( IsFirstRegister && ( FirstRegister == LastRegister ) ) { MemOp . Op = <STR_LIT> :: Reg ; MemOp . OuterReg = FirstRegister ; } else { if ( MemOp . Op == <STR_LIT> :: Reg ) { MemOp . Op = <STR_LIT> :: RegMask ; MemOp . RegMask = <NUM_LIT> << getRegisterIndex ( MemOp . OuterReg ) ; if ( MemOp . RegMask == <NUM_LIT> ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } if ( ( FirstRegisterIndex >= <NUM_LIT> ) ||


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>leTargetMachine > X ( The<ISA_LIT>leTarget ) ; RegisterTargetMachine < <ISA_LIT>beTargetMachine > Y ( The<ISA_LIT>beTarget ) ; RegisterTargetMachine < <ISA_LIT>leTargetMachine > Z (


<s> Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , <STR_LIT> ) ; unsigned SrcOddReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcOddReg ) ; Offset += <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestOddReg = getSubReg ( DestReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) ; replaceFI ( MF , * StMI , * StMI , dl , <NUM_LIT> , Offset , FrameReg ) ; MI . setDesc ( TII . get ( <STR_LIT> )


<s> unsigned Ra = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return


<s> std :: vector < uint8_t > BinaryValue = bianrySerialize<ISA_LIT>ProgramHeader ( Header ) ; Fragment -> getContents ( ) . append ( BinaryValue . begin ( ) , BinaryValue . end ( ) ) ; Fragment -> setAlignToBundleEnd ( true ) ; Out . SwitchSection ( MetadataSection ) ; Out . PopSection ( ) ; } std :: string RootFileName = getContext ( ) . getMainFileName ( ) ; if ( ! RootFileName . empty ( ) ) { Out . PushSection ( ) ; MCSectionELF * KernelInfoSection = getContext ( ) . getELFSection ( KernelInfoSectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; KernelInfoSection -> getFragmentList ( ) . clear ( ) ; MCDataFragment * Fragment = new MCDataFragment ( KernelInfoSection ) ; StringRef BareFileName = llvm :: sys :: path :: stem ( RootFileName ) ; std :: string KernelInfo = GenerateKernelInfo ( BareFileName ) ; Fragment -> getContents ( ) . append ( KernelInfo . begin ( ) , KernelInfo . end ( ) ) ; Fragment -> setAlignToBundleEnd ( true ) ; Out . SwitchSection ( KernelInfoSection ) ; Out . PopSection


<s> bool <ISA_LIT>MCAsmInfo :: shouldOmitSectionDirective ( StringRef SectionName ) const { return true


<s> for ( MachineInstr * MI : LoweredEndCf ) { MachineBasicBlock & MBB = * MI -> getParent ( ) ; auto Next = skipIgnoreExecInstsTrivialSucc ( MBB , std :: next ( MI -> getIterator ( ) ) ) ; if ( Next == MBB . end ( ) || ! LoweredEndCf . count ( &


<s> StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI


<s> EVT VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; assert ( VecTy . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SelectBaseMVE_VMLLDAV ( N , Predicated , OpcodesS , OpcodesU


<s> if ( GET_MODE ( addr ) == Pmode || GET_MODE ( addr ) == VOIDmode ) { reg = copy_addr_to_reg ( addr ) ; REG_POINTER ( reg ) = <NUM_LIT> ; return reg ; } else { gcc_assert ( GET_MODE ( addr ) == DImode && Pmode == SImode ) ; reg = copy_to_mode_reg ( DImode , addr ) ; REG_POINTER ( reg ) = <NUM_LIT>


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind ,

const MCExpr * Expr , MCContext & Ctx ) {


<s> case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op


<s> static DecodeStatus DecodeRegisterClass ( MCInst & Inst , unsigned RegNo , const uint16_t Table [ ]


<s> bool avr_has_nibble_0xf ( rtx ival ) { unsigned int map = UINTVAL ( ival ) & GET_MODE_MASK ( SImode


<s> unsigned <ISA_LIT>MCCodeEmitter :: get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && (

MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ;


<s> if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; return isIntrinsicSourceOfDivergence ( TM . getIntrinsicInfo ( ) , Intrinsic ) ; } if ( isa < CallInst > ( V ) || isa


<s> if ( ! NDS32_EXT_DSP_P ( ) ) return word_mode ; switch (


<s> case MachineOperand :: MO_Register : MCOp = MCOperand :: CreateReg ( encodeVirtualRegister ( MO . getReg ( ) ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( MO , getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand ::


<s> __v2du rshift , shmask ; const __v2du shmax = { <NUM_LIT> , <NUM_LIT> } ; __v2du result ; rshift = ( __v2du ) vec_splat ( ( __v2du ) __B , <NUM_LIT> ) ; shmask = rshift < shmax ; result = vec_vsrd ( ( __v2du ) __A , rshift


<s> if ( ! Subtarget -> hasMVEIntegerOps ( ) || ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return SDValue ( ) ; SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup -> getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , N

-> getValueType ( <NUM_LIT> ) , Negate ) ;


<s> const GCNSubtarget & STI = MF -> getSubtarget < GCNSubtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand (


<s> if ( selectBDXAddr ( <STR_LIT> , <STR_LIT> , Op , Base , Disp , Index ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ; OutOps . push_back ( Index ) ; return


<s> return ( uint16x4_t ) __builtin_neon_vld1_lanev4hi ( ( const __builtin_neon_hi * ) __a , (


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) return false ; return fixed_regs [


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT )


<s> fs -> curr . reg [ UNW_REG_RP ] . val = <NUM_LIT> ; return _URC_NO_REASON ; } return _URC_END_OF_STACK ; } context -> region_start = ent -> start_offset + segment_base ; fs -> when_target = ( ( context -> rp & - <NUM_LIT> ) - context -> region_start ) / <NUM_LIT> * <NUM_LIT> + ( context -> rp & <NUM_LIT> ) ; unw = ( unsigned long * ) ( ent -> info_offset + segment_base ) ; header = * unw ; length = UNW_LENGTH ( header ) ; if ( UNW_FLAG_EHANDLER ( header ) | UNW_FLAG_UHANDLER ( header ) ) { fs -> personality = * ( _Unwind_Personality_Fn * ) ( unw [ length + <NUM_LIT> ] + context -> gp ) ; context -> lsda = unw + length + <NUM_LIT> ; } insn = ( unsigned char * ) ( unw + <NUM_LIT> ) ; insn_end = ( unsigned char * ) ( unw + <NUM_LIT> + length ) ; while ( ! fs -> done && insn < insn_end ) insn = unw_decode ( insn , fs -> in_body , fs ) ; free_label_states ( fs -> labeled_states ) ; free_state_stack ( & fs -> curr


<s> <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler ( ) .


<s> <ISA_LIT>_64RelType Type = getType64 ( Fixup . getKind ( ) , Modifier , IsPCRel ) ; if ( getEMachine ( ) == ELF :: EM_<ISA_LIT>_64 ) return getRelocType64 ( Ctx , Fixup . getLoc ( ) , Modifier , Type , IsPCRel ) ; assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine ( ) == ELF :: EM_IAMCU ) && <STR_LIT> ) ; return getRelocType32 ( Modifier , getType32 ( Type


<s> <STR_LIT> CalleeMode ( * Callee ) ; if ( ! CallerMode . isInlineCompatible ( CalleeMode ) ) return false ; if ( InlineMaxBB && ! Callee -> hasFnAttribute ( Attribute :: InlineHint ) ) { size_t BBSize = Caller -> size ( ) + Callee -> size ( ) - <NUM_LIT> ; return BBSize <= InlineMaxBB ; } return true


<s> MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand (


<s> case fixup_<ISA_LIT>_B7_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B7_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B9_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B9_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B13_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask =


<s> static inline unsigned getT1Imm5 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> ,


<s> static unsigned getRd ( InsnType insn


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopUnrollPass


<s> const char * fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( int i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { for ( int j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x


<s> return ( __m128i ) __builtin_ia32_pmovzxbq128_mask ( ( __v16qi ) __A , (


<s> DecodeGPR64RegisterClass ( Inst , Rn , Address , Decoder ) ; } else { DecodeGPR64RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rn , Address , Decoder ) ; } Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> )


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > && AB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && CE , bool RelaxAll , bool IncrementalLinkerCompatible ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , std :: move ( AB ) , std :: move ( CE ) , std :: move ( OW ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; S -> getAssembler ( ) . setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ; return


<s> unsigned Opcode = MI . getOpcode ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool isCC = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( isCC ? <NUM_LIT> : <NUM_LIT> ) ; bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . addReg


<s> static MCStreamer * createMachOStreamer ( MCContext & Ctx , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll ,


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler :: Success


<s> if ( GET_MODE_BITSIZE ( mode ) > <NUM_LIT> && TARGET_AVX128_OPTIMAL ) return cost * GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; return


<s> bool isAddr64 ( ) const { return isImmTy (


<s> void <ISA_LIT>InstPrinter :: printExpCompr ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printNamedBit ( MI , OpNo , O , <STR_LIT>


<s> if ( MII -> getOpcode ( ) == TargetOpcode :: KILL || MII -> getOpcode ( ) == TargetOpcode :: PHI

|| MII -> getOpcode ( ) == TargetOpcode :: COPY ) return false ;


<s> return __builtin_ia32_vcvtudq2ph512_mask_round ( ( __v16si ) __B , _mm256_setzero_ph ( ) , __A ,


<s> bool <ISA_LIT>InstrInfo :: hasDisplacementPairInsn ( unsigned Opcode ) const { const MCInstrDesc & MCID = get ( Opcode ) ; if ( MCID . TSFlags & <STR_LIT> ) return <STR_LIT>


<s> } LDM . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; STM . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; std :: sort ( ScratchRegs . begin ( ) , ScratchRegs . end ( ) , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 )


<s> if ( NewMB > <NUM_LIT> || NewSH > <NUM_LIT> ) return false ; if ( ( <NUM_LIT> - NewSH ) != MEMI ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewSH ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( NewMB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; NumRotatesCollapsed ++


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT Op1VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT ResVT = Val . getValueType ( ) ; if ( ! isTypeLegal ( ResVT ) ) return SDValue ( ) ; bool ValidTypeForStoreFltAsInt = ( Op1VT == <STR_LIT> || Op1VT == <STR_LIT> || ( Subtarget . hasP9Vector ( ) && ( Op1VT == <STR_LIT> || Op1VT == <STR_LIT> ) ) ) ; if ( ResVT == <STR_LIT> || ! Subtarget . hasP8Vector ( ) || cast < StoreSDNode > ( N ) -> isTruncatingStore ( ) || ! ValidTypeForStoreFltAsInt


<s> return ( __m256 ) __builtin_ia32_vfrczps256 (


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O <<


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned V0 = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back (


<s> static int iq2000_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { if ( mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - <NUM_LIT> ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr ,


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFCOPYSIGN ( SDValue Op , SelectionDAG & DAG ) const { EVT Ty = Op . getValueType ( ) ; assert ( Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( Ty == <STR_LIT> || Has<ISA_LIT>64 ) return LowerFCOPYSIGNLargeIntReg ( Op , DAG ) ; return LowerFCOPYSIGNSmallIntReg ( Op , DAG ,


<s> default : return false ; } unsigned DstIdx = <NUM_LIT> ; unsigned SrcIdx = IncDec -> getNumExplicitDefs ( ) ; while ( IncDec -> getOperand ( DstIdx ) . getReg ( ) != Reg ) { if ( IncDec -> getOperand ( SrcIdx ) . isReg ( ) ) ++ DstIdx ; ++ SrcIdx ; } if ( ! mi_match ( IncDec -> getOperand ( SrcIdx ) . getReg ( ) , MRI , m_all_of ( m_MInstr ( Load ) , m_FoldedLdAbs

( StoreMI , Addr , AA ) ) ) ) return false ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; for ( auto RegNo : getRegList ( ) ) Inst .

addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << RegNo << <STR_LIT> << Reg << <STR_LIT> ) ; return RegNo ; } else if ( MO . isImm ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> << MO . getImm ( ) << <STR_LIT> ) ; return static_cast < unsigned > ( MO . getImm ( ) ) ; } LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MI , MO . getExpr ( ) , Fixups ,


<s> RC = getRegClassFor ( ( VT == <STR_LIT> ) ? <STR_LIT> : VT ) ; assert ( Reg < RC -> getNumRegs ( ) ) ; return std :: make_pair ( * ( RC -> begin ( ) + Reg ) ,


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { _parser = <STR_LIT> ( )


<s> pa_asm_output_aligned_local ( FILE , NAME , SIZE , ALIGN ) { rtx addr = ADDR ; \ switch ( GET_CODE ( addr ) ) \ { \ case REG : \ fprintf ( FILE , <STR_LIT> , reg_names [ REGNO ( addr ) ] ) ; \ break ; \ case PLUS : \ gcc_assert ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) ; \ fprintf ( FILE , <STR_LIT> , ( int ) INTVAL ( XEXP ( addr , <NUM_LIT> ) ) , \ reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; \ break ; \ case LO_SUM : \ if ( ! symbolic_operand ( XEXP ( addr , <NUM_LIT> ) , VOIDmode ) ) \ fputs ( <STR_LIT> , FILE ) ; \ else if ( flag_pic == <NUM_LIT> ) \ fputs ( <STR_LIT> , FILE ) ; \ else \ fputs ( <STR_LIT> , FILE ) ; \ pa_output_global_address ( FILE , XEXP ( addr , <NUM_LIT>

) , <NUM_LIT> ) ; \ fputs ( <STR_LIT> , FILE ) ; \ output_operand ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; \ fputs ( <STR_LIT> , FILE ) ; \ break ; \ case CONST_INT : \ fprintf ( FILE , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( addr ) ) ; \ break ; \ default : \ output_addr_const ( FILE , addr ) ; \ } }


<s> bool isU4Imm ( ) const { return isImm ( <NUM_LIT>


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ; if ( ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ) { if ( NC -> getZExtValue ( ) * <NUM_LIT> == LdSt -> getMemoryVT ( ) . getSizeInBits ( ) ) Offset = CurDAG ->


<s> case GTU : fputs ( <STR_LIT> , file ) ; return ; case GEU : fputs ( <STR_LIT> , file ) ; return ; case LTU : fputs ( <STR_LIT> , file ) ; return ; case LEU : fputs ( <STR_LIT> , file ) ; return ; default : abort_with_insn ( x , <STR_LIT> ) ; } return ; } if ( code == REG ) { int regno = REGNO ( x ) ; if ( letter == 'D' ) regno ++ ; fprintf ( file , <STR_LIT> , reg_names [ regno ] ) ; return ; } if ( code == MEM ) { output_address ( XEXP ( x , <NUM_LIT> ) ) ; return ; } if ( code == CONST_INT || code == CONST_DOUBLE ) { if ( GET_MODE ( x ) ==


<s> if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return false ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return false ; return


<s> const SDLoc & dl ( Op ) ; unsigned HwWidth = <NUM_LIT> * Subtarget . getVectorLength ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT ResTy = ty ( Op ) ; MVT OpTy = ty ( Op0 ) ; if ( ! Subtarget . isHVXElementType ( OpTy ) || ! Subtarget . isHVXElementType ( ResTy ) ) return SDValue ( ) ; auto getFactor = [ HwWidth ] ( MVT Ty ) { unsigned Width = Ty . getSizeInBits ( ) ; return HwWidth > Width ? HwWidth / Width : <NUM_LIT> ; } ; auto getWideTy = [ getFactor ] ( MVT Ty ) { unsigned WideLen = Ty . getVectorNumElements ( ) * getFactor ( Ty ) ; return <STR_LIT> ( Ty . getVectorElementType ( ) , WideLen ) ; } ; unsigned Opcode = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue WideOp = appendUndef ( Op0 , getWideTy ( OpTy ) , DAG ) ; SDValue WideRes = DAG . getNode ( Opcode , dl , getWideTy ( ResTy ) , WideOp ) ; return WideRes


<s> assert ( ! Subtarget -> has<ISA_LIT>32r6 ( ) ) ; EVT Ty = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Mult = DAG . getNode ( NewOpc , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Lo , Hi ; if ( HasLo ) Lo = DAG . getNode (


<s> bool Imm ; return SelectSMRDOffset ( Addr , Offset , Imm ) && ! Imm && !


<s> bool isSub = NumBytes < <NUM_LIT> ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( IsLP64 ) ; else Opc = isSub ? getSUBriOpcode ( IsLP64 , Offset ) : getADDriOpcode ( IsLP64 , Offset ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? <STR_LIT> : <STR_LIT> ) : ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr


<s> <ISA_LIT>AsmLexer ( const Target & T , const MCRegisterInfo & MRI , const MCAsmInfo & MAI ) : <ISA_LIT>BaseAsmLexer ( T


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; Changed = removeDeadCode ( MDT -> getRootNode ( ) ) ; const <ISA_LIT>Evaluator HE ( * HRI , * MRI , * HII , MF ) ; BitTracker BTLoc ( HE , MF ) ; BTLoc . trace ( isDebug ( ) ) ; BTLoc . run ( ) ; CellMapShadow MS ( BTLoc ) ; CMS = & MS ; buildOrderingMF ( BaseOrd ) ; buildOrderingBT ( BaseOrd , CellOrd ) ; if ( isDebug ( ) ) { dbgs ( ) << <STR_LIT> ; for ( RegisterOrdering :: iterator I = CellOrd . begin ( ) , E = CellOrd . end ( ) ; I != E ; ++ I ) { unsigned VR = I -> first , Pos = I -> second ; dbgs ( ) << PrintReg ( VR , HRI ) << <STR_LIT> << Pos << <STR_LIT> ; } } MachineBasicBlock * RootB = MDT -> getRoot ( ) ; OrderedRegisterList AvailR ( CellOrd ) ; const char * const TGName = <STR_LIT> ; const char * const TGDesc = <STR_LIT> ; { NamedRegionTimer _T ( <STR_LIT> , <STR_LIT> , TGName , TGDesc , TimingDetail ) ; collectInBlock ( RootB , AvailR ) ; computeRemovableRegisters ( ) ; } if ( isDebug ( ) ) { dbgs ( ) << <STR_LIT> ; dump_map ( ) ; } if ( IFMap . empty ( ) ) return Changed ; { NamedRegionTimer _T ( <STR_LIT> , <STR_LIT> , TGName , TGDesc , TimingDetail ) ; pruneCandidates ( )


<s> unsigned NewDMaskVal = <NUM_LIT> ; unsigned OrigLoadIdx = <NUM_LIT> ; for ( unsigned SrcIdx = <NUM_LIT> ; SrcIdx < <NUM_LIT> ; ++ SrcIdx ) { const unsigned Bit = <NUM_LIT> << SrcIdx ; if ( ! ! ( DMaskVal & Bit ) ) { if ( ! ! DemandedElts [ OrigLoadIdx ] ) NewDMaskVal |= Bit ; OrigLoadIdx ++ ; } } if ( DMaskVal != NewDMaskVal ) Args [ DMaskIdx ] = ConstantInt :: get ( DMask -> getType ( ) , NewDMaskVal ) ; } unsigned NewNumElts = DemandedElts . countPopulation ( ) ; if ( ! NewNumElts ) return UndefValue :: get ( II . getType ( ) ) ; if ( II . getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> && NewNumElts == <NUM_LIT> ) return nullptr ; if ( NewNumElts >= VWidth && DemandedElts . isMask ( ) ) { if ( DMaskIdx >= <NUM_LIT> ) II . setArgOperand ( DMaskIdx , Args [ DMaskIdx ] ) ; return nullptr ; } SmallVector < Type * , <NUM_LIT> > OverloadTys ; if ( ! <STR_LIT> ( II . getCalledFunction ( ) , OverloadTys ) ) return nullptr ; Module * M = II . getParent ( ) -> getParent ( ) -> getParent ( ) ; Type * EltTy = IIVTy -> getElementType ( ) ; Type * NewTy = ( NewNumElts == <NUM_LIT> ) ? EltTy : FixedVectorType :: get ( EltTy , NewNumElts ) ; OverloadTys [ <NUM_LIT> ] = NewTy ; Function * NewIntrin = <STR_LIT> ( M , II .


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { PM -> add ( create<ISA_LIT>FPMoverPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID


<s> return ( __m128 ) __builtin_ia32_subps ( ( __v4sf )


<s> ValidCopy = KnownValid || isValidCopy ( I , DstRegBank , MRI , TRI , RBI ) ; assert ( ValidCopy && <STR_LIT> ) ; ( void ) KnownValid ; return ValidCopy ; } ; if ( I . isCopy ( ) ) { if ( ! SrcRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned SrcSize = TRI . getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = TRI . getRegSizeInBits ( * DstRC ) ; unsigned SubReg ; if ( getMinSizeForRegBank ( SrcRegBank ) > DstSize ) { const TargetRegisterClass * DstTempRC = getMinClassForRegBank ( DstRegBank , SrcSize , true ) ; getSubRegForClass ( DstRC , TRI , SubReg ) ; MachineIRBuilder MIB ( I ) ; auto Copy = MIB . buildCopy ( { DstTempRC } , { SrcReg } ) ; copySubReg ( I , MRI , RBI , Copy . getReg ( <NUM_LIT> ) , DstRC , SubReg ) ; } else if ( SrcSize > DstSize ) { const TargetRegisterClass * SubRegRC = getMinClassForRegBank ( SrcRegBank , DstSize , true ) ; getSubRegForClass ( SubRegRC , TRI , SubReg ) ; copySubReg ( I , MRI , RBI , SrcReg , DstRC , SubReg ) ; } else if ( DstSize > SrcSize ) { const TargetRegisterClass * PromotionRC = getMinClassForRegBank ( SrcRegBank , DstSize , true ) ; getSubRegForClass ( SrcRC , TRI , SubReg ) ; Register PromoteReg = MRI . createVirtualRegister ( PromotionRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , PromoteReg ) . addImm ( <NUM_LIT> ) .


<s> <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa (


<s> if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ; } else { assert ( DispSpec . isExpr ( )


<s> break ; } const unsigned PtrIdx = <NUM_LIT> ; const unsigned ValIdx = <NUM_LIT> ; if ( DA -> isDivergentUse ( & I . getOperandUse ( PtrIdx ) ) ) { return ; } const bool ValDivergent = DA -> isDivergentUse ( & I . getOperandUse ( ValIdx ) ) ; if ( ValDivergent && ( ! ST -> hasDPP ( ) || DL -> getTypeSizeInBits ( I . getType ( ) ) != <NUM_LIT> ) ) { return ; } const ReplacementInfo Info = { & I , Op , ValIdx , ValDivergent } ; ToReplace . push_back ( Info


<s> if ( TARGET_64BIT ) d_add_builtin_version ( <STR_LIT> ) ; else d_add_builtin_version ( <STR_LIT> ) ; if ( TARGET_SOFT_FLOAT ) d_add_builtin_version


<s> if ( auto COff = getIConstantVRegSExtVal ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) { int64_t Imm = * COff ; if ( isInt < <NUM_LIT> > ( Imm ) ) { AM . Disp = static_cast < int32_t > ( Imm ) ; AM . Base . Reg = I .


<s> if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ; reg = ( mode == QImode ) ? X : AX ; if ( mode == QImode || ! is_virtual_register ( OP ( opno ) ) ) { OP ( opno ) = move_to_acc ( opno , before ) ; OP ( opno ) = move_acc_to_reg ( OP ( opno )


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) return <NUM_LIT> ; FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex


<s> unsigned Value = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; Value <<= ( Bits + <NUM_LIT> ) ; int32_t tmp = ( int32_t ) MO2


<s> addPass ( new <ISA_LIT>DAGToDAGISel ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ; } void addPreEmitPass ( ) override { addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; } } ; return new <ISA_LIT>PassConfig ( this


<s> } EVT SignExtSrcVT = cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; EVT SrcMemVT = cast < VTSDNode > ( Src -> getOperand ( MemVTOpNum ) ) -> getVT ( ) ; if ( ( SignExtSrcVT != SrcMemVT ) || ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( DstVT , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> ; I < Src -> getNumOperands ( ) ; ++ I ) Ops . push_back ( Src -> getOperand ( I ) ) ; SDValue ExtLoad = DAG . getNode ( NewOpc , SDLoc ( N ) , VTs , Ops ) ; DCI . CombineTo ( N , ExtLoad ) ; DCI . CombineTo ( Src . getNode ( ) , ExtLoad , ExtLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N ,


<s> __tmp . f = __builtin_ia32_vec_ext_v4sf ( ( __v4sf ) __X , __N ) ; return __tmp . i


<s> bool supportsScalableVectors ( ) const { return ST -> hasVInstructions


<s> } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || (


<s> unsigned NumElems = HwLen / ( ElemTy . getSizeInBits ( )


<s> SDValue <ISA_LIT>TargetLowering :: getSqrtInputTest ( SDValue Op , SelectionDAG & DAG , const DenormalMode & Mode ) const { EVT VT = Op . getValueType ( ) ; if ( ! isTypeLegal ( <STR_LIT> ) || ( VT != <STR_LIT> && ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! Subtarget . hasVSX ( ) ) ) ) return TargetLowering :: getSqrtInputTest


<s> EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue , EltTy . getSizeInBits ( ) ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { int32_t Log2 = ImmValue . exactLogBase2 ( ) ; if ( Log2 != - <NUM_LIT> ) { Imm = CurDAG -> getTargetConstant ( Log2 , SDLoc ( N ) , EltTy ) ; return true ; } } return false


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmfaa ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t


<s> if ( ! DefMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; const MCInstrDesc & UseMCID = UseMI -> getDesc ( ) ; if ( UseMCID . isPseudo ( ) ) return false ; unsigned UseIdx ; for ( UseIdx = <NUM_LIT> ; UseIdx < UseMI -> getNumOperands ( ) ; ++ UseIdx ) if ( UseMI -> getOperand ( UseIdx ) . isReg ( ) && UseMI -> getOperand ( UseIdx ) . getReg ( ) == Reg ) break ; assert ( UseIdx < UseMI -> getNumOperands ( ) && <STR_LIT> ) ; assert ( UseIdx < UseMCID . getNumOperands ( ) && <STR_LIT> ) ; const MCOperandInfo * UseInfo = & UseMCID . OpInfo [ UseIdx ] ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { if ( UseInfo -> RegClass != <NUM_LIT> ) return false ; } else { if ( UseInfo -> RegClass != <STR_LIT> && UseInfo -> RegClass != <STR_LIT> ) return false ; } if ( UseInfo -> Constraints != <NUM_LIT> ) return false ; unsigned ZeroReg ; if ( UseInfo -> isLookupPtrRegClass ( ) ) { bool is<ISA_LIT>64 = TM . getSubtargetImpl ( ) -> is<ISA_LIT>64 ( ) ; ZeroReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; } else { ZeroReg = UseInfo -> RegClass == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI -> getOperand ( UseIdx ) . setReg ( ZeroReg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true


<s> if ( ! PointerEntry . second ) return PointerEntry . first -> second ; auto * I16Ty = Type :: getInt16Ty ( Ctx ) ; GlobalVariable * LDSPointer = new GlobalVariable ( M , I16Ty , false , GlobalValue :: InternalLinkage , UndefValue :: get ( I16Ty ) , GV -> getName ( ) + Twine ( <STR_LIT> ) , nullptr , GlobalVariable :: NotThreadLocal , <ISA_LIT>AS :: LOCAL_ADDRESS ) ; LDSPointer -> setUnnamedAddr ( GlobalValue :: UnnamedAddr


<s> Value * <ISA_LIT>IREmitter :: visitWrapperRIP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; SDLoc SL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || ! C -> isNullValue ( ) ) return SDValue ( ) ; SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) ,

RHS , LHS . getOperand ( <NUM_LIT> ) } ;


<s> if ( Set . find ( Val ) == Set . end ( ) )


<s> BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && CI . Paired -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * CI . Paired


<s> if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; } } printOperand ( MI , OpNo


<s> if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { Amount -= TII . getFramePoppedByCallee ( * I ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( ScratchReg ) && <STR_LIT> ) ; BuildStackAdjustment ( MF , MBB , I , I -> getDebugLoc


<s> bool <ISA_LIT>CFGStructurizer :: hasBackEdge ( MachineBasicBlock * MBB ) const { MachineLoop * LoopRep = MLI -> getLoopFor (


<s> assert ( ( Type == <STR_LIT> ) == IsFunc ) ; if ( Type == <STR_LIT> || IsFunc ) report_fatal_error ( <STR_LIT> ) ; if ( Type == <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Type == <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const auto & WinEHXMMSlotInfo = <ISA_LIT>FI -> getWinEHXMMSlotInfo ( ) ; const auto it = WinEHXMMSlotInfo . find ( FI ) ; if ( it == WinEHXMMSlotInfo . end ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) . getFixed ( ) ; FrameReg = TRI -> getStackRegister ( ) ; return alignDown ( MFI . getMaxCallFrameSize ( ) , getStackAlign ( ) . value ( ) ) + it


<s> if ( arg . type && TREE_CODE ( arg . type ) == VECTOR_TYPE ) mode = type_natural_mode ( arg . type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) reg = function_arg_ms_64 ( cum , mode , arg . mode , arg . named , arg . type , bytes ) ; else reg = function_arg_64 ( cum , mode , arg . mode , arg . type , arg . named ) ; } else reg = function_arg_32 ( cum , mode , arg . mode , arg . type , bytes , words ) ; if ( reg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return reg


<s> } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR || FR ) ; unsigned MuxR = <NUM_LIT> , MuxSR = <NUM_LIT> ; if ( TR && FR ) { Register DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; MuxR = buildMux ( FP . SplitB , FP . SplitB -> getFirstTerminator ( ) , RC , FP . PredR , TR , TSR , FR , FSR ) ; } else if ( TR ) { MuxR = TR ; MuxSR = TSR ; } else { MuxR = FR ; MuxSR = FSR ; } PN -> addOperand ( MachineOperand :: CreateReg ( MuxR , false , false , false , false , false


<s> case GK_RV730 : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_RV730 ; case GK_RV770 : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_RV770 ; case GK_CEDAR : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CEDAR ; case GK_CYPRESS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CYPRESS ; case GK_JUNIPER : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_JUNIPER ; case GK_REDWOOD : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_REDWOOD ; case GK_SUMO : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_SUMO ; case GK_BARTS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_BARTS ; case GK_CAICOS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAICOS ; case GK_CAYMAN : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAYMAN ; case GK_TURKS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_TURKS ; case GK_GFX600 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX600 ; case GK_GFX601 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX601 ; case GK_GFX700 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 ; case GK_GFX701 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 ; case GK_GFX702 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 ; case GK_GFX703 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 ; case GK_GFX704 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 ; case GK_GFX801 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 ; case GK_GFX802 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 ; case GK_GFX803 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 ; case GK_GFX810 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 ; case GK_GFX900 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 ; case GK_GFX902 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 ; case GK_GFX904 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 ; case GK_GFX906 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 ; case GK_GFX908 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 ; case GK_GFX909 : return ELF ::


<s> if ( I == E ) return false ; while ( I != E && ! I -> isBranch ( ) && ! I -> isReturn ( ) ) { switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> if ( pred ) rws_sum [ regno ] . write_count ++ ; else rws_sum [ regno ] . write_count = <NUM_LIT> ; rws_sum [ regno ] . written_by_fp |= flags . is_fp ; rws_sum [ regno ] . written_by_and


<s> bool isLegalMaskedStore ( Type * DataTy , MaybeAlign Alignment ) { return isLegalMaskedLoad ( DataTy


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && OpInfo [ <NUM_LIT> ] . isPredicate ( ) && OpInfo [ <NUM_LIT> ]

. RegClass == <STR_LIT> && <STR_LIT> ) ;


<s> void insert ( unsigned BBNum , BasicBlockInfo BBI ) { BBInfo . insert ( BBInfo . begin


<s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : reverse ( NonLibcallCSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; } const char * RestoreLibCall = getRestoreLibCallName ( * MF , CSI ) ; if ( RestoreLibCall )


<s> Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) { EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue Eq = DAG . getSetCC ( DL , CCVT , Operand , FPZero , <STR_LIT> ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( VT . isVector ( ) ? <STR_LIT> : <STR_LIT> , DL , VT , Eq , Operand , Estimate ) ; } ExtraSteps =


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i + NumElems / <NUM_LIT> ) , i + NumElems ) ) return false ; return true


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( MFI . hasCalls ( ) || MFI . hasVarSizedObjects (


<s> BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; } BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent


<s> fprintf ( asm_out_file , <STR_LIT> , * ( const char *

const * ) directive , XCOFF_CSECT_DEFAULT_ALIGNMENT_STR ) ;


<s> static unsigned sizeSIBByte ( ) { return


<s> unsigned <ISA_LIT>TTI :: getShuffleCost ( ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) const { return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index


<s> unsigned <ISA_LIT>_MC :: getDwarfRegFlavour ( const Triple & TT , bool isEH ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return DWARFFlavour :: <ISA_LIT>_64 ; if ( TT . isOSDarwin ( ) ) return isEH ? DWARFFlavour :: <ISA_LIT>_32_DarwinEH : DWARFFlavour :: <ISA_LIT>_32_Generic ; if ( TT . isOSCygMing ( ) ) return DWARFFlavour ::


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . isImm ( ) ) O << ( unsigned


<s> last2 = <NUM_LIT> ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; length = get_attr_length ( insn ) ; if ( length > <NUM_LIT> && USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; } mips_sim_finish_insn ( & state , insn )


<s> if ( ReadCount == <NUM_LIT> && Buf [ <NUM_LIT> ] . getKind ( ) == AsmToken :: RParen ) { HadParens = true ; LParen = getParser ( ) . getTok ( ) ; getParser ( ) . Lex ( ) ; } } switch ( getLexer ( ) . getKind ( ) ) { default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name


<s> switch ( parser . getAssemblerDialect ( ) ) { case <NUM_LIT> : ParseBytes = PrintAsEncoded ; break ; case <NUM_LIT> : ParseBytes = PrintCallAsBytes ;


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmian ( __ev64_opaque__ a , __ev64_opaque__ b ) { __ev64_opaque__ t ; t = __ev_mwhsmi ( a


<s> rtl_opt_pass * make_pass_tag_collision_avoidance ( gcc :: context * ctxt ) { return new pass_tag_collision_avoidance (


<s> SDValue Lane = Op1 . getOperand ( <NUM_LIT> ) ; EVT ResTy = N -> getValueType ( <NUM_LIT> ) ; EVT VecResTy ; SDLoc DL ( N ) ; assert ( Vec . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Vec . getValueType ( ) == <STR_LIT> ) VecResTy = <STR_LIT> ; else if ( Vec . getValueType ( ) == <STR_LIT> ) VecResTy = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Convert = DAG . getNode ( <STR_LIT> , DL , VecResTy , IID , Vec , Shift ) ; return DAG . getNode ( <STR_LIT> , DL , ResTy , Convert , Lane ) ; } return SDValue ( )


<s> gcc_assert ( TARGET_BACKCHAIN ) ; if ( TARGET_PACKED_STACK ) chain = plus_constant ( stack_pointer_rtx , STACK_POINTER_OFFSET - UNITS_PER_WORD ) ; else chain =


<s> if ( Pos != std :: string :: npos ) { Pos += StrToFind . length ( ) ; std :: string Color = <STR_LIT> ; char c = Sectn . at ( Pos ) ; while ( c >= '0' &&


<s> static bool isKnownNeverSNan ( SelectionDAG & DAG , SDValue


<s> SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP


<s> break ; case <STR_LIT> : Changed |= shortenFusedFPOp ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenFusedFPOp ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn001AddCC ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn001AddCC ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; default : { int TwoOperandOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( TwoOperandOpcode == - <NUM_LIT> ) break ; if ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && ( ! MI . isCommutable ( ) || MI . getOperand ( <NUM_LIT>

) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) || ! TII -> commuteInstruction ( MI , false , <NUM_LIT> , <NUM_LIT> ) ) ) break ;


<s> return & InstrInfo -> getRegisterInfo


<s> } const StructType * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) { Type * ETy = STy -> getElementType ( i ) ; unsigned int align = getOpenCLAlignment ( TD , ETy ) ; if ( align > alignStruct ) alignStruct = align ; } return alignStruct


<s> return selectIntToBool ( IntReg , ResVReg , ArgType , ResType , I ) ; } bool IsSigned = GR . isScalarOrVectorSigned ( ResType ) ; unsigned Opcode = IsSigned ?


<s> DeadMap [ R ] . add ( IndexType :: Entry , IndexType :: Exit , false , false ) ; return ; } RangeList & RL = F -> second ; RangeList :: iterator A = RL . begin ( ) , Z = RL . end ( ) - <NUM_LIT> ; if ( A -> start ( ) != IndexType :: Entry ) { IndexType DE = IndexMap . getPrevIndex ( A -> start ( ) ) ; if ( DE != IndexType :: Entry ) DeadMap [ R ] . add ( IndexType :: Entry , DE , false , false ) ; } while ( A != Z ) { IndexType AE = ( A -> end ( ) == IndexType :: None ) ? A -> start ( ) : A -> end ( ) ; IndexType DS = IndexMap . getNextIndex ( AE ) ; ++ A ; IndexType DE = IndexMap . getPrevIndex ( A


<s> SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; int FirstFI = - MFI -> getNumFixedObjects ( ) - <NUM_LIT> , LastFI = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue Arg = OutVals [ i ] ; CCValAssign & VA = ArgLocs [ i ] ; MVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( <STR_LIT> ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; WriteByValArg ( ByValChain , Chain , dl , RegsToPass , MemOpChains , LastFI , MFI , DAG , Arg , VA , Flags , getPointerTy ( ) , Subtarget -> isLittle ( ) ) ; continue ; } if ( VA . isMemLoc ( ) ) { LastFI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue PtrOff = DAG . getFrameIndex ( LastFI , getPointerTy ( ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } } if ( LastFI ) <ISA_LIT>FI -> extendOutArgFIRange ( FirstFI , LastFI ) ; if ( InChain != ByValChain ) DAG . UpdateNodeOperands ( CallSeqStart . getNode ( ) , ByValChain , NextStackOffsetVal ) ; if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag


<s> case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT>


<s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst ::


<s> void <ISA_LIT>AsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo


<s> WriteGraph ( OS , G , false , <STR_LIT> + MF . getName ( )


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeMemChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const { if ( AddrSpace == ST -> get<ISA_LIT>AS (


<s> assert ( MI . isRegSequence ( ) ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( DstReg ) ) ) return false ; if ( ! MRI . hasOneUse ( DstReg ) ) return false ; MachineInstr & CopyUse = * MRI . use_instr_begin ( DstReg ) ; if ( ! CopyUse . isCopy ( ) ) return false ; if ( CopyUse . getOperand ( <NUM_LIT> ) . getReg ( ) . isPhysical ( ) ) return false ; const TargetRegisterClass * SrcRC , * DstRC ; std :: tie ( SrcRC , DstRC ) = getCopyRegClasses ( CopyUse , * TRI , MRI ) ; if ( ! isSGPRToVGPRCopy ( SrcRC , DstRC , * TRI ) ) return false ; if ( tryChangeVGPRtoSGPRinCopy ( CopyUse , TRI , TII ) ) return true ; unsigned SubReg = CopyUse . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( SubReg != <STR_LIT> ) return false ; MRI . setRegClass ( DstReg , DstRC ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( CopyUse . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; bool IsAGPR = TRI -> isAGPRClass ( DstRC ) ; for ( unsigned I = <NUM_LIT> , N = MI . getNumOperands ( ) ; I != N ; I += <NUM_LIT> ) { Register SrcReg = MI . getOperand ( I ) . getReg ( ) ; unsigned SrcSubReg = MI . getOperand ( I ) . getSubReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; assert ( TRI -> isSGPRClass ( SrcRC ) && <STR_LIT> ) ; SrcRC = TRI -> getSubRegClass ( SrcRC , SrcSubReg ) ; const TargetRegisterClass * NewSrcRC = TRI -> getEquivalentVGPRClass ( SrcRC ) ; Register TmpReg = MRI . createVirtualRegister ( NewSrcRC ) ; BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , TmpReg ) . add ( MI . getOperand ( I ) ) ; if ( IsAGPR ) { const TargetRegisterClass * NewSrcRC = TRI -> getEquivalentAGPRClass ( SrcRC ) ; Register TmpAReg = MRI . createVirtualRegister ( NewSrcRC ) ; unsigned Opc = NewSrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( Opc ) , TmpAReg ) . addReg (


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned ( MachineOperand & Root ) const { Register Reg ; unsigned Offset ; std :: tie ( Reg , Offset ) = selectDS64Bit4ByteAlignedImpl ( Root ) ; return {


<s> enum machine_mode dest_mode = GET_MODE ( dest ) ; int vsel_insn_index = get_vsel_insn ( GET_MODE ( dest ) ) ; temp = gen_reg_rtx ( dest_mode ) ; t = gen_rtx_SET ( VOIDmode , temp , gen_rtx_UNSPEC ( dest_mode , gen_rtvec ( <NUM_LIT> , op2 , op1 , mask


<s> bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } return true


<s> return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc Loc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { MCInst Inst ; unsigned MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo


<s> static SDValue extractF64Exponent ( SDValue Hi , SDLoc SL , SelectionDAG & DAG ) { const unsigned FractBits = <NUM_LIT> ; const unsigned ExpBits = <NUM_LIT> ; SDValue ExpPart = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( FractBits - <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( ExpBits , <STR_LIT> ) ) ; SDValue Exp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , ExpPart , DAG . getConstant (


<s> else if ( size == <NUM_LIT> ) return RomData32bitsDirective ; else return NULL


<s> return ( mode1 == mode2 || ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) &&

( mode1 != SFmode && mode2 != SFmode ) ) ) ;


<s> int <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , bool IsComplex ) { unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) &&

IsComplex ) return NumVectorInstToHideOverhead ;


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , Register Addr , uint64_t MemSize , MachinePointerInfo & MPO , CCValAssign & VA ) override { Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ <NUM_LIT> ]


<s> assert ( GISel && <STR_LIT> ) ; return GISel -> getLegalizerInfo (


<s> addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg128RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg32RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg64RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg64RegClass ) ; computeRegisterProperties ( ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom


<s> bool <ISA_LIT>FrameLowering :: targetHandlesStackFrameRounding (


<s> int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || Val == std ::


<s> if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; if ( Node -> getMachineOpcode ( ) == AMDGPU :: INSERT_SUBREG || Node -> getMachineOpcode ( ) == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return


<s> SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( isa < ConstantInt > ( * RV ) ) { const Constant * C = cast < Constant > ( RV ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( C , <STR_LIT> ) ; unsigned RetReg = ValLocs [ <NUM_LIT> ] . getLocReg ( ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign


<s> if ( Nd . getMemoryVT ( ) != <STR_LIT> || ! NoDPLoadStore ) return <ISA_LIT>TargetLowering :: lowerSTORE ( Op , DAG ) ; SDLoc DL ( Op ) ; SDValue Val = Nd . getValue ( ) , Ptr = Nd . getBasePtr ( ) , Chain = Nd . getChain ( ) ; EVT PtrVT = Ptr . getValueType ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val

, DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock &


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , TTI


<s> RegOp . setReg ( SubRegCopy . getReg ( <NUM_LIT> ) ) ; if ( ! Register :: isPhysicalRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) RBI . constrainGenericRegister ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * To , MRI ) ; return


<s> struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; enum insn_code icode = N2FPU_ICODE ( code ) ; int nargs , argno , opno = <NUM_LIT> ; int num_operands = N2FPU ( code ) . num_operands ; machine_mode dst_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; bool has_target_p = ( dst_mode != VOIDmode ) ; if ( N2FPU_N ( code ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> <STR_LIT> , N2FPU_NAME ( code ) , N2FPU_NAME ( code ) ) ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , dst_mode ) ; else num_operands -= <NUM_LIT> ; nargs = call_expr_nargs ( exp ) ; for ( argno = <NUM_LIT> ; argno < nargs ; argno ++ ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( & ops [ opno ++ ] , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } if ( ! maybe_expand_insn ( icode , num_operands , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ]


<s> unsigned Op = MI . getOpcode ( ) ; switch ( Op ) { case <STR_LIT> : case <STR_LIT> : { if ( ( Op == <STR_LIT> && MFI -> getMode ( ) . FP32Denormals ) || ( Op == <STR_LIT> && MFI -> getMode ( ) . FP64FP16Denormals ) ) return std :: make_pair ( nullptr , <STR_LIT> ) ; const MachineOperand * RegOp = nullptr ; const MachineOperand * ImmOp = nullptr ; const MachineOperand * Src0 = TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src0 -> isImm ( ) ) { ImmOp = Src0 ; RegOp = Src1 ; } else if ( Src1 -> isImm ( ) ) { ImmOp = Src1 ; RegOp = Src0 ; } else return std :: make_pair ( nullptr , <STR_LIT> ) ; int OMod = getOModValue ( Op , ImmOp -> getImm ( )


<s> if ( AddrDispShift != <NUM_LIT> ) { if ( MI . isNonListDebugValue ( ) ) { Expr = DIExpression :: prepend ( Expr , DIExpression :: StackValue , AddrDispShift ) ; } else { SmallVector < uint64_t , <NUM_LIT> > Ops ; DIExpression :: appendOffset ( Ops , AddrDispShift ) ; for ( MachineOperand & Op : MI . getDebugOperandsForReg ( OldReg ) ) { unsigned OpIdx = MI . getDebugOperandIndex ( & Op ) ; Expr = DIExpression :: appendOpsToArg ( Expr , Ops , OpIdx ) ; } } } MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI . isIndirectDebugValue ( ) ; const MDNode * Var = MI . getDebugVariable ( ) ; unsigned Opcode = MI . isNonListDebugValue ( ) ? TargetOpcode :: DBG_VALUE : TargetOpcode :: DBG_VALUE_LIST ; if ( IsIndirect ) assert ( MI . getDebugOffset ( ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < MachineOperand , <NUM_LIT>


<s> if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( CurDAG -> getTargetConstant ( LaneNo


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Vd = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( regs == <NUM_LIT> || regs > <NUM_LIT> || ( Vd + regs ) > <NUM_LIT> ) { regs = Vd + regs > <NUM_LIT> ? <NUM_LIT> - Vd : regs ; regs = std :: max ( <NUM_LIT> , regs ) ; regs = std :: min ( <NUM_LIT> , regs


<s> unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , DL . getPointerSizeInBits ( <NUM_LIT> ) ) ) ; MIRBuilder . buildFrameIndex ( AddrReg ,


<s> SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Lane = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Lane ) ) return SDValue ( ) ; Op . dump ( ) ; Op . getOperand ( <NUM_LIT> ) . dump (


<s> bool csky_simple_addr_operand_p ( rtx op ) { struct csky_address addr ; if ( ! decompose_csky_address ( op , & addr ) ) return false ; if ( addr . disp && GET_CODE ( addr


<s> unsigned PCLabelId = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * NewCPV = nullptr ; if ( ACPV -> isGlobalValue ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> , ACPV -> getModifier ( ) , ACPV -> mustAddCurrentAddress ( ) ) ; else if ( ACPV -> isExtSymbol ( ) ) NewCPV = <ISA_LIT>ConstantPoolSymbol :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) , PCLabelId , <NUM_LIT> ) ; else if ( ACPV -> isBlockAddress ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isLSDA ( ) ) NewCPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , PCLabelId , <STR_LIT> , <NUM_LIT> ) ; else if ( ACPV -> isMachineBasicBlock ( ) ) NewCPV = <ISA_LIT>ConstantPoolMBB :: Create ( MF . getFunction ( ) -> getContext ( ) , cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) , PCLabelId , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> )


<s> if ( SelectRegShifterOperand ( TrueVal , CPTmp0 , CPTmp1 , CPTmp2 ) ) { SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ,


<s> O << <STR_LIT> << getFunctionNumber ( )


<s> const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) .

addOperand ( TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;


<s> bool SelectOffsetUImm12 ( SDValue N , SDValue & UImm12 ) { const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ; if ( ! CN || CN -> getZExtValue ( ) % MemSize != <NUM_LIT> || CN -> getZExtValue ( ) / MemSize > <NUM_LIT> ) return false ; UImm12 = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) /


<s> if ( Worklist . empty ( ) ) return false ; const RangeTy & Range = Worklist . back (


<s> SDValue <ISA_LIT>TargetLowering :: ExpandFrameIndex ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * Func = MF . getFunction ( ) ; const std :: string Name = Func -> getName ( ) ; FrameIndexSDNode * FR = dyn_cast < FrameIndexSDNode > ( SDValue (


<s> static void fatal ( const char * msg ) { fprintf ( stderr , <STR_LIT> , msg ) ; abort (


<s> return ( __m512i ) __builtin_ia32_expandloadsi512_mask ( ( const __v16si * ) __P , ( __v16si )


<s> std :: string Name = AccessInfo . IsWrite ? <STR_LIT> : <STR_LIT> ; std :: string SymName = <STR_LIT> + Name + utostr ( <NUM_LIT> << AccessInfo . AccessSizeIndex ) + <STR_LIT> + utostr ( Reg ) ; Sym = OutContext . getOrCreateSymbol ( SymName ) ; } EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( Sym ,


<s> SmallVector < SDValue , <NUM_LIT> > ShufBytes ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> )


<s> uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ! Binary ) { MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; } const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; int Size = Desc . Size ; if ( ( TSFlags & <STR_LIT> ) != <STR_LIT> ) { bool isBundled = MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; if ( isBundled )


<s> GlobalAddressSDNode * GSDN = dyn_cast < GlobalAddressSDNode > ( TGA ) ; if ( GSDN -> getAddressSpace ( ) == <STR_LIT> ) return true ; return


<s> if ( isLoadAfterStore ( SU ) && CurSlots < <NUM_LIT> ) { unsigned Directive = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget >