<s> unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; assert ( Amount % <NUM_LIT> == <NUM_LIT> ) ; Amount /= <NUM_LIT> ; bool isU6 = isImmU6 ( Amount ) ; if ( ! isU6 && ! isImmU16 ( Amount ) ) { errs ( ) << <STR_LIT> << Amount << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ! isInt < <NUM_LIT> > ( ImmValue ) ; } return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Inst . getNumOperands ( ) == <NUM_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) ) { int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm (


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } return <NUM_LIT>


<s> assert ( Dmask ) ; Comp = countTrailingZeros ( Dmask ) ; Dmask &= ~ ( <NUM_LIT> << Comp ) ; } if ( Users [ Lane ] ) return ; Users [ Lane ] = * I ; NewDmask |= <NUM_LIT> << Comp ; } if ( NewDmask == OldDmask ) return ; std :: vector < SDValue > Ops ; Ops . push_back ( DAG . getTargetConstant ( NewDmask , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Node -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Node -> getOperand ( i ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops . data ( ) , Ops . size ( ) ) ; if ( NewDmask && ( NewDmask & ( NewDmask - <NUM_LIT> ) ) == <NUM_LIT> ) { SDValue RC = DAG . getTargetConstant ( AMDGPU :: VReg_32RegClassID , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = AMDGPU :: sub0 ; i < <NUM_LIT> ; ++


<s> SUnit * Pred = PredDep . getSUnit ( ) ; if ( <ISA_LIT>TII -> isLowLatencyInstruction ( * Pred -> getInstr ( ) ) ) { IsLowLatencyUser = true ; } if ( Pred -> NodeNum >= DAGSize ) continue ; unsigned PredPos = ScheduledSUnitsInv [ Pred -> NodeNum ] ; if ( PredPos >= MinPos ) MinPos = PredPos + <NUM_LIT> ; } if ( <ISA_LIT>TII -> isLowLatencyInstruction ( * SU -> getInstr ( ) ) ) { unsigned BestPos = LastLowLatencyUser + <NUM_LIT> ; if ( ( int ) BestPos <= LastLowLatencyPos ) BestPos = LastLowLatencyPos + <NUM_LIT> ; if ( BestPos < MinPos ) BestPos = MinPos ; if ( BestPos < i ) { for ( unsigned u = i ; u > BestPos ; -- u ) { ++ ScheduledSUnitsInv [ ScheduledSUnits [ u - <NUM_LIT> ] ] ; ScheduledSUnits [ u ] = ScheduledSUnits [ u - <NUM_LIT> ] ; } ScheduledSUnits [ BestPos ] = SU -> NodeNum ; ScheduledSUnitsInv [ SU -> NodeNum ] = BestPos ; } LastLowLatencyPos = BestPos ; if ( IsLowLatencyUser ) LastLowLatencyUser = BestPos ; } else if ( IsLowLatencyUser ) { LastLowLatencyUser = i ; } else if ( SU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> ) { bool CopyForLowLat = false ; for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( <ISA_LIT>TII -> isLowLatencyInstruction ( * Succ -> getInstr (


<s> if ( ! expectEqualInt ( Lexer , Err ) ) return false ; C .* ptr = ( T ) Lexer . getTok (


<s> else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , TII , dl , * this , NumBytes ) ; } else emitSPUpdate ( MBB , MBBI , TII , dl , * this , NumBytes ) ; } } if ( VARegSaveSize ) { while ( MBBI != MBB . end ( ) && isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ) . addReg ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) ; emitSPUpdate ( MBB , MBBI , TII , dl , * this , VARegSaveSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MBB . erase ( MBBI


<s> static bool isUnpackWdShuffleMask ( ArrayRef < int > Mask , MVT VT ) { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; SmallVector < int , <NUM_LIT> > Unpcklwd ; createUnpackShuffleMask ( <STR_LIT> , Unpcklwd


<s> static void mn10300_encode_section_info ( tree decl , rtx rtl , int first ATTRIBUTE_UNUSED ) { rtx symbol ; if ( GET_CODE ( rtl ) != MEM ) return ; symbol = XEXP ( rtl , <NUM_LIT> ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return ; if ( flag_pic ) SYMBOL_REF_FLAG ( symbol ) = ( *


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateTraceSyncBarrierOpt ( <STR_LIT> Opt , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_TraceSyncBarrierOpt ) ; Op -> TSBOpt . Val = Opt ; Op -> StartLoc = S


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) return false ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( MO . isTied ( ) ) return false ; RegUse & Map = MO . isDef ( ) ? Uses : Defs ; auto Conflict = Map . find ( Reg ) ; if ( Conflict == Map . end


<s> static void mt_print_operand_simple_address ( FILE * file , rtx addr ) { if ( ! addr ) error ( <STR_LIT> ) ; else switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( addr ) ] ) ; break ; case PLUS : { rtx reg = <NUM_LIT> ; rtx offset = <NUM_LIT> ; rtx arg0 = XEXP ( addr , <NUM_LIT> ) ; rtx arg1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( arg0 ) == REG ) { reg = arg0 ; offset = arg1 ; if ( GET_CODE ( offset ) == REG ) fatal_insn ( <STR_LIT> , addr ) ; } else if ( GET_CODE ( arg1 ) == REG ) reg = arg1 , offset = arg0 ; else if ( CONSTANT_P ( arg0 ) && CONSTANT_P ( arg1 ) ) { fprintf ( file , <STR_LIT> , reg_names [ GPR_R0 ] ) ; output_addr_const ( file , addr ) ; break ; } fprintf ( file , <STR_LIT> , reg_names [ REGNO ( reg ) ] ) ; output_addr_const ( file , offset ) ; break ; } case LABEL_REF : case SYMBOL_REF : case CONST_INT : case CONST : output_addr_const ( file


<s> B . getInt32 ( <STR_LIT> :: ET_NULL ) , B . getInt32 ( <NUM_LIT> ) , Undef , Undef , Undef , Undef , B . getTrue ( ) , B . getTrue ( ) , } ) ; } PHINode * PN = nullptr ; if ( F . getReturnType ( ) -> isVoidTy ( ) ) { B . CreateRetVoid ( ) ; } else { PN = B . CreatePHI ( F . getReturnType ( ) , ReturningBlocks . size ( ) , <STR_LIT> ) ; assert ( ! InsertExport ) ; B . CreateRet ( PN ) ; } for ( BasicBlock * BB : ReturningBlocks ) { if ( PN ) PN -> addIncoming ( BB -> getTerminator ( ) -> getOperand ( <NUM_LIT> ) , BB ) ; BB -> getTerminator ( ) -> eraseFromParent ( ) ; BranchInst :: Create ( NewRetBlock , BB ) ; } for ( BasicBlock * BB :


<s> return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_splat ( (

vec_uchar16 ) ( si_from_int ( <NUM_LIT> - count ) ) , <NUM_LIT> ) ) ) ) ;


<s> MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes (


<s> if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 ,


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> &&


<s> StringRef getPassName ( ) const override { return


<s> inline vector signed short vec_vmaxsh ( vector signed short a1 , vector signed short a2 ) { return ( vector signed short ) __builtin_altivec_vmaxsh ( ( vector signed short ) a1


<s> MachineBasicBlock :: iterator I = LoopBB . begin ( ) ; unsigned VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; unsigned SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned CondReg0 = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned CondReg1 = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned AndCond = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned SRsrcSub0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub0 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub1 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub2 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub3 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) . addReg ( SRsrcSub0 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub1 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub2 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub3 ) . addImm ( <STR_LIT> ) ; Rsrc . setReg ( SRsrc ) ; Rsrc . setIsKill ( true ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg0 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT> ) . addReg ( VRsrc , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg1 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT>


<s> for ( unsigned I = <NUM_LIT> , N = MI . getNumOperands ( ) ; I != N ; I += <NUM_LIT> ) { unsigned SrcReg = MI . getOperand ( I ) . getReg ( ) ; unsigned SrcSubReg = MI . getOperand ( I ) . getSubReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; assert ( TRI -> isSGPRClass ( SrcRC ) && <STR_LIT> ) ; SrcRC = TRI -> getSubRegClass ( SrcRC , SrcSubReg ) ; const TargetRegisterClass * NewSrcRC = TRI -> getEquivalentVGPRClass ( SrcRC ) ; unsigned TmpReg = MRI . createVirtualRegister ( NewSrcRC ) ; BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , TmpReg ) . addOperand ( MI . getOperand ( I ) ) ; MI . getOperand ( I ) . setReg ( TmpReg ) ; } CopyUse . eraseFromParent (


<s> unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg ( incr ) . addImm ( <NUM_LIT> ) ; } unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg (


<s> return ( __m256i ) __builtin_ia32_psradi256 ( ( __v8si )


<s> AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> return static_cast < <ISA_LIT>TargetStreamer * >


<s> return dyn_cast < llvm :: ConstantInt > ( val ) -> getZExtValue ( ) ; } else return -


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case E_DImode : return gen_load_pairdi ( reg1 , mem1 , reg2 , mem2 ) ; case E_DFmode : return gen_load_pairdf ( reg1 , mem1 , reg2 ,


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg


<s> std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool has<ISA_LIT>16Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool hasNo<ISA_LIT>16Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool HasMicro<ISA_LIT>Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool HasNoMicro<ISA_LIT>Attr = F . getFnAttribute ( <STR_LIT> ) . isValid ( ) ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , isLittle , * this , MaybeAlign ( Options . StackAlignmentOverride ) ) ; } return I . get (


<s> return <STR_LIT> ( getFeatureBits ( )


<s> LastMI = <NUM_LIT> ; FpMLxStalls = <NUM_LIT> ; ScoreboardHazardRecognizer :: Reset (


<s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF .


<s> if ( GP_REG_P ( regno ) ) { if ( ! GP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_regs [ regno ] && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ; } else return


<s> static __inline vec_double2 spu_shuffle ( vec_double2 a , vec_double2 b , vec_uchar16 pattern ) { return ( ( vec_double2 ) ( si_shufb ( ( qword ) ( a ) , ( qword


<s> rtx new_addr = NULL ; gcc_assert ( CONST_INT_P ( element_offset ) ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , <NUM_LIT> ) ; rtx op1 = XEXP ( addr , <NUM_LIT> ) ; if ( CONST_INT_P ( op1 ) ) { HOST_WIDE_INT offset = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) + INTVAL ( element_offset ) ; if ( offset == <NUM_LIT> ) new_addr = op0 ; else { rtx plus = gen_rtx_PLUS ( Pmode , op0 , GEN_INT ( offset ) ) ; new_addr = gen_rtx_CONST ( Pmode ,


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( ) ) ; } if ( ! GVar ) { llvm_unreachable ( <STR_LIT> ) ; } Type * Ty = cast < PointerType > ( GV -> getType ( ) ) -> getElementType ( ) ; if ( ! Ty -> isSized ( ) || isZeroLengthArray ( Ty ) ) { errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } SDValue base = getGlobalAddressWrapper ( GA , GV , DAG ) ; const TargetData * TD = TM . getTargetData


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned TargetAlign = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ( maxCallFrameSize & ( MaxAlign - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; if ( MaxAlign < TargetAlign && isInt < <NUM_LIT> > ( FrameSize ) ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( LP64 ) { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg (

<STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ;


<s> if ( ! isU6 && ! isImmU16 ( Offset ) ) { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << Offset ; llvm_report_error ( Msg . str ( ) ) ; } int Opcode = isU6 ? <STR_LIT>


<s> } RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) ] = N -> getOperand ( i ) ; RegSeqArgs [ <NUM_LIT> + ( <NUM_LIT> * i ) + <NUM_LIT> ] = CurDAG -> getTargetConstant ( TRI -> getSubRegFromChannel ( i ) , <STR_LIT> ) ; } if ( ! IsRegSeq ) break ; return CurDAG -> SelectNodeTo ( N , AMDGPU :: REG_SEQUENCE , N -> getVTList ( ) , RegSeqArgs , <NUM_LIT> * N -> getNumOperands ( ) + <NUM_LIT> ) ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; const AMDGPUSubtarget & ST = TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { break ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( AMDGPU :: SReg_128RegClassID , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( AMDGPU :: sub0_sub1 , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( AMDGPU :: sub2_sub3 , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( AMDGPU :: VSrc_64RegClassID , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( AMDGPU :: sub0 , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( AMDGPU :: sub1 , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } case <STR_LIT> : { const AMDGPUSubtarget & ST = TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) break ; SDValue Addr , Offset ; SelectADDRIndirect ( N -> getOperand ( <NUM_LIT> ) , Addr , Offset ) ; const SDValue Ops [ ] = { Addr , Offset , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , } ; return CurDAG -> getMachineNode ( AMDGPU :: <ISA_LIT>_RegisterLoad , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; } case <STR_LIT> : { const AMDGPUSubtarget & ST = TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) break ; SDValue Addr , Offset ; SelectADDRIndirect ( N -> getOperand ( <NUM_LIT> ) , Addr , Offset ) ; const SDValue Ops [ ] =


<s> while ( PrevI -> isDebugValue ( ) && PrevI != MBB . begin ( ) ) -- PrevI ; MachineInstr & PrevMI = * PrevI ; unsigned Opcode = PrevMI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI . getOperand ( PrevMI . getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; assert ( ( ( isThumb2 && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> ) && <STR_LIT> ) ; PrevMI . setDesc ( TII -> get ( NewOpc ) ) ; MO . setReg ( <STR_LIT> ) ; PrevMI . copyImplicitOps ( * MBB . getParent ( ) , * MBBI ) ; MBB . erase ( MBBI ) ; MachineFrameInfo & MFI = MBB . getParent (


<s> if ( ( MIaG != <STR_LIT> ) && ( MIbG != <STR_LIT> ) ) { if ( subInstWouldBeExtended ( MIa ) ) return false ; if ( subInstWouldBeExtended ( MIb ) && ! ExtendedB ) return false ; } if ( MIbG == <STR_LIT> ) { if ( ( MIb . getNumOperands ( ) > <NUM_LIT> ) && MIb . getOperand ( <NUM_LIT> ) . isReg ( ) && ( MIb . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; if ( ( MIb . getNumOperands ( ) > <NUM_LIT> ) && MIb . getOperand ( <NUM_LIT> ) . isReg ( ) && ( MIb . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; } if ( ( MIbG == <STR_LIT> ) || ( MIbG == <STR_LIT>


<s> Is<ISA_LIT>INTR = MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ; bool FnHasLiveInYmmOrZmm = checkFnHasLiveInYmmOrZmm ( MRI ) ; bool YmmOrZmmUsed = FnHasLiveInYmmOrZmm ; for ( auto * RC : { & <STR_LIT> , & <STR_LIT> } ) { if ( ! YmmOrZmmUsed ) { for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YmmOrZmmUsed = true ; break ; } } } } if ( ! YmmOrZmmUsed ) return false ; assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineBasicBlock & MBB : MF ) processBasicBlock ( MBB ) ; if ( FnHasLiveInYmmOrZmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock * Succ : MBB . successors (


<s> return DAG . getNode ( <STR_LIT> , SL , VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; } if ( const ConstantSDNode * Arg = dyn_cast < ConstantSDNode > ( Src ) ) { if ( Arg -> isNullValue ( ) ) return DAG . getConstant ( <NUM_LIT> , SL , VT ) ; if ( Arg -> isOne ( ) ) { Register Exec


<s> for ( unsigned i = <NUM_LIT> ; i != Multiple - <NUM_LIT> ; ++ i ) { if ( UniquedVals [ i ] . getNode ( ) == <NUM_LIT> ) continue ; LeadingZero &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isNullValue ( ) ; LeadingOnes &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isAllOnesValue ( ) ; } if ( LeadingZero ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; if ( OpVal . getNode ( ) == <NUM_LIT> ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( OpVal . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) { Value = CN -> getZExtValue ( ) ; } else if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( OpVal ) ) { assert ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; Value = FloatToBits ( CN -> getValueAPF ( ) . convertToFloat ( ) ) ; } if ( ValSizeInBytes < ByteSize ) return SDValue ( ) ; while ( ValSizeInBytes > ByteSize ) { ValSizeInBytes >>= <NUM_LIT> ; if ( ( ( Value >> ( ValSizeInBytes * <NUM_LIT> ) ) & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) != ( Value & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) ) return SDValue ( ) ; } int ShAmt = ( <NUM_LIT> - ByteSize ) * <NUM_LIT> ; int MaskVal = ( ( int ) Value <<


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue PSHUFB = lowerVectorShuffleWithPSHUFB ( DL , <STR_LIT> , Mask

, V1 , V2 , Subtarget , DAG ) ) return PSHUFB ;


<s> void PadShortFunc :: addPadding ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator & MBBI , unsigned int NOOPsToAdd ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; while ( NOOPsToAdd -- > <NUM_LIT> ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * MBB , MBBI , DL , TII ->


<s> return ( uint32x4_t ) __builtin_neon_vcagtv4sf ( __a ,


<s> cum -> nbytes = ( cum -> nbytes + align - <NUM_LIT> ) & ~ ( align - <NUM_LIT> ) ; if ( cum -> nbytes > <NUM_LIT> * UNITS_PER_WORD ) return <NUM_LIT> ; if ( cum -> nbytes + size <= <NUM_LIT> * UNITS_PER_WORD ) return <NUM_LIT> ; if ( type == NULL_TREE && cum -> nbytes + size > <NUM_LIT> * UNITS_PER_WORD ) return <NUM_LIT> ; return <NUM_LIT> * UNITS_PER_WORD - cum


<s> MBBI != MBBE ; ++ MBBI ) { MBB = & * MBBI ; for ( MachineBasicBlock :: iterator mi = MBB -> begin ( ) , me = MBB -> end ( ) ; mi != me ; ) { MachineBasicBlock :: iterator nmi = std :: next ( mi ) ; MachineInstr * MI = & * mi ; auto opc = MI -> getOpcode ( ) ; if ( opc == TargetOpcode :: COPY ) { MachineOperand des = MI -> getOperand ( <NUM_LIT> ) ; if ( des . isReg ( ) ) { Register destreg = des . getReg ( ) ; TCopyKind CopyKind = TCopyKind ( none ) ; if ( ! destreg . isPhysical ( ) ) { const TargetRegisterClass * RC ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; RC = MRI . getRegClass ( destreg ) ; } } } mi = nmi


<s> SDValue <ISA_LIT>SETargetLowering :: lowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { if ( ! Subtarget . has<ISA_LIT>32r6 ( ) ) return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ; EVT ResTy = Op -> getValueType ( <NUM_LIT>


<s> if ( Opt . getNumOccurrences ( ) ) return Opt ; if ( TM -> getOptLevel ( )


<s> return addOperand ( Inst , DAsm -> decodeSrcOp ( <ISA_LIT>Disassembler :: OPW512 , Imm


<s> tree ftype , decl ; ix86_init_builtin_types ( ) ; ix86_init_platform_type_builtins ( ) ; def_builtin_const ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , FLOAT128_FTYPE_VOID , IX86_BUILTIN_INFQ ) ; def_builtin_const ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , FLOAT128_FTYPE_VOID , IX86_BUILTIN_HUGE_VALQ ) ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_CONST_STRING ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_NANQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_NANQ ] = decl ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_NANSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_NANSQ ] = decl ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_FLOAT128 ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_FABSQ , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ; TREE_READONLY ( decl ) = <NUM_LIT> ; ix86_builtins [ ( int ) IX86_BUILTIN_FABSQ ] = decl ; ftype = ix86_get_builtin_func_type ( FLOAT128_FTYPE_FLOAT128_FLOAT128 ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IX86_BUILTIN_COPYSIGNQ , BUILT_IN_MD , <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printIfSet ( const MCInst * MI , unsigned OpNo , raw_ostream & O , char Asm ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; assert ( Op . isImm


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL ,

FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> bool hasSameSEW ( const VSETVLIInfo & Other ) const { assert ( isValid ( ) && Other . isValid ( ) && <STR_LIT> ) ; assert ( ! isUnknown ( ) && ! Other


<s> CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) ) CanAcceptPredicationCode = Mnemonic != <STR_LIT> ; else CanAcceptPredicationCode = Mnemonic != <STR_LIT>


<s> case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } if ( isSelectOp ) BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy1MBB ) ; else BuildMI ( BB , DL , TII . get ( NewCC ) ) . addReg ( LHS ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMBB ( Copy1MBB ) ; BB = Copy0MBB ; BB -> addSuccessor ( Copy1MBB ) ; BB = Copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT>


<s> break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; unsigned Alignment = DAG . getEVTAlignment ( Tmp . getValueType ( ) ) ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; Alignment = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Alignment ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , Alignment ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr = FIPtr ; RLI . MPI = MPI ; RLI . Alignment


<s> return false ; case USE : * total = <NUM_LIT> ; break ; case CONST_INT : if ( outer_code == SET ) { if ( satisfies_constraint_Is05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else if ( satisfies_constraint_Is20 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else * total = COSTS_N_INSNS


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains ( DestReg ,


<s> return ( int16x4_t ) __builtin_aarch64_subhnv4si ( __a ,


<s> const char * <ISA_LIT>Relocator :: getName ( Relocator :: Type pType ) const { assert ( ApplyFunctions . find ( pType ) != ApplyFunctions .


<s> if ( InsPt != MBB . end ( ) && ( InsPt -> getOpcode ( ) == <STR_LIT> || InsPt -> getOpcode ( ) == <STR_LIT> || InsPt -> getOpcode ( ) == <STR_LIT> ) && InsPt -> definesRegister ( Src ) ) { InsPt ++ ; return BuildMI ( MBB , InsPt , InsPt -> getDebugLoc ( ) , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , Dst ) . addReg ( Src ,

<NUM_LIT> , SrcSubReg ) . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> return std :: numeric_limits < unsigned > :: max (


<s> const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) && ( ! STI -> isSwift ( ) || isNotVFP || Count != <NUM_LIT> || ! ( PRegNum & <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { BaseKill = Loc -> killsRegister ( Base ) ; MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch ,


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs ) != ValNo ; Align OrigAlign = ArgFlags . getNonZeroOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == Align ( <NUM_LIT> ) ) ; bool isVectorFloat = <ISA_LIT>State -> WasOriginalArgVectorFloat ( ValNo ) ; if ( ValVT == <STR_LIT> && isVectorFloat ) { if ( ArgFlags . isSplit ( ) ) { Reg = State . AllocateReg ( FloatVectorIntRegs ) ; if ( Reg == <STR_LIT> ) State . AllocateReg ( <STR_LIT> ) ; else if ( Reg == <NUM_LIT> ) State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( IntRegs ) ; } } else if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs ) ; State . AllocateReg ( IntRegs ) ; } else { Reg = State . AllocateReg ( F64Regs ) ; unsigned Reg2 = State . AllocateReg ( IntRegs ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( ! Reg ) { unsigned Offset = State . AllocateStack ( ValVT . getStoreSize ( ) , OrigAlign ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; } else State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( <ISA_LIT>CreateInstSelector ( * this ) ) ; return


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MIB -> setDebugLoc ( DL ) ; MIB -> setDesc ( TII .


<s> return log2LdstWidth ( Opcode ) == <NUM_LIT> ? isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) : isShiftedUInt <


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool IsSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I64 : RTLIB :: UDIVREM_I64 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value :


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; int Opcode = - <NUM_LIT> ; if ( RI . isSGPRClass ( RC ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S32_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S64_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S128_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S256_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S512_SAVE ; break ; } } else if ( shouldTryToSpillVGPRs ( MF ) && RI . hasVGPRs ( RC ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V32_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V64_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V96_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V128_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V256_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V512_SAVE ; break ; } } if ( Opcode != -


<s> void addAM2OffsetImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE ->


<s> ( void ) TT ; return new <ISA_LIT>DCTranslator ( Ctx , DL , OptLevel ,


<s> AmountAboveFunclet += <NUM_LIT> ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; unsigned StackSlotsUsedByFunclet = <NUM_LIT> ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { StackSlotsUsedByFunclet = Last - <STR_LIT> ; AmountAboveFunclet += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { AmountAboveFunclet += <NUM_LIT> ; SavedBlink = true ; } if ( unsigned MoveAmount = StackSize - AmountAboveFunclet ) { unsigned Opc = <STR_LIT> ; if ( isUInt < <NUM_LIT> > ( MoveAmount ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( MoveAmount ) ) Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - AmountAboveFunclet ) ; } if ( StackSlotsUsedByFunclet ) { BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( load_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; unsigned Opc = <STR_LIT> ; if ( isUInt < <NUM_LIT> > ( <NUM_LIT> *

StackSlotsUsedByFunclet ) ) Opc = <STR_LIT> ;


<s> bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI ,


<s> unsigned CountD = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned CountS = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned InVal = <NUM_LIT> + CountS ; ShuffleMask [ CountD ] = InVal ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] =


<s> int32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ,


<s> MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI . getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI . getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . add ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . add ( MI . getOperand ( NOp ++ ) ) ; MI . setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI . getNumOperands ( ) ) MI . removeOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI . addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ; MRI . clearKillFlags ( PredReg


<s> bool enableEarlyIfConversion ( ) const override { return true


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Index = AM . IndexReg ; if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } Disp = getI8Imm ( AM . Disp ,


<s> virtual unsigned int execute ( function *


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return true ; } llvm_unreachable ( <STR_LIT>


<s> return ( __m512i ) __builtin_ia32_punpcklbw512_mask ( ( __v64qi ) __A , ( __v64qi ) __B , ( __v64qi ) _mm512_setzero_qi ( ) ,


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> )


<s> MDNode * Operand = N -> getOperand ( i ) ; MDNode * NewOperand = remapMDNode ( M , Operand ) ; OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return ; } N -> dropAllReferences ( ) ; for ( SmallVectorImpl < MDNode * > :: iterator I = NewOperands . begin


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && ( Imm == <NUM_LIT> ) &&

VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> const Item * item ( ) const { return reinterpret_cast < const Item * > ( Ref . data ( )


<s> setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setTruncStoreAction ( VT , <STR_LIT> , Expand ) ; } MVT PtrVT = <STR_LIT> ( TM . getPointerSizeInBits ( <NUM_LIT> ) ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT IntVT : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; setOperationAction ( <STR_LIT> , IntVT , Legal ) ; LegalizeAction Act = ( IntVT == <STR_LIT> ) ? Promote : Legal ; setOperationAction ( <STR_LIT> , IntVT , Act ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


) _mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> float32_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT>


<s> bool flushCacheLineSWAP ( ) const { return


<s> case <STR_LIT> : O << <STR_LIT> ; return true ; } } O << <STR_LIT> ; printMemOperand ( MI , <NUM_LIT> , O ) ; return true ; case <STR_LIT> : O << <STR_LIT> ; printMemOperand ( MI , <NUM_LIT> , O ) ; return true ; } } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isV9 ( ) || ( MI -> getNumOperands ( ) != <NUM_LIT> ) || ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) ) return false ; switch ( MI -> getOpcode


<s> static uint8_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ unreachable ( <STR_LIT> ) ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_XMM128 : \ case TYPE_XMM64 : \ case TYPE_XMM32 : \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_MM64 : \ case TYPE_MM32 : \ case TYPE_MM : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _MM0 + index ; \ case TYPE_SEGMENTREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + index ; \ case TYPE_DEBUGREG : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _DR0 + index ; \ case TYPE_CR32 : \ if ( index > <NUM_LIT> ) \ *

valid = <NUM_LIT> ; \ return prefix ## _ECR0 + index ; \ case TYPE_CR64 : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _RCR0 + index ; \ } \ }


<s> static DecodeStatus DecodeCRBITRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeRegisterClass ( Inst , RegNo ,


<s> unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = <STR_LIT> . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = <NUM_LIT> ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = <STR_LIT> . getRegister ( ( <NUM_LIT> * Index ) + Chan ) ; Reserved . set (


<s> MCSection * SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM


<s> bool UseMovt = STI . useMovt ( MF ) ; unsigned Size = TM . getPointerSize ( <NUM_LIT> ) ; unsigned Alignment = <NUM_LIT> ; auto addOpsForConstantPoolLoad = [ & MF , Alignment , Size ] ( MachineInstrBuilder & MIB , const GlobalValue * GV , bool IsSBREL ) { assert ( MIB -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; auto ConstPool = MF . getConstantPool ( ) ; auto CPIndex = IsSBREL ? ConstPool -> getConstantPoolIndex ( <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) , Alignment ) : ConstPool -> getConstantPoolIndex ( GV , Alignment ) ; MIB . addConstantPoolIndex ( CPIndex , <NUM_LIT> , <NUM_LIT> ) . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , Size , Alignment ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( Indirect ? <STR_LIT> : <STR_LIT> ) : ( Indirect ? <STR_LIT> : <STR_LIT> ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags (


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , unsigned


<s> MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , <NUM_LIT>


<s> if ( GET_CODE ( pat ) == SET && REG_P ( XEXP ( pat , <NUM_LIT> ) ) && REGNO ( XEXP ( pat , <NUM_LIT> ) ) == REGNO ( m_ccreg ) && CONST_INT_P ( XEXP ( pat , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( pat , <NUM_LIT> ) ) == <NUM_LIT> || INTVAL ( XEXP ( pat , <NUM_LIT> )

) == STORE_FLAG_VALUE ) ) return XEXP ( pat , <NUM_LIT> ) ;


<s> return new <ISA_LIT>TargetStreamer ( S


<s> bool <ISA_LIT>MCInstrInfo :: isDuplex ( MCInstrInfo const & MCII , MCInst const &


<s> bool WasOriginalRetVectorFloat ( unsigned


<s> OW -> WriteZeros ( Count ) ; return true


<s> bool empty ( ) const { return Edges . empty (


<s> if ( TARGET_OLDABI ) return ( TYPE_MODE ( type ) == BLKmode ) ; else return ( ( int_size_in_bytes ( type ) > ( <NUM_LIT> * UNITS_PER_WORD ) ) ||

( int_size_in_bytes ( type ) == - <NUM_LIT> ) ) ;


<s> MachineOperand & MO = Iter -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { if ( MO . isUse ( ) ) return false ; SeenDef = true ; } } if ( SeenDef ) return true ; ++ Iter ; if ( Iter == MBB . end ( ) ) return true ; } Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == MBB . begin ( ) ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; bool SawKill = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter -> getOperand ( j ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { if ( MO . isDef ( ) ) return


<s> return Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ,


<s> int i = <NUM_LIT> ; if ( ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) || ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) ) { O << * CurrentFnSym << <STR_LIT> << paramIndex ; return ; } for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , i ++ ) { if ( i == paramIndex )


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddr ( SDValue Addr , SDValue & Base ,


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ) return ; MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase ( MBBI


<s> if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } } else if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } } return true


<s> if ( LinkerConfig :: Object != config ( ) . codeGenType ( ) ) { ELFFileFormat * file_format = getOutputFormat ( ) ; LDSection & got = file_format -> getGOT ( ) ; m_pGOT = new <ISA_LIT>_64GOT ( got ) ; LDSection & gotplt = file_format -> getGOTPLT ( ) ; m_pGOTPLT = new <ISA_LIT>_64GOTPLT ( gotplt ) ; LDSection & plt = file_format -> getPLT ( ) ; plt . setAlign ( <NUM_LIT> ) ; m_pPLT = new <ISA_LIT>_64PLT ( plt , * m_pGOTPLT , config ( ) ) ; LDSection & relplt = file_format


<s> static bool callWaitsOnFunctionReturn ( const


<s> case TargetOpcode :: G_GLOBAL_VALUE : { const GlobalValue & GV = * MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV . isThreadLocal ( ) && Subtarget -> isTargetMachO ( ) ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : return true


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { return LowerOperationWrapper ( N , Results


<s> __builtin_ia32_pmovqd256mem_mask ( ( __v4si * ) __P , ( __v4di )


<s> llvm_report_error ( Msg . str ( ) ) ; } int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , dl , TII . get ( Opcode ) , DstReg )


<s> const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || startswith ( section , <STR_LIT> ) || startswith ( section , <STR_LIT> ) || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || startswith ( section , <STR_LIT> ) || startswith ( section , <STR_LIT> ) || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || startswith ( section , <STR_LIT> ) || startswith ( section , <STR_LIT> ) ) return true ; } else return PLACE_IN_SDATA_P ( exp ) ; return false


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS ,


<s> <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { int offset = <NUM_LIT> ; for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; Register VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; CFRegNode . push_back ( Val . getValue ( Val -> getNumValues ( ) - <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) ) ; MemOps . push_back ( Store ) ; } } else { XFI -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , LRSaveSize + CCInfo . getNextStackOffset ( ) , true ) ) ; } } if ( ! CFRegNode . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CFRegNode ) ; for ( SmallVectorImpl < ArgDataPair > :: const_iterator ArgDI = ArgData . begin ( ) , ArgDE = ArgData . end ( ) ; ArgDI != ArgDE ; ++ ArgDI ) { if ( ArgDI -> Flags . isByVal ( ) && ArgDI -> Flags . getByValSize ( ) ) { unsigned Size = ArgDI -> Flags . getByValSize ( ) ; Align Alignment = std :: max ( Align ( StackSlotSize ) , ArgDI -> Flags . getNonZeroByValAlign ( ) ) ; int FI = MFI . CreateStackObject ( Size , Alignment ,


<s> return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info


<s> getBranchTargetOpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr ,


<s> if ( targetm . sched . init_dfa_post_cycle_insn ) targetm . sched . init_dfa_post_cycle_insn ( ) ; state -> issue_rate = mips_issue_rate ( ) ; state -> dfa_state = dfa_state ; mips_sim_reset (


<s> if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return (

regno & <NUM_LIT> ) == <NUM_LIT> && GPR_P ( regno ) ;


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( isZeroShuffle ( SVOp ) ) return getZeroVector ( VT , Subtarget -> hasXMMInt ( ) , DAG , dl ) ; if ( SVOp -> isSplat ( ) ) { unsigned NumElem = VT . getVectorNumElements ( ) ; int Size = VT . getSizeInBits ( ) ; if ( NumElem <= <NUM_LIT> && CanXFormVExtractWithShuffleIntoLoad ( Op , DAG , TLI ) ) return Op ; if ( Subtarget -> hasAVX ( ) && isVectorBroadcast ( V1 ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( ( Size == <NUM_LIT> && NumElem <= <NUM_LIT> ) || ( Size == <NUM_LIT> && NumElem < <NUM_LIT> ) ) return SDValue ( ) ; return PromoteSplat ( SVOp , DAG ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> } case <STR_LIT> : { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ImmVal = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( DstReg ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( SOImmValV1 ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } { MCInst TmpInst ; TmpInst . setOpcode


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( getThe<ISA_LIT>Target (


<s> max = MAX_ARGS_IN_REGISTERS ; words = ( ( ( mode != BLKmode ) ? ( int ) GET_MODE_SIZE ( mode ) :

int_size_in_bytes ( type ) ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) ) return false ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) return false ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) return false ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) return false ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto * CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) return false ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CombinedOffset , CP -> getTargetFlags ( ) ) ; } else { return


<s> if ( MI . getOperand ( OpndIdx ) . isImm ( ) && ! isShiftedInt < Width , Scale > ( MI . getOperand ( OpndIdx ) . getImm ( ) ) ) { ErrInfo = <STR_LIT>


<s> skipInterleaving = true ; break ; } } if ( skipInterleaving ) continue ; std :: list < MachineInstr * > InstrsM ; std :: list < MachineInstr * > InstrsS1 ; std :: list < MachineInstr * > InstrsS2 ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> isTerminator ( ) ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I ) ; } } I ++ ; } emitInstrs_5Interleaving ( MBB , I , InstrsM , InstrsS1 , InstrsS2 ) ; break ; } else if ( std :: next ( I ) == E ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) ) { int distinguishResult = distinguishInstr ( I ) ; if ( distinguishResult == - <NUM_LIT> ) { errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> << I -> getParent ( ) -> getName ( ) << <STR_LIT> << * I << <STR_LIT> ; exit ( <NUM_LIT> ) ; } else { if ( distinguishResult == <NUM_LIT> ) { InstrsM . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS1 . push_back ( I ) ; } else if ( distinguishResult == <NUM_LIT> ) { InstrsS2 . push_back ( I


<s> const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( int & I : EhDataRegFI ) { const TargetRegisterClass & RC = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( )


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TargetCC ; SDValue Flags = EmitCmp ( LHS , RHS , TargetCC , CC , DL , DAG ) ; EVT VT = Op . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT>

, DL , VT ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , TargetCC , Flags ) ;


<s> if ( getMemBaseReg ( ) ) Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ; else Inst . addOperand ( MCOperand :: createReg ( getMemDefaultBaseReg ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( getMemIndexReg ( ) ) ) ; addExpr ( Inst , getMemDisp (


<s> int NewNumElts = NumElements / <NUM_LIT> ; MVT NewVT = <STR_LIT> ( NewEltVT , NewNumElts ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( find ( WidenedMask , SM_SentinelZero ) != WidenedMask . end ( ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] = i + NewNumElts ; UsedZeroVector = true ; } if ( UsedZeroVector ) V2 = getZeroVector ( NewVT , Subtarget , DAG , DL ) ; } V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } if ( canonicalizeShuffleMaskWithCommute ( Mask ) ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( SDValue V = lowerVectorShuffleWithVPMOV ( DL , Mask , VT , V1 , V2 , DAG , Subtarget ) ) return V ; if ( VT . is128BitVector ( ) ) return lower128BitVectorShuffle ( DL , Mask , VT , V1 , V2 , Zeroable , Subtarget , DAG ) ; if ( VT . is256BitVector ( ) ) return lower256BitVectorShuffle ( DL , Mask


<s> void <ISA_LIT>AsmParser :: cvtVOP3 ( MCInst & Inst , const OperandVector & Operands ) { ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; unsigned i = <NUM_LIT> ; std :: map < enum <ISA_LIT>Operand :: ImmTy , unsigned > OptionalIdx ; if ( operandsHaveModifiers ( Operands ) ) { for ( unsigned e = Operands . size ( ) ; i != e ; ++ i ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ i ] ) ; if ( Op . isRegWithInputMods ( ) ) { ( ( <ISA_LIT>Operand & ) * Operands [ i ] ) . addRegWithInputModsOperands ( Inst , <NUM_LIT> ) ; continue ; } OptionalIdx [ Op . getImmTy ( ) ] = i ; } unsigned ClampIdx = OptionalIdx [ <ISA_LIT>Operand :: ImmTyClamp ] ; unsigned OModIdx = OptionalIdx [ <ISA_LIT>Operand :: ImmTyOMod ] ; ( ( <ISA_LIT>Operand & ) * Operands [ ClampIdx ] ) . addImmOperands ( Inst ,


<s> if ( BaseType == <STR_LIT> ) MO . push_back ( MachineOperand :: CreateReg ( Base . Reg , false , false , false , false , false , false , <NUM_LIT> , false ) ) ; else { assert ( BaseType == <STR_LIT> ) ; MO . push_back ( MachineOperand :: CreateFI ( Base . FrameIndex ) ) ; } MO . push_back ( MachineOperand :: CreateImm ( Scale ) ) ; MO . push_back ( MachineOperand :: CreateReg ( IndexReg , false , false , false , false , false , false , <NUM_LIT> , false ) ) ; if ( GV ) MO . push_back ( MachineOperand :: CreateGA ( GV , Disp , GVOpFlags ) ) ; else MO . push_back ( MachineOperand :: CreateImm ( Disp ) ) ; MO . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false , false , false ,


<s> static bool resolveTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , const SelectionDAG & DAG ) { if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , Mask , Inputs , DAG ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs ,


<s> bool requiresRegisterScavenging ( const MachineFunction & MF


<s> inline vector signed char vec_vmaxsb ( vector signed char


<s> for ( auto * User : I . users ( ) ) ProcessUser ( MemOpOffsetMap ,


<s> MachineInstr * ReplaceTLSBaseAddrCall ( MachineInstr * I , unsigned TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const bool is64Bit = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case <ISA_LIT>_64_RELOC_SUBTRACTOR : { Rel . moveNext ( ) ; any_relocation_info RENext = Obj -> getRelocation ( Rel . getRawDataRefImpl ( ) ) ; unsigned RType = Obj -> getAnyRelocationType ( RENext ) ; if ( RType != <ISA_LIT>_64_RELOC_UNSIGNED ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const MCExpr * LHS = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; symbol_iterator RSymI = Rel . getSymbol ( ) ; uint64_t RSymAddr ; RSymI -> getAddress ( RSymAddr ) ; StringRef RSymName ; RSymI -> getName ( RSymName ) ; MCSymbol * RSym = Ctx . GetOrCreateSymbol ( RSymName ) ; if ( ! RSym -> isVariable ( ) ) RSym -> setVariableValue ( MCConstantExpr :: Create ( RSymAddr , Ctx ) ) ; const MCExpr * RHS = MCSymbolRefExpr :: Create ( RSym , Ctx ) ; Expr = MCBinaryExpr :: CreateSub (


<s> if ( isTargetDarwin ( ) ) return <STR_LIT> ; return


<s> if ( ! TARGET_64BIT ) { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; if ( ASSEMBLER_DIALECT == <NUM_LIT> ) fputs ( <STR_LIT> , f ) ; else fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; if ( TARGET_PA_20 ) { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f


<s> static bool createShuffleMaskFromVSELECT ( SmallVectorImpl < int > & Mask , SDValue Cond ) { if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return false ; unsigned Size = Cond . getValueType ( ) . getVectorNumElements ( ) ; Mask . resize ( Size , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != ( int ) Size ; ++ i ) { SDValue CondElt = Cond . getOperand (


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O


<s> bool FoundBump = false ; instr_iterator CmpIt = CmpI , NextIt = llvm :: next ( CmpIt ) ; for ( instr_iterator I = NextIt , E = BB -> instr_end ( ) ; I != E ; ++ I ) { MachineInstr * In = & * I ; for ( unsigned i = <NUM_LIT> , n = In -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = In -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUse ( ) ) { if ( MO . getReg ( ) == PredR ) return false ; } } if ( In == BumpI ) { instr_iterator After = BumpI ; instr_iterator From =


<s> uint32_t UnmaskedReg = RegSave & <NUM_LIT> & ( ~ Mask ) ; if ( UnmaskedReg == <NUM_LIT> ) { EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= <NUM_LIT> ; } else if ( UnmaskedReg == ( <NUM_LIT> << <NUM_LIT> ) ) { EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= <NUM_LIT> ; } } if ( ( RegSave & <NUM_LIT> ) != <NUM_LIT> ) EmitInt16 ( <STR_LIT> :: UNWIND_OPCODE_POP_REG_MASK_R4 |


<s> LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV = V1 ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } } return DAG . getNode ( <STR_LIT> , DL , VT , LowV , HighV , getV4<ISA_LIT>ShuffleImm8ForMask ( NewMask


<s> rtx base , offset ; split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ; return op


<s> void <ISA_LIT>TargetELFStreamer :: finishAttributeSection ( ) { if ( FPU != <STR_LIT> ) emitFPUDefaultAttributes ( ) ; if ( Arch != <STR_LIT> ) emitArchDefaultAttributes ( ) ; if ( Contents . empty ( ) ) return ; std :: sort ( Contents . begin ( ) , Contents . end ( ) , AttributeItem :: LessTag ) ; <ISA_LIT>ELFStreamer & Streamer = getStreamer ( ) ; if ( AttributeSection ) { Streamer . SwitchSection ( AttributeSection ) ; } else { AttributeSection = Streamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ; Streamer . SwitchSection ( AttributeSection ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItem item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag ) ; switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeItem :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue ) ; break ; case AttributeItem :: TextAttribute : Streamer . EmitBytes ( item . StringValue . upper ( ) ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; break ; case AttributeItem :: NumericAndTextAttributes : Streamer . EmitULEB128IntValue ( item . IntValue ) ; Streamer . EmitBytes ( item . StringValue . upper ( )


<s> bool Changed = false ; for ( auto * F : Functions ) { for ( auto & BB : * F ) { SmallSetVector < IntrinsicInst * , <NUM_LIT> > SVAllPTrues ; SmallSetVector < IntrinsicInst * , <NUM_LIT> > SVPow2PTrues ; for ( Instruction & I : BB ) { if ( I . use_empty ( ) ) continue ; auto * IntrI = dyn_cast < IntrinsicInst > ( &


<s> store_reg ( i , offset , HARD_FRAME_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } gr_saved ++ ; } else { offset = local_fsize - actual_fsize ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i , regno ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , regno , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( regno , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_or_fixed_reg_p ( i ) ) { if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , i , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } if ( merge_sp_adjust_with_store ) set_reg_plus_d ( STACK_POINTER_REGNUM , STACK_POINTER_REGNUM , actual_fsize , <NUM_LIT> ) ; } if ( flag_pic && actual_fsize != <NUM_LIT> && ! TARGET_64BIT ) { rtx addr = gen_rtx_PLUS ( word_mode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( word_mode , addr ) , pic_offset_table_rtx ) ; } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { rtx base ; if ( frame_pointer_needed ) { set_reg_plus_d ( <NUM_LIT> , HARD_FRAME_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = hard_frame_pointer_rtx ; } else { set_reg_plus_d ( <NUM_LIT> , STACK_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = stack_pointer_rtx ; } for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) { if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { rtx addr , reg ; rtx_insn * insn ; addr = gen_rtx_MEM ( DFmode , gen_rtx_POST_INC ( word_mode , tmpreg ) ) ; reg = gen_rtx_REG ( DFmode , i ) ; insn = emit_move_insn ( addr , reg ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( TARGET_64BIT ) { rtx mem = gen_rtx_MEM ( DFmode , plus_constant ( Pmode , base , offset ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } else { rtx meml = gen_rtx_MEM ( SFmode , plus_constant ( Pmode , base , offset


( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HRI = * HST . getRegisterInfo ( ) ; const unsigned int ALLOCFRAME_MAX = <NUM_LIT> ; auto * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getStack ( MF , <NUM_LIT> ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; DebugLoc dl = MBB . findDebugLoc ( InsertPt ) ; unsigned SP = HRI . getStackRegister


<s> SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ; DEBUG ( { dbgs ( ) << LLVM_FUNCTION_NAME << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( ) << <STR_LIT> ; } ) ; SDValue AC = DAG . getConstant ( A , dl ,


<s> rtx_insn * insn ; insn = mips_epilogue_emit_cfa_restores ( ) ; if ( reg != mips_epilogue . cfa_reg || offset != mips_epilogue . cfa_offset ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , plus_constant ( Pmode , reg , offset ) , REG_NOTES ( insn ) ) ; mips_epilogue . cfa_reg =


<s> rs6000_output_symbol_ref ( FILE , SYM ) { char * buffer = ( char * ) alloca ( strlen ( NAME ) + <NUM_LIT> ) ; \ char * p ; \ int dollar_inside = <NUM_LIT> ; \ strcpy ( buffer , NAME ) ; \ p = strchr ( buffer , '$' ) ; \ while ( p ) { \ * p = '_' ; \ dollar_inside ++ ; \ p =

strchr ( p + <NUM_LIT> , '$' ) ; \ } \ if ( dollar_inside ) { \ fputs ( <STR_LIT> , FILE ) ; \ RS6000_OUTPUT_BASENAME ( FILE , buffer ) ; \ putc ( '\n' , FILE ) ; \ fprintf ( FILE , <STR_LIT> , buffer , NAME ) ; \ } \ }


<s> unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( ) . getOperandNo ( ) ; User = * User ->


<s> case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef SymbolName = Tok . getIdentifier ( ) ; MCSymbol * Sym = getContext ( ) . lookupSymbol ( SymbolName ) ; if ( ! Sym ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement

) ) return addErrorSuffix ( <STR_LIT> ) ;


<s> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) .


<s> if ( ! MO . isReg ( ) ) OS << 'i' ; return false ; } } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ; case MachineOperand :: MO_GlobalAddress : PrintSymbolOperand ( MO , OS


<s> MachineInstr * Clone = & * std :: prev ( MachineBasicBlock :: instr_iterator ( Insert ) ) ; LIS . InsertMachineInstrInMaps ( * Clone ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; ImposeStackOrdering ( Clone ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Clone -> dump ( ) ) ; bool IsDead = MRI . use_empty ( Reg ) ; if ( ! IsDead ) { LiveInterval & LI = LIS . getInterval ( Reg ) ; ShrinkToUses ( LI , LIS ) ; IsDead = ! LI . liveAt ( LIS . getInstructionIndex ( * Def ) . getDeadSlot ( ) ) ; } if ( IsDead ) { DEBUG ( dbgs ( ) << <STR_LIT>


<s> int log2constp ( unsigned HOST_WIDE_INT c ) { c &= <NUM_LIT>


<s> static DecodeStatus DecodeGPR64spRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> )


<s> bool isReg ( ) const override { return Kind == Register


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAddrModePCOpValue ( const MCInst & MI , unsigned OpIdx ,

SmallVectorImpl < MCFixup > & Fixups ) const {


<s> return ( int32x2_t ) __builtin_aarch64_srsra_nv2si ( __a ,


<s> bool is16Bit ( ) const { return In16BitMode


<s> if ( score > max_score ) { max_score = score ; max_index = i ; } } if ( max_index != - <NUM_LIT> ) { if ( max_index != last_index ) { tmp = ready [ max_index ] ; ready [ max_index ] = ready [ last_index ] ; ready [ last_index ] = tmp ; if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ last_index ] ) ) ; } else if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ last_index ] ) ) ; } if ( verbose > <NUM_LIT> ) { fprintf ( file , <STR_LIT> , sched_state . group_state ) ; for ( i = last_index ; i >= <NUM_LIT> ; i -- ) { unsigned int sched_mask ; rtx_insn * insn = ready [ i ] ; if ( recog_memoized ( insn ) < <NUM_LIT> ) continue ; sched_mask = s390_get_sched_attrmask ( insn ) ; fprintf ( file , <STR_LIT> , INSN_UID ( insn ) , s390_sched_score (


<s> void printPCD32Mem ( const MCInst * MI , uint64_t Address ,


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , raw_ostream & O ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( O , MAI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum )


<s> bool AMDGPUDAGToDAGISel :: isGlobalLoad ( const LoadSDNode


<s> } } bool FirstVReg = true ; for ( unsigned Idx = <NUM_LIT> , IdxE = MRI -> getNumVirtRegs ( ) ; Idx != IdxE ; ++ Idx ) { unsigned VReg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; if ( FirstVReg ) { OS << ( First ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; First = false ; } OS << ( FirstVReg ? <STR_LIT> : <STR_LIT> ) << getRegTypeName ( VReg ) ; FirstVReg = false ; } if ( ! First ) OutStreamer -> EmitRawText ( OS . str ( ) ) ; AsmPrinter :: EmitFunctionBodyStart ( )


<s> void <ISA_LIT>InstPrinter :: printPostIncOperand48 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printPostIncOperand ( MI , OpNo


<s> static void rs6000_elf_unique_section ( tree


<s> return ; } if ( Info . hasAVLImm ( ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ; return ; } Register AVLReg = Info . getAVLReg ( ) ; if ( AVLReg == <STR_LIT> ) { if ( PrevInfo . isValid ( ) && ! PrevInfo . isUnknown ( ) && Info . hasSameVLMAX ( PrevInfo ) ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Info . encodeVTYPE ( ) ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return ; } BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState

:: Define | RegState :: Dead ) . addImm ( <NUM_LIT> ) . addImm ( Info . encodeVTYPE ( ) ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes (


<s> if ( <ISA_LIT>II :: isLoadInst ( MCI ) ) { idx = <NUM_LIT> ; } else if ( <ISA_LIT>II :: isSPUInst ( MCI ) ) { idx = <NUM_LIT> ; } else if ( <ISA_LIT>II :: isVPUInst ( MCI ) ) { idx =


<s> return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; switch ( form_int ) { case <NUM_LIT> : emit_insn ( gen_move_from_CR_ov_bit ( target , scratch ) ) ; return target ; case <NUM_LIT> : code = EQ ; break ; case <NUM_LIT> : code = LT ; break ; case <NUM_LIT> : code = GT ; break ; default : error ( <STR_LIT> ) ; return const0_rtx ; } tmp = gen_rtx_fmt_ee ( code , SImode , scratch


<s> assert ( MO1 . isImm ( ) && <STR_LIT> ( MO1 . getImm ( ) ) && <STR_LIT> ) ; unsigned V1 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary )


<s> static rtx gen_tls_get_addr ( void ) { if ( ! gen_tls_tga ) gen_tls_tga = init_one_libfunc ( <STR_LIT> ) ; return


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelPLT ( ) const { assert ( m_pRelPlt !=


<s> gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr


<s> FunctionPass * llvm :: createSandBoxingPreRegallocPass


<s> } if ( BigEndian ) std :: swap ( SplatValueA , SplatValueB ) ; SDValue Ops [ <NUM_LIT> ] = { SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB , SplatValueA , SplatValueB } ; SDValue Result = DAG . getBuildVector ( ViaVecTy , DL , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( )


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) ,


<s> WriteGraph ( OS , G , false , <STR_LIT> +


<s> void <ISA_LIT>LowerControlFlow :: combineMasks ( MachineInstr & MI ) { assert ( MI . getNumExplicitOperands ( ) == <NUM_LIT> ) ; SmallVector < MachineOperand , <NUM_LIT> > Ops ; unsigned OpToReplace = <NUM_LIT> ; findMaskOperands ( MI , <NUM_LIT> , Ops ) ; if ( Ops . size ( ) == <NUM_LIT> ) OpToReplace = <NUM_LIT> ; findMaskOperands ( MI , <NUM_LIT> , Ops ) ; if ( Ops . size ( ) != <NUM_LIT> ) return ; unsigned UniqueOpndIdx ; if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ; return false


<s> O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; if (


<s> else llvm_unreachable ( <STR_LIT> ) ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_TLVPPAGEOFF ; else llvm_unreachable ( <STR_LIT> ) ; } else { if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PAGEOFF ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr