<s> case <STR_LIT> : <STR_LIT> :: write < uint16_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint32_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : <STR_LIT> :: write < uint64_t > ( OS , MO . getImm ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else { encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else if ( MO . isFPImm ( ) ) { const MCOperandInfo & Info = Desc . OpInfo [ i ] ; if ( Info . OperandType == <STR_LIT> ) { float f = float ( MO . getFPImm ( ) ) ; <STR_LIT> :: write < float > ( OS , f , <STR_LIT> ) ; } else { assert ( Info . OperandType == <STR_LIT> ) ; double d = MO . getFPImm ( ) ; <STR_LIT> :: write < double > ( OS , d , <STR_LIT> ) ; } } else if ( MO . isExpr ( ) ) { const MCOperandInfo & Info = Desc . OpInfo [ i ] ; llvm :: MCFixupKind FixupKind ; size_t PaddedSize = <NUM_LIT> ; switch ( Info . OperandType ) { case <STR_LIT> : FixupKind = MCFixupKind ( <STR_LIT> ) ; break ; case <STR_LIT> : FixupKind = MCFixupKind ( <STR_LIT> ) ; PaddedSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FixupKind = MCFixupKind ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> )


<s> rtl_opt_pass * make_pass_visium_reorg ( gcc :: context * ctxt ) { return new pass_visium_reorg (


<s> bool isU1Imm ( ) const { return isImm ( <NUM_LIT> ,


<s> StringRef getPassName ( ) const override { return


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter


<s> vld4q_f32 ( const float32_t * __a ) { float32x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregxiv4sf ( __o , <NUM_LIT>


<s> static SDValue GetGlobalReg ( SelectionDAG & DAG , EVT Ty ) { <ISA_LIT>FunctionInfo * FI = DAG . getMachineFunction ( ) .


<s> MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , IfFalseMBB ) ; F -> insert ( It , SinkMBB ) ; SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( IfFalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; BuildMI ( ThisMBB , dl , TII . get ( BROpcode ) ) . addMBB ( SinkMBB ) . addImm ( CC ) ; IfFalseMBB -> addSuccessor ( SinkMBB ) ; BuildMI ( * SinkMBB , SinkMBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ; MI . eraseFromParent ( ) ; return SinkMBB


<s> if ( MBB -> begin ( ) -> getOpcode ( ) == <STR_LIT> ) { unsigned OldOffset = BBOffsets [ i ] - delta ; if ( ( OldOffset % <NUM_LIT> ) == <NUM_LIT> && ( BBOffsets [ i ] % <NUM_LIT> ) != <NUM_LIT> ) { BBSizes [ i ] += <NUM_LIT> ; delta += <NUM_LIT> ; } else if ( ( OldOffset % <NUM_LIT> ) != <NUM_LIT> && ( BBOffsets [ i ] % <NUM_LIT> ) == <NUM_LIT> ) { BBSizes [ i ] -= <NUM_LIT> ; delta -= <NUM_LIT> ; } } MachineInstr * ThumbJTMI = prior ( MBB -> end ( ) ) ; if ( ThumbJTMI -> getOpcode ( ) == <STR_LIT> ) { unsigned NewMIOffset = GetOffsetOf ( ThumbJTMI ) ; unsigned OldMIOffset = NewMIOffset - delta ; if ( ( OldMIOffset % <NUM_LIT> ) == <NUM_LIT> && ( NewMIOffset % <NUM_LIT> ) != <NUM_LIT> ) { BBSizes [ i ] -= <NUM_LIT> ; delta -= <NUM_LIT> ; } else if ( ( OldMIOffset % <NUM_LIT> ) != <NUM_LIT> && ( NewMIOffset % <NUM_LIT> ) == <NUM_LIT> ) { BBSizes [ i ] += <NUM_LIT> ; delta +=


<s> else parm_regs = x86_64_int_parameter_registers ; return gen_rtx_REG ( Pmode , parm_regs [ aggr ] ) ; } nregs = ix86_function_regparm ( type , function ) ; if ( nregs > <NUM_LIT> && ! stdarg_p ( type ) ) { int regno ; unsigned int ccvt = ix86_get_callcvt ( type ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != <NUM_LIT> ) regno = aggr ? DX_REG : CX_REG ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) { regno = CX_REG ; if ( aggr ) return gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> ) ) ; } else { regno = AX_REG ; if ( aggr


<s> Name = StringRef ( std :: string ( <STR_LIT> ) + getLexer ( ) . getTok ( ) . getString ( ) . str ( ) ) ; break ; case AsmToken :: Identifier : Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; break ; } unsigned RegNo = MatchRegisterName


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> static inline MachineOperand t1CondCodeOp ( bool isDead = false ) { return MachineOperand :: CreateReg ( <STR_LIT> , true , false


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO3 . getReg ( ) ) O << <STR_LIT> <<


<s> SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode ( <STR_LIT>


<s> const char * b = * ( const char * const * ) vb ; while ( * a && * b ) { if ( ISALPHA ( * a ) && ISDIGIT ( * b ) ) return - <NUM_LIT> ; if ( ISDIGIT ( * a ) && ISALPHA ( * b ) ) return <NUM_LIT> ; if ( * a != * b ) return * a - * b ; a ++


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_<ISA_LIT>_SaveList


<s> TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target


<s> __builtin_neon_vst1_lanev8qi ( ( __builtin_neon_qi * ) __a ,


<s> Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { loadRegPairFromStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , DestReg , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { loadRegPairFromStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , DestReg , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( )


<s> static tree spu_handle_vector_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { tree type = * node , result = NULL_TREE ; machine_mode mode ; int unsigned_p ; while ( POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE || TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; mode = TYPE_MODE ( type ) ; unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case E_DImode : result = ( unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node ) ; break ; case E_SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case E_HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case E_QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case E_SFmode : result = V4SF_type_node ; break ; case E_DFmode : result = V2DF_type_node ; break ; default : break ; } if ( result && result != type && TYPE_QUALS ( type ) ) result = build_qualified_type ( result , TYPE_QUALS ( type ) ) ; * no_add_attrs = true ; if ( ! result ) warning ( <NUM_LIT> , <STR_LIT> , name ) ; else * node = lang_hooks . types . reconstruct_complex_type ( * node , result ) ; return NULL_TREE


<s> if ( Op . getSubReg ( ) != <STR_LIT> ) return & Op ; MachineInstr * Def = MRI . getVRegDef ( Op . getReg ( ) ) ; if ( Def && Def ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerStore ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; StoreSDNode * SN = cast < StoreSDNode > ( Op . getNode ( ) ) ; const SDValue & Value = SN -> getValue ( ) ; const SDValue & Base = SN -> getBasePtr ( ) ; const SDValue & Offset = SN -> getOffset ( ) ; if ( Is<ISA_LIT>Global (


<s> if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } } else { SymToPrint = getSymbol ( GV


<s> Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod


<s> mask = spu_rlmask ( spu_splats ( ( unsigned int ) <NUM_LIT> ) , exp ) ; mask = spu_sel ( spu_splats ( ( unsigned int ) <NUM_LIT> ) , mask , spu_cmpgt ( exp , - <NUM_LIT> ) ) ; mask = spu_or ( mask , spu_xor ( ( vec_uint4 ) ( spu_rlmaska ( spu_add ( exp , - <NUM_LIT> ) ,


<s> default : return SDValue ( ) ; case <STR_LIT> : { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand (


<s> int Size = getSizeOf ( Ty ) ; if ( HST . isTypeForHVX ( Ty ) ) return Size == static_cast < int >


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) .


<s> HOST_WIDE_INT off ; rtx base ; gcc_assert ( MEM_P ( dest ) ) ; if ( GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) == REG ) { base = XEXP ( dest , <NUM_LIT> ) ; off = <NUM_LIT> ; } else { gcc_assert ( GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ; base = XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ; off = INTVAL ( XEXP ( XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ) ; } if ( base == hard_frame_pointer_rtx ) { saveop = <STR_LIT> ; off = - off ; } else { gcc_assert ( base == stack_pointer_rtx ) ; saveop = <STR_LIT> ; } src_regno = REGNO ( src ) ; switch ( src_regno ) { case BR_REG ( <NUM_LIT> ) : gcc_assert ( ! current_frame_info . r [ reg_save_b0 ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case PR_REG ( <NUM_LIT> ) : gcc_assert ( ! current_frame_info . r [ reg_save_pr ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case AR_LC_REGNUM : gcc_assert ( ! current_frame_info . r [ reg_save_ar_lc ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case AR_PFS_REGNUM : gcc_assert ( ! current_frame_info . r [ reg_save_ar_pfs ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case AR_UNAT_REGNUM : gcc_assert ( ! current_frame_info . r [ reg_save_ar_unat ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , saveop , off ) ; break ; case GR_REG ( <NUM_LIT> ) : case GR_REG ( <NUM_LIT> ) : case GR_REG ( <NUM_LIT> ) : case GR_REG (


<s> LLVMContext & Ctx = F . getContext ( ) ; Type * I8 = Type :: getInt8Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I8 , Arg . getType ( ) } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( GetArgumentSymbolName ( Arg ) , FnType ) ; Value * ArgName = CreateStringPtr ( BB , Arg . getName ( ) ) ; Value * Args [ ] = { ArgName , ConstantInt :: get (


<s> PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple :: Bitrig ) &&

T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , op0 , mode , op1 , mode , XEXP ( rem , <NUM_LIT> ) , Pmode ) ; * quot_p = quot


<s> ReadyQueue & Q = Zone . Available ; for ( SUnit * SU : Q ) { SchedCandidate TryCand ( ZonePolicy ) ; initCandidate ( TryCand , SU , Zone . isTop ( ) , RPTracker , SRI , SGPRPressure , VGPRPressure ) ; SchedBoundary * ZoneArg = Cand . AtTop == TryCand . AtTop ? & Zone : nullptr ; GenericScheduler :: tryCandidate ( Cand , TryCand , ZoneArg


<s> static int mvtc_inform_done = <NUM_LIT> ; if ( GET_CODE ( op ) == CONST_INT ) switch ( INTVAL ( op ) ) { case <NUM_LIT> : case 'c' : case 'C' : case <NUM_LIT> : case 'z' :


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( VA . isUpperBitsInLoc ( ) ) { unsigned ValSizeInBits = Ins [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; unsigned Shift = VA . getLocInfo ( ) == CCValAssign :: ZExtUpper ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( Shift , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; } switch ( VA . getLocInfo


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( nvptxSubtarget . hasROT32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( int i = <STR_LIT> ; i <= <STR_LIT> ; ++ i ) { MVT VT = ( <STR_LIT>


<s> if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } if ( <STR_LIT> ( CnstVal ) ) { CnstVal = <STR_LIT> ( CnstVal ) ; MVT MovTy = ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( <STR_LIT> , dl , MovTy , LHS , DAG . getConstant ( CnstVal , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mov ) ; } } if ( SecondTry ) goto FailedModImm ; SecondTry = true ; CnstBits = ~


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( <NUM_LIT> << Lg2 ) - <NUM_LIT> , VT ) ; SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( N0 , Zero , <STR_LIT> , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CSel , DAG .


<s> return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , true


<s> int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI . eraseFromParent


<s> ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( N1C && N1C -> getAPIntValue ( ) == <NUM_LIT>


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx ,


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx , true


<s> } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BrInstr = & * I ; continue ; } if ( analyzeCompare ( * I , SrcReg , CmpValue ) ) { if ( CmpInstr ) return nullptr ; CmpInstr = & * I ; continue ; } CmpBrOnly = false ; break ; } if ( ! TBB || ! FBB || ! CmpInstr ) return nullptr ; switch ( CC ) { case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( TBB , FBB ) ; Modified = true ; break ; case <STR_LIT> : if ( CmpValue == INT_MAX ) return nullptr ; CC = <STR_LIT> ; CmpValue += <NUM_LIT> ; Modified = true ; break ; case <STR_LIT> : if ( CmpValue == INT_MIN ) return nullptr ; CC = <STR_LIT> ; CmpValue -= <NUM_LIT> ; Modified = true ; break ; default : Modified = false ; break ; } return std :: make_unique < TargetMBBInfo > ( TargetMBBInfo { TBB , FBB , BrInstr , CmpInstr , CC , SrcReg , CmpValue


<s> unsigned postOffset ( ) const { return Offset +


<s> if ( Subtarget -> is64Bit ( ) ) return LowerReturn_64 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; return LowerReturn_32 ( Chain , CallConv , IsVarArg , Outs , OutVals ,


<s> assert ( State . PrefixPass == false ) ; MCInst PrefixInst ; PrefixInst . setOpcode ( Opc ) ; State . PrefixPass = true ; Out . EmitInstruction ( PrefixInst ) ; assert ( State . PrefixSaved == <NUM_LIT> ) ; assert ( State . PrefixPass ==


<s> <ISA_LIT>Type * <ISA_LIT>GlobalRegistry :: getOpTypeVector ( uint32_t NumElems , <ISA_LIT>Type * ElemType , MachineIRBuilder & MIRBuilder ) { auto EleOpc = ElemType -> getOpcode (


<s> BuildMI ( * MI . getParent ( ) , MI , DL , TII -> get ( <STR_LIT> ) , Mod ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; insertEmulatedTimings ( MBB , MI , Dst , Mod ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; MI . removeFromParent ( ) ; return true


<s> else if ( insn -> vexXopType == TYPE_XOP ) insn -> vvvv = vvvvFromXOP3of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) insn -> vvvv &= <NUM_LIT> ; return <NUM_LIT>


<s> case E_QImode : return V16QImode ; case E_HImode : return V8HImode ; case E_SImode : return V4SImode ; case E_DImode : return V2DImode ; case E_SFmode : return V4SFmode ; case


<s> bool <ISA_LIT>AsmParser :: cvtLdWriteBackRegAddrMode3 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ->

addAddrMode3Operands ( Inst , <NUM_LIT> ) ;


<s> DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , imm , Addr , Fail , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return


<s> void <ISA_LIT>RegisterInfo :: lowerCRRestore ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = &


<s> for ( i = <NUM_LIT> ; i < d -> nelt ; ++ i ) if ( ( d -> perm [ i ] ^ ( i * <NUM_LIT> ) ) & ( <NUM_LIT> * d -> nelt / <NUM_LIT> ) ) return false ; if ( d -> testing_p ) return true ; nelt = d -> nelt ; eltsz = GET_MODE_SIZE ( GET_MODE_INNER ( d -> vmode ) ) ; m128 = GEN_INT ( - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & ( nelt / <NUM_LIT> - <NUM_LIT> ) ; unsigned which = d -> perm [ i ] >= nelt ; unsigned xorv = ( i >= nelt / <NUM_LIT> && i < <NUM_LIT> * nelt / <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ which ] [ ( i * eltsz + j ) ^ xorv ] = GEN_INT ( e * eltsz + j ) ; rperm [ <NUM_LIT> - which ] [ ( i * eltsz + j ) ^ xorv ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d ->


<s> vector < Instruction * > listOfStore ; vector < LoadToStorIRFEV > Load2Store ; vector < Instruction * > temp ; unsigned long intrinInd = <NUM_LIT> ; vector < std :: pair < <STR_LIT> , <STR_LIT> >> intrinSics = { { <STR_LIT> , <STR_LIT> } , } ; do { for ( auto & Bb : F . getBasicBlockList ( ) ) { listOfLoad = extractIntrinFromList ( get_list_of < IntrinsicInst > ( ( & Bb ) ) , intrinSics [ intrinInd ] . first ) ; for ( auto & runer : listOfLoad ) m_load . push_back ( runer ) ; listOfStore = extractIntrinFromList ( get_list_of < IntrinsicInst > ( ( & Bb ) ) , intrinSics [ intrinInd ] . second ) ; for ( auto & runer : listOfStore ) m_store . push_back ( runer ) ; } temp = m_load . size ( ) > m_store . size ( ) ? m_store : m_load ; intrinInd ++ ; } while ( temp . size ( ) == <NUM_LIT> && intrinInd < intrinSics . size ( ) ) ; if ( m_load . size ( ) != m_store . size ( ) ) { dbgs ( ) << <STR_LIT> ; } for ( unsigned long i = <NUM_LIT> ; i < temp .


<s> unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned * , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = NULL ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case


<s> Root = SPScope :: createSPScopeTree ( MF , getAnalysis < MachineLoopInfo > (


<s> SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VTBLMask ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG .


<s> if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass (


<s> for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx


<s> case 'r' : if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y'


<s> case FK_GPRel_4 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } SDValue Funnel ; APInt APIntShiftAmt ; MVT ResultVT = Op0 . getSimpleValueType ( ) ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; Funnel = DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , ResultVT , Op0 , Op1 , DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } else { if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) ) Amt = widenSubVector ( Amt , false , Subtarget , DAG , DL , <NUM_LIT> ) ; Funnel = DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , ResultVT , Op0 , Op1 , Amt ) ; } if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) ) Funnel = extractSubVector ( Funnel , <NUM_LIT> , DAG , DL , VT . getSizeInBits ( ) ) ; return Funnel ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . shouldOptForSize ( ) ; bool ExpandFunnel = ! OptForSize && Subtarget . isSHLDSlow ( ) ; if ( ( VT == <STR_LIT> || ( ExpandFunnel && VT == <STR_LIT> ) ) && ! isa < ConstantSDNode > ( Amt ) ) { unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; SDValue Mask = DAG . getConstant ( EltSizeInBits - <NUM_LIT> , DL , Amt . getValueType ( ) ) ; SDValue HiShift = DAG . getConstant ( EltSizeInBits , DL , Amt . getValueType ( ) ) ; Op0 = DAG . getAnyExtOrTrunc ( Op0 , DL , <STR_LIT> ) ; Op1 = DAG . getZExtOrTrunc ( Op1 , DL , <STR_LIT> ) ; Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , Mask ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , HiShift ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Op1 ) ; if ( IsFSHR ) { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; } else { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , HiShift ) ; } return DAG . getZExtOrTrunc ( Res , DL , VT ) ; } if ( VT == <STR_LIT> || ExpandFunnel ) return SDValue ( ) ; if ( VT == <STR_LIT>


<s> const <ISA_LIT>TargetMachine & getTargetMachine


<s> } } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc =


<s> const char * getPassName ( ) const { return


<s> void recordReplacement ( int OFI , int


<s> if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( recog_op_alt [ opno ] [ which_alternative ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; result = true ; } else if ( GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , <NUM_LIT>

) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( op , <NUM_LIT> ) ) ) {


<s> return ( float32x4_t ) __builtin_neon_vld1v4sf ( ( const


<s> if ( UserI -> getOperand ( i ) == FoldedValue ) continue ; if ( Instruction * OtherOp = dyn_cast < Instruction > ( UserI -> getOperand ( i ) ) ) { LoadInst * OtherLoad = dyn_cast < LoadInst > ( OtherOp ) ; if ( ! OtherLoad && ( isa < TruncInst > ( OtherOp ) || isa < SExtInst > ( OtherOp ) || isa < ZExtInst > ( OtherOp ) ) ) OtherLoad = dyn_cast < LoadInst > ( OtherOp -> getOperand ( <NUM_LIT> ) ) ; if ( OtherLoad && isFoldableLoad ( OtherLoad , FoldedValue ) ) return i == <NUM_LIT> ; } } return <NUM_LIT> ; } } unsigned NumOps = ( Src -> isVectorTy ( ) ? getNumVectorRegs ( Src ) : getNumberOfParts ( Src ) ) ; if ( ( ( ! Src -> isVectorTy ( ) && NumOps == <NUM_LIT> ) || ST -> hasVectorEnhancements2 ( ) ) && I != nullptr ) { if ( Opcode == Instruction :: Load && I -> hasOneUse ( ) ) { const Instruction * LdUser = cast < Instruction > ( * I -> user_begin ( ) ) ; if ( isBswapIntrinsicCall ( LdUser ) && ( ! LdUser -> hasOneUse ( ) || ! isa <

StoreInst > ( * LdUser -> user_begin ( ) ) ) ) return <NUM_LIT> ;


<s> } else { NumBytes = StackSize - CSSize - TailCallArgReserveSize ; } uint64_t SEHStackAllocAmt = NumBytes ; MachineBasicBlock :: iterator AfterPop = MBBI ; if ( HasFP ) { if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { int Offset = <NUM_LIT> + mergeSPUpdates ( MBB , MBBI , true ) ; emitSPUpdate ( MBB , MBBI , DL , Offset , true ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; if ( <ISA_LIT>FI -> hasSwiftAsyncContext ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , MachineFramePtr ) . addUse ( MachineFramePtr ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } if ( NeedsDwarfCFI ) { unsigned DwarfStackPtr = TRI -> getDwarfRegNum ( Is64Bit ? <STR_LIT> : <STR_LIT> , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: cfiDefCfa ( nullptr , DwarfStackPtr , SlotSize ) , MachineInstr :: FrameDestroy ) ; if ( ! MBB . succ_empty ( ) && ! MBB . isReturnBlock ( ) ) { unsigned DwarfFramePtr = TRI -> getDwarfRegNum ( MachineFramePtr , true ) ; BuildCFI ( MBB , AfterPop , DL , MCCFIInstruction :: createRestore ( nullptr , DwarfFramePtr ) , MachineInstr :: FrameDestroy ) ; -- MBBI ; -- AfterPop ; } -- MBBI ; } } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI


<s> SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG )


<s> Register DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedDMask = CI . DMask | Paired . DMask ; unsigned DMaskIdx = <STR_LIT> ( CI . I -> getOpcode ( ) , <STR_LIT> :: dmask ) ; auto MIB = BuildMI ( * MBB , InsertBefore , DL , TII -> get ( Opcode ) , DestReg ) ; for ( unsigned I = <NUM_LIT> , E = ( * CI . I ) . getNumOperands ( ) ; I != E ; ++ I ) { if ( I == DMaskIdx ) MIB . addImm ( MergedDMask ) ; else MIB . add ( ( * CI . I ) . getOperand ( I ) ) ; } assert ( CI . I -> hasOneMemOperand ( ) && Paired . I ->


<s> void <ISA_LIT>AsmPrinter :: printAddrMode3OffsetOperand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( MO1 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << TRI -> getAsmName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2 .


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case

( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> const char * RecipOp ; if ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) RecipOp = <STR_LIT> ; else if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) ) RecipOp = <STR_LIT> ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; UseOneConstNR = false


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> initializeBaseYamlFields ( YamlMFI , MF , PFS , Error , SourceRange ) ) return true ; if ( MFI -> Occupancy == <NUM_LIT> ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; MFI -> Occupancy = ST . computeOccupancy ( MF . getFunction ( ) , MFI -> getLDSSize ( ) ) ; } auto parseRegister = [ & ] ( const yaml :: StringValue & RegName , Register & RegVal ) { Register TempReg ; if ( parseNamedRegisterReference ( PFS , TempReg , RegName . Value , Error ) ) { SourceRange = RegName . SourceRange ; return true ; } RegVal = TempReg ; return false ; } ; auto diagnoseRegisterClass = [ & ] ( const yaml :: StringValue & RegName ) { const MemoryBuffer & Buffer = * PFS . SM -> getMemoryBuffer ( PFS . SM -> getMainFileID ( ) ) ; Error = SMDiagnostic ( * PFS . SM , SMLoc ( ) , Buffer . getBufferIdentifier ( ) , <NUM_LIT> , RegName . Value . size ( ) , SourceMgr :: DK_Error , <STR_LIT> , RegName . Value , None , None ) ; SourceRange = RegName . SourceRange ; return true ; } ; if ( parseRegister ( YamlMFI . ScratchRSrcReg , MFI -> ScratchRSrcReg ) || parseRegister ( YamlMFI . FrameOffsetReg , MFI -> FrameOffsetReg ) || parseRegister ( YamlMFI . StackPtrOffsetReg , MFI -> StackPtrOffsetReg ) ) return true ; if ( MFI -> ScratchRSrcReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> ScratchRSrcReg ) ) { return diagnoseRegisterClass ( YamlMFI . ScratchRSrcReg ) ; } if ( MFI -> FrameOffsetReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> FrameOffsetReg ) ) { return diagnoseRegisterClass ( YamlMFI . FrameOffsetReg ) ; } if ( MFI -> StackPtrOffsetReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> StackPtrOffsetReg ) ) { return diagnoseRegisterClass ( YamlMFI . StackPtrOffsetReg ) ; } auto parseAndCheckArgument = [ & ] ( const Optional < yaml :: <ISA_LIT>Argument > & A , const TargetRegisterClass & RC , ArgDescriptor & Arg , unsigned UserSGPRs , unsigned SystemSGPRs ) { if ( ! A ) return false ; if ( A -> IsRegister ) { Register Reg ; if ( parseNamedRegisterReference ( PFS , Reg , A -> RegisterName . Value , Error ) ) { SourceRange = A -> RegisterName . SourceRange ; return true ; } if ( ! RC . contains ( Reg ) ) return diagnoseRegisterClass (


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) return ParseSectionDirectiveHSAText ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirective<ISA_LIT>HsaKernel ( ) ; return


<s> bool useNEONForSinglePrecisionFP ( ) const { return hasNEON ( )


<s> static unsigned getMaxCalleeSavedReg ( const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo & TRI ) { static_assert ( <STR_LIT> > <NUM_LIT> , <STR_LIT> ) ; if ( CSI . empty ( ) ) return <NUM_LIT> ; unsigned Max = getMax32BitSubRegister ( CSI [ <NUM_LIT> ] . getReg ( ) , TRI ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( )


<s> unsigned PCLabelId = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( isThumb || isThumb2 ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolMBB :: Create ( F -> getContext ( ) , DispatchBB , PCLabelId , PCAdj ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else if ( isThumb ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister


<s> static MCTargetStreamer * createTargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , <NUM_LIT> > Ops = { Src0 , Src1 ,


<s> static rtx frv_read_argument ( tree exp , unsigned int index ) { return expand_normal ( CALL_EXPR_ARG ( exp , index


<s> bool closeParen = printVariantKind ( OS , Kind ) ; const MCExpr * Expr = getSubExpr ( ) ; Expr -> print (


<s> case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : break ; } const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; int64_t Val ; if ( ! Expr -> EvaluateAsAbsolute ( Val ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Val < <NUM_LIT> || Val >


<s> return static_cast < <ISA_LIT>DCBasicBlock & > ( DCInstruction :: getParent ( )


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned MemOpc = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MemReg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( MemOpc ) , MemReg ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( ValOps )


<s> if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = <ISA_LIT>MCExpr :: VK_SECREL_LO12 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefKind = <ISA_LIT>MCExpr :: VK_SECREL_HI12 ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , RefKind , Ctx ) ; return MCOperand :: createExpr ( Expr


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case


<s> unsigned Reg = Src . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair


<s> std :: string llvm :: getSamplerName (


<s> case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return <ISA_LIT>AS :: CONSTANT_ADDRESS ; case PseudoSourceValue


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder &


<s> if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType


<s> unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pos2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pos1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn ,


double __C , double __D , double __E , double __F , double __G , double __H ) {


<s> void MetadataStreamerV3 :: emitVersion ( ) { auto Version = HSAMetadataDoc -> getArrayNode ( ) ; Version . push_back ( Version . getDocument ( ) -> getNode ( VersionMajor ) ) ; Version . push_back ( Version . getDocument ( ) -> getNode ( VersionMinor ) ) ; getRootMetadata ( <STR_LIT> ) =


<s> SDLoc DL ( N ) ; RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( Base ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else { assert ( Index . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Index = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> ,

DL , <STR_LIT> ) , Index , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> int i ; int check_regno ; rtx elt ; rtx elt_reg ; rtx elt_mem ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { elt = XVECEXP ( op , <NUM_LIT> , i + par_index ) ; if ( GET_CODE ( elt ) != SET ) return false ; elt_reg = load_p ? SET_DEST ( elt ) : SET_SRC ( elt ) ; elt_mem = load_p ? SET_SRC ( elt ) : SET_DEST ( elt ) ; if ( GET_CODE ( elt_reg ) != REG || GET_MODE ( elt_reg ) != SImode ) return false ; if ( GET_CODE ( elt_mem ) != MEM || GET_MODE ( elt_mem


<s> Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) return false ; if ( ! State . AllocateReg ( ArgGPRs ) ) return false ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true


<s> unsigned R600MCCodeEmitter :: getHWReg ( unsigned RegNo )


<s> } } if ( ! SN -> isTruncatingStore ( ) && ! SN -> isVolatile ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT>

) , Ops , MemVT , SN -> getMemOperand ( ) ) ;


<s> DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getBitcast ( VT , ResNode ) ; } } SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleHigh128VectorInsertLow ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getUNDEF ( VT ) , V , <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleLow128VectorInsertHigh ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , <NUM_LIT> , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getUNDEF ( VT ) , V , NumElems / <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo (


<s> auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) { return nullptr


<s> MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SwapVector [ EntryIdx ] . VSEId << <STR_LIT> ) ; LLVM_DEBUG ( MI -> dump ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! isVecReg ( Reg ) && ! isScalarVecReg


<s> else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if (


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { static const unsigned Regs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; return Regs [ TFI -> hasFP ( MF ) ] [ TT . isArch64Bit (


<s> emit_insn ( gen_add3_insn ( reg , reg , size_rtx ) ) ; addr = reg ; } else if ( GET_CODE ( addr ) == PRE_MODIFY ) { rtx reg = XEXP ( addr , <NUM_LIT> ) ; rtx expr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; gcc_assert ( GET_CODE ( expr ) == PLUS ) ; emit_insn ( gen_add3_insn ( reg , XEXP ( expr , <NUM_LIT> ) , XEXP ( expr , <NUM_LIT> ) ) ) ; addr =


<s> SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result . getValue


<s> if ( Op . getValueType ( ) . isVector ( ) ) { assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned NumElements = Op . getValueType ( ) . getVectorNumElements ( ) ; assert ( NumElements != <NUM_LIT> && <STR_LIT> ) ; switch ( Load -> getAddressSpace ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( NumElements <= <NUM_LIT> ) break ; case <STR_LIT> : return SplitVectorLoad ( Op ,


<s> return __cmpdf2 ( ( double ) x1 , ( double


<s> return ( reload_completed && cfun -> static_chain_decl == <NUM_LIT> && compute_total_frame_size ( ) == <NUM_LIT> && tilepro_current_function_is_leaf ( ) && ! crtl ->

profile && ! df_regs_ever_live_p ( TILEPRO_LINK_REGNUM ) ) ;


<s> if ( getParser ( ) . checkForValidSection ( ) ) return true ; StringRef Name ; SMLoc NameLoc = getLoc ( ) ; if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; MCSymbol * Symbol = getContext ( ) . getOrCreateSymbol ( Name ) ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; unsigned LocalMemorySize = <STR_LIT> :: getLocalMemorySize ( & getSTI ( ) ) ; int64_t Size


<s> case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT>


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; MCNumFixups += <NUM_LIT> ; return <NUM_LIT>


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer & Out


<s> static enum insn_code tilegx_multiply_get_opcode ( const struct tilegx_multiply_insn_seq_entry * entry


<s> bool <ISA_LIT>TargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; return


<s> update_base_p = true ; base_reg = XEXP ( XEXP ( base_addr , <NUM_LIT> ) , <NUM_LIT> ) ; } const char * update_base = update_base_p ? <STR_LIT> : <STR_LIT> ; regno = REGNO ( operands [ <NUM_LIT> ] ) ; otherops [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; otherops [ <NUM_LIT> ] = base_reg ; if ( regno >= <NUM_LIT> ) { enable4 = nds32_regno_to_enable4 ( regno ) ; sprintf ( buff , <STR_LIT> , update_base , enable4 ) ; } else { sprintf ( buff , <STR_LIT> , update_base ) ; } output_asm_insn ( buff , otherops ) ; return <STR_LIT>


<s> MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr -> getNumOperands ( ) ; OpIdx < EndIdx ; ++ OpIdx ) { MachineOperand & MO = Instr -> getOperand ( OpIdx ) ; const TargetRegisterClass * OpRegCstraints = Instr -> getRegClassConstraint ( OpIdx , TII , TRI ) ; if ( ! OpRegCstraints ) continue ; if ( MO . isFI ( ) ) continue ; assert ( MO . isReg ( ) && <STR_LIT> ) ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) { if ( ! OpRegCstraints -> contains ( Reg ) ) return false ; } else if ( ! OpRegCstraints -> hasSubClassEq ( MRI -> getRegClass ( Reg ) ) && ! MRI -> constrainRegClass ( Reg , OpRegCstraints ) ) return false ; } return


<s> Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { APInt Diff = TrueC -> getAPIntValue ( ) - FalseC -> getAPIntValue ( ) ; assert ( Diff . getBitWidth ( ) == N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) && <STR_LIT> ) ; bool isFastMultiplier = false ; if ( Diff . ult ( <NUM_LIT> ) ) { switch ( Diff . getZExtValue ( ) ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { Cond = getSETCC ( CC , Cond , DL , DAG ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; if ( Diff != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( Diff , DL , Cond . getValueType ( ) ) ) ; if ( FalseC -> getAPIntValue ( ) != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; return Cond ; } } } } if ( ! DCI . isBeforeLegalize ( ) && ! DCI . isBeforeLegalizeOps ( ) ) { ConstantSDNode * CmpAgainst = nullptr ; if ( ( Cond . getOpcode ( ) == <STR_LIT> || Cond . getOpcode ( ) == <STR_LIT> ) && ( CmpAgainst = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) && ! isa < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) { if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( FalseOp ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( TrueOp ) ) { SDValue Ops [ ] = { FalseOp , Cond . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( CC , DL , <STR_LIT> ) , Cond } ; return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } } } if ( CC == <STR_LIT> ) { SDValue Flags ; <STR_LIT> CC0 , CC1 ; bool isAndSetCC ; if ( checkBoolTestAndOrSetCCCombine ( Cond , CC0 , CC1 , Flags ,


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; AccOp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , AccOp , Zero ) ; SDValue Rdx = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Pg , AccOp , VecOp ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; while ( true ) { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; assert ( End . getPointer ( ) <= EndPtr && <STR_LIT> ) ; if ( End . getPointer ( ) == EndPtr ) break ; } Identifier = LineBuf ; if ( ! Result ) { StringRef InternalName = SemaCallback -> LookupInlineAsmLabel ( Identifier , getSourceManager ( ) , Loc , false ) ; assert ( InternalName . size ( ) && <STR_LIT> ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Label , Loc , Identifier . size ( ) , InternalName ) ) ; } MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Identifier ) ; MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr


<s> if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; return lowerShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( V2 . isUndef ( ) && ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { SDValue VPermMask = getConstVector ( Mask , <STR_LIT> , DAG , DL , true ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , VPermMask ) ; } if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG ,


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx


<s> Msg . Loc = getLoc ( ) ; if ( isToken ( AsmToken :: Identifier ) && ( Msg . Id = getMsgId ( getTokenStr ( ) ) ) >= <NUM_LIT> ) { Msg . IsSymbolic = true ; lex ( ) ; } else if ( ! parseExpr ( Msg . Id , <STR_LIT> ) ) { return false ; } if ( trySkipToken ( AsmToken :: Comma ) ) { Op . IsDefined = true ; Op . Loc = getLoc ( ) ; if ( isToken ( AsmToken :: Identifier ) && ( Op . Id = getMsgOpId ( Msg . Id , getTokenStr ( ) )


<s> SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( <STR_LIT> , DL , VT , Add , N0 , CCVal , Cmp ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CSel . getNode ( ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , <STR_LIT> ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG .

getConstant ( <NUM_LIT> , DL , VT ) , SRA ) ;


<s> MCRegister getBPReg ( ) { return <STR_LIT>


<s> virtual const <ISA_LIT>ompactTargetLowering * getTargetLowering


<s> if ( LastLoadedElt == NumElems - <NUM_LIT> ) { if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; return DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; } else if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT>


<s> int i ; for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( ! regs_ever_live [ i ] ) return i ; } return INVALID_REGNUM


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand


<s> int OpIdx = TII -> getOperandIdx ( * OldMI , Op ) ; if ( OpIdx > -


<s> else if ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; } if ( TII -> usesLGKM_CNT ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; if ( mayAccessLDSThroughFlat ( Inst ) ) ScoreBrackets -> setPendingFlat ( ) ; } } else if ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) || ( TII -> isMIMG ( Inst ) && ! Inst . mayLoad ( ) && ! Inst . mayStore ( ) ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else if ( Inst . mayStore ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI


<s> if ( Res . getNode ( ) ) return Res ; } assert ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) ; return SDValue ( )


<s> const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned NewOpcode = TII -> getEquivalentCompactForm ( Branch ) ; Branch = TII -> genInstrWithNewOpc ( NewOpcode , Branch ) ; std :: next ( Branch ) -> eraseFromParent


<s> const SDLoc & dl ( Results . InpNode ) ; int VecLen = SM . Mask . size ( ) ; for ( int M : SM . Mask ) { if ( M != - <NUM_LIT> && M >= VecLen ) return OpRef :: fail ( ) ; } ForwardDeltaNetwork FN ( SM . Mask ) ; if ( FN . run ( FC ) ) { SDValue Ctl = getVectorConstant ( FC , dl ) ; Results . push ( <STR_LIT> , ResTy , { Va , OpRef ( Ctl ) } ) ; return OpRef :: res ( Results . top ( ) ) ; } ReverseDeltaNetwork RN ( SM . Mask ) ; if ( RN . run ( RC ) ) { SDValue Ctl = getVectorConstant ( RC , dl ) ; Results . push ( <STR_LIT> , ResTy , { Va , OpRef


<s> start_sequence ( ) ; m68k_libcall_value_in_a0_p = true ; a0 = emit_library_call_value ( m68k_get_m68k_read_tp ( ) , NULL_RTX , LCT_PURE , Pmode ) ; m68k_libcall_value_in_a0_p = false ; insns = get_insns ( ) ; end_sequence ( ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_RELOC32 ) ; gcc_assert ( can_create_pseudo_p ( ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest ,


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; unsigned DivOp = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Div = DAG . getNode ( DivOp , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , VT , Div


<s> MCSection * <ISA_LIT>ElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { if ( isExecuteOnlyFunction ( GO , SK , TM ) ) SK =


<s> virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const { const MCSectionELF & ES = static_cast <


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { Target & T = getThe<ISA_LIT>Target ( ) ; TargetRegistry :: RegisterMCAsmInfo ( T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter


<s> if ( I -> getOpcode ( ) == <STR_LIT> && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! Dest ) { MBBStartOffset += TII -> getInstSizeInBytes ( * I ) ; continue ; } int BranchSize = computeBranchSize ( Fn , & MBB , Dest , MBBStartOffset ) ; if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr & OldBranch = * I ; DebugLoc dl = OldBranch . getDebugLoc ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { <STR_LIT> Pred = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CRReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ( Pred ) ) . addReg ( CRReg ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { unsigned CRBit = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( CRBit ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { unsigned CRBit = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( CRBit ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else if ( I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , dl , TII -> get (


<s> if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) { const uint32_t * MB = PRI . getRegMaskBits ( RR . Reg ) ; for ( unsigned i = <NUM_LIT> , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; if ( ! hasCoverOf ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ) return false ; } return true ; } RegisterRef NR = PRI . normalize ( RR ) ; if ( NR . Mask . none ( ) ) return true ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) { if ( ( NR . Mask & F -> second ) ==


<s> MachineInstr & MI = * I ; int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i


<s> note = find_reg_note ( insn , REG_FRAME_RELATED_EXPR , <NUM_LIT> ) ; expr = ( note != <NUM_LIT> ? XEXP ( note , <NUM_LIT> ) : copy_rtx ( PATTERN ( insn ) ) ) ; RTX_FRAME_RELATED_P ( expr ) = <NUM_LIT> ; return


<s> linkExceptionRegistration ( Builder , Trampoline ) ; CxxLongjmpUnwind = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getVoidTy ( TheModule -> getContext ( ) ) , Int8PtrType , false ) ) ; cast < Function > ( CxxLongjmpUnwind -> stripPointerCasts ( ) ) -> setCallingConv ( CallingConv :: <ISA_LIT>_StdCall ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { RegNodeTy = getSEHRegistrationType ( ) ; RegNode = Builder . CreateAlloca ( RegNodeTy ) ; Value * SP = Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> ) , { } ) ; Builder . CreateStore ( SP , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; StateFieldIndex = <NUM_LIT> ; StringRef PersonalityName = PersonalityFn -> getName ( ) ; UseStackGuard = ( PersonalityName == <STR_LIT> ) ; ParentBaseState = UseStackGuard ? - <NUM_LIT> : - <NUM_LIT> ; insertStateNumberStore ( & * Builder . GetInsertPoint ( ) , ParentBaseState ) ; Value * LSDA = emitEHLSDA ( Builder , F ) ; Type * Int32Ty = Type :: getInt32Ty ( TheModule -> getContext ( ) ) ; LSDA = Builder . CreatePtrToInt ( LSDA , Int32Ty ) ; if ( UseStackGuard ) { Cookie = TheModule -> getOrInsertGlobal ( <STR_LIT> , Int32Ty ) ; Value * Val = Builder . CreateLoad ( Int32Ty , Cookie ) ; LSDA = Builder . CreateXor ( LSDA , Val ) ; } Builder . CreateStore ( LSDA , Builder . CreateStructGEP ( RegNodeTy , RegNode , <NUM_LIT> ) ) ; Link = Builder . CreateStructGEP ( RegNodeTy ,


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg0 , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg1 , Offset + <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( Reg , true ) + <NUM_LIT> ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg0 , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg1 , Offset + <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } else { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } if ( <ISA_LIT>FI -> callsEhReturn (


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT )


<s> rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else { rtx reg2 = gen_rtx_REG ( mode


<s> SDValue getBorrowGenerateShufMask ( SelectionDAG & DAG , DebugLoc dl ) { SmallVector < SDValue , <NUM_LIT> > ShufBytes ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> ,


<s> if ( re == rs + <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> , rs ) ; else fprintf ( asm_out_file , <STR_LIT> , rs , re - <NUM_LIT> ) ; rs = re + <NUM_LIT> ; } if ( out_state ) fputc


<s> MCInst Inst ; if ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { Out . EmitInstruction ( Inst , this ->


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) ) ; } return SDValue


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; addStringImm ( getExtInstSetName ( static_cast < ExtInstSet > ( Set ) ) , Inst


<s> BTFOffsetReloc OffsetReloc ; OffsetReloc . Label = ORSym ; OffsetReloc . OffsetNameOff = addString ( IndexPattern ) ; OffsetReloc . TypeID = RootId ; AccessOffsets [ AccessPattern . str ( ) ] = std :: stoi ( OffsetStr ) ; OffsetRelocTable [ SecNameOff ] .


<s> if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI . getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - <NUM_LIT> && DefCycle <= <NUM_LIT> ) ; } return false


<s> FnProperties adjustToCaller ( const FnProperties & CallerProps ) const { FnProperties New ( ( Features & ~ TargetFeatures ) | CallerProps . Features


<s> bool canOpTrap ( unsigned Op , EVT VT ) const override { return


<s> return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , AMDGPU :: EXEC ) . Case ( <STR_LIT> , AMDGPU :: VCC ) . Case ( <STR_LIT> , AMDGPU :: FLAT_SCR ) . Case ( <STR_LIT> , AMDGPU :: M0 ) . Case ( <STR_LIT> , AMDGPU :: SCC ) . Case ( <STR_LIT> , AMDGPU

:: FLAT_SCR_LO ) . Case ( <STR_LIT> , AMDGPU :: FLAT_SCR_HI ) . Case ( <STR_LIT> , AMDGPU :: VCC_LO ) . Case ( <STR_LIT> , AMDGPU :: VCC_HI ) . Case ( <STR_LIT> , AMDGPU :: EXEC_LO ) . Case ( <STR_LIT> , AMDGPU :: EXEC_HI ) . Default ( <NUM_LIT> ) ;


<s> case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' : return std :: make_pair ( <NUM_LIT> , static_cast <

const TargetRegisterClass * > ( <NUM_LIT> ) ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) { CondBrMBBOperand = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = A64InvertCondCode ( CC ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; } else { MachineInstrBuilder InvertedMI ; int InvertedOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; } InvertedMI = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( InvertedOpcode ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { InvertedMI . addOperand ( MI -> getOperand ( i ) ) ; if ( MI -> getOperand ( i ) . isMBB ( ) ) CondBrMBBOperand = i ; } MI -> eraseFromParent (


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { O << getRegisterName ( MO . getReg ( ) ) ; } else if ( MO . isExpr


<s> Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LogicalShift = true ; ShiftLeft = true ; break ; } assert ( ( LogicalShift || ! ShiftLeft ) && <STR_LIT> ) ; Value * Vec = II . getArgOperand ( <NUM_LIT> ) ; Value * Amt = II . getArgOperand ( <NUM_LIT> ) ; auto * VT = cast < FixedVectorType > ( II . getType ( ) ) ; Type * SVT = VT -> getElementType ( ) ; int NumElts = VT -> getNumElements ( ) ; int BitWidth = SVT -> getIntegerBitWidth ( ) ; KnownBits KnownAmt = llvm :: computeKnownBits ( Amt , II . getModule ( ) -> getDataLayout ( ) ) ; if ( KnownAmt . getMaxValue ( ) . ult ( BitWidth ) ) { return ( LogicalShift ? ( ShiftLeft ? Builder . CreateShl ( Vec , Amt ) : Builder . CreateLShr ( Vec , Amt ) ) : Builder . CreateAShr ( Vec , Amt ) ) ; } auto * CShift = dyn_cast < Constant > ( Amt ) ; if ( ! CShift ) return nullptr ; bool AnyOutOfRange = false ; SmallVector < int , <NUM_LIT> > ShiftAmts ; for ( int I = <NUM_LIT> ; I < NumElts ; ++ I ) { auto * CElt = CShift -> getAggregateElement ( I ) ; if ( isa_and_nonnull < UndefValue > ( CElt ) ) { ShiftAmts . push_back ( - <NUM_LIT> ) ; continue ; } auto * COp = dyn_cast_or_null < ConstantInt > ( CElt ) ; if ( ! COp ) return nullptr ; APInt ShiftVal = COp -> getValue ( ) ; if ( ShiftVal . uge ( BitWidth ) ) { AnyOutOfRange = LogicalShift ; ShiftAmts . push_back ( LogicalShift ? BitWidth : BitWidth - <NUM_LIT> ) ; continue ; } ShiftAmts . push_back ( ( int ) ShiftVal . getZExtValue ( ) ) ; } auto OutOfRange = [ & ] ( int Idx ) { return ( Idx < <NUM_LIT> ) || ( BitWidth <= Idx ) ; } ; if ( llvm :: all_of ( ShiftAmts , OutOfRange ) ) { SmallVector < Constant * , <NUM_LIT> > ConstantVec ; for ( int Idx : ShiftAmts ) { if ( Idx < <NUM_LIT> ) { ConstantVec . push_back ( UndefValue :: get ( SVT ) ) ; } else


<s>
switch
(
Inst
)
{
case
OpenCL_std
::
vstore_half_r
:
case
OpenCL_std
::
vstore_halfn_r
:
case
OpenCL_std
::
vstorea_halfn_r
:
{
for
(
unsigned
i
=
NumFixedOps
;
i
<
NumOps
<NUM_LIT>
;
++
i
)
{
printOperand
(
MI
,
i
,
O
)
;
O
<<
' '
;
}
printSymbolicOperand
<
OperandCategory
::
FPRoundingModeOperand
>
(
MI
,
NumOps
<NUM_LIT>
,
O
)
;
break
;
}
default
:
printRemainingVariableOps
(
MI
,
NumFixedOps
,
O
,
true
)
;
}
}
else
{
printRemainingVariableOps
(
MI
,
NumFixedOps
,
O
,


<s> static const char * getRegisterName ( unsigned RegNo ) { return <ISA_LIT>InstPrinter :: getRegisterName


<s> unsigned ShuffleSize = ShuffleVT . getVectorNumElements ( ) ; unsigned MaskRatio = ShuffleSize / NumMaskElts ; if ( Depth == <NUM_LIT> && Root . getOpcode ( ) == <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != ShuffleSize ; ++ i ) if ( Mask [ i / MaskRatio ] < <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; SDValue Zero = getZeroVector ( ShuffleVT , Subtarget , DAG , DL ) ; Res = DAG . getBitcast ( ShuffleVT , Input ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , ShuffleVT , Res , Zero , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; DCI . CombineTo ( Root . getNode ( ) , DAG . getBitcast ( RootVT , Res ) , true ) ; return true ; } } if ( Depth < <NUM_LIT> ) return false ; if ( ( Depth >= <NUM_LIT> || HasPSHUFB ) && ( ( VT . is128BitVector ( ) && Subtarget . hasSSSE3 ( ) ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( VT . is512BitVector ( ) && Subtarget . hasBWI ( ) ) ) ) { SmallVector < SDValue , <NUM_LIT> > PSHUFBMask ; int NumBytes = VT . getSizeInBits ( ) / <NUM_LIT> ; int Ratio = NumBytes / NumMaskElts ; for ( int i = <NUM_LIT> ; i < NumBytes ; ++ i ) { int M = Mask [ i / Ratio ] ; if ( M == SM_SentinelUndef ) { PSHUFBMask . push_back ( DAG . getUNDEF ( <STR_LIT> ) ) ; continue ; } if ( M == SM_SentinelZero ) { PSHUFBMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; continue ; } M = Ratio * M + i % Ratio ; if ( ( M / <NUM_LIT> ) != ( i / <NUM_LIT> ) ) return false ; PSHUFBMask . push_back ( DAG . getConstant ( M , DL , <STR_LIT> ) ) ; } MVT ByteVT = <STR_LIT> ( <STR_LIT> , NumBytes ) ; Res = DAG . getBitcast ( ByteVT , Input ) ; DCI . AddToWorklist ( Res . getNode ( ) ) ; SDValue PSHUFBMaskOp = DAG . getBuildVector ( ByteVT , DL , PSHUFBMask ) ; DCI . AddToWorklist ( PSHUFBMaskOp . getNode ( ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , ByteVT , Res


<s> bool <ISA_LIT>16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg


<s> if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > <NUM_LIT> && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > <NUM_LIT> && ! FLOAT128_2REG_P ( mode ) ) return true ; return


<s> print_predicate ( MI , OS ) ; printInstruction ( MI , OS ) ; OS << <STR_LIT> ; OutStreamer . EmitRawText ( OS . str ( )


<s> EVT InScalarVT = InVT . getVectorElementType ( ) ; if ( InScalarVT . getFixedSizeInBits ( ) <= ScalarVT . getFixedSizeInBits ( ) ) return SDValue ( ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( In . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto IsConstVectorInRange = [ ] ( SDValue V , unsigned Min , unsigned Max ) { return <STR_LIT> ( V , [ Min , Max ] ( ConstantSDNode * C ) { return ! ( C -> getAPIntValue ( ) . ult ( Min ) || C -> getAPIntValue ( ) . ugt ( Max ) ) ; } ) ; } ; auto LHS = In . getOperand ( <NUM_LIT> ) ; auto RHS = In . getOperand ( <NUM_LIT> ) ; if ( ! IsConstVectorInRange ( RHS , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; auto AVGBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; auto AVGSplitter = [ & ] ( SDValue Op0 , SDValue Op1 ) { unsigned NumElemsPow2 = PowerOf2Ceil ( NumElems ) ; EVT Pow2VT = EVT :: getVectorVT ( * DAG . getContext ( ) , ScalarVT , NumElemsPow2 ) ; if ( NumElemsPow2 != NumElems ) { SmallVector < SDValue , <NUM_LIT> > Ops0 ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops1 ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Idx = DAG . getIntPtrConstant


<s> sel = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , sel ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_1 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_1 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_2 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; t_3 = expand_simple_binop ( SImode , AND , gen_lowpart ( SImode , t_3 ) , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_1 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; t_2 = expand_simple_binop ( SImode , IOR , t_2 , t_3 , t_2 , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_simple_binop ( SImode , IOR , sel , t_2 , sel , <NUM_LIT> , OPTAB_DIRECT ) ; sel = expand_mult ( SImode , sel , GEN_INT ( <NUM_LIT> ) , sel , <NUM_LIT> ) ; t_1 = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; break ; case E_V8QImode : sel = expand_simple_binop ( DImode , AND , sel , GEN_INT ( ( HOST_WIDE_INT


<s> else if ( RC == & <STR_LIT> ) CopyLocalOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyLocalOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyLocalOpcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( CopyLocalOpcode ) , DestReg ) . addReg ( SrcReg , KillSrc ? RegState


<s> unsigned Offset = TFL -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; return DAG . getConstant ( Offset * <NUM_LIT> * TFL -> getStackWidth ( MF ) , SDLoc


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getThisReturnPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: GHC ) return nullptr ; return STI . isTargetDarwin ( ) ?


<s> static void nios2_init_libfuncs ( void


<s> assert ( I . getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES && <STR_LIT> ) ; if ( RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) -> getID ( ) != <STR_LIT> || RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } unsigned NumElts = I . getNumOperands ( ) - <NUM_LIT> ; Register SrcReg = I . getOperand ( NumElts ) . getReg ( ) ; const LLT NarrowTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( ( WideTy . isVector ( ) || WideTy . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; assert ( WideTy . getSizeInBits ( ) > NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; if ( ! NarrowTy . isScalar ( ) ) return selectSplitVectorUnmerge ( I , MRI ) ; MachineIRBuilder MIB ( I ) ; unsigned CopyOpc = <NUM_LIT> ; unsigned ExtractSubReg = <NUM_LIT> ; if ( ! getLaneCopyOpcode ( CopyOpc , ExtractSubReg , NarrowTy . getSizeInBits ( ) ) ) return false ; MachineBasicBlock & MBB = * I . getParent ( ) ; SmallVector < Register , <NUM_LIT> > InsertRegs ; unsigned NumInsertRegs = NumElts - <NUM_LIT> ; if ( NarrowTy . getSizeInBits ( ) * NumElts == <NUM_LIT> ) { InsertRegs = SmallVector < Register , <NUM_LIT> > ( NumInsertRegs , SrcReg ) ; } else { for ( unsigned Idx = <NUM_LIT> ; Idx < NumInsertRegs ; ++ Idx ) { Register ImpDefReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & ImpDefMI = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImpDefReg ) ; Register InsertReg = MRI . createVirtualRegister ( & <STR_LIT>


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo


<s> static inline bool mode_supports_pre_incdec_p


<s> if ( next == NULL_RTX || GET_MODE ( next ) == TImode || CALL_P ( insn ) ) { PUT_MODE ( insn , QImode ) ; } else { PUT_MODE ( insn , SImode ) ; } } if ( get_attr_type ( insn ) == TYPE_NOTHING ) { if ( GET_MODE ( insn ) == QImode && prev != NULL && GET_MODE ( prev )


<s> if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt


<s> break ; case MCK__HASH_8 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__HASH_16 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK_ModImm : if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return Match_rGPR ; case MCK_GPRPair : if ( Op . isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) .

contains ( Op . getReg ( ) ) ) return Match_Success ;


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [


<s> exp = EXPD ( dl1 ) - EXPONENT_BIAS - MANTISSA_BITS ; if ( exp <= - PRECISION ) return <NUM_LIT> ; if ( ( EXPD ( dl1 ) == <NUM_LIT> ) && ! FRACD_ZERO_P ( dl1 ) ) return <NUM_LIT> ; if ( exp >= - HIGH_LL_FRAC_BITS ) { l = ( long long )


<s> rtx inner ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) return immed_double_const ( val , <NUM_LIT> , mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return hwint_to_const_double ( mode , val ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) inner = immed_double_const ( val

, <NUM_LIT> , GET_MODE_INNER ( mode ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getFSOpcode ( unsigned OpcCJE ) { switch ( OpcCJE ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default :


<s> BuildMI ( * MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; return ; } BuildMI ( * MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> )

. addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , N0 ) ; return SDValue (


<s> if ( Func . getName ( ) != <STR_LIT> && Func . getName ( ) != <STR_LIT> ) return false ; if ( Constant * Exp = dyn_cast < Constant > ( CI -> getArgOperand ( <NUM_LIT> ) ) ) if ( ConstantFP * CFP = dyn_cast_or_null < ConstantFP > ( Exp -> getSplatValue ( ) ) ) { if ( ! CI -> hasNoInfs ( ) || ! CI -> hasApproxFunc ( ) ) return false ; if ( ! CFP -> isExactlyValue ( <NUM_LIT> ) && ! CFP -> isExactlyValue ( <NUM_LIT> ) ) return false ; if ( CFP -> isExactlyValue ( <NUM_LIT> ) && ! CI -> hasNoSignedZeros (


<s> return getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) .


<s> NextBB = std :: next ( FI ) ; BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; if ( Next != E ) { BasicBlock * NextInstBB = Next -> getParent ( ) ; if ( NextInstBB != BB ) { BB = NextInstBB ; E = BB -> end ( ) ; FE = F .


<s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT