<s> if ( ! REG_P ( operands [ <NUM_LIT> ] ) || ! REG_P ( operands [ <NUM_LIT> ] ) ) return false ; regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; regno1 = true_regnum ( operands [ <NUM_LIT> ] ) ; return ix86_lea_outperforms ( insn , regno0 , regno1 , INVALID_REGNUM , <NUM_LIT>


<s> assert ( ( value <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) && <STR_LIT> ) ; O <<


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; BuildMI ( MBB , llvm :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIBundleBuilder ( MBB , I , llvm :: next ( llvm :: next ( I ) ) ) ; } return Changed


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override { uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) <STR_LIT> :: write < uint32_t > (


<s> void adjustArgFlags ( CallLowering :: ArgInfo & Arg , LLT Ty ) { if ( ! Ty . isPointer ( ) ) return ; auto & Flags = Arg . Flags [ <NUM_LIT> ] ; Flags . setPointer (


<s> InstrInfo & II = Instructions [ & MI ] ; assert ( Flag == StateWQM || Flag == StateExact ) ; if ( II . Needs ) return ; II . Needs =


<s> SDValue DataToStore = N -> getValue ( ) ; MVT VT = DataToStore . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; SDValue Mask = N -> getMask ( ) ; SDLoc dl ( Op ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && <STR_LIT> ) ; assert ( ( ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) ) ) && <STR_LIT> ) ; unsigned NumEltsInWideVec = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; MVT WideDataVT = <STR_LIT> ( ScalarVT , NumEltsInWideVec ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; DataToStore = ExtendToType ( DataToStore , WideDataVT , DAG ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; return DAG . getMaskedStore ( N -> getChain ( ) , dl , DataToStore , N -> getBasePtr ( ) , Mask

, N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> isTruncatingStore ( ) ) ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) : <ISA_LIT>AsmBackend ( T ) { HasAbsolutizedSet = true


<s> char buf [ <NUM_LIT> ] ; section * s ; if ( priority == DEFAULT_INIT_PRIORITY ) snprintf ( buf , sizeof ( buf ) , <STR_LIT> ) ; else { snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; } s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ; switch_to_section ( s ) ; assemble_aligned_integer ( INIT_ARRAY_ENTRY_BYTES , symbol


<s> * p = '_' ; dollar_inside ++ ; p = strchr ( p + <NUM_LIT> , '$' ) ; } if ( TREE_PUBLIC ( n -> decl ) ) { if ( ! RS6000_WEAK || ! DECL_WEAK ( n -> decl ) ) { if ( dollar_inside ) { if ( data -> function_descriptor ) fprintf ( data -> file , <STR_LIT> , buffer , name ) ; fprintf ( data -> file , <STR_LIT> , buffer , name ) ; } if ( data -> function_descriptor ) { fputs ( <STR_LIT> , data -> file ) ; RS6000_OUTPUT_BASENAME ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } fputs ( <STR_LIT> , data -> file ) ; assemble_name ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } else if ( DECL_WEAK ( n -> decl ) && ! data -> function_descriptor ) ASM_WEAKEN_DECL ( data -> file , n -> decl , name , NULL ) ; } else { if ( dollar_inside ) { if ( data -> function_descriptor ) fprintf ( data -> file ,


<s> return ( int8x8_t ) __builtin_neon_vshrs_nv8qi ( __a ,


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( Subtarget . isAIXABI ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TM . is<ISA_LIT>64 ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . is32BitELFABI ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , <STR_LIT> ) ; else markSuperRegs ( Reserved , <STR_LIT>


<s> static bool CC_<ISA_LIT>Assign2XLen ( unsigned XLen , CCState & State , CCValAssign VA1 , <STR_LIT> ArgFlags1 , unsigned ValNo2 , MVT ValVT2 , MVT LocVT2 , <STR_LIT> ArgFlags2 ) { unsigned XLenInBytes = XLen / <NUM_LIT> ; if ( unsigned Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , Reg , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; } else { unsigned StackAlign = std :: max ( XLenInBytes , ArgFlags1 . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , State . AllocateStack ( XLenInBytes , StackAlign ) , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , XLenInBytes ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( unsigned Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ; } else { State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , XLenInBytes ) , LocVT2 ,


<s> return __builtin_aarch64_crypto_sha1mv4si_uuuu ( hash_abcd , hash_e , wk


<s> case Triple :: COFF : return LowerGlobalAddressWindows ( Op , DAG ) ; case Triple :: ELF : return LowerGlobalAddressELF ( Op , DAG ) ; case Triple :: MachO : return LowerGlobalAddressDarwin ( Op , DAG ) ; } case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG


<s> Inst . addOperand ( MCOperand :: CreateImm ( ( Imm + Add ) & ( Add - <NUM_LIT> ) ) ) ; return Success


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result ; } else { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return


<s> if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> ,


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT ,


<s> if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Imm = ConvertI1VectorToInteger ( Op , DAG ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , Imm ) ; SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef ( ) ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) & <NUM_LIT> ) << idx ; HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getSelect ( dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG .


<s> MachineInstr * UseMI = Use -> getParent ( ) ; const MachineOperand & UseOp = UseMI -> getOperand ( Use . getOperandNo ( ) ) ; if ( UseOp . isReg ( ) && UseOp . getSubReg ( ) && OpToFold . isReg ( ) ) { continue ; } APInt Imm ; if ( FoldingImm ) { unsigned UseReg = UseOp . getReg ( ) ; const TargetRegisterClass * UseRC = TargetRegisterInfo :: isVirtualRegister ( UseReg ) ? MRI . getRegClass ( UseReg ) : TRI . getRegClass ( UseReg ) ; Imm = APInt ( <NUM_LIT> , OpToFold . getImm ( ) ) ; if ( UseOp . getSubReg ( ) ) { if ( UseRC -> getSize ( ) != <NUM_LIT> ) continue ; if ( UseOp . getSubReg ( ) == AMDGPU :: sub0 ) { Imm = Imm . getLoBits ( <NUM_LIT> ) ; } else { assert ( UseOp . getSubReg ( ) == AMDGPU :: sub1 ) ; Imm = Imm . getHiBits ( <NUM_LIT> ) ; } } if ( UseMI -> getOpcode ( ) == AMDGPU :: COPY ) { unsigned DestReg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DestRC = TargetRegisterInfo :: isVirtualRegister ( DestReg ) ? MRI . getRegClass ( DestReg ) : TRI . getRegClass ( DestReg ) ; unsigned MovOp = TII -> getMovOpcode ( DestRC ) ; if ( MovOp == AMDGPU :: COPY ) continue ; UseMI -> setDesc ( TII -> get ( MovOp ) ) ; } } const MCInstrDesc & UseDesc = UseMI -> getDesc ( ) ; if ( UseDesc . isVariadic ( ) || UseDesc . OpInfo [ Use . getOperandNo ( ) ] . RegClass == - <NUM_LIT> ) continue ; if ( FoldingImm ) { MachineOperand ImmOp = MachineOperand :: CreateImm ( Imm . getSExtValue ( ) ) ; tryAddToFoldList ( FoldList , UseMI , Use . getOperandNo ( ) , & ImmOp , TII ) ; continue ; } tryAddToFoldList ( FoldList , UseMI , Use . getOperandNo ( ) , & OpToFold , TII ) ; } for ( FoldCandidate & Fold : FoldList ) { if ( updateOperand ( Fold , TRI ) ) { if ( ! Fold . isImm ( ) ) { assert ( Fold . OpToFold && Fold . OpToFold -> isReg ( ) ) ; Fold . OpToFold -> setIsKill ( false ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << Fold . UseOpNo << <STR_LIT> << *


<s> LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { SDValue ResNode ; ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; const Constant * C = N ->


<s> static DecodeStatus decodePixelRotOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address


<s> size = ( gp_saved * UNITS_PER_WORD ) + ( fp_saved * UNITS_PER_HWFPVALUE ) ; if ( ! no_rtl && size > <NUM_LIT> ) { rtx ptr = force_reg ( Pmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - size ) ) ; if ( gp_saved > <NUM_LIT> ) { rtx mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , ptr , fp_saved * UNITS_PER_HWFPVALUE ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( locargs -> grcount + GP_ARG_FIRST , mem , gp_saved ) ; } if ( fp_saved > <NUM_LIT> ) { rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; gcc_assert ( UNITS_PER_WORD == UNITS_PER_HWFPVALUE ) ; move_block_from_reg ( locargs -> frcount + FP_ARG_FIRST , mem ,


<s> if ( flags & MASK_64BIT ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_APP_REGS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_FASTER_STRUCTS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_FLAT ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_FMAF ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_FSMULD ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_FPU ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_HARD_QUAD ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_POPC ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_PTR64 ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_STACK_BIAS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_UNALIGNED_DOUBLES ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_V8PLUS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS ) fprintf ( stderr , <STR_LIT> ) ; if ( flags & MASK_VIS2 ) fprintf ( stderr , <STR_LIT>


<s> op0 = frv_volatile_memref ( insn_data [ icode ] . operand [ <NUM_LIT> ] . mode , op0 ) ; convert_move ( target , op0 , <NUM_LIT> ) ; emit_insn ( GEN_FCN ( icode ) ( copy_rtx ( op0 ) , cookie ,


<s> while ( num -- ) { rtx op = operands [ num ] ; if ( GET_CODE ( op ) == MEM ) { lo_half [ num ] = adjust_address ( op , DImode , <NUM_LIT> ) ; hi_half [ num ] = adjust_address ( op , DImode , <NUM_LIT> ) ; } else { lo_half [ num ] = simplify_gen_subreg ( DImode


<s> MachineFunction :: iterator EndMBB = MF . end ( ) ; for ( ; MBBI != EndMBB ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB ->


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( false && <STR_LIT>


<s> static bool UpdateOperandRegClass ( MachineInstr * Instr ) { MachineBasicBlock * MBB = Instr -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetMachine * TM = & MF -> getTarget ( ) ; const TargetInstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; const TargetRegisterInfo * TRI = TM -> getSubtargetImpl ( ) -> getRegisterInfo ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr -> getNumOperands ( ) ; OpIdx < EndIdx ; ++ OpIdx )


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>WinCOFFObjectWriter ( OS ,


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasE2 ( ) ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) markSuperRegs ( Reserved , <STR_LIT> + i ) ; } markSuperRegs ( Reserved , <STR_LIT>


<s> void initRPTracker ( RegPressureTracker & RPTracker


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { llvm_unreachable ( <STR_LIT> )


<s> nodeType getType ( ) { return type . getNodeType


<s> x = plus_constant ( Pmode , frame_pointer_rtx , offset ) ; x = gen_rtx_MEM ( SImode , x


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto CC = static_cast < <STR_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ; BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB


<s> case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FMA : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FCONSTANT : case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : case TargetOpcode :: G_FCEIL : case TargetOpcode :: G_FFLOOR : case TargetOpcode :: G_FNEARBYINT : case TargetOpcode :: G_FNEG : case TargetOpcode :: G_FCOS : case TargetOpcode :: G_FSIN : case TargetOpcode :: G_FLOG10 : case TargetOpcode :: G_FLOG : case TargetOpcode :: G_FLOG2 : case TargetOpcode :: G_FSQRT : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FEXP : case TargetOpcode :: G_FRINT : case TargetOpcode :: G_INTRINSIC_TRUNC : case TargetOpcode :: G_INTRINSIC_ROUND : case TargetOpcode :: G_FMAXNUM : case TargetOpcode


<s> args_byte_size += hfa_size ; fp_regs ++ ; } if ( ! cum -> prototype ) offset = <NUM_LIT> ; else if ( byte_size != offset ) int_regs += offset / UNITS_PER_WORD ; for ( ; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS ; i ++ ) { enum machine_mode gr_mode = DImode ; unsigned int gr_size ; if ( offset & <NUM_LIT> ) gr_mode = SImode ; else if ( byte_size - offset == <NUM_LIT> ) gr_mode = SImode ; loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( gr_mode , ( basereg + int_regs ) ) , GEN_INT ( offset ) ) ; gr_size = GET_MODE_SIZE ( gr_mode ) ; offset += gr_size ; if ( gr_size == UNITS_PER_WORD || ( gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == <NUM_LIT> ) ) int_regs ++ ; else if ( gr_size > UNITS_PER_WORD ) int_regs += gr_size / UNITS_PER_WORD ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( i , loc ) ) ; } else if ( mode == TFmode || mode == TCmode || ( ! FLOAT_MODE_P ( mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) ) { int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; if ( BYTES_BIG_ENDIAN && ( mode == BLKmode || ( type && AGGREGATE_TYPE_P ( type ) ) ) && byte_size < UNITS_PER_WORD && byte_size > <NUM_LIT> ) { rtx gr_reg = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , ( basereg + cum -> words + offset ) ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gr_reg ) ) ; } else return gen_rtx_REG ( mode , basereg


<s> virtual const TargetData * getTargetData


<s> FunctionPass * <ISA_LIT>PassConfig :: createTargetRegisterAllocator ( bool


<s>
const
char
*
JTEntryDirective
=
MJTI
->
getEntrySize
(
)
==
<NUM_LIT>
TAI
->
getData32bitsDirective
(
)
:
TAI
->
getData64bitsDirective
(
)
;
O
<<
JTEntryDirective
<<
' '
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
||
Subtarget
->
isPICStyleStubPIC
(
)
)
{
O
<<
TAI
->
getPrivateGlobalPrefix
(
)
<<
getFunctionNumber
(
)
<<
'_'
<<
uid
<<
<STR_LIT>
<<
MBB
->
getNumber
(
)
;
}
else
if
(
Subtarget
->
isPICStyleGOT
(
)
)
{
printBasicBlockLabel
(
MBB
,
false
,
false
,
false
)
;
O
<<
<STR_LIT>
;
}
else
printBasicBlockLabel
(
MBB
,
false


<s> return ( __m512i ) __builtin_ia32_pmovsxdq512_mask ( ( __v8si ) __X , ( __v8di ) _mm512_undefined_si512 ( ) , (


<s> SUnit * <ISA_LIT>SchedStrategy :: pickOther ( int QID ) { SUnit * SU = nullptr ; std :: vector < SUnit * > & AQ = Available [ QID ] ; if ( AQ . empty ( ) ) { MoveUnits ( Pending [ QID ] , AQ ) ; } if ( ! AQ . empty ( ) ) { SU = AQ . back ( ) ; AQ . resize ( AQ . size ( ) - <NUM_LIT> ) ; } return SU


<s> static DecodeStatus DecodeCRRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t


<s> static DecodeStatus DecodeG8pRCRegisterClass ( MCInst & Inst , uint64_t RegNo

, uint64_t Address , const void * Decoder ) {


<s> Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( OutStreamer , TmpInst


<s> RegisterTarget < Triple :: cpu0el , true > Y ( getThe<ISA_LIT>elTarget ( ) , <STR_LIT> , <STR_LIT>


<s> static DecodeStatus DecodeDaddiGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) << <NUM_LIT> ; bool HasRs = false ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs =


<s> if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return


<s> if ( fcode == AARCH64_BUILTIN_RNG_RNDR ) icode = CODE_FOR_aarch64_rndr ; else if ( fcode == AARCH64_BUILTIN_RNG_RNDRRS ) icode = CODE_FOR_aarch64_rndrrs ; else gcc_unreachable ( ) ; rtx rand = gen_reg_rtx ( DImode ) ; pat = GEN_FCN ( icode ) ( rand ) ; if ( ! pat ) return NULL_RTX ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx res_addr = expand_normal ( arg0 ) ; res_addr = convert_memory_address ( Pmode , res_addr ) ; rtx res_mem = gen_rtx_MEM ( DImode , res_addr ) ; emit_insn ( pat ) ; emit_move_insn ( res_mem , rand


<s> assert ( MaxNumVScale && <STR_LIT> ) ; return * MaxNumVScale * VF . getKnownMinValue


<s> char pattern [ <NUM_LIT> ] ; char size ; rtx code = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; size = nds32_byte_to_size ( byte ) ; switch ( nds32_mem_format ( operands [ <NUM_LIT> ] ) ) { case ADDRESS_REG : operands [ <NUM_LIT> ] = code ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case ADDRESS_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_INC_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_FP_IMM7U : output_asm_insn ( <STR_LIT> , operands )


<s> static const fltSemantics * getFltSemantics ( MVT


<s> MachineInstr * DefMI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; DefMI -> substituteRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( MI , DefMI ) ; MachineInstr & Instr = * -- MI ; MachineOperand & MO = Instr . getOperand ( <NUM_LIT> ) ; assert ( MO . isReg ( ) && MO . isDef ( ) ) ; if ( ! MO . getReg ( ) . isVirtual ( ) ) return ; if ( MO . isTied ( )


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , false ,

MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( ! GetLane ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewToVT = EVT :: getIntegerVT ( C ,


<s> if ( AGGREGATE_TYPE_P ( type ) && TYPE_ALIGN ( type ) < GET_MODE_ALIGNMENT ( mode ) )


<s> static bool readInstruction16 ( const MemoryObject & region , uint64_t address , uint64_t & size , uint16_t & insn ) { uint8_t Bytes [ <NUM_LIT> ] ; if ( region . readBytes ( address , <NUM_LIT> , Bytes ) == - <NUM_LIT> ) { size = <NUM_LIT> ; return false ; } insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> )

| ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> if ( ! SN -> isTruncatingStore ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> ) , Ops ,


<s> if ( Kind . isMergeableConst4 ( ) ) return MergeableConst4Section ; if ( Kind . isMergeableConst8 ( ) ) return MergeableConst8Section ; if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ; assert ( ( Kind . isReadOnly ( ) || Kind . isReadOnlyWithRel ( ) ) &&


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo


<s> len = get_attr_length ( insn ) ; if ( len <= <NUM_LIT> ) return <NUM_LIT> ; if ( ! JUMP_P ( insn ) ) { enum attr_type type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MULTI : if ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) return <NUM_LIT> ; break ; case TYPE_OTHER : case TYPE_FCMP : break ; default : return len ; } l = get_attr_length_address ( insn ) ; if ( l < <NUM_LIT> && symbolic_reference_mentioned_p ( PATTERN ( insn ) ) ) l = <NUM_LIT> ; } if ( l ) return <NUM_LIT> + l ; else return


<s> static uint16_t name ( struct InternalInstruction * insn , \ OperandType type , \ uint8_t index , \ uint8_t * valid ) { \ * valid = <NUM_LIT> ; \ switch ( type ) { \ default : \ debug ( <STR_LIT> ) ; \ * valid = <NUM_LIT> ; \ return <NUM_LIT> ; \ case TYPE_Rv : \ return base + index ; \ case TYPE_R8 : \ if ( insn -> rexPrefix && \ index >= <NUM_LIT> && index <= <NUM_LIT> ) { \ return prefix ## _SPL + ( index - <NUM_LIT> ) ; \ } else { \ return prefix ## _AL + index ; \ } \ case TYPE_R16 : \ return prefix ## _AX + index ; \ case TYPE_R32 : \ return prefix ## _EAX + index ; \ case TYPE_R64 : \ return prefix ## _RAX + index ; \ case TYPE_ZMM : \ return prefix ## _ZMM0 + index ; \ case TYPE_YMM : \ return prefix ## _YMM0 + index ; \ case TYPE_XMM : \ return prefix ## _XMM0 + index ; \ case TYPE_VK : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _K0 + index ; \ case TYPE_MM64 : \ return prefix ## _MM0 + ( index & <NUM_LIT> ) ; \ case TYPE_SEGMENTREG : \ if ( ( index & <NUM_LIT> ) > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _ES + ( index & <NUM_LIT> ) ; \ case TYPE_DEBUGREG : \ return prefix ## _DR0 + index ; \ case TYPE_CONTROLREG : \ return prefix ## _CR0 + index

; \ case TYPE_BNDR : \ if ( index > <NUM_LIT> ) \ * valid = <NUM_LIT> ; \ return prefix ## _BND0 + index ; \ case TYPE_MVSIBX : \ return prefix ## _XMM0 + index ; \ case TYPE_MVSIBY : \ return prefix ## _YMM0 + index ; \ case TYPE_MVSIBZ : \ return prefix ## _ZMM0 + index ; \ } \ }


<s> for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) O << utohexstr ( ( Value & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) )


<s> initialize<ISA_LIT>ProxyRegErasurePass ( * PassRegistry :: getPassRegistry ( )


<s> if ( ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) && STI . ldsRequiresM0Init ( ) ) { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ,


<s> bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , <NUM_LIT>


<s> SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; } else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; } } } for ( auto * II : Gathers ) Changed |= tryCreateStridedLoadStore ( II , II -> getType ( ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ; for ( auto * II : Scatters ) Changed |= tryCreateStridedLoadStore ( II , II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) , II -> getArgOperand ( <NUM_LIT> )


<s> std :: map < unsigned , IntrinsicData > :: const_iterator itr = IntrWithoutChainMap . find ( IntNo ) ; if ( itr == IntrWithoutChainMap . end ( ) ) return NULL ; return & ( itr


<s> case CortexA65 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexA77 : case CortexA78 : case CortexA78C : case CortexR82 : case CortexX1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case A64FX : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case AppleA7 : case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT>


<s> return ( uint32x2_t ) __builtin_neon_vreinterpretv2sidi (


<s> } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ( ! TT . isOSAIX ( ) || STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! L || L == <NUM_LIT> || L == <NUM_LIT> || L == <NUM_LIT> || L == <NUM_LIT> ) { O << <STR_LIT> ; if ( L != <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; printAnnotation ( O , Annot ) ; return ; } } if ( ! printAliasInstr ( MI , Address , STI , O ) ) printInstruction ( MI


<s> } auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) { assert ( ( isa < CondCodeSDNode > ( V ) || V . getValueType ( ) . isScalableVector ( ) ) && <STR_LIT> ) ; Operands . push_back (


<s> w = ( __vector signed short ) vec_splats ( __w ) ; return ( __m64 ) ( ( __vector long long ) w ) [ <NUM_LIT> ] ; __m64_union __res ; __res . as_short [ <NUM_LIT> ] = __w ; __res . as_short [ <NUM_LIT> ] = __w ; __res . as_short [ <NUM_LIT> ] =


<s> assert ( I -> getType ( ) -> getTypeID ( ) == Type :: VectorTyID ) ; SrcWidth = I -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> getPrimitiveSizeInBits ( ) ; DestWidth = I -> getType ( ) -> getScalarType ( ) -> getPrimitiveSizeInBits ( ) ; if ( SrcWidth == <NUM_LIT> ) { if ( DestWidth ==


<s> static reg_class_t ix86_spill_class ( reg_class_t rclass , machine_mode mode ) { if ( <NUM_LIT> && TARGET_GENERAL_REGS_SSE_SPILL && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC && TARGET_INTER_UNIT_MOVES_FROM_VEC && ( mode == SImode || ( TARGET_64BIT && mode == DImode ) ) && INTEGER_CLASS_P ( rclass )


<s> gcc_assert ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ; long_jump_p = ( insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; switch ( code ) { case GT : case GE : case


<s> if ( GP_REG_P ( REGNO ( dest ) ) ) return <STR_LIT> ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return <STR_LIT> ; if ( TARGET_64BIT ) return <STR_LIT> ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return <STR_LIT> ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ?


<s> CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CallerPreserved ) return false ; bool CCMatch = CallerCC == CalleeCC ; if ( DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { if ( canGuaranteeTCO ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( IsVarArg ) return false ; for ( const Argument & Arg : CallerF -> args ( ) ) { if ( Arg . hasByValAttr ( ) ) return false ; } LLVMContext & Ctx = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , Ctx , Ins , CCAssignFnForCall ( CalleeCC , IsVarArg ) , CCAssignFnForCall

( CallerCC , IsVarArg ) ) ) return false ;


<s> return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } default : return MI . getDesc ( ) . getSize (


<s> assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; } MI . eraseFromParent


<s> assert ( ( Kills & Defs ) == <NUM_LIT> && <STR_LIT> ) ; while ( Kills && Defs ) { unsigned KReg = CountTrailingZeros_32 ( Kills ) ; unsigned DReg = CountTrailingZeros_32 ( Defs ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> << DReg << <STR_LIT> ) ; std :: swap ( Stack [ getSlot ( KReg ) ] , Stack [ getSlot ( DReg ) ] ) ; std :: swap ( RegMap [ KReg ] , RegMap [ DReg ] ) ; Kills &= ~ ( <NUM_LIT> << KReg ) ; Defs &= ~ ( <NUM_LIT> << DReg ) ; } if ( Kills && I != MBB -> begin ( ) ) { MachineBasicBlock :: iterator I2 = llvm :: prior ( I ) ; for ( ; ; ) { unsigned KReg = getStackEntry ( <NUM_LIT> ) ; if ( ! ( Kills & ( <NUM_LIT> << KReg ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; popStackAfter ( I2 ) ; Kills &= ~ ( <NUM_LIT> << KReg ) ; } } while ( Kills ) { unsigned KReg = CountTrailingZeros_32 ( Kills ) ; DEBUG ( dbgs ( ) << <STR_LIT> << KReg << <STR_LIT> ) ; freeStackSlotBefore ( I , KReg


<s> nregs = XVECLEN ( p , <NUM_LIT> ) - <NUM_LIT> ; reg = REGNO ( XEXP ( XVECEXP ( p , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( reg < <NUM_LIT> ) { if ( nregs * <NUM_LIT> == offset - <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> ) ; offset -= <NUM_LIT> ; } reg_size = <NUM_LIT> ; } else if ( IS_VFP_REGNUM ( reg ) ) { offset -= <NUM_LIT> ; reg_size = <NUM_LIT> ; } else if ( reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM ) { asm_fprintf ( asm_out_file , <STR_LIT> , reg , nregs ) ; return ; } else abort ( ) ; if ( offset != nregs * reg_size ) abort ( ) ; fprintf ( asm_out_file , <STR_LIT> ) ; offset = <NUM_LIT> ; lastreg = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= nregs ; i ++ ) { e = XVECEXP ( p , <NUM_LIT> , i ) ; if ( GET_CODE ( e ) != SET || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != MEM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG ) abort ( ) ; reg = REGNO ( XEXP ( e , <NUM_LIT> ) ) ; if ( reg < lastreg ) abort ( ) ; if ( i != <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( reg ) ) asm_fprintf ( asm_out_file , <STR_LIT> , ( reg - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( asm_out_file , <STR_LIT> , reg ) ; e = XEXP ( XEXP ( e , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( e ) == PLUS ) { offset += reg_size ; if ( GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG || REGNO ( XEXP ( e , <NUM_LIT> ) ) != SP_REGNUM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != CONST_INT || offset != INTVAL ( XEXP ( e , <NUM_LIT> ) ) ) abort ( ) ; } else if ( i != <NUM_LIT> || GET_CODE ( e ) != REG || REGNO ( e ) != SP_REGNUM )


<s> case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( )


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; } } else { switch ( CI . Width + Paired . Width ) { default : return nullptr ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT>


<s> if ( Size == <NUM_LIT> ) return ( getGeneration ( ) >=


<s> if ( mode != TFmode && FLOAT128_IBM_P ( TFmode ) ) set_conv_libfunc ( sext_optab , mode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , IFmode , mode , <STR_LIT> ) ; if ( mode != TFmode && FLOAT128_IBM_P ( TFmode ) ) set_conv_libfunc ( trunc_optab , TFmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , SDmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , mode , DDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , mode , TDmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TDmode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , DImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , DImode , <STR_LIT> ) ; if ( TARGET_POWERPC64 ) { set_conv_libfunc ( sfix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , TImode , mode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , mode , TImode , <STR_LIT> ) ; set_conv_libfunc ( ufloat_optab , mode , TImode , <STR_LIT> ) ; } } else { set_optab_libfunc ( add_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( neg_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , mode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , mode , <STR_LIT> ) ; if ( TARGET_PPC_GPOPT ) set_optab_libfunc ( sqrt_optab


<s> const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + <NUM_LIT> ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( Offset > <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DstReg != <STR_LIT> && <STR_LIT> ) ; II ++ ; if ( II != MBB . end ( ) ) foldFrameOffset ( II , Offset , DstReg ) ; switch ( DstReg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Offset ) ) { Opcode = <STR_LIT> ; break ; } LLVM_FALLTHROUGH ; } default : { Opcode = <STR_LIT> ; Offset = - Offset ; break ; } } MachineInstr * New = BuildMI ( MBB , II , dl , TII . get ( Opcode ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addImm ( Offset ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return ; } if ( Offset > <NUM_LIT> ) { unsigned AddOpc = <STR_LIT> , SubOpc = <STR_LIT> ; int AddOffset = Offset -


<s> void R600SchedStrategy :: releaseTopNode ( SUnit *


<s> return insn -> prefixPresent [ prefix ] == <NUM_LIT> && insn -> prefixLocations [


<s> return __builtin_aarch64_crypto_sha1cv4si_uuuu ( hash_abcd , hash_e , wk


<s> & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . add ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . add ( SrcRegSub1 ) . addReg ( MidReg ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , GetGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty ,


<s> Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( Offset ) { assert ( Offset > <NUM_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Offset , * Ctx ) , * Ctx ) ; } if ( TargetKind != <ISA_LIT>MCExpr :: CEK_None ) Expr = <ISA_LIT>MCExpr :: create ( TargetKind , Expr , * Ctx ) ; return MCOperand :: createExpr


<s> __builtin_ia32_scatterpfdpd ( mask , ( __v8si ) index , ( long long


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; unsigned Zero = MRI . createVirtualRegister ( PtrRC ) ; unsigned Drop = MRI . createVirtualRegister ( PtrRC ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; BuildMI ( MBB , InsertAddr , DL , TII -> get (

<STR_LIT> ) , Zero ) . addImm ( <NUM_LIT> ) ;


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind


<s> static DecodeStatus DecodePRRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= array_lengthof ( PRRegDecoderTable ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( PRRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler :: Success


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( ! MRI . isPhysRegUsed ( reg ) ) continue ; unsigned mapped_reg = ( reg - <STR_LIT> + <STR_LIT> ) ; assert ( ! MRI . isPhysRegUsed ( mapped_reg ) ) ; MRI . replaceRegWith ( reg , mapped_reg ) ; MRI . setPhysRegUnused ( reg


<s> OS << getAssumed ( ) . getLower ( ) << ',' << getAssumed ( ) . getUpper ( ) - <NUM_LIT> ; AttrList . push_back ( Attribute :: get ( Ctx , <STR_LIT> , OS . str ( ) ) ) ; return IRAttributeManifest :: manifestAttrs ( A , getIRPosition (


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; Is<ISA_LIT>64 = TheTriple . is<ISA_LIT>64 ( ) ; IsDarwin = TheTriple . isMacOSX


<s> if ( isa < LoadInst > ( I ) ) { } else if ( StoreInst * SI = dyn_cast < StoreInst > ( I ) ) { if ( V != SI -> getOperand ( <NUM_LIT> ) ) return true ; } else if ( Operator :: getOpcode ( I ) == Instruction :: GetElementPtr ) { if ( isAddressTaken ( I ) ) return true ; } else if ( Operator :: getOpcode ( I ) == Instruction :: BitCast ) { if ( isAddressTaken ( I ) ) return true ; } else if ( ICmpInst * ICI = dyn_cast < ICmpInst > ( I


<s> } SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Passv64i1ArgInRegs ( dl , DAG , Chain , ValToCopy , RegsToPass , VA , RVLocs [ ++ I ] , Subtarget ) ; assert ( <NUM_LIT> == RegsToPass . size ( ) && <STR_LIT> ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RVLocs [ I ] . getLocReg ( ) ) ; } else { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ValToCopy ) ) ; } for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , dl , Reg . first , Reg . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( RetOps [ <NUM_LIT> ] , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget . is64Bit ( ) && ! Subtarget . isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RetValReg ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ; <STR_LIT> opcode =


<s> else func_addr = func ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = gen_rtx_USE ( VOIDmode , cookie ) ; n = <NUM_LIT> ; if ( TARGET_SECURE_PLT && flag_pic && GET_CODE ( func_addr ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( func_addr ) ) call [ n ++ ] = gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ; call [ n ++ ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n , call


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const MCSubtargetInfo


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { bool Modified = false ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = STI . getRegisterInfo ( ) ; TII = STI . getInstrInfo ( ) ; MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ; for ( Block & MBB : MF


<s> assert ( ( Kind == k_Memory ) && <STR_LIT> ) ; return Mem .


<s> assert ( NOps == <NUM_LIT> ) ; O << '\t' << MAI -> getCommentString ( ) << <STR_LIT> ; DIVariable V ( const_cast < MDNode * > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) ) ; O << V . getName ( ) ; O << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this , Subtarget . isDarwin (


<s> if ( ! isUIntN ( Width , Value ) ) { std :: string Diagnostic = <STR_LIT> + Description ; int64_t Max = maxUIntN ( Width ) ; Diagnostic += <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ; if ( Ctx )


<s> Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; AI != AE ; AI ++ ) { CCValAssign & VA = ArgLocs [ AI ] ; SDValue Arg = OutVals [ AI ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto Reg


<s> MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = OrigBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddr11MM ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT>


<s> for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return false ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumVecs + <NUM_LIT> ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , VLD -> getDebugLoc ( ) , SDTys , Ops , <NUM_LIT> , VLDMemInt -> getMemoryVT ( ) , VLDMemInt ->


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantFP ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) const { if ( ! ST -> hasVFP3 ( ) ) return SDValue ( ) ; bool IsDouble = Op . getValueType ( ) == <STR_LIT> ; ConstantFPSDNode * CFP = cast < ConstantFPSDNode > ( Op ) ; APFloat FPVal = CFP -> getValueAPF ( ) ; int ImmVal = IsDouble ? <STR_LIT> ( FPVal ) : <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) .


<s> } case LABEL_REF : * total = <NUM_LIT> ; return true ; case CONST : case SYMBOL_REF : * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : if ( x != CONST0_RTX ( GET_MODE ( x ) == VOIDmode ? DImode : GET_MODE ( x ) ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case MULT : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT || exact_log2 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) ) { if ( TARGET_HAS_MUL_INSNS ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) + COSTS_N_INSNS ( <NUM_LIT> ) / <NUM_LIT> ; return true ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; case UDIV : case MOD : case UMOD : case DIV : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT || exact_log2 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; case AND : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT && ! CONST_OK_FOR_LETTER_P ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) , 'I' ) ) { * total = ( rtx_cost ( XEXP ( x , <NUM_LIT> ) , outer_code ) + <NUM_LIT> + <NUM_LIT> * GET_MODE_NUNITS ( GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ) ; return true ; } return false ; case ZERO_EXTEND : case SIGN_EXTEND : * total = rtx_cost ( XEXP ( x , <NUM_LIT> ) ,


<s> return ( int32x4_t ) __builtin_neon_vmlals_lanev4hi ( __a ,


<s> unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < <NUM_LIT> ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , <ISA_LIT>FI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize ,


<s> rtx stkslot = gen_rtx_MEM ( GET_MODE ( reg ) , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; rtx insn = emit_move_insn ( reg , stkslot ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; return GET_MODE_SIZE ( GET_MODE ( reg


<s> static void note_np_check_stores ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ATTRIBUTE_UNUSED ) { if ( REG_P ( x ) && ( REGNO ( x ) == REG_CC || ( int ) REGNO (

x ) == np_check_regno ) ) np_check_regno = - <NUM_LIT> ;


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { MIB . addUse


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemRI ( OperandVector & Operands ) { OperandMatchResultTy Result = parseImmediate ( Operands ) ; if ( Result != MatchOperand_Success ) return Result ; AsmToken CommaTok = Lexer . getTok ( ) ; if ( CommaTok . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; consumeToken ( ) ; Result = parseRegister ( Operands ) ; if ( Result != MatchOperand_Success ) return MatchOperand_ParseFail ; unsigned Size = Operands . size ( ) ; assert ( Size >= <NUM_LIT> ) ; auto RegOperand = std :: move ( Operands [ Size - <NUM_LIT> ] ) ; auto ImmOperand = std :: move ( Operands [ Size - <NUM_LIT> ] ) ; Operands . pop_back ( )


<s> const typename std :: remove_reference < copier_type > :: type & get_copier ( ) const SPIMPL_NOEXCEPT { return


<s> rtx desta , srca , count ; rtx desto , srco , counto ; desta = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; srca = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; count = operands [ <NUM_LIT> ] ; desto = gen_reg_rtx ( Pmode ) ; srco = gen_reg_rtx ( Pmode ) ; counto = gen_reg_rtx ( HImode ) ; if ( GET_CODE ( desta ) != REG || REGNO ( desta ) < FIRST_PSEUDO_REGISTER ) desta = copy_to_mode_reg ( Pmode , desta ) ; if ( GET_CODE ( srca ) != REG || REGNO ( srca ) < FIRST_PSEUDO_REGISTER ) srca = copy_to_mode_reg ( Pmode , srca ) ; if ( GET_CODE ( count ) == CONST_INT && ! ( INTVAL ( count ) & <NUM_LIT> ) && ( INTVAL ( count ) > <NUM_LIT> ) ) { count = copy_to_mode_reg ( HImode , GEN_INT ( INTVAL ( count ) / <NUM_LIT> ) ) ; if ( TARGET_A16 ) emit_insn ( gen_cpymemhi_whi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_cpymemhi_wpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return <NUM_LIT> ; } if ( GET_CODE ( count ) != REG || REGNO ( count ) < FIRST_PSEUDO_REGISTER ) count = copy_to_mode_reg ( HImode , count ) ; if ( TARGET_A16 ) emit_insn ( gen_cpymemhi_bhi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_cpymemhi_bpsi_op ( desto , srco , counto , desta , srca , count


<s> if ( ( mask [ <NUM_LIT> ] >> REG_RA ) & <NUM_LIT> ) alpha_procedure_type = PT_STACK ; else if ( get_frame_size ( ) != <NUM_LIT> ) alpha_procedure_type = PT_REGISTER ; else alpha_procedure_type = PT_NULL ; if ( alpha_procedure_type == PT_STACK ) sa_size -= <NUM_LIT> ; vms_base_regno = ( frame_pointer_needed || current_function_has_nonlocal_label || alpha_procedure_type == PT_STACK || current_function_outgoing_args_size ) ? REG_PV : HARD_FRAME_POINTER_REGNUM ; vms_save_fp_regno = - <NUM_LIT> ; if ( vms_base_regno == HARD_FRAME_POINTER_REGNUM ) for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! fixed_regs [ i ] && call_used_regs [ i ] && ! regs_ever_live [ i ] ) vms_save_fp_regno = i ; if ( vms_save_fp_regno == - <NUM_LIT> && alpha_procedure_type == PT_REGISTER ) vms_base_regno = REG_PV , alpha_procedure_type = PT_STACK ; else if ( alpha_procedure_type == PT_NULL ) vms_base_regno = REG_PV ; vms_unwind_regno = ( vms_base_regno == REG_PV ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; if ( alpha_procedure_type == PT_STACK ) sa_size += <NUM_LIT> ; } else { if ( sa_size & <NUM_LIT> ) sa_size ++ ; } return sa_size *


<s> for ( unsigned i = <NUM_LIT> ; i < W ; ++ i ) { const BitTracker :: BitValue & V1 = OutC1 [ i ] , & V2 = OutC2 [ i ] ; if ( V1 . Type != V2 . Type || V1 . Type == BitTracker :: BitValue :: One ) return false ; if ( V1 . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V1 . RefI . Pos != V2 . RefI . Pos ) return false ; if ( V1 . RefI . Reg != InpR1 ) return false ; if ( V2 . RefI . Reg == <NUM_LIT> || V2 .


<s> if ( ! isPreISelGenericOpcode ( Opcode ) ) { if ( Opcode == TargetOpcode :: LOAD_STACK_GUARD ) return false ; if ( I . isCopy ( ) ) return selectCopy ( I , MRI ) ; return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ; if ( selectImpl ( I , CoverageInfo ) ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . print ( dbgs ( ) ) ) ; switch ( I . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_STORE : case TargetOpcode :: G_LOAD : return selectLoadStoreOp ( I , MRI , MF ) ; case TargetOpcode :: G_GEP : case TargetOpcode :: G_FRAME_INDEX : return selectFrameIndexOrGep ( I , MRI , MF ) ; case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MRI , MF ) ; case TargetOpcode :: G_CONSTANT : return selectConstant ( I , MRI , MF ) ; case TargetOpcode :: G_FCONSTANT : return materializeFP ( I , MRI , MF ) ; case TargetOpcode :: G_PTRTOINT : case TargetOpcode :: G_TRUNC : return selectTruncOrPtrToInt ( I , MRI , MF ) ; case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_CONCAT_VECTORS : return selectMergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDValue Load = DAG . getNode ( <STR_LIT> , DL , {


<s> return ( MI -> isBranch ( ) && isPredicated ( * MI ) ) || isConditionalTransfer ( MI ) || isConditionalALU32 ( MI ) || isConditionalLoad ( MI ) || ( MI -> mayStore ( ) && isPredicated ( * MI

) && ! isNewValueStore ( MI ) && ! isPredicatedNew ( * MI ) ) ;


<s> uint64_t Length = Field >> <NUM_LIT> ; uint64_t Base = ( Field >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ?


<s> static bool isFrameLoadOpcode ( int Opcode ) { switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; break ; } return


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RegClass = OpInfo [ OpIdx ] . RegClass ; assert ( ( RegClass == <STR_LIT> || RegClass == <STR_LIT> ) && <STR_LIT> ) ; bool isSP = ( RegClass == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeVFPRd ( insn , isSP ) ) ) ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; RegClass = OpInfo [ OpIdx ] . RegClass


<s> std :: unique_ptr < MCELFObjectTargetWriter > MOTW ( new <ISA_LIT>ELFObjectWriter ( OSABI ) ) ; return createELFObjectWriter ( std :: move ( MOTW


<s> MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute (


<s> return ( uint16x8_t ) __builtin_neon_vcvtmuv8hf


<s> arc_regno_reg_class [ R30_REG ] = GENERAL_REGS ; } } if ( TARGET_MUL64_SET ) { fix_start = R57_REG ; fix_end = R59_REG ; strcpy ( rname57 , <STR_LIT> ) ; strcpy ( rname58 , <STR_LIT> ) ; strcpy ( rname59 , <STR_LIT> ) ; } if ( arc_tp_regno != - <NUM_LIT> ) fixed_regs [ arc_tp_regno ] = call_used_regs [ arc_tp_regno ] = <NUM_LIT> ; if ( TARGET_MULMAC_32BY16_SET ) { fix_start = MUL32x16_REG ; fix_end = fix_end > R57_REG ? fix_end : R57_REG ; strcpy ( rname56 , TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; strcpy ( rname57 , TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; } for ( regno = fix_start ; regno <= fix_end ; regno ++ ) { if ( ! fixed_regs [ regno ] ) warning ( <NUM_LIT> , <STR_LIT> , regno ) ; fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( TARGET_RF16 ) { for ( i = R4_REG ; i <= R9_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; for ( i = R16_REG ; i <= R25_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; } if ( TARGET_HS ) for ( regno = R1_REG ; regno < R32_REG ; regno += <NUM_LIT> ) arc_hard_regno_modes [ regno ] = S_MODES ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( i < ILINK1_REG ) { if ( ( i <= R3_REG ) || ( ( i >= R12_REG ) && ( i <= R15_REG ) ) ) arc_regno_reg_class [ i ] = ARCOMPACT16_REGS ; else arc_regno_reg_class [ i ] = GENERAL_REGS ; } else if ( i < LP_COUNT ) arc_regno_reg_class [ i ] = GENERAL_REGS ; else arc_regno_reg_class [ i ] = NO_REGS ; arc_regno_reg_class [ CC_REG ] = NO_REGS ; arc_regno_reg_class [ FRAME_POINTER_REGNUM ] = GENERAL_REGS ; arc_regno_reg_class [ ARG_POINTER_REGNUM ] = GENERAL_REGS ; if ( TARGET_DPFP ) for ( i = R40_REG ; i < R44_REG ; ++ i ) { arc_regno_reg_class [ i ] = DOUBLE_REGS ; if ( ! TARGET_ARGONAUT_SET ) CLEAR_HARD_REG_BIT ( reg_class_contents [ GENERAL_REGS ] , i ) ; } else { arc_regno_reg_class [ R40_REG ] = ALL_REGS ; arc_regno_reg_class [ R41_REG ] = ALL_REGS ; arc_regno_reg_class [ R42_REG ] = ALL_REGS ; arc_regno_reg_class [ R43_REG ] = ALL_REGS ; fixed_regs [ R40_REG ] = <NUM_LIT> ; fixed_regs [ R41_REG ] = <NUM_LIT> ; fixed_regs [ R42_REG ] = <NUM_LIT> ; fixed_regs [ R43_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R40_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R42_REG ] = <NUM_LIT> ; } if ( TARGET_SIMD_SET ) { gcc_assert ( ARC_FIRST_SIMD_VR_REG == <NUM_LIT> ) ; gcc_assert ( ARC_LAST_SIMD_VR_REG == <NUM_LIT> ) ; for ( i = ARC_FIRST_SIMD_VR_REG ; i <= ARC_LAST_SIMD_VR_REG ; i ++ ) arc_regno_reg_class [ i ] = SIMD_VR_REGS ; gcc_assert ( ARC_FIRST_SIMD_DMA_CONFIG_REG == <NUM_LIT>


<s> return __builtin_mve_vcvtnq_m_sv8hi ( __inactive ,


<s> if ( errorToBool ( StatusOrErr . takeError ( ) ) || * StatusOrErr != APFloat :: opOK ) llvm_unreachable ( <STR_LIT> ) ; if ( getFPImm ( ) . bitwiseIsEqual ( RealVal ) ) return DiagnosticPredicateTy


<s> split_double ( src , & words [ <NUM_LIT> ] , & words [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , words [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , words [ <NUM_LIT> ] ) ) ; } } else if ( src_code == REG && dest_code == MEM ) { rtx addr = XEXP ( dest , <NUM_LIT> ) ; rtx src0 ; rtx src1 ; gcc_assert ( GET_CODE ( addr ) == REG ) ; src0 = operand_subword ( src , <NUM_LIT> , TRUE , mode ) ; src1 = operand_subword ( src , <NUM_LIT> , TRUE , mode ) ; emit_move_insn ( adjust_address ( dest , SImode , <NUM_LIT> ) , src0 ) ; if ( REGNO ( addr ) == STACK_POINTER_REGNUM || REGNO ( addr ) == FRAME_POINTER_REGNUM ) emit_insn ( gen_rtx_SET ( adjust_address ( dest , SImode , UNITS_PER_WORD ) , src1 ) ) ; else { rtx new_mem ; rtx scratch_reg_r0 = gen_rtx_REG ( SImode , <NUM_LIT> ) ; emit_insn ( gen_movsi_internal ( scratch_reg_r0 , addr ) ) ; emit_insn ( gen_addsi_small_int ( scratch_reg_r0 , scratch_reg_r0 , GEN_INT ( UNITS_PER_WORD )


<s> ( void ) MaskTySize ; assert ( ( MaskTySize == <NUM_LIT> || MaskTySize == <NUM_LIT> ) && <STR_LIT> ) ; SmallBitVector UndefElts ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , ElSize , UndefElts , RawMask ) ) return ; unsigned NumElts = RawMask . size ( ) ; unsigned NumEltsPerLane = <NUM_LIT> / ElSize ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Selector = RawMask [ i ] ; unsigned MatchBit = ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; if ( ( M2Z & <NUM_LIT> ) != <NUM_LIT> && MatchBit != ( M2Z & <NUM_LIT> ) ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } int Index = i & ~ ( NumEltsPerLane - <NUM_LIT> ) ; if ( ElSize == <NUM_LIT> ) Index += ( Selector >> <NUM_LIT> ) & <NUM_LIT> ; else Index +=


<s> return <STR_LIT> ( Func -> getCallingConv (


<s> static MCDisassembler * create<ISA_LIT>Disassebler ( const Target & T , const

MCSubtargetInfo & STI , MCContext & Ctx ) {


<s> align = SYMBOL_REF_DECL ( x ) ? DECL_ALIGN_UNIT ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ; return IN_RANGE ( offset , <NUM_LIT> , align -


<s> assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; assert ( Largest + <NUM_LIT> < <NUM_LIT> ) ; result . push_back ( { Largest + <NUM_LIT> , LegalizerInfo :: Unsupported } ) ; result . push_back ( { <NUM_LIT> , LegalizerInfo


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t NumBytes =


<s> bool <ISA_LIT>FPRoundingModePass :: runOnMachineFunction ( MachineFunction & MF ) { for ( MachineFunction :: iterator bbi = MF . begin ( ) , bbe = MF . end ( ) ; bbi != bbe ; ++ bbi ) { MachineBasicBlock & MBB = * bbi ; for ( MachineBasicBlock :: iterator ii = MBB . begin ( ) , ie = MBB . end ( ) ; ii != ie ; ++ ii ) { MachineInstr & MI = * ii ; processInstruction ( MI


<s> void x86_output_aligned_bss ( FILE * file , tree decl ATTRIBUTE_UNUSED , const char * name , unsigned HOST_WIDE_INT size , int align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) named_section ( decl , <STR_LIT> , <NUM_LIT> ) ; else bss_section ( ) ; ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl =


<s> int TargetMBB = getTargetMBB ( * Br ) -> getNumber ( ) ; if ( ThisMBB < TargetMBB ) { for ( int N = ThisMBB + <NUM_LIT> ; N < TargetMBB ; ++ N ) Offset += MBBInfos [


<s> break ; case <STR_LIT> : ExtVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF ( ExtVT ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V2 . getNode ( ) ) ) V2 = getOnesVector ( ExtVT , DAG , DL ) ; else V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; SDValue Shuffle = DAG . getVectorShuffle ( ExtVT , DL , V1 , V2 , Mask ) ; int NumElems = VT . getVectorNumElements ( ) ; if ( ( Subtarget . hasBWI ( ) && ( NumElems >= <NUM_LIT> ) ) || ( Subtarget . hasDQI ( ) && ( NumElems < <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Shuffle ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>BoolRetToIntPass ( PR ) ; initialize<ISA_LIT>ExpandISELPass ( PR ) ; initialize<ISA_LIT>PreEmitPeepholePass ( PR ) ; initialize<ISA_LIT>TLSDynamicCallPass ( PR


<s> uws . next = ptr + <NUM_LIT> ; uws . bytes_left = <NUM_LIT> ; uws . words_left = ( ( * ptr ) >> <NUM_LIT>


<s> if ( SrcReg == DestReg ) return ; if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , RegState :: Define ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ; if ( SrcReg != <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , RegState :: Define ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; KillSrc = true ; } assert ( KillSrc && <STR_LIT>


<s> if ( fndecl == NULL_TREE ) cfun -> machine -> call_abi = ix86_abi ; else cfun -> machine -> call_abi = ix86_function_type_abi ( TREE_TYPE (


<s> MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo (


<s> if ( P . hasDSP ( ) ) ASESet |= <STR_LIT> ; if ( P . hasDSPR2 ( ) ) ASESet |= <STR_LIT> ; if ( P . hasMSA ( ) ) ASESet |= <STR_LIT> ; if ( P . inMicro<ISA_LIT>Mode ( )


<s> bool isUDATA_Type ( ) const { return T


<s> static struct machine_function * tilepro_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > (


<s> if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != <STR_LIT> ) return CS ; } } return


<s> bool runOnMachineFunction ( MachineFunction & F ) override { <ISA_LIT>FI = F . getInfo < <ISA_LIT>FunctionInfo >


<s> return addParam ( <ISA_LIT>_PARAM_TYPE_CALL_RET ,


<s> static inline __ev64_opaque__ __ev_set_ufix32_fs_internal ( __ev64_opaque__ a , float b , uint32_t pos ) { __ev64_opaque__ v ; float other ; other = __ev_get_fs_internal ( a , pos ^ <NUM_LIT> ) ; v = __ev_create_ufix32_fs (


<s> if ( Subtarget . isDarwin ( ) ) return <NUM_LIT> ; unsigned Align = Subtarget . is<ISA_LIT>64


<s> StringRef getPassName ( ) const override { return


<s> if ( MI . isEHLabel ( ) || MI . isCFIInstruction ( ) ) return true ; if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; if ( isSchedBarrier ( MI ) )


<s> return Reg != <NUM_LIT> && ! TargetRegisterInfo :: isStackSlot ( Reg ) && TargetRegisterInfo :: isVirtualRegister (


<s> if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , false , false , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr


<s> new GOTPLTEntry ( <NUM_LIT> , m_SectionData ) ; new GOTPLTEntry ( <NUM_LIT>


<s> return <STR_LIT> :: getSGPRAllocGranule (


<s> if ( MF -> getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { EmitNop ( Ctx , * OutStreamer , <NUM_LIT> , getSubtargetInfo ( ) ) ; return ; } MCSymbol * fentry = Ctx . getOrCreateSymbol ( <STR_LIT> ) ; const MCSymbolRefExpr * Op = MCSymbolRefExpr :: create ( fentry , MCSymbolRefExpr :: VK_PLT , Ctx ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT>

) . addExpr ( Op ) , getSubtargetInfo ( ) ) ;


<s> mips16_lay_out_constants ( true ) ; if ( mips_cfg_in_reorg ( ) ) { mips_df_reorg ( ) ; free_bb_for_insn (


<s> return ( TARGET_EXPLICIT_RELOCS && mips_symbolic_constant_p ( x , & symbol_type )


<s> return CreateReg ( Index , RegKind_FCC , RegInfo ,


<s> MachineInstrBuilder MIB ( * MF , newInstr ) ; MIB . addReg ( dstReg , RegState :: Define ) ; MIB . addReg ( src1Reg ) ; MIB . addReg ( src2Reg ) ; blk -> insert ( instrPos , newInstr


<s> static bool LessOrEqualTypeSize ( Value * V


<s> bool isInstAddr ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags &


<s> static void PlaceMarkers ( MachineFunction & MF , const MachineLoopInfo & MLI , const <ISA_LIT>InstrInfo & TII , MachineDominatorTree & MDT , <ISA_LIT>FunctionInfo & MFI ) { SmallVector < MachineBasicBlock * , <NUM_LIT> > ScopeTops ( MF . getNumBlockIDs ( ) + <NUM_LIT> ) ; DenseMap < const MachineInstr * , MachineInstr * > LoopTops ; DenseMap < const MachineInstr * , MachineInstr * > BlockTops ; for ( auto & MBB : MF ) { PlaceLoopMarker ( MBB , MF , ScopeTops , LoopTops , TII , MLI ) ; PlaceBlockMarker ( MBB , MF , ScopeTops , BlockTops , LoopTops , TII , MLI , MDT , MFI ) ; } SmallVector < const MachineBasicBlock * , <NUM_LIT> > Stack ; for ( auto & MBB : reverse ( MF ) ) { for ( auto & MI : reverse ( MBB ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ScopeTops [ Stack . back ( ) -> getNumber ( ) ] -> getNumber ( ) <= MBB . getNumber ( ) && <STR_LIT> ) ; Stack . pop_back ( ) ; break ; case <STR_LIT> : assert ( Stack . back ( ) == & MBB && <STR_LIT> ) ; Stack . pop_back (


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_ostream & OS )


<s> return ( __m256i ) __builtin_ia32_cvttpd2udq512_mask ( ( __v8df ) __A , ( __v8si ) __W , (


<s> static void nds32_relax_group ( void ) { rtx_insn * insn ; compute_bb_for_insn ( ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_insn_rescan_all ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_active_insn ( insn ) ; insn ; insn = next_active_insn ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_sethi && nds32_symbolic_operand ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) , SImode ) && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ) ) nds32_group_insns ( insn ) ; else if ( recog_memoized ( insn ) == CODE_FOR_tls_ie ) nds32_group_tls_insn ( insn ) ; else if ( TARGET_FPU_SINGLE && recog_memoized ( insn ) == CODE_FOR_move_addr && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ) ) { nds32_group_float_insns ( insn ) ; } } else if ( CALL_P ( insn ) && recog_memoized ( insn ) == CODE_FOR_tls_desc ) { nds32_group_tls_insn ( insn ) ; } } df_insn_rescan_all ( ) ; df_finish_pass ( false ) ; free_dominance_info (


<s> const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . createTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: createAdd ( Base , Expr , Ctx ) ; } const MCExpr * Sym = nullptr ; if ( AllowTLS && getLexer ( ) . is ( AsmToken :: Colon ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; StringRef Name = Parser . getTok ( ) . getString ( ) ; if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSGD ; else if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSLDM ; else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = Parser . getTok ( ) . getString ( ) ; Sym = MCSymbolRefExpr :: create ( Ctx . getOrCreateSymbol ( Identifier ) , Kind , Ctx ) ; Parser . Lex ( ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; if ( AllowTLS ) Operands . push_back ( <ISA_LIT>Operand :: createImmTLS ( Expr , Sym , StartLoc , EndLoc ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; return MatchOperand_Success


<s> assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( SrcBytes && Alignment && Alignment < SrcBytes ) Cost *= ( SrcBytes / Alignment ) ; return Cost


<s> assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . getSize ( ) == <NUM_LIT>


<s> int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; if ( needsStackRealignment ( MF ) && MFI -> hasVarSizedObjects ( ) ) return true ; return


<s> default : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) return DW_EH_PE_pcrel | ( Model ==

CodeModel :: Small ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8 ) ;


<s> for ( auto & I : AllocasToInstrument ) { const memtag :: AllocaInfo & Info = I . second ; AllocaInst * AI = Info . AI ; if ( ! PrologueBB ) { PrologueBB = AI -> getParent ( ) ; continue ; } PrologueBB = DT -> findNearestCommonDominator ( PrologueBB , AI -> getParent ( ) ) ; } assert ( PrologueBB


<s> } else { unsigned OffsetReg = <STR_LIT> ; unsigned OffsetLo = ( unsigned ) ( Offset & <NUM_LIT> ) ; unsigned OffsetHi = ( unsigned ) ( ( Offset & <NUM_LIT> ) >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( OffsetLo ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( OffsetHi ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , OffsetReg ) . addReg ( OffsetReg ) . addImm ( OffsetHi ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } return OffsetReg


<s> SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> )


<s> if ( I . second . empty ( ) ) continue ; HasNE = true ; break ; } if ( ! DefEx || HasNE ) { auto IsEmpty = [ ] ( const IFRecordWithRegSet & IR ) -> bool { return IR . second . empty ( ) ; } ; llvm :: erase_if ( LL , IsEmpty ) ; } else { IFRecord MaxIF = LL [ <NUM_LIT> ] . first ; for ( unsigned i = <NUM_LIT> , n = LL . size ( ) ; i < n ; ++ i ) { const IFRecord & IF = LL [ i ] . first ; unsigned M0 = BaseOrd [ MaxIF . SrcR ] , M1 = BaseOrd [ MaxIF . InsR ] ; unsigned R0 = BaseOrd [ IF . SrcR ] , R1 = BaseOrd [ IF . InsR ] ; if ( M0 > R0 )


<s> } if ( mode == SDmode ) return true ; } else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; return


<s> <ISA_LIT>TargetStreamer & <ISA_LIT>AsmPrinter :: getTargetStreamer ( ) { return static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( )


<s> return ( __m64 ) __builtin_ia32_phsubw ( ( __v4hi ) __X , ( __v4hi )


<s> static __inline qword si_frsqest ( qword a ) { return ( ( qword ) ( vec_rsqrte ( ( vec_float4 ) (


<s> if ( MV55 ) return <STR_LIT> ; if ( MV60 ) return <STR_LIT> ; if ( MV62 ) return <STR_LIT> ; if ( MV65 ) return <STR_LIT> ; return <STR_LIT>


<s> assert ( ( Kind == k_RegList ) && <STR_LIT> ) ; return * ( RegList . List


<s> MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new Darwin<ISA_LIT>AsmBackend ( T , TT , CS ) ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return new <ISA_LIT>WinCOFFAsmBackend ( T , TT ) ; case Triple :: ELF : assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , TT , OSABI


<s> if ( Op0 . getValueType ( ) != <STR_LIT> && Op0 . getValueType ( ) != <STR_LIT> && ! DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) && ! Subtarget -> isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; } SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl ,


<s> ++ iterBlk , ++ i ) { os << <STR_LIT> << ( * iterBlk ) -> getNumber ( ) ; os << <STR_LIT> << getSCCNum ( * iterBlk ) << <STR_LIT> << ( * iterBlk ) -> size ( ) << <STR_LIT> ; if ( i != <NUM_LIT> && i % <NUM_LIT> == <NUM_LIT> ) { os << <STR_LIT> ; } else


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) || FuncInfo -> usesTOCBasePtr ( ) || MF . hasInlineAsm ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; } if ( TM . is<ISA_LIT>64 ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> needsFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; bool IsPositionIndependent = TM . isPositionIndependent ( ) ; if ( hasBasePointer ( MF ) ) { if ( Subtarget . isSVR4ABI ( ) && ! TM . is<ISA_LIT>64 ( ) && IsPositionIndependent ) markSuperRegs ( Reserved , <STR_LIT> ) ; else markSuperRegs ( Reserved


<s> mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case E_V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case E_V16HFmode : extract = gen_avx_vextractf128v16hf ; mode = V8HFmode ; break ; case E_V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode


<s> if ( ReturnAddrIndex == <NUM_LIT> ) { uint64_t SlotSize = TD -> getPointerSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , true , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex ,


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void * New ) { llvm_report_error ( <STR_LIT>


<s> LSDASection = NULL ; } AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> , SectionKind


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model >


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S , OS ) ; return S


<s> machine_mode dest_mode = GET_MODE ( dest ) ; enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; mask = spu_emit_vector_compare ( rcode , cc_op0 , cc_op1 , dest_mode ) ; emit_insn ( gen_selb ( dest , op2 , op1 , mask


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc (


<s> Type * DestTy = I -> getType ( ) ; Value * Op = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Op -> getType ( ) ; EVT SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; EVT DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( Op ) ; unsigned ResultReg ; if ( SrcVT == <STR_LIT> ) { uint64_t Mask = <NUM_LIT> ; switch ( DestVT . SimpleTy


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O ,


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { SMLoc Start = getLexer ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( Name , Start , Start ) ) ; bool First = true ; while ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ! First ) { eatComma ( ) ; } else { First = false ; } auto MatchResult = MatchOperandParserImpl ( Operands , Name ) ; if ( MatchResult == MatchOperand_Success )