<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT , getFeatureBits ( ) ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { AS = <STR_LIT> (


<s> if ( std :: is_same < int16_t , std :: make_signed_t < T >> :: value ) return IsImm8 || IsImm16 ||


<s> if ( prob > ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != PC ) lab = XEXP ( src , <NUM_LIT> ) ; else if ( prob < ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != PC ) lab = XEXP ( src , <NUM_LIT> ) ; } if ( lab ) { if ( GET_CODE ( lab ) == RETURN ) return gen_rtx_REG ( SImode , LINK_REGISTER_REGNUM ) ; return lab ; } return <NUM_LIT> ; } return src ; } else if ( CALL_P ( branch ) ) { rtx call ; if ( GET_CODE ( PATTERN ( branch ) ) != PARALLEL ) abort ( ) ; call = XVECEXP ( PATTERN ( branch ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) != CALL ) abort ( ) ; return XEXP ( XEXP ( call ,


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { assert ( false && <STR_LIT> )


<s> rtx val = GEN_INT ( size * direction ) ; rtx insn ; insn = ( TARGET_BIG ? gen_addpsi3 : gen_addhi3 ) ( stack_pointer_rtx , stack_pointer_rtx , val ) ; emit_insn (


<s> RestoreMBB -> setHasAddressTaken ( ) ; SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; Register LabelReg = prepareMBB ( * MBB , MachineBasicBlock :: iterator ( MI ) , RestoreMBB , DL ) ; const <ISA_LIT>FrameLowering * TFI = Subtarget -> getFrameLowering ( ) ; if ( TFI -> hasBP ( * MF ) ) { MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( BufReg ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB . setMemRefs ( MMOs ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addReg ( LabelReg , getKillRegState ( true ) ) ; MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * ThisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( RestoreMBB ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; MIB . addRegMask ( RegInfo -> getNoPreservedMask ( ) ) ; ThisMBB -> addSuccessor ( MainMBB ) ; ThisMBB -> addSuccessor (


<s> if ( PredicateFtor && ! PredicateFtor ( MF . getFunction ( ) ) ) return false ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( STI -> isThumb1Only ( ) || STI -> prefers32BitThumb ( ) ) return false ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; OptimizeSize = MF . getFunction ( ) . hasOptSize ( ) ; MinimizeSize = STI -> hasMinSize (


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM ,


<s> Counts . Named . LGKM = <STR_LIT> ( ISA , Imm ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Counts . Array [ i ] <= LastIssued . Array [ i ] ) WaitOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; else WaitOn . Array [ i ] = <NUM_LIT> ; } increaseCounters ( DelayedWaitOn , WaitOn )


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT>


<s> if ( ( V_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) ) return <NUM_LIT> ; if ( ( HILO_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return <NUM_LIT> ; if ( HILO_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) return <NUM_LIT> ; if ( ( HILO_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) || ( V_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( isInt < <NUM_LIT> > ( Val ) ) { int64_t Hi20 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; if ( Hi20 ) Res . push_back ( Inst ( <STR_LIT> , Hi20 ) ) ; if ( Lo12 || Hi20 == <NUM_LIT> ) { unsigned AddiOpc = ( IsRV64 && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( Inst ( AddiOpc , Lo12 ) ) ; } return ; } assert ( IsRV64 && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( ( uint64_t ) Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , IsRV64 , Res ) ; Res . push_back ( Inst ( <STR_LIT> , ShiftAmount ) ) ; if ( Lo12 ) Res . push_back ( Inst


<s> SDValue BC0 = peekThroughOneUseBitcasts ( Op0 ) ; SDValue BC1 = peekThroughOneUseBitcasts ( Op1 ) ; return <STR_LIT> ( BC0 . getNode ( ) ) || <STR_LIT> ( BC1 . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( Opcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! N -> isOnlyUserOf ( Src . getNode ( ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Src . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Src . getOperand ( <NUM_LIT> ) ; if ( TLI . isOperationLegalOrPromote ( Opcode , VT ) && IsRepeatedOpOrFreeTruncation ( Op0 , Op1 ) ) return TruncateArithmetic ( Op0 , Op1 ) ; break ; } case <STR_LIT> : if ( SrcVT . getScalarType ( ) == <STR_LIT> && TLI . isOperationLegal ( Opcode , VT ) && ! TLI . isOperationLegal ( Opcode , SrcVT ) ) return TruncateArithmetic ( Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue Op0 = Src .


<s> return ( __m128d ) __builtin_ia32_xorpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , ( __v2df ) _mm_setzero_pd ( ) ,


<s> } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] :


<s> BuildMI ( MBB , MBBI , dl , TII . get

( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItem item = Contents [ i ] ; Streamer . EmitULEB128IntValue (


<s> int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC ,


<s> case E_QImode : case E_HImode : case E_SImode : case E_DImode : return true ; case


<s> sched_no_dce = false ; rtx_insn * * call_labels = XCNEWVEC ( rtx_insn * , get_max_uid ( ) + <NUM_LIT> ) ; reorg_split_calls ( call_labels ) ; if ( c6x_flag_schedule_insns2 ) { FOR_EACH_BB_FN ( bb , cfun ) if ( ( bb -> flags & BB_DISABLE_SCHEDULE ) == <NUM_LIT> ) assign_reservations ( BB_HEAD ( bb ) , BB_END ( bb ) ) ; } if ( c6x_flag_var_tracking ) { timevar_push ( TV_VAR_TRACKING ) ; variable_tracking_main ( ) ; timevar_pop ( TV_VAR_TRACKING ) ; } reorg_emit_nops ( call_labels )


<s> if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s1_d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; return MCDisassembler :: Success


<s> EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT ,


<s> void setSCEVValue ( const SCEV * value


<s> void WinEHStatePass :: insertStateNumberStore ( Value * ParentRegNode , Instruction * IP , int State ) { IRBuilder < > Builder


<s> if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) getTargetStreamer ( ) -> getPALMetadata ( ) -> readFromIR ( M ) ; if ( isHsaAbiVersion3Or4 ( getGlobalSTI ( ) ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ; IsaVersion Version = getIsaVersion ( getGlobalSTI ( ) -> getCPU ( )


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( ! setTargetShuffleZeroElements ( Op , Mask , Ops ) ) if ( ! getFauxShuffleMask ( Op , Mask , Ops ) ) return false ; int NumElts = Mask . size ( ) ; bool Op0InUse = any_of ( Mask , [ NumElts ] ( int Idx ) { return <NUM_LIT> <= Idx &&


<s> else IsValid = isUInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr ::

VK_<ISA_LIT>_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ) ;


<s> __builtin_ia32_aand64 ( ( long long * ) __A ,


<s> assert ( ( ( ! isGP64bit ( ) && isABI_O32 ( ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( isFP64bit ( ) && ! has<ISA_LIT>64 ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( inAbs2008Mode ( ) && has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; assert ( inAbs2008Mode ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( )


<s> static bool matchLogicBlend ( SDNode * N , SDValue & X , SDValue & Y , SDValue & Mask ) { if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand (


<s> if ( Index ) O << '%' << getRegisterName ( Index ) << ',' ; O << '%' << getRegisterName ( Base ) << ')' ; } else assert ( ! Index && <STR_LIT>


<s> SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue VIdx = Node -> getOperand ( <NUM_LIT> ) ; SDValue VMask = Node -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Scale = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! Scale ) return nullptr ; SDVTList VTs = CurDAG -> getVTList ( VSrc . getValueType ( ) , VSrc . getValueType ( ) , <STR_LIT> ) ; SDLoc DL ( Node ) ; SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) , DL ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , DL , VTs , Ops ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) ,


<s> setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s>
unsigned
Rot
=
<STR_LIT>
(
V
)
;
if
(
Rot
)
{
O
<<
<STR_LIT>
<<
Imm
<<
<STR_LIT>
<<
Rot
;
if
(
VerboseAsm
)
O
<<
' '
<<
TAI
->
getCommentString
(
)
<<
' '
<<
(
int
)
<STR_LIT>
(
Imm
,
Rot
)
;
}


<s> sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; unsigned LabelReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned LabelReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned BufReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned FP = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> ) . addReg ( FP ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg , RegState :: Define ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( LabelReg2 , RegState :: Define ) . addReg ( LabelReg , RegState :: Kill ) . addMBB ( restoreMBB , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( RegSize ) . addReg ( LabelReg2 , RegState :: Kill ) ; const unsigned <ISA_LIT> = <STR_LIT> ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <ISA_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( BufReg ) . addImm ( <NUM_LIT> * RegSize ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) . addImm ( <STR_LIT> ) ; MIB = BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mainMBB ) . addImm ( <STR_LIT> ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( restoreMBB ) ; MIB = BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( mainDstReg , RegState :: Define

) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( MI . killsRegister ( Reg , TRI ) ) return ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , Reg ) . addReg ( Reg ,


<s> unsigned Opc = DefMI . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; assert ( DefMI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; RegMO = & DefMI . getOperand ( <NUM_LIT> ) ; ImmMO = & DefMI . getOperand


<s> uint32_t <ISA_LIT>MCCodeEmitter :: SMRDmemriEncode ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixup ) const { uint32_t Encoding ; const MCOperand & OffsetOp = MI . getOperand ( OpNo + <NUM_LIT> ) ; assert ( OffsetOp . isImm (


<s> return ( uint32x2_t ) __builtin_neon_vrhadduv2si ( ( int32x2_t ) __a , ( int32x2_t )


<s> MCInst <ISA_LIT>InstrInfo :: getNop ( ) const { MCInst Nop ; Nop . setOpcode


<s> CommentString = <STR_LIT> ; SupportsDebugInformation = true


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty ( Op ) ,


<s> static bool frv_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( mode == BLKmode ) return true ; if ( type == NULL )


<s> if ( N -> getNumOperands ( ) == <NUM_LIT> ) if ( SDValue RV = PerformVMOVDRRCombine ( N , DAG ) ) return RV ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> || ! hasNormalLoadOperand ( N ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumElts = VT .


<s> gcc_assert ( REG_P ( slot ) ) ; res = gen_reg_rtx (


<s> return ( __m512i ) __builtin_ia32_vpdpbusd_v16si_mask ( ( __v16si ) __A , ( __v16si ) __C , (


<s> if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) ) return false ; return true


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectAddrSpaceCast ( AddrSpaceCastSDNode * ASC ) const { SDValue Cast ( ASC , <NUM_LIT> ) ; unsigned DstAS = ASC -> getDestAddressSpace ( ) ; unsigned SrcAS = ASC -> getSrcAddressSpace ( ) ; EVT DestVT = ASC -> getValueType ( <NUM_LIT> ) ; EVT SrcVT = ASC -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; bool Src32 = ( SrcVT == <STR_LIT> ) ; bool Dst32 = ( DestVT == <STR_LIT> ) ; unsigned Opcode ; SDValue Segment , NoNull , Ptr , DestType , SrcType ; SDLoc SL ( ASC ) ; if ( SrcAS == <STR_LIT> ) { if ( Src32 && Dst32 ) Opcode = <STR_LIT> ; else if ( Src32 && ! Dst32 ) llvm_unreachable ( <STR_LIT> ) ; else if ( ! Src32 && Dst32 ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; Segment = CurDAG -> getTargetConstant ( DstAS , SL , <STR_LIT> ) ; SelectAddrSpaceCastCommon ( * ASC , NoNull , Ptr , DestType , SrcType ) ; } else if ( DstAS == <STR_LIT> ) { if ( Src32 && Dst32 ) Opcode = <STR_LIT> ; else if ( Src32 && ! Dst32 ) Opcode = <STR_LIT> ; else if ( ! Src32 && Dst32 ) llvm_unreachable ( <STR_LIT> ) ; else Opcode = <STR_LIT> ; Segment = CurDAG -> getTargetConstant ( SrcAS , SL , <STR_LIT> ) ; SelectAddrSpaceCastCommon ( * ASC , NoNull , Ptr , DestType ,


<s> void <ISA_LIT>InstPrinter :: printARIDMem ( const MCInst * MI , int


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM


<s> bool <ISA_LIT>PacketizerList :: demoteToDotOld ( MachineInstr & MI ) { int NewOpcode = HII -> getDotOldOp ( MI . getOpcode ( ) ) ; MI . setDesc ( HII -> get ( NewOpcode ) ) ; return


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const

MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override {


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB .


<s> epilogue_completed = <NUM_LIT> ; no_new_pseudos = <NUM_LIT> ; reset_block_changes ( ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; else this = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; emit_insn ( TARGET_32BIT ? gen_addsi3 ( this , this , delta_rtx ) : gen_adddi3 ( this , this , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this ) ) ; if ( ( ( unsigned HOST_WIDE_INT ) vcall_offset ) + <NUM_LIT> >= <NUM_LIT> ) { emit_insn ( TARGET_32BIT ? gen_addsi3 ( tmp , tmp , vcall_offset_rtx ) : gen_adddi3 ( tmp , tmp , vcall_offset_rtx ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; } else { rtx loc = gen_rtx_PLUS ( Pmode , tmp , vcall_offset_rtx ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , loc ) ) ; } emit_insn ( TARGET_32BIT ? gen_addsi3 ( this , this , tmp ) : gen_adddi3 ( this , this , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSetVL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVMSET_VMCLR ( MBB , MBBI , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandVSPILL ( MBB , MBBI ) ; case <STR_LIT> : case <STR_LIT> : case


<s> BuildMI ( * BB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT>

) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> void <ISA_LIT>FunctionInfo :: initWARegs ( MachineRegisterInfo & MRI ) { assert ( WARegs . empty ( ) ) ; unsigned Reg = UnusedReg


<s> std :: shared_ptr < msgpack :: MapNode > MetadataStreamerV3 :: getHSAKernelProps ( const MachineFunction & MF , const <ISA_LIT>ProgramInfo & ProgramInfo ) const { const GCNSubtarget & STM = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>MachineFunctionInfo & MFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Function & F = MF . getFunction ( ) ; auto HSAKernelProps = std :: make_shared < msgpack :: MapNode > ( ) ; auto & Kern = * HSAKernelProps ; unsigned MaxKernArgAlign ; Kern [ <STR_LIT> ] = std :: make_shared < msgpack :: ScalarNode > ( STM . getKernArgSegmentSize ( F , MaxKernArgAlign ) ) ; Kern [ <STR_LIT> ] = std :: make_shared < msgpack :: ScalarNode > ( ProgramInfo . LDSSize ) ; Kern [ <STR_LIT> ] = std :: make_shared < msgpack :: ScalarNode > ( ProgramInfo . ScratchSize ) ; Kern [ <STR_LIT> ] = std :: make_shared < msgpack :: ScalarNode > ( std :: max ( uint32_t ( <NUM_LIT> ) , MaxKernArgAlign ) ) ; Kern [ <STR_LIT> ] = std :: make_shared < msgpack :: ScalarNode >


<s> } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ; const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ; assert ( isa < Constant > ( Sym ) && <STR_LIT> ) ; const Value * Operand = cast < Constant > ( Sym ) -> getOperand ( <NUM_LIT> ) ; if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Operand ) ) { assert ( GV -> hasInitializer ( ) && <STR_LIT> ) ; const Constant * Initializer = GV -> getInitializer ( ) ; Operand = Initializer ; } assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; std :: string ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( VarMap . find ( ReflectArg ) != VarMap . end ( ) ) { ReflectVal = VarMap [ ReflectArg ]


<s> unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( isHReg ( SrcReg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc =


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { unsigned Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return ; unsigned NumBytes = getFixupKindNumBytes ( Kind ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Asm , Fixup , Target , Value , IsResolved , Ctx , STI ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( Endian ==


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegsViaCopy ( const MachineFunction * MF ) const { return nullptr


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc =


<s> SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo , Hi ) ; } if ( Model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue TGATLS = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; SDValue TPOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA , GOTPtr ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TPOffset , TGATLS ) ; } if ( Model == TLSModel :: GeneralDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { setUsesTOCBasePtr ( DAG ) ; SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { if ( picLevel == PICLevel :: SmallPIC ) GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; else GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA , TGA ) ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <NUM_LIT> ) ; SDValue GOTPtr ; if ( is64bit


<s> inline static bool isGlobalStubReference ( unsigned char TargetFlag ) { switch ( TargetFlag )


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MCPhysReg * CSRegs = MRI . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg ( CSRegs [ i ] ) ; for ( unsigned Reg : RC ) { if ( LiveRegs . available ( MRI , Reg


<s> if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( mode ) ) flags |= FLAG_FP ; if ( ! flag_trapping_math ) flags &= ~ FLAG_RAISE_FP_EXCEPTIONS ; return flags


<s> MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ; I . eraseFromParent


<s> unsigned Align = MFI . getObjectAlignment ( FrameIdx ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , Align ) ; unsigned LoadOp = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) { switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; case <NUM_LIT> : LoadOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) && <STR_LIT> ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : LoadOp =


<s> void <ISA_LIT>CFGStackify :: unregisterScope ( MachineInstr * Begin ) { assert ( BeginToEnd . count ( Begin ) ) ; MachineInstr * End = BeginToEnd [ Begin ] ; assert ( EndToBegin . count ( End ) ) ; BeginToEnd . erase ( Begin ) ; EndToBegin . erase ( End ) ; MachineBasicBlock * EHPad = TryToEHPad . lookup ( Begin ) ; if ( EHPad ) { assert ( EHPadToTry . count ( EHPad ) ) ; TryToEHPad . erase ( Begin ) ; EHPadToTry . erase (


<s> if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Basic ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Basic ; return <NUM_LIT> * TTI :: TCC_Basic ; } return <NUM_LIT> *


<s> SDValue <ISA_LIT>TargetLowering :: LowerREADCYCLECOUNTER ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VTs


<s> case MCExpr :: Constant : OS << cast < MCConstantExpr > ( Expr ) . getValue ( ) ; return ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SRE = cast < MCSymbolRefExpr > ( Expr ) ; const MCSymbol & Sym = SRE . getSymbol ( ) ; Sym . print ( OS , MAI ) ; return ; } case MCExpr :: Unary : { const MCUnaryExpr & UE = cast < MCUnaryExpr > ( Expr ) ; switch ( UE . getOpcode ( ) ) { case MCUnaryExpr :: LNot : OS << '!' ; break ; case MCUnaryExpr :: Minus : OS << '-' ; break ; case MCUnaryExpr :: Not : OS << '~' ; break ; case MCUnaryExpr :: Plus : OS << '+' ; break ; } printMCExpr ( * UE . getSubExpr ( ) , OS ) ; return ; } case MCExpr :: Binary : { const MCBinaryExpr & BE = cast < MCBinaryExpr > ( Expr ) ; if ( isa < MCConstantExpr > ( BE . getLHS ( ) ) || isa < MCSymbolRefExpr > ( BE . getLHS ( ) ) || isa < <ISA_LIT>GenericMCSymbolRefExpr > ( BE . getLHS ( ) ) ) { printMCExpr ( * BE . getLHS ( ) , OS ) ; } else { OS << '(' ; printMCExpr ( * BE . getLHS ( ) , OS ) ; OS << ')' ; } switch ( BE . getOpcode ( ) ) { case MCBinaryExpr :: Add : if ( const MCConstantExpr * RHSC = dyn_cast < MCConstantExpr > ( BE . getRHS ( ) ) ) { if ( RHSC -> getValue ( ) < <NUM_LIT> ) { OS << RHSC -> getValue ( ) ; return ; } } OS << '+'


<s> int param_size = csky_num_arg_regs ( mode , type ) ; if ( * pcum + param_size > CSKY_NPARM_REGS ) * pcum = CSKY_NPARM_REGS ; else * pcum +=


<s> return false ; } StringRef Option = Tok . getIdentifier ( ) ; if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement (


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveCpload ( unsigned RegNo ) { if ( ! Pic || ( isN32 ( ) || isN64 ( ) ) ) return ; StringRef SymName ( <STR_LIT> ) ; MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCSymbol * GP_Disp = MCA . getContext ( ) . GetOrCreateSymbol ( SymName ) ; MCA . getOrCreateSymbolData ( * GP_Disp ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext (


<s> static rtx frv_expand_store_builtin ( enum insn_code icode , tree call ) { rtx op0 = frv_read_argument ( call , <NUM_LIT> ) ; rtx op1 = frv_read_argument ( call , <NUM_LIT> ) ; rtx cookie = frv_io_address_cookie ( op0


<s> case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand (


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getTargetLowering ( ) ) { initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry (


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . BaseRegNum == <STR_LIT> ) return false ; if ( ! Memory . OffsetImm ) return false ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val == std :: numeric_limits < int32_t > :: min ( ) ) || (

Val > - <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> static DecodeStatus DecodeCPURegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg


<s> static const int8_t NoopsInSledCount = <NUM_LIT> ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol


<s> return __builtin_aarch64_urshlv2si_uus ( __a ,


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget


<s> set_optab_libfunc ( smul_optab , HFmode , NULL ) ; set_optab_libfunc ( neg_optab , HFmode , NULL ) ; set_optab_libfunc ( sub_optab , HFmode , NULL ) ; set_optab_libfunc ( eq_optab , HFmode , NULL ) ; set_optab_libfunc ( ne_optab , HFmode , NULL ) ; set_optab_libfunc ( lt_optab , HFmode , NULL ) ; set_optab_libfunc ( le_optab , HFmode , NULL ) ; set_optab_libfunc ( ge_optab , HFmode


<s> unsigned <ISA_LIT>RegisterInfo :: getHWRegIndex ( unsigned Reg ) const { return getEncodingValue ( Reg


<s> const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = std :: find_if ( std :: begin ( PrefixEntries ) , std :: end ( PrefixEntries ) , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) ,


<s> MinSize = <NUM_LIT> ; PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass ( ) ? <NUM_LIT>


<s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyEnd ( ) { VRegMapping . clear


<s> return ( Reg == <STR_LIT> || Reg == <STR_LIT> || ( Reg == <STR_LIT> &&


<s> Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New


<s> const LLT Ty = MRI . getType ( Reg ) ; if ( ! Ty . isValid ( ) || Ty . getSizeInBits ( ) != <NUM_LIT> ) return false ; return MRI . getVRegDef ( Reg ) -> getOpcode ( ) != <STR_LIT> && RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID ( )


<s> fprintf ( asm_out_file , <STR_LIT> <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; sec = sec -> next ; } file_end_indicate_exec_stack (


<s> LastUsed = ( Last -> Flags & GepNode :: Used ) ; if ( LastUsed ) break ; NodeChildrenMap :: iterator CF = NCM . find ( Last ) ; LastCN = ( CF != NCM . end ( ) ) ? CF -> second . size ( ) : <NUM_LIT> ; if ( LastCN != <NUM_LIT> ) break ; GepNode * Child = CF -> second . front ( ) ; BasicBlock * ChildB = cast_or_null < BasicBlock > ( Loc [ Child ] ) ; if ( ChildB != nullptr && LastB != ChildB ) break ; Last = Child ; } while ( true ) ; BasicBlock :: iterator InsertAt = LastB -> getTerminator ( ) -> getIterator ( ) ; if ( LastUsed || LastCN > <NUM_LIT> ) { ValueVect Urs ; getAllUsersForNode ( Root , Urs , NCM ) ; BasicBlock :: iterator FirstUse = first_use_of_in_block ( Urs , LastB ) ; if ( FirstUse != LastB -> end ( ) ) InsertAt = FirstUse ; } Value * NewInst = fabricateGEP ( NA , InsertAt , LastB ) ; if ( LastCN > <NUM_LIT> ) { NodeVect & Cs = NCM [ Last ] ; for ( NodeVect :: iterator I = Cs . begin ( ) , E = Cs . end ( ) ; I != E ; ++ I ) { GepNode * CN = * I ; CN -> Flags &= ~ GepNode ::


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = MachO :: GENERIC_RELOC_VANILLA ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + A -> getName ( ) + <STR_LIT> , false ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A_SD -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO ::


<s> static bool pru_valid_const_ubyte_offset ( machine_mode mode , HOST_WIDE_INT offset ) { bool valid = UBYTE_INT ( offset ) ; if ( valid && GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( SImode ) ) valid = UBYTE_INT ( offset + GET_MODE_SIZE ( mode )


<s> if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Amt ) ) if ( auto * AmtSplat = AmtBV -> getConstantSplatNode ( ) ) { APInt ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getSimpleVT ( ) . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ShiftAmt . trunc ( <NUM_LIT> ) . uge ( MaxAmount ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; } return SDValue (


<s> void EmitByte ( uint8_t C , unsigned & CurByte , raw_ostream & OS ) const { OS << ( char ) C ; ++ CurByte


<s> void AMDGPUTTI :: getUnrollingPreferences ( Loop * L , UnrollingPreferences & UP ) const { for ( const BasicBlock * BB : L -> getBlocks ( ) ) { for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP -> getAddressSpace ( ) != <STR_LIT> ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr ) ) ; if ( Alloca ) { UP . Threshold


<s> case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : case <STR_LIT>


<s> if ( ! FuncInfo . StaticAllocaMap . count ( C ) ) return <NUM_LIT> ; assert ( C -> isStaticAlloca ( ) && <STR_LIT> ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII .


<s> if ( N . getOpcode ( ) != <STR_LIT> ) return false ; SDValue VScale = N . getOperand ( <NUM_LIT> ) ; if ( VScale . getOpcode ( ) != <STR_LIT> ) return false ; TypeSize TS = MemVT . getSizeInBits ( ) ; int64_t MemWidthBytes = static_cast < int64_t > ( TS . getKnownMinSize ( ) ) / <NUM_LIT> ; int64_t MulImm = cast < ConstantSDNode > ( VScale . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ( MulImm % MemWidthBytes ) != <NUM_LIT> ) return false ; int64_t Offset = MulImm / MemWidthBytes ; if ( Offset < Min || Offset > Max ) return false ; Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; } OffImm = CurDAG -> getTargetConstant ( Offset , SDLoc ( N ) , <STR_LIT> ) ; return


<s> return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , Flag , MFI . getObjectSize


<s> if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align . reset ( ) ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) , true ) ; if ( Info . memVT == <STR_LIT> ) { Info . memVT = memVTFromAggregate ( CI . getType ( ) ) ; } Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad


<s> if ( ( Subtarget . hasBMI ( ) || Subtarget . hasTBM ( ) ) && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { ConstantSDNode * MaskNode = dyn_cast < ConstantSDNode > ( N1 ) ; ConstantSDNode * ShiftNode = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( MaskNode && ShiftNode ) { uint64_t Mask = MaskNode -> getZExtValue ( ) ; uint64_t Shift = ShiftNode -> getZExtValue ( ) ; if ( isMask_64 ( Mask ) ) { uint64_t MaskSize = countPopulation ( Mask ) ; if ( Shift + MaskSize <= VT . getSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Shift | ( MaskSize << <NUM_LIT> ) , DL , VT ) ) ; } } } return SDValue (


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM


<s> static bool isConditionalBranch ( const MachineInstr & MI ) { return ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) &&

MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ;


<s> if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != <STR_LIT> && FirstInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) return SDValue ( ) ; SDValue Ext1 = FirstInput . getOperand ( <NUM_LIT> ) ; SDValue Ext2 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op


<s> OutStreamer . EmitLabel ( StubLabel ) ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue (


<s> if ( ( SignedDivRem || UnsignedDivRem ) && Args . size ( ) == <NUM_LIT> ) { if ( const Constant * C = dyn_cast < Constant > ( Args [ <NUM_LIT> ] ) ) { const ConstantInt * CVal = ( C -> getType ( ) -> isVectorTy ( ) ? dyn_cast_or_null < const ConstantInt > ( C -> getSplatValue ( ) ) : dyn_cast < const ConstantInt > ( C ) ) ; if ( CVal != nullptr && ( CVal -> getValue ( ) . isPowerOf2 ( ) || ( - CVal -> getValue ( ) ) . isPowerOf2 ( ) ) ) DivRemConstPow2 = true ; else DivRemConst = true ; } } if ( Ty -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned VF = Ty -> getVectorNumElements ( ) ; unsigned NumVectors = getNumVectorRegs ( Ty ) ; if ( Opcode == Instruction :: Shl || Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) { return NumVectors ; } if ( DivRemConstPow2 ) return ( NumVectors * ( SignedDivRem ? SDivPow2Cost : <NUM_LIT> ) ) ; if ( DivRemConst ) return VF * DivMulSeqCost + getScalarizationOverhead ( Ty , Args ) ; if ( ( SignedDivRem || UnsignedDivRem ) && VF > <NUM_LIT> ) return <NUM_LIT> ; if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) { switch ( ScalarBits ) { case <NUM_LIT> : { if ( ST -> hasVectorEnhancements1 ( ) ) return NumVectors ; unsigned ScalarCost = getArithmeticInstrCost ( Opcode , Ty -> getScalarType ( ) ) ; unsigned Cost = ( VF * ScalarCost ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } case <NUM_LIT> : case <NUM_LIT> : return NumVectors ; default : break ; } } if ( Opcode == Instruction


<s> nvptx_assemble_value ( INTVAL ( x ) , size ) ; break ; case CONST : x = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == PLUS ) ; val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; x = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; gcc_fallthrough ( ) ; case SYMBOL_REF : gcc_assert ( size == init_frag . size ) ; if ( init_frag . offset ) sorry ( <STR_LIT> ) ; nvptx_maybe_record_fnsym ( x ) ; init_frag . val = val ; output_init_frag ( x ) ; break ; } return


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) ,

RegInfo -> getSpillAlignment ( * RC ) , false ) ;


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI


<s>
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
unsigned
CSStackSize
=
<NUM_LIT>
;
unsigned
SVECSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
{
auto
RegSize
=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
if
(
<STR_LIT>
.
contains
(
Reg
)
||
<STR_LIT>
.
contains
(
Reg
)
)
SVECSStackSize
+=
RegSize
;
else
CSStackSize
+=
RegSize
;
}
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
unsigned
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
int64_t
SVEStackSize
=
alignTo
(
SVECSStackSize
+
estimateSVEStackObjectOffsets
(
MFI
)
,
<NUM_LIT>
)
;
bool
CanEliminateFrame
=
(
SavedRegs
.
count
(
)
==
<NUM_LIT>
)
&&
!
SVEStackSize
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
SVEStackSize
||
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
UnspilledCSGPR
;
}
if
(
!
ExtraCSSpill
||
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
ExtraCSSpill
)
)
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
<STR_LIT>
;
unsigned
Size
=
TRI
->
getSpillSize
(
RC
)
;
unsigned
Align
=
TRI
->
getSpillAlignment
(
RC
)
;
int
FI
=
MFI
.
CreateStackObject
(
Size
,
Align
,
false
)
;
RS
->
addScavengingFrameIndex


<s> data . ptr = NULL_RTX ; nvptx_propagate ( block , insn , pre_p ? PM_read : PM_write , wprop_gen , & data ) ; if ( data . offset ) { rtx init = gen_rtx_SET ( data .


<s> void <ISA_LIT>InstPrinter :: printPSRFlag ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { auto V = MI -> getOperand ( OpNo ) . getImm ( ) ; ListSeparator LS ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return STI . getFramePointerReg ( ) ; return


<s> vld1q_dup_s16 ( const int16_t * __a ) { return ( int16x8_t ) __builtin_neon_vld1_dupv8hi ( ( const __builtin_neon_hi * )


<s> if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { return Fail ; } return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; } else { if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn48 ; if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) return Fail ; Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; if ( Success == Result ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn16 ; if ( ! readInstruction16 ( Bytes , Address , Size , Insn16 ) ) return Fail ; return decodeInstruction ( DecoderTable16 , Instr , Insn16 , Address , this


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm


<s> if ( errorToBool ( StatusOrErr . takeError ( ) ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( isNegative ) RealVal . changeSign ( ) ; if ( AddFPZeroAsLiteral && RealVal . isPosZero ( ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; } else Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( RealVal , * StatusOrErr == APFloat :: opOK , S , getContext ( ) ) ) ; } Parser . Lex ( ) ; return MatchOperand_Success


<s> unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool hasAtomicRMW = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return ( Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) && hasAtomicRMW

) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } } assert ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) !=

<NUM_LIT> ) V2 = DAG . getUNDEF ( VT ) ;


<s> unsigned A15SDOptimizer :: createImplicitDef ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL ) { Register Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertBefore , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , Out ) ; return


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Default : case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBase ( Table


<s> unsigned Lane = cast < ConstantSDNode > ( N -> getOperand ( Vec0Idx + NumVecs ) ) -> getZExtValue ( ) ; EVT VT = N -> getOperand ( Vec0Idx ) . getValueType ( ) ; bool is64BitVector = VT . is64BitVector ( ) ; EVT VT64 ; if ( is64BitVector ) { VT64 = VT ; VT = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) * <NUM_LIT> ) ; } unsigned OpcodeIndex ; switch ( VT . getScalarType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <NUM_LIT> : OpcodeIndex = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Opc = Opcodes [ OpcodeIndex ] ; SmallVector < EVT , <NUM_LIT> > ResTys ; if ( IsLoad ) { if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc

= getVLDSTRegisterUpdateOpcode ( Opc ) ;


<s> SDValue R600TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; DebugLoc DL = Op . getDebugLoc ( ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Ptr = Op . getOperand ( <NUM_LIT> ) ; SDValue LoweredLoad ; int ConstantBlock = ConstantAddressBlock ( LoadNode -> getAddressSpace ( ) ) ; if ( ConstantBlock > - <NUM_LIT> ) { SDValue Result ; if ( dyn_cast < ConstantExpr > ( LoadNode -> getSrcValue ( ) ) || dyn_cast < Constant > ( LoadNode -> getSrcValue ( ) ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Slots , <NUM_LIT> ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , <NUM_LIT> , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <STR_LIT> ) { return SDValue ( ) ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( getTargetMachine ( ) . getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( VT . isVector ( ) ) { unsigned NumElemVT = VT . getVectorNumElements ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Loads [ <NUM_LIT> ] ; assert ( NumElemVT >= StackWidth && <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElemVT ; ++ i ) { unsigned Channel , PtrIncr


<s> Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) ,

Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ;


<s> MachineInstrBuilder emitInstStore ( unsigned Opc , unsigned SrcReg , unsigned MemReg , int64_t MemOffset ) { return emitInst ( Opc ) . addReg ( SrcReg ) .

addReg ( MemReg ) . addImm ( MemOffset ) ;


<s> case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int Offset = VA . getLocMemOffset ( ) ; assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue SPN = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> ) ; SDValue OffsetN = DAG . getIntPtrConstant ( Offset ) ; OffsetN = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SPN , OffsetN ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , OffsetN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] .


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> static unsigned getStoreRegOpcode ( unsigned SrcReg , const TargetRegisterClass * RC , bool isStackAligned , const <ISA_LIT>Subtarget & STI ) { return getLoadStoreRegOpcode ( SrcReg , RC , isStackAligned ,


<s> Optional < <ISA_LIT>MemOpInfo > <ISA_LIT>MemOpAccess :: getAtomicCmpxchgOrRmwInfo ( const MachineBasicBlock :: iterator & MI ) const { assert ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ; if ( ! ( MI -> mayLoad ( ) && MI -> mayStore ( ) ) ) return None ; if ( MI -> getNumMemOperands ( ) == <NUM_LIT> ) return <ISA_LIT>MemOpInfo ( ) ; return constructFromMIWithMMO (


<s> const LLT PtrTy = MRI -> getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned AS = PtrTy . getAddressSpace ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) return selectGlobalAtomicFadd ( I , I

. getOperand ( <NUM_LIT> ) , I . getOperand ( <NUM_LIT> ) ) ;


<s> int64_t BlockNumber = strtoi ( SectionName . drop_front ( <NUM_LIT> ) ) ; if ( BlockNumber == <NUM_LIT> || BlockNumber == <NUM_LIT> ) return BlockNumber ; } report_fatal_error (


<s> auto Lead = MBB . begin ( ) , E = MBB . end ( ) ; if ( MBB . succ_size ( ) != <NUM_LIT> || Lead == E || ! isEndCF ( * Lead , TRI ) ) continue ; const MachineBasicBlock * Succ = * MBB . succ_begin ( ) ; if ( ! MBB . isLayoutSuccessor ( Succ ) ) continue ; auto I = std :: next ( Lead ) ; for ( ; I != E ; ++ I ) if ( ! TII -> isSALU ( * I ) || I -> readsRegister ( <STR_LIT> , TRI ) ) break ; if ( I != E ) continue ; const auto NextLead = Succ -> begin ( ) ; if ( NextLead == Succ -> end ( ) || ! isEndCF ( * NextLead , TRI ) || ! getOrExecSource ( * NextLead , * TII , MRI ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * Lead << '\n' ) ; auto SaveExec = getOrExecSource ( * Lead , * TII , MRI ) ; unsigned SaveExecReg = getOrNonExecReg ( * Lead , * TII ) ; for ( auto & Op : Lead -> operands ( ) ) { if ( Op . isReg ( ) ) RecalcRegs . insert ( Op . getReg ( ) ) ; } LIS -> RemoveMachineInstrFromMaps ( * Lead ) ; Lead -> eraseFromParent ( ) ; if ( SaveExecReg ) { LIS -> removeInterval ( SaveExecReg ) ; LIS -> createAndComputeVirtRegInterval ( SaveExecReg ) ; } Changed = true ; if ( ! SaveExec || ! SaveExec -> isFullCopy ( ) ) continue ; unsigned SavedExec = SaveExec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SafeToReplace = true ; for ( auto & U : MRI . use_nodbg_instructions ( SavedExec ) ) { if ( U . getParent ( ) != SaveExec -> getParent ( ) ) { SafeToReplace = false ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExec << '\n' ) ; } if ( SafeToReplace ) { LIS -> RemoveMachineInstrFromMaps (


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; JTI -> Initialize ( MF , IsPIC , Subtarget -> isLittle ( ) ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ) emitInstruction ( * I ++ , * MBB ) ; } } while ( MCE . finishFunction ( MF )


<s> ~ <ISA_LIT>SchedBoundary ( ) { delete


<s> if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P ( REGNO ( XEXP ( x , <NUM_LIT> ) ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; HOST_WIDE_INT low = ( ( val & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; HOST_WIDE_INT high = ( ( ( val - low ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( high + low != val ) return NULL_RTX ; x = gen_rtx_PLUS ( GET_MODE ( x ) , gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) , GEN_INT ( high ) ) , GEN_INT ( low ) ) ; push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; return


<s> Op -> Reg . Kind = Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return


<s> return ArgDescriptor ( Arg . Reg , Mask , Arg . IsStack , Arg


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR64 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR128 : LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx + <NUM_LIT>

) , MachineMemOperand :: MOLoad , Size , Align ) ) ;


<s> bool selectRegAddr ( SDValue Addr , SDValue & Base ) { Base =


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue Vec = Op0 . getOperand ( <NUM_LIT> ) ; for ( auto * U : Vec -> uses ( ) ) { if ( U != Op0 . getNode ( ) && U -> hasOneUse ( ) && U -> getOpcode ( ) == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) == Vec && U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { SDValue OtherExtend = SDValue ( * U -> use_begin ( ) , <NUM_LIT> ) ; if ( OtherExtend . getOpcode ( ) == <STR_LIT> && OtherExtend . getOperand ( <NUM_LIT> ) == SDValue ( U , <NUM_LIT> ) && OtherExtend . getValueType ( ) == <STR_LIT> ) { SDValue VExtend = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Vec ) ; DCI . AddToWorklist ( VExtend . getNode ( ) ) ; SDValue Extract1 = DAG . getNode ( <STR_LIT> , SDLoc ( U ) , <STR_LIT> , VExtend ,

DAG . getConstant ( <NUM_LIT> , SDLoc ( U ) , <STR_LIT> ) ) ;


<s> return ( __m64 ) __builtin_arm_waddsubhx ( ( __v4hi )


<s> auto TypeEntry = llvm :: make_unique < BTFTypeFwd > ( CTy -> getName ( ) , IsUnion ) ; TypeId = addType ( std :: move ( TypeEntry ) , CTy


<s> bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; if ( RPI . IsGPR ) StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII


<s> unsigned Dcpu16RegisterInfo :: getEHHandlerRegister (


<s> bool isDXReg ( ) const { return Kind == Memory && getMemBaseReg ( ) == <STR_LIT> && !

getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectLoad ( SDNode * N ) { SDLoc dl ( N ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return SelectIndexedLoad ( LD , dl ) ; if ( SDNode * LI = SelectLoadOfLoadIntrinsic ( LD ) ) return LI ; return SelectCode (


<s> StringRef getPassName ( ) const override { return


, ( __v8hf ) __B , _MM_FROUND_CUR_DIRECTION ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> const StoreInst * Store = cast < StoreInst > ( I ) ; if ( Store -> isAtomic ( ) ) return false ; if ( ! Subtarget -> hasSIMD128 ( ) && Store -> getValueOperand ( ) -> getType ( ) -> isVectorTy ( ) ) return false ; Address Addr ; if ( ! computeAddress ( Store -> getPointerOperand ( ) , Addr ) ) return false ; unsigned Opc ; bool VTIsi1 = false ; switch ( getSimpleType ( Store -> getValueOperand ( ) -> getType ( ) ) ) { case <STR_LIT> : VTIsi1 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddress ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { if ( MatchAddressRecursively ( N , AM , <NUM_LIT> ) ) return true ; if ( AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . Base . Reg = AM . IndexReg ; AM . Scale = <NUM_LIT>


<s> return new <ISA_LIT>BranchRelaxation ( )


<s> rtx op1 = operands [ <NUM_LIT> ] ; rtx insn ; bool need_ccmpeq = false ; if ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { op0 = force_reg ( mode , op0 ) ; op1 = force_reg ( mode , op1 ) ; } else { if ( code != EQ || mode == DImode ) { op0 = force_reg ( mode , op0 ) ; if ( op1 != const0_rtx || code == GTU || code == GEU ) op1 = force_reg ( mode , op1 ) ; } } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( code == LT || ( code == LE && TARGET_IEEE && TARGET_SH2E ) || ( code == GE && ! ( TARGET_IEEE && TARGET_SH2E ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } if ( code == GE ) { gcc_assert ( TARGET_IEEE && TARGET_SH2E ) ; need_ccmpeq = true ; code = GT ; } gcc_assert ( code == EQ || code == GT || code == NE || code == LE ) ; } switch ( code


<s> static bool microblaze_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; return


<s> bool LowOverheadLoop :: RecordVPTBlocks ( MachineInstr * MI ) { if ( isVCTP ( MI ) && VCTP ) return false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } if ( isVCTP ( MI ) ) VCTP = MI ; unsigned VPROpNum = MI -> getNumOperands ( ) - <NUM_LIT> ; bool IsUse = false ; if ( MI -> getOperand ( VPROpNum ) . isReg ( ) && MI -> getOperand ( VPROpNum ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( VPROpNum ) . isUse ( ) ) { if ( ! MI -> getOperand ( VPROpNum - <NUM_LIT> ) . isImm ( ) || MI -> getOperand ( VPROpNum - <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } CurrentBlock -> addInst ( MI , CurrentPredicate ) ; IsUse = true ; } bool IsDef = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) - <NUM_LIT> ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO .


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT ,


<s> unsigned V = rotr32 ( ~ <NUM_LIT> , getT2SOImmValRotate ( Imm ) ) & Imm ; if ( getT2SOImmVal ( V )


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * Gep = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! Gep || Gep -> getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return None ; if ( ! MRI . hasOneUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand (


<s> } if ( Op . getOpcode ( ) == <STR_LIT> ) { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Tmp = DAG . getConstantFP ( APF , dl , <STR_LIT> ) ; SDValue True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Tmp ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True ) ; True = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , True , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue False = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getSelectCC ( dl , Op . getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream &


<s> DebugLoc dl = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; MI . eraseFromParent


<s> void addImmSExt8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( )


<s> vqdmulh_n_s32 ( int32x2_t a , int32_t b ) { int32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return


<s> ArrayRef < size_t > getPreallocatedArgOffsets (


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { assert ( Subtarget -> usePackets ( ) && <STR_LIT> ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert ( Ok ) ; ( void ) Ok ; if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) == <NUM_LIT>


<s> return getLoadStoreRegOpcode ( SrcReg , RC , isStackAligned


<s> rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI


<s> if ( exp < - <NUM_LIT> ) return <NUM_LIT> ; if ( ( EXP ( fl1 ) == <NUM_LIT> ) && ( FRAC ( fl1 ) != <NUM_LIT> ) ) return <NUM_LIT> ; if ( exp >= <NUM_LIT> ) { return <NUM_LIT> ; } l = MANT ( fl1 ) ; if ( exp > <NUM_LIT> ) l <<=


<s> bool <ISA_LIT>InstrInfo :: isInlineConstant ( const MachineOperand & MO , unsigned OpSize ) const { if ( MO . isImm ( ) ) { unsigned BitSize =


<s> static DecodeStatus DecodeBlezGroupBranchMMR6 ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> ; bool HasRs = false ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler ::


<s> if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = & * std :: next (


<s> return new <ISA_LIT>PagerandoOptimizer


<s> if ( AM . hasSymbolicDisplacement ( ) ) return true ; SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; } return


<s> <ISA_LIT>_IMM :: expandMOVImm ( Imm , RegSize , Insn ) ; if ( Insn . size ( ) == <NUM_LIT> ) return false ; Imm0 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; Imm1 = Imm &


<s> static int insn_get_clock ( rtx insn ) { return insn_uid_get_clock ( INSN_UID


<s> SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( GA ) , GA ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ; SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex (


<s> static std :: pair < unsigned , const TargetRegisterClass * > parseRegisterNumber ( StringRef Constraint , const TargetRegisterClass * RC , const unsigned * Map , unsigned Size ) { assert ( * ( Constraint . end ( ) - <NUM_LIT> ) == '}' && <STR_LIT> ) ; if ( isdigit ( Constraint [ <NUM_LIT> ] ) ) { unsigned Index ; bool Failed = Constraint . slice ( <NUM_LIT> , Constraint . size ( )

- <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , Index ) ;


<s> ITBlockSize = <NUM_LIT> ; PostRAHazardRecognizer :: Reset


<s> return isa < StoreInst > ( I ) || isa < LoadInst > ( I ) || isa < InsertValueInst > ( I ) || isa <

ExtractValueInst > ( I ) || isa < AtomicCmpXchgInst > ( I ) ;


<s> static MCSymbol * getPICLabel ( const char * Prefix , unsigned FunctionNumber , unsigned LabelId , MCContext & Ctx ) { MCSymbol * Label = Ctx . GetOrCreateSymbol ( Twine ( Prefix ) + <STR_LIT> + Twine ( FunctionNumber


<s> unsigned <ISA_LIT>MCCodeEmitter :: NEONThumb2DupPostEncoder ( const MCInst & MI , unsigned EncodedValue ) const { const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isThumb2 ( ) ) { EncodedValue &= <NUM_LIT>


<s> bool isFLATGlobal ( uint16_t Opcode ) const { return get ( Opcode )


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO .


<s> assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { SDValue GotAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GotAddr ) ; } if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small && <STR_LIT> ) ; SDValue Hi = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; unsigned char LoFlags = <STR_LIT> | <STR_LIT> ; SDValue Lo = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , LoFlags ) ; SDValue PoolAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , DL , PtrVT ) ) ; return GlobalAddr ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG .

getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ;


<s> * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> ) ; case <NUM_LIT> : * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> ) ; default : if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) break ; case <NUM_LIT> : * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> ) ; } } else if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) ) fatal_insn ( <STR_LIT> , insn ) ; out_shift_with_cnt ( <STR_LIT> , insn , operands , len , <NUM_LIT> ) ; return <STR_LIT>


<s> bool Changed = false ; for ( unsigned EntryIdx = <NUM_LIT> ; EntryIdx < SwapVector . size ( ) ; ++ EntryIdx ) { if ( SwapVector [ EntryIdx ] . WillRemove ) { Changed = true ; MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , SwapVector [ EntryIdx ] . VSEId ) ) ; DEBUG ( MI -> dump ( ) ) ; MI -> eraseFromParent ( ) ; } } return Changed


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << StringRef ( utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << <STR_LIT> ; return false ; } case 'D' : case 'L'


<s> if ( ! SYMBOLIC_CONST ( op ) ) return <NUM_LIT> ; return <NUM_LIT>


<s> static int hppa_address_cost ( rtx X , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { switch ( GET_CODE ( X ) ) { case REG : case PLUS : case LO_SUM : return <NUM_LIT> ; case HIGH : return


<s> unsigned <ISA_LIT>RegisterInfo :: getIndirectSubReg ( unsigned IndirectIndex )


<s> static uint64_t adjustFixupValue ( unsigned Kind , uint64_t Value ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT>


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true


<s> bool hasFineGrainedTraps ( ) const { return


<s> return <ISA_LIT>II :: getIsPredicated ( getDesc ( MCII , MCI


<s> SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode =


<s> bool isInteger_32 ( InstType InstTy , unsigned OpSize ) const { if ( InstTy == InstType :: Integer && OpSize ==


<s> if ( BranchOffset > <NUM_LIT> ) BranchOffset = - <NUM_LIT> * ( <NUM_LIT> - BranchOffset ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT>


<s> const char * name ; if ( ! TREE_PUBLIC ( decl ) || DECL_COMMON ( decl ) || DECL_INITIAL ( decl ) == NULL_TREE || DECL_INITIAL ( decl ) == error_mark_node || ( flag_zero_initialized_in_bss && initializer_zerop ( DECL_INITIAL ( decl ) ) ) ) return ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl )


<s> case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op ,


<s> static unsigned matchSVEVectorRegName ( StringRef Name ) { return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT>

) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ; if ( ! Ld0 -> hasOneUse ( )


<s> SDValue Cmp = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Log2b = Log2_32 ( VT . getSizeInBits ( ) ) ; SDLoc dl ( Op ) ; SDValue Clz = DAG . getNode ( <STR_LIT> , dl , VT , Cmp -> getOperand ( <NUM_LIT> ) ) ; SDValue Trunc = DAG . getZExtOrTrunc ( Clz , dl , <STR_LIT> ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trunc , DAG . getConstant ( Log2b , dl , <STR_LIT> ) ) ; return Scc


<s> AS . FLAT_ADDRESS = <NUM_LIT> ; AS . PRIVATE_ADDRESS = <NUM_LIT> ; AS . REGION_ADDRESS =


<s> if ( ! In64BitMode ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( )

|| isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ;


<s> addPass ( & PostRAHazardRecognizerID ) ; addPass ( create<ISA_LIT>MemoryLegalizerPass ( ) ) ; if ( Enable<ISA_LIT>InsertWaitcntsPass ) addPass ( create<ISA_LIT>InsertWaitcntsPass ( ) ) ; else addPass ( create<ISA_LIT>InsertWaitsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( & <ISA_LIT>InsertSkipsPassID ) ; addPass ( create<ISA_LIT>DebuggerInsertNopsPass ( ) ) ; addPass ( & BranchRelaxationPassID


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask


<s> addMember ( PA , G ) ; return ; } assert ( M . Addr -> getType ( ) == NodeAttrs :: Code ) ; if ( M . Addr -> getKind ( ) == NodeAttrs :: Stmt ) { Code . FirstM = PA . Id ; PA . Addr -> setNext ( M . Id ) ; } else { assert ( M . Addr -> getKind ( ) == NodeAttrs :: Phi ) ; NodeAddr < NodeBase * > MN = M ; do { M = MN ; MN = G . addr < NodeBase * > ( M . Addr -> getNext ( ) ) ; assert ( MN . Addr -> getType ( ) == NodeAttrs :: Code ) ; } while ( MN . Addr -> getKind ( ) == NodeAttrs :: Phi ) ; addMemberAfter ( M , PA , G


<s> SDLoc DL ( Op ) ; SDValue FpToFp16 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToFp16 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> InstructionCost getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI ->


<s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned IntTyWidthInBit ) const { return TargetTransformInfo :: PSK_FastHardware


<s> bool isBFWidth ( ) const { return isImm ( <NUM_LIT>


<s> SDValue InGlue = DivRem ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , dl , LO , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ; InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ; } if ( N -> hasAnyUseOfValue ( <NUM_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FrameIndex = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op

. getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) ) ; SDValue truncShuffle = DAG . getNode ( <STR_LIT> , dl , VecVT , Op0 , Op0 , shufMask ) ; return DAG . getNode ( <STR_LIT> ,


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD

( ) ) return CSR_XLEN_F64_Interrupt_SaveList ;