<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; } else { unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ]


<s> reportError ( I . getLoc ( ) , llvm :: Twine ( <STR_LIT> ) + ( Inner ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + <STR_LIT> + <STR_LIT> + llvm :: Twine ( RI . getName ( <STR_LIT> ) ) + <STR_LIT> ) ; return false ; } } } return true


<s> if ( ! VT . isVector ( ) || Op0 . getOpcode ( ) != <STR_LIT> || DAG . ComputeNumSignBits ( Op0 . getOperand ( <NUM_LIT> ) ) != NumEltBits || VT . getSizeInBits ( ) != Op0 . getValueSizeInBits ( ) ) return SDValue ( ) ; if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst ; if ( IsStrict ) SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , SDValue ( BV , <NUM_LIT> ) } ) ; else SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT


<s> } } else { const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; bool IsIndirect = Subtarget . isGVIndirectSymbol ( GV ) ; unsigned TargetFlags = <STR_LIT> ; if ( Subtarget . isTargetMachO ( ) ) { TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) TargetFlags |= <STR_LIT> ; else if ( IsIndirect ) TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isGVInGOT ( GV ) ) { TargetFlags |= <STR_LIT> ; } BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , TargetFlags ) ; if ( IsIndirect ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , unsigned , bool *


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> ++ SplitPoint ; if ( SplitPoint == BB -> end ( ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineBasicBlock * SplitBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; for ( MachineBasicBlock * Succ : BB -> successors ( ) ) { for ( MachineInstr & MI : * Succ ) { if ( ! MI . isPHI ( ) ) break ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { MachineOperand & FromBB = MI . getOperand ( I ) ; if ( BB == FromBB . getMBB ( ) ) { FromBB . setMBB ( SplitBB ) ; break ; } } } } MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ; SplitBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( SplitBB


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue MulOp0 = N -> getOperand ( <NUM_LIT> ) ; SDValue MulOp1 = N -> getOperand ( <NUM_LIT> ) ; SDValue OP0 ; SDValue OP1 ; if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext0 = MulOp0 . getOperand ( <NUM_LIT> ) ; if ( Sext0 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { SelectCode ( N ) ; return ; } OP0 = Sext0 ; } else if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp0 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { SelectCode ( N ) ; return ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; OP0 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { SelectCode ( N ) ; return ; } if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand (


<s> return const0_rtx ; case IA64_BUILTIN_INFQ : case IA64_BUILTIN_HUGE_VALQ : { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = const_double_from_real_value ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; } case IA64_BUILTIN_NANQ


<s> SmallVector < MCInst , <NUM_LIT> > Instructions ; expandInstruction ( Inst , IDLoc , Instructions ) ; for ( unsigned i = <NUM_LIT> ; i < Instructions . size ( ) ; i ++ ) { Out . EmitInstruction ( Instructions [ i ] , getSTI ( ) ) ; } } else { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; } return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~


<s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; if ( ! lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) ) EmitToStreamer (


<s> size = int_size_in_bytes ( type ) ; if ( TARGET_AAPCS_BASED ) { if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != VECTOR_TYPE && TREE_CODE ( type ) != COMPLEX_TYPE ) return false ; if ( ( ( unsigned HOST_WIDE_INT ) size ) <= UNITS_PER_WORD ) return false ; if ( aapcs_select_return_coproc ( type , fntype ) >= <NUM_LIT> ) return false ; if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < <NUM_LIT> || size > ( <NUM_LIT> * UNITS_PER_WORD ) ) ; return true ; } if ( TREE_CODE ( type ) == VECTOR_TYPE ) return ( size < <NUM_LIT> || size > ( <NUM_LIT> * UNITS_PER_WORD ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && ( TREE_CODE ( type ) != VECTOR_TYPE ) ) return false ; if ( arm_abi != ARM_ABI_APCS ) { return ( size < <NUM_LIT> || size > UNITS_PER_WORD ) ; } if ( size < <NUM_LIT> || size > UNITS_PER_WORD ) return true ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field && TREE_CODE ( field ) != FIELD_DECL ; field = DECL_CHAIN ( field ) ) continue ; if ( field == NULL ) return false ; if ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return true ; if ( arm_return_in_memory ( TREE_TYPE ( field ) , NULL_TREE )


<s> CurrentSection = nullptr ; CachedEntries . clear


<s> static MCOperand createPCXCallOP ( MCSymbol * Label , MCContext & OutContext ) { return create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_Sparc_WDI<ISA_LIT>30 , Label , OutContext


<s> if ( MI . isDebugValue ( ) || MI . getOpcode ( ) == TargetOpcode :: STACKMAP || MI . getOpcode ( ) == TargetOpcode :: PATCHPOINT ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , true ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister (


<s> if ( Enable<ISA_LIT>FastISel ) return new


<s> static bool isFullExecCopy ( const MachineInstr & MI , const GCNSubtarget & ST ) { unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; if ( MI . isFullCopy ( ) && MI . getOperand (

<NUM_LIT> ) . getReg ( ) == Exec ) return true ;


<s> assert ( N == <NUM_LIT> && isMemoryIndexed64 ( ) && <STR_LIT> ) ; addMemoryIndexedOperands ( Inst , N , <NUM_LIT>


<s> void printARIPI16Mem ( const MCInst * MI , unsigned opNum ,


<s> return ( ( qword ) ( vec_add ( vec_mule ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 )


<s> if ( ! std :: holds_alternative < cell > ( * cl ) ) { return make < unknown


<s> void addUImm4Operands ( MCInst & Inst , unsigned N )


<s> tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ) ? UNITS_PER_WORD : <NUM_LIT> ) ; int set = get_varargs_alias_set ( ) ; if ( argadj ) offset = plus_constant ( current_function_arg_offset_rtx , argadj ) ; else offset = current_function_arg_offset_rtx ; mem = gen_rtx_MEM ( SImode , current_function_internal_arg_pointer ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , <NUM_LIT> )


<s> int64_t Count , Type ; if ( ! nextLEB ( Count , Bytes , Size , false ) || ! nextLEB ( Type , Bytes , Size , false ) ) return None ; for ( int64_t J = <NUM_LIT> ; J < Count ; J ++ ) { if ( I || J ) outs ( ) << <STR_LIT> ; outs ( ) << <STR_LIT> (


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; } assert ( Opc && <STR_LIT> ) ; const MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) ; if ( Offset ) MI . addImm ( <NUM_LIT>


<s> void setIncomingArgSize ( unsigned Size )


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock


<s> if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) return <NUM_LIT> ; if ( ( ~ ZImmVal < <NUM_LIT> ) || <STR_LIT>


<s> return decodeRegisterClass ( Inst , RegNo , XRegs


<s> unsigned getMatrixReg ( ) const { assert ( Kind == k_MatrixRegister && <STR_LIT>


<s> getTargetStreamer ( ) -> emitIndIdx ( AsmPrinter :: lowerConstant ( cast < ConstantAsMetadata > ( Idx -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ) ) ; } ComputeLegalValueVTs ( F , TM , F . getReturnType ( ) , ResultVTs ) ; if ( ResultVTs . size ( ) == <NUM_LIT> ) getTargetStreamer ( ) -> emitResult ( CurrentFnSym , ResultVTs ) ; else getTargetStreamer ( ) -> emitResult ( CurrentFnSym , ArrayRef < MVT > ( ) ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { assert ( MFI -> getLocals ( ) . empty ( ) ) ; for ( unsigned Idx = <NUM_LIT> , IdxE = MRI -> getNumVirtRegs ( )


<s> prev = cur ; } gcc_assert ( cur ) ; if ( prev && ! DECL_PACKED ( field ) && ! integer_zerop ( DECL_SIZE ( field ) ) && DECL_BIT_FIELD_TYPE ( field ) != DECL_BIT_FIELD_TYPE ( prev ) ) { int prev_align = TYPE_ALIGN ( TREE_TYPE ( prev ) ) ; int cur_align = TYPE_ALIGN ( TREE_TYPE ( field ) ) ; computed = ( prev_align > cur_align ) ? prev_align : cur_align ; } } return


<s> if ( BYTES_BIG_ENDIAN ) shift = expand_binop ( SImode , xor_optab , shift , mode_mask , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; shift = expand_binop ( SImode , ashl_optab , shift , GEN_INT ( <NUM_LIT> ) , shift , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; * pshift = shift ; mask = expand_binop ( SImode , ashl_optab , GEN_INT ( GET_MODE_MASK ( mode ) ) , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; * pmask =


<s> SC = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; SC = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; } AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO )


<s> LoadSDNode * LD = cast < LoadSDNode > ( N1 ) ; if ( ! isValidIndexedLoad ( LD ) ) return NULL ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opc = ( VT == <STR_LIT> ? Opc16 : Opc8 ) ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr ( ) , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( Op , Opc , VT ,


<s> if ( GET_CODE ( x ) == CONST_VECTOR ) x = simplify_subreg ( DImode , x , GET_MODE ( x ) , <NUM_LIT> ) ; gcc_assert ( CONST_INT_P (


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , PtrVT , Offset ) ; return DAG . getNode ( <STR_LIT> , SDLoc (


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) &&


<s> SDValue tba = DAG . getTargetBlockAddress ( BA , Ty ) ; SDValue Mov = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) ,

Ty , tba , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ;


<s> int32_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MF . getFrameInfo ( ) -> CreateFixedObject ( - TailCallReturnAddrDelta , ( - <NUM_LIT> * SlotSize ) + TailCallReturnAddrDelta ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> )


<s> else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) vvvv = vvvvFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_XOP ) vvvv = vvvvFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) vvvv


<s> if ( V -> getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) ) return false ; ConstantSDNode * CN = cast < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) ; return CurDAG -> MaskedValueIsZero ( V -> getOperand ( <NUM_LIT> )


<s> else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else return true ; Parser . Lex ( ) ; if ( St == <STR_LIT> ) return false ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex (


<s> vld1_s32 ( const int32_t * a ) { return __builtin_aarch64_ld1v2si ( ( const __builtin_aarch64_simd_si * ) a


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new


<s> const SubOperator * Sub = dyn_cast < SubOperator > ( CE ) ; if ( ! Sub ) return nullptr ; const PtrToIntOperator * SubLHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; const PtrToIntOperator * SubRHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; if ( ! SubLHS || ! SubRHS ) return nullptr ; if ( SubLHS -> getPointerAddressSpace ( ) != <NUM_LIT> || SubRHS -> getPointerAddressSpace ( ) != <NUM_LIT> ) return nullptr ; const auto * GOLHS = dyn_cast < GlobalObject > ( SubLHS -> getPointerOperand ( ) ) ; const auto * GVRHS = dyn_cast < GlobalVariable > ( SubRHS -> getPointerOperand ( ) ) ; if ( ! GOLHS || ! GVRHS ) return nullptr ; if ( GVRHS -> isThreadLocal ( ) || GVRHS -> getName ( ) != <STR_LIT> || ! GVRHS -> hasExternalLinkage ( ) || GVRHS -> hasInitializer ( ) || GVRHS -> hasSection ( ) ) return nullptr ; if ( GOLHS -> isThreadLocal ( ) ) return nullptr ; return MCSymbolRefExpr :: Create ( TM . getSymbol ( GOLHS , Mang ) , MCSymbolRefExpr :: VK_COFF_IMGREL32


<s> const MCInstrDesc & getDesc ( void ) const


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG


<s> } if ( bytes > <NUM_LIT> ) return ; for ( unsigned i = <NUM_LIT> , e = Desc . getNumOperands ( ) ; i < e ; ++ i ) { if ( ! <STR_LIT> ( Desc , i ) ) continue ; const MCOperand & Op = MI . getOperand ( i ) ; if ( getLitEncoding ( Op , Desc . OpInfo [ i ] , STI ) != <NUM_LIT> ) continue ; int64_t Imm = <NUM_LIT> ; if ( Op . isImm ( ) ) Imm = Op . getImm ( ) ; else if ( Op . isExpr ( ) ) { if ( const auto * C = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ) Imm = C -> getValue ( ) ; } else if ( ! Op . isExpr ( ) ) llvm_unreachable ( <STR_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j


<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB -> addSuccessor ( SetMBB ) ; MBB = SetMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetrySwapVal ) . addReg ( SwapVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( RetrySwapVal ) . addReg ( NegBitShift ) . addImm ( - BitSize ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , RetryOldVal ) . addReg ( OldVal ) . addReg ( StoreVal ) . add (


<s> ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt


<s> __builtin_ia32_scatterpfdpd ( ( __mmask8 ) <NUM_LIT> , ( __v8si ) index , ( long long const *


<s> static void sparc_va_start ( tree valist , rtx nextarg ) { nextarg = expand_builtin_saveregs


<s> int NumEltsPerLane = NumElts / NumLanes ; SmallVector < int , <NUM_LIT> > SrcLaneMask ( NumLanes , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ; PermMask [ i ] = ( DstLane * NumEltsPerLane ) + ( M % NumEltsPerLane ) ; } SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; for ( int DstLane = <NUM_LIT> ; DstLane != NumLanes ; ++ DstLane ) { int SrcLane = SrcLaneMask [ DstLane ] ; if ( <NUM_LIT> <= SrcLane ) for ( int j = <NUM_LIT> ; j != NumEltsPerLane ; ++ j ) { LaneMask [ ( DstLane * NumEltsPerLane ) + j ] = ( SrcLane * NumEltsPerLane ) + j ; } } int NumIdentityLanes = <NUM_LIT> ; bool OnlyShuffleLowestLane = true ; for ( int i = <NUM_LIT> ; i != NumLanes ; ++ i ) { if ( isSequentialOrUndefInRange ( PermMask , i * NumEltsPerLane , NumEltsPerLane , i * NumEltsPerLane ) )


<s> if ( Size > <NUM_LIT> && Size <= <NUM_LIT> ) { if ( <STR_LIT> ( Load -> getBasePtr ( ) . getOpcode ( ) ) ) return false ; if ( <STR_LIT> ( Store -> getBasePtr ( )


<s> void setSpillsVRSAVE ( ) { SpillsVRSAVE = true


<s> if ( gt_p ) lab = gen_label_rtx ( ) ; xstormy16_emit_cbranch ( unsigned_p ? LTU : LT , gt_p ? lab : loc ) ; xstormy16_emit_cbranch ( gt_p ? NE : EQ , loc ) ; if ( gt_p ) emit_label ( lab ) ; return ; } else if ( mode == SImode && ( code == NE || code == EQ ) && op1 != const0_rtx ) { rtx lab = NULL_RTX ; int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; if ( code == EQ ) lab = gen_label_rtx ( ) ; for ( i = <NUM_LIT> ; i < num_words - <NUM_LIT> ; i ++ ) { xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( NE , code == EQ ? lab : loc ) ; } xstormy16_compare_op0 = simplify_gen_subreg ( word_mode , op0 , mode , i * UNITS_PER_WORD ) ; xstormy16_compare_op1 = simplify_gen_subreg ( word_mode , op1 , mode , i * UNITS_PER_WORD ) ; xstormy16_emit_cbranch ( code , loc ) ; if ( code == EQ ) emit_label ( lab ) ; return ; } if ( mode != HImode ) { rtx tmp ; tmp = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp , op0 ) ; op0 = tmp ; } condition_rtx = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ; cy_clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( BImode ) ) ; if ( mode == HImode ) vec = gen_rtvec ( <NUM_LIT> , branch , cy_clobber ) ; else if ( code == NE || code == EQ ) vec = gen_rtvec ( <NUM_LIT> , branch , gen_rtx_CLOBBER ( VOIDmode , op0 ) ) ; else { rtx sub ; sub = gen_rtx_SET ( VOIDmode , op0 , gen_rtx_MINUS ( SImode , op0 , op1 ) ) ; sub = gen_rtx_CLOBBER ( SImode , op0 ) ; vec = gen_rtvec ( <NUM_LIT> , branch , sub , cy_clobber ) ; } emit_jump_insn ( gen_rtx_PARALLEL ( VOIDmode


<s> } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( getSubtarget ( ) -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = getInverseCCForVSEL ( CC ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( getSubtarget ( ) -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { if ( getTargetMachine ( ) . Options . UnsafeFPMath && LHS == TrueVal && RHS == FalseVal ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , TrueVal , FalseVal ) ; } bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { if ( swpCmpOps ) std :: swap ( LHS , RHS ) ; if ( swpVselOps ) std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS


<s> int getMIMGOpcode ( unsigned BaseOpcode , unsigned MIMGEncoding , unsigned VDataDwords , unsigned VAddrDwords ) { const MIMGInfo * Info = getMIMGOpcodeHelper ( BaseOpcode , MIMGEncoding , VDataDwords ,


<s> for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / <NUM_LIT> ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks (


<s> static DecodeStatus DecodeRRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler ::


<s> return Reg != <NUM_LIT> && ! llvm :: Register :: isStackSlot (

Reg ) && llvm :: Register :: isVirtualRegister ( Reg ) ;


<s> return getExtSymb ( DAG , <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; break ; default : return


<s> arm_init_bf16_types ( ) ; if ( TARGET_MAYBE_HARD_FLOAT ) { tree lane_check_fpr = build_function_type_list ( void_type_node , intSI_type_node , intSI_type_node , NULL ) ; arm_builtin_decls [ ARM_BUILTIN_SIMD_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , ARM_BUILTIN_SIMD_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; if ( TARGET_HAVE_MVE ) arm_init_mve_builtins ( ) ; else arm_init_neon_builtins ( ) ; arm_init_vfp_builtins ( ) ; arm_init_crypto_builtins ( ) ; } if ( TARGET_CDE ) arm_init_cde_builtins ( ) ; arm_init_acle_builtins ( ) ; if ( TARGET_MAYBE_HARD_FLOAT ) { tree ftype_set_fpscr = build_function_type_list ( void_type_node ,


<s> bool IsNaCl = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn ) return CSR_NaCl64EHRet_SaveList ; return CSR_NaCl64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList


<s> bool <ISA_LIT>AsmParser :: parseDirectiveEven ( SMLoc L ) { if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return false ; const MCSection * Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; if ( ! Section ) { getStreamer ( ) . InitSections ( false ) ; Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT>


<s> unsigned TotalSize = BlockOffsets [ Begin -> getNumber ( ) ] ; for ( auto & MBB : make_range ( Begin , MF -> end ( ) ) ) { BlockOffsets [ MBB . getNumber (


<s> rtx def_insn = DF_REF_INSN ( link -> ref ) ; ( void ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( def_insn ) ) ; } link = link


<s> void <ISA_LIT>AddressSanitizer64 :: InstrumentMemOperandLarge ( <ISA_LIT>Operand & Op , unsigned AccessSize , bool IsWrite , const RegisterContext & RegCtx , MCContext & Ctx , MCStreamer & Out ) { unsigned AddressRegI64 = RegCtx . AddressReg ( <STR_LIT> ) ; unsigned ShadowRegI64 = RegCtx . ShadowReg ( <STR_LIT> ) ; ComputeMemOperandAddress ( Op , <STR_LIT> , AddressRegI64 , Ctx , Out ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( AddressRegI64 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( ShadowRegI64 ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; switch ( AccessSize ) { case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst ) ; } MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitCallAsanReport ( AccessSize , IsWrite ,


<s> static __inline__ double __fnmsub ( double x , double y , double z ) { double


<s> bool MadeChange = false ; if ( ! L -> empty ( ) ) return MadeChange ; SmallPtrSet < const Value * , <NUM_LIT> > EphValues ; CodeMetrics :: collectEphemeralValues ( L , AC , EphValues ) ; CodeMetrics Metrics ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) if ( CallInst * CI = dyn_cast < CallInst > ( J ) ) if ( Function * F = CI -> getCalledFunction ( ) ) if ( F -> getIntrinsicID ( ) == <STR_LIT> ) return MadeChange ; Metrics . analyzeBasicBlock ( * I , * TTI , EphValues ) ; } unsigned LoopSize = Metrics . NumInsts ; if ( ! LoopSize ) LoopSize = <NUM_LIT> ; unsigned ItersAhead = PrefDist / LoopSize ; if ( ! ItersAhead ) ItersAhead = <NUM_LIT> ; SmallVector < std :: pair < Instruction * , const SCEVAddRecExpr * > , <NUM_LIT> > PrefLoads ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) { for ( BasicBlock :: iterator J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { Value * PtrValue ; Instruction * MemI


<s> EVT VT = Vec . getValueType ( ) ; EVT ElVT = VT . getVectorElementType ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk -


<s> } else { bytes += <NUM_LIT> ; SDValue stack_ptr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , getPointerTy ( ) ) ; SDValue addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , stack_ptr , DAG . getIntPtrConstant ( bytes ) ) ; SDValue store = DAG . getStore ( Chain , dl , arg , addr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; stack_args . push_back ( store ) ; } } SDValue InFlag ; if ( ! stack_args . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & stack_args [ <NUM_LIT> ] , stack_args . size ( ) ) ; } for ( unsigned i = <NUM_LIT> ; i < reg_args . size ( ) ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , reg_args [ i ] . first , reg_args [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * g = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( g -> getGlobal ( ) , dl , <STR_LIT> , g -> getOffset ( ) ) ; } else if ( ExternalSymbolSDNode * e = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( e -> getSymbol ( ) , <STR_LIT> ) ; } SDVTList OperandTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > ops ; ops . push_back ( Chain ) ; ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> ; i < reg_args . size ( ) ; ++ i ) { ops . push_back ( DAG . getRegister ( reg_args [ i ] . first , reg_args [ i ] . second . getValueType ( ) ) ) ; } if ( InFlag . getNode ( ) ) ops . push_back ( InFlag ) ; const bool isIndirectCall = ( Callee . getOpcode ( ) != <STR_LIT> && Callee . getOpcode ( ) != <STR_LIT> && Callee . getOpcode ( ) != <STR_LIT> && Callee . getOpcode ( ) != <STR_LIT> ) ; if ( isIndirectCall ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; MCSymbol * indirectCallOperand = MMI . getContext ( ) . CreateTempSymbol ( ) ; const char * retLabName = indirectCallOperand -> getName ( ) . data ( ) ; SDValue glueVal = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , DAG

. getTargetExternalSymbol ( retLabName , getPointerTy ( ) , <NUM_LIT> ) , glueVal ) ;


<s> if ( SDValue BlendOp = lowerVSELECTtoVectorShuffle ( Op , Subtarget , DAG ) ) return BlendOp ; MVT CondVT = Cond . getSimpleValueType ( ) ; unsigned CondEltSize = Cond . getScalarValueSizeInBits ( ) ; if ( CondEltSize == <NUM_LIT> ) return Op ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue Mask = DAG . getSetCC ( dl , MaskVT , Cond , DAG . getConstant ( <NUM_LIT> , dl , CondVT ) , <STR_LIT> ) ; return DAG . getSelect ( dl , VT , Mask , LHS , RHS ) ; } if ( CondEltSize != EltSize ) { if ( CondEltSize != DAG . ComputeNumSignBits ( Cond ) ) return SDValue ( ) ; MVT NewCondSVT = <STR_LIT> ( EltSize ) ; MVT NewCondVT = <STR_LIT> ( NewCondSVT , NumElts ) ; Cond = DAG . getSExtOrTrunc ( Cond , dl , NewCondVT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cond , LHS , RHS ) ; } switch ( VT . SimpleTy ) { default : return Op ; case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) return Op ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : { MVT CastVT = <STR_LIT> ( <STR_LIT> , NumElts * <NUM_LIT> ) ; Cond = DAG . getBitcast ( CastVT


<s> IRBuilder < > builder ( secondBB ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > itrin [ <NUM_LIT> ] = { get_list_of < IntrinsicInst , <NUM_LIT> > ( & firstBB ) , get_list_of < IntrinsicInst , <NUM_LIT> > ( & secondBB ) } ; vector < Instruction * > selectItrin [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) selectItrin [ i ] = extractIntrinFromList ( itrin


<s> if ( ! MI -> getOperand ( OpNo + i ) . isReg ( ) ) continue ; unsigned Reg = MI -> getOperand ( OpNo +


<s> if ( DisableForwardSearch || ! Slot -> isCall ( ) ) return false ; RegDefsUses RegDU ( TM ) ; NoMemInstr NM ; Iter Filler ; RegDU . setCallerSaved ( * Slot ) ; if ( ! searchRange ( MBB , std :: next ( Slot ) , MBB . end ( ) , RegDU , NM , Filler , Slot ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB


<s> return Subtarget -> isTargetWindows ( ) && ! Subtarget ->


<s> length = pa_attr_length_millicode_call ( insn ) + <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } } if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) length += compute_movmem_length ( insn ) - <NUM_LIT> ; else if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( pat ) == PARALLEL && GET_CODE ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) == SET && GET_CODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == MEM &&

XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == const0_rtx && GET_MODE ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) == BLKmode ) length += compute_clrmem_length ( insn ) - <NUM_LIT> ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF


<s> ( ( struct u8 * ) ptr ) -> data = data ; return


<s> MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcHiReg = getSubReg ( SrcReg , <STR_LIT> ) ; Register SrcLoReg = getSubReg ( SrcReg , <STR_LIT> ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( FrameReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> )


<s> } frame -> nregs = nregs ; if ( size == <NUM_LIT> && nregs == <NUM_LIT> ) { frame -> padding0 = <NUM_LIT> ; frame -> padding1 = frame -> padding2 = <NUM_LIT> ; frame -> frame_pointer_offset = frame -> to_allocate = <NUM_LIT> ; frame -> outgoing_arguments_size = <NUM_LIT> ; return ; } if ( ! frame -> push_rts ) offset += frame -> nregs * <NUM_LIT> ; if ( offset == <NUM_LIT> && size == <NUM_LIT> && crtl -> outgoing_args_size == <NUM_LIT> && ! crtl -> is_leaf ) frame -> padding0 = frame -> padding1 = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) frame -> padding1 = <NUM_LIT> ; else frame -> padding1 = <NUM_LIT> ; offset += frame -> padding0 + frame -> padding1 ; frame -> frame_pointer_offset = offset ; offset +=


<s> case ALL_REGS : case FP_REGS : case FP_LO_REGS : return aarch64_vector_mode_p ( mode ) ? ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> : ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; case STACK_REG : return <NUM_LIT> ; case NO_REGS : return <NUM_LIT>


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success


<s> unsigned Opc ; if ( VT == XLenVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , XLenVT , Src . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( FRM , DL , XLenVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> if ( MI -> getOperand ( OpNo ) . isExpr ( ) && isa < MCBinaryExpr > ( MI -> getOperand ( OpNo ) . getExpr ( ) ) ) { O <<


<s> tem = op0 , code2 = code ; } else { switch ( code ) { case EQ : case LT : case LE : case LEU : case LTU : code1 = code ; code2 = NE ; break ; default : code1 = reverse_condition ( code ) ; code2 = EQ ; break ; } emit_insn ( gen_rtx_SET ( tem , gen_rtx_fmt_ee ( code1 , BImode , op0 , op1 ) ) ) ; } return gen_rtx_fmt_ee ( code2 , BImode , tem


<s> for ( auto I = FaultingMI . operands_begin ( ) + OperandsBeginIdx , E = FaultingMI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & FaultingMI , * I ) ) MI . addOperand ( MaybeOperand . getValue ( ) ) ; OutStreamer -> EmitInstruction ( MI , getSubtargetInfo (


<s> EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) ) { if ( VT == <STR_LIT> && Enabled == ReciprocalEstimate :: Unspecified ) return SDValue ( ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; int BccOpcNot = <STR_LIT> ; MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) !=


<s> DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo ( SV , Offset ) , false , false , <NUM_LIT> ) ; Offset += <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , DL


<s> BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor (


<s> int RegBytes = TRI -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; if ( RegBytes > <NUM_LIT> ) return false ; const TargetRegisterClass * NOREXRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> } ; if ( RC == NOREXRegClasses [ Log2_32 ( RegBytes ) ] ) return false ; const TargetRegisterClass * GPRRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT>


<s> unsigned RegSeqDstSubReg = UseMI -> getOperand ( UseOpIdx + <NUM_LIT> ) . getImm ( ) ; for ( MachineRegisterInfo :: use_iterator RSUse = MRI -> use_begin ( RegSeqDstReg ) , RSE = MRI -> use_end ( ) ; RSUse != RSE ; ++ RSUse ) { MachineInstr * RSUseMI = RSUse -> getParent ( ) ; if ( RSUse -> getSubReg ( ) != RegSeqDstSubReg ) continue ; foldOperand ( OpToFold , RSUseMI , RSUse . getOperandNo ( ) , FoldList , CopiesToReplace ) ; } return ; } bool FoldingImm = OpToFold . isImm ( ) ; if ( FoldingImm && UseMI -> isCopy ( ) ) { unsigned DestReg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DestRC = TargetRegisterInfo :: isVirtualRegister ( DestReg ) ? MRI -> getRegClass ( DestReg ) : TRI -> getPhysRegClass ( DestReg ) ; unsigned MovOp = TII -> getMovOpcode ( DestRC ) ; if ( MovOp == <STR_LIT> ) return ; UseMI -> setDesc ( TII -> get ( MovOp ) ) ; CopiesToReplace . push_back (


<s> MachineInstr & LoadMI = * I ; Register BaseReg = getLdStBaseOp ( LoadMI ) . getReg ( ) ; if ( MBBI == B ) return false ; ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { MBBI = prev_nodbg ( MBBI , B ) ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && getLdStOffsetOp ( MI ) . isImm ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) ) return false ; if ( MI . mayStore ( ) && LoadMI . mayAlias ( AA , MI , false ) ) return false ; } while ( MBBI != B && Count < Limit ) ; return


<s> static MachineOperand * getCallTargetRegOpnd ( MachineInstr & MI ) { if ( MI . getNumOperands ( ) == <NUM_LIT>


<s> bool <ISA_LIT>FrameLowering :: expandStoreInt ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Opc = MI -> getOpcode ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT>


<s> if ( ST . debuggerReserveRegs ( ) ) return <NUM_LIT> ; return


<s> MBB . addLiveIn ( PreloadedScratchRsrcReg ) ; } } DebugLoc DL ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; Register ScratchWaveOffsetReg ; if ( TRI -> isSubRegisterEq ( ScratchRsrcReg , PreloadedScratchWaveOffsetReg ) ) { ArrayRef < MCPhysReg > AllSGPRs = TRI -> getAllSGPR32 ( MF ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; AllSGPRs = AllSGPRs . slice ( std :: min ( static_cast < unsigned > ( AllSGPRs . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( ScratchRsrcReg , Reg ) && GITPtrLoReg != Reg ) { ScratchWaveOffsetReg = Reg ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ; break ; } } } else { ScratchWaveOffsetReg = PreloadedScratchWaveOffsetReg ; } assert ( ScratchWaveOffsetReg ) ; if ( requiresStackPointerReference ( MF ) ) { Register SPReg = MFI -> getStackPtrOffsetReg ( ) ; assert ( SPReg != <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addImm ( MF . getFrameInfo ( ) . getStackSize ( ) * getScratchScaleFactor ( ST ) ) ; } if ( hasFP ( MF ) ) { Register FPReg = MFI -> getFrameOffsetReg ( ) ; assert ( FPReg != <STR_LIT>


<s> void CFStack :: popLoop ( ) { CurrentEntries --


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( x & ( ( unsigned short ) <NUM_LIT> << ( <NUM_LIT> - i ) ) ) break ; return i


<s> EVT DestEVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( DestVT != <STR_LIT> ) return false ; unsigned DivOpc ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; case


<s> for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual


<s> bool <ISA_LIT>VectorRegMerger :: areAllUsesSwizzeable ( unsigned Reg ) const { for ( MachineRegisterInfo :: use_instr_iterator It = MRI -> use_instr_begin ( Reg ) , E = MRI -> use_instr_end ( ) ; It != E ; ++ It ) { if ( ! canSwizzle ( * It ) ) return


<s> std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? <NUM_LIT> : MF -> getFunction ( ) -> getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : LLVM_FALLTHROUGH ; case Instruction :: BitCast : return lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; case Instruction ::


<s> int GCNHazardRecognizer :: checkReadM0Hazards ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo


<s> SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal


<s> } else { B . buildInstr ( <STR_LIT> ) . addDef ( Def ) . addUse ( Use ) . addMBB ( BrCond -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( <NUM_LIT> ) ; } MRI . setRegClass ( Def , TRI -> getWaveMaskRegClass ( ) ) ; MRI . setRegClass ( Use , TRI -> getWaveMaskRegClass ( ) ) ; MI . eraseFromParent ( ) ; BrCond -> eraseFromParent ( ) ; return true ; } return false ; } case <STR_LIT> : { if ( MachineInstr * BrCond = verifyCFIntrinsic ( MI , MRI ) ) { const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; B . setInstr ( * BrCond ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; B . buildInstr ( <STR_LIT> ) . addUse ( Reg ) . addMBB ( BrCond -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MI . eraseFromParent ( ) ; BrCond -> eraseFromParent ( ) ; MRI . setRegClass ( Reg , TRI -> getWaveMaskRegClass ( ) ) ; return true ; } return false ; } case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizeImplicitArgPtr ( MI , MRI , B ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizeFDIVFastIntrin ( MI , MRI , B ) ; case <STR_LIT> : return legalizeIsAddrSpace ( MI , MRI , B , <ISA_LIT>AS :: LOCAL_ADDRESS ) ; case <STR_LIT> : return legalizeIsAddrSpace ( MI , MRI , B , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; case <STR_LIT> : { B . setInstr ( MI ) ; B . buildConstant ( MI . getOperand ( <NUM_LIT> ) , ST . getWavefrontSize ( ) ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : return legalizeRawBufferStore ( MI , MRI , B , false ) ; case <STR_LIT> : return legalizeRawBufferStore ( MI , MRI ,


<s> return ! ( MaxSize <= <NUM_LIT> ) && (

int ) Collection . size ( ) >= MaxSize ;


<s> if ( ! Subtarget -> hasV6T2Ops ( ) ) return ; bool isThumb2 = Subtarget -> isThumb ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; unsigned And_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N1 . getNode ( ) , <STR_LIT> , And_imm ) ) { if ( isOpcWithIntImmediate ( N0 . getNode ( ) , <STR_LIT> , And_imm ) ) std :: swap ( N0 , N1 ) ; } if ( ! And_imm ) continue ; unsigned TZ = countTrailingZeros ( And_imm ) ; if ( TZ != <NUM_LIT> && TZ != <NUM_LIT> ) continue ; And_imm >>= TZ ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) continue ; SDValue Srl = N1 . getOperand ( <NUM_LIT> ) ; unsigned Srl_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( Srl . getNode ( ) , <STR_LIT> , Srl_imm ) || ( Srl_imm <= <NUM_LIT> ) ) continue ; SDValue CPTmp0 ; SDValue CPTmp1 ; SDValue CPTmp2 ; if ( isThumb2 ) { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) ) continue ; } else { if ( SelectImmShifterOperand ( N0 , CPTmp0 , CPTmp1 ) || SelectRegShifterOperand ( N0 , CPTmp0 , CPTmp1 , CPTmp2 ) ) continue ; } Srl = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Srl ) , <STR_LIT> , Srl . getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( Srl_imm + TZ , SDLoc ( Srl ) , <STR_LIT> ) ) ; N1 = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N1 ) , <STR_LIT> , Srl , CurDAG -> getConstant ( And_imm


<s> int reg_base = true_regnum ( XEXP ( base , <NUM_LIT> ) ) ; if ( AVR_TINY ) return avr_out_movhi_r_mr_reg_disp_tiny ( op , plen ) ; if ( disp > MAX_LD_OFFSET ( GET_MODE ( src ) ) ) { if ( REGNO ( XEXP ( base , <NUM_LIT> ) ) != REG_Y ) fatal_insn ( <STR_LIT> , insn ) ; return disp <= <NUM_LIT> + MAX_LD_OFFSET ( GET_MODE ( src ) ) ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } if ( reg_base == REG_X ) return reg_base == reg_dest ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; return reg_base == reg_dest ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else if ( GET_CODE ( base ) == PRE_DEC ) { if ( AVR_TINY ) return avr_out_movhi_r_mr_pre_dec_tiny ( insn , op , plen ) ; if ( reg_overlap_mentioned_p ( dest , XEXP ( base , <NUM_LIT> ) ) ) fatal_insn ( <STR_LIT> , insn ) ; if ( ! mem_volatile_p ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; return REGNO ( XEXP ( base , <NUM_LIT> ) ) == REG_X ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else if ( GET_CODE ( base ) == POST_INC ) { if ( reg_overlap_mentioned_p ( dest , XEXP ( base , <NUM_LIT> ) ) ) fatal_insn ( <STR_LIT> , insn ) ; return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else if ( CONSTANT_ADDRESS_P ( base ) ) { int n_words = AVR_TINY ? <NUM_LIT> : <NUM_LIT> ; return optimize > <NUM_LIT> && io_address_operand ( base , HImode ) ? avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - n_words ) ; } fatal_insn ( <STR_LIT> , insn ) ; return <STR_LIT>


<s> OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( Result == MatchOperand_Success ) return Result ; if ( Result == MatchOperand_ParseFail ) { Parser . eatToEndOfStatement ( ) ; return Result ; } assert ( Result == MatchOperand_NoMatch && <STR_LIT> ) ; if ( Lexer . is ( AsmToken :: Percent ) ) { unsigned RegNo


<s> inline static RoundingMode stringToRoundingMode ( StringRef Str ) { return StringSwitch < RoundingMode > ( Str ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT>


<s> return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerREM ( Op ,


<s> Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( ST -> getOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride , Tile } ; Builder . CreateIntrinsic ( <STR_LIT> , None , Args


<s> MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( <NUM_LIT> ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) || OpToFold . isGlobal ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI ,


<s> SrcBlkInfo -> IsRetired = true ; assert ( MBB -> succ_size ( ) == <NUM_LIT> &&

MBB -> pred_size ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg


<s> unsigned getAddrModeImm12OpValue ( const MachineInstr & MI , unsigned Op ) const { const MachineOperand & MO = MI . getOperand ( Op ) ; const MachineOperand & MO1 = MI . getOperand ( Op + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { emitConstPoolAddress ( MO . getIndex ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned Reg = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; uint32_t Binary ; Binary = Imm12 & <NUM_LIT>


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_prefetch_i64scatter_pd ( void * addr , __m512i index , int scale , int hint ) { __builtin_ia32_scatterpfqpd ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , (

long long const * ) addr , scale , hint ) ;


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) .


<s> return & InstrInfo -> getRegisterInfo


<s> bool isFI ( ) const { return isImmTy ( ImmTyDppFi )


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock ( false ) ; EmitTST ( Out , Reg ) ; Out . EmitInstruction ( Saved [


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , DestBB , Br . MaxDisp ) ) return false ; if ( ! Br . isCond ) return FixUpUnconditionalBr ( Fn , Br ) ; return FixUpConditionalBr ( Fn , Br


<s> SDValue V1 = Ops [ <NUM_LIT> ] ; SDValue V2 = IsUnary ? V1 : Ops [ <NUM_LIT> ] ; V1 = peekThroughBitcasts ( V1 ) ; V2 = peekThroughBitcasts ( V2 ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { Mask [ i ] = SM_SentinelUndef ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) continue ; if ( ( Size % V . getNumOperands ( ) ) == <NUM_LIT> ) { int Scale = Size / V -> getNumOperands ( ) ; SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) ) Mask [ i ] = SM_SentinelUndef ; else if ( <STR_LIT> ( Op ) ) Mask [ i ] = SM_SentinelZero ; continue ; } if ( ( V . getNumOperands ( )


<s> static bool vr4130_true_reg_dependence_p (


<s> tmp = plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * i ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; tmp = gen_frame_mem ( BLKmode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , par [ <NUM_LIT> ] ) ; par [ <NUM_LIT> ] = tmp ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( i , par ) ) ; insn = emit_insn ( tmp ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * i ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , tmp ) ; par [ <NUM_LIT> ] = tmp ; for ( j = <NUM_LIT> ; real_regs ; ++ j , real_regs &= real_regs - <NUM_LIT> ) { regno = ctz_hwi ( real_regs ) ; reg = gen_rtx_REG ( SImode , regno ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , j * <NUM_LIT> ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; par [ j + <NUM_LIT> ] = tmp ; } if ( j == <NUM_LIT> ) tmp = par [ <NUM_LIT> ] ; else { RTX_FRAME_RELATED_P ( par [ <NUM_LIT> ] ) = <NUM_LIT> ; tmp = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec_v ( j + <NUM_LIT> , par


<s> return new <ISA_LIT>DagToDagISel ( tm


<s> else if ( MO1 . isImm ( ) ) O << <STR_LIT> << MO1 . getImm ( ) << <STR_LIT> ; else llvm_unreachable (


<s> int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI !=


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , createMCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , createMCRegisterInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , createMCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , createAsmBackend ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , createMCSubtargetInfo ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T


<s> if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> )


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) || ( VT == <STR_LIT> && <ISA_LIT>ScalarSSEf32 ) || ( VT == <STR_LIT>


<s> bool hasFP ( const MachineFunction & ) const override { return


<s> SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; if ( const auto * MCE = dyn_cast < MCConstantExpr > ( Value ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; getStreamer ( ) . EmitIntValue ( IntValue ,


<s> PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ; MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ]


<s> } unsigned CPI = getCombinedIndex ( CPEMI ) ; assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [ CPI ] . getAlignment


<s> SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; bool UseHVXSgl = Subtarget . useHVXSglOps ( ) ; if ( ! VT . isVector ( ) || ! UseHVX ) return SDValue ( ) ; EVT ResVT = Op . getValueType ( ) ; unsigned ResSize = ResVT . getSizeInBits ( ) ; unsigned VectorSizeInBits = UseHVXSgl ? ( <NUM_LIT> * <NUM_LIT> ) : ( <NUM_LIT> * <NUM_LIT> ) ; unsigned OpSize = VT . getSizeInBits ( ) ; if ( ! ( ResVT . isByteSized ( ) && ResSize == VectorSizeInBits ) || ! ( VT . isByteSized ( ) && OpSize == <NUM_LIT> * VectorSizeInBits ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst )


<s> if ( Base . Reg . getNode ( ) != <NUM_LIT> ) Base . Reg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Base . FrameIndex << '\n' << <STR_LIT> << Scale << '\n' << <STR_LIT> ; if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n'


<s> bool isMemDisp12Len8 ( RegisterKind RegKind ) const { return isMemDisp12 ( BDLMem , RegKind ) && inRange ( Mem . Length , <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS .


<s> if ( auto Value = stripModuloOnShift ( * this , N , DCI . DAG ) ) return Value ; return SDValue (


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; unsigned Reg = LI ; if ( Reg != InnerRegion -> getBBSelectRegOut ( ) ) { const TargetRegisterClass * RegClass = MRI -> getRegClass ( Reg ) ; unsigned PHIDestReg = MRI -> createVirtualRegister ( RegClass ) ; unsigned IfSourceReg = MRI -> createVirtualRegister ( RegClass ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg ) << <STR_LIT> ) ; TII -> materializeImmediate ( * IfBB , IfBB -> getFirstTerminator ( ) , DebugLoc ( ) , IfSourceReg , <NUM_LIT> ) ; InnerRegion -> replaceRegisterOutsideRegion ( Reg , PHIDestReg , true , MRI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; insertMergePHI ( IfBB , InnerRegion -> getExit ( ) , MergeBB , PHIDestReg , IfSourceReg , Reg , true ) ; } } SmallVector < unsigned , <NUM_LIT> > Sources ; if ( PHIInfo . findSourcesFromMBB ( CodeBB , Sources ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * CodeBB ) << <STR_LIT> ) ; for ( auto <ISA_LIT> : Sources ) { unsigned DestReg ; PHIInfo . findDest ( <ISA_LIT> , CodeBB , DestReg ) ; insertChainedPHI ( IfBB , CodeBB , MergeBB , InnerRegion , DestReg , <ISA_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( PHIInfo . dump


<s> unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i

+ j + <NUM_LIT> ] != j + NumElts + WhichResult ) ) return false ;


<s> break ; case LT : if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) cond = <STR_LIT> ; else if ( cc_mode == CCNZmode ) cond = <STR_LIT> ; else cond = <STR_LIT> ; break ; case GEU : cond = <STR_LIT> ; break ; case GTU : cond = <STR_LIT> ; break ; case LEU : cond = <STR_LIT> ; break ; case LTU : cond = <STR_LIT> ; break ; case UNORDERED : cond = <STR_LIT> ; break ; case ORDERED : cond = <STR_LIT> ; break ; case UNGE : cond = <STR_LIT> ; break ; case UNGT : cond = <STR_LIT> ; break ; case UNLE : cond = <STR_LIT> ; break ; case UNLT : cond = <STR_LIT> ; break ; case UNEQ : case LTGT : default : gcc_unreachable (


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString (


<s> fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } } if ( epiphany_m1reg >= <NUM_LIT> ) { fixed_regs [ epiphany_m1reg ] = <NUM_LIT> ; call_used_regs [ epiphany_m1reg ] = <NUM_LIT> ; } if ( ! TARGET_PREFER_SHORT_INSN_REGS ) CLEAR_HARD_REG_SET ( reg_class_contents [ SHORT_INSN_REGS ] ) ; COPY_HARD_REG_SET ( reg_class_contents [ SIBCALL_REGS ] , reg_class_contents [ GENERAL_REGS ] ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! call_used_regs [ i ] ) CLEAR_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS


<s> if ( ST -> hasSlowLoadDSubregister ( ) && Opcode == Instruction :: InsertElement && ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { if ( ValTy -> getVectorElementType ( ) -> isIntegerTy ( ) ) return <NUM_LIT> ; if ( ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return std :: max ( BaseT :: getVectorInstrCost ( Opcode ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode (

) , FrameAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> name = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM ) ; fprintf ( f , <STR_LIT> ) ; if ( arm_dllexport_name_p ( name ) ) name = arm_strip_name_encoding ( name ) ; asm_fprintf ( f , <STR_LIT>


<s> return CurDAG -> getTargetConstant ( Imm , Node ->


<s> assert ( ! ( getFlags ( ) & NodeAttrs :: PhiRef )


<s> unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = <STR_LIT> ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; if ( DCI . isBeforeLegalize ( ) || TruncVT != <STR_LIT> ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } assert ( InVT == <STR_LIT> && <STR_LIT> ) ; SDValue Cast = DAG . getBitcast ( <STR_LIT> , Op0 ) ; SDValue Shuf = DAG . getVectorShuffle ( <STR_LIT> , dl , Cast , Cast , { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ) ; return DAG . getNode ( <STR_LIT> ,


<s> bool isSImm6NonZero ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t Imm


<s> return getWavesPerWorkGroup ( FlatWorkGroupSize )


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast


<s> unsigned TargetFlags = get ( Opcode ) . TSFlags ; return ( ( TargetFlags & <STR_LIT> ) | ( TargetFlags

& <STR_LIT> ) | ( TargetFlags & <STR_LIT> ) ) ;


<s> return isRegNumber ( ) && ( getImm ( ) &


<s> N -> Flags |= GepNode :: Root | InBounds ; } else { N -> Parent = F -> second ; } N -> PTy = PtrOp -> getType ( ) ; N -> Idx = * GepI -> idx_begin ( ) ; UseSet Us ; for ( Value :: user_iterator UI = GepI -> user_begin ( ) , UE = GepI -> user_end ( ) ; UI != UE ; ++ UI ) { if ( isa < GetElementPtrInst > ( * UI ) ) { GetElementPtrInst * UserG = cast < GetElementPtrInst > ( * UI ) ; if ( isHandledGepForm ( UserG ) ) continue ; } Us . insert ( & UI . getUse ( ) ) ; } Nodes . push_back ( N ) ; NodeOrder . insert ( N ) ; GepNode * PN = N ; Type * PtrTy = cast < PointerType > ( PtrOp -> getType ( ) ) -> getElementType ( ) ; for ( User :: op_iterator OI = GepI -> idx_begin ( ) + <NUM_LIT> , OE = GepI -> idx_end ( ) ; OI != OE ; ++ OI ) { Value * Op = * OI ; GepNode * Nx = new ( * Mem ) GepNode ; Nx -> Parent = PN ; Nx -> Flags |= GepNode :: Internal | InBounds ; Nx -> PTy = PtrTy ; Nx -> Idx = Op ; Nodes . push_back ( Nx ) ; NodeOrder . insert ( Nx )


<s> assert ( Op . isImm ( ) ) ; OptionalIdx [ Op . getImmTy ( ) ] = i ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOffset ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDFMT ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyNFMT ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySLC


<s> unsigned <ISA_LIT>RegisterInfo :: getNumArgRegs ( const MachineFunction * MF ) { return array_lengthof ( <ISA_LIT>_ArgRegs


<s> case MCK_ImmS16 : if ( AsmOp -> isImm ( )


<s> void <ISA_LIT>InstPrinter :: printMemRegReg ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getReg


<s> assert ( Elements . size ( ) == NumElems ) ; return DAG -> getNode ( <STR_LIT> , dl , VT


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { OutStreamer . EmitRawText ( Twine ( <STR_LIT> + Opt<ISA_LIT>Version ) ) ; OutStreamer . EmitRawText ( Twine ( <STR_LIT> + Opt<ISA_LIT>Target ) ) ; OutStreamer . AddBlankLine (


<s> machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; bool collisionparts [ <NUM_LIT> ] ; if ( TARGET_64BIT && GET_MODE_SIZE ( GET_MODE ( operands [ <NUM_LIT> ] ) ) == <NUM_LIT> ) { if ( MEM_P ( operands [ <NUM_LIT> ] ) && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) operands [ <NUM_LIT> ] = get_pool_constant ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( push_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) { operands [ <NUM_LIT> ] = copy_rtx ( operands [ <NUM_LIT> ] ) ; PUT_MODE ( operands [ <NUM_LIT> ] , word_mode ) ; } else operands [ <NUM_LIT> ] = gen_lowpart ( DImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_lowpart ( DImode , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } if ( push_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) push = <NUM_LIT> ; else gcc_assert ( ! MEM_P ( operands [ <NUM_LIT> ] ) || offsettable_memref_p ( operands [ <NUM_LIT> ] ) ) ; nparts = ix86_split_to_parts ( operands [ <NUM_LIT> ] , part [ <NUM_LIT> ] , GET_MODE ( operands [ <NUM_LIT> ] ) ) ; ix86_split_to_parts ( operands [ <NUM_LIT> ] , part [ <NUM_LIT> ] , GET_MODE ( operands [ <NUM_LIT> ] ) ) ; if ( push && MEM_P ( operands [ <NUM_LIT> ] ) && reg_overlap_mentioned_p ( stack_pointer_rtx , operands [ <NUM_LIT> ] ) ) { rtx src_base = XEXP ( part [ <NUM_LIT> ] [ nparts - <NUM_LIT> ] , <NUM_LIT> ) ; if ( ! TARGET_64BIT && nparts == <NUM_LIT> && mode == XFmode && TARGET_128BIT_LONG_DOUBLE ) src_base = plus_constant ( Pmode , src_base , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nparts ; i ++ ) part [ <NUM_LIT> ] [ i ] = change_address ( part [ <NUM_LIT> ] [ i ] , GET_MODE ( part [ <NUM_LIT> ] [ i ] ) , src_base ) ; } if ( REG_P ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) && MEM_P ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ) { rtx tmp ; for ( i = <NUM_LIT> ; i < nparts ; i ++ ) { collisionparts [ i ] = reg_overlap_mentioned_p ( part [ <NUM_LIT> ] [ i ] , XEXP ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( collisionparts [ i ]


<s> rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) ) return false ; REAL_VALUE_TYPE r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst0 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconst2 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconst1 ) ) asm_fprintf ( f , <STR_LIT> ) ; else if ( real_equal ( & r , & dconsthalf ) ) asm_fprintf ( f , <STR_LIT> ) ; else { const int buf_size


<s> unsigned getMaxNumElements ( ElementCount VF ) const { if ( ! VF . isScalable ( ) ) return VF


<s> return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , STI , CS ) ; } if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , true , STI ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . getEnvironment ( ) == Triple :: GNUX32 ) return new ELF<ISA_LIT>_X32AsmBackend ( T


<s> void <ISA_LIT>AsmPrinter :: EmitSectionList ( Module & M , const std :: vector < <ISA_LIT>Section * > & SList ) { for ( unsigned i = <NUM_LIT> ; i < SList . size ( ) ; i ++ ) { if ( SList [ i ] -> getName ( ) . find ( <STR_LIT> ) != std :: string :: npos ) continue ; OutStreamer . AddBlankLine


<s> static SDValue PerformADDECombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI

, const <ISA_LIT>Subtarget * Subtarget ) {


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign

( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < Inst . getNumOperands ( ) ; ++ i ) { const MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isExpr ( ) ) hasExp = true ; if ( Op . isReg ( ) && Op . getReg ( ) ==


<s> if ( DL -> getOpcode ( ) != <STR_LIT> && DL -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue SV = DL -> getOperand ( <NUM_LIT> ) ; if ( SV . getOpcode ( ) != <STR_LIT> ) return false ; SDValue EV = SV . getOperand


<s> else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetWindows ( ) && ! Subtarget -> isTargetCygMing ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; typedef <ISA_LIT>COFFMachineModuleInfo :: externals_iterator externals_iterator ; for ( externals_iterator I = COFFMMI . externals_begin ( ) , E = COFFMMI . externals_end ( ) ; I != E ; ++ I ) { OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; SmallString < <NUM_LIT> > name ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; CallingConv :: ID CallConv = MBB . getParent ( ) -> getFunction ( ) -> getCallingConv ( ) ; assert ( CallConv == CallingConv :: <ISA_LIT>_PS || CallConv == CallingConv :: <ISA_LIT>_GS ) ; if ( ( Op . isImm ( ) ) ) { if ( Op . getImm ( ) & <NUM_LIT> ) { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } } else { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addOperand


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressBase ( SDValue N , <ISA_LIT>ISelAddressMode & AM , bool isRoot , unsigned Depth ) { if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base . Reg . getNode ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> && ! AM . isRIPRel ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return


<s> uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New


<s> static bool nextLEB ( int64_t & Val , ArrayRef < uint8_t > Bytes , uint64_t & Size , bool Signed ) { unsigned N = <NUM_LIT> ; const char * Error = nullptr ; Val = Signed ? decodeSLEB128 ( Bytes . data ( ) + Size , & N , Bytes . data ( ) + Bytes . size ( ) , & Error ) : static_cast < int64_t > ( decodeULEB128 ( Bytes . data ( ) + Size , & N , Bytes . data ( ) + Bytes . size ( ) , & Error ) ) ; if ( Error ) return false ; Size += N ; return true


<s> if ( NextElement == - <NUM_LIT> ) { NextElement = Mask [ i ] != <NUM_LIT> ? VectorType . getVectorNumElements ( ) : <NUM_LIT> ; IsZeroSideLeft = NextElement != <NUM_LIT> ; } if ( NextElement != Mask [ i ] ) return false ; NextElement ++


<s> bool <ISA_LIT>Disassembler :: isGFX10 ( )


<s> if ( <ISA_LIT>SinglePathInfo :: isEnabled ( ) ) { addPass ( create<ISA_LIT>SPMarkPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SinglePathInfoPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SPPreparePass ( get<ISA_LIT>TargetMachine (


<s> if ( code >= NUM_SPU_BUILTINS ) return error_mark_node ; return spu_builtin_decls [ code


<s> static unsigned getRn ( InsnType insn ) { return getBits ( insn , <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Inst . getParent ( ) -> getParent ( ) -> getTarget (


<s> for ( MachineInstr & MI : * Succ ) { if ( ! MI . isPHI ( ) ) break ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( )


<s> if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z'


<s> SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( PreservedSrc . getOpcode ( ) == <STR_LIT> ) PreservedSrc = getZeroVector (


<s> unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN ->


<s> assert ( get ( opcode ) . isBranch ( ) && <STR_LIT> ) ; if ( isEndLoopN ( opcode ) ) return true ; unsigned NewOpcode = getInvertedPredicatedOpcode ( opcode ) ; Cond [ <NUM_LIT> ] . setImm (


<s> if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc =


<s> gimple * fold_type ( gimple_folder & f ) const { T arg0 , arg1 ; if ( ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg0 ) || ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg1 ) ) return NULL ; if ( m_eq_p ? known_gt ( arg0 , arg1 ) : known_ge ( arg0 , arg1 ) ) return f . fold_to_pfalse ( ) ; if ( m_eq_p ? maybe_gt ( arg0 , arg1 ) : maybe_ge ( arg0 , arg1 ) ) return NULL ; poly_uint64 diff = arg1 - arg0 ; poly_uint64 nelts = GET_MODE_NUNITS ( f . vector_mode ( <NUM_LIT> ) ) ; if ( m_eq_p ) nelts -=


<s> auto UseAligned = [ & ] ( unsigned NeedAlign , unsigned HasAlign ) { return ! NeedsAligna && ( NeedAlign <= HasAlign ) ; } ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstHi ) . addFrameIndex

( FI ) . addImm ( Size ) . cloneMemRefs ( * MI ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI ,

const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> static bool DisassembleThumb2LdSt ( bool Load , MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { unsigned Rn = decodeRn ( insn ) ; if ( Thumb2PreloadOpcode ( Opcode ) ) return DisassembleThumb2PreLoad ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; if ( Load && Rn == <NUM_LIT> ) return DisassembleThumb2Ldpci ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; const TargetOperandInfo * OpInfo = TID . OpInfo ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool ThreeReg = ( OpInfo [ <NUM_LIT> ] . RegClass > <NUM_LIT> ) ; bool TIED_TO = ThreeReg && TID . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; bool Imm12 = ! ThreeReg && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; unsigned R0 , R1 , R2 = <NUM_LIT> ; unsigned Rd = decodeRd ( insn ) ; int Imm = <NUM_LIT> ; if ( ! Load && TIED_TO ) { R0 = Rn ; R1 = Rd ; } else { R0 = Rd ; R1 = Rn ; } if ( ThreeReg ) { if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else


<s> static inline int bpf_fib_lookup ( void * ctx , struct bpf_fib_lookup * param , int plen


<s> extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( REG_P ( recog_data . operand [ i ] ) ) { if ( GET_MODE ( recog_data . operand [ i ] ) == DImode && GENERAL_REG_P ( recog_data . operand [ i ] ) ) return <NUM_LIT> + <NUM_LIT> ; } else { if ( MEM_P ( recog_data . operand [ i ] ) && x86_extended_reg_mentioned_p ( recog_data . operand [ i ] ) ) return <NUM_LIT> + <NUM_LIT> ; } return <NUM_LIT> +


<s> } else { VecVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; } SDValue CtPop = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecVal ) ; SDValue UaddLV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , CtPop ) ; if ( VT == <STR_LIT> ) UaddLV = DAG . getNode ( <STR_LIT> , DL ,


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) { AlignmentIsInBytes = false


<s> if ( IsStackReg ( Op . getMemBaseReg ( ) ) ) Displacement -= OrigSPOffset ; if ( IsStackReg ( Op . getMemIndexReg ( ) ) ) Displacement -= OrigSPOffset * Op . getMemScale ( ) ; assert ( Displacement >= <NUM_LIT> ) ; if ( Displacement == <NUM_LIT> ) { EmitLEA ( Op , Size , Reg , Out ) ; return ; } int64_t Residue


<s> return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode ( <STR_LIT> ,


<s> void addRegVSFRCOperands ( MCInst & Inst , unsigned N )


<s> bool <ISA_LIT>InstPrinter :: printAlias ( const MCInst * MI , raw_ostream


<s> if ( RI . RegClass != nullptr && ! BadRC [ R ] ) { if ( RC -> LaneMask != RI . RegClass -> LaneMask ) { BadRC . set ( R ) ; RI . RegClass = nullptr ; } } else RI . RegClass = RC ; } } auto HasPartialOverlaps = [ this ] ( uint32_t Reg ) -> bool { for ( MCRegAliasIterator A ( Reg , & TRI , false ) ; A . isValid ( ) ; ++ A ) if ( ! TRI . isSubRegister ( Reg , * A ) && ! TRI . isSubRegister ( * A , Reg ) ) return true ; return


<s> EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; UpdateValueMap ( I , SrcReg ) ; return true


<s> std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const TargetData * TD = TM . getTargetData ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - TD -> getPointerSize ( ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT>