<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & ) const { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveTLSDescCall ( SMLoc L ) { StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return Error ( L , <STR_LIT>


<s> bool hasExtLSX ( ) const { return HasExtLSX


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> )

. getImm ( ) == <STR_LIT> ) return true ;


<s> if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return ( regno == GLOBAL_POINTER_REGNUM ? TARGET_CALL_SAVED_GP : ! call_really_used_regs [


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned isRead = ~ cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) & <NUM_LIT> ; if ( ! isRead && ( ! Subtarget -> hasV7Ops ( ) || ! Subtarget -> hasMPExtension ( ) ) ) return Op . getOperand ( <NUM_LIT> ) ; unsigned isData = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Subtarget -> isThumb ( ) ) { isRead = ~ isRead & <NUM_LIT> ; isData = ~ isData &


<s> assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ; } else { assert ( Op . isExpr ( )


<s> bool isALU ( const MachineInstr & MI ) const { if ( TII -> isALUInstr ( MI . getOpcode ( ) ) ) return true ; if ( TII -> isVector ( MI ) || TII -> isCubeOp ( MI . getOpcode (


<s> assert ( RegSplitParts . size ( ) + <NUM_LIT> >= EltDWORDs ) ; const std :: vector < int16_t > & Parts = RegSplitParts [ EltDWORDs - <NUM_LIT> ] ; const unsigned NumParts =


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; StringRef BiasedFlagStr = Tok . getString ( ) ; unsigned Biased = StringSwitch < unsigned > ( BiasedFlagStr . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT>


<s> return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT>


<s> static int getCompactUnwindRegNum ( const uint16_t * CURegs , unsigned Reg ) { for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ; return -


<s> if ( ! extended && n == <NUM_LIT> ) return arm_fp16_format == ARM_FP16_FORMAT_IEEE ? HFmode : VOIDmode ; return default_floatn_mode ( n ,


<s> static bool vax_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; xfoo1 = XEXP ( x , <NUM_LIT> ) ; if ( CONST_INT_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( CONST_INT_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; return true


<s> return CreateReg ( Index , RegKind_GPR , RegInfo


<s> __builtin_aarch64_st1v2si ( ( __builtin_aarch64_simd_si * ) a , (


<s> enum rs6000_builtins fn = ( enum rs6000_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; switch ( fn ) { case RS6000_BUILTIN_RSQRTF : if ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( V4SFmode ) && out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ ALTIVEC_BUILTIN_VRSQRTFP ] ; break ; case RS6000_BUILTIN_RSQRT : if ( VECTOR_UNIT_VSX_P ( V2DFmode ) && out_mode == DFmode && out_n == <NUM_LIT> && in_mode == DFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; break ; case RS6000_BUILTIN_RECIPF : if ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( V4SFmode ) && out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode && in_n == <NUM_LIT> ) return rs6000_builtin_decls [ ALTIVEC_BUILTIN_VRECIPFP ] ; break ; case


<s> bool <ISA_LIT>TargetAsmInfo < BaseTAI > :: LowerToBSwap ( CallInst * CI ) const { if ( CI -> getNumOperands ( ) != <NUM_LIT> || CI -> getType ( ) != CI -> getOperand ( <NUM_LIT> ) -> getType ( ) || ! CI -> getType ( ) -> isInteger ( ) ) return false ; const IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( ! Ty || Ty -> getBitWidth ( ) % <NUM_LIT> != <NUM_LIT> ) return false ; const Type * Tys [ ] = {


<s> BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MMI . addFrameInst ( DefCfa ) ) ; auto OffR31 = MCCFIInstruction :: createOffset ( FrameLabel , DwRAReg , - <NUM_LIT> ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MMI . addFrameInst ( OffR31 ) ) ; auto OffR30 = MCCFIInstruction :: createOffset ( FrameLabel , DwFPReg , - <NUM_LIT> ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MMI . addFrameInst ( OffR30 ) ) ; } static unsigned int RegsToMove [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( unsigned i = <NUM_LIT> ; RegsToMove [ i ] != <STR_LIT> ; ++ i ) { unsigned Reg = RegsToMove [ i ] ; auto IfR = [ Reg ] ( const CalleeSavedInfo & C ) -> bool { return C . getReg ( ) == Reg ; } ; auto F = std :: find_if ( CSI . begin ( ) , CSI . end ( ) , IfR ) ; if ( F == CSI . end ( ) ) continue ; int64_t Offset ; if ( HasFP ) { Offset = MFI . getObjectOffset ( F -> getFrameIdx ( ) ) ; } else { unsigned FrameReg ; Offset = getFrameIndexReference ( MF , F -> getFrameIdx ( ) , FrameReg ) ; } Offset -= <NUM_LIT> ; if ( Reg < <STR_LIT> || Reg > <STR_LIT> ) { unsigned DwarfReg = HRI . getDwarfRegNum ( Reg , true ) ; auto OffReg = MCCFIInstruction :: createOffset ( FrameLabel , DwarfReg , Offset ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MMI . addFrameInst ( OffReg ) ) ; } else { unsigned HiReg = HRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned LoReg = HRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned HiDwarfReg = HRI . getDwarfRegNum ( HiReg , true ) ; unsigned LoDwarfReg = HRI . getDwarfRegNum ( LoReg , true ) ; auto OffHi = MCCFIInstruction :: createOffset ( FrameLabel , HiDwarfReg , Offset + <NUM_LIT> ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MMI . addFrameInst ( OffHi ) ) ; auto OffLo = MCCFIInstruction :: createOffset ( FrameLabel ,


<s> bool hasPackedD16 ( const MCSubtargetInfo & STI ) { return ! STI . getFeatureBits ( ) [ <STR_LIT> ] && ! isCI ( STI ) && !


<s> std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameInfo ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameInfo ( Subtarget ) : ( <ISA_LIT>FrameInfo

* ) new Thumb1FrameInfo ( Subtarget ) ) {


<s> if ( TRI -> getEncodingValue ( DestReg ) < <NUM_LIT> ) { MIB -> setDesc ( LoadDesc ) ; } else { MIB -> setDesc ( BroadcastDesc ) ; DestReg = TRI -> getMatchingSuperReg ( DestReg , SubIdx , & <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; } return true


<s> <ISA_LIT>GenExtract ( ) : FunctionPass ( ID


<s> unsigned VR0 = MRI . createVirtualRegister ( RC ) ; unsigned VR1 = MRI . createVirtualRegister ( RC ) ; unsigned Dst = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Lo = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; unsigned Hi = RegInfo . getSubReg ( Dst , <STR_LIT> ) ; DebugLoc DL = I -> getDebugLoc ( ) ; const MCInstrDesc & Desc = TII . get ( TargetOpcode :: COPY ) ; TII . loadRegFromStack ( MBB , I , VR0 , FI , RC , &


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) << ShiftAmt >= <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( ! MRI -> use_empty ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } return I ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y (


<s> const char * rs6000_indirect_sibcall_template ( rtx * operands , unsigned


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile (


<s> break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : if ( ! Disable<ISA_LIT>FallthroughReturnOpt && & MBB == & MF . back ( ) && & MI == & MBB .

back ( ) ) MI . setDesc ( TII . get ( <STR_LIT> ) ) ;


<s> static SDValue buildPCRelGlobalAddress ( SelectionDAG & DAG , const GlobalValue * GV , SDLoc DL ,

unsigned Offset , EVT PtrVT , unsigned GAFlags = <ISA_LIT>InstrInfo :: MO_NONE ) {


<s> if ( flag_openacc && optval ) error (


<s> MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case RIT_<ISA_LIT>_64_Subtractor : { RelocationRef RelNext ; Obj -> getRelocationNext ( Rel . getRawDataRefImpl ( ) , RelNext ) ; RelocationEntry RENext = Obj -> getRelocation ( RelNext . getRawDataRefImpl ( ) ) ; unsigned RType = Obj -> getAnyRelocationType ( RENext ) ; if ( RType != RIT_<ISA_LIT>_64_Unsigned ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const MCExpr * LHS = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; symbol_iterator RSymI = RelNext . getSymbol ( ) ; uint64_t RSymAddr ; RSymI -> getAddress ( RSymAddr ) ; StringRef RSymName ; RSymI -> getName ( RSymName ) ; MCSymbol * RSym = Ctx . GetOrCreateSymbol ( RSymName ) ; if ( RSym -> isVariable ( ) == false ) RSym -> setVariableValue ( MCConstantExpr :: Create ( RSymAddr , Ctx ) ) ; const MCExpr * RHS = MCSymbolRefExpr :: Create ( RSym , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( LHS , RHS , Ctx ) ; break ; } default : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; break ; } return


<s> Result += ! isDuplexAGroup ( subInst1Opcode ) ; } else Result += Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT>

&& Type != <STR_LIT> && ( Type != <STR_LIT> || <ISA_LIT>MCInstrInfo :: isFloat ( MCII , ID ) ) ;


<s> if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; bool is31 = ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) ; if ( is<ISA_LIT>64 ) return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , is31 ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) ; else return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , is31 ? <STR_LIT> : <STR_LIT>


<s> TYPE_ATTRIBUTES ( t ) = make_attribute ( <STR_LIT> , <STR_LIT> ,


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter


<s> if ( COMPARISON_P ( x ) && GET_MODE ( x ) == VOIDmode ) PUT_MODE ( x , SImode ) ; int insn_code = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; if ( insn_code < <NUM_LIT> && COMPARISON_P ( x ) ) { machine_mode cmp_mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; if ( cmp_mode == VOIDmode ) cmp_mode = GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ; PUT_CODE ( x , reverse_condition ( GET_CODE ( x ) ) ) ; insn_code = recog ( PATTERN ( i ) , i , <NUM_LIT> ) ; append_nott = true ; } gcc_assert ( insn_code >= <NUM_LIT> ) ; } std :: pair < rtx_insn * , rtx_insn * > insnlist = sh_try_split_insn_simple ( i , curr_insn ) ; recog_data = prev_recog_data ; rtx_insn * nott_insn = sh_is_nott_insn ( insnlist . second ) ? insnlist .


<s> unsigned <ISA_LIT>TargetELFStreamer :: getEFlagsMesa3D ( ) { assert ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: Mesa3D ) ; return getEFlagsV3 (


<s> assert ( RestoreGPRs . LowGPR != RestoreGPRs . HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( HasFP ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm ( RestoreGPRs . GPROffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg != RestoreGPRs . LowGPR && Reg != RestoreGPRs . HighGPR && <STR_LIT> . contains ( Reg ) ) MIB . addReg (


<s> int match_type ; enum s390_builtin_ov_type_index type_index = type_for_overloaded_builtin_var [ bindex ] ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , ( int ) bindex ) ; match_type = s390_fn_types_compatible ( type_index , arglist ) ; if ( match_type == INT_MAX ) continue ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , match_type == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , match_type ) ; if ( match_type < last_match_type ) { num_matches = <NUM_LIT> ; last_match_type = match_type ; last_match_fntype_index = type_index ; last_match_index = bindex ; } else if ( match_type == last_match_type ) num_matches ++ ; } if ( last_match_type == INT_MAX ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } else if ( num_matches > <NUM_LIT> ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( ! TARGET_VXE && bflags_overloaded_builtin_var [ last_match_index ] & B_VXE ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( ! TARGET_VXE2 && bflags_overloaded_builtin_var [ last_match_index ] & B_VXE2 ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( bflags_overloaded_builtin_var [ last_match_index ] & B_DEP ) warning_at ( loc , <NUM_LIT> , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; if ( bt_for_overloaded_builtin_var [ last_match_index ] == S390_BUILTIN_MAX ) target_builtin_decl = ob_fndecl ; else target_builtin_decl = s390_builtin_decls [ bt_for_overloaded_builtin_var [ last_match_index ] ] ; all_op_flags = opflags_overloaded_builtin_var [ last_match_index ] ; return_type = s390_builtin_types [ s390_builtin_ov_types [ last_match_fntype_index ] [ <NUM_LIT> ] ] ; for ( i = <NUM_LIT> ; i < ob_args_num ; i ++ ) { unsigned int op_flags = all_op_flags & ( ( <NUM_LIT> << O_SHIFT ) - <NUM_LIT> ) ; tree arg = ( * arglist ) [ i ] ; tree type = s390_builtin_types [ s390_builtin_ov_types [ last_match_fntype_index ] [ i + <NUM_LIT> ] ] ; all_op_flags = all_op_flags >> O_SHIFT ; if ( op_flags == O_ELEM ) { int n_elem = s390_vec_n_elem ( target_builtin_decl ) ; gcc_assert ( n_elem > <NUM_LIT> ) ; gcc_assert ( type == integer_type_node ) ; ( * arglist ) [ i ] = build2 ( BIT_AND_EXPR , integer_type_node , fold_convert ( integer_type_node , arg ) , build_int_cst ( NULL_TREE , n_elem - <NUM_LIT> ) ) ; } if ( TREE_CODE ( arg ) != INTEGER_CST ||


<s> assert ( getGeneration ( ) <= NORTHERN_ISLANDS ) ; switch ( getWavefrontSize ( ) ) { case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return hasCaymanISA ( ) ? <NUM_LIT>


<s> rtx op1 = expand_normal ( arg1 ) ; rtx op2 = expand_normal ( arg2 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return NULL_RTX ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return NULL_RTX ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 =


<s> static void mips_sim_init ( struct mips_sim * state , state_t dfa_state ) { state -> issue_rate = mips_issue_rate (


<s> if ( getGeneration ( ) >= SOUTHERN_ISLANDS ) return static_cast < const <ISA_LIT>Subtarget * > ( this ) ->


<s> rtx old_reg , new_reg , cmp_reg , ar_ccv , label ; enum insn_code icode ; if ( ( mode == SImode || mode == DImode ) && ( code == PLUS || code == MINUS ) && fetchadd_operand ( val , mode ) ) { if ( code == MINUS ) val = GEN_INT ( - INTVAL ( val ) ) ; if ( ! old_dst ) old_dst = gen_reg_rtx ( mode ) ; switch ( model ) { case MEMMODEL_ACQ_REL : case MEMMODEL_SEQ_CST : case MEMMODEL_SYNC_SEQ_CST : emit_insn ( gen_memory_barrier ( ) ) ; case MEMMODEL_RELAXED : case MEMMODEL_ACQUIRE : case MEMMODEL_SYNC_ACQUIRE : case MEMMODEL_CONSUME : if ( mode == SImode ) icode = CODE_FOR_fetchadd_acq_si ; else icode = CODE_FOR_fetchadd_acq_di ; break ; case MEMMODEL_RELEASE : case MEMMODEL_SYNC_RELEASE : if ( mode == SImode ) icode = CODE_FOR_fetchadd_rel_si ; else icode = CODE_FOR_fetchadd_rel_di ; break ; default : gcc_unreachable ( ) ; } emit_insn ( GEN_FCN ( icode ) ( old_dst , mem , val ) ) ; if ( new_dst ) { new_reg = expand_simple_binop ( mode , PLUS , old_dst , val , new_dst , true , OPTAB_WIDEN ) ; if ( new_reg != new_dst ) emit_move_insn ( new_dst , new_reg ) ; } return ; } gcc_assert ( is_mm_relaxed ( model ) || is_mm_release ( model ) || MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg = cmp_reg ; if ( code == NOT ) { new_reg = expand_simple_binop ( DImode , AND , new_reg , val , NULL_RTX , true , OPTAB_DIRECT ) ; new_reg = expand_simple_unop ( DImode , code , new_reg , NULL_RTX ,


<s> return getWavesPerWorkGroup ( FlatWorkGroupSize ) ==


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc dl = Orig -> getDebugLoc ( ) ; if ( Orig -> getOpcode ( ) == <STR_LIT> ) { RI . emitLoadConstPool ( MBB , I , DestReg , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getImm ( ) , Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) , this , false , dl ) ; return ; } MachineInstr * MI = MBB . getParent ( )


<s> ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregxiv8hi


<s> for ( unsigned I = <NUM_LIT> ; I != NumElems ; ++ I ) { if ( UndefElts [ I ] || EltBits [ I ] . uge ( SVTBits ) ) continue ; uint64_t ShAmt = EltBits [ I ] . getZExtValue ( ) ; Elts [ I ] = DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i , dl ) ) ; } } return V ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt , LastElt ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i -


<s> return ( __m128i ) __builtin_ia32_pminuw128_mask ( ( __v8hi ) __A , ( __v8hi )


<s> return DAG . getLoad ( Op . getValueType ( ) , dl , RLI . Chain , RLI . Ptr , RLI . MPI , false , false , RLI . IsInvariant , RLI . Alignment , RLI . AAInfo ,


<s> void addSImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr >


<s> XVECEXP ( p , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_REG ( SImode , regno ) ; XVECEXP ( p , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_REG ( SImode , regno


<s> static bool indirectable_address_p ( rtx x , bool strict , bool indirect ) { if ( indirectable_constant_address_p ( x , indirect ) ||

BASE_REGISTER_P ( x , strict ) ) return true ;


<s> rtx cris_return_addr_rtx ( int count , rtx frameaddr ATTRIBUTE_UNUSED ) { cfun -> machine -> needs_return_address_on_stack = <NUM_LIT> ; return count == <NUM_LIT> ? gen_rtx_MEM ( Pmode , plus_constant ( Pmode , virtual_incoming_args_rtx , - <NUM_LIT> )


<s> return NULL_TREE ; } tree size = TREE_VALUE ( args ) ; if ( TREE_CODE ( size ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return NULL_TREE ; } unsigned HOST_WIDE_INT value = tree_to_uhwi ( size ) ; if ( maybe_ne ( value , BITS_PER_SVE_VECTOR ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; return NULL_TREE ; } if ( lang_GNU_C ( ) && VECTOR_BOOLEAN_TYPE_P ( type ) ) type = build_variant_type_copy ( type ) ; else type = build_distinct_type_copy ( type ) ; TYPE_ATTRIBUTES ( type ) = remove_attribute ( <STR_LIT> , copy_list ( TYPE_ATTRIBUTES ( type ) ) ) ; if ( ! VECTOR_BOOLEAN_TYPE_P ( type ) ) TYPE_INDIVISIBLE_P ( type ) = <NUM_LIT> ; * node = type ; return NULL_TREE


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { if ( ! Subtarget -> useConstIslands ( ) ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs ( MIB


<s> std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; auto ABIName = Options . MCOptions . getABIName ( ) ; if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) { auto TargetABI = <STR_LIT> ( ABIName ) ; if ( TargetABI != <STR_LIT> && ModuleTargetABI -> getString ( )


<s> SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ResultLo = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0Lo , Op1Lo ) ; SDValue ResultHi = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT ,


<s> default : return MatchOperand_NoMatch ; case AsmToken :: LParen : case AsmToken :: Dot : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Percent : return parseOperandWithModifier (


<s> BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } unsigned NewStateReg = extractPredStateFromSP ( MBB , InsertPt , Loc ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addSym ( RetSymbol ) ; } else { Register ActualRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ActualRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addReg ( ActualRetAddrReg , RegState :: Kill ) ; } int PredStateSizeInBytes = TRI -> getRegSizeInBits ( * PS -> RC ) / <NUM_LIT> ; auto CMovOp = <STR_LIT> ( PredStateSizeInBytes ) ; Register UpdatedStateReg = MRI -> createVirtualRegister ( PS -> RC


<s> bool GCNTTIImpl :: isInlineAsmSourceOfDivergence ( const CallInst * CI , ArrayRef < unsigned > Indices ) const { if ( Indices . size ( ) > <NUM_LIT> ) return true ; const DataLayout & DL = CI -> getModule ( ) -> getDataLayout ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST -> getRegisterInfo ( ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = TLI -> ParseConstraints ( DL , ST -> getRegisterInfo ( ) , * CI ) ; const int TargetOutputIdx = Indices . empty ( ) ? - <NUM_LIT> : Indices [ <NUM_LIT> ] ; int OutputIdx = <NUM_LIT> ; for ( auto & TC : TargetConstraints ) { if ( TC . Type != InlineAsm :: isOutput ) continue ; if ( TargetOutputIdx != - <NUM_LIT> && TargetOutputIdx != OutputIdx ++ ) continue ; TLI -> ComputeConstraintToUse ( TC , SDValue ( ) ) ; Register AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = TLI -> getRegForInlineAsmConstraint ( TRI , TC . ConstraintCode , TC .


<s> static void sparc_file_end ( void ) { if ( got_helper_needed ) { const char * name = XSTR ( got_helper_rtx , <NUM_LIT> ) ; bool do_cfi ; if ( USE_HIDDEN_LINKONCE ) { tree decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ; DECL_VISIBILITY_SPECIFIED ( decl ) = <NUM_LIT> ; resolve_unique_section ( decl , <NUM_LIT> , flag_function_sections ) ; allocate_struct_function ( decl , true ) ; cfun -> is_thunk = <NUM_LIT> ; current_function_decl =


<s> translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_IRC : mcInst . addOperand ( MCOperand :: createImm ( insn . RC ) ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ; case ENCODING_DI : return translateDstIndex ( mcInst , insn ) ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : case ENCODING_Rv : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ; case ENCODING_CC : mcInst . addOperand ( MCOperand :: createImm ( insn . immediates [ <NUM_LIT> ] ) ) ; return false ; case ENCODING_FP : translateFPRegister ( mcInst , insn . modRM & <NUM_LIT> ) ; return false ; case ENCODING_VVVV : translateRegister ( mcInst , insn . vvvv ) ; return false ; case ENCODING_DUP : return translateOperand ( mcInst , insn . operands [ operand . type - TYPE_DUP0 ]


<s> Ordered [ <NUM_LIT> ] = ExpInstrTypesSeen == <NUM_LIT> ; Ordered [ <NUM_LIT> ] = false ; Counters Counts = WaitCounts ; bool NeedWait = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Required . Array [ i ] <= WaitedOn . Array [ i ] ) continue ; NeedWait = true ; if ( Ordered [ i ] ) { unsigned Value = LastIssued . Array [ i ] - Required . Array [ i ] ; Counts . Array [ i ] = std :: min ( Value , WaitCounts . Array [ i ] ) ; } else Counts . Array [ i ] = <NUM_LIT> ; WaitedOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; } if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ( Counts . Named . VM & <NUM_LIT> ) | ( ( Counts . Named . EXP & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Counts . Named . LGKM & <NUM_LIT> ) << <NUM_LIT> ) ) ; LastOpcodeType = OTHER


<s> TYPE_SATURATING ( * node ) = sat_p ; TYPE_UNSIGNED ( * node ) = UNSIGNED_FIXED_POINT_MODE_P ( mode ) ; TYPE_IBIT ( * node ) = GET_MODE_IBIT ( mode ) ; TYPE_FBIT ( * node ) = GET_MODE_FBIT ( mode ) ; TYPE_PRECISION ( * node ) = GET_MODE_BITSIZE ( mode ) ; SET_TYPE_ALIGN ( * node


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { UpdateValueMap ( I , InputReg ) ; return true ; } if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ; } unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , InputReg , true , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ; return true


<s> rtx x ; gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , true ) ; x = DECL_RTL ( imp_decl ) ; if ( want_reg ) x = force_reg ( Pmode ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( HasAVX2 ) return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( HasAVX2 ) return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> BranchPredicate Pred = static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; if ( Pred == VCCZ || Pred == SCC_FALSE ) { Pred = static_cast < BranchPredicate > ( - Pred ) ; std :: swap ( TrueReg , FalseReg ) ; } MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( DstReg ) ; unsigned DstSize = RI . getRegSizeInBits ( * DstRC ) ; if ( DstSize == <NUM_LIT> ) { unsigned SelOp = Pred == SCC_TRUE ? <STR_LIT> : <STR_LIT> ; MachineInstr * Select = BuildMI ( MBB , I , DL , get ( SelOp ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } if ( DstSize == <NUM_LIT> && Pred == SCC_TRUE ) { MachineInstr * Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { return false


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF

, const MCAsmLayout & Layout ) const override {


<s> Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) { const MachineInstrBuilder & MIB = BuildMI ( MBB , I , DL , get ( Opcode ) ) ; AddSubReg ( MIB , DestReg , Indices [ SubReg ] , RegState :: Define , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , <NUM_LIT> , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , getKillRegState (


<s> CCInfo . AllocateReg ( InputPtrRegLo ) ; CCInfo . AllocateReg ( InputPtrRegHi ) ; CCInfo . AllocateReg ( ScratchPtrRegLo ) ; CCInfo . AllocateReg ( ScratchPtrRegHi ) ; MF . addLiveIn ( InputPtrReg , & AMDGPU :: SReg_64RegClass ) ; MF . addLiveIn ( ScratchPtrReg , & AMDGPU :: SReg_64RegClass ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , Splits ) ; } AnalyzeFormalArguments ( CCInfo , Splits ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped [ i ] ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; MVT VT = VA . getLocVT ( ) ; if ( VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = Splits [ i ] . VT ; const unsigned Offset = <NUM_LIT> + VA . getLocMemOffset ( ) ; SDValue Arg = LowerParameter ( DAG , VT , MemVT , DL , DAG . getRoot ( ) , Offset , Ins [ i ] . Flags . isSExt ( ) ) ; const PointerType * ParamTy = dyn_cast < PointerType > ( FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ) ; if ( Subtarget -> getGeneration ( ) == AMDGPUSubtarget :: SOUTHERN_ISLANDS && ParamTy && ParamTy -> getAddressSpace ( ) == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , Arg . getValueType ( ) , Arg , DAG . getValueType ( <STR_LIT> ) ) ; } InVals . push_back ( Arg ) ; Info -> ABIArgOffset = Offset + MemVT . getStoreSize ( ) ; continue ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; unsigned Reg = VA . getLocReg ( ) ; if ( VT == <STR_LIT> ) { Reg = TRI -> getMatchingSuperReg ( Reg , AMDGPU :: sub0 , & AMDGPU :: SReg_64RegClass ) ; Reg = MF . addLiveIn ( Reg , & AMDGPU :: SReg_64RegClass ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ) ; continue ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg


<s> bool hasFPUv3HalfWord ( ) const { return HasFPUv3HalfWord


<s> bool isCK802 ( ) const { return <ISA_LIT>ProcFamily ==


<s> } else if ( N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , Imm ) && ( ! EncodingAlignment || isAligned ( * EncodingAlignment , Imm ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown .


<s> uint64_t currTextBegin = currTextFrag -> getParent ( ) -> getSection ( ) . addr ( ) + currTextFrag -> getOffset ( ) ; if ( currTextBegin > prevTextEnd ) { RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . insert ( it , frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) , * FragmentRef :: Create ( * frag , <NUM_LIT> ) , <NUM_LIT> ) ; reloc -> setSymInfo ( CreateLocalSymbolToFragmentEnd ( pModule , * prevTextFrag ) ) ; addExtraRelocation ( reloc ) ; } prevTextEnd = currTextBegin + currTextFrag -> size ( ) ; prevTextFrag = currTextFrag ; ++ it ; } RegionFragment * frag = new RegionFragment ( cantUnwindRegion , nullptr ) ; frag -> setParent ( sectData ) ; list . push_back ( frag ) ; Relocation * reloc = Relocation :: Create ( static_cast < uint32_t > ( llvm :: ELF :: R_<ISA_LIT>_PREL31 ) , * FragmentRef ::


<s> } bool Recorded = false ; for ( iterator I = AVs . begin ( ) , E = AVs . end ( ) ; I != E ; ++ I ) { unsigned SrcR = * I ; int FDi = - <NUM_LIT> , LDi = - <NUM_LIT> ; const BitTracker :: RegisterCell & AC = CMS -> lookup ( SrcR ) ; uint16_t AW = AC . width ( ) ; for ( uint16_t i = <NUM_LIT> , w = std :: min ( W , AW ) ; i < w ; ++ i ) { if ( RC [ i ] == AC [ i ] ) continue ; if ( FDi == - <NUM_LIT> ) FDi = i ; LDi = i ; } if ( FDi == - <NUM_LIT> ) continue ; uint16_t FD = FDi , LD = LDi ; uint16_t MinL = LD - FD + <NUM_LIT> ; for ( uint16_t L = MinL ; L < W ; ++ L ) { LRSMapType :: iterator F = LM . find ( L ) ; if ( F == LM . end ( ) ) continue ; RSListType & LL = F -> second ; for ( unsigned i = <NUM_LIT> , n = LL . size ( ) ; i < n ; ++ i ) { uint16_t S = LL [ i ] . second ; if ( S > FD ) continue ; uint16_t EL = L - MinL ; uint16_t LowS = ( EL < FD ) ? FD - EL : <NUM_LIT> ; if ( S < LowS ) continue ; unsigned InsR = LL [ i ] . first ; if ( ! isValidInsertForm ( VR , SrcR , InsR , L , S ) ) continue ; if ( isDebug ( ) ) { dbgs ( ) << PrintReg ( VR , HRI ) << <STR_LIT> << PrintReg ( SrcR , HRI ) << ',' << PrintReg ( InsR

, HRI ) << <STR_LIT> << L << <STR_LIT> << S << <STR_LIT> ;


<s> const MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler

& Mang , const TargetMachine & TM ) const {


<s> if ( Scope . equals ( <STR_LIT> ) ) return false ; if ( Scope . equals ( <STR_LIT> ) ) return true ; assert ( Scope . equals ( <STR_LIT> ) && <STR_LIT> ) ; for ( const auto & Info : MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ) if ( Info . getReg (


<s> MCInst LabelInst ; LabelInst . setOpcode ( <STR_LIT> ) ; LabelInst . addOperand ( MCOperand :: createReg ( MAI -> getOrCreateMBBRegister ( MBB ) ) ) ; outputMCInst ( LabelInst


<s> case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MI , MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MI , MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; case MachineOperand :: MO_GlobalAddress : return LowerSymbolOperand ( MI , MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return LowerSymbolOperand ( MI , MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_MachineBasicBlock : return LowerSymbolOperand ( MI , MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; case MachineOperand :: MO_RegisterMask : break ; } return MCOperand (


<s> tree field = NULL_TREE , field_chain = NULL_TREE ; int i ; tree type = make_node ( RECORD_TYPE ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ i ] ) , unsigned_type_node ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; } field = build_decl ( UNKNOWN_LOCATION , FIELD_DECL , get_identifier ( field_name [ <NUM_LIT> ] ) , build_array_type ( unsigned_type_node , build_index_type ( size_one_node ) ) ) ; if ( field_chain != NULL_TREE ) DECL_CHAIN ( field ) = field_chain ; field_chain = field ; finish_builtin_struct ( type , <STR_LIT> , field_chain ,


<s> return std :: find ( table . begin ( ) , table . end ( ) , CPU ) != table .


<s> for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return <NUM_LIT> ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return <NUM_LIT> ; } return


<s> if ( AR . Reg == BR . Reg ) { LaneBitmask M = AR . Mask & BR . Mask ; return M . any ( ) ? RegisterRef ( AR . Reg , M ) : RegisterRef ( ) ; } RegisterRef NAR = PRI . normalize ( AR ) ; RegisterRef NBR = PRI . normalize (


<s> MachineBasicBlock * BB = I . getParent ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Src1Ty = MRI -> getType ( Src1Reg ) ; unsigned DstSize = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; unsigned InsSize = Src1Ty . getSizeInBits ( ) ; int64_t Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || InsSize % <NUM_LIT> != <NUM_LIT> ) return false ; if ( InsSize > <NUM_LIT> ) return false ; unsigned SubReg = TRI . getSubRegFromChannel ( Offset / <NUM_LIT> , InsSize / <NUM_LIT> ) ; if ( SubReg ==


<s> return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= <NUM_LIT> && INTVAL ( op ) <= <NUM_LIT> ) ) ; return ( ( GET_CODE ( op ) == CONST_INT && INTVAL ( op ) >= <NUM_LIT> ) || ( GET_CODE ( op ) ==

CONST_DOUBLE && CONST_DOUBLE_HIGH ( op ) == <NUM_LIT> ) ) ;


<s> case EQ : case NE : case GTU : case LTU : case GEU : case LEU : return <NUM_LIT> ; case GT : case LT : case GE : case LE : return ! ( cc_prev_status .


<s> return nullptr ; } const TargetRegisterClass * DstRC = getRegClassForTypeOnBank ( ScalarTy , DstRB , RBI , true ) ; if ( ! DstRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } const RegisterBank & VecRB = * RBI . getRegBank ( VecReg , MRI , TRI ) ; const LLT & VecTy = MRI . getType ( VecReg ) ; const TargetRegisterClass * VecRC = getRegClassForTypeOnBank ( VecTy , VecRB , RBI , true ) ; if ( ! VecRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertReg = VecReg ; if ( ! DstReg ) DstReg = MRI . createVirtualRegister ( DstRC ) ; if ( LaneIdx == <NUM_LIT> ) { auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { * DstReg } , { } ) . addReg ( VecReg , <NUM_LIT> , ExtractSubReg ) ; RBI . constrainGenericRegister ( * DstReg , * DstRC , MRI ) ; return &


<s> unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT>


<s> } NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; } NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign


<s> if ( TARGET_32BIT ) arm32_output_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; else arm_thumb1_mi_thunk ( file , thunk ,


<s> bool IsTable = false ; if ( GlobalVT -> isArrayTy ( ) && <STR_LIT> ( GlobalVT -> getArrayElementType ( ) ) ) { MVT VT ; IsTable = true ; switch ( GlobalVT -> getArrayElementType ( ) -> getPointerAddressSpace ( ) ) { case <STR_LIT> :: WASM_ADDRESS_SPACE_FUNCREF : VT = <STR_LIT> ; break ; case <STR_LIT> :: WASM_ADDRESS_SPACE_EXTERNREF : VT = <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; } Type = <STR_LIT> ( VT ) ; } else if ( VTs . size ( ) == <NUM_LIT> ) { Type = <STR_LIT> ( VTs [ <NUM_LIT> ] ) ; } else report_fatal_error ( <STR_LIT> ) ; if ( IsTable ) { Sym -> setType ( <STR_LIT> ) ; Sym -> setTableType ( Type ) ; }


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; FrameReg = <STR_LIT> ; return MFI . getObjectOffset ( FI )


<s> if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || startswith ( section , <STR_LIT> ) || startswith ( section , <STR_LIT> ) || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || startswith ( section , <STR_LIT> ) || startswith ( section , <STR_LIT> ) ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes (


<s> EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc


<s> <ISA_LIT>PostRAScavenging ( ) : MachineFunctionPass (


<s> const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | MO_NC ) ) ; } SDValue Hi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; SDValue Lo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP


<s> bool in<ISA_LIT>16ModeDefault ( ) const


<s> Lv -> PredReg = Terminator -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Lv -> Polarity = ! Terminator -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Lv -> IsPredicated = true ; } Terminator -> removeFromParent


<s> if ( V . getOperand ( <NUM_LIT> ) != V . getOperand ( <NUM_LIT> ) || ! V -> isOnlyUserOf ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; Chain . push_back ( V ) ; V = V . getOperand ( <NUM_LIT> ) ; do { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( V . getOpcode ( ) == CombineOp ) break ; Chain . push_back ( V ) ; case <STR_LIT> : V = V . getOperand ( <NUM_LIT> ) ; continue ; } break ; } while ( V . hasOneUse ( ) ) ; break ; } break ; } if ( ! V . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > VMask = getPSHUFShuffleMask ( V ) ; for ( int & M : Mask ) M = VMask [ M ] ; V = DAG . getNode ( V . getOpcode ( ) , DL , V . getValueType ( ) , V . getOperand ( <NUM_LIT> ) , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; while ( ! Chain . empty ( ) ) { SDValue W = Chain . pop_back_val ( ) ; if ( V . getValueType ( ) != W . getOperand ( <NUM_LIT> ) . getValueType ( ) ) V = DAG . getBitcast ( W . getOperand ( <NUM_LIT> ) . getValueType ( ) , V ) ; switch ( W . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT>


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue TgtBA = DAG . getBlockAddress ( BA , PtrVT , true ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; const TargetMachine & TM = DAG . getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > (


<s> if ( SMPos0 != SMPos1 || SMSize0 != SMSize1 ) return SDValue ( ) ; SDValue Shl = And1 . getOperand ( <NUM_LIT> ) ; if ( Shl . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; unsigned Shamt = CN -> getZExtValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( ( Shamt != SMPos0 ) || ( SMPos0 + SMSize0 > ValTy . getSizeInBits ( ) )


<s> auto MinPhysReg = [ this ] ( RegisterRef RR ) -> unsigned { const TargetRegisterInfo & TRI = DFG . getTRI ( ) ; const TargetRegisterClass & RC = * TRI . getMinimalPhysRegClass ( RR . Reg ) ; if ( ( RC . LaneMask & RR . Mask ) == RC . LaneMask ) return RR . Reg ; for ( MCSubRegIndexIterator S ( RR . Reg , & TRI ) ; S . isValid ( ) ; ++ S ) if ( RR . Mask == TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ) return S . getSubReg ( ) ; llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ; } ; for ( auto C : Copies ) { if ( HasLimit && CpCount >= CpLimit ) break ; auto SA = DFG . addr < InstrNode * > ( C ) ; auto FS = CopyMap . find ( SA . Id ) ; if ( FS == CopyMap . end ( ) ) continue ; EqualityMap & EM = FS -> second ; for ( NodeAddr < DefNode * > DA : SA . Addr -> members_if ( DFG . IsDef , DFG ) ) { RegisterRef DR = DA . Addr -> getRegRef ( DFG ) ; auto FR = EM . find ( DR ) ; if ( FR == EM . end ( ) ) continue ; RegisterRef SR = FR -> second ; if ( DR == SR ) continue ; auto & RDefSR = RDefMap [ SR ] ; NodeId RDefSR_SA = RDefSR [ SA . Id ] ; for ( NodeId N = DA . Addr -> getReachedUse ( ) , NextN ; N ; N = NextN ) { auto UA = DFG . addr < UseNode * > ( N ) ; NextN = UA . Addr -> getSibling ( ) ; uint16_t F = UA . Addr -> getFlags ( ) ; if ( ( F & NodeAttrs :: PhiRef ) || ( F & NodeAttrs :: Fixed ) ) continue ; if ( UA . Addr -> getRegRef ( DFG ) != DR ) continue ; NodeAddr < InstrNode * > IA = UA . Addr ->


<s> <ISA_LIT>InstructionLookupBuilder ( ) : NumWritten ( <NUM_LIT> ) { Mask . fill ( <NUM_LIT>


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( * TM . getDataLayout ( ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - <NUM_LIT> : - <NUM_LIT> ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles ::


<s> Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , SafeShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Cond = DAG . getSetCC ( dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue Hi , Lo ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Cond , Tmp3 , Tmp2 ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VT , Cond , Tmp1 , Tmp3 ) ; }


<s> CPUDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasEFPU2 = false ; HasFPU = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasMMA = false ; HasROPProtect = false ; HasPrivileged = false ; HasP10Vector = false ; HasPrefixInstrs = false ; HasPCRelativeMemops = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; AllowsUnalignedFPAccess = false ; DeprecatedDST = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasQuadwordAtomics = false ; HasDirectMove = false ; HasHTM = false ; HasFloat128 = false ; HasFusion = false ; HasStoreFusion = false ; HasAddiLoadFusion = false ; HasAddisLoadFusion =


<s> unsigned <ISA_LIT>CodeEmitter :: getSimm19Lsl2Encoding ( const MachineInstr & MI , unsigned OpNo ) const { llvm_unreachable ( <STR_LIT>


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addImm ( Hi ) ; return


<s> std :: bitset < <NUM_LIT> > Bits ( GetImplicitBits ( * this ) ) ; Bits . set ( packetBeginIndex , f


<s> const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) { APInt ImmS = Imm . ashr ( Imm . countTrailingZeros


<s> bool enableMachineScheduler ( ) const


<s> case MODE_VECTOR_FLOAT : if ( ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) || ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) || ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) || ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) || ( TARGET_MMX && VALID_MMX_REG_MODE ( mode ) ) ) units = GET_MODE_SIZE ( mode ) ; } return COSTS_N_INSNS ( CEIL ( GET_MODE_SIZE ( mode ) ,


<s> return true ; case MOD : case DIV : case UMOD : case UDIV : if ( TARGET_V850E && ! speed ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case MULT : if ( TARGET_V850E && ( mode == SImode || mode == HImode || mode == QImode ) ) { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) * total = <NUM_LIT> ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { if ( CONST_OK_FOR_O ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) * total = <NUM_LIT> ; else if ( CONST_OK_FOR_K ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) * total = <NUM_LIT> ; } } else * total = <NUM_LIT> ; return true ; case ZERO_EXTRACT : if ( outer_code == COMPARE )


<s> if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return


<s> const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT>

) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( isMClass ( ) ) { unsigned FlagsVal = StringSwitch < unsigned > ( Mask ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = LowercaseString ( Mask . slice ( Start , Next ) ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( ! FlagsVal ) FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success


<s> } case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF12 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_THM_BF18 ; } } switch ( Kind ) { default : Ctx . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS8 ; } case FK_Data_2 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS16 ; } case FK_Data_4 : switch ( Modifier ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : return ELF :: R_<ISA_LIT>_NONE ; case MCSymbolRefExpr :: VK_GOT : return ELF :: R_<ISA_LIT>_GOT_BREL ; case MCSymbolRefExpr :: VK_TLSGD : return ELF :: R_<ISA_LIT>_TLS_GD32 ; case MCSymbolRefExpr :: VK_TPOFF : return ELF :: R_<ISA_LIT>_TLS_LE32 ; case MCSymbolRefExpr :: VK_GOTTPOFF : return ELF :: R_<ISA_LIT>_TLS_IE32 ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_ABS32 ; case MCSymbolRefExpr :: VK_GOTOFF : return ELF :: R_<ISA_LIT>_GOTOFF32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : return ELF :: R_<ISA_LIT>_GOT_PREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : return ELF :: R_<ISA_LIT>_TARGET1 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 : return ELF :: R_<ISA_LIT>_TARGET2 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 : return ELF :: R_<ISA_LIT>_PREL31 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL : return ELF :: R_<ISA_LIT>_SBREL32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDO : return ELF :: R_<ISA_LIT>_TLS_LDO32 ; case MCSymbolRefExpr :: VK_TLSCALL : return ELF :: R_<ISA_LIT>_TLS_CALL ; case MCSymbolRefExpr :: VK_TLSDESC : return ELF :: R_<ISA_LIT>_TLS_GOTDESC ; case MCSymbolRefExpr :: VK_TLSLDM : return ELF :: R_<ISA_LIT>_TLS_LDM32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSDESCSEQ


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return &


<s> if ( ! mi_match ( DstReg , MRI , m_GTrunc ( m_Reg ( SrcReg ) ) ) ) return false ; return MRI . getType ( SrcReg ) . getSizeInBits


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t _OSABI , StringRef CPU ) : <ISA_LIT>AsmBackend ( T , CPU ) , OSABI ( _OSABI ) { HasReliableSymbolDifference = true


<s> MachineBasicBlock * MBB = I -> getParent ( ) ; ++ I ; for ( MachineInstr * MI : InstsToMove ) { MI -> removeFromParent ( ) ; MBB -> insert ( I


<s> case ShaderType :: VERTEX : RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS ; break ; } unsigned LDSAlignShift ; if ( STM . getGeneration ( ) < AMDGPUSubtarget :: SEA_ISLANDS ) { LDSAlignShift = <NUM_LIT> ; } else { LDSAlignShift = <NUM_LIT> ; } unsigned LDSBlocks = RoundUpToAlignment ( MFI -> LDSSize , <NUM_LIT> << LDSAlignShift ) >> LDSAlignShift ; if ( MFI -> getShaderType ( ) == ShaderType :: COMPUTE ) { OutStreamer . EmitIntValue ( R_00B848_COMPUTE_PGM_RSRC1 , <NUM_LIT> ) ; const uint32_t ComputePGMRSrc1 = S_00B848_VGPRS ( KernelInfo . NumVGPR / <NUM_LIT> ) | S_00B848_SGPRS ( KernelInfo . NumSGPR / <NUM_LIT> ) | S_00B848_PRIORITY ( KernelInfo . Priority ) | S_00B848_FLOAT_MODE ( KernelInfo . FloatMode ) | S_00B848_PRIV ( KernelInfo . Priv ) | S_00B848_DX10_CLAMP ( KernelInfo . DX10Clamp ) | S_00B848_IEEE_MODE ( KernelInfo . DebugMode ) | S_00B848_IEEE_MODE ( KernelInfo . IEEEMode ) ; OutStreamer . EmitIntValue ( ComputePGMRSrc1 , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( R_00B84C_COMPUTE_PGM_RSRC2 , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( S_00B84C_LDS_<ISA_LIT>ZE ( LDSBlocks ) ,


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> else { regno = GP_ARG_LAST + <NUM_LIT> ; break ; } } next_arg_reg = iq2000_function_arg ( args_so_far , VOIDmode , void_type_node , true ) ; if ( next_arg_reg != <NUM_LIT> && GET_CODE ( next_arg_reg ) == PARALLEL ) { rtvec adjust = XVEC ( next_arg_reg , <NUM_LIT> ) ; int num = GET_NUM_ELEM ( adjust ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) { rtx pattern ; pattern = RTVEC_ELT ( adjust , i ) ; if ( GET_CODE ( pattern ) != SET || GET_CODE ( SET_SRC ( pattern ) ) != ASHIFT ) abort_with_insn ( pattern , <STR_LIT> ) ; PUT_CODE ( SET_SRC ( pattern ) , ASHIFTRT ) ; emit_insn ( pattern ) ; } } tsize = compute_frame_size ( get_frame_size ( ) ) ; if ( store_args_on_stack && ( stdarg_p ( fntype ) || last_arg_is_vararg_marker ) ) { int offset = ( regno - GP_ARG_FIRST ) * UNITS_PER_WORD ; rtx ptr = stack_pointer_rtx ; for ( ; regno <= GP_ARG_LAST ; regno ++ ) { if ( offset != <NUM_LIT> ) ptr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; emit_move_insn ( gen_rtx_MEM ( gpr_mode , ptr ) , gen_rtx_REG ( gpr_mode , regno ) ) ; offset += GET_MODE_SIZE ( gpr_mode ) ; } } if ( tsize > <NUM_LIT> ) { rtx tsize_rtx = GEN_INT ( tsize ) ; rtx adjustment_rtx , dwarf_pattern ; rtx_insn * insn ; if ( tsize > <NUM_LIT> ) { adjustment_rtx = gen_rtx_REG ( Pmode , IQ2000_TEMP1_REGNUM ) ; emit_move_insn ( adjustment_rtx , tsize_rtx ) ; } else adjustment_rtx = tsize_rtx ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , adjustment_rtx ) ) ; dwarf_pattern = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - tsize ) ) ; iq2000_annotate_frame_insn ( insn , dwarf_pattern ) ; save_restore_insns (


<s> x = gen_rtx_REG ( value_mode , FP_RETURN ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode


<s> } else { STM = BuildMI ( * BB , MI , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) ; } MachineOperand LDBase ( MI -> getOperand ( <NUM_LIT> ) ) ; LDM . add ( LDBase ) . add ( predOps ( <STR_LIT> ) ) ; MachineOperand STBase ( MI -> getOperand ( <NUM_LIT> ) ) ; STM . add ( STBase ) . add ( predOps ( <STR_LIT> ) ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > ScratchRegs ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumOperands ( ) ; ++ I ) ScratchRegs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; llvm :: sort ( ScratchRegs , [ & TRI ] ( const unsigned & Reg1 , const unsigned & Reg2 ) -> bool { return TRI . getEncodingValue ( Reg1 ) < TRI . getEncodingValue ( Reg2 ) ; } ) ; for ( const auto & Reg


<s> if ( OpNo < MI -> getNumOperands ( ) ) { <STR_LIT> e = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> (


<s> SDValue <ISA_LIT>TargetLowering :: getCapGlobalReg ( SelectionDAG & DAG , EVT Ty ) const { assert ( Ty . isFatPointer ( )


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; const Function & F = * MF . getFunction ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , VReg , Offset ) ; } )


<s> MachineIRBuilder MIB ( MF ) ; addConstantsToTrack ( MF , GR ) ; foldConstantsIntoIntrinsics ( MF ) ; insertBitcasts ( MF , GR , MIB ) ; generateAssignInstrs ( MF , GR , MIB ) ; processInstrsWithTypeFolding ( MF , GR , MIB ) ; processSwitches ( MF ,


<s> DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) . getSimpleVT ( ) , DAG . getConstant ( <NUM_LIT> , Op . getValueType (

) . getSimpleVT ( ) ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> if ( Subtarget . hasStdExtV ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target (


<s> bool <ISA_LIT>XPLINKFrameLowering :: hasFP ( const MachineFunction & MF ) const { return


<s> bool mips_unsigned_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift


<s> return ( int32x2x2_t ) { vtrn1_s32 ( a , b ) , vtrn2_s32 ( a ,


<s> const uint32_t * getNoPreservedMask ( ) const override { return


<s> return ( int32x2_t ) __builtin_neon_vqrdmulh_nv2si ( __a ,


<s> EVT VT = N0 . getValueType ( ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) { APInt LHSZero , LHSOne ; APInt RHSZero , RHSOne ; CurDAG -> computeKnownBits ( N0 , LHSZero , LHSOne ) ; if ( LHSZero . getBoolValue ( ) ) { CurDAG -> computeKnownBits ( N1 , RHSZero


<s> tree builtin_type ; builtin_type = rs6000_builtin_type ( id ) ; if ( INTEGRAL_TYPE_P ( t ) && INTEGRAL_TYPE_P ( builtin_type


<s> assert ( PredReg . isReg ( ) && <STR_LIT> ) ; assert ( Polarity . isImm ( ) && <STR_LIT> ) ; assert ( MRI . getRegClass ( <STR_LIT> ) . contains ( PredReg . getReg ( ) ) && <STR_LIT> ) ; if ( Polarity . getImm (


<s> if ( Indices . size ( ) != Factor || UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment ,

AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ;


<s> bool i386_pe_type_dllimport_p ( tree decl ) { gcc_assert ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl


<s> MachinePointerInfo <ISA_LIT>FunctionInfo :: callPtrInfo ( const GlobalValue


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return


<s> inline bool function_call_info :: function_returns_void_p ( ) { return TREE_TYPE ( TREE_TYPE ( fndecl ) )


<s> rtx pattern , set ; int nops , ninsns ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= <NUM_LIT> ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / <NUM_LIT> ; if ( ninsns == <NUM_LIT> ) return ; if ( * hilo_delay < <NUM_LIT> && reg_set_p ( lo_reg , pattern ) ) nops = <NUM_LIT> - * hilo_delay ; else if ( * delayed_reg != <NUM_LIT> && reg_referenced_p ( * delayed_reg , pattern ) ) nops = <NUM_LIT> ; else if ( * fs_delay && get_attr_can_delay ( insn ) == CAN_DELAY_NO && GET_CODE ( PATTERN ( after ) ) != SEQUENCE && GET_CODE ( pattern ) != ASM_INPUT && asm_noperands ( pattern ) < <NUM_LIT> ) nops = <NUM_LIT> ; else nops =


<s> SMShadowTracker . count ( Inst , getSubtargetInfo ( )


<s> if ( ! GV ) return false ; if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { Kind = <ISA_LIT>PreserveArrayAI ; TypeMeta = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! TypeMeta ) report_fatal_error ( <STR_LIT> ) ; AccessIndex = cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> )


<s> if ( SeenDef ) return true ; ++ Iter ; while ( Iter != E && Iter -> isDebugInstr ( ) ) ++ Iter ; } if ( Iter == E ) { for ( MachineBasicBlock * S : MBB . successors ( ) ) if ( S -> isLiveIn ( <STR_LIT> ) ) return false ; return true ; } MachineBasicBlock :: iterator B = MBB . begin ( ) ; Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == B ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; while ( Iter != B && Iter -> isDebugInstr ( ) ) -- Iter ; bool SawKill = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter


<s> Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg

) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ;


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end


<s> MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand (


<s> bool <ISA_LIT>MCInstrInfo :: isDuplexPair ( MCInst const &


<s> LLVMContext & Ctx = M . getContext ( ) ; auto Type = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , false ) ; Function * F = Function :: Create ( Type , GlobalValue :: LinkOnceODRLinkage , Name , & M ) ; F -> setVisibility ( GlobalValue :: HiddenVisibility ) ; F -> setComdat ( M . getOrInsertComdat ( Name ) ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ; F -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ; BasicBlock * Entry = BasicBlock :: Create ( Ctx , <STR_LIT> , F ) ; IRBuilder < > Builder ( Entry ) ; Builder . CreateRetVoid


<s> int Idx = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( M > HalfSize ) return SDValue ( ) ; if ( Idx < <NUM_LIT> || ( Src == V && Idx == ( M - i ) ) ) { Src = V ; Idx = M - i ; continue ; } return SDValue ( ) ; } if ( Idx < <NUM_LIT> ) return SDValue ( ) ; assert ( ( Idx + Len ) <= HalfSize && <STR_LIT> ) ; int BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; int BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Src , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; } ; if ( SDValue ExtrQ = LowerAsEXTRQ ( ) ) return ExtrQ ; auto LowerAsInsertQ = [ & ] ( ) { for ( int Idx = <NUM_LIT> ; Idx != HalfSize ; ++ Idx ) { SDValue Base


<s> bool isMUBUF ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags &


<s> if ( ! loongarch_legitimate_address_p ( mode , x , false ) ) x = force_reg


<s> DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const Target & pTarget , const std :: string & pTriple ) { return new DWARFLineInfo (


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo (


<s> MachineInstr * MI = MRI . getVRegDef ( Src ) ; if ( MI && MI -> getOpcode ( ) == <STR_LIT> && MRI . getType ( Src ) == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Mods ^= ( <STR_LIT> | <STR_LIT> ) ; Src = MI -> getOperand ( <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = TID . getNumOperands ( ) ; i != e ; ++ i ) if ( TID . OpInfo [ i ] . isPredicate


<s> MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( TrapBB ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( )


<s> return F . hasFnAttribute ( Attribute :: SanitizeAddress ) || F . hasFnAttribute ( Attribute :: SanitizeThread ) || F . hasFnAttribute (

Attribute :: SanitizeMemory ) || F . hasFnAttribute ( Attribute :: SanitizeHWAddress ) || F . hasFnAttribute ( Attribute :: SanitizeMemTag ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context


<s> if ( ! attr ) return false ; * name = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return true


<s> EVT VT = Op . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; assert ( ( NumElems % <NUM_LIT> ) == <NUM_LIT> && ( SizeInBits %


<s> unsigned AddrSpace = Ptr -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace != <STR_LIT> ) { return SDValue ( ) ; } ConstantSDNode * BasePtr = dyn_cast < ConstantSDNode > ( Ptr -> getBasePtr ( ) ) ; assert ( BasePtr ) ; unsigned TypeDwordWidth = VT . getSizeInBits ( ) / <NUM_LIT> ; const TargetRegisterClass * dstClass ; switch ( TypeDwordWidth


<s> case FRAME_POINTER_REGNUM : offset = <NUM_LIT> ; break ; case STACK_POINTER_REGNUM : offset = lm32_compute_frame_size ( get_frame_size ( ) ) - current_frame_info . pretend_size ; break ; default : gcc_unreachable ( ) ; } break ; default : gcc_unreachable ( ) ; } return offset


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> )


<s> const char * getPassName ( ) const { return <STR_LIT>


<s> bool runOnMachineFunction ( MachineFunction & MF


<s> for ( EVT VT : VTs ) { unsigned NumRegs = TLI . getNumRegisters ( Context , VT ) ; MVT RegisterVT = TLI . getRegisterType ( Context , VT ) ; for ( unsigned i = <NUM_LIT> ; i != NumRegs ; ++ i ) ValueVTs . push_back


<s> MCOp = GetSymbolRef ( MO , GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : if ( Subtarget -> genExecuteOnly ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCOp = GetSymbolRef ( MO , GetCPISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm ( ) -> getValueAPF ( ) ; bool ignored ; Val . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmTowardZero , & ignored ) ; MCOp = MCOperand :: createFPImm ( Val . convertToDouble ( ) ) ; break ; } case MachineOperand :: MO_RegisterMask : return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return outliner :: InstrType :: Illegal ; } if ( FuncInfo -> getLOHRelated ( ) . count ( & MI ) ) return outliner :: InstrType :: Illegal ; if ( MI . isCFIInstruction ( ) ) return outliner :: InstrType :: Illegal ; if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isKill ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isTerminator ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; if ( MOP . isReg ( ) && ! MOP . isImplicit ( ) && ( MOP . getReg ( ) == <STR_LIT> || MOP . getReg ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return outliner :: InstrType :: Legal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee )


<s> void MBBInfo :: postVisit ( ) { delete HTScope


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo (


<s> for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i )


<s> if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( valtype ) , valtype , & dummy_mode , & dummy_int , NULL , false ) ) return false ; pure_scalable_type_info pst_info ; if ( pst_info . analyze_registers ( valtype ) ) return false ; return


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op ,


<s> getExclusiveOperation ( Size , Ord , ldrOpc , strOpc ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( exitMBB ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( newval ) . addReg ( ptr ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( stxr_status ) . addMBB ( loop1MBB ) ; BB -> addSuccessor ( loop1MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = exitMBB ; MI -> eraseFromParent


<s> MachineLocation <ISA_LIT>AsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { assert ( MI -> getNumOperands ( ) ==


<s> switch ( code ) { case LT : return <STR_LIT> ; case GE : return <STR_LIT> ; } } switch ( code ) { case EQ : return <STR_LIT> ; case NE : return <STR_LIT> ; case LT : return <STR_LIT> ; case LE : return <STR_LIT> ; case GT : return <STR_LIT> ; case GE : return <STR_LIT> ; case LTU : return <STR_LIT> ; case LEU


<s> bool isSImm6 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm (


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: parseIdentifier ( ) { SMLoc Start = Parser . getTok ( ) . getLoc ( ) ; SMLoc End = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res , * RHS = nullptr ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( Lexer . getKind ( ) != AsmToken :: Identifier ) return nullptr ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return nullptr ; if ( Identifier . equals_lower ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; else if ( Identifier . equals_lower ( <STR_LIT>

) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ;


<s> offset -= UNITS_PER_WORD ; } for ( regno = DSP_ACC_REG_FIRST ; regno <= DSP_ACC_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . acc_mask , ( ( regno - DSP_ACC_REG_FIRST ) / <NUM_LIT>


<s> } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasThumb2DSP ( ) && ( Mask & <NUM_LIT> )


<s> return Kind == k_VectorIndex && VectorIndex .


<s> break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT>


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp , InVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( NumElts / <NUM_LIT> + <NUM_LIT> ) ) ; } else { InVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ; SDValue VecOp2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ; Mask [ <NUM_LIT> ] = <NUM_LIT> ; Mask [ <NUM_LIT>


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode = false


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI


<s> unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SubReg1 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned SubReg2 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == SubReg1 && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI -> getOperand ( <NUM_LIT> )


<s> } if ( MIs . size ( ) < <NUM_LIT> || ( RegImm . Imm != <NUM_LIT> && MIs . size ( ) < <NUM_LIT> ) ) return <STR_LIT> ; const TargetRegisterClass * RCToScavenge ; if ( <STR_LIT> . contains ( RegImm . Reg ) ) RCToScavenge = & <STR_LIT> ; else if ( <STR_LIT> . contains ( RegImm . Reg ) ) RCToScavenge = & <STR_LIT> ; else if ( <STR_LIT> . contains ( RegImm . Reg ) ) RCToScavenge = & <STR_LIT> ; else return


<s> std :: map < RegisterRef , IndexType > LastDef , LastUse ; RegisterSet LiveOnEntry ; MachineBasicBlock & B = IndexMap . getBlock ( ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ; for ( auto R : getLiveIns ( B ) ) for ( auto S : expandToSubRegs ( R , MRI , TRI ) ) LiveOnEntry . insert ( S ) ; for ( auto R : LiveOnEntry ) LastDef [ R ] = IndexType :: Entry ; auto closeRange = [ & LastUse , & LastDef , & LiveMap ] ( RegisterRef R ) -> void { auto LD = LastDef [ R ] , LU = LastUse [ R ] ; if ( LD == IndexType :: None ) LD = IndexType :: Entry ; if ( LU == IndexType :: None ) LU = IndexType :: Exit ; LiveMap [ R ] . add ( LD , LU , false , false ) ; LastUse [ R ] = LastDef [ R ] = IndexType :: None ; } ; for ( auto & In : B ) { if ( In . isDebugValue ( ) ) continue ; IndexType Index = IndexMap . getIndex ( & In ) ; for ( auto & Op : In . operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . isUndef ( ) ) continue ; RegisterRef R = { Op . getReg ( ) , Op . getSubReg ( ) } ; if ( TargetRegisterInfo :: isPhysicalRegister ( R . Reg ) && Reserved [ R . Reg ] ) continue ; bool IsKill = Op . isKill ( ) ; for ( auto S : expandToSubRegs ( R , MRI , TRI ) ) { LastUse [ S ]


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const MachineFunction


<s> MachineBasicBlock * TBB = MBB -> back ( ) . getOperand ( <NUM_LIT> ) . getMBB ( ) ; assert ( TBB && <STR_LIT> ) ; MBB -> back ( ) . eraseFromParent ( ) ; if ( TBB != infoSucc . MBB ) { MachineInstr * branchMI = BuildMI ( * MBB , MBB -> end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( predicates [ <NUM_LIT> ] . getImm ( ) ) . addReg ( predicates [ <NUM_LIT> ] . getReg ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * branchMI ) ; } } if ( insertExplicitBranch ) { assert ( MBB -> isSuccessor ( succ ) && <STR_LIT> ) ; MachineInstr * branchMI = TII -> addDefaultPred ( BuildMI ( * MBB , MBB -> end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( succ ) ) ; DEBUG ( dbgs ( ) <<


<s> <ISA_LIT>AssemblerImpl :: <ISA_LIT>AssemblerImpl ( ) { JavaVMInitArgs vm_args ; JavaVMOption options [ <NUM_LIT> ] ; std :: string libPath = <STR_LIT> ; std :: string classPath = <STR_LIT> ; if ( ! Process :: GetEnv ( <STR_LIT> ) . hasValue ( ) ) report_fatal_error ( <STR_LIT> ) ; classPath = classPath + Process :: GetEnv ( <STR_LIT> ) . getValue ( ) ; classPath = classPath + <STR_LIT> ; libPath = libPath + Process :: GetEnv ( <STR_LIT> ) . getValue ( ) ; classObjectBuffer = nullptr ; llvm :: outs (


<s> bool popFeatureBits ( ) { assert ( FeatureBitStack . size ( ) == ParserOptionsStack . size ( ) && <STR_LIT> ) ; if ( FeatureBitStack . empty ( ) ) return true ; FeatureBitset FeatureBits = FeatureBitStack . pop_back_val ( ) ; copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits ) ) ; ParserOptions = ParserOptionsStack . pop_back_val ( ) ; return false


<s> bool MVEVPTOptimisations :: runOnMachineFunction ( MachineFunction & Fn ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ! STI . isThumb2 ( ) || ! STI . hasMVEIntegerOps (


<s> return new R600EmitClauseMarkersPass (


<s> MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT>


<s> static void vms_asm_out_constructor ( rtx symbol , int priority ATTRIBUTE_UNUSED ) { switch_to_section ( ctors_section


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant ,

const char * ExtraCode , raw_ostream & O ) {


<s> void <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I


<s> BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( CurReg ) ; } else if ( CurVal ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( ExecReg ) ; } else { BuildMI ( MBB , I , DL , TII -> get ( XorOp ) , DstReg ) . addReg ( ExecReg ) . addImm ( - <NUM_LIT> ) ; } return ; } unsigned PrevMaskedReg = <NUM_LIT> ; unsigned CurMaskedReg = <NUM_LIT> ; if ( ! PrevConstant ) { if ( CurConstant && CurVal ) { PrevMaskedReg = PrevReg ; } else { PrevMaskedReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , I , DL , TII -> get ( AndN2Op ) , PrevMaskedReg ) . addReg ( PrevReg ) . addReg ( ExecReg ) ; } } if ( ! CurConstant ) { if ( PrevConstant && PrevVal ) { CurMaskedReg = CurReg ; } else { CurMaskedReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , I , DL , TII -> get ( AndOp ) , CurMaskedReg ) . addReg ( CurReg ) . addReg ( ExecReg ) ; } } if ( PrevConstant && ! PrevVal ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( CurMaskedReg ) ; } else if ( CurConstant && ! CurVal ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( PrevMaskedReg ) ; } else if ( PrevConstant && PrevVal ) { BuildMI ( MBB , I , DL , TII -> get ( OrN2Op ) , DstReg ) . addReg