<s> else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false


<s> if ( OrigTy . getSizeInBits ( ) >= <NUM_LIT> ) return N ; EVT NewVT = getExtensionTo64Bits ( OrigTy ) ; return DAG . getNode ( ExtOpcode , SDLoc ( N


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , StringRef


<s> EVT VT = Value . getValueType ( ) ; if ( ( VT == <STR_LIT> ) || SD -> isTruncatingStore ( ) ) { SDValue SWL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; return CreateStoreLR ( <STR_LIT> , DAG , SD , SWL , IsLittle ? <NUM_LIT> : <NUM_LIT> ) ; } assert ( VT == <STR_LIT> ) ; SDValue SDL = CreateStoreLR ( <STR_LIT> , DAG , SD , Chain


<s> <ISA_LIT>UnifyDivergentExitNodes ( ) : FunctionPass


<s> if ( Opcode == <STR_LIT> ) { SDValue LHS = Val -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Val -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; bool isInteger = LHS . getValueType ( ) . isInteger ( ) ; if ( Negate ) CC = getSetCCInverse ( CC , isInteger ) ; SDLoc DL ( Val ) ; if ( isInteger ) { OutCC = changeIntCCTo<ISA_LIT>CC ( CC ) ; } else { assert ( LHS . getValueType ( ) . isFloatingPoint ( ) ) ; <STR_LIT> ExtraCC ; changeFPCCToAND<ISA_LIT>CC ( CC , OutCC , ExtraCC ) ; if ( ExtraCC != <STR_LIT> ) { SDValue ExtraCmp ; if ( ! CCOp . getNode ( ) ) ExtraCmp = emitComparison ( LHS , RHS , CC , DL , DAG ) ; else ExtraCmp = emitConditionalComparison ( LHS , RHS , CC , CCOp , Predicate , ExtraCC , DL , DAG ) ; CCOp = ExtraCmp ; Predicate = ExtraCC ; } } if ( ! CCOp ) return emitComparison ( LHS , RHS , CC , DL , DAG ) ; return emitConditionalComparison ( LHS , RHS , CC , CCOp , Predicate , OutCC , DL , DAG ) ; } assert ( Val -> hasOneUse ( ) && <STR_LIT> ) ; bool IsOR = Opcode == <STR_LIT> ; SDValue LHS = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateL ; bool MustBeFirstL ; bool ValidL = canEmitConjunction ( LHS , CanNegateL , MustBeFirstL , IsOR ) ; assert ( ValidL && <STR_LIT> ) ; ( void ) ValidL ; SDValue RHS = Val -> getOperand ( <NUM_LIT> ) ; bool CanNegateR ; bool MustBeFirstR ; bool ValidR = canEmitConjunction ( RHS , CanNegateR , MustBeFirstR , IsOR ) ; assert ( ValidR && <STR_LIT> ) ; ( void ) ValidR ; if ( MustBeFirstL ) { assert ( ! MustBeFirstR && <STR_LIT> ) ; std :: swap ( LHS , RHS ) ; std :: swap ( CanNegateL , CanNegateR ) ; std :: swap ( MustBeFirstL , MustBeFirstR ) ; } bool NegateR ; bool NegateAfterR ; bool NegateL ; bool NegateAfterAll ; if ( Opcode == <STR_LIT> ) { if ( ! CanNegateL ) { assert ( CanNegateR && <STR_LIT> ) ; assert ( ! MustBeFirstR && <STR_LIT> ) ; assert ( ! Negate ) ; std :: swap ( LHS , RHS ) ; NegateR = false ; NegateAfterR = true ; } else { NegateR = CanNegateR ; NegateAfterR = ! CanNegateR


<s> default : error ( <STR_LIT> ) ; return const0_rtx ; } } } else if ( i == nargs - <NUM_LIT> ) { if ( ! insn_p -> operand [ nargs ] . predicate ( op , SImode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( INTVAL ( op ) == NO_ROUND ) redundant_embed_rnd = <NUM_LIT> ; } else { if ( VECTOR_MODE_P ( mode ) ) op = safe_vector_operand ( op , mode ) ; op = fixup_modeless_constant ( op , mode ) ; if ( GET_MODE ( op ) == mode || GET_MODE ( op ) == VOIDmode ) { if ( optimize || ! match ) op = copy_to_mode_reg ( mode , op ) ; } else { op = copy_to_reg ( op ) ; op = simplify_gen_subreg ( mode , op , GET_MODE ( op ) , <NUM_LIT> ) ; } } args [ i ] . op = op ; args [ i ] . mode = mode ; } switch ( nargs ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op , args [ <NUM_LIT> ] . op ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return <NUM_LIT> ; if ( redundant_embed_rnd ) pat = ix86_erase_embedded_rounding ( pat ) ; emit_insn ( pat ) ; return target


<s> Ops . push_back ( Symbol ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag , DL ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ; HiLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Ret , HiLo , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD , DAG ) ) ; } if ( model == TLSModel :: InitialExec ) { unsigned ldTF = ( ( PtrVT == <STR_LIT> ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LDX : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL


<s>
OS
<<
MAI
->
getCommentString
(
)
<<
' '
<<
Comments
.
substr
(
<NUM_LIT>
,
Position
)
<<
'\n'
;
Comments
=
Comments
.
substr
(
Position
+
<NUM_LIT>
)
;
}
while
(
!
Comments
.
empty


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; if ( Index != - <NUM_LIT> ) { std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( Val ) ; if ( ! LT . second .


<s> return Kind == k_Register && Reg . Kind == RegKind :: NeonVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT>


<s> Re = cfun -> machine -> callee_saved_last_gpr_regno ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_position = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_v3pop_fpr_callee_saved ( fpr_position ) ; } nds32_emit_stack_v3pop ( Rb , Re , sp_adjust ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT> ) ; } else { nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = sp_adjust - cfun -> machine -> callee_saved_area_gpr_padding_bytes - cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_v3pop_fpr_callee_saved ( <NUM_LIT>


<s> if ( Id != <STR_LIT> ) return error ( <STR_LIT> + Id ) ; if ( expect ( AsmToken :: Equal , <STR_LIT> ) ) return true ; if ( ! Lexer . is ( AsmToken :: Integer ) ) return error ( <STR_LIT> ) ; parseSingleInteger ( false , Operands ) ; } else { auto IsLoadStoreLane = InstName . find ( <STR_LIT> ) != StringRef :: npos ; if ( IsLoadStoreLane && Operands . size ( ) == <NUM_LIT> ) return false ; auto Tok = Lexer . getTok ( ) ; Operands . push_back ( std :: make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Tok . getLoc ( ) , Tok . getEndLoc ( ) , <STR_LIT> {


<s> static rtx cris_function_incoming_arg ( cumulative_args_t ca , machine_mode mode , const_tree type , bool named ) { return cris_function_arg_1 ( ca , mode , type


<s> SDValue <ISA_LIT>TargetLowering :: lowerKernargMemParameter ( SelectionDAG & DAG , EVT VT , EVT MemVT , const SDLoc & SL , SDValue Chain , uint64_t Offset , bool Signed , const <STR_LIT> * Arg ) const { const DataLayout & DL = DAG . getDataLayout ( ) ; Type * Ty = MemVT . getTypeForEVT ( * DAG . getContext ( ) ) ; PointerType * PtrTy = PointerType :: get ( Ty , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get


<s> MBB . addLiveIn ( <STR_LIT> ) ; MBB . insert ( MBB . end ( ) , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define

) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ;


<s> assert ( OPW_FIRST_ <= Width && Width < OPW_LAST_ ) ; switch ( Width ) { default : case OPW32 : return SGPR_32RegClassID ; case OPW64 : return SGPR_64RegClassID ; case OPW128 : return SGPR_128RegClassID


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned NumWaitStates = TII -> getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr =


<s> int getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty


<s> assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; UseSmallSection = ! IsLinux && ( RM == Reloc :: Static


<s> assert ( ( ! OptForMinSize || MF . getFunction ( ) . hasOptSize ( ) ) && <STR_LIT> ) ; SelectionDAGISel :: runOnMachineFunction ( MF


<s> void setScoreUB ( InstCounterType T , int32_t Val ) { assert ( T < NUM_INST_CNTS ) ; if ( T >= NUM_INST_CNTS ) return ; ScoreUBs [ T ] =


<s> for ( auto * I : Tys ) { if ( ! I -> isVectorTy ( ) ) continue ; if ( I -> getScalarSizeInBits ( ) * I -> getVectorNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , <NUM_LIT> , <NUM_LIT> ) + getMemoryOpCost ( Instruction :: Load , I , <NUM_LIT> , <NUM_LIT> ) ; } return Cost


<s> assert ( And . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { KnownBits Known = DAG . computeKnownBits ( Op0 ) ; if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } else { bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal ) ) ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ; RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , dl , LHS .


<s> StringRef getPassName ( ) const override { return


<s> printOperand ( MI , opNum + <STR_LIT> , O ) ; O << ',' ; printOperand ( MI , opNum + <STR_LIT> ,


<s> return maybe_split_mode ( mode ) != VOIDmode


<s> fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( riscv_mcsr_check ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( riscv_emit_attribute_p ) riscv_emit_attribute (


<s> AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage (


<s> ME = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) ; return true ; } else { Val = ~ Val ; if ( isShiftedMask_64 ( Val ) ) { ME = countLeadingZeros ( Val ) - <NUM_LIT> ; MB = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) + <NUM_LIT> ; return


<s> if ( Candidate . R . OriginalAddend != PreviousBest . R . OriginalAddend ) return Candidate . R . OriginalAddend <


<s> if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1


<s> FlowQ . pop ( ) ; if ( EdgeExec . count ( Edge ) ) return ; EdgeExec . insert ( Edge ) ; ReachedBB . insert ( Edge . second ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr & PI = * It ++ ; InstrExec . insert ( & PI ) ; visitPHI ( PI )


<s> const <ISA_LIT>Subtarget * Subtarget = & TM .

getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> Op -> Reg . Kind = ScalarReg ; Op -> Reg . Num


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> (


<s> switch ( MO . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : return AP . getSymbol ( MO . getGlobal ( ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return AP . GetCPISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return AP . GetJTISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_BlockAddress : return AP . GetBlockAddressSymbol ( MO . getBlockAddress (


<s> static void encode_pdp11_f ( const struct real_format * fmt ATTRIBUTE_UNUSED , long


<s> DEBUG ( LRMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( ESMI -> dump ( ) ) ; if ( isLate && isEarly ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } return false


<s> gcc_checking_assert ( GET_CODE ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) && REGNO ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; if ( x == tocrel_base && tocrel_offset != const0_rtx ) { if ( INTVAL ( tocrel_offset ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; } else if ( TARGET_ELF ) fputs ( <STR_LIT> , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file


<s> if ( ! std :: count ( BusyRegs . begin ( ) , BusyRegs .

end ( ) , Reg ) ) return convReg ( Reg , VT ) ;


<s> return ( __m128i ) __builtin_ia32_lddqu ( ( char const


<s> } else { baseReg = MI . getOperand ( <NUM_LIT> ) ; offsetOp = MI . getOperand ( <NUM_LIT> ) ; } assert ( baseReg . isReg ( ) && <STR_LIT> ) ; encoding = Ctx . getRegisterInfo ( ) -> getEncodingValue ( baseReg . getReg ( ) ) ; if ( offsetOp . isImm ( ) ) encoding |= static_cast < short > ( offsetOp . getImm ( ) ) << <NUM_LIT> ; else if ( const <ISA_LIT>MCExpr * McExpr = dyn_cast < <ISA_LIT>MCExpr > ( offsetOp . getExpr ( ) ) ) { if ( McExpr -> getKind ( ) == <ISA_LIT>MCExpr ::


<s> SDValue PredOp = CurDAG -> getTargetConstant ( <ISA_LIT>Predicate :: Normal , <STR_LIT> ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( Target . getOpcode ( ) == <STR_LIT> ) ; assert ( Pred . getValueType ( ) == <STR_LIT> ) ; SDValue Ops [ ] = { Target , Pred , PredOp , Chain } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT>


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects


<s> if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 =


<s> bool isf32Ext ( ) const { return false


<s> BlendMask [ i ] = i ; } else if ( Mask [ i ] >= Size ) { V2Mask [ i ] = Mask [ i ] - Size ; BlendMask [ i ] = i + Size ; } V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF ( VT ) , V1Mask ) ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; return DAG . getVectorShuffle ( VT , DL , V1 ,


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { assert ( I . getParent ( ) && <STR_LIT> ) ; assert ( I . getParent ( ) -> getParent ( ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned Opcode = I . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opcode ) ) { if ( Opcode == TargetOpcode :: LOAD_STACK_GUARD ) return false ; if ( I . isCopy ( ) ) return selectCopy ( I , MRI ) ; return true ; } assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ; if ( selectImpl ( I , CoverageInfo ) ) return true ; DEBUG ( dbgs ( ) << <STR_LIT> ; I . print ( dbgs ( ) ) ) ; switch ( I . getOpcode ( ) ) { default : return false ; case TargetOpcode :: G_STORE : case TargetOpcode :: G_LOAD : return selectLoadStoreOp ( I , MRI ,


<s> for ( int I = MFI . getObjectIndexBegin ( ) , E = MFI . getObjectIndexEnd ( ) ; I != E ;


<s> HOST_WIDE_INT align ; align = SYMBOL_REF_DECL ( x ) ? DECL_ALIGN_UNIT ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ; return IN_RANGE ( offset , <NUM_LIT> ,


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) &&


<s> case <STR_LIT> : return combineSUBX ( N , DAG ) ; case <STR_LIT> : return combineADDX ( N , DAG , DCI ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT>


<s> for ( MachineInstr & MI : Pred -> terminators ( ) ) for ( MachineOperand & MO : MI . explicit_operands ( )

) if ( MO . isMBB ( ) && MO . getMBB ( ) == MBB ) return true ;


<s> encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = ( Size * <NUM_LIT> )


<s> std :: string Name = GV ? Mang -> getValueName ( GV ) : TAI -> getGlobalPrefix ( ) ; if ( ! GV ) Name += ACPV -> getSymbol ( ) ; if ( ACPV -> isNonLazyPointer ( ) ) { if ( GV -> hasHiddenVisibility ( ) ) HiddenGVNonLazyPtrs . insert ( Name ) ; else GVNonLazyPtrs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; } else if ( ACPV -> isStub ( ) ) { FnStubs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; } else O << Name ; if ( ACPV -> hasModifier ( ) ) O << <STR_LIT> << ACPV -> getModifier ( ) << <STR_LIT> ; if ( ACPV -> getPCAdjustment


<s> tree target = TREE_TYPE ( actual ) ; type_suffix_index type = find_type_suffix_for_scalar_type ( target ) ; if ( type == NUM_TYPE_SUFFIXES ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , build_qualified_type ( target , <NUM_LIT> ) ) ; return NUM_TYPE_SUFFIXES ; } unsigned int bits = type_suffixes [ type ] . element_bits ; if ( gather_scatter_p && bits != <NUM_LIT> && bits != <NUM_LIT> ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl ) ; return NUM_TYPE_SUFFIXES


<s> msp430_allocate_stack_slots_for_args static bool msp430_allocate_stack_slots_for_args ( void ) { return ! is_naked_func (


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand ::


<s> else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > Visited ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { LoLoop . End } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Remove ; if ( ! IsSafeToRemove ( LoLoop . Dec , RDA , Visited , Remove ,


<s> int64_t getStackPointerBias ( ) const { return is64Bit ( ) ?


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> } else { sve_nunits = ordered_min ( sve_nunits , GET_MODE_SIZE ( vector_mode ) ) ; if ( aarch64_sve_data_mode ( element_mode , sve_nunits ) . exists ( & sve_mode ) ) return sve_mode ; } } if ( ( vec_flags & VEC_ADVSIMD ) && known_eq ( nunits , <NUM_LIT> ) && known_eq ( GET_MODE_BITSIZE ( vector_mode ) , <NUM_LIT> ) && maybe_ge ( GET_MODE_BITSIZE ( element_mode ) *

GET_MODE_NUNITS ( vector_mode ) , <NUM_LIT> ) ) {


<s> if ( cast < FixedVectorType > ( Op -> getType ( ) ) -> getNumElements ( ) < <NUM_LIT> ) return false ; if ( ! cast < VectorType > ( Op -> getType ( ) ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; auto * Mul = dyn_cast < BinaryOperator > ( Op ) ; if ( ! Mul || Mul -> getOpcode ( ) != Instruction :: Mul ) return false ; Value * LHS = Mul -> getOperand ( <NUM_LIT> ) ; Value * RHS = Mul -> getOperand ( <NUM_LIT> ) ; if ( ST -> hasSSE41 ( ) ) { if ( LHS == RHS ) { if ( ! isa < Constant > ( LHS ) && ! LHS -> hasNUses ( <NUM_LIT> ) ) return false ; } else { if ( ! isa < Constant > ( LHS ) && ! LHS -> hasOneUse ( ) ) return false ; if ( ! isa < Constant > ( RHS ) && ! RHS -> hasOneUse ( ) ) return false ; } } auto CanShrinkOp = [ & ] ( Value * Op ) { auto IsFreeTruncation = [ & ] ( Value * Op ) { if ( auto * Cast = dyn_cast < CastInst > ( Op ) ) { if ( Cast -> getParent ( ) == Mul -> getParent ( ) && ( Cast -> getOpcode ( ) == Instruction :: SExt || Cast -> getOpcode ( ) == Instruction :: ZExt ) && Cast -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return true ; } return isa < Constant >


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx


<s> for ( auto * MBB : Blocks ) { if ( MBB != Entry ) { for ( auto * Pred : MBB -> predecessors ( ) ) { assert ( inRegion ( Pred


<s> bool disableGenericCombines ( CodeGenOpt :: Level OptLevel ) const override { return


<s> assert ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { Register ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; unsigned ImmR = RegSize - Shift ; unsigned ImmS = std :: min < unsigned > ( SrcBits - <NUM_LIT> , DstBits - <NUM_LIT> - Shift ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; unsigned Opc = OpcTable [ IsZExt ] [ Is64Bit ] ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { Register TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ,

TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 ) . addImm ( <STR_LIT> ) ;


<s> int mips_dspalu_bypass_p ( rtx out_insn , rtx in_insn ) { int i ; int num_bypass = ARRAY_SIZE ( dspalu_bypass_table ) ; enum insn_code out_icode = ( enum insn_code ) INSN_CODE ( out_insn ) ; enum insn_code in_icode = ( enum insn_code


<s> StringRef NoAnnot ; Nop . setOpcode ( <STR_LIT> ) ; <ISA_LIT>MCInstrInfo :: setPacketBegin ( Nop , <ISA_LIT>MCInstrInfo :: isPacketBegin ( * MI ) ) ; printInst ( & Nop , O , NoAnnot , STI ) ; } if ( <ISA_LIT>MCInstrInfo :: isPacketEnd ( * MI ) ) O << PacketPadding << endPacket ; printInstruction ( MI , O ) ; } else { if ( <ISA_LIT>MCInstrInfo :: isPacketBegin ( * MI ) ) O << PacketPadding << startPacket << '\n' ; printInstruction ( MI , O ) ; if ( <ISA_LIT>MCInstrInfo :: isPacketEnd ( * MI ) ) O << '\n' << PacketPadding << endPacket ; } printAnnotation ( O ,


<s> if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ; return nullptr


<s> return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ||


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueV ) ; Ops . push_back ( FalseV ) ; Ops . push_back ( TargetCC ) ; Ops . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl


<s> SDValue <ISA_LIT>TargetLowering :: splitBinaryBitConstantOp ( DAGCombinerInfo & DCI , const SDLoc & SL , unsigned Opc , SDValue LHS , const ConstantSDNode * CRHS ) const { uint64_t Val = CRHS -> getZExtValue ( ) ; uint32_t ValLo = Lo_32 ( Val ) ; uint32_t ValHi = Hi_32 ( Val ) ; const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo (


<s> static bool shouldScheduleAdjacent ( const TargetInstrInfo & TII , const TargetSubtargetInfo & TSI , const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { const <ISA_LIT>Subtarget & ST = static_cast < const <ISA_LIT>Subtarget & > ( TSI ) ; if ( ST . hasArithmeticBccFusion ( ) && isArithmeticBccPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair


create<ISA_LIT>MIPreEmitCheckingPass ( ) {


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ST . getTargetLowering ( ) -> isNoopAddrSpaceCast ( SrcAS , DestAS ) ) { MI . setDesc ( MIRBuilder . getTII ( ) . get ( TargetOpcode :: G_BITCAST ) ) ; return true ; } if ( DestAS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { MIRBuilder . buildExtract ( Dst , Src , <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; uint32_t AddrHiVal = Info -> get32BitAddressHighBits ( ) ; auto HighAddr = MIRBuilder . buildConstant ( LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT , <NUM_LIT> ) , AddrHiVal ) ; MIRBuilder . buildMerge ( Dst , { Src , HighAddr . getReg ( <NUM_LIT> ) } ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: FLAT_ADDRESS ) { assert ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; auto SegmentNull = MIRBuilder . buildConstant ( DstTy , NullVal ) ; auto FlatNull = MIRBuilder . buildConstant ( SrcTy , <NUM_LIT> ) ; Register PtrLo32 = MRI . createGenericVirtualRegister ( DstTy ) ; MIRBuilder . buildExtract ( PtrLo32 , Src , <NUM_LIT> ) ; Register CmpRes = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildICmp ( CmpInst :: ICMP_NE , CmpRes , Src , FlatNull . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildSelect ( Dst , CmpRes , PtrLo32 , SegmentNull . getReg ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcAS != <ISA_LIT>AS :: LOCAL_ADDRESS && SrcAS != <ISA_LIT>AS :: PRIVATE_ADDRESS ) return false ; if ( ! ST . hasFlatAddressSpace ( ) ) return false ; auto SegmentNull = MIRBuilder . buildConstant ( SrcTy , TM . getNullPointerValue ( SrcAS ) ) ; auto FlatNull = MIRBuilder . buildConstant ( DstTy , TM . getNullPointerValue ( DestAS ) ) ; Register ApertureReg = getSegmentAperture ( DestAS , MRI , MIRBuilder ) ; Register CmpRes = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT>


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( nvptxSubtarget . hasROT32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } else { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> ,


<s> static unsigned int mips_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; if ( FP_REG_P (


<s> if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Op . Reg . RegNum = VM512Regs [ regIdx /


<s> MVT NewVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * ( EltSizeBits / <NUM_LIT> ) ) ; assert ( NewVT . isValid ( ) && <STR_LIT> ) ; SDValue L = DAG . getLoad ( NewVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getOriginalAlign ( ) , Load -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getMergeValues ( { DAG . getBitcast ( VT , L ) , L . getValue ( <NUM_LIT> )


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT>


<s> if ( ! parseExpr ( Imm , <STR_LIT> ) ) { return false ; } if ( ! isUInt < <NUM_LIT> > ( Imm ) ) { Error ( OffsetLoc , <STR_LIT> ) ; return false


<s> <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo , O


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getTargetConstant ( IncVal , <STR_LIT> ) ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ?


<s> XorOpc = <STR_LIT> ; MovTermOpc = <STR_LIT> ; Andn2TermOpc = <STR_LIT> ; XorTermrOpc = <STR_LIT> ; OrSaveExecOpc = <STR_LIT> ; Exec = <STR_LIT> ; } else { AndOpc = <STR_LIT> ; OrOpc = <STR_LIT> ; XorOpc = <STR_LIT> ; MovTermOpc = <STR_LIT> ; Andn2TermOpc = <STR_LIT> ; XorTermrOpc = <STR_LIT> ; OrSaveExecOpc = <STR_LIT> ; Exec = <STR_LIT> ; } MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next , Last ; for ( I = MBB . begin ( ) , Last = MBB . end ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : emitIf ( MI ) ; break ; case <STR_LIT> : emitElse ( MI ) ; break ; case <STR_LIT> : emitIfBreak ( MI ) ; break ; case <STR_LIT> : emitLoop ( MI ) ; break ; case <STR_LIT> : emitEndCf ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : combineMasks ( MI ) ; Last = I ; continue ; default : Last = I ; continue ; } Next = ( Last == MBB . end ( ) ) ? MBB . begin ( ) : Last ; } } LoweredEndCf . clear ( ) ; LoweredIf . clear ( )


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; assert ( ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && ( Binary & <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Binary |= encodeVFPRd ( MI , OpIdx ++ ) ; if ( TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> )


<s> for ( unsigned j = <NUM_LIT> ; j < instList . size ( ) ; j ++ ) if ( auto val = dyn_cast < IntrinsicInst > ( instList [ j ] ) ) { if ( val -> getIntrinsicID ( ) == intrinId ) selectInst . push_back ( instList [ j


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AsmPrinter :: runOnMachineFunction ( MF ) ; return


<s> Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , Entry -> begin ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> begin ( ) , DebugLoc ( ) , TII -> get

( TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ;


<s> <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , DL , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , DL ,


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) .


<s> int Half = NumElems / <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < Half ; ++ i ) if ( ! isUndefOrInRange ( Mask

[ i ] , NumElems , NumElems * <NUM_LIT> ) ) return false ;


<s> CmpInstr . RemoveOperand ( DeadNZCVIdx ) ; bool succeeded = UpdateOperandRegClass ( CmpInstr ) ; ( void ) succeeded ; assert ( succeeded && <STR_LIT> ) ; return true ; } if ( CmpInstr . getOpcode ( ) == <STR_LIT> ) return optimizePTestInstr ( & CmpInstr , SrcReg , SrcReg2 , MRI ) ; if ( SrcReg2 != <NUM_LIT> ) return false ; if ( ! MRI -> use_nodbg_empty ( CmpInstr . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( CmpValue == <NUM_LIT> && substituteCmpToZero ( CmpInstr , SrcReg , *


<s> const DenseMap < unsigned , unsigned > :: const_iterator It = PVs . find ( Src ) ; if ( It != PVs . end ( ) ) MI .

getOperand ( OperandIdx ) . setReg ( It -> second ) ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT>


<s> return ( __m128i ) vec_mergeh ( ( __v16qu ) __A , (


<s> } if ( QII -> isPredicated ( PacketMI ) ) { if ( ! QII -> isPredicated ( MI ) ) return false ; unsigned predRegNumSrc = <NUM_LIT> ; unsigned predRegNumDst = <NUM_LIT> ; const TargetRegisterClass * predRegClass = nullptr ; for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) { if ( PacketMI -> getOperand ( opNum ) . isReg ( ) ) predRegNumSrc = PacketMI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumSrc ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) ) predRegNumDst = MI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || QII -> isDotNewInst ( PacketMI ) != QII -> isDotNewInst ( MI ) || getPredicateSense ( MI , QII ) != getPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit [ * VI ] ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI ->


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects


<s> if ( ! isExtend ( ) ) return false ; <STR_LIT> ET = getShiftExtendType (


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return encodeThumbBLOffset ( MO . getImm (


<s> MIB . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } else if ( HII -> getAddrMode ( * OldMI ) == <STR_LIT> ) { short NewOpCode = HII -> getAbsoluteForm ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; int64_t Offset = ImmOp . getOffset ( ) + OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addGlobalAddress ( GV , Offset , ImmOp . getTargetFlags ( ) ) ; MIB . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } Changed = true ; DEBUG ( dbgs ( ) << <STR_LIT> << * OldMI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MIB << <STR_LIT> ) ; } else if ( ImmOpNum == <NUM_LIT> && OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { short NewOpCode = HII -> xformRegToImmOffset ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII ->


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerSymbolOperandDarwin ( const MachineOperand & MO , MCSymbol * Sym


<s> static unsigned int nds32_function_arg_boundary ( machine_mode mode , const_tree type ) { return ( nds32_needs_double_word_align ( mode , type ) ? NDS32_DOUBLE_WORD_ALIGNMENT : PARM_BOUNDARY


<s> Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'q' : <STR_LIT> Ty = P . getSubtarget ( ) . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , Ty ) ; break ; } O << '%' << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ; return


<s> bool riscv_new_address_profitable_p ( rtx memref , rtx_insn * insn , rtx new_addr ) { addr_space_t as = MEM_ADDR_SPACE ( memref ) ; bool speed = optimize_bb_for_speed_p ( BLOCK_FOR_INSN ( insn ) ) ; int old_cost = address_cost ( XEXP ( memref , <NUM_LIT> ) , GET_MODE ( memref ) , as , speed ) ; int new_cost = address_cost ( new_addr , GET_MODE ( memref ) , as , speed ) ; return new_cost


<s> unsigned RegMaskSize = MachineOperand :: getRegMaskSize ( getNumRegs ( ) ) ; memcpy ( UpdatedMask , * Mask , sizeof ( UpdatedMask [ <NUM_LIT> ] ) * RegMaskSize ) ; for ( size_t i = <NUM_LIT> ; i < <STR_LIT> . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegCustomCalleeSaved ( i ) ) { for ( MCSubRegIterator SubReg ( <STR_LIT> . getRegister ( i ) , this , true ) ; SubReg . isValid ( )


<s> for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OW


<s> bool <ISA_LIT>LowerEmscriptenEHSjLj :: runOnModule ( Module & M ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVMContext & C = M . getContext ( ) ; IRBuilder < > IRB ( C ) ; Function * SetjmpF = M . getFunction ( <STR_LIT> ) ; Function * LongjmpF = M . getFunction ( <STR_LIT> ) ; bool SetjmpUsed = SetjmpF && ! SetjmpF -> use_empty ( ) ; bool LongjmpUsed = LongjmpF && ! LongjmpF -> use_empty ( ) ; bool DoSjLj = EnableSjLj && ( SetjmpUsed || LongjmpUsed ) ; ThrewGV = getGlobalVariableI32 ( M , IRB , <STR_LIT> ) ; ThrewValueGV = getGlobalVariableI32 ( M , IRB , <STR_LIT> ) ; GetTempRet0Func = getEmscriptenFunction ( FunctionType :: get ( IRB . getInt32Ty ( ) , false ) , <STR_LIT> , & M ) ; SetTempRet0Func = getEmscriptenFunction ( FunctionType :: get ( IRB . getVoidTy ( ) , IRB . getInt32Ty ( ) , false ) , <STR_LIT> , & M ) ; GetTempRet0Func -> setDoesNotThrow ( ) ; SetTempRet0Func -> setDoesNotThrow ( ) ; bool Changed = false ; if ( EnableEH ) { FunctionType * ResumeFTy = FunctionType :: get ( IRB . getVoidTy ( ) , IRB . getInt8PtrTy ( ) , false ) ; ResumeF = getEmscriptenFunction ( ResumeFTy , <STR_LIT> , & M ) ; FunctionType * EHTypeIDTy = FunctionType :: get ( IRB . getInt32Ty ( ) , IRB . getInt8PtrTy ( ) , false ) ; EHTypeIDF = getEmscriptenFunction ( EHTypeIDTy , <STR_LIT> , & M ) ; for ( Function & F : M ) { if ( F . isDeclaration ( ) ) continue ; Changed |= runEHOnFunction ( F ) ; } } if ( DoSjLj ) { Changed = true ; if ( LongjmpF ) { EmLongjmpJmpbufF = getEmscriptenFunction ( LongjmpF -> getFunctionType ( ) , <STR_LIT> , & M ) ; LongjmpF -> replaceAllUsesWith ( EmLongjmpJmpbufF ) ; } if ( SetjmpF ) { FunctionType * SetjmpFTy = SetjmpF -> getFunctionType ( ) ; FunctionType * FTy = FunctionType :: get ( Type :: getInt32PtrTy ( C ) , { SetjmpFTy -> getParamType ( <NUM_LIT> ) , IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } , false ) ; SaveSetjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ; FTy = FunctionType :: get ( IRB . getInt32Ty ( ) , { IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } , false ) ; TestSetjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ; FTy = FunctionType :: get ( IRB . getVoidTy ( ) , { IRB . getInt32Ty ( ) ,


<s> return ( poly8x8_t ) __builtin_neon_vsri_nv8qi ( ( int8x8_t ) __a , ( int8x8_t )


<s> value_rtx = convert_to_mode ( Pmode , value_rtx , <NUM_LIT> ) ; emit_library_call ( wrd_memset_libfunc , LCT_NORMAL , VOIDmode , <NUM_LIT> , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> <NUM_LIT> ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == <NUM_LIT> ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , convert_to_mode ( QImode , value_rtx ,


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { return new <ISA_LIT>ELFStreamer ( S , STI


<s> if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) )


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 ,


<s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned TyWidth ) { assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ; if ( ST -> hasPOPCNTD ( ) != <ISA_LIT>Subtarget :: POPCNTD_Unavailable && TyWidth <= <NUM_LIT> ) return ST -> hasPOPCNTD ( ) == <ISA_LIT>Subtarget :: POPCNTD_Slow ? TTI :: PSK_SlowHardware : TTI :: PSK_FastHardware ; return TTI ::


<s> Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives = false ; WeakRefDirective = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler = true ; HasIdentDirective = true


<s> if ( auto * I = dyn_cast < Instruction > ( Op ) ) { if ( I -> getParent ( ) == Parent && Base -> comesBefore ( I ) ) WorkQ . push_back ( I ) ; } } } return Deps ; } ; auto tryAddTo = [ & ] ( const AddrInfo & Info , MoveGroup & Move ) { assert ( ! Move . Main . empty ( ) && <STR_LIT> ) ; if ( Move . IsHvx != isHvx ( Info ) ) return false ; Instruction * Base = Move . Main . front ( ) ; if ( Base -> getParent ( ) != Info . Inst -> getParent ( ) ) return false ; auto isSafeToMoveToBase = [ & ] ( const Instruction * I ) { return HVC . isSafeToMoveBeforeInBB ( * I , Base -> getIterator ( ) ) ; } ; DepList Deps = getUpwardDeps ( Info . Inst , Base


<s> assert ( Last . getParent ( ) == First . getParent ( ) && <STR_LIT> ) ; assert ( InstrPos . find ( & First ) != InstrPos . end ( ) && InstrPos . find ( & Last ) != InstrPos . end ( ) && <STR_LIT> ) ; return InstrPos [ & Last ] - InstrPos


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] && ExtraCode [ <NUM_LIT> ] != 'a' ) return true ; const MachineOperand & MO = MI -> getOperand


<s> return getGeneration ( ) == <ISA_LIT>Subtarget


<s> void <ISA_LIT>TargetWasmStreamer :: emitStackPointer ( uint32_t Index ) { Streamer . PushSection ( ) ; Streamer . SwitchSection ( Streamer . getContext ( ) . getWasmSection ( <STR_LIT> , SectionKind :: getMetadata ( ) ) ) ; Streamer . EmitIntValue ( Index , <NUM_LIT> ) ; Streamer . PopSection ( )


<s> } if ( SrcRC == <STR_LIT> && SrcReg == <STR_LIT> && DestRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) ; return true ; } if ( DestRC == <STR_LIT> && DestReg == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return true ; } return false


<s> virtual const <ISA_LIT>FrameInfo * getFrameInfo (


<s> static DecodeStatus DecodeT2AddrModeImm8s4 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT>


<s> unsigned Idx = ISDOpc - <STR_LIT> ; Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } if ( ! <STR_LIT> ( Imm , RegSize ) ) return <NUM_LIT> ; unsigned ResultReg = fastEmitInst_ri ( Opc , RC , LHSReg , <STR_LIT> ( Imm , RegSize ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> && ISDOpc != <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask


<s> if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return Subtarget . hasFP16 ( ) ; case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } return


<s> continue ; } NumRLInsts += SelectRotMask64Count ( BG . RLAmt , BG . Repl32 , BG . StartIdx , BG . EndIdx , ! FirstBG ) ; FirstBG = false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << ( VRI . Repl32 ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << NumAndInsts << <STR_LIT> << NumRLInsts << <STR_LIT> ) ; if ( NumAndInsts > NumRLInsts ) continue ; if ( ( Use32BitInsts || MoreBG ) && NumAndInsts == NumRLInsts ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt || ( VRI . Repl32 && ! isUInt < <NUM_LIT> > ( Mask ) ) ) VRot = SelectRotMask64 ( VRI . V , dl , VRI . RLAmt , VRI . Repl32 , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> , VRI . Repl32 ? <NUM_LIT> : <NUM_LIT> ) ; else VRot = VRI . V ; SDValue TotalVal ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( VRot , dl ) , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( VRot , dl ) , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal =


<s> if ( Subtarget . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; O << <STR_LIT> << CPUDirectives [ Directive ] << '\n' ; bool Result = AsmPrinter :: doInitialization ( M ) ; assert ( MMI ) ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS

| MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ;


<s> if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( SDValue ReplacedZeroSplat = replaceZeroVectorStore ( DAG , * S ) ) return ReplacedZeroSplat ; if ( ! Subtarget -> isMisaligned128StoreSlow ( ) ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; if ( VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant (


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter


<s> if ( usesHardware ( <STR_LIT> ) ) { return MAX_LDS_<ISA_LIT>ZE_800


<s> PM -> add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( )


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS . write (


<s> static insn_info * find_reg_killed_by ( const bb_info * bb , rtx x ) { if ( ! x || vlmax_avl_p ( x ) || ! REG_P ( x ) ) return nullptr ; for ( insn_info * insn : bb -> reverse_real_nondebug_insns ( ) ) if ( find_access ( insn -> defs ( ) , REGNO ( x ) ) ) return insn ; return nullptr


<s> Changed |= expandStoreInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandStoreVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadVec2 ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandStoreVec2 ( B , I , MRI , HII , NewRegs ) ; break ; case


<s> Stub * <ISA_LIT>To<ISA_LIT>Stub :: doClone (


<s> unsigned oc = MI . getOpcode ( ) ; if ( oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { sourceReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; destReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } else if ( oc == <STR_LIT> ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { sourceReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; destReg = MI . getOperand ( <NUM_LIT> )


<s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( MFI -> isVRegStackified ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; if ( isVerbose ( ) ) { OutStreamer -> AddComment ( <STR_LIT> + utostr ( MFI -> getWARegStackId ( MFI -> getWAReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) ) ; OutStreamer -> AddBlankLine ( ) ; } break ; } case <STR_LIT> : if ( isVerbose ( ) ) { OutStreamer -> AddComment


<s> assert ( Imm > <NUM_LIT> && Imm <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << Imm <<


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } SelectCode (


<s> uint64_t NumBytes = <NUM_LIT> ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < <NUM_LIT> > ( Offset ) ) return


<s> LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> ,


<s> return ( __m128d ) _mm_setr_pd ( r [ <NUM_LIT> ] , ( ( __v2df ) __A )


<s> void <ISA_LIT>HSATargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; TextSection = <STR_LIT> ( Ctx ) ; DataGlobalAgentSection = <STR_LIT> (


<s> <ISA_LIT>ExprKind getKind ( ) const { return Kind


<s> callee_size = <NUM_LIT> ; reg_save_mask = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < SP_REGNUM ; regno ++ ) { if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) { reg_save_mask |= <NUM_LIT> << regno ; callee_size += UNITS_PER_WORD ; } } if ( df_regs_ever_live_p ( RA_REGNUM ) || ! crtl -> is_leaf || ! optimize ) { reg_save_mask |= <NUM_LIT> << RA_REGNUM ; callee_size += UNITS_PER_WORD ; } if ( ! ( reg_save_mask & ( <NUM_LIT> << FP_REGNUM ) ) && frame_pointer_needed ) { reg_save_mask |= <NUM_LIT> << FP_REGNUM ; callee_size += UNITS_PER_WORD ; } total_size = pretend_size + args_size + locals_size + callee_size ; total_size = ( total_size + <NUM_LIT> )


<s> int regno ; if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != <NUM_LIT> ) return <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return <NUM_LIT> ; if ( flag_pic && current_function_uses_pic_offset_table )


<s> static bool isVINSERTIndex ( SDNode * N , unsigned vecWidth ) { assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getVectorElementType ( )


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( ! MCID . isTerminator ( ) ) return false ; if ( MCID . isBranch ( ) && ! MCID . isBarrier ( ) ) return true ; if ( ! MCID . isPredicable ( ) ) return true ; return ! isPredicated


<s> uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> PostRASchedContext :: ~ PostRASchedContext ( ) { delete


<s> unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode = getOpcodeForOffset ( isHighReg ( Reg ) ? HighOpcode : LowOpcode , MI . getOperand ( <NUM_LIT> ) . getImm (


<s> static SDValue PerformVMOVRRDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SDValue InDouble = N -> getOperand ( <NUM_LIT> ) ; if ( InDouble . getOpcode ( ) == <STR_LIT> ) return DCI . CombineTo ( N , InDouble . getOperand ( <NUM_LIT> ) , InDouble . getOperand ( <NUM_LIT> ) ) ; SDNode * InNode = InDouble . getNode ( ) ; if ( <STR_LIT> ( InNode ) && InNode -> hasOneUse ( ) && InNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && InNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && ! cast < LoadSDNode >


<s> MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( )


<s> SMLoc S = getLoc ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) return MatchOperand_NoMatch ; auto Ry = Operands . back ( ) -> getReg ( ) ; Operands . pop_back ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Minus )


<s> if ( B . succ_empty ( ) ) return NULL ; CmpWeight Cmp ( B , getAnalysis < MachineBranchProbabilityInfo > (


<s> if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) . getRetAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg ,


<s> SDValue DataToTruncate = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MVT VT = DataToTruncate . getSimpleValueType ( ) ; MVT SVT = <STR_LIT> ( ElementType , VT . getVectorNumElements ( ) ) ; if ( isAllOnes ( Mask ) ) return DAG . getTruncStore ( Chain , dl , DataToTruncate , Addr , MachinePointerInfo ( ) , SVT , false , false , SVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; MVT BitcastVT = <STR_LIT> ( <STR_LIT> , Mask . getSimpleValueType (


<s> static bool arm_macro_fusion_p ( void ) { return current_tune -> fuseable_ops != ARM_FUSE_NOTHING


<s> unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; return ResultReg


<s> static void seh_emit_save ( FILE * f , struct seh_frame_state * seh , rtx reg , HOST_WIDE_INT cfa_offset ) { const unsigned int regno = REGNO ( reg ) ; HOST_WIDE_INT offset ; seh -> reg_offset [ regno ] = cfa_offset ; gcc_assert ( seh -> sp_offset >= cfa_offset ) ; offset = seh ->


<s> return false ; } void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind


<s> if ( ! GlobalBaseReg ) { getGlobalBaseReg ( ) ; initGlobalBaseReg ( )


<s> else if ( delta < <NUM_LIT> ) fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ADDITIVE_SIZE_MODIFIER ( - delta ) , - delta , reg_names [ CRIS_FIRST_ARG_REG ] ) ; fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , XSTR ( XEXP ( DECL_RTL ( funcdecl ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( stream , <STR_LIT> ) ; final_end_function (


<s> assert ( ! isOverloaded ( IntrID ) && <STR_LIT> ) ; AttrListPtr AList = getAttributes ( M -> getContext ( ) , ( <STR_LIT> )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , n = IV_Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { MachineBasicBlock * MBB = IV_Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; if ( MBB == Preheader ) InitialValue = & IV_Phi -> getOperand ( i ) ; else if ( MBB == Latch ) IVReg = IV_Phi -> getOperand ( i ) . getReg ( ) ; } if ( ! InitialValue ) return <NUM_LIT> ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * TB = <NUM_LIT> , * FB = <NUM_LIT> ; bool NotAnalyzed = TII -> AnalyzeBranch ( * Latch , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return <NUM_LIT> ; MachineBasicBlock * Header = L -> getHeader ( ) ; assert ( TB && <STR_LIT> ) ; assert ( ( ! FB || TB == Header || FB == Header ) && <STR_LIT> ) ; if ( ! TB || ( FB && TB != Header && FB != Header ) ) return <NUM_LIT> ; bool Negated = ( Cond . size ( ) > <NUM_LIT> ) ^ ( TB != Header ) ; unsigned PredReg = Cond [ Cond . size ( ) - <NUM_LIT> ] . getReg ( ) ; MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ; unsigned CondOpc = CondI -> getOpcode ( ) ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int Mask = <NUM_LIT> , ImmValue = <NUM_LIT> ; bool AnalyzedCmp = TII -> analyzeCompare ( CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ; if ( ! AnalyzedCmp ) return <NUM_LIT> ; OldInsts . push_back ( CondI ) ; OldInsts . push_back ( IVOp ) ; Comparison :: Kind Cmp ; bool isSwapped = false ; const MachineOperand & Op1 = CondI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op2 = CondI -> getOperand ( <NUM_LIT> ) ; const MachineOperand * EndValue = <NUM_LIT> ; if ( Op1 . isReg ( ) ) { if ( Op2 . isImm ( ) || Op1 . getReg ( ) == IVReg ) EndValue = & Op2 ; else { EndValue = & Op1 ; isSwapped = true ; } } if ( ! EndValue ) return <NUM_LIT> ; switch ( CondOpc ) { case <STR_LIT>


<s> SDValue ExpPart = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , DAG . getConstant ( FractBits - <NUM_LIT> ,

<STR_LIT> ) , DAG . getConstant ( ExpBits , <STR_LIT> ) ) ;


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qidi (


<s> void AnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , CCAssignFn Fn , std

:: vector < TargetLowering :: ArgListEntry > & FuncArgs , const char * Func ) {


<s> void i386_pe_adjust_class_at_definition ( tree t ) { tree member ; gcc_assert ( CLASS_TYPE_P ( t ) ) ; if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( t ) ) != NULL_TREE ) { tree tmv = TYPE_MAIN_VARIANT ( t ) ; if ( tmv != NULL_TREE && CLASSTYPE_TYPEINFO_VAR ( tmv ) != NULL_TREE ) { tree na , ti_decl = CLASSTYPE_TYPEINFO_VAR ( tmv ) ; na = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , NULL_TREE ) ; decl_attributes ( & ti_decl , na , <NUM_LIT> ) ; } for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; for ( member = TYPE_METHODS ( t ) ; member ; member = DECL_CHAIN (

member ) ) if ( TREE_CODE ( member ) == FUNCTION_DECL ) {


<s> if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return true ; V = Imm ; if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) != - <NUM_LIT> ) V &= ~ <NUM_LIT> ; else if ( getT2SOImmValSplatVal ( V & <NUM_LIT> ) != - <NUM_LIT> ) V &= ~ <NUM_LIT> ; if ( getT2SOImmVal ( V ) != - <NUM_LIT> ) return true ; return


<s> bool allowMixed16_32 ( ) const { return in<ISA_LIT>16ModeDefault ( ) |


<s> void setSRetReturnReg ( Register Reg ) { SRetReturnReg = Reg


<s> while ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; NumBytes -= <NUM_LIT> ; } assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( HasFP ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } AFI -> setLocalStackSize ( NumBytes ) ; if ( NumBytes ) { if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) TII -> copyPhysReg ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , false ) ; if ( needsFrameMoves ) { const DataLayout * TD = MF . getSubtarget ( ) . getDataLayout ( ) ; const int StackGrowth = - TD -> getPointerSize ( <NUM_LIT> ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( HasFP ) { unsigned Reg = RegInfo -> getDwarfRegNum ( FramePtr , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> * StackGrowth ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) .


<s> return __builtin_mve_vqrdmlsdhq_sv4si ( __inactive ,


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG (


<s> for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { unsigned Reg = it -> getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , it -> getReg ( ) , it -> getFrameIdx ( ) , RC


<s> count = <NUM_LIT> ; if ( TARGET_CHECK_ZERO_DIV ) { if ( GENERATE_DIVIDE_TRAPS ) count ++ ; else count += <NUM_LIT>


<s> SDValue TrueOpnd = N -> getOperand ( <NUM_LIT> ) ; SDValue FalseOpnd = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Cond . getOpcode ( ) != <STR_LIT> || TrueOpnd . getOpcode ( ) != <STR_LIT> || FalseOpnd . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! ( Cond . hasOneUse ( ) || TrueOpnd . hasOneUse ( ) || FalseOpnd . hasOneUse ( ) ) ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TrueOpnd , FalseOpnd ) ; break ; } SDValue CmpOpnd1 = Cond . getOperand ( <NUM_LIT> ) ; SDValue CmpOpnd2 = Cond . getOperand ( <NUM_LIT> ) ; if ( TrueOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd1 && TrueOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd2 && FalseOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd2 && FalseOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd1 ) { return DAG . getNode ( <STR_LIT> , dl , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) , CmpOpnd1 , CmpOpnd2 , DAG . getTargetConstant


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex


<s> if ( ! DstTy . isVector ( ) || ! SrcTy . isVector ( ) ) return false ; assert ( SrcTy . getSizeInBits ( ) > DstTy . getSizeInBits ( ) && <STR_LIT> ) ; if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else return false ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstReg , MRI ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcReg , MRI ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg


<s> if ( ! STI . is64Bit ( ) || ! MF . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI . getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME .


<s> if ( words ) * cum = ROUND_ADVANCE_CUM ( * cum , arg . mode , arg . type ) ; for ( i = <NUM_LIT> ; i < words ; i ++


<s> SDValue Hint = Op . getOperand ( <NUM_LIT> ) ; unsigned HintVal ; if ( dyn_cast < ConstantSDNode > ( Hint ) == nullptr || ( HintVal = dyn_cast < ConstantSDNode > ( Hint ) -> getZExtValue ( ) ) > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned Opcode = ( HintVal ? Intr . Opc1 : Intr . Opc0 ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getPrefetchNode ( Opcode , Op , DAG , Mask , Base , Index , Scale , Chain ) ; } case RDTSC : { SmallVector < SDValue , <NUM_LIT> > Results ; getReadTimeStampCounter ( Op . getNode ( ) , dl , Intr . Opc0 , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , dl ) ; } case RDPMC : { SmallVector < SDValue , <NUM_LIT> > Results ; getReadPerformanceCounter ( Op . getNode ( ) , dl , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , dl ) ; } case XTEST : { SDVTList VTs = DAG . getVTList ( Op -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue InTrans = DAG . getNode ( <STR_LIT> , dl , VTs , Op . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , InTrans ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , dl , Op -> getValueType ( <NUM_LIT> ) , SetCC ) ; return DAG . getNode ( <STR_LIT> , dl , Op -> getVTList ( ) , Ret , SDValue ( InTrans . getNode ( ) , <NUM_LIT> ) ) ; } } llvm_unreachable ( <STR_LIT> )


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; O << <STR_LIT> ; printAnnotation ( O , Annot


<s> const MDOperand & FuncOperand = MetadataNode -> getOperand ( <NUM_LIT> ) ; if ( ! FuncOperand ) continue ; auto FuncConstant = dyn_cast < ConstantAsMetadata > ( FuncOperand ) ; if ( ! FuncConstant ) continue ; auto Func = dyn_cast < Function > ( FuncConstant -> getValue ( ) ) ; if ( ! Func ) continue ; auto NewFunc = this -> ProcessFunction ( M , Func ) ; if ( NewFunc ) { Changed = true ; MetadataNode -> replaceOperandWith ( <NUM_LIT> , llvm :: ConstantAsMetadata :: get ( NewFunc ) ) ; } } return Changed


<s> static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> if ( WantExtend ) { <STR_LIT> Ext = getExtendTypeForNode ( N . getOperand ( <NUM_LIT> ) , true ) ; if ( Ext == <STR_LIT> ) return false ; Offset = narrowIfNeeded ( CurDAG , N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SignExtend = CurDAG -> getTargetConstant ( Ext == <STR_LIT> , dl , <STR_LIT> ) ; } else { Offset = N . getOperand ( <NUM_LIT> ) ; SignExtend = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; } unsigned LegalShiftVal = Log2_32 ( Size ) ; unsigned ShiftVal = CSD -> getZExtValue ( ) ; if ( ShiftVal != <NUM_LIT> &&

ShiftVal != LegalShiftVal ) return false ;


<s> if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <= <NUM_LIT> ) return <NUM_LIT> ; if ( VGPRs <=


<s> if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC


<s> SmallPtrSet < Instruction * , <NUM_LIT> > Sinks ; WorkList . insert ( V ) ; SmallPtrSet < Value * , <NUM_LIT> > CurrentVisited ; CurrentVisited . clear ( ) ; auto AddLegalInst = [ & ] ( Value * V ) { if ( CurrentVisited . count ( V ) ) return true ; if ( isa < GetElementPtrInst > ( V ) ) return true ; if ( ! isSupportedValue ( V ) || ( shouldPromote ( V ) && ! isLegalToPromote ( V ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } WorkList . insert ( V ) ; return true ; } ; while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) return false ; CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) ) Sources


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , uint64_t required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) { gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value

) -> required_extensions & ~ required_extensions ) == <NUM_LIT> ) ;


<s> } if ( Subtarget -> isTargetWindows ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; IDX = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , IDX , Scale ) ; SDValue res = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , ThreadPointer , IDX ) ; res = DAG . getLoad ( getPointerTy ( ) , dl , Chain , res ,


<s> DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( ST . createFillMFMAShadowMutation ( DAG -> TII ) ) ; return


<s> switch ( i & <NUM_LIT> ) { case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case


<s> return ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm )

&& VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> std :: string Buffer ; { raw_string_ostream TempStream ( Buffer ) ; InstPrinter . printInst ( & Inst , TempStream , <STR_LIT> , STI ) ; } StringRef Contents ( Buffer ) ; auto PacketBundle = Contents . rsplit ( '\n' ) ; auto HeadTail = PacketBundle . first . split ( '\n' ) ; StringRef Separator = <STR_LIT> ; StringRef Indent = <STR_LIT> ; OS << <STR_LIT> ; while ( ! HeadTail . first . empty ( ) ) { StringRef InstTxt ; auto Duplex = HeadTail . first . split ( '\v' ) ; if ( ! Duplex . second . empty ( ) ) { OS << Indent << Duplex . first << Separator ; InstTxt = Duplex . second ; } else if ( ! HeadTail . first . trim ( ) . startswith ( <STR_LIT> ) ) { InstTxt = Duplex . first ; } if ( ! InstTxt . empty ( ) ) OS << Indent << InstTxt << Separator ; HeadTail = HeadTail . second . split ( '\n' ) ; } if ( <ISA_LIT>MCInstrInfo :: isMemReorderDisabled ( Inst ) ) OS << <STR_LIT> << PacketBundle . second ; else OS << <STR_LIT> << PacketBundle .


<s> LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto NumUnmerge = B . buildUnmerge ( S32 , LHS ) ; auto DenUnmerge = B . buildUnmerge ( S32 , RHS ) ; auto Scale0Unmerge = B . buildUnmerge ( S32 , DivScale0 ) ; auto Scale1Unmerge = B . buildUnmerge ( S32 , DivScale1 ) ; auto CmpNum = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , NumUnmerge . getReg ( <NUM_LIT> ) , Scale1Unmerge . getReg ( <NUM_LIT> ) ) ; auto CmpDen = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , DenUnmerge . getReg ( <NUM_LIT> ) , Scale0Unmerge . getReg ( <NUM_LIT> ) ) ; Scale = B . buildXor ( S1 , CmpNum , CmpDen ) . getReg ( <NUM_LIT> ) ; } else { Scale = DivScale1 . getReg ( <NUM_LIT> ) ; } auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( Mul . getReg (

<NUM_LIT> ) ) . addUse ( Scale ) . setMIFlags ( Flags ) ;


<s> <ISA_LIT>PropagateAttributes ( const TargetMachine * TM , bool AllowClone ) : TM ( TM ) , AllowClone


<s> enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; enum machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_loadd ( x , op1 ) ) ; op1 = gen_lowpart ( TImode


<s> <ISA_LIT>_32ATTAsmParser ( const Target & T , MCAsmParser & _Parser , TargetMachine & TM )

: <ISA_LIT>ATTAsmParser ( T , _Parser , TM ) {


<s> Src = B . buildCopy ( Ty , Src ) . getReg ( <NUM_LIT> ) ; MRI . setRegBank ( Src , <STR_LIT> ) ; } LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; unsigned NumParts = Bits / <NUM_LIT> ; SmallVector < Register , <NUM_LIT> > SrcParts ; SmallVector < Register , <NUM_LIT> > DstParts ; if ( Bits == <NUM_LIT> ) { SrcParts . push_back ( Src ) ; } else { auto Unmerge = B . buildUnmerge ( S32 , Src ) ; for ( unsigned i = <NUM_LIT> ; i < NumParts ; ++ i ) SrcParts . push_back ( Unmerge . getReg ( i ) ) ; } for ( unsigned i = <NUM_LIT> ; i < NumParts ; ++ i ) { Register SrcPart = SrcParts [ i ] ; Register DstPart = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . setType ( DstPart , NumParts == <NUM_LIT> ? Ty : S32 ) ; const TargetRegisterClass * Constrained = constrainGenericRegister ( SrcPart , <STR_LIT> , MRI ) ; ( void ) Constrained ; assert ( Constrained && <STR_LIT> ) ; B . buildInstr ( <STR_LIT> , { DstPart


<s> <ISA_LIT>CTRLoops ( ) : FunctionPass ( ID ) { initialize<ISA_LIT>CTRLoopsPass ( * PassRegistry :: getPassRegistry ( )


<s> EVT NodeTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & InFlag , <NUM_LIT> ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD

, DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( TARGET_SIMD && AARCH64_VALID_SIMD_QREG_MODE ( mode ) && ( nelems >= <NUM_LIT> && nelems <= <NUM_LIT> ) )


<s> if ( is_any_def_and ) { gcc_assert ( and_insns . length ( ) == and_ops . length ( ) ) ; rtx src_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; df_ref src_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_USE ( src_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( src_use ) , src_reg ) ) continue ; struct df_link * link = DF_REF_CHAIN ( src_use ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx new_reg = <NUM_LIT> ; rtx and_mask = <NUM_LIT>


<s> SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! isDead ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned i = <NUM_LIT> , n = Regs . size ( ) ; i != n ; ++ i ) MRI . markUsesInDebugValueAsUndef ( Regs [ i ] ) ; Changed = true ; } return


<s> return getRelaxedOpcode ( Inst . getOpcode (


<s> ComplexRendererFns selectAddrModeUnscaled128 ( MachineOperand & Root ) const { return selectAddrModeUnscaled ( Root , <NUM_LIT> )


<s> static unsigned getRetOpcode ( const <ISA_LIT>Subtarget


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Addr , Op . getOperand ( <NUM_LIT> )

, MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : <STR_LIT> ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : <STR_LIT> ( TmpInst ) ; } uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) llvm_unreachable (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT


<s> static bool arm_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type


<s> if ( need_atomic_barrier_p ( model , false ) ) emit_insn ( gen_memory_barrier