<s> int mcore_naked_function_p ( ) { return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) )


<s> const InstType & getRecordedTypeForInstr ( const MachineInstr * MI ) const { assert ( wasVisited ( MI ) && <STR_LIT>


<s> return __builtin_mve_uqrshl_si ( value , shift


<s> bool <ISA_LIT>TargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N


<s> SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , WideVT ) , BitShift ) ; if ( Opcode != <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( <NUM_LIT> - BitSize , WideVT ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( uint32_t ( - <NUM_LIT> ) >> BitSize , WideVT ) ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , Src2 , BitShift , NegBitShift , DAG . getConstant ( BitSize , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( Opcode , DL , VTList , Ops , array_lengthof ( Ops ) , NarrowVT , MMO ) ; SDValue ResultShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift

, DAG . getConstant ( BitSize , WideVT ) ) ;


<s> Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand ::


<s> initSubtargetFeatures ( CPU , FS ) ; return *


<s> const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Addr , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , AddrHi ) ,

<NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , } ;


<s> return ( ( qword ) ( vec_nmsub ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , ( vec_float4 )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCode ( SMLoc L ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Val = Parser . getTok ( ) . getIntVal ( ) ; if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( )


<s> } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , NumBytes , true ) ; -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI


<s> Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } assert ( SrcVT . getSizeInBits ( ) == <NUM_LIT> * VT . getSizeInBits ( ) ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( NumSrcElts ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( NumSrcElts ) ) ; unsigned Imm = Src . MinElt * getExtFactor ( VEXTSrc1 ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; } } for ( auto & Src : Sources ) { EVT SrcEltTy = Src . ShuffleVec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy == SmallestEltTy ) continue ; assert ( ShuffleVT . getVectorElementType ( ) == SmallestEltTy ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , ShuffleVT , Src . ShuffleVec ) ; Src . WindowScale = SrcEltTy . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; Src . WindowBase *= Src . WindowScale ; } DEBUG ( for ( auto Src : Sources ) assert ( Src . ShuffleVec . getValueType ( ) == ShuffleVT ) ; ) ; SmallVector < int , <NUM_LIT> > Mask ( ShuffleVT . getVectorNumElements ( ) , - <NUM_LIT> ) ; int BitsPerShuffleLane = ShuffleVT . getVectorElementType ( ) . getSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) { SDValue Entry = Op . getOperand ( i ) ; if ( Entry . getOpcode ( ) == <STR_LIT>


<s> vdupq_n_s64 ( int64_t __a ) { return ( int64x2_t ) {


<s> void <ISA_LIT>AsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , const char * Modifier ) { if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { printOperand ( MI , opNum + <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , opNum ) ; return ; } printOperand ( MI , opNum ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> ) ; O <<


<s> bool <ISA_LIT>DAGToDAGISel :: foldOffsetIntoAddress ( uint64_t Offset , <ISA_LIT>ISelAddressMode & AM ) { if ( Offset != <NUM_LIT> && ( AM . ES || AM . MCSym ) ) return true ; int64_t Val = AM . Disp + Offset ; CodeModel :: Model M =


<s> if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ; return *


<s> OS << <STR_LIT> ; Symbol -> print ( OS


<s> assert ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_<ISA_LIT>NT && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; switch ( static_cast < unsigned > ( Fixup . getKind ( ) ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF ::


<s> mcld :: TargetRegistry :: RegisterTargetLDBackend ( mcld :: The<ISA_LIT>Target , mcld


<s> } } unsigned Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) ) { Opcode = <STR_LIT> ; OpcodeVT = <STR_LIT> ; RISBG . Start &= <NUM_LIT> ; RISBG . End &= <NUM_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { getUNDEF ( SDLoc ( N ) , OpcodeVT ) , convertTo ( SDLoc ( N ) , OpcodeVT , RISBG . Input ) , CurDAG -> getTargetConstant ( RISBG . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . End | <NUM_LIT> , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , OpcodeVT , Ops ) ; return convertTo ( SDLoc ( N ) , VT , SDValue ( N , <NUM_LIT>


<s> Error ( Loc , Twine ( DepCtrName , <STR_LIT> ) ) ; return ; case OPR_ID_DUPLICATE : Error ( Loc , Twine ( <STR_LIT> , DepCtrName ) ) ; return ; case


<s> Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize ( ) ) , getPointerTy ( ) ) ; IDX = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , IDX , Scale ) ; SDValue res = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , ThreadPointer , IDX ) ; res = DAG . getLoad ( getPointerTy ( ) , dl , Chain , res , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , <STR_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , res ,


<s> SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget , OptLevel ) ; if ( Result . getNode ( ) ) return Result ; return PerformADDCombineWithOperands ( N , N1 , N0 ,


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant


<s> assert ( ( Kind == k_MImmOp ) && <STR_LIT> ) ; return MImm


<s> void <ISA_LIT>TargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( llvm :: any_of ( Regs , [ & STI ] ( auto Reg ) { return STI . isRegisterReservedByUser ( Reg . first ) ; } ) ) F . getContext ( ) . diagnose (


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForCall ( )


<s> bool cris_return_address_on_stack ( void ) { return df_regs_ever_live_p ( CRIS_SRP_REGNUM ) ||

cfun -> machine -> needs_return_address_on_stack ;


<s> while ( <NUM_LIT> ) { unsigned NextReg = SrcReg ; MachineInstr * Inst = MRI -> getVRegDef ( SrcReg ) ; if ( BB1 && Inst -> getOpcode ( ) == <STR_LIT> && Inst -> getParent ( ) == BB2 ) { NextReg = getIncomingRegForBlock ( Inst , BB1 ) ; BB1 = nullptr ; } else if ( Inst -> isFullCopy ( ) ) NextReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( NextReg == SrcReg || ! Register :: isVirtualRegister


<s> MCStreamer :: EmitWinEHHandlerData ( ) ; MCWin64EHUnwindEmitter :: EmitUnwindInfo ( * this


<s> __vector signed int a , b , c ; a = ( __vector signed int ) vec_splats ( __m1 ) ; b = ( __vector signed int ) vec_splats ( __m2 ) ; c = vec_sub ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_int [ <NUM_LIT> ] = m1 . as_int [ <NUM_LIT> ] - m2 . as_int [ <NUM_LIT> ] ; res . as_int [ <NUM_LIT> ] = m1 . as_int [ <NUM_LIT> ] - m2 . as_int [ <NUM_LIT> ] ; return ( __m64 ) res


<s> if ( S . getSUnit ( ) -> isBoundaryNode ( ) || isScheduled ( S . getSUnit ( ) ) || S . getKind ( ) != SDep :: Data ) continue ; for ( const auto & P : S . getSUnit ( ) -> Preds ) { auto PSU = P . getSUnit ( ) ; assert ( ! PSU -> isBoundaryNode ( ) ) ; if ( PSU != SchedSU && ! isScheduled ( PSU ) ) { Set . insert ( PSU ) ; } } } SmallVector < const SUnit * , <NUM_LIT> > Worklist ( Set . begin ( ) , Set .


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; } return Reserved


<s> Triple TheTriple ( TT ) ; bool is<ISA_LIT>64 = TheTriple . getArch ( ) == Triple :: ppc64 ; if ( TheTriple . getOS ( ) == Triple :: Darwin ) return new


<s> void emitHiddenKernelArgs ( const MachineFunction & MF , unsigned & Offset , msgpack :: ArrayDocNode Args ) override { llvm_unreachable ( <STR_LIT>


<s> } } for ( typename SmallVector < BlockT * , DEFAULT_VEC_SLOTS > :: iterator iter = contBlk . begin ( ) , iterEnd = contBlk . end ( ) ; iter != iterEnd ; ++ iter ) { ( * iter ) -> removeSuccessor ( loopHeader ) ; } numLoopcontPatternMatch += numCont ; return numCont


<s> if ( ! eq ) { error ( <STR_LIT> <STR_LIT> ) ; return false ; } while ( ISSPACE ( * ( ++ eq ) ) ) ; while ( ISSPACE ( * ( -- end_eq ) ) ) ; nios2_handle_custom_fpu_cfg ( eq , end_eq + <NUM_LIT> , true ) ; } else if ( ! strncmp ( argstr , <STR_LIT> , <NUM_LIT> ) ) { int code = - <NUM_LIT> ; unsigned int i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) if ( ! strncmp ( argstr + <NUM_LIT> , N2FPU_NAME ( i ) , strlen ( N2FPU_NAME ( i ) ) ) ) { code = i ; break ; } if ( code >= <NUM_LIT> ) { if ( no_opt ) { if ( eq ) { error ( <STR_LIT> , N2FPU_NAME ( code ) ) ; return false ; } nios2_deregister_custom_code ( N2FPU_N ( code ) ) ; N2FPU_N ( code ) = - <NUM_LIT> ; } else { char * t ; if ( eq ) while ( ISSPACE ( * ( ++ eq ) ) ) ; if ( ! eq || eq == p ) { error ( <STR_LIT> , N2FPU_NAME ( code ) ) ; return false ; } for ( t = eq ; t != p ; ++ t ) { if ( ISSPACE ( * t ) ) continue ; if ( ! ISDIGIT (


<s> static bool is<ISA_LIT>LogicalCmp ( SDValue Op ) { unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ; return false


<s> void setShuffleError ( unsigned e ) { s . ShuffleError =


<s> if ( TARGET_FPU_ANY && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode ==


<s> if ( lv -> StepSel ) mask |= <NUM_LIT> ; if ( lv -> IsPredicated ) mask |= <NUM_LIT> ; switch ( mask ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> return Error ( NameLoc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( Name , NameLoc , * this ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) && ParseBracketSuffix ( Name , Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( ParseBracketSuffix ( Name , Operands ) ) return true ; } else if ( getLexer ( ) . is ( AsmToken :: LParen ) && ParseParenSuffix ( Name , Operands ) ) return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( )


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const


<s> } if ( CM == CodeModel :: Default ) { Triple T ( TT ) ; if ( ! T . isOSDarwin ( ) && ( T . getArch ( ) == Triple :: ppc64 || T .

getArch ( ) == Triple :: ppc64le ) ) CM = CodeModel :: Medium ;


<s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , <STR_LIT>


<s> if ( ! AddRec ) return p_SEL -> getZero ( Expr -> getType ( ) ) ; if ( AddRec -> getLoop ( ) == TargetLoop ) return AddRec -> getStepRecurrence ( *


! TARGET_DFP || ! TARGET_64BIT || GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && ( ! TARGET_VX || ( SCALAR_FLOAT_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) > <NUM_LIT> ) ) ) ;


<s> AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU )


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; Register FramePointer = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const Register ActualNegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool KillNegSizeReg = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; Register NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCInstrDesc & CopyInst = TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ; if ( FramePointer == NegSizeReg ) { assert ( KillNegSizeReg && <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , II , dl , CopyInst , ActualNegSizeReg ) . addReg ( NegSizeReg ) . addReg ( NegSizeReg ) ; NegSizeReg =


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) || LdSt . getNumExplicitOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( )


<s> Register <ISA_LIT>FunctionInfo :: getGlobalBaseRegForGlobalISel ( MachineFunction & MF ) { if ( static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . useCheriCapTable ( ) ) { if ( ! CapGlobalBaseReg ) { getCapGlobalBaseReg ( MF ) ; initCapGlobalBaseReg ( MF ) ; } return CapGlobalBaseReg ; } if ( ! GlobalBaseReg )


<s> EVT N00VT = N00 . getValueType ( ) ; if ( N00VT == N10 . getValueType ( ) && ( N00VT == <STR_LIT> || N00VT == <STR_LIT> ) && N00VT . getScalarSizeInBits ( ) == <NUM_LIT> * VT . getScalarSizeInBits ( ) ) { MVT MidVT = ( N00VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ( MidVT . getVectorNumElements ( ) ) ; for ( size_t i = <NUM_LIT> ; i < Mask . size ( ) ; ++ i ) Mask [ i ] = i * <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( MidVT , dl , DAG . getNode ( <STR_LIT> , dl , MidVT , N00 ) , DAG . getNode ( <STR_LIT> , dl , MidVT , N10 ) , Mask ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N0 == N1 && VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidenVector ( N0 , DAG ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( N1 -> getOpcode ( ) !=


<s> } ) ; assert ( ReservedVGPRInfoItr != FuncInfo -> getSGPRSpillVGPRs ( ) . end ( ) ) ; auto Index = std :: distance ( FuncInfo -> getSGPRSpillVGPRs ( ) . begin ( ) , ReservedVGPRInfoItr ) ; FuncInfo -> setSGPRSpillVGPRs ( LowestAvailableVGPR , FI , Index ) ; for ( MachineBasicBlock & MBB : MF ) { assert ( LowestAvailableVGPR . isValid ( ) && <STR_LIT> ) ; MBB . addLiveIn ( LowestAvailableVGPR ) ; MBB . sortUniqueLiveIns (


<s> void <ISA_LIT>ELFObjectWriter :: sortRelocs ( const MCAssembler & Asm , std :: vector < ELFRelocationEntry > & Relocs ) { if ( Relocs . size ( ) < <NUM_LIT> ) return ; array_pod_sort ( Relocs . begin ( ) , Relocs . end ( ) , cmpRel ) ; std :: vector < <ISA_LIT>RelocationEntry > <ISA_LIT>Relocs ; for ( unsigned I = <NUM_LIT> , E = Relocs . size ( ) ; I != E ; ++ I ) <ISA_LIT>Relocs . push_back ( <ISA_LIT>RelocationEntry ( Relocs [ I ] ) ) ; for ( int32_t I = <NUM_LIT> , E = <ISA_LIT>Relocs . size ( ) ; I != E ;


<s> return ELF :: R_<ISA_LIT>_32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_7_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_13_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_6_ADIW ; case <STR_LIT>


<s> unsigned TypeSize = DL . getTypeStoreSize ( ParamTy ) ; Register PtrReg = lowerParameterPtr ( B , ParamTy , Offset ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , TypeSize , Align ) ; B . buildLoad ( DstReg , PtrReg


<s> void <ISA_LIT>AsmPrinter :: emitEndOfAsmFile ( Module & M ) { for ( std :: map < const char * , const <STR_LIT> * > :: const_iterator it = StubsNeeded . begin ( ) ; it != StubsNeeded . end ( ) ; ++


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz


<s> return BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get


<s> } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT . first


<s> std :: map < unsigned , MachineInstr * > ColCfgs ; getTileShapesCfg ( CfgMI , ShapedTiles ) ; assert ( ShapedTiles . size ( ) && <STR_LIT> ) ; getShapeCfgInstrs ( CfgMI , RowCfgs


<s> getParser ( ) . parseStringToEndOfStatement ( ) ; return


<s> bool <ISA_LIT>Z80TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return


<s> static int rs6000_clone_priority ( tree fndecl ) { tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; HOST_WIDE_INT isa_masks ; int ret = CLONE_DEFAULT ; tree attrs = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; const char * attrs_str = NULL ; attrs = TREE_VALUE ( TREE_VALUE ( attrs ) ) ; attrs_str = TREE_STRING_POINTER ( attrs ) ; if ( strcmp ( attrs_str , <STR_LIT> ) != <NUM_LIT> ) { if ( fn_opts == NULL_TREE ) fn_opts = target_option_default_node ; if ( ! fn_opts || ! TREE_TARGET_OPTION ( fn_opts ) )


<s> assert ( MI -> getOpcode ( ) == TargetOpcode :: COPY && <STR_LIT> ) ; for ( const auto & MO : MI -> operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg (


<s> InsertedThunks = false ; return false


<s> for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return


<s> bool isLegalMaskedLoadStore ( Type * DataType , Align Alignment ) { if ( ! ST -> hasSVE ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ! ST -> useSVEForFixedLengthVectors ( ) ) return false ; return ! DataType -> getScalarType ( ) -> isIntegerTy ( <NUM_LIT> ) && isElementTypeLegalForScalableVector ( DataType


, <NUM_LIT> , ( __mmask32 ) - <NUM_LIT> ) ;


<s> static void mips_print_float_branch_condition ( FILE * file , enum rtx_code code , int letter ) { switch ( code ) { case EQ : if ( ISA_HAS_CCF ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> ,


<s> unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize


<s> int64_t getFramePoppedByCallee ( const MachineInstr & MI ) const { assert ( isFrameInstr ( MI ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) .

getImm ( ) >= <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . is256BitVector ( ) && SubVecVT . is128BitVector ( ) ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( SubVec2 . getNode ( ) && SubVec2 . getOpcode ( ) == <STR_LIT> ) SubVec2 = SubVec2 . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( SubVec2 ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment


<s> bool Changed = false ; for ( auto FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed


<s> return CFP -> isExactlyValue ( <NUM_LIT> ) ; } return isAllOnesConstant ( Op )


<s> unsigned Reg = SavedRegs [ I ] ; if ( Reg == <NUM_LIT> ) continue ; int CURegNum = getCompactUnwindRegNum ( Reg , Is64Bit ) ; if ( CURegNum == - <NUM_LIT> ) return ~ <NUM_LIT> ; RegEnc |= ( CURegNum & <NUM_LIT> ) << ( Idx ++ * <NUM_LIT> ) ; } assert ( ( RegEnc & <NUM_LIT> ) == RegEnc && <STR_LIT> ) ; return


<s> Op -> Kind = Memory ; Op -> Mem . BaseRegNum = BaseRegNum ; Op -> Mem . OffsetIsReg = OffsetIsReg ; Op -> Mem . Offset = Offset ; Op -> Mem . OffsetRegNum = OffsetRegNum ; Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc


<s> Name = Name . drop_front ( <NUM_LIT> ) ; } size_t p = <NUM_LIT> ; size_t q = <NUM_LIT> ; while ( q != StringRef :: npos ) { q = Name . find_first_not_of ( Syntax , p ) ; if ( q != p ) { NewName += Name . slice ( p , q ) ; } if ( q == StringRef :: npos ) break ; NewName += '_'


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) )


<s> case SYMBOL_REF : output_addr_const ( stream , x ) ; break ; case REG : if ( TARGET_REDUCED_REGS && REGNO ( x ) == STATIC_CHAIN_REGNUM ) sorry ( <STR_LIT> ) ; fputs ( reg_names [ REGNO ( x ) ] , stream ) ; break ; case MEM : output_address ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) ) ; break ; case CODE_LABEL : case CONST_INT : case CONST


<s> if ( attr ) { tree id = TREE_VALUE ( TREE_VALUE ( attr ) ) ; const char * name ; if ( TREE_CODE ( id ) == IDENTIFIER_NODE ) name = IDENTIFIER_POINTER ( id ) ; else if ( TREE_CODE ( id ) == STRING_CST ) name = TREE_STRING_POINTER ( id ) ; else abort ( ) ; fprintf ( file , <STR_LIT> , name ) ; } else fprintf ( file , <STR_LIT> , COMMON_ASM_OP ) ; assemble_name ( file , name ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , size , align / BITS_PER_UNIT ) ; fputc ( '\n' ,


<s> const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! MFI -> isEntryFunction ( ) ) { return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; } B . setInstr ( MI ) ; uint64_t Offset = ST . getTargetLowering ( ) -> getImplicitParameterOffset ( B . getMF ( ) , <ISA_LIT>TargetLowering :: FIRST_IMPLICIT ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI .


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT>


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo <

<ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; bool EltIs64Bits = DL . getTypeSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; if ( EltTy -> isHalfTy ( ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( )


<s> return ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) .


<s> const LLT Ty = MRI . getType ( Reg ) ; if ( ! Ty . isValid ( ) || Ty . getSizeInBits ( ) != <NUM_LIT> ) return false ; return MRI . getVRegDef ( Reg ) -> getOpcode ( ) != <STR_LIT> && RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID


<s> return TM . TargetABI == <ISA_LIT>BaseTargetMachine


<s> int getVariadicGPRIdx ( ) const { return VariadicGPRIdx


<s> if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult .


<s> void print<ISA_LIT>NegImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { int value = MI -> getOperand ( OpNo


<s> static bool isCalleeLoad ( SDValue Callee , SDValue & Chain , bool HasCallSeq ) { if ( Callee . getNode ( ) == Chain . getNode ( ) || ! Callee . hasOneUse ( ) ) return false ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( Callee . getNode ( ) ) ; if ( ! LD || ! LD -> isSimple ( ) || LD -> getAddressingMode ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> ) return false ; while ( HasCallSeq && Chain . getOpcode ( ) != <STR_LIT> ) { if ( ! Chain . hasOneUse ( ) ) return false ; Chain = Chain . getOperand ( <NUM_LIT> ) ; } if ( ! Chain . getNumOperands


<s> RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; SDValue InVal ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , true ) ; InVal = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVal = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , false , false ,


<s> const uint16_t * <ISA_LIT>65816RegisterInfo :: getCalleeSavedRegs ( const MachineFunction


<s> REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_DOUBLE_P ( elt ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ; if ( real_equal ( & r , & dconsthalf


<s> assert ( isReg ( ) && <STR_LIT> ) ; return Reg .


<s> Base = CurDAG -> getRegister ( AMDGPU :: INDIRECT_BASE_ADDR , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; } else if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) && ( C = dyn_cast <

ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) ) {


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType


<s> case CallingConv :: <ISA_LIT>_HS : return R_00B428_SPI_SHADER_PGM_RSRC1_HS ; case CallingConv :: <ISA_LIT>_GS : return R_00B228_SPI_SHADER_PGM_RSRC1_GS ; case CallingConv :: <ISA_LIT>_PS :


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isCortexA53 ( ) || TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isCortexA57 ( ) ) && usingDefaultRegAlloc ( )

) addPass ( create<ISA_LIT>A57FPLoadBalancing ( ) ) ;


<s> uint64_t MulFactor = <NUM_LIT> << N -> getConstantOperandVal ( <NUM_LIT> ) ; return CurDAG -> getConstant ( MulFactor , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) .


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder ,


<s> SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( MILabel ) ; SM . recordPatchPoint ( * MILabel , MI ) ; PatchPointOpers opers ( & MI ) ; unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ; if ( ! ( CalleeMO . isImm ( ) && !


<s> case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; printOffset ( MO . getOffset ( ) , O ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex


<s> lshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; shmask = vec_cmplt ( lshift , shmax ) ; result = vec_sl ( ( __v4su ) __A , lshift ) ; result = vec_sel ( ( __v4su ) shmask ,


<s> if ( BitSize == <NUM_LIT> ) return TTI :: TCC_Free ; if ( BitSize > <NUM_LIT> ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> : case <STR_LIT>


<s> return new <ISA_LIT>ELFTargetAsmInfo (


<s> bool isGP64bit ( ) const { return IsGP64bit


<s> for ( rd = <NUM_LIT> ; rd < <NUM_LIT> ; rd ++ ) { u = ( ( u >> <NUM_LIT> ) & <NUM_LIT> ) | ( u << <NUM_LIT> ) ; if ( ( - <NUM_LIT> <= ( int32_t ) u ) && ( ( int32_t ) u <= <NUM_LIT> ) ) { ft32_load_immediate ( dst , ( int32_t ) u ) ; sprintf ( pattern , <STR_LIT> , rd ) ; output_asm_insn ( pattern , & dst ) ; return <STR_LIT> ; } } ft32_load_immediate ( dst , i >> <NUM_LIT> ) ; sprintf ( pattern , <STR_LIT> ,


<s> if ( ! Subtarget -> isTargetLinux ( ) ) return TargetLowering :: insertS<ISA_LIT>Declarations ( M


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL

) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) {


<s> auto Loc = getLoc ( ) ; if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth ) ) return <STR_LIT> ; if ( RegWidth != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } for ( ; trySkipToken ( AsmToken :: Comma ) ; ) { RegisterKind NextRegKind ; unsigned NextReg , NextRegNum , NextRegWidth ; Loc = getLoc ( ) ; if ( ! Parse<ISA_LIT>Register ( NextRegKind , NextReg , NextRegNum , NextRegWidth , Tokens ) ) { return <STR_LIT> ; } if ( NextRegWidth != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } if ( NextRegKind !=


<s> unsigned Reg = MRI -> createVirtualRegister ( PromoteRC ) ; auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ( Cond ) ) , Reg ) ; ( void ) SetI


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs


<s> bool <ISA_LIT>StackModel :: runOnBasicBlocks ( MachineFunction & MF , const Stack & StartStack ) { bool Changed = false ; auto & FirstBB = MF . front ( ) ; BBInfo [ & FirstBB ] . setFixedBegin ( StartStack ) ; using RPOTType = ReversePostOrderTraversal < MachineFunction * > ; RPOTType RPOT ( & MF ) ; llvm :: dbgs ( ) << <STR_LIT> ; for ( RPOTType :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) { auto MBB = * I ; llvm :: dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) ; } llvm :: dbgs ( ) << <STR_LIT> ; for ( RPOTType :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) { auto MBB = * I ; auto & bbInfo = BBInfo [ MBB ] ; auto CurrentStack = bbInfo . fixedBegin


<s> switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; } case AsmToken :: Integer : case AsmToken :: Minus : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( IdVal ,


<s> case <NUM_LIT> : switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : return MCDisassembler :: Fail ; default : align = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT>


<s> bool sh_cfun_resbank_handler_p ( void ) { return ( ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) && ( lookup_attribute

( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) && TARGET_SH2A ) ;


<s> if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , DAG , Subtarget , IsFadd ) ) return DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ; return SDValue ( )


<s> MachineFunctionPass ( ID ) , PTM ( tm ) , STC ( tm . getSubtarget < <ISA_LIT>Subtarget


<s> auto_vec < tree , <NUM_LIT> > argument_types ; function_instance function_instance ( group . base_name , * group . base , * group . shape , group . ops_infos . types [ vec_type_idx ] , group . preds [ pred_idx


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case VK_<ISA_LIT>_HI : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ; break ; case VK_<ISA_LIT>_HA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; break ; case VK_<ISA_LIT>_HIGH : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGH ; break ; case VK_<ISA_LIT>_HIGHA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHA ; break ; case VK_<ISA_LIT>_HIGHERA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case VK_<ISA_LIT>_HIGHER : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case VK_<ISA_LIT>_HIGHEST : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case VK_<ISA_LIT>_HIGHESTA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; } Sym = MCSymbolRefExpr :: create ( & Sym ->


<s> LoADDI = MRI -> use_begin ( HiLuiDestReg ) -> getParent ( ) ; if ( LoADDI -> getOpcode ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || LoADDI -> getOperand ( <NUM_LIT> ) .

getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( LoADDI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: isIndirectCall ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasAVX512 ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . hasVLX ( ) && Super -> getSize ( ) == RC -> getSize ( ) ) return Super ; break ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVLX ( ) && Super -> getSize ( ) ==


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true


<s> return __builtin_loongson_psubh_u ( s , t


<s> FunctionPass * llvm :: create<ISA_LIT>DebugFixup ( ) { return new <ISA_LIT>DebugFixup (


<s> for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; SmallString < <NUM_LIT> > name ; for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e ; ++ i ) { if ( Subtarget -> isTargetWindows ( ) ) name = <STR_LIT> ; else name = <STR_LIT> ; name += DLLExportedGlobals [ i ] -> getName ( ) ; if ( Subtarget -> isTargetWindows ( ) ) name += <STR_LIT> ; else name += <STR_LIT> ; OutStreamer . EmitBytes ( name ) ; } for ( unsigned i = <NUM_LIT> , e = DLLExportedFns . size ( ) ; i != e ; ++ i ) { if ( Subtarget -> isTargetWindows ( ) ) name = <STR_LIT> ; else name = <STR_LIT> ; name += DLLExportedFns [ i ] -> getName ( ) ; OutStreamer . EmitBytes ( name ) ; } } } if ( Subtarget -> isTargetELF ( ) ) { const TargetLoweringObjectFileELF & TLOFELF = static_cast < const TargetLoweringObjectFileELF & > ( getObjFileLowering ( ) ) ; MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT> )


<s> bool isToken ( ) const override { return Kind


<s> const unsigned ValSize = ValTy . getSizeInBits ( ) ; const LLT MemTy = MMO -> getMemoryType ( ) ; const Align MemAlign = MMO -> getAlign ( ) ; const unsigned MemSize = MemTy . getSizeInBits ( ) ; const unsigned AlignInBits = <NUM_LIT> * MemAlign . value ( ) ; if ( shouldWidenLoad ( ST , MemTy , AlignInBits , AddrSpace , MI . getOpcode ( ) ) ) { const unsigned WideMemSize = PowerOf2Ceil ( MemSize ) ; if ( WideMemSize == ValSize ) { MachineFunction & MF = B . getMF ( ) ; MachineMemOperand * WideMMO = MF . getMachineMemOperand ( MMO , <NUM_LIT> , WideMemSize / <NUM_LIT> ) ; Observer . changingInstr ( MI ) ; MI . setMemRefs ( MF , { WideMMO } ) ; Observer . changedInstr ( MI ) ; return true ; } if ( ValSize > WideMemSize ) return false ; LLT WideTy = widenToNextPowerOf2 ( ValTy ) ; Register WideLoad ; if ( ! WideTy . isVector ( ) ) { WideLoad = B . buildLoadFromOffset ( WideTy , PtrReg , * MMO , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; B . buildTrunc ( ValReg , WideLoad ) . getReg ( <NUM_LIT> ) ; } else


<s> static bool isGPR ( const TargetRegisterClass * RC ) { return <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq

( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & )


<s> SDValue In = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; unsigned Opc = Op . getOpcode ( ) ; bool IsSigned = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( VT . isScalableVector ( ) ) { if ( InVT . getVectorElementType ( ) == <STR_LIT> ) { unsigned CastOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; EVT CastVT = getPromotedVTForPredicate ( InVT ) ; In = DAG . getNode ( CastOpc , dl , CastVT , In ) ; return DAG . getNode ( Opc , dl , VT , In ) ; } unsigned Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opcode ) ; } if ( useSVEForFixedLengthVectorVT ( VT ) || useSVEForFixedLengthVectorVT ( InVT ) ) return LowerFixedLengthIntToFPToSVE ( Op , DAG ) ; uint64_t VTSize = VT . getFixedSizeInBits ( ) ; uint64_t InVTSize = InVT . getFixedSizeInBits ( ) ; if ( VTSize < InVTSize ) { MVT CastVT = <STR_LIT> ( <STR_LIT> ( InVT . getScalarSizeInBits ( ) ) , InVT .


<s> case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return LowerGlobalAddress ( MFI , Op , DAG ) ; } case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerADDRSPACECAST ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return lowerTRAP ( Op , DAG ) ; case <STR_LIT> : return lowerDEBUGTRAP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return splitUnaryVectorOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFMINNUM_FMAXNUM ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget )


<s> if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ; Value |= tmp &


<s> bool <ISA_LIT>PreEmitPeephole :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator MBBE = MBB . getFirstTerminator ( ) ; if ( MBBE != MBB . end ( ) ) { MachineInstr & MI = * MBBE ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Changed |= optimizeVccBranch ( MI ) ; continue ; default : break ; } } if ( ! ST . hasVGPRIndexMode ( ) ) continue ; MachineInstr * SetGPRMI = nullptr ; const unsigned Threshold = <NUM_LIT> ; unsigned Count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; ++ MBBI ; if ( Count == Threshold ) SetGPRMI


<s> if ( CONSTANT_ADDRESS_P ( xfoo0 ) && GET_CODE ( xfoo1 ) == REG ) return <NUM_LIT> ; if ( CONSTANT_ADDRESS_P ( xfoo1 ) && GET_CODE ( xfoo0


<s> return getParser ( ) . Warning ( L , Msg


<s> TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV ,


<s> return __builtin_mve_vcmphiq_v16qi ( __a ,


<s> else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * TFL = Subtarget . getFrameLowering <


<s> if ( OPTION_SET_P ( rs6000_cpu_index ) ) { fprintf ( file , <STR_LIT> , start , processor_target_table [ rs6000_cpu_index ] . name ) ; start = <STR_LIT> ; } if ( OPTION_SET_P ( rs6000_tune_index ) ) { fprintf ( file , <STR_LIT> , start , processor_target_table [ rs6000_tune_index ] . name ) ; start = <STR_LIT> ; } if ( PPC405_ERRATUM77 ) { fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; } switch ( rs6000_sdata ) { case SDATA_NONE : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_DATA : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata && g_switch_value ) { fprintf ( file , <STR_LIT> , start , g_switch_value ) ; start = <STR_LIT> ; } if ( * start == '\0' ) putc ( '\n' , file ) ; } rs6000_machine = rs6000_machine_from_flags ( ) ; emit_asm_machine ( ) ; if ( DEFAULT_ABI == ABI_ELFv2 ) fprintf ( file ,


<s> Ops [ <NUM_LIT> ] = SDNodeArg ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( switchType , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = ( SDNodeArg2 == nullptr ) ? DAG . getUNDEF


<s> if ( N . getOpcode ( ) != <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT>


<s> return ( ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ? reg_no <= LAST_LO_REGNUM : ( reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM ) ) || reg_no >= FIRST_PSEUDO_REGISTER ; } else if ( ( ( code == POST_MODIFY || code == PRE_MODIFY ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && XEXP ( op , <NUM_LIT> ) == XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) && REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) || ( reload_completed && code == PLUS && REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ) { reg_no = REGNO ( XEXP ( op , <NUM_LIT> ) ) ; if ( code == PLUS ) val = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; else val = INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; switch ( mode ) { case E_V16QImode


<s> case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_255 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc ,


<s> void <ISA_LIT>DAGToDAGISel :: EmitSpecialCodeForMain ( MachineBasicBlock * BB , MachineFrameInfo * MFI ) { const TargetInstrInfo * TII = getInstrInfo (


<s> return emitAddSub_ri ( false , RetVT , LHSReg , LHSIsKill ,


<s> bool <ISA_LIT>InstrInfo :: isImmOperandLegal ( const MachineInstr * MI , unsigned OpNo , const MachineOperand & MO ) const { const MCOperandInfo & OpInfo = get ( MI -> getOpcode ( ) ) . OpInfo [ OpNo ] ; assert ( MO . isImm ( ) || MO .


<s> return __builtin_ia32_comisdle ( ( __v2df ) __A , ( __v2df )


<s> unsigned RegNo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegNo ) ) { OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + getVirtualRegisterName ( RegNo ) ) ; } else { const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + STI . getRegisterInfo ( ) -> getName ( RegNo ) ) ; } OutStreamer -> AddBlankLine ( )


<s> assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA


<s> uint64_t Immed = cast < ConstantSDNode > ( N . getNode ( ) ) -> getZExtValue ( ) ; unsigned ShiftAmt ; if ( Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; } else if ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) { ShiftAmt = <NUM_LIT> ; Immed = Immed >> <NUM_LIT> ; } else return false ; unsigned ShVal = <STR_LIT> ( <STR_LIT> , ShiftAmt ) ; Val = CurDAG -> getTargetConstant ( Immed , <STR_LIT> ) ; Shift = CurDAG -> getTargetConstant ( ShVal , <STR_LIT> ) ; return true


<s> tree idp ; rtlname = XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , <NUM_LIT> ) ; if ( mcore_dllexport_name_p ( oldname ) ) return ; newname = XALLOCAVEC ( char , strlen ( oldname ) + <NUM_LIT> ) ; sprintf ( newname , <STR_LIT> , oldname ) ; idp = get_identifier (


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultSMEMOffset ( ) const { return <ISA_LIT>Operand :: CreateImm ( this , <NUM_LIT> , SMLoc ( )


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit , CPUType , CPUSubtype ) , OS ,


<s> BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: SReg_64RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_64RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B64 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: SReg_128RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_128RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_3 ; } else if ( AMDGPU :: SReg_256RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_256RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_7 ; } else if ( AMDGPU :: SReg_512RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_512RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_15 ; } else if ( AMDGPU :: VGPR_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VGPR_32RegClass . contains ( SrcReg ) || AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_MOV_B32_e32 ) , DestReg ) .


<s> MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction


<s> static DecodeStatus DecodeT2AddrModeImm7s4 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeT2Imm7S4 ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S


<s> ++ NumIter ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NumIter << <STR_LIT> << NumRemainedBlk << <STR_LIT> ; ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator E = OrderedBlks . end ( ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator SccBeginIter = It ; MachineBasicBlock * SccBeginMBB = nullptr ; int SccNumBlk = <NUM_LIT> ; int SccNumIter ; while ( It != E ) { MBB = * It ; if ( ! SccBeginMBB ) { SccBeginIter = It ; SccBeginMBB = MBB ; SccNumIter = <NUM_LIT> ; SccNumBlk = NumRemainedBlk ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( SccBeginMBB ) ; dbgs ( ) << <STR_LIT> ; ) ; } if ( ! isRetiredBlock ( MBB ) ) patternMatch ( MBB ) ; ++ It ; bool ContNextScc = true ; if ( It == E || getSCCNum ( SccBeginMBB ) != getSCCNum ( * It ) ) { ++ SccNumIter ; int sccRemainedNumBlk = countActiveBlock ( SccBeginIter , It ) ; if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk >= SccNumBlk ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter ; dbgs ( ) << <STR_LIT> ; ) ; ContNextScc = true ; } else if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk < SccNumBlk ) { SccNumBlk = sccRemainedNumBlk ; It = SccBeginIter ; ContNextScc = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter << '\n' ; ) ; } else { ContNextScc = true ; } } else { ContNextScc =


<s> static NodeType * getEntryNode ( const


<s> const <ISA_LIT>FrameLowering * <ISA_LIT>Subtarget :: getFrameLowering ( ) const { return &


<s> int M = Mask [ Lane + Elt ] ; if ( M < <NUM_LIT> ) continue ; if ( M < NumElts ) { Blend1 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range1 . first = std :: min ( Range1 . first , M ) ; Range1 . second = std :: max ( Range1 . second , M ) ; } else { M -= NumElts ; Blend2 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range2 . first = std :: min ( Range2 . first , M ) ; Range2 . second = std :: max ( Range2 . second , M ) ; } } } if ( ! ( <NUM_LIT> <= Range1 . first && Range1 . second < NumEltsPerLane ) || ! ( <NUM_LIT> <= Range2 . first && Range2 . second < NumEltsPerLane ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> && ( Blend1 || Blend2 ) ) return SDValue ( ) ; auto RotateAndPermute = [ & ] ( SDValue Lo , SDValue Hi , int RotAmt , int Ofs ) { MVT ByteVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits (


<s> SelectionDAG & DAG = DCI . DAG ; if ( ! isS16 ( OpS16 , DAG ) && ! isSRA16 ( OpS16 ) ) { OpS16 = OpS32 ; OpS32 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } SDLoc dl ( OR ) ; unsigned Opcode = <NUM_LIT> ; if ( isS16 ( OpS16 , DAG ) ) Opcode = <STR_LIT> ; else if ( isSRA16 ( OpS16 ) ) { Opcode = <STR_LIT> ; OpS16 = OpS16 -> getOperand ( <NUM_LIT> ) ; } else return SDValue ( ) ; SDValue Res = DAG . getNode ( Opcode , dl , <STR_LIT> , OpS32 , OpS16 ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( OR , <NUM_LIT> ) , Res ) ; return SDValue ( OR


<s> uint32_t ParseBits = ( Count % ( MaxPacketSize * HEXAGON_INSTR_SIZE ) ) ? ParseIn : ParseEnd ; <STR_LIT> :: write < uint32_t > ( OS , Nopcode | ParseBits , Endian ) ; } return true


<s> block -> flags &= ~ BB_VISITED ; BB_SET_SESE ( block ,


<s> MachineInstr * NewInst = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opc ) ) . addDef ( Dest ) . add ( BaseAddr ) . addImm ( Offset ) . addUse ( TiedDest ) . addMemOperand ( * I . memoperands_begin ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * NewInst , TII


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc SL ( N ) ; if ( ! Subtarget -> hasDLInsts ( ) || VT != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; SDValue FMA = N -> getOperand ( <NUM_LIT> ) ; if ( FMA . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetOptions & Options = DAG . getTarget ( ) . Options ; if ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( N -> getFlags ( ) . hasAllowContract ( ) && FMA -> getFlags ( ) . hasAllowContract ( ) ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; Op2 = Op2 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Idx1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Vec2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FMAOp1 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAOp2 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAAcc = FMA . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; FMAOp1 = FMAOp1 . getOperand ( <NUM_LIT> ) ; FMAOp2 = FMAOp2 . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec3 = FMAOp1 . getOperand ( <NUM_LIT> ) ; SDValue Vec4 = FMAOp2 . getOperand


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: ParseOperand ( StringRef Mnemonic ) { if ( isParsingIntelSyntax ( ) )


<s> void <ISA_LIT>ELFStreamer :: EmitHandlerData ( ) { FlushUnwindOpcodes ( false )


<s> static tree aarch64_get_attributes ( aarch64_simd_builtin_datum * d ) { tree attrs = NULL_TREE ; if ( ! aarch64_modifies_global_state_p ( d ) ) { if ( aarch64_reads_global_state_p ( d ) ) attrs = aarch64_add_attribute (


<s> if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; Register DestReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg


<s> if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ; return


<s> RemainingAdj /= <NUM_LIT> ; if ( RetOpcode == <STR_LIT> ) { SmallVector < StackSlotInfo , <NUM_LIT> > SpillList ; GetEHSpillList ( SpillList , MFI , XFI , MF . getSubtarget ( ) . getTargetLowering ( ) ) ; RestoreSpillList ( MBB , MBBI , dl , TII , RemainingAdj , SpillList ) ; unsigned EhStackReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned EhHandlerReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( EhStackReg ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( EhHandlerReg ) ; MBB . erase ( MBBI ) ; return ; } bool restoreLR = XFI -> hasLRSpillSlot ( ) ; bool UseRETSP = restoreLR && RemainingAdj && ( MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) == <NUM_LIT> ) ; if ( UseRETSP ) restoreLR = false ; bool FP = hasFP ( MF ) ; if ( FP ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FramePtr ) ; SmallVector < StackSlotInfo , <NUM_LIT> > SpillList ; GetSpillList ( SpillList , MFI , XFI , restoreLR , FP ) ; RestoreSpillList ( MBB , MBBI , dl , TII , RemainingAdj , SpillList ) ; if ( RemainingAdj ) { IfNeededLDAWSP ( MBB , MBBI , dl , TII , <NUM_LIT> , RemainingAdj ) ; if ( UseRETSP ) { assert ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; int Opcode = isImmU6 ( RemainingAdj ) ? <STR_LIT>


<s> const Value * AndRHS = AI -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( AndLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( AndLHS , AndRHS ) ; if ( const auto * C = dyn_cast < ConstantInt > ( AndRHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) { TestBit = C -> getValue ( ) . logBase2 ( ) ; LHS = AndLHS ; } } if ( VT == <STR_LIT> ) TestBit = <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_NE ; break ; case CmpInst :: ICMP_SLT : case CmpInst :: ICMP_SGE : if ( ! isa < Constant > ( RHS ) || ! cast < Constant > ( RHS ) -> isNullValue ( ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLT ; break ; case CmpInst :: ICMP_SGT : case CmpInst :: ICMP_SLE : if ( ! isa < ConstantInt > ( RHS ) ) return false ; if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != APInt ( BW , - <NUM_LIT> , true ) ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = Predicate == CmpInst :: ICMP_SLE ; break ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool IsBitTest = TestBit != - <NUM_LIT> ; bool Is64Bit = BW == <NUM_LIT> ; if ( TestBit < <NUM_LIT> && TestBit >= <NUM_LIT> ) Is64Bit = false ; unsigned Opc = OpcTable [ IsBitTest ] [ IsCmpNE ]


<s> if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; LoadSDNode * LN = cast < LoadSDNode > ( N ) ; if ( LN -> isVolatile ( ) || ! <STR_LIT> ( LN ) || hasVolatileUser ( LN ) ) return SDValue ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; unsigned Align = LN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT


<s> if ( SDValue Test = EmitAVX512Test ( Op0 , Op1 , CC , dl , DAG , Subtarget , <ISA_LIT>CC ) ) return Test ; if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; <ISA_LIT>CC = Op0 . getOperand ( <NUM_LIT> ) ; if ( Invert ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( isAllOnesConstant ( Op1 ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isProfitableToUseFlagOp ( Op0 ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op0 . getNode ( ) , <NUM_LIT> ) , New ) ; <STR_LIT> CCode = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint (


<s> void <ISA_LIT>ConstantIslands :: verify ( MachineFunction & MF ) { assert ( BBOffsets . size ( ) == BBSizes . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = BBOffsets . size ( ) ; i != e ; ++ i ) assert ( BBOffsets [ i - <NUM_LIT> ] + BBSizes [ i - <NUM_LIT> ] == BBOffsets [ i ] ) ; if ( ! isThumb ) return ; for ( MachineFunction :: iterator MBBI = MF . begin ( ) , E = MF . end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) && MBB -> begin


<s> } NumBytes = - SubTarget . getAdjustedFrameSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( <STR_LIT> , true


<s> do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return


<s> if ( Old -> getOpcode ( ) == <STR_LIT> ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT> ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT>

) . addReg ( <STR_LIT> ) . addImm ( Amount ) ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true ,


<s> if ( regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ( ) ) return true ; if ( cfun -> machine -> interrupt_handler_p && ! crtl -> is_leaf && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return false


<s> return llvm :: createAsmStreamer ( Ctx , S , OS , isVerboseAsm , useLoc , useCFI , useDwarfDirectory , InstPrint , CE , TAB


<s> rtx sc_reg = force_reg ( Pmode , static_chain ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , <STR_LIT> ) , FALSE , VOIDmode , <NUM_LIT> , addr , Pmode , GEN_INT ( frv_trampoline_size

( ) ) , SImode , fnaddr , Pmode , sc_reg , Pmode ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg

) . addReg ( SrcReg , KillSrc ? RegState :: Kill : <NUM_LIT> ) ;


<s> void setLinearizedRegion ( LinearizedRegion * LinearizeRegion


<s> MVT VT = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , NULL , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) ,


<s> bool isPositionIndependent ( ) const { return TM . getRelocationModel ( ) == Reloc ::


<s> else if ( isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; break ; case <STR_LIT> : { if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; else if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_COPYWIDEN ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_SPLAT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl


<s> static __inline vec_double2 spu_slqwbytebc ( vec_double2 a , unsigned int count ) { return ( ( vec_double2 ) ( si_shlqbybi ( ( qword ) ( a ) , si_from_uint


<s> return Res ; } case <STR_LIT> : case <STR_LIT> : { if ( ! mayIgnoreSignedZero ( N0 ) ) return SDValue ( ) ; SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue MHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) LHS = LHS . getOperand ( <NUM_LIT> ) ; else if ( MHS . getOpcode ( ) == <STR_LIT> ) MHS = MHS . getOperand ( <NUM_LIT> ) ; else MHS = DAG . getNode ( <STR_LIT> , SL , VT , MHS ) ; if ( RHS . getOpcode ( ) != <STR_LIT> ) RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; else RHS = RHS . getOperand ( <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Opc , SL , VT , LHS , MHS , RHS ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( isConstantCostlierToNegate ( RHS ) ) return SDValue ( ) ; SDValue NegLHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; unsigned Opposite = inverseMinMax ( Opc ) ; SDValue Res = DAG . getNode ( Opposite , SL , VT , NegLHS , NegRHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : { SDValue Ops [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) Ops [ I ] = DAG . getNode ( <STR_LIT> , SL , VT , N0 -> getOperand ( I ) , N0 -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , SL , VT , Ops , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return BUFFER_LOAD ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BUFFER_STORE ; } } if ( TII . isMIMG ( Opc ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: vaddr ) == - <NUM_LIT> ) return UNKNOWN ; if ( TII . get ( Opc ) . mayStore ( ) || ! TII . get ( Opc ) . mayLoad ( ) || TII . isGather4 ( Opc ) ) return UNKNOWN ; return MIMG ; } if ( TII . isMTBUF ( Opc ) ) { switch ( <STR_LIT> ( Opc ) ) { default : return UNKNOWN ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBUFFER_LOAD ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBUFFER_STORE ; } } return UNKNOWN ; case <STR_LIT> : case


<s> return StringSwitch < int > ( RegString . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT>

, <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> static bool hasVPRUse ( MachineInstr & MI ) { return MI . findRegisterUseOperandIdx ( <STR_LIT>


<s> else { operands [ <NUM_LIT> ] = regno_reg_rtx [ long_branch_regnum ] ; spilled = true ; gcc_assert ( current_function_has_lr_slot ( ) ) ; } if ( spilled ) { if ( final_sequence ) { rtx_insn * delay = NEXT_INSN ( insn ) ; gcc_assert ( delay ) ; final_scan_insn ( delay , asm_out_file , optimize , <NUM_LIT> , NULL ) ; PATTERN ( delay ) = gen_blockage ( ) ; INSN_CODE ( delay ) = - <NUM_LIT> ; } if ( current_function_saves_fp ( ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; } output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCapFloat32Store ( MachineInstr & MI , MachineBasicBlock *


<s> if ( to_as != ADDR_SPACE_FAR && from_as == ADDR_SPACE_FAR ) { if ( CONSTANT_P ( op ) ) return gen_rtx_CONST ( HImode , op ) ; result = gen_reg_rtx ( HImode ) ; emit_insn ( gen_truncpsihi2 ( result , op ) ) ; return result


<s> bool <ISA_LIT>FastISel :: optimizeIntExtLoad ( const Instruction * I , MVT RetVT , MVT SrcVT ) { const auto * LI = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! LI || ! LI -> hasOneUse ( ) ) return false ; unsigned Reg = lookUpRegForValue ( LI ) ; if ( ! Reg ) return false ; MachineInstr * MI = MRI . getUniqueVRegDef ( Reg ) ; if ( ! MI ) return false ; bool IsZExt = isa < ZExtInst > ( I ) ; const auto * LoadMI = MI ; if ( LoadMI -> getOpcode ( ) == TargetOpcode :: COPY && LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { unsigned LoadReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LoadMI = MRI . getUniqueVRegDef ( LoadReg ) ; assert ( LoadMI && <STR_LIT> ) ; } if ( ! ( IsZExt && isZExtLoad ( LoadMI ) ) && ! ( ! IsZExt && isSExtLoad ( LoadMI ) ) ) return false ; if ( RetVT != <STR_LIT> || SrcVT > <STR_LIT> ) { updateValueMap ( I , Reg ) ; return true ; } if ( IsZExt ) { unsigned Reg64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( Reg , getKillRegState ( true ) ) . addImm ( <STR_LIT> ) ; Reg =


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , FastDenormalF32 ( false ) , HalfRate64Ops ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , DoesNotSupportXNACK ( false ) , EnableCuMode ( false ) , TrapHandler ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX8Insts ( false ) , GFX9Insts ( false ) , GFX10Insts ( false ) , GFX7GFX8GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDPP8 ( false ) , HasR128A16 ( false ) , HasGFX10A16 ( false ) , HasNSAEncoding ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , HasDot3Insts ( false ) , HasDot4Insts ( false ) , HasDot5Insts ( false ) , HasDot6Insts ( false ) , HasMAIInsts ( false ) , HasPkFmacF16Inst ( false ) , HasAtomicFaddInsts ( false ) , EnableSRAMECC ( false ) , DoesNotSupportSRAMECC ( false ) , HasNoSdstCMPX ( false ) , HasVscnt ( false ) , HasRegisterBanking ( false ) , HasVOP3Literal ( false ) , HasNoDataDepHazard ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , ScalarFlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , LDSMisalignedBug ( false ) , HasMFMAInlineLiteralBug ( false ) , ScalarizeGlobal ( false ) , HasVcmpxPermlaneHazard ( false ) , HasVMEMtoScalarWriteHazard ( false ) , HasSMEMtoVectorWriteHazard ( false ) , HasInstFwdPrefetchBug ( false ) , HasVcmpxExecWARHazard ( false ) , HasLdsBranchVmemWARHazard ( false ) , HasNSAtoVMEMBug ( false ) , HasOffset3fBug ( false ) , HasFlatSegmentOffsetBug ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { MaxWavesPerEU = <STR_LIT> :: getMaxWavesPerEU ( this


<s> static SDValue performADDCombine ( SDNode * N ,


<s> bool isSVEVectorList ( ) const { if ( Kind != k_VectorList


<s> static bool isHardwareLoopOne ( const MachineInstr & MI ) { return MI . getOpcode ( ) == <STR_LIT> || MI .


<s> unsigned int getSmVersion ( ) const { return SmVersion


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; return SDValue (


<s> const GlobalValue * Value = GA -> getGlobal ( ) ; const Type * Ty = Value -> getValueType ( ) ; if ( Ty -> isArrayTy ( ) && <STR_LIT> ( Ty -> getArrayElementType ( )


<s> static bool isSUBSRegImm ( unsigned Opcode )


<s> } if ( code == GTU ) { cop0 = force_reg ( mode , cop0 ) ; switch ( mode ) { case V16SImode : case V8DImode : case V8SImode : case V4DImode : case V4SImode : case V2DImode : { rtx t1 , t2 , mask ; rtx ( * gen_sub3 ) ( rtx , rtx , rtx ) ; switch ( mode ) { case V16SImode : gen_sub3 = gen_subv16si3 ; break ; case V8DImode : gen_sub3 = gen_subv8di3 ; break ; case V8SImode : gen_sub3 = gen_subv8si3 ; break ; case V4DImode : gen_sub3 = gen_subv4di3 ; break ; case V4SImode : gen_sub3 = gen_subv4si3 ; break ; case V2DImode : gen_sub3 = gen_subv2di3 ; break ; default : gcc_unreachable ( ) ; } mask = ix86_build_signbit_mask ( mode , true , false ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_sub3 ( t1 , cop0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_sub3 ( t2 , cop1 , mask ) ) ; cop0 = t1 ; cop1 = t2 ; code = GT ; } break ; case V64QImode : case V32HImode : case V32QImode : case V16HImode : case V16QImode : case V8HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_US_MINUS ( mode , cop0 , cop1 ) ) ) ; cop0 = x ; cop1 = CONST0_RTX ( mode ) ; code = EQ ; * negate = ! *


<s> ++ MO ; } MIB . addReg ( PredR ) ; for ( ; MO . isValid ( ) ; ++ MO ) MIB . addOperand ( * MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCInstrDesc & D = HII -> get ( IfTrue ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( * ToB , At , DL , D ) . addReg ( PredR ) . addMBB ( TB ) ; MI -> eraseFromParent (