<s> if ( insn == NULL_RTX ) return false ; return get_attr_z13_unit_fpd ( insn ) || get_attr_z14_unit_fpd ( insn ) ||


<s> return sparc_function_arg_1 ( cum , arg


<s> void printROROperand ( const MCInst * MI ,


<s> PostGenericScheduler :: initialize ( Dag )


<s> if ( ! INSN_P ( insn ) ) continue ; if ( code == JUMP_INSN ) return <NUM_LIT> ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; int retval = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return <NUM_LIT> ; code = JUMP_INSN ; } if ( set && reg_overlap_mentioned_p ( reg , SET_SRC ( set ) ) ) return <NUM_LIT> ; if ( set && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) { if ( ! MEM_P ( SET_DEST ( set ) ) ) retval = <NUM_LIT> ; else return <NUM_LIT> ; } if ( set == <NUM_LIT> && reg_overlap_mentioned_p ( reg , PATTERN ( this_insn ) ) ) return <NUM_LIT> ; } if ( retval == <NUM_LIT> ) return <NUM_LIT> ; else if ( code == JUMP_INSN ) return


<s> bool isAtomicRet ( const MachineInstr & MI ) const { return <STR_LIT> ( MI . getOpcode ( )


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( auto * CN = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) ,


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - StackSize + RVFI -> getVarArgsSaveSize ( )


<s> const unsigned * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ]


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( PtrTy , MFI -> getStackPtrOffsetReg ( ) ) . getReg ( <NUM_LIT> ) ; auto OffsetReg = MIRBuilder . buildConstant ( S32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( PtrTy , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg . getReg (


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter


<s> uint64_t Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT> ) { Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; Amount -= TII . getFramePoppedByCallee ( Old ) ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = TII . getFramePoppedByCallee ( * I ) ) { MachineInstr & Old


<s> if ( I != BB . begin ( ) ) PrevMI = prior ( I ) ; ++ NumFP ; DEBUG ( errs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { cerr << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I


<s> int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT (


<s> return emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , DAG . getIntPtrConstant (


<s> void addImm0_7Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm


<s> SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Imm = Node -> getOperand ( <NUM_LIT> ) ; const ConstantInt * Val = cast < ConstantSDNode > ( Imm ) -> getConstantIntValue ( ) ; Imm = CurDAG -> getTargetConstant ( * Val , SDLoc ( Node ) , Imm . getValueType ( ) ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( MayFoldLoad && N1 -> getOpcode ( ) == <STR_LIT> && N1 -> hasOneUse ( ) && tryFoldVecLoad ( Node , N1 . getNode ( ) , N1 . getOperand ( <NUM_LIT> ) , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Load = N1 . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , Load . getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ; ReplaceUses ( Load . getValue ( <NUM_LIT> ) , SDValue ( CNode , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < LoadSDNode > ( Load ) -> getMemOperand ( ) ; CNode -> setMemRefs ( MemOp ,


<s> bool Tile64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext


<s> VectorType * VecTy = SVI -> getType ( ) ; assert ( VecTy -> getVectorNumElements ( ) % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubElts = VecTy -> getVectorNumElements ( ) / Factor ; Type * EltTy = VecTy -> getVectorElementType ( ) ; VectorType * SubVecTy = VectorType :: get ( EltTy , NumSubElts ) ; const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeAllocSizeInBits ( SubVecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI ->


<s> Br . MaxDisp = ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; ++ NumUBrFixed ; LLVM_DEBUG ( dbgs ( ) <<


<s> for ( auto & Reg : functionCallArgs ) { MachineBasicBlock * lastCheck = NULL ; newBB = insertVoting ( MF , MI , Reg , lastCheck


<s> MachineBasicBlock & BB = * I . getParent ( ) ; if ( Val == <NUM_LIT> ) { MI = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( NewReg ) . addUse ( GR . get<ISA_LIT>TypeID ( SpvI32Ty ) ) ; } else { MI = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( NewReg )

. addUse ( GR . get<ISA_LIT>TypeID ( SpvI32Ty ) ) . addImm ( APInt ( <NUM_LIT> , Val ) . getZExtValue ( ) ) ;


<s> SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; unsigned ZMask = <NUM_LIT> ; int V1DstIndex = - <NUM_LIT> ; int V2DstIndex = - <NUM_LIT> ; bool V1UsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == Mask [ i ] ) { V1UsedInPlace = true ; continue ; } if ( V1DstIndex != - <NUM_LIT> || V2DstIndex != - <NUM_LIT> ) return SDValue ( ) ; if ( Mask [ i ] < <NUM_LIT> ) { V1DstIndex = i ; } else { V2DstIndex = i ; } } if ( V1DstIndex == - <NUM_LIT> && V2DstIndex == - <NUM_LIT> ) return SDValue ( ) ; unsigned V2SrcIndex = <NUM_LIT> ; if ( V1DstIndex != - <NUM_LIT> ) { V2SrcIndex = Mask [ V1DstIndex ] ; V2DstIndex = V1DstIndex ; V2 = V1 ; } else { V2SrcIndex = Mask [ V2DstIndex ] - <NUM_LIT> ; } if ( ! V1UsedInPlace ) V1 = DAG . getUNDEF ( <STR_LIT> ) ; unsigned InsertPSMask = V2SrcIndex << <NUM_LIT> | V2DstIndex << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT>


<s> return std :: make_unique < <ISA_LIT>WinCOFFObjectWriter


<s> if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } Base =


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { if ( isa < LoadInst > ( Inst ) && Ord ==

AtomicOrdering :: SequentiallyConsistent ) return Builder . CreateFence ( Ord ) ;


<s> EVT PtrTy = getPointerTy ( ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; MVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = CC . intArgRegs ( ) [ ByVal . FirstIdx + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * CC . regSize ( ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , FIN , DAG . getConstant ( Offset


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override { return &


<s> if ( ! DCI . isBeforeLegalizeOps ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Setcc = DAG . getNode ( <STR_LIT> , DL , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N -> getOpcode ( ) , DL , VT , N0 , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ; if ( N0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( N0 . getOpcode ( ) , DL , VT , N0 . getOperand


<s> if ( ST -> isSwift ( ) && Opcode == Instruction :: InsertElement && ValTy -> isVectorTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( ( Opcode == Instruction :: InsertElement || Opcode == Instruction :: ExtractElement ) ) { if ( ValTy -> getVectorElementType ( ) -> isIntegerTy ( )


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler


<s> SDValue DemandedRHS = DAG . GetDemandedBits ( RHS , DemandedMask ) ; if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ? DemandedRHS : RHS ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue ( <NUM_LIT> ) , DCI ) ) return SDValue (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> bool MatchUnpack = true ; SmallVector < int , <STR_LIT> > SrcBytes ; for ( unsigned Elt = <NUM_LIT> ; Elt < <STR_LIT> ; Elt ++ ) { unsigned ToEltSize = UnpackFromEltSize * <NUM_LIT> ; bool IsZextByte = ( Elt % ToEltSize ) < UnpackFromEltSize ; if ( ! IsZextByte ) SrcBytes . push_back ( Bytes [ Elt ] ) ; if ( Bytes [ Elt ] != - <NUM_LIT> ) { unsigned OpNo = unsigned ( Bytes [ Elt ] ) / <STR_LIT> ; if ( IsZextByte != ( OpNo == ZeroVecOpNo ) ) { MatchUnpack = false ; break ; } } } if ( MatchUnpack ) { if ( Ops . size ( ) == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> / <NUM_LIT> ; i ++ ) if ( SrcBytes [ i ] != - <NUM_LIT> && SrcBytes [ i ] % <NUM_LIT> != int ( i ) ) { UnpackFromEltSize = UINT_MAX


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ECX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EBP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: ESI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return N86 :: EDI ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RegNo - <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDValue P , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { if ( <STR_LIT> ( N . getNode ( ) ) && N . hasOneUse ( ) && IsLegalAndProfitableToFold ( N . getNode ( ) , P . getNode ( ) , P . getNode ( ) ) ) return SelectAddr

( P , N . getOperand ( <NUM_LIT> ) , Base , Scale , Index , Disp , Segment ) ;


<s> dbgs ( ) << <STR_LIT> ; Header -> dump ( ) ; dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; bool Changed = false ; ReductionList Reductions = MatchReductions ( F , L , Header ) ; for ( auto & R : Reductions ) { ParallelMACList MACCandidates = MatchParallelMACs ( R ) ; if ( ! SetMemoryLocations ( MACCandidates ) ) continue ; Instructions Aliases = AliasCandidates ( Header , MACCandidates ) ; if ( AreAliased ( AA , Aliases


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI , MODE_32BIT ,


<s> if ( N . getOpcode ( ) != <STR_LIT> ) { if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> ) { RHSC /= Scale ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getRegister (


<s> vpadalq_u16 ( uint32x4_t a , uint16x8_t b ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result


<s> mips_prepare_builtin_arg ( & ops [ <NUM_LIT> ] , exp , <NUM_LIT> ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , const0_rtx ) ; if ( GET_CODE ( ops [ <NUM_LIT> ] . value ) != REG ) ops [ <NUM_LIT> ] . value = force_reg ( ops [ <NUM_LIT> ] . mode , ops [ <NUM_LIT> ] . value ) ; if ( ( cbranch = maybe_gen_insn ( icode , <NUM_LIT> , ops ) ) == NULL_RTX ) error ( <STR_LIT> ) ; cmp_result = gen_reg_rtx ( SImode ) ; mips_emit_move ( cmp_result , const0_rtx ) ; emit_jump_insn ( cbranch ) ; emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( true_label )


<s> case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Op = <STR_LIT> ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Op = <STR_LIT> ; bool writeback = ( P == <NUM_LIT> ) || ( W == <NUM_LIT> ) ; unsigned idx_mode = <NUM_LIT> ; if ( P && writeback ) idx_mode = <STR_LIT> ; else if ( ! P && writeback ) idx_mode = <STR_LIT> ; if ( writeback && ( Rn == <NUM_LIT> || Rn == Rt ) ) S = MCDisassembler :: SoftFail ; if ( reg ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Opc = <STR_LIT> ; switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc =


<s> HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE1 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( Aligned ) Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT>


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( STI . hasV4TOps ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && ! DisableDeallocRet ) { MBB . erase ( MBBI ) ; BuildMI ( MBB , MBBI_end , dl , TII . get ( <STR_LIT> ) ) . addImm ( NumBytes ) ; }


<s> to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx new_reg = <NUM_LIT> ; rtx and_mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < and_insns . length ( ) ; i ++ ) { rtx_insn * and_insn = and_insns [ i ] ; rtx and_op = and_ops [ i ] ; rtx and_base = XEXP ( and_op , <NUM_LIT> ) ; if ( ! new_reg ) { new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; and_mask = XEXP ( and_op , <NUM_LIT> ) ; } rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn ) ) ; df_insn_rescan ( new_insn ) ; } XEXP ( mem , <NUM_LIT> ) = gen_rtx_AND ( GET_MODE ( new_reg ) , new_reg , and_mask ) ; SET_SRC ( body ) = mem ; INSN_CODE ( insn )


<s> rtx reg ; if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ; reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; return reg


<s> getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage (


<s> static void bpf_asm_named_section ( const char * name , unsigned int flags ATTRIBUTE_UNUSED ,


<s> static __inline qword si_from_uchar ( unsigned char c ) { union { qword q ; unsigned char c [ <NUM_LIT> ]


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return nullptr


<s> unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case


<s> if ( ( Ty . isScalar ( ) && ! isFP ) || Ty . isPointer ( ) ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : return PMI_GPR8 ; case <NUM_LIT> : return PMI_GPR16 ; case <NUM_LIT> : return PMI_GPR32 ; case <NUM_LIT> : return PMI_GPR64 ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Ty . isScalar ( ) ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : return PMI_FP32 ; case <NUM_LIT> : return PMI_FP64 ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( Ty .


<s> MachineFunctionPass ( ID ) , TRI ( nullptr ) , TII ( nullptr


<s> gcc_assert ( BYTES_BIG_ENDIAN ) ; if ( GET_CODE ( dest ) == SUBREG ) dest = SUBREG_REG ( dest ) ; if ( GET_CODE ( src ) == SUBREG ) src = SUBREG_REG ( src ) ; if ( ! REG_P ( dest ) || ! REG_P ( src ) || aarch64_classify_vector_mode ( GET_MODE ( dest ) ) != VEC_SVE_DATA || aarch64_classify_vector_mode ( GET_MODE ( src ) ) != VEC_SVE_DATA || ( GET_MODE_UNIT_SIZE ( GET_MODE ( dest ) ) == GET_MODE_UNIT_SIZE ( GET_MODE ( src ) ) ) ) return false ; rtx ptrue = force_reg ( VNx16BImode , CONSTM1_RTX ( VNx16BImode ) ) ; rtx unspec = gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( <NUM_LIT> , ptrue , src ) , UNSPEC_REV_SUBREG ) ; emit_insn ( gen_rtx_SET ( dest ,


<s> FunctionPass * llvm :: create<ISA_LIT>IndirectThunksPass ( )


<s> if ( <STR_LIT> . contains ( DstReg ) && Base . isReg ( ) && <STR_LIT> . contains ( Base . getReg ( ) ) && Off . isImm ( ) && <STR_LIT> ( Off . getImm ( ) ) ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode =


<s> auto * Symbol = cast < MCSymbolELF > ( getContext ( ) . getOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ) ; EmitLabel ( Symbol , Loc , F ) ; Symbol -> setType ( ELF :: STT_NOTYPE ) ; Symbol -> setBinding ( ELF :: STB_LOCAL ) ; Symbol -> setExternal ( false ) ; Symbol -> setOffset ( Offset


<s> if ( ! MI . mayLoadOrStore ( ) ) return false ; unsigned XFormOpcode = RI . getMappedIdxOpcForImmOpc ( MI . getOpcode ( ) ) ; assert ( ( XFormOpcode != <STR_LIT> ) && <STR_LIT> ) ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! instrHasImmForm ( XFormOpcode , IsVFReg , III , PostRA ) ) return false ; if ( ! III . IsSummingOperands ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; MachineOperand ImmOperandMI = MI . getOperand ( III . ImmOpNo ) ; if ( ! ImmOperandMI . isImm ( ) ) return false ; MachineOperand * ImmMO = nullptr ; MachineOperand * RegMO = nullptr ; if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI . getImm ( ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm , ImmBase ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( MI . getOperand ( III . OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( III . OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . setReg ( RegMO -> getReg ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . setIsKill ( RegMO -> isKill ( ) ) ; MI . getOperand ( III . ImmOpNo )


<s> GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , Cast -> getOperand ( <NUM_LIT> ) , Indices , <STR_LIT> , GEPI ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; NewGEP -> takeName ( GEP ) ; NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , <STR_LIT> , GEPI ) ; GEP -> replaceAllUsesWith ( NewASC ) ; } else { Constant * NewGEP = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast ->

getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ;


<s> int reverse = <NUM_LIT> ; int seeking_return = <NUM_LIT> ; rtx_insn * start_insn = insn ; enum attr_type jump_insn_type ; if ( optimize < <NUM_LIT> || TARGET_NO_COND_EXEC ) return ; if ( ! INSN_P ( insn ) ) return ; body = PATTERN ( insn ) ; if ( state -> state == <NUM_LIT> ) { if ( insn == state -> target_insn ) { state -> target_insn = NULL ; state -> state = <NUM_LIT> ; } return ; } if ( state -> state == <NUM_LIT> ) { if ( simplejump_p ( insn ) ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) { start_insn = next_nonnote_insn ( start_insn ) ; } if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == state -> target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) reverse = TRUE ; else return ; } else if ( GET_CODE ( body ) == SIMPLE_RETURN ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == state -> target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) { reverse = TRUE ; seeking_return = <NUM_LIT> ; } else return ; } else return ; } if ( GET_CODE ( insn ) != JUMP_INSN || GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC ) return ; jump_insn_type = get_attr_type ( insn ) ; if ( jump_insn_type == TYPE_BRCC || jump_insn_type == TYPE_BRCC_NO_DELAY_SLOT || jump_insn_type == TYPE_LOOP_END || ( jump_insn_type == TYPE_CALL && ! get_attr_predicable ( insn ) ) ) return ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , <NUM_LIT> ) > <NUM_LIT> ) body = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( reverse || ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == PC && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) ) { int insns_skipped = <NUM_LIT> , fail = FALSE , succeed = FALSE ; int then_not_else = TRUE ; int next_must_be_target_label_p ; rtx_insn * this_insn = start_insn ; rtx label = <NUM_LIT>


<s> if ( count <= <NUM_LIT> ) { error ( <STR_LIT> , count ) ; return NULL ; } gcc_assert ( GET_CODE ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) ) == PLUS ) ; gcc_assert ( GET_CODE ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) == REG ) ; gcc_assert ( GET_CODE ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) == CONST_INT ) ; stack_bytes = INTVAL ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) ; stack_bytes += ( count - ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) ) * <NUM_LIT> ; if ( stack_bytes != <NUM_LIT> && stack_bytes != - <NUM_LIT> ) { error ( <STR_LIT> , stack_bytes ) ; return NULL ; } mask = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < count - ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) ; i ++ ) { rtx vector_element = XVECEXP ( op , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( vector_element ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( vector_element ) ) == REG ) ; gcc_assert ( register_is_ok_for_epilogue ( SET_SRC ( vector_element ) , SImode ) ) ; mask |= <NUM_LIT> << REGNO ( SET_SRC ( vector_element ) ) ; } for ( first = <NUM_LIT> ; first < <NUM_LIT> ; first ++ ) { if ( mask & ( <NUM_LIT> << first ) ) break ; } gcc_assert ( first < <NUM_LIT> ) ; if ( mask & ( <NUM_LIT> << LINK_POINTER_REGNUM ) ) { gcc_assert ( stack_bytes == - <NUM_LIT> ) ; last = LINK_POINTER_REGNUM ; } else { gcc_assert ( ! stack_bytes ) ; gcc_assert ( mask & ( <NUM_LIT> << <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , TRI , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIndex ) . addReg ( SrcReg ,


<s> switch ( Callee -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case


<s> UnsignedMap RegMap ; for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { unsigned VR = I -> first ; const TargetRegisterClass * RC = MRI -> getRegClass ( VR ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; RegMap [ VR ] = NewVR ; } for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = MRI -> getVRegDef ( I -> first ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = RegMap [ I -> first ] ; bool R32 = MRI -> getRegClass ( NewR ) == & <STR_LIT> ; const MCInstrDesc & D = R32 ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; IFRecord IF = I -> second [ <NUM_LIT> ] . first ; unsigned Wdh = IF . Wdh , Off = IF . Off ; unsigned InsS = <NUM_LIT> ; if ( R32 && MRI -> getRegClass ( IF . InsR ) == & <STR_LIT> ) { InsS = <STR_LIT> ; if ( Off >= <NUM_LIT> ) { InsS = <STR_LIT> ; Off -= <NUM_LIT> ; } } MachineBasicBlock :: iterator At = MI ; if ( MI -> isPHI ( ) ) At = B . getFirstNonPHI ( ) ; BuildMI ( B , At , DL , D , NewR ) . addReg ( IF . SrcR ) . addReg ( IF . InsR , <NUM_LIT> , InsS ) . addImm ( Wdh ) . addImm ( Off ) ; MRI -> clearKillFlags ( IF . SrcR ) ; MRI -> clearKillFlags ( IF . InsR ) ; } for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2AddrModeImm7 ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> << Shift , - <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift


<s> if ( Insert . second ) { PreallocatedStackSizes . push_back ( <NUM_LIT> ) ; PreallocatedArgOffsets . emplace_back ( ) ; } return Insert . first ->


<s> obstack_1grow ( & m_string_obstack , <NUM_LIT> ) ; return ( char * ) obstack_finish ( & m_string_obstack


<s> SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , Base , Scale , Index , Disp , Segment , Mask , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) ,


<s> break ; case <STR_LIT> : case <STR_LIT> : { if ( ! MinimizeSize ) return false ; if ( ! MI -> hasOneMemOperand ( ) || ( * MI -> memoperands_begin ( ) ) -> getAlign ( ) < Align ( <NUM_LIT> ) ) return false ; bool IsStore = Entry . WideOpc == <STR_LIT> ; Register Rt = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; Register Rn = MI -> getOperand ( IsStore ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; unsigned Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned PredImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Register PredReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( Rt ) ) ; assert ( is<ISA_LIT>LowRegister ( Rn ) ) ; if ( Offset != <NUM_LIT> ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; auto MIB = BuildMI ( MBB , MI , dl , TII -> get ( Entry . NarrowOpc1 ) ) . addReg ( Rn , RegState :: Define ) . addReg ( Rn ) . addImm ( PredImm ) . addReg ( PredReg ) . addReg ( Rt , IsStore ? <NUM_LIT> : RegState :: Define ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; MI -> eraseFromBundle ( ) ; ++ NumLdSts ; return true ; } case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isOK = false ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) { if ( MO . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) , <NUM_LIT> ) ) if ( MO . getReg ( ) == BaseReg ) return false ; break ; } case <STR_LIT> : { Register BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT>


<s> bool HasAlloca = MFI . hasVarSizedObjects ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool NoOpt = MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; Register SP = HRI . getStackRegister ( ) ; Register FP = HRI . getFrameRegister ( ) ; Register AP = HMFI . getStackAlignBasePhysReg ( ) ; if ( AP == <NUM_LIT> ) AP = FP ; bool UseFP = false , UseAP =


<s> void addMemoryIndexed128Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && isMemoryIndexed128 ( ) && <STR_LIT> ) ; addMemoryIndexedOperands ( Inst , N , <NUM_LIT> )


<s> bool hasExceptionHandling ( ) const { return HasExceptionHandling


<s> unsigned Size = <NUM_LIT> << getFixupKindLog2Size ( Fixup . Kind ) ; assert ( Fixup . Offset + Size <= DF . getContents ( ) . size ( ) &&


<s> if ( len == <NUM_LIT> ) { error ( <STR_LIT> , str ) ; return ; } for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , str , len ) == <NUM_LIT> ) { selected_cpu = cpu ; aarch64_isa_flags = selected_cpu -> flags ; if ( ext != NULL ) { aarch64_parse_extension ( ext


<s> set_optab_libfunc ( ne_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( ge_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( lt_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( le_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( unord_optab , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , <STR_LIT> ) ; set_conv_libfunc ( sfloat_optab , TFmode ,


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> && Sc . getOpcode ( ) != <STR_LIT> ) { if ( ! Subtarget -> hasInt256 ( ) ) return SDValue ( ) ; if ( VT . is256BitVector ( ) ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; bool hasRegVer = Subtarget -> hasAVX512 ( ) && VT . is512BitVector ( ) && Ld . getValueType ( ) . getSizeInBits ( ) >= <NUM_LIT> ; if ( ! ConstSplatVal && ( ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) && ! hasRegVer ) ) return SDValue ( ) ; break ; } } bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( ConstSplatVal && Subtarget -> hasInt256 ( ) ) { EVT CVT = Ld . getValueType (


<s> return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end (


<s> const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned Size = DL . getTypeStoreSize ( AI -> getCompareOperand ( ) -> getType (


<s> static const AluKind IndexToID [ ] = { AluT_X , AluT_Y , AluT_Z , AluT_W } ; SUnit * SlotedSU = PopInst ( AvailableAlus [ IndexToID [ Slot ] ] , AnyAlu ) ; if ( SlotedSU ) return SlotedSU ; SUnit * UnslotedSU = PopInst ( AvailableAlus [ AluAny


<s> EVT VT = St -> getValue ( ) . getValueType ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool NoImplicitFloatOps = F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ; bool F64IsLegal = ! UseSoftFloat && ! NoImplicitFloatOps && Subtarget -> hasSSE2 ( ) ; if ( ( VT . isVector ( ) || ( VT == <STR_LIT> && F64IsLegal && ! Subtarget -> is64Bit ( ) ) ) && isa < LoadSDNode > ( St -> getValue ( ) ) && ! cast < LoadSDNode > ( St -> getValue ( ) ) -> isVolatile ( ) && St -> getChain ( ) . hasOneUse ( ) && ! St -> isVolatile ( ) ) { SDNode * LdVal = St -> getValue ( ) . getNode ( ) ; LoadSDNode * Ld = <NUM_LIT> ; int TokenFactorIndex = - <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops ; SDNode * ChainVal = St -> getChain ( ) . getNode ( ) ; if ( ChainVal == LdVal ) Ld = cast < LoadSDNode > ( St -> getChain ( ) ) ; else if ( St -> getValue ( ) . hasOneUse ( ) && ChainVal -> getOpcode ( ) == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = ChainVal -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ChainVal -> getOperand ( i ) . getNode ( ) == LdVal ) { TokenFactorIndex = i ; Ld = cast < LoadSDNode > ( St -> getValue ( ) ) ; } else Ops . push_back ( ChainVal -> getOperand ( i ) ) ; } } if ( ! Ld || ! <STR_LIT> ( Ld ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) && ! Ld -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; DebugLoc LdDL = Ld -> getDebugLoc ( ) ; DebugLoc StDL = N -> getDebugLoc ( ) ; if ( Subtarget -> is64Bit ( ) || F64IsLegal


<s> if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Subtarget -> is64Bit ( ) ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Has64BitPointers ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned SPReg = <ISA_LIT>StackPtr ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT> ) ; if ( Align ) { SP = DAG . getNode ( <STR_LIT> , dl , VT , SP . getValue ( <NUM_LIT> ) , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , SP ) ; } SDValue Ops1 [ <NUM_LIT> ] = { SP


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase &


<s> AU . addRequired < MachineModuleInfoWrapperPass >


<s> if ( ! compressEnabled ) { return ; } if ( ! Buffer . empty ( ) ) { flushBuffer ( Out , STI , true ) ; } if ( pInst != nullptr ) { Out . EmitInstruction ( prevInst , STI ) ; pInst = nullptr


<s> unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false


<s> auto It = Buffer . begin ( ) ; for ( ; It != Buffer . end ( ) ; ++ It ) { if ( any_isa < MCInst > ( * It ) ) { auto & Inst = any_cast < MCInst & > ( * It ) ; StringRef Looplabel ; if ( ! isLoopMCInst ( Inst , Looplabel ) ) { if ( ! DoNotCompressNextInst && maybeCompressInstr ( Inst , false ) ) flushInstCompressed ( Inst , Out , STI ) ; else { flushInstUncompressed ( Inst , Out , STI ) ; DoNotCompressNextInst = false ; } } else { flushLoopsInsts ( It , Out , STI ) ; } } else { MCSymbol * Label = any_cast < MCSymbol


<s> bool <ISA_LIT>DAGToDAGISel :: isConstantLoad ( const MemSDNode * N , int CbId ) const { if ( ! N -> readMem ( ) ) return


<s> <ISA_LIT>PALMetadata * getPALMetadata ( ) { return & PALMetadata


<s> switch ( Expr -> getKind ( ) ) { case MCExpr :: Binary : O << '#' << * Expr ; break ; case MCExpr :: Constant : { const MCConstantExpr * Constant = cast < MCConstantExpr > ( Expr ) ; int64_t TargetAddress ; if ( ! Constant -> EvaluateAsAbsolute ( TargetAddress ) ) { O << '#' << * Expr ; } else { O << <STR_LIT> ; O . write_hex ( static_cast < uint32_t > ( TargetAddress )


<s> if ( Stage == ClusteredLowOccupancyReschedule ) { if ( StartingOccupancy <= MinOccupancy ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MinOccupancy << <STR_LIT> ) ; } if ( Stage == PreRARematerialize ) { if ( RegionsWithMinOcc . none ( ) || Regions . size ( ) == <NUM_LIT> ) break ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( ST . computeOccupancy ( MF . getFunction ( ) , MFI . getLDSSize ( ) ) == MinOccupancy ) break ; static_assert ( LastStage == PreRARematerialize , <STR_LIT> ) ; collectRematerializableInstructions ( ) ; if ( RematerializableInsts . empty ( ) || ! sinkTriviallyRematInsts ( ST , TII ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MinOccupancy << <STR_LIT> ) ; } } if ( Stage == UnclusteredReschedule ) SavedMutations . swap ( Mutations ) ; for ( auto Region : Regions ) { if ( ( ( Stage == UnclusteredReschedule || Stage == PreRARematerialize ) && ! RescheduleRegions [ RegionIdx ] ) || ( Stage == ClusteredLowOccupancyReschedule && ! RegionsWithClusters [ RegionIdx ] && ! RegionsWithHighRP [ RegionIdx ] ) ) { ++ RegionIdx ; continue ; } RegionBegin = Region . first ; RegionEnd = Region . second ; if ( RegionBegin -> getParent ( ) != MBB ) { if ( MBB ) finishBlock ( ) ; MBB = RegionBegin -> getParent ( ) ; startBlock ( MBB ) ; if ( Stage == InitialSchedule ) computeBlockPressure ( MBB ) ; } unsigned NumRegionInstrs = std :: distance ( begin ( ) , end ( ) ) ; enterRegion ( MBB , begin ( ) , end ( ) , NumRegionInstrs ) ; if ( begin ( ) == end ( ) || begin ( ) == std :: prev ( end ( ) ) ) { exitRegion ( ) ; ++ RegionIdx ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << MF . getName ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> << * begin ( ) << <STR_LIT> ; if ( RegionEnd != MBB -> end ( ) ) dbgs ( ) << * RegionEnd ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << NumRegionInstrs << '\n' ) ; schedule ( ) ; exitRegion ( ) ; ++ RegionIdx ; } finishBlock ( ) ; if ( Stage == UnclusteredReschedule ) SavedMutations . swap


<s> void emit_pic_move ( rtx * operands , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx temp = reload_in_progress ? operands [ <NUM_LIT> ] : gen_reg_rtx ( Pmode


<s> bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( SkipPred && MCID . OpInfo [ i ] . isPredicate ( ) ) continue ; MIB . add ( MI -> getOperand ( i ) ) ; } MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ Num2Addrs


<s> if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > (


<s> Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; Op -> Mem . Length = Length ; return Op


<s> if ( flag_pic ) { fprintf ( file , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , MCOUNT_NAME ) ; } else { fprintf ( file , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , MCOUNT_NAME ) ; } if ( cfun


<s> if ( visium_flags_exposed && gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) && gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; return true


<s> return D ( <STR_LIT> , a , <STR_LIT>


<s> op0 = alpha_emit_xfloating_compare ( & code , op0 , op1 ) ; op1 = const0_rtx ; cmp_mode = DImode ; } if ( cmp_mode == DFmode && ! TARGET_FIX ) return <NUM_LIT> ; cmp_code = UNKNOWN ; switch ( code ) { case EQ : case LE : case LT : case LEU : case LTU : case UNORDERED : if ( cmp_mode == DFmode ) cmp_code = code , code = NE ; break ; case NE : if ( cmp_mode == DImode && op1 == const0_rtx ) break ; case ORDERED : cmp_code = reverse_condition ( code ) ; code = EQ ; break ; case GE : case GT : case GEU : case GTU : if ( cmp_mode == DImode && op1 == const0_rtx ) break ; code = swap_condition ( code ) ; if ( cmp_mode == DFmode ) cmp_code = code , code = NE ; std :: swap ( op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } if ( cmp_mode == DImode ) { if ( ! register_operand ( op0 , DImode ) ) op0 = force_reg ( DImode , op0 ) ; if ( ! reg_or_8bit_operand ( op1 , DImode ) ) op1 = force_reg ( DImode , op1 ) ; } if ( cmp_code != UNKNOWN ) { tmp = gen_reg_rtx ( cmp_mode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_fmt_ee ( cmp_code , cmp_mode , op0 , op1 ) ) ) ; op0 = cmp_mode != DImode ? gen_lowpart ( DImode , tmp ) : tmp ; op1 =


<s> bool hasBranchFusion ( ) const { return HasBranchFusion


<s> auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; bool Success = true ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . getCCAssignFn ( F . getCallingConv ( ) , true , F . isVarArg ( ) ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , <NUM_LIT> } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex


<s> Symbol = Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: CreateExpr ( MCSym ) ; assert ( Offset > <NUM_LIT> ) ; const MCConstantExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , * Ctx ) ; const MCBinaryExpr * AddExpr = MCBinaryExpr :: CreateAdd


<s> if ( SubIdx == <STR_LIT> ) return RC ; unsigned Count = countPopulation ( getSubRegIndexLaneMask ( SubIdx ) ) ; if ( isSGPRClass ( RC ) ) { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . getCCAssignFn ( F . getCallingConv ( ) , true , F . isVarArg ( ) ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , <NUM_LIT> } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; <ISA_LIT>OutgoingArgHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; Success = determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } MIRBuilder . insertInstr ( MIB


<s> return ( __m128i ) __builtin_ia32_vpmacssdd ( ( __v4si ) __A , ( __v4si )


<s> bool <ISA_LIT>InstrInfo :: isLiteralConstantLike ( const MachineOperand & MO , const MCOperandInfo & OpInfo ) const { switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : return false ; case MachineOperand :: MO_Immediate : return ! isInlineConstant ( MO , OpInfo ) ; case MachineOperand :: MO_FrameIndex : case MachineOperand :: MO_MachineBasicBlock


<s> VmemType getVmemType ( const MachineInstr & Inst ) { assert ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) ) ; if ( ! <ISA_LIT>InstrInfo :: isMIMG ( Inst ) ) return VMEM_NOSAMPLER ; const <STR_LIT> * Info = <STR_LIT> ( Inst . getOpcode ( ) ) ; return <STR_LIT> ( Info -> BaseOpcode ) -> Sampler ? VMEM_SAMPLER


<s> <ISA_LIT>TargetMachine ( T , TT , CPU ,


<s> if ( MO . isRegMask ( ) ) ModifiedRegs . setBitsNotInMask ( MO . getRegMask ( ) ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) ModifiedRegs . set ( * AI ) ; } else { assert ( MO . isUse ( ) && <STR_LIT>


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) DestRC = <STR_LIT> ; if ( SrcRC == <STR_LIT> ) SrcRC = <STR_LIT> ; if ( DestRC != SrcRC ) { if ( DestRC -> getSize ( ) != SrcRC -> getSize ( ) ) return false ; if ( DestRC -> getSize ( ) != <NUM_LIT> && DestRC -> getSize ( ) != <NUM_LIT> ) return false ; } if ( DestRC == <STR_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT>


<s> bool <ISA_LIT>FrameLowering :: canSimplifyCallFramePseudos ( const


<s> ReadOnlySection = nullptr ; StaticCtorSection = nullptr ; StaticDtorSection = nullptr ; LSDASection = nullptr ; EHFrameSection = nullptr ; DwarfAbbrevSection = nullptr ; DwarfInfoSection = nullptr ; DwarfLineSection = nullptr ; DwarfFrameSection = nullptr ; DwarfPubTypesSection = nullptr ; DwarfDebugInlineSection = nullptr ; DwarfStrSection = nullptr ; DwarfLocSection = nullptr ; DwarfARangesSection = nullptr ; DwarfRangesSection =


<s> if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; rtx addr ; bool extend = false ; if ( get_si_mem_base_reg ( mem , & addr , & extend ) ) { HOST_WIDE_INT regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; if ( i == <NUM_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_MCSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand :: MO_RegisterMask


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const <ISA_LIT>TargetMachine & TM ) : TargetLowering ( TM ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ; TD = getDataLayout ( ) ; resetOperationActions (


<s> if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ; N = New . getNode ( ) ; } if ( ! N -> isMachineOpcode ( ) ) SelectCode ( N ) ; return true ; } } unsigned Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) && RISBG . Start >= <NUM_LIT> && RISBG . End >= RISBG . Start && ( ( RISBG . Start + RISBG . Rotate ) & <NUM_LIT> ) >= <NUM_LIT> && ( ( RISBG . End + RISBG . Rotate ) & <NUM_LIT> ) >= ( ( RISBG . Start + RISBG . Rotate ) & <NUM_LIT> ) ) { Opcode = <STR_LIT> ; OpcodeVT = <STR_LIT> ; RISBG . Start &= <NUM_LIT> ; RISBG . End &= <NUM_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { getUNDEF ( DL , OpcodeVT ) , convertTo ( DL , OpcodeVT , RISBG . Input ) , CurDAG -> getTargetConstant ( RISBG . Start , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . End | <NUM_LIT> , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RISBG . Rotate , DL , <STR_LIT> ) } ; SDValue New = convertTo ( DL , VT , SDValue ( CurDAG -> getMachineNode (

Opcode , DL , OpcodeVT , Ops ) , <NUM_LIT> ) ) ;


<s> CPEBB -> setAlignment ( <NUM_LIT> ) ; } else CPEBB -> setAlignment ( getCPELogAlign ( CPEBB -> begin ( ) ) ) ; adjustBBOffsetsAfter ( CPEBB ) ; assert ( ! BBIsJumpedOver ( CPEBB )


<s> Instr ( unsigned Opcode , Register Def , Register LHS , Register RHS ) : Opcode ( Opcode ) , Def ( Def ) , LHS ( LHS


<s> bool hasBranchDivergence ( ) { return true


<s> case ADDRESS_REG_UXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return ; case ADDRESS_REG_SXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return ; case ADDRESS_REG_WB : switch ( GET_CODE ( x ) ) { case PRE_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , GET_MODE_SIZE ( mode ) ) ; return ; case POST_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , GET_MODE_SIZE ( mode ) ) ; return ; case


<s> IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * TB = nullptr , * FB = nullptr ; bool NotAnalyzed = TII -> AnalyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return false ; unsigned PredR , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) return false ; MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; if ( ! PredI -> isCompare ( ) ) return false ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int CmpImm = <NUM_LIT> , CmpMask = <NUM_LIT> ; bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ; if ( ! CmpAnalyzed ) return false ; InductionMap :: iterator IndMapEnd = IndMap . end ( ) ; InductionMap :: iterator F = IndMapEnd


<s> } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm

( ) ) ) << ImmOffs << markup ( <STR_LIT> ) ;


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym


<s> static DecodeStatus DecodeT2BROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ; return MCDisassembler ::


<s> return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } default : return false ; } SDNode * ResNode = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , VT , PtrVT , <STR_LIT> , LD -> getBasePtr ( ) , LD -> getChain ( ) ) ; ReplaceUses ( N , ResNode ) ; CurDAG -> RemoveDeadNode ( N ) ; return


<s> case AMDGPU :: S_LOAD_DWORDX4_IMM : case AMDGPU :: S_LOAD_DWORDX4_SGPR : { if ( NewOpcode == N -> getMachineOpcode ( ) ) { NewOpcode = AMDGPU :: BUFFER_LOAD_DWORDX4_ADDR64 ; } if ( fitsRegClass ( DAG , N -> getOperand ( <NUM_LIT> ) , AMDGPU :: SReg_64RegClassID ) ) { return N ; } ConstantSDNode * Offset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue Ops [ ] =


<s> assemble_name ( stream , name ) ; fprintf ( stream


<s> continue ; } if ( CachedConsts . size ( ) == <NUM_LIT> ) { CachedConsts . push_back ( BankLine ) ; UsedKCache . push_back ( std :: pair < unsigned , unsigned > ( <NUM_LIT> , KCacheIndex ) ) ; continue ; } if ( CachedConsts [ <NUM_LIT> ] == BankLine ) { UsedKCache . push_back ( std :: pair < unsigned , unsigned > ( <NUM_LIT> , KCacheIndex ) ) ; continue ; } return false ; } for ( unsigned i = <NUM_LIT> , j = <NUM_LIT> , n = Consts . size ( ) ; i < n ; ++ i ) { if ( Consts [ i ] . first -> getReg ( ) != AMDGPU :: ALU_CONST ) continue ; switch ( UsedKCache [ j ] . first ) { case <NUM_LIT> : Consts [ i ] . first -> setReg ( AMDGPU :: R600_KC0RegClass . getRegister ( UsedKCache [ j ] . second ) ) ; break ; case <NUM_LIT> : Consts [ i ] . first -> setReg ( AMDGPU :: R600_KC1RegClass . getRegister ( UsedKCache [ j ] . second ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } j ++


<s> return ( __m64 ) __builtin_arm_wmulwum ( ( __v2si ) a , ( __v2si )


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return split256IntArith ( Op ,


<s> if ( gbr_disp . is_reg ( ) && REGNO ( gbr_disp . reg ( ) ) == GBR_REG ) { for ( df_ref d = DF_REG_DEF_CHAIN ( GBR_REG ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { if ( CALL_P ( DF_REF_INSN ( d ) ) ) { if ( TEST_HARD_REG_BIT ( regs_invalidated_by_call , GBR_REG


<s> return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ,


<s> RAInfos . clear ( ) ; RAInfos = RAInfo :: computeRegAlloc ( RootScope , AvailPredRegs . size ( ) ) ; for ( auto iter = df_begin ( RootScope ) , end = df_end ( RootScope ) ; iter != end ; ++ iter ) { applyPredicates ( * iter , MF ) ; } for ( auto iter = df_begin ( RootScope ) , end = df_end ( RootScope ) ; iter != end ; ++ iter ) { auto scope = * iter ; insertPredDefinitions ( scope ) ; insertStackLocInitializations ( scope ) ; } fixupKillFlagOfCondRegs ( ) ; GuardsLdStElim = new RedundantLdStEliminator ( MF , TRI , GuardsReg , * PMFI ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; LinearizeWalker LW ( * this , MF ) ; RootScope -> walk ( LW ) ; mergeMBBs ( MF ) ; ElimLdStCnt += GuardsLdStElim -> process ( ) ; delete GuardsLdStElim ; eliminateFrameIndices ( MF ) ; MF . RenumberBlocks ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; MF . dump ( ) ) ; DEBUG ( { dbgs ( ) <<


<s> const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; if ( ! MO . isJTI ( ) && MO .

getOffset ( ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> return ( t == float128_type_node || ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && t ==


<s> unsigned i = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { const AttributeList & Attrs = F -> getAttributes ( ) ; if ( Attrs . hasParamAttribute ( i , Attribute :: ByVal ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftSelf ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftError ) || Attrs . hasParamAttribute ( i , Attribute :: InAlloca ) || Attrs . hasParamAttribute ( i , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; if ( ! Subtarget -> hasSIMD128 ( ) && ArgTy -> isVectorTy ( ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( ArgTy ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( i ) ; updateValueMap ( & Arg , ResultReg ) ; ++ i ; } MRI . addLiveIn ( <STR_LIT> ) ; auto * MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( auto const & Arg : F -> args ( ) ) { <STR_LIT> ArgTy = getLegalType ( getSimpleType ( Arg . getType ( ) ) ) ; if ( ArgTy == <STR_LIT> ) { MFI -> clearParamsAndResults ( ) ; return false ; } MFI -> addParam ( ArgTy ) ; } if ( ! F -> getReturnType ( ) -> isVoidTy ( ) ) { <STR_LIT> RetTy = getLegalType ( getSimpleType ( F -> getReturnType ( ) ) ) ; if ( RetTy == <STR_LIT> ) { MFI -> clearParamsAndResults ( ) ; return false


<s> void <ISA_LIT>InstrInfo :: loadRegFromAddr ( MachineFunction & MF , unsigned DestReg , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * >


<s> return __builtin_mve_vmovltq_uv16qi (


<s> MRI . setType ( GetReg , S32 ) ; auto ShiftAmt = B . buildConstant ( S32 , WidthM1 + <NUM_LIT> ) ; B . buildInstr ( TargetOpcode :: G_SHL ) . addDef ( ApertureReg ) . addUse ( GetReg ) . addUse ( ShiftAmt . getReg ( <NUM_LIT> ) ) ; return ApertureReg ; } Register QueuePtr = MRI . createGenericVirtualRegister ( LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! loadInputValue ( QueuePtr , B , & MFI -> getArgInfo ( ) . QueuePtr ) ) return Register ( ) ; uint32_t StructOffset = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; Value * V = UndefValue :: get ( PointerType :: get ( Type :: getInt8Ty ( MF . getFunction ( ) . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ) ; MachinePointerInfo PtrInfo ( V , StructOffset


<s> if ( ! I -> definesRegister ( AMDGPU :: M0 ) ) continue ; unsigned Opc = I -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != AMDGPU :: S_MOV_B32 ) break ; if ( ! I -> readsRegister ( SrcReg ) ) break ; return ; } } if ( AMDGPU :: SReg_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: SReg_64RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_64RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B64 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: SReg_128RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_128RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_3 ; } else if ( AMDGPU :: SReg_256RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_256RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_7 ; } else if ( AMDGPU :: SReg_512RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_512RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: S_MOV_B32 ; SubIndices = Sub0_15 ; } else if ( AMDGPU :: VReg_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_32RegClass . contains ( SrcReg ) || AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_MOV_B32_e32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( AMDGPU :: VReg_64RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_64RegClass . contains ( SrcReg ) || AMDGPU :: SReg_64RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: V_MOV_B32_e32 ; SubIndices = Sub0_1 ; } else if ( AMDGPU :: VReg_96RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_96RegClass . contains ( SrcReg ) ) ; Opcode = AMDGPU :: V_MOV_B32_e32 ; SubIndices =


<s> if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first ->


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle , bool MinSize ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , ReservedGPRegisters ( <STR_LIT> . getNumRegs ( ) ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo (


<s> if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) )


<s> } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; if ( MACHOPIC_INDIRECT ) funexp = machopic_indirect_call_target ( funexp ) ; insn = emit_call_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_CALL ( VOIDmode , funexp , const0_rtx ) , gen_rtx_USE ( VOIDmode , const0_rtx ) , simple_return_rtx ) ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT> ) ; final_end_function ( ) ; reload_completed = <NUM_LIT> ; epilogue_completed =


<s> const MachineOperand & RO = PN -> getOperand ( i ) , & BO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( BO . getMBB ( ) == FP . SplitB ) SR = RO . getReg ( ) , SSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . TrueB ) TR = RO . getReg ( ) , TSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR


<s> gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part


<s> Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; Register Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) ) ) MIB . add ( MO ) ; if ( ! Using<ISA_LIT>32 ) { Register Tmp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( Rt , <NUM_LIT> , <STR_LIT> ) ; Rt =


<s> for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCII , MCI ) ) { if ( <ISA_LIT>MCInstrInfo :: isDuplex ( MCII , I ) ) return true ; } return


<s> SmallVector < int , <NUM_LIT> > Mask ( NumElems ) ; for ( unsigned i = <NUM_LIT> , Half = NumElems / <NUM_LIT> ; i != Half ; ++ i ) { Mask [ i * <NUM_LIT> ] = i + Half ; Mask [ i * <NUM_LIT> + <NUM_LIT> ]


<s> } case GATHER : { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getGatherNode ( IntrData -> Opc0 , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case SCATTER : { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getScatterNode ( IntrData -> Opc0 , Op , DAG , Src , Mask , Base , Index , Scale , Chain ) ; } case PREFETCH : { SDValue Hint = Op . getOperand ( <NUM_LIT> ) ; unsigned HintVal ; if ( dyn_cast < ConstantSDNode > ( Hint ) == nullptr || ( HintVal = dyn_cast < ConstantSDNode > ( Hint ) -> getZExtValue ( ) ) > <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; unsigned Opcode = ( HintVal ? IntrData -> Opc1 : IntrData -> Opc0 ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getPrefetchNode ( Opcode , Op , DAG , Mask , Base , Index , Scale , Chain ) ; } case RDTSC :


<s> bool <ISA_LIT>MCInst :: isPacketBegin ( )


<s> unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ; high = ( highp ? <NUM_LIT> : nelt


<s> const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & SrcRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( SrcRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( OffsetImmOp . isImm ( ) && <STR_LIT> ) ; unsigned SrcReg = SrcRegOp . getReg ( ) ; int64_t OffsetValue = OffsetImmOp . getImm ( ) ; unsigned ATReg = <NUM_LIT> ; bool LoadedOffsetInAT = false ; if ( ! isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) || ! isInt < <NUM_LIT> > ( OffsetValue ) ) { ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; LoadedOffsetInAT = true ; warnIfNoMacro ( IDLoc ) ; if ( loadImmediate ( OffsetValue , ATReg , <STR_LIT> , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Instructions ) ) return true ; if ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> ) createAddu ( ATReg , ATReg , SrcReg , ABI . ArePtrs64bit ( ) , Instructions ) ; } unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg ; int64_t LeftLoadOffset = <NUM_LIT> , RightLoadOffset = <NUM_LIT> ; if ( isLittle ( ) ) { LeftLoadOffset = LoadedOffsetInAT ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; RightLoadOffset = LoadedOffsetInAT ?


<s> const avl_info & get_avl_info ( ) const { return m_avl


<s> current_target_pragma = NULL_TREE ; for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode


<s> if ( ! ( target_type_from == FP32 ) ) goto LOOP_BOTTOM ; int clean_type_to = ~ ( ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> ) ; int window = sw & clean_type_to ; int sw_to_i32 = window | ( INT32 << <NUM_LIT> ) ; unsigned incomreg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MIB = BuildMI ( * MBB , mi , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , incomreg ) ; unsigned dr2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MIB = BuildMI ( * MBB , mi , MI -> getDebugLoc ( ) , MI -> getDesc ( ) , dr2 ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( sw_to_i32 ) ; MIB . addReg ( incomreg ) ; for ( unsigned int i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; i ++ ) { MIB . add ( MI -> getOperand ( i ) ) ; } MIB = BuildMI ( * MBB , mi , MI -> getDebugLoc ( ) , TII -> get ( is_gaudi ? <STR_LIT> : <STR_LIT> ) , destreg ) ; MIB . addReg ( dr2 ) ; MIB . addImm ( <NUM_LIT> ) ; sw = ( ( target_type_to & <NUM_LIT> ) << <NUM_LIT> ) | ( rm << <NUM_LIT> ) | lane_sel ; MIB . addImm ( sw ) ; for ( unsigned int i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; i ++ ) { MIB . add ( MI -> getOperand ( i ) ) ; } MI -> removeFromParent ( ) ; ++ NumReplaced ; } else if ( opc == <STR_LIT> ) { MachineOperand opnd2 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand opnd3 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand opnd4 = MI -> getOperand ( <NUM_LIT> ) ; int64_t destreg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( opnd2 . isImm ( ) && opnd3 . isImm ( ) && opnd4 . isReg ( ) ) ; int64_t sw = opnd3 . getImm ( ) ; int lane_sel = sw & <NUM_LIT> ; int target_type_to = ( sw >> <NUM_LIT> ) & <NUM_LIT> ; if ( ! ( target_type_to == INT8 || target_type_to == INT16 ) ) goto LOOP_BOTTOM ; int rm = ( sw >> <NUM_LIT> ) &


<s> OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( VSTRS_CC ) ; OPCODE ( VSTRSZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( ATOMIC_CMP_SWAP ) ; OPCODE ( ATOMIC_LOAD_128 ) ; OPCODE ( ATOMIC_STORE_128 ) ; OPCODE ( ATOMIC_CMP_SWAP_128 ) ; OPCODE ( LRV ) ; OPCODE ( STRV ) ; OPCODE ( VLER ) ; OPCODE ( VSTER )


, <NUM_LIT> , narrowToSmallerAndWidenToSmallest ) ;


<s> bool isISA3_0 ( ) const { return IsISA3_0


<s> emit_insn ( gen_add2_insn ( countreg , GEN_INT ( - value


<s> TargetRegistry :: RegisterMCAsmBackend ( * T , createAsmBackend ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , createMCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T


<s> if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode =


<s> return ( __m64 ) __builtin_ia32_packssdw ( ( __v2si ) __m1 ,


<s> return ( __m64 ) __builtin_ia32_pcmpgtd ( ( __v2si ) __m1 , ( __v2si )


<s> case FRV_BUILTIN_MWTACC : return frv_expand_mwtacc_builtin ( CODE_FOR_mwtacc , arglist ) ; case FRV_BUILTIN_MWTACCG : return frv_expand_mwtacc_builtin ( CODE_FOR_mwtaccg , arglist ) ; case FRV_BUILTIN_MDPACKH : return frv_expand_mdpackh_builtin ( arglist , target ) ; case FRV_BUILTIN_IACCreadll : { rtx src = frv_read_iacc_argument ( DImode , & arglist ) ; if ( target == <NUM_LIT> || ! REG_P ( target ) ) target = gen_reg_rtx ( DImode ) ; frv_split_iacc_move ( target , src ) ; return target ; } case FRV_BUILTIN_IACCreadl : return frv_read_iacc_argument ( SImode , & arglist ) ; case FRV_BUILTIN_IACCsetll : { rtx dest = frv_read_iacc_argument ( DImode , & arglist ) ; rtx src = frv_read_argument ( & arglist ) ; frv_split_iacc_move ( dest , force_reg ( DImode , src ) ) ; return <NUM_LIT> ; } case FRV_BUILTIN_IACCsetl : { rtx dest = frv_read_iacc_argument ( SImode , & arglist ) ; rtx src = frv_read_argument ( & arglist ) ; emit_move_insn ( dest , force_reg ( SImode , src ) ) ; return <NUM_LIT> ; } default : break ; } for ( i = <NUM_LIT> , d = bdesc_set ; i < ARRAY_SIZE ( bdesc_set ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_set_builtin ( d -> icode , arglist , target ) ; for ( i = <NUM_LIT> , d = bdesc_1arg ; i < ARRAY_SIZE ( bdesc_1arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_unop_builtin ( d -> icode , arglist , target ) ; for ( i = <NUM_LIT> , d = bdesc_2arg ; i < ARRAY_SIZE ( bdesc_2arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_binop_builtin ( d -> icode , arglist , target ) ; for ( i = <NUM_LIT> , d = bdesc_cut ; i < ARRAY_SIZE ( bdesc_cut ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_cut_builtin ( d -> icode , arglist , target ) ; for ( i = <NUM_LIT> , d = bdesc_2argimm ; i < ARRAY_SIZE ( bdesc_2argimm ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_binopimm_builtin ( d


<s> } } ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( Offset . getValue

( ) , AddrSpace , Signed ) ) return Default ;


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( Subtarget . hasAVX512 ( ) && ( Subtarget . useAVX512Regs ( ) || ! VT . is512BitVector ( ) ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT . is256BitVector ( ) ; bool AShift = LShift && VT != <STR_LIT> && VT != <STR_LIT> ; return ( Opcode == <STR_LIT> ) ? AShift :


<s> void <ISA_LIT>TargetStreamer :: closeLastSection (


<s> return legalizeLoadStore ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return legalizeShlAshrLshr ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeSmallCMGlobalValue ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_TRUNC : return legalizeVectorTrunc ( MI , Helper ) ; case TargetOpcode :: G_SBFX : case TargetOpcode :: G_UBFX : return legalizeBitfieldExtract ( MI , MRI , Helper ) ; case TargetOpcode :: G_ROTR : return legalizeRotate ( MI , MRI , Helper ) ; case TargetOpcode :: G_CTPOP : return legalizeCTPOP ( MI , MRI , Helper ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpxchg128 ( MI , MRI , Helper ) ; case TargetOpcode :: G_CTTZ : return legalizeCTTZ ( MI , Helper ) ; case TargetOpcode ::


<s> static LLT divideLLT ( LLT Ty , int Factor ) { if ( Ty . isVector ( ) ) return LLT :: vector ( Ty . getNumElements ( ) / Factor , Ty . getElementType ( ) ) ; return LLT :: scalar ( Ty . getSizeInBits ( )


<s> FunctionPass * llvm :: create<ISA_LIT>DomainReassignmentPass ( ) { return new <ISA_LIT>DomainReassignment (


<s> void llvm :: getLibcallSignature ( const <ISA_LIT>Subtarget & Subtarget , const char * Name , SmallVectorImpl < <STR_LIT> > & Rets , SmallVectorImpl < <STR_LIT> > & Params ) { auto & Map = LibcallNameMap -> Map ; auto Val = Map . find ( Name ) ; if ( Val == Map . end ( ) ) { auto message = std :: string ( <STR_LIT> ) + Name ; llvm_unreachable ( message . c_str ( ) ) ; } return getLibcallSignature ( Subtarget , Val -> second


<s> else Reg = V64RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> std :: tie ( type , stloc ) = R . getDefLoc ( pred ) ; if ( type == RAInfo :: Stack ) { int fi ; unsigned bitpos ; getStackLocPair ( fi , bitpos , stloc ) ; DEBUG ( dbgs ( ) << <STR_LIT> << pred << <STR_LIT> << stloc << <STR_LIT> << fi << <STR_LIT> << bitpos << <STR_LIT> ) ; if ( ! masks . count ( fi ) ) { masks [ fi ] = <NUM_LIT> ; } masks [ fi ] |= ( <NUM_LIT> << bitpos ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * MBB = S -> getHeader ( ) -> getMBB ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; if ( S -> isTopLevel ( ) ) { while ( MI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MI ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DebugLoc DL ; for ( std :: map < int , uint32_t > :: iterator I = masks . begin ( ) , E = masks . end ( ) ; I != E ; ++ I ) { int fi = I -> first ; uint32_t mask = I -> second ; DEBUG ( dbgs ( ) << <STR_LIT> << fi << <STR_LIT> << mask << <STR_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , GuardsReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , GuardsReg ) ) . addReg


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass >


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrModeNoIndex ( SDValue N , SDValue & Val ) { EVT ValTy = N . getValueType ( ) ; if ( ValTy != <STR_LIT> ) return false ; Val =


<s> } } if ( DoSjLj ) { Changed = true ; Function * MallocF = M . getFunction ( <STR_LIT> ) ; Function * FreeF = M . getFunction ( <STR_LIT> ) ; if ( ! MallocF || ! FreeF ) report_fatal_error ( <STR_LIT> ) ; FunctionType * SetjmpFTy = SetjmpF -> getFunctionType ( ) ; SmallVector < Type * , <NUM_LIT> > Params = { SetjmpFTy -> getParamType ( <NUM_LIT> ) , IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } ; FunctionType * FTy = FunctionType :: get ( Type :: getInt32PtrTy ( C ) , Params , false ) ; SaveSetjmpF = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , SaveSetjmpFName , & M ) ; Params = { IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } ; FTy = FunctionType :: get ( IRB . getInt32Ty ( ) , Params , false ) ; TestSetjmpF = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , TestSetjmpFName , & M ) ; if ( LongjmpF ) { EmLongjmpJmpbufF = Function :: Create ( LongjmpF -> getFunctionType ( ) , GlobalValue :: ExternalLinkage , EmLongjmpJmpbufFName , & M ) ; LongjmpF -> replaceAllUsesWith ( EmLongjmpJmpbufF ) ; } FTy = FunctionType :: get ( IRB . getVoidTy ( ) , { IRB . getInt32Ty ( ) , IRB . getInt32Ty ( ) } , false ) ; EmLongjmpF = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , EmLongjmpFName , & M ) ; SmallPtrSet < Function * , <NUM_LIT> > SetjmpUsers ; for ( User * U :


<s> static bool isBaseAlignmentOfN ( unsigned N , SDNode * Base , const TargetLowering & TLI ) { GlobalValue *


<s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) { return MCDisassembler :: Fail ; } Register Reg = FPR64DecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success


<s> if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue Madd = DAG . getNode ( <STR_LIT> , DL , MAddVT , N0 , N1 ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , Madd , Zero ) ; return DAG . getNode ( <STR_LIT> , DL , VT ,


<s> enum machine_mode mode = TYPE_MODE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE && ! VECTOR_MODE_P ( mode ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == <NUM_LIT> || size == <NUM_LIT> ) && TYPE_VECTOR_SUBPARTS ( type ) > <NUM_LIT> ) { enum machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type


<s> bool <ISA_LIT>PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( create<ISA_LIT>ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass (


<s> MachineBasicBlock * getMBB ( ) const { return


<s> if ( CPU == <STR_LIT> ) return <STR_LIT> ; if ( Subtarget -> hasV8Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isMClass ( ) && Subtarget -> hasThumb2DSP ( ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( Subtarget -> hasV6T2Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6MOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TEOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV4TOps ( ) ) return <STR_LIT> ; else return <STR_LIT>


<s> LowerPATCHABLE_FUNCTION_EXIT ( * MI ) ; return ; case <STR_LIT> : LowerPATCHABLE_TAIL_CALL ( * MI ) ; return ; } if ( EmitJalrReloc && ( MI -> isReturn ( ) || MI -> isCall ( ) || MI -> isIndirectBranch ( ) ) ) { emitDirectiveRelocJalr ( * MI , OutContext , TM , * OutStreamer , * Subtarget ) ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I ->

getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) {


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) .

addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen )

) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ;