<s> unsigned Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else { Expr = getImm ( ) ; } <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( <ISA_LIT>AsmParser :: classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) { return DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGEOFF || ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF && Addend == <NUM_LIT> ) || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr

:: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ;


<s> case <STR_LIT> : { Opcode = <STR_LIT> ; break ; } } SDValue Chain = ST -> getChain ( ) ; SDVTList VTs = ST -> getVTList ( ) ; SDValue Ops [ ] = { ST -> getValue ( ) , Base . getOperand ( <NUM_LIT> ) , Base . getOperand ( <NUM_LIT> ) , Chain } ; SDNode * MN = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; transferMemOperands ( ST , MN ) ; ReplaceNode ( ST , MN


<s> __builtin_ia32_pmovqb128mem_mask ( ( unsigned short * ) __P , ( __v2di ) __A ,


<s> SDValue OP1 ; if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext0 = MulOp0 . getOperand ( <NUM_LIT> ) ; if ( Sext0 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP0 = Sext0 ; } else if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp0 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; OP0 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand ( <NUM_LIT> ) ; if ( Sext1 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP1 = Sext1 ; } else if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp1 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; OP1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , OP0


<s> unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ; SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD , DAG . getUNDEF ( SadVT ) , Mask ) ; SAD = DAG . getNode ( <STR_LIT> , DL , SadVT , SAD , Shuffle ) ; } } unsigned ExtractSizeInBits = ExtractVT . getSizeInBits ( ) ; EVT ResVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtractVT , SadVT . getSizeInBits ( ) / ExtractSizeInBits ) ; SAD = DAG . getBitcast ( ResVT , SAD


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoMacro ( ) { OS <<


<s> for ( ptr = isr_attribute_args ; ptr -> arg != NULL ; ptr ++ ) if ( streq ( arg , ptr -> arg ) ) return ptr -> return_value ; return


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> :


<s> const TargetRegisterClass * TRC = TargetRegisterInfo :: isVirtualRegister ( RegNo ) ? MRI -> getRegClass ( RegNo ) : MRI -> getTargetRegisterInfo ( ) -> getMinimalPhysRegClass ( RegNo ) ; for ( MVT T : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if


<s> bool has<ISA_LIT>32r2 ( ) const { return <ISA_LIT>ArchVersion == <ISA_LIT>32r2 || <ISA_LIT>ArchVersion == <ISA_LIT>32r6 || <ISA_LIT>ArchVersion ==


<s> if ( ! target ) { return ; } assert ( target -> MBB && <STR_LIT> ) ; if ( target -> MBB != layout_successor ) { const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; if ( PTM . getCodeModel ( ) != CodeModel :: Large || block -> Region == target -> Region ) { unsigned Opc = block -> Region == target -> Region ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( Opc ) ) ) . addMBB ( target -> MBB ) ; } else { AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) ) . addMBB ( target -> MBB ) ; AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } MachineBasicBlock :: iterator II = fallthrough -> end ( ) ; -- II ; unsigned cycles = PTM . getSubtargetImpl ( ) -> getDelaySlotCycles ( * II ) ; if ( PTM . getSubtargetImpl ( ) -> getCFLType ( ) != <ISA_LIT>Subtarget :: CFL_NON_DELAYED && ! PII . hasRegUse ( & * II ) ) { cycles = PII . moveUp ( * fallthrough , II ) ; } for ( unsigned i = <NUM_LIT> ; i < cycles ; i ++ ) { AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ) ; NOPsInserted ++ ; } FallthroughFixups ++ ; block -> FallthroughTarget = NULL ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << fallthrough -> getName ( ) << <STR_LIT> << ( layout_successor ? layout_successor -> getName ( ) : <STR_LIT> ) <<

<STR_LIT> << target -> getName ( ) << <STR_LIT> ) ;


<s> static bool readsVCCZ ( unsigned Opcode


<s> static unsigned char * unw_decode_b2 ( unsigned char * dp , unsigned char code , void * arg ) { unw_word t ; t = unw_decode_uleb128 ( & dp


<s> MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_Mask ( Op , Subtarget , DAG ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == <STR_LIT> ) { if ( ! ExperimentalVectorWideningLegalization || VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , In ) ; unsigned NumElems = InVT


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get (


<s> LowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT> ) ; return


<s> Value = extractBitsForFixup ( Fixup . getKind ( ) , Value ) ; return ( int16_t ) Value != ( int64_t


<s> SDValue Glued = emitIntrinsicWithGlue ( DAG , Op , Opcode ) ; SDValue CC = getCCResult ( DAG , Glued . getNode ( ) ) ; if ( Op -> getNumValues ( ) == <NUM_LIT> ) return CC ; assert ( Op -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op -> getVTList ( ) , Glued , CC ) ; } unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Id ) { case <STR_LIT> : return lowerThreadPointer ( SDLoc ( Op ) , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case


<s> while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return computed ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type =


<s> if ( <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) return false ; unsigned SchedClass = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . getSchedClass ( ) ; switch ( SchedClass ) { case <STR_LIT> :: ALU32_3op_tc_2_SLOT0123 : case <STR_LIT>


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS


<s> if ( ! Parser . getTok ( ) . is ( AsmToken :: Colon ) ) return false ; Lex ( ) ; char const * MemNoShuffMsg = <STR_LIT> <STR_LIT> ; StringRef Option = Parser . getTok ( ) . getString ( ) ; auto IDLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; } else if ( Option . compare_lower ( <STR_LIT> )


<s> unsigned Opc = MBBI -> getOpcode ( ) ; if ( MBBI -> readsRegister ( Base ) ) { int Offset ; bool IsLoad = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsStore = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; unsigned InstrSrcReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( MBBI ) || MBBI -> isCall ( ) || MBBI -> isBranch


<s> SDValue <ISA_LIT>TargetLowering :: lowerFABS ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> has<ISA_LIT>64 ( ) && ( Op . getValueType ( ) == <STR_LIT> ) ) return lowerFABS64 (

Op , DAG , Subtarget -> has<ISA_LIT>32r2 ( ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) Val = <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return


<s> } else if ( <STR_LIT> . contains ( BP ) ) { MinGPR = std :: min < unsigned > ( MinGPR , BP ) ; HasGPSaveArea = true ; } } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { if ( ! GPRegs [ i ] . isSpilledToReg ( ) ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { if ( ! G8Regs [ i ] . isSpilledToReg ( ) ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && Subtarget . is32BitELFABI ( ) ) { for ( const auto & CSInfo : CSI ) { if ( CSInfo . getReg ( ) == <STR_LIT> ) { int FI = CSInfo . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; break ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSAVESaveArea ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSaveArea ) { assert ( LowerBound <= <NUM_LIT> && <STR_LIT> ) ; LowerBound &= ~ ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = VRegs . size ( )


<s> return ( code == SYMBOL_REF || code == LABEL_REF || code == CONST || code == HIGH


<s> { <STR_LIT> , <STR_LIT> , MASK_64BIT } , { <STR_LIT> , <STR_LIT> , OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF \ | MASK_POWERPC64 } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , OPTION_MASK_ALTIVEC } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { NULL , <STR_LIT> , <NUM_LIT> } } ; const char * cpu_id = <STR_LIT> ; size_t i ; rs6000_file_start ( ) ; darwin_file_start ( ) ; if ( rs6000_default_cpu != <NUM_LIT> && rs6000_default_cpu [ <NUM_LIT> ] != '\0' ) cpu_id = rs6000_default_cpu ; if ( OPTION_SET_P ( rs6000_cpu_index ) ) cpu_id = processor_target_table [ rs6000_cpu_index ] . name ; i = <NUM_LIT> ; while ( mapping [ i ] . arg != NULL && strcmp ( mapping [ i ] . arg , cpu_id ) != <NUM_LIT> && ( mapping [ i

] . if_set & rs6000_isa_flags ) == <NUM_LIT> ) i ++ ;


<s> unsigned DstB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; DstB = decodeBField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstB , Address , Decoder ) ; using Field = decltype ( Insn ) ; Field U6Field = fieldFromInstruction ( Insn


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cmpord_ss ( __m128 __A , __m128 __B ) { __vector unsigned int a , b ; __vector unsigned int c , d ; static const __vector unsigned int float_exp_mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __A ) ; b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( float_exp_mask


<s> case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; Align Alignment = GV -> getPointerAlignment ( CurDAG -> getDataLayout ( ) ) ; MaxDisplacement = std :: min ( ( int ) Alignment . value ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase = true


| __C , ( __v2df ) _mm_setzero_pd ( ) , __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getCPUDirective ( ) == <STR_LIT>


<s> if ( AVR_HAVE_RAMPY && ! frame_pointer_needed && ( REG_Y == regno || REG_Y + <NUM_LIT> == regno ) && TEST_HARD_REG_BIT ( * set , REG_Y ) && TEST_HARD_REG_BIT ( * set , REG_Y + <NUM_LIT> ) ) continue ; if ( AVR_HAVE_RAMPZ && ( REG_Z == regno || REG_Z + <NUM_LIT> == regno ) && TEST_HARD_REG_BIT ( * set , REG_Z ) && TEST_HARD_REG_BIT ( * set , REG_Z + <NUM_LIT> ) ) continue ; CLEAR_HARD_REG_BIT ( * set , regno ) ; return regno


<s> void <ISA_LIT>InsertWaits :: handleSendMsg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { if ( ST -> getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return ; if ( LastInstWritesM0 && I -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; LastInstWritesM0 = false


<s> Optional < <STR_LIT> :: <ISA_LIT>TargetID > & getTargetID ( ) { return


<s> if ( ! Subtarget . has<ISA_LIT>64 ( ) ) PM . add ( create<ISA_LIT>EmitGPRestorePass ( * this ) ) ; return


<s> bool <STR_LIT> ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } if ( isCallIndirect ( MI . getOpcode ( ) ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI . getOpcode ( ) ) ) ; assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow (


<s> static MachineInstr * MoveForSingleUse ( unsigned Reg , MachineInstr * Def , MachineBasicBlock & MBB , MachineInstr * Insert , LiveIntervals & LIS , <ISA_LIT>FunctionInfo & MFI ) { MBB . splice ( Insert , & MBB , Def ) ; LIS . handleMove ( * Def


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc =


<s> replaceNodeWithFunctionCall ( I , URemFunc ) ; return true ; case Instruction :: SDiv : if ( ! SDivFunc ) report_fatal_error ( <STR_LIT> ) ; replaceNodeWithFunctionCall ( I , SDivFunc ) ; return true ; case Instruction :: SRem : if ( ! SRemFunc ) report_fatal_error ( <STR_LIT> ) ; replaceNodeWithFunctionCall ( I ,


<s> return new <ISA_LIT>PassConfig ( * this ,


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm - <NUM_LIT> ) && VK == <ISA_LIT>MCExpr


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < <NUM_LIT> ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym ,


<s> aarch64_layout_frame ( ) ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + <NUM_LIT> ) ; bitmap_clear ( components ) ; for ( unsigned regno = <NUM_LIT> ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { HOST_WIDE_INT offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components


<s> EVT VT = Op0 . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumActiveLanes = NumElts ; assert ( ( NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> || NumActiveLanes == <NUM_LIT> ) && <STR_LIT> ) ; while ( NumActiveLanes > <NUM_LIT> ) { unsigned RevOpcode = NumActiveLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Rev = DAG . getNode ( RevOpcode , dl , VT , Op0 ) ; Op0 = DAG . getNode ( BaseOpcode , dl , VT , Op0 , Rev ) ; NumActiveLanes /= <NUM_LIT> ; } SDValue Res ; if ( NumActiveLanes == <NUM_LIT> ) { SDValue Ext0 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext2 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ext3 = DAG . getNode ( <STR_LIT> , dl , EltVT , Op0 , DAG . getConstant ( <NUM_LIT> * NumElts / <NUM_LIT> , dl


<s> if ( MEM_SIZE_KNOWN_P ( orig_dst ) ) set_mem_size ( dst , MEM_SIZE ( orig_dst ) - align_bytes ) ; if ( ! issetmem ) { int src_align_bytes = get_mem_align_offset ( src , desired_align * BITS_PER_UNIT ) ; if ( src_align_bytes >= <NUM_LIT> ) src_align_bytes = desired_align - src_align_bytes ; if ( src_align_bytes >= <NUM_LIT> ) { unsigned int src_align ; for ( src_align = desired_align ; src_align >= <NUM_LIT> ; src_align >>= <NUM_LIT> ) { if ( ( src_align_bytes & ( src_align - <NUM_LIT> ) ) == ( align_bytes & ( src_align - <NUM_LIT> ) ) ) break ; } if ( src_align > ( unsigned int ) desired_align ) src_align = desired_align ; if ( MEM_ALIGN ( src ) < src_align * BITS_PER_UNIT ) set_mem_align ( src , src_align * BITS_PER_UNIT ) ; } if ( MEM_SIZE_KNOWN_P ( orig_src ) ) set_mem_size ( src ,


<s> case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShiftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFunnelShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerZERO_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerANY_EXTEND ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerEXTEND_VECTOR_INREG ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerStore ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFaddFsub ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFABSorFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op ,


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override


<s> if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue SetCC32 = DAG . getSetCC ( dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) , CC ) ; int ShuffV [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue Shuff = DAG . getVectorShuffle ( <STR_LIT> , dl , SetCC32 , SetCC32 , ShuffV ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shuff , SetCC32 ) ) ; } return Op ; } if ( SDValue V = lowerCmpEqZeroToCtlzSrl ( Op , DAG ) ) return V ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { if ( C -> isAllOnes ( ) || C -> isZero ( ) ) return SDValue ( ) ; } if ( LHSVT . isInteger ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { EVT VT = Op . getValueType ( ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl


<s> return & * I ; } ++ NumCmpTermRejs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; return nullptr ; } for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) || ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumImmRangeRejs ; return nullptr ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case


<s> if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return nullptr ; } std :: pair < bool , SDNode * > Ret = selectNode ( Node ) ; if ( Ret . first ) return Ret . second ; switch ( Opcode ) { default :


<s> std :: vector < std :: string > lim ( Ax a , Ax b ) { return D ( <STR_LIT> , R ( a )


<s> else if ( IDVal == <STR_LIT> ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveRegSave ( DirectiveID .


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU16ImmDecOperand ( MI , OpNo ,


<s> static section * spu_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( TREE_TYPE ( decl ) != error_mark_node && TYPE_ADDR_SPACE (

TREE_TYPE ( decl ) ) == ADDR_SPACE_EA ) {


<s> return ( __m512i ) __builtin_ia32_expandloadqi512_mask ( ( const __v64qi * ) __C , ( __v64qi ) __A , (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL )

: LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {


<s> initialize<ISA_LIT>CopyToCombinePass ( * PassRegistry ::


<s> MCObjectWriter * create<ISA_LIT>WinCOFFObjectWriter ( raw_pwrite_stream


<s> EVT VT = V . getValueType ( ) ; DebugLoc dl = V . getDebugLoc ( ) ; if ( VT . is128BitVector ( ) ) { V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT> ) , & SplatMask [ <NUM_LIT> ] ) ; } else if ( VT . is256BitVector ( ) ) { int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo , EltNo + <NUM_LIT> , EltNo + <NUM_LIT>

, EltNo + <NUM_LIT> , EltNo + <NUM_LIT> } ;


<s> const MachineOperand * ImmOp = getNamedOperand ( DefMI , <STR_LIT> :: src0 ) ; assert ( ImmOp ) ; if ( ! ImmOp -> isImm ( ) ) { return false ; } UseMI . setDesc ( get ( NewOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( ImmOp -> getImm ( ) ) ; UseMI . addImplicitDefUseOperands ( * UseMI . getParent ( ) -> getParent ( ) ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; const MachineOperand & ImmOp = DefMI . getOperand ( <NUM_LIT> ) ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; unsigned Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands (


<s> static int indirectable_constant_address_p ( rtx x ) { return CONSTANT_ADDRESS_P ( x


<s> gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = <NUM_LIT> ; unsigned int actual_versions = <NUM_LIT> ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= <NUM_LIT> ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - <NUM_LIT> ) ) ; default_decl = ( * fndecls ) [ <NUM_LIT> ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rn |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) )


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned SPReg = MFI -> getStackPtrOffsetReg ( ) ; unsigned Op = IsDestroy ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII -> get ( Op ) , SPReg ) . addReg ( SPReg ) . addImm ( Amount * ST . getWavefrontSize ( ) ) ; } else if ( CalleePopAmount != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } return MBB . erase (


<s> ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregxidf ( __o , <NUM_LIT> ) } ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregxidf ( __o ,


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( SDValue Res = tryCombineToEXTR ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineToBSL ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineVecOrNot ( N , DCI ) ) return Res ; return SDValue ( )


unsigned int __data1 , unsigned int __flags ) {


<s> case 'c' : return make_vector < unsigned > ( I0 , I1 , I2 , I3 , B0 , B1 , B2 , B3 , L0 , L1 , L2 , L3 , <NUM_LIT> ) ; case 't' : return make_vector < unsigned > ( LT0 , LT1 , <NUM_LIT> ) ; case 'u' : return make_vector < unsigned > ( LB0 , LB1 , <NUM_LIT> ) ; case 'k' : return make_vector < unsigned > ( LC0 , LC1 , <NUM_LIT> ) ; case 'y' : return make_vector < unsigned > ( RETS , RETN , RETI , RETX , RETE , ASTAT , SEQSTAT


<s> bool <ISA_LIT>InstructionSelector :: selectG_GEP ( MachineInstr &


<s> int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , Data0Idx ) ) / <NUM_LIT> ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; BaseOps . push_back ( BaseOp ) ; Offset = EltSize * Offset0 ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) { DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data1 ) ; Width += getOpSize ( LdSt , DataOpIdx ) ; } else { Width = getOpSize ( LdSt , DataOpIdx ) ; } } return true ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * RSrc = getNamedOperand ( LdSt , <STR_LIT> :: srsrc ) ; if ( ! RSrc ) return false ; BaseOps . push_back ( RSrc ) ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( BaseOp && ! BaseOp -> isFI ( ) ) BaseOps . push_back ( BaseOp ) ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; Offset = OffsetImm -> getImm ( ) ; const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset ) { if ( SOffset -> isReg ( ) ) BaseOps . push_back ( SOffset ) ; else Offset += SOffset -> getImm ( ) ; } DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdata ) ; if ( DataOpIdx == - <NUM_LIT> ) return false ; Width = getOpSize ( LdSt , DataOpIdx ) ; return true ; } if ( isMIMG ( LdSt ) ) { int SRsrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; BaseOps . push_back ( & LdSt . getOperand


<s> case <STR_LIT> : switch ( Gb ) { default : break ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } break ; case <STR_LIT> : switch ( Gb ) { default : break ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } break ; case <STR_LIT> : switch ( Gb ) { default : break ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } break ; case <STR_LIT> : switch ( Gb ) { default : break ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } break ; case <STR_LIT> : switch ( Gb ) { default : break ; case <STR_LIT> : return <NUM_LIT> ; } break ; case <STR_LIT> : switch ( Gb ) { case <STR_LIT> : return <NUM_LIT>


<s> assert ( Addr && Addr -> isFI ( ) ) ; FrameIndex = Addr -> getIndex ( ) ; return getNamedOperand ( MI , <STR_LIT> :: data )


<s> if ( cum -> nregs && bytes <= cum -> nregs ) return gen_rtx_REG ( mode , cum ->


<s> memset ( sc -> rws_insn , <NUM_LIT> , sizeof ( rws_insn ) ) ; sc -> first_instruction = <NUM_LIT> ; sc -> pending_data_specs = <NUM_LIT> ; sc -> current_cycle = <NUM_LIT> ; memset ( sc -> mem_ops_in_group , <NUM_LIT> , sizeof ( mem_ops_in_group ) ) ; } else { memcpy ( sc -> prev_cycle_state , prev_cycle_state , dfa_state_size ) ; sc -> last_scheduled_insn = last_scheduled_insn ; memcpy ( sc -> rws_sum , rws_sum , sizeof ( rws_sum ) ) ; memcpy ( sc -> rws_insn , rws_insn , sizeof ( rws_insn ) ) ; sc -> first_instruction


<s> static HOST_WIDE_INT get_label_padding ( rtx label ) { HOST_WIDE_INT align , min_insn_size ; align = <NUM_LIT> << label_to_alignment ( label ) ; min_insn_size = TARGET_THUMB ? <NUM_LIT>


<s> auto TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; SmallVector < unsigned , <NUM_LIT> > PhysRegs ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { RegOffsets . push_back ( Offset ) ; SplitRegs . push_back ( Reg ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( ! RegOffsets . empty ( ) ) MIRBuilder . buildSequence ( OrigRet . Reg , SplitRegs , RegOffsets ) ; } CallSeqStart . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; return


<s> if ( offset != <NUM_LIT> ) { if ( ! loongarch_valid_base_register_p ( base , mode , false ) ) base = copy_to_mode_reg ( Pmode , base ) ; addr = loongarch_add_offset ( NULL , base , offset ) ; return loongarch_force_address ( addr , mode


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> || Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ValTy = Op -> getValueType


<s> assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; if ( ! IsSigned && isIntegerTypeFTOL ( DstTy ) ) Opc = <STR_LIT> ; else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack (

SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ;


<s> tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return


<s> Size = getPointerWidth ( ) ; InstInfo -> AsmRewrites -> emplace_back ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ; } return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size , Identifier , Info . OpDecl ) ; } const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Disp ) ; bool IsSymRef = isa < MCSymbolRefExpr > ( BinOp ? BinOp -> getLHS ( ) : Disp ) ; if ( IsSymRef ) { if ( ! Size ) { Size = Info .


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_adds_pu8 ( __m64 __m1 , __m64 __m2 ) { __vector unsigned char a , b , c ; a = ( __vector unsigned char ) vec_splats ( __m1 ) ; b = ( __vector unsigned char ) vec_splats ( __m2 ) ; c = vec_adds ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t )


<s> const uint64_t Mask = ( ( UINT64_C ( <NUM_LIT> ) << width ) - <NUM_LIT> ) << shift ; C .* ptr &= ( T ) ~ Mask ; C .* ptr |= ( T ) ( ( Lexer . getTok ( ) . getIntVal ( ) << shift ) & Mask ) ; return true


<s> for ( auto I = Begin ; I != End ; ++ I ) { MachineInstr * MI = * I ; if ( ! MI ) continue ; if ( handledStoreType ( MI ) ) { if ( instrAliased ( Group , getStoreTarget ( MI ) ) ) return ; if ( instrAliased ( Other , getStoreTarget ( MI ) ) ) return ; unsigned BR = getBaseAddressRegister ( MI


<s> unsigned SType = <NUM_LIT> ; SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant


<s> int unspec_for ( const function_instance & instance ) const { return ( ! instance . type_suffix ( <NUM_LIT> ) . integer_p ? m_unspec_for_fp : instance . type_suffix ( <NUM_LIT> ) . unsigned_p


<s> void print ( DiagnosticPrinter & DP ) const override { DP <<


<s> df_ref src_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_USE ( src_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( src_use ) , src_reg ) ) continue ; struct df_link * link = DF_REF_CHAIN ( src_use ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; rtx and_base = XEXP ( and_operation , <NUM_LIT> ) ; rtx new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn ) ) ; df_insn_rescan ( new_insn ) ; XEXP ( mem , <NUM_LIT> ) = gen_rtx_AND ( GET_MODE ( and_base ) , new_reg , XEXP ( and_operation , <NUM_LIT> ) ) ; SET_SRC ( body ) = src_reg ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan (


<s> bool isImm0_255 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return


<s> static void printRegs ( formatted_raw_ostream & OS , ListSeparator & LS


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; int32_t OffImm = ( int32_t ) MO1 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; O << <STR_LIT> << markup


<s> WasmTM -> setTargetFeatureString ( FeatureStr ) ; for ( auto & F : M ) replaceFeatures ( F , FeatureStr ) ; bool StrippedAtomics = false ; bool StrippedTLS = false ; if ( ! Features [ <STR_LIT> ] ) { StrippedAtomics = stripAtomics ( M ) ; StrippedTLS = stripThreadLocals


<s> unsigned STReg = getSTReg ( FPRegNo ) ; unsigned OldSlot = getSlot ( FPRegNo ) ; unsigned TopReg = Stack [ StackTop - <NUM_LIT> ] ; Stack [ OldSlot ] = TopReg ; RegMap [ TopReg ] = OldSlot ; RegMap [ FPRegNo ] = ~ <NUM_LIT> ; Stack [ -- StackTop ]


<s> assert ( Operation -> getOperand ( <NUM_LIT> ) == Op2 ) ; assert ( Op1 -> getOperand ( <NUM_LIT> ) == Op2 -> getOperand (


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false


<s> SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) ) , VT . getVectorNumElements (


<s> const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( create<ISA_LIT>PrepareScratchRegs ( ) ,


<s> if ( SuperRegSize % <NUM_LIT> == <NUM_LIT> ) { return { <NUM_LIT> , Store ? <STR_LIT> : <STR_LIT> } ; } return { <NUM_LIT> , Store ? <STR_LIT> : <STR_LIT>


<s> return ( TARGET_EXPLICIT_RELOCS && mips_symbolic_constant_p ( x , & symbol_type ) &&


<s> BufferType :: const_iterator end ( ) const { return Buffer . end ( )


<s> Register Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Fs = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; Register Wtemp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * GPRRC = IsFGR64on<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; unsigned MFC1Opc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : ( IsFGR64on<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) ; unsigned FILLOpc = IsFGR64on<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; Register Rtemp = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( MFC1Opc ) , Rtemp ) . addReg ( Fs ) ; BuildMI ( * BB , MI , DL , TII -> get ( FILLOpc ) , Wtemp ) . addReg ( Rtemp ) ; unsigned WPHI = Wtemp ; if ( IsFGR64on<ISA_LIT>32 ) { Register Rtemp2 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Rtemp2 ) . addReg ( Fs ) ; Register Wtemp2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register Wtemp3 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp2 ) . addReg ( Wtemp ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp3 ) . addReg ( Wtemp2 ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; WPHI = Wtemp3


<s> tree arg ; for ( arg = DECL_ARGUMENTS ( current_function_decl ) ; arg ; arg = TREE_CHAIN ( arg ) ) { rtx incoming = DECL_INCOMING_RTL (


<s> LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Dst ) ) ; B . setInstr ( MI ) ; if ( IdxVal -> Value < VecTy . getNumElements ( ) ) B . buildExtract ( Dst , Vec , IdxVal -> Value * EltTy . getSizeInBits ( ) ) ; else B . buildUndef ( Dst ) ; MI . eraseFromParent ( ) ; return


<s> const char * getPassName ( ) const { return <STR_LIT>


<s> MCOperand <ISA_LIT>MCInstLower :: LowerOperand ( const MachineOperand & MO , unsigned offset ) const { MachineOperandType MOTy = MO . getType ( ) ; switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) +


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool isPCRel ) const { unsigned NumBytes = <NUM_LIT> ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetData > ( ) ; AU . addPreserved < MachineFunctionAnalysis >


<s> NOPInsertionPass ( bool is64Bit_ ) : MachineFunctionPass ( ID ) , is64Bit


<s> llvm_unreachable ( <STR_LIT> ) ; return


<s> Asm -> getOrCreateSymbolData ( * Symbol


<s> bool Changed = false ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) if ( I -> hasDelaySlot ( ) ) { MachineBasicBlock :: iterator J = I ; ++ FilledSlots ; Changed = true ; BuildMI ( MBB , ++ J , I -> getDebugLoc ( ) , TII -> get (


<s> return new <ISA_LIT>PassConfig ( * this


<s> EVT IntLoadVT = LoadVT . changeTypeToInteger ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; DAG . ExtractVectorElements ( Result , Elts ) ; for ( SDValue & Elt : Elts ) Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Elt ) ; Result = DAG . getBuildVector ( IntLoadVT , DL , Elts ) ; return DAG . getNode ( <STR_LIT> , DL ,


<s> SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( VecV ) . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> ) return insertHvxElementPred ( VecV , IdxV , ValV , dl , DAG ) ; return insertHvxElementReg ( VecV , IdxV ,


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getELEN ( ) ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return TLI -> isLegalElementTypeForRVV ( DataType ->


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( SDValue Select = pushAddIntoCmovOfConsts ( N , DAG , Subtarget ) ) return Select ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , DL , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , DL , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = combineAddOfPMADDWD ( DAG , Op0 , Op1 , DL , VT ) ) return MAdd ; if ( SDValue V = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op1 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op0 , SExt ) ; } } if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 -> hasOneUse ( ) && <STR_LIT> ( Op0 . getOperand ( <NUM_LIT> ) ) ) { assert ( ! Op0 -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , Op0 -> getVTList ( ) , Op1 , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } return combineAddOrSubToADCOrSBB ( N ,


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( RegisterKind Kind , unsigned Num , SMLoc StartLoc ,


<s> void setPICStyle ( PICStyles :: Style Style ) { PICStyle = Style


<s> bool function_resolver :: scalar_argument_p ( unsigned int i ) { tree type = get_argument_type ( i ) ; return ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P (

type ) || SCALAR_FLOAT_TYPE_P ( type ) ) ;


<s> unsigned getReturnRegsCount ( ) const { return


<s> case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_BARTS : AK = GK_BARTS ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAICOS : AK = GK_CAICOS ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAYMAN : AK = GK_CAYMAN ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_TURKS : AK = GK_TURKS ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX600 : AK = GK_GFX600 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX601 : AK = GK_GFX601 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 : AK = GK_GFX700 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 : AK = GK_GFX701 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 : AK = GK_GFX702 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 : AK = GK_GFX703 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 : AK = GK_GFX704 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 : AK = GK_GFX801 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 : AK = GK_GFX802 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 : AK = GK_GFX803 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 : AK = GK_GFX810 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 : AK = GK_GFX900 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 : AK = GK_GFX902 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 : AK = GK_GFX904 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 : AK = GK_GFX906 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 : AK = GK_GFX908 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX909 : AK


<s> TargetRegistry :: RegisterMCAsmInfo ( T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfoImpl ) ; TargetRegistry :: RegisterELFStreamer ( T , create<ISA_LIT>MCELFStreamer ) ; TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( T


<s> for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) { Changed |= convertToHardwareLoop ( * I ) ; } if ( Changed ) { return Changed ; } CountValue * TripCount = getTripCount ( L ) ; if ( TripCount == <NUM_LIT> ) { return false ; } if ( containsInvalidInstruction ( L ) ) { return false ; } MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( Preheader == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ; MachineBasicBlock * LastMBB = L -> getExitingBlock ( ) ; if ( LastMBB == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ; MachineBasicBlock * LoopStart = L -> getTopBlock ( ) ; if ( L -> getLoopLatch ( ) != LastMBB ) { LoopStart = L -> getLoopLatch ( ) ; if ( ! LastMBB -> isSuccessor ( LoopStart ) ) { return false ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; if ( TripCount -> isReg ( ) ) { MachineFunction * MF = LastMBB -> getParent ( ) ; const TargetRegisterClass * RC = MF -> getRegInfo ( ) . getRegClass ( TripCount -> getReg ( ) ) ; unsigned CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) ) ; if ( TripCount -> isNeg ( ) ) { unsigned CountReg1 = CountReg ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CountReg ) . addReg ( CountReg1 ) ; } BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; } else { assert ( TripCount -> isImm ( ) && <STR_LIT> ) ; int64_t CountImm = TripCount -> getImm ( ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ; } LoopStart -> setHasAddressTaken (


<s> static DecodeStatus DecodeCCRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateReg ( RegNo


<s> vec_double2 vd ; } out ; union { float f [ <NUM_LIT> ] ; vec_float4 vf ; } in ; in . vf = ( vec_float4


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target


<s> emit_cmp_and_jump_insns ( count , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , zerobyte_end_label , very_unlikely ) ; emit_move_insn ( dst_addr , force_operand ( XEXP ( dst , <NUM_LIT> ) , NULL_RTX ) ) ; dst = change_address ( dst , VOIDmode , dst_addr ) ; if ( val != const0_rtx ) { set_mem_size ( dst , <NUM_LIT> ) ; dstp1 = adjust_address ( dst , VOIDmode , <NUM_LIT> ) ; emit_cmp_and_jump_insns ( count , const1_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , onebyte_end_label , very_unlikely ) ; } temp = expand_binop ( mode , add_optab , count , val == const0_rtx ? constm1_rtx : GEN_INT ( - <NUM_LIT> ) , count , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != count ) emit_move_insn ( count , temp ) ; temp = expand_binop ( mode , lshr_optab , count , GEN_INT ( <NUM_LIT> ) , blocks , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , restbyte_end_label ) ; emit_jump ( loop_start_label ) ; if ( val != const0_rtx ) { emit_label ( onebyte_end_label ) ; emit_move_insn ( adjust_address ( dst , QImode , <NUM_LIT> ) , val ) ; emit_jump ( zerobyte_end_label ) ; } emit_label ( loop_start_label ) ; if ( TARGET_Z10 && ( GET_CODE ( len ) != CONST_INT || INTVAL ( len ) > <NUM_LIT> ) ) { rtx prefetch = gen_prefetch ( gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( <NUM_LIT> ) ) , const1_rtx , const0_rtx ) ; emit_insn ( prefetch ) ; PREFETCH_SCHEDULE_BARRIER_P ( prefetch ) = true ; } if ( val == const0_rtx ) emit_insn ( gen_clrmem_short ( dst , GEN_INT ( <NUM_LIT> ) ) ) ; else { emit_move_insn ( adjust_address ( dst , QImode , <NUM_LIT> ) , val ) ; emit_insn ( gen_movmem_short ( dstp1 , dst , GEN_INT ( <NUM_LIT> ) ) ) ; } s390_load_address ( dst_addr , gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( <NUM_LIT>


<s> for ( const Argument & Arg : Fn . args ( ) ) { Type * BaseArgTy = Arg . getType ( ) ; unsigned Align = DL . getABITypeAlignment ( BaseArgTy ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; unsigned AllocSize = DL . getTypeAllocSize ( BaseArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , Align ) + ExplicitOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , Align ) + AllocSize ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , CC , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , CC , ArgVT ) ; if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ; } else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) { MemVT = ArgVT . getScalarType ( ) ; } else if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { unsigned MemoryBits = ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT .


<s> O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( const IntegerType * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { unsigned totalsz = TD -> getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ idx ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } } O <<


<s> RegisterRef Liveness :: getRestrictedRegRef ( NodeAddr < RefNode * > RA ) const { assert ( DFG . IsRef < NodeAttrs :: Use > ( RA


<s> if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsS32 ( ) ) return makeArrayRef ( S32IntRegs ) ; llvm_unreachable ( <STR_LIT>


<s> aarch64_print_operand_address ( STREAM , X ) { \ rtx fun , lr ; \ lr = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; \ fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_NAME ) ; \ emit_library_call

( fun , LCT_NORMAL , VOIDmode , <NUM_LIT> , lr , Pmode ) ; \ }


<s> MOVEMState Temp = State ; if ( State . IsStore ( ) == IsStore && State . GetBase ( ) == Reg && State . Update ( Offset , Mask ) ) { return true ; } else { State = Temp ; State . SetEnd ( MI ) ; Finish ( MBB , State ) ; return ProcessMI ( MBB , MI , State , Mask , Offset , Reg , IsStore ) ; } } else if ( Reg == TRI -> getStackRegister ( ) || Reg == TRI -> getBaseRegister ( ) || Reg == TRI -> getFrameRegister ( * MBB . getParent ( ) ) ) { State . SetBegin ( MI ) ; State . SetBase ( Reg ) ; State . Update ( Offset , Mask ) ; IsStore ? State . SetStore ( ) : State . SetLoad ( ) ; return true


<s> PM . add ( create<ISA_LIT>BundlingPass ( * this ) ) ; return


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( VA . getValVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Register LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) ,


<s> fprintf ( file , <STR_LIT> , ASM_COMMENT_START , cfun -> machine -> var_size ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START , cfun -> machine -> args_size ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START , cfun -> machine -> save_reg_size ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START , cfun -> machine -> initialized ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START , cfun -> machine -> save_regs_offset ) ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START , crtl


<s> unsigned <ISA_LIT>CustomBehaviour :: checkCustomHazard ( ArrayRef < mca :: InstRef

> IssuedInst , const mca :: InstRef & IR ) {


<s> dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( GET_CODE ( dest ) == JUMP_INSN && GET_CODE ( PATTERN ( dest ) ) ==


<s> SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SVOp -> getDebugLoc ( ) ; SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsAllZero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( VT != <STR_LIT> || ! Subtarget -> hasInt256 ( ) || ( ! V2IsUndef && ! V2IsAllZero && ! V1IsAllZero ) ) return SDValue ( ) ; if ( V1IsAllZero &&


<s> StringRef getPassName ( ) const override { return


<s> return mode == DFmode ? loongarch_cost -> fp_mult_df :


<s> static rtx msp430_expand_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; rtx arg1 = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( fcode == MSP430_BUILTIN_DELAY_CYCLES ) return msp430_expand_delay_cycles ( arg1 ) ; if ( ! msp430_is_interrupt_func ( ) ) { error ( <STR_LIT> ) ; return NULL_RTX ; } if ( ! REG_P ( arg1 ) && ! CONSTANT_P ( arg1 ) ) arg1 = force_reg ( mode , arg1 ) ; switch ( fcode ) { case MSP430_BUILTIN_BIC_SR : emit_insn ( gen_bic_SR ( arg1


<s> void ia64_profile_hook ( int labelno ) { rtx label , ip ; if ( NO_PROFILE_COUNTERS ) label = const0_rtx ; else { char buf [ <NUM_LIT> ] ; const char * label_name ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; SYMBOL_REF_FLAGS ( label ) = SYMBOL_FLAG_LOCAL ; } ip = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_ip_value ( ip


<s> SDValue Y = Op . getOperand ( <NUM_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ; SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi , <STR_LIT> ) ; SDValue CmpNum = DAG . getSetCC ( SL , <STR_LIT> , NumHi


<s> return __builtin_mve_vhsubq_uv8hi ( __a ,


<s> SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) )


<s> static bool avr_warn_func_return ( tree decl )


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> static void emitThumbRegPlusImmInReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , unsigned BaseReg , int NumBytes , bool CanChangeCC , const TargetInstrInfo & TII , const <ISA_LIT>RegisterInfo & MRI , DebugLoc dl ) { bool isHigh = ! MRI . isLowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! MRI . isLowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , false , false , true ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addReg ( LdReg , false , false , true ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , LdReg , NumBytes , <STR_LIT> , <NUM_LIT> , & TII , true , dl ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get (


<s> Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if ( restrict_addressing_modes_for_nacl ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList (


<s> return ( VT == <STR_LIT> ) && ( Opc == <STR_LIT>


<s> if ( TRI -> isVGPR ( * MRI , Op0 . getReg ( ) ) ) { Opcode = <STR_LIT> ( Opcode ) ; VcmpMI = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . add ( Op1 ) . add ( Op0 ) ; } else { VcmpMI = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( Op1 ) . addImm ( <NUM_LIT> ) . add ( Op0 ) . addImm ( <NUM_LIT> ) ; } Register VCC = ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * MaskUpdateMI = BuildMI ( MBB , MI , DL , TII -> get ( AndN2Opc ) , LiveMaskReg ) . addReg ( LiveMaskReg ) . addReg ( VCC ) ; MachineInstr * EarlyTermMI = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MachineInstr * ExecMaskMI = BuildMI ( MBB , MI , DL , TII -> get ( AndN2Opc ) , Exec ) . addReg ( Exec ) . addReg ( VCC ) ; assert ( MBB . succ_size ( ) == <NUM_LIT> ) ; MachineInstr * NewTerm = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( * MBB . succ_begin ( ) ) ; LIS -> ReplaceMachineInstrInMaps ( MI , * VcmpMI ) ; MBB . remove (


<s> const char * <ISA_LIT>AsmPrinter :: getPassName (


<s> if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ; return new <ISA_LIT>TargetStreamer (


<s> const int AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( Ty -> isVectorTy ( ) && Ty -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned ProfitableNumElements ; if ( Opcode == Instruction :: Store ) ProfitableNumElements = <NUM_LIT> ; else ProfitableNumElements = <NUM_LIT> ; if ( Ty -> getVectorNumElements ( )


<s> break ; } if ( lFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( ppFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( insn -> mode != MODE_16BIT && isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_ADSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( insn -> mode == MODE_16BIT && insn -> opcodeType == ONEBYTE && insn -> opcode == <NUM_LIT> ) attrMask ^= ATTR_ADSIZE ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT && insn -> vectorExtensionType != TYPE_NO_VEX_XOP ) { if ( ( insn -> vectorExtensionType == TYPE_EVEX && wFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_VEX_3B && wFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) || ( insn -> vectorExtensionType == TYPE_XOP && wFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ) { uint16_t instructionIDWithREXW ; if ( getIDWithAttrMask ( & instructionIDWithREXW , insn , attrMask | ATTR_REXW ) ) { insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return <NUM_LIT> ; } const char * SpecName = GetInstrName ( instructionIDWithREXW , miiArg ) ; if ( ! is64Bit ( SpecName ) ) { insn -> instructionID = instructionIDWithREXW ; insn -> spec = specifierForUID ( instructionIDWithREXW ) ; return <NUM_LIT> ; } } } if ( insn -> opcodeType == ONEBYTE && ( ( insn -> opcode & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_ADSIZE ; if ( insn -> prefixPresent [ <NUM_LIT> ] ) attrMask |= ATTR_OPSIZE ; if ( insn -> mode == MODE_16BIT ) attrMask ^= ATTR_ADSIZE | ATTR_OPSIZE ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; insn -> instructionID = instructionID ; insn -> spec = specifierForUID ( instructionID ) ; return


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction (


<s> static inline bool offset_6bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple


<s> if ( class == PREGS || class == PREGS_CLOBBERED ) return NO_REGS ; if ( class == DREGS || class == DPREGS ) return large_constant_p ? PREGS : NO_REGS ; return PREGS ; } if ( x_class == AREGS ) return class == DREGS || class == AREGS ? NO_REGS : DREGS ; if ( class == AREGS ) { if ( x != const0_rtx && x_class != DREGS ) return DREGS ; else return NO_REGS ; } if ( class == CCREGS && x_class != DREGS ) return DREGS ; if ( x_class == CCREGS && class != DREGS ) return DREGS ; if ( code == MEM ) if ( ! reg_class_subset_p ( class , default_class )


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand


<s> SmallVector < MachineOperand , <NUM_LIT> > AfterOps ; SmallVector < MachineOperand , <NUM_LIT> > ImpOps ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( i >= Index && i < Index + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( Op . isReg ( ) && Op . isImplicit ( ) ) ImpOps . push_back ( Op ) ; else if ( i < Index ) BeforeOps . push_back ( Op ) ; else if ( i > Index ) AfterOps . push_back ( Op ) ; } if ( UnfoldLoad ) { std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; loadRegFromAddr ( MF , Reg , AddrOps , RC , MMOs . first , MMOs . second , NewMIs ) ; if ( UnfoldStore ) { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> + <STR_LIT> ; ++ i ) { MachineOperand & MO = NewMIs [ <NUM_LIT> ] -> getOperand ( i ) ; if ( MO . isReg ( ) ) MO . setIsKill ( false ) ; } } } MachineInstr * DataMI = MF . CreateMachineInstr ( MCID , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , DataMI ) ; if ( FoldedStore ) MIB . addReg ( Reg , RegState :: Define ) ; for ( MachineOperand & BeforeOp : BeforeOps ) MIB . addOperand ( BeforeOp ) ; if ( FoldedLoad ) MIB . addReg ( Reg ) ; for ( MachineOperand & AfterOp : AfterOps ) MIB . addOperand ( AfterOp ) ; for ( MachineOperand & ImpOp : ImpOps ) { MIB . addReg ( ImpOp . getReg ( ) , getDefRegState ( ImpOp . isDef ( ) ) | RegState :: Implicit | getKillRegState ( ImpOp . isKill ( ) ) | getDeadRegState ( ImpOp . isDead ( ) ) | getUndefRegState ( ImpOp . isUndef ( ) ) ) ; } switch ( DataMI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isSigned ) return ~ ( - <NUM_LIT> <<


<s> static inline bool isThumbImm16ShiftedVal (


<s> } if ( fp_plus_const_operand ( x , mode ) ) { rtx op2 = XEXP ( x , <NUM_LIT> ) ; int large_constant_p = ! CONST_7BIT_IMM_P ( INTVAL ( op2 ) ) ; if ( class == PREGS || class == PREGS_CLOBBERED ) return NO_REGS ; if ( class == DREGS || class == DPREGS ) return large_constant_p ? PREGS : NO_REGS ; return PREGS ; } if ( x_class == AREGS ) return class == DREGS || class == AREGS ? NO_REGS : DREGS ; if ( class == AREGS ) { if ( x != const0_rtx && x_class != DREGS ) return DREGS ; else return NO_REGS ; } if ( class == CCREGS && x_class != DREGS ) return DREGS ; if ( x_class == CCREGS && class != DREGS


<s> Ldst . RemoveOperand ( OffPos ) ; Ldst . RemoveOperand ( BasePos ) ; if ( IsStore ) { Src = Ldst . getOperand ( BasePos - <NUM_LIT> ) ; Ldst . RemoveOperand ( BasePos - <NUM_LIT> ) ; } Ldst . setDesc ( AST -> getInstrInfo ( ) -> get ( NewOpcode ) ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( NewBase , true ) ) ; if ( IsStore ) Ldst . addOperand ( Src ) ; Ldst . addOperand ( MachineOperand :: CreateReg ( BaseReg , false )


<s> switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; if ( PPC405_ERRATUM77 ) emit_insn ( gen_memory_barrier ( )


<s> MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + <STR_LIT> ) ; int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset ,


<s> rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( GET_CODE ( op0 ) != CONST_INT || INTVAL ( op0 ) > <NUM_LIT> || INTVAL ( op0 ) < <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx


<s> switch ( BrOpc ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static char templ [ <NUM_LIT> ] ; struct simd_immediate_info info ; bool is_valid = aarch64_simd_valid_immediate ( const_unspec , & info ) ; gcc_assert ( is_valid && info . insn == simd_immediate_info :: PTRUE ) ; char element_char = sizetochar ( GET_MODE_BITSIZE ( info . elt_mode ) ) ; snprintf ( templ , sizeof ( templ ) , <STR_LIT> , element_char , svpattern_token ( info


<s> GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( AllocaUser ) ; if ( ! GEP ) { if ( ! canVectorizeInst ( cast < Instruction > ( AllocaUser ) , Alloca ) ) return false ; WorkList . push_back ( AllocaUser ) ; continue ; } Value * Index = GEPToVectorIndex ( GEP ) ; if ( ! Index ) { DEBUG ( dbgs ( ) << <STR_LIT> << * GEP << '\n' ) ; return false ; } GEPVectorIdx [ GEP ] = Index ; for ( User * GEPUser : AllocaUser -> users ( ) ) { if ( ! canVectorizeInst ( cast < Instruction > ( GEPUser ) , AllocaUser ) ) return false ; WorkList . push_back ( GEPUser ) ; } } VectorType * VectorTy = arrayTypeToVecType ( AllocaTy ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * AllocaTy << <STR_LIT> << * VectorTy << '\n' ) ; for ( Value * V : WorkList ) { Instruction * Inst = cast < Instruction > ( V ) ; IRBuilder < > Builder ( Inst ) ; switch ( Inst ->


<s> emit_jump_insn ( gen_condjump ( condition , true_label ) ) ; emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( true_label ) ; mips_emit_move ( target , value_if_true ) ; emit_label ( done_label ) ; return


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = <STR_LIT> ( TM . getTargetTriple ( ) , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isABI_N32 ( ) || isABI_N64 ( ) ) stackAlignment = <NUM_LIT> ; else { assert ( isABI_O32 ( ) && <STR_LIT> ) ; stackAlignment =


<s> Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . parseAbsoluteExpression ( Value ) ) return nullptr ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } SMLoc MemEnd = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( is64BitMode ( ) || ( BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> ) ) && BaseReg != <STR_LIT> ) { Error ( BaseLoc , <STR_LIT> ) ; return nullptr ; } if ( BaseReg == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { Error ( IndexLoc , <STR_LIT> ) ; return nullptr ; } StringRef ErrMsg ; if ( CheckBaseRegAndIndexReg ( BaseReg , IndexReg , ErrMsg ) ) { Error ( BaseLoc , ErrMsg ) ; return nullptr ; } if ( SegReg || BaseReg || IndexReg ) return <STR_LIT> ( SegReg , Disp , BaseReg , IndexReg , Scale , MemStart , MemEnd ) ; return <STR_LIT> ( Disp , MemStart , MemEnd


<s> unsigned RetOpcode = MI -> getOpcode ( ) ; isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; isTrap = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isTrap && STI . hasV5TOps ( ) ) { if ( MBB . succ_empty ( ) ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; std :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) ,

<STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return createMachOStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll ) ; if ( TheTriple . isOSWindows ( ) ) return createWinCOFFStreamer ( Ctx , MAB , * _Emitter ,


<s> int nds32_can_use_return_insn ( void ) { int sp_adjust ; if ( ! reload_completed ) return <NUM_LIT> ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return <NUM_LIT> ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == <NUM_LIT>


<s> if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI , false


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo (


<s> static __inline qword si_nor ( qword a , qword b ) { return ( ( qword ) ( vec_nor ( ( vec_uchar16 ) ( a )


<s> putc ( '$' , file ) ; assemble_name ( file , fnname ) ; fputs ( <STR_LIT> , file ) ; } } if ( TARGET_ABI_OPEN_VMS && ! TREE_PUBLIC ( decl ) && DECL_CONTEXT ( decl ) && ! TYPE_P ( DECL_CONTEXT ( decl ) ) && TREE_CODE ( DECL_CONTEXT ( decl ) ) != TRANSLATION_UNIT_DECL ) { strcpy ( tramp_label , fnname ) ; strcat ( tramp_label , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( file , tramp_label ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } strcpy ( entry_label , fnname ) ; if ( TARGET_ABI_OPEN_VMS ) strcat ( entry_label , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( file , entry_label ) ; inside_function = TRUE ; if ( TARGET_ABI_OPEN_VMS ) fprintf ( file , <STR_LIT> , vms_base_regno ) ; if ( TARGET_ABI_OSF && TARGET_IEEE_CONFORMANT && ! flag_inhibit_size_directive ) { fputs ( <STR_LIT> , file ) ; } alpha_auto_offset = - frame_size + crtl -> args . pretend_args_size ; alpha_arg_offset = - frame_size + <NUM_LIT> ; if ( TARGET_ABI_OPEN_VMS ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , vms_unwind_regno , frame_size >= max_frame_size ? <NUM_LIT> : frame_size , reg_offset ) ; else if ( ! flag_inhibit_size_directive ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ( frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) , frame_size >= max_frame_size ? <NUM_LIT> : frame_size , crtl -> args . pretend_args_size ) ; if ( TARGET_ABI_OPEN_VMS ) { if ( imask ) fprintf ( file , <STR_LIT> , imask & ~ ( <NUM_LIT> << REG_RA ) ) ; if ( fmask ) fprintf ( file , <STR_LIT> , fmask ) ; if ( alpha_procedure_type == PT_REGISTER ) fprintf ( file , <STR_LIT> , vms_save_fp_regno ) ; } else if ( ! flag_inhibit_size_directive )


<s> bool <ISA_LIT>TargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type ,


<s> case Match_MnemonicFail : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = Loc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) .


<s> for ( auto Pos = InsertPos , E = MBB -> begin ( ) ; Pos != E ; -- Pos ) assert ( ! AfterSet . count ( & * std :: prev ( Pos ) ) ) ; break ; } -- InsertPos ; } return InsertPos


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( N ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Alignment , AM . Disp , <NUM_LIT> ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , SDLoc ( N ) , <STR_LIT> ) ; return


<s> bool hasV65TOpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) == <STR_LIT> ::


<s> const DataLayout * getDataLayout ( )


<s> static SDValue performXorCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; return performIntegerAbsCombine ( N , DAG


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return


<s> unsigned Opc ; unsigned LSB , MSB ; SDValue Opd0 , Opd1 ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; APInt NUsefulBits ; getUsefulBits ( SDValue ( N , <NUM_LIT> ) , NUsefulBits ) ; if ( ! NUsefulBits ) return CurDAG -> SelectNodeTo ( N , TargetOpcode :: IMPLICIT_DEF , VT ) ; if ( ! isBitfieldInsertOpFromOr ( N , Opc , Opd0 , Opd1 , LSB , MSB ,

NUsefulBits , CurDAG ) ) return nullptr ;


<s> static bool selectCCOpsAreFMaxCompatible ( SDValue Cmp , SDValue Result ) { if ( Cmp == Result ) return true ; ConstantFPSDNode * CCmp = dyn_cast < ConstantFPSDNode > ( Cmp ) ; ConstantFPSDNode * CResult = dyn_cast < ConstantFPSDNode > ( Result ) ; if ( CCmp && CResult && Cmp . getValueType ( ) == <STR_LIT> && Result . getValueType ( ) == <STR_LIT> ) { bool Lossy ; APFloat CmpVal = CCmp -> getValueAPF ( ) ; CmpVal . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Lossy ) ; return CResult -> getValueAPF ( ) . bitwiseIsEqual ( CmpVal ) ; } return Result -> getOpcode ( ) == <STR_LIT> && Result -> getOperand ( <NUM_LIT> )