<s> static void processInstr ( MachineInstr & MI , MachineIRBuilder & MIB , MachineRegisterInfo & MRI , <ISA_LIT>GlobalRegistry * GR ) { unsigned Opc = MI . getOpcode ( ) ; assert ( MI . getNumDefs ( ) > <NUM_LIT> && MRI . hasOneUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; MachineInstr & AssignTypeInst = * ( MRI . use_instr_begin ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; auto NewReg = createNewIdReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Opc , MRI , * GR ) . first ; AssignTypeInst . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MIB . setInsertPt ( * MI . getParent ( ) , ( MI . getNextNode ( ) ? MI . getNextNode ( ) -> getIterator ( ) : MI . getParent ( ) -> end ( ) ) ) ; for ( auto & Op : MI . operands ( ) ) { if ( ! Op . isReg ( ) || Op . isDef ( ) ) continue ; auto IdOpInfo = createNewIdReg ( Op . getReg ( ) , Opc , MRI , * GR ) ; MIB . buildInstr ( IdOpInfo . second ) . addDef ( IdOpInfo . first ) . addUse ( Op . getReg ( ) ) ; Op . setReg ( IdOpInfo .


<s> default : break ; case Instruction :: Alloca : { assert ( false && <STR_LIT> ) ; return false ; } } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( Obj ) ) { ( void ) GV ; return false ; } Reg = getRegForValue ( Obj ) ; if ( Reg == <NUM_LIT> ) return false ; if ( Offset != <NUM_LIT> ) { <STR_LIT> Pred = <STR_LIT> ; unsigned PredReg = <NUM_LIT> ; if ( ! isThumb ) emit<ISA_LIT>RegPlusImmediate ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , Reg , Reg , Offset , Pred , PredReg , static_cast < const <ISA_LIT>BaseInstrInfo & > ( TII ) ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , Reg , Reg , Offset , Pred , PredReg , static_cast


<s> bool SelectAddrIdx ( SDValue Op , SDValue N , SDValue & Base


<s> return true ; } ; auto MatchShift = [ & ] ( int Shift ) { for ( int i = <NUM_LIT> ; i != Size - Shift ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != Shift + i ) return false ; return true ; } ; for ( int Shift = <NUM_LIT> ; Shift != Size ; ++ Shift ) if ( CheckUndefs ( Shift ) && MatchShift ( Shift ) ) return Shift ; return -


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI ) { MCAsmParserExtension :: Initialize ( Parser ) ; MCStreamer & S = getParser (


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _MM_SET_ROUNDING_MODE ( unsigned int __mode ) { _mm_setcsr ( ( _mm_getcsr ( ) & ~


<s> break ; } case <STR_LIT> : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( <STR_LIT> ) ) { LHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; SelectVT = <STR_LIT> ; } SDValue NewSelect = DAG . getNode ( <STR_LIT> , SL , SelectVT , N -> getOperand ( <NUM_LIT> ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( <STR_LIT> ,


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI

, const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {


<s> static bool parseTexFail ( SDValue TexFailCtrl , SelectionDAG & DAG , SDValue * TFE , SDValue * LWE , bool & IsTexFail ) { auto TexFailCtrlConst = cast < ConstantSDNode > ( TexFailCtrl . getNode ( ) ) ; uint64_t Value = TexFailCtrlConst -> getZExtValue


<s> static void cris_print_operand_address ( FILE * file , rtx x ) { putc ( '[' , file ) ; if ( CONSTANT_ADDRESS_P ( x ) ) cris_output_addr_const ( file , x ) ; else if ( cris_base_or_autoincr_p ( x , true ) ) cris_print_base ( x , file ) ; else if ( GET_CODE ( x ) == PLUS ) { rtx x1 , x2 ; x1 = XEXP ( x , <NUM_LIT> ) ; x2 = XEXP ( x , <NUM_LIT> ) ; if ( cris_base_p ( x1 , true ) ) { cris_print_base ( x1 , file ) ; cris_print_index ( x2 , file ) ; } else if ( cris_base_p ( x2 , true ) ) { cris_print_base ( x2 , file ) ; cris_print_index ( x1 , file ) ; } else LOSE_AND_RETURN ( <STR_LIT> , x ) ; } else if ( MEM_P ( x ) ) { putc ( '[' , file ) ; cris_print_base ( XEXP ( x , <NUM_LIT> )


<s> unsigned Chan = getReassignedChan ( RemapChan , Swizzle ) ; MachineInstr * Tmp = BuildMI ( MBB , Pos , DL , TII -> get ( AMDGPU :: INSERT_SUBREG ) , DstReg ) . addReg ( SrcVec ) . addReg ( SubReg ) . addImm ( Chan ) ; UpdatedRegToChan [ SubReg ] = Chan ; std :: vector < unsigned > :: iterator ChanPos = std :: find ( UpdatedUndef . begin ( ) , UpdatedUndef . end ( ) , Chan ) ; if ( ChanPos != UpdatedUndef . end ( ) ) UpdatedUndef . erase ( ChanPos ) ; assert ( std :: find ( UpdatedUndef . begin ( ) , UpdatedUndef . end ( ) , Chan ) == UpdatedUndef . end ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Tmp -> dump ( ) ; ) ; ( void ) Tmp ; SrcVec = DstReg ; } Pos = BuildMI ( MBB , Pos , DL , TII -> get ( AMDGPU :: COPY ) , Reg ) . addReg ( SrcVec ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Pos -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( MachineRegisterInfo :: use_instr_iterator It = MRI -> use_instr_begin ( Reg ) , E = MRI -> use_instr_end ( ) ; It


<s> <ISA_LIT>Type * <ISA_LIT>GlobalRegistry :: getOrCreate<ISA_LIT>VectorType ( <ISA_LIT>Type * BaseType , unsigned NumElements , MachineInstr & I , const <ISA_LIT>InstrInfo & TII ) { Type * LLVMTy = FixedVectorType :: get ( const_cast < Type * > ( getTypeFor<ISA_LIT>Type ( BaseType ) )


<s> if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , false ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < Register , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands ( ) ) { unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; Flags . setOrigAlign ( DL . getABITypeAlign


<s> if ( ! IsData ) return Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; bool IsWrite = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Code = IsWrite ? <STR_LIT> : <STR_LIT> ; auto * Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Code , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Node -> getVTList ( ) , Ops , Node ->

getMemoryVT ( ) , Node -> getMemOperand ( ) ) ;


<s> SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getScalarValueSizeInBits ( ) != <NUM_LIT> ) { APInt DemandedBits ( APInt :: getSignMask ( VT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedBits , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewMask = TLI . SimplifyMultipleUseDemandedBits ( Mask , DemandedBits , DAG ) ) return DAG . getMaskedStore ( Mst -> getChain ( ) , SDLoc ( N ) , Mst -> getValue ( ) , Mst -> getBasePtr ( ) , Mst ->

getOffset ( ) , NewMask , Mst -> getMemoryVT ( ) , Mst -> getMemOperand ( ) , Mst -> getAddressingMode ( ) ) ;


<s> default : return SDValue ( ) ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : return SDValue ( ) ; } SDValue Result = DAG . getConstant ( SplatValue , ViaVecTy ) ; if ( ViaVecTy != ResTy ) Result = DAG . getNode ( <STR_LIT> , SDLoc ( Node ) , ResTy , Result ) ; return Result ; } else if ( isSplatVector ( Node ) ) return Op ; else if ( ! isConstantOrUndefBUILD_VECTOR ( Node ) ) { EVT ResTy = Node -> getValueType ( <NUM_LIT> ) ; assert ( ResTy . isVector ( ) ) ; unsigned NumElts = ResTy . getVectorNumElements ( ) ; SDValue Vector = DAG . getUNDEF ( ResTy ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { Vector = DAG . getNode ( <STR_LIT> , DL , ResTy , Vector , Node -> getOperand ( i ) , DAG . getConstant ( i , <STR_LIT> ) ) ; } return


<s> unsigned <ISA_LIT>16InstrInfo :: whichOp8u_or_16simm ( unsigned shortOp , unsigned longOp , int64_t Imm ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return


<s> BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations (


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : if ( ! Check ( S , MCDisassembler :: Fail ) ) return MCDisassembler :: Fail ; } if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: CreateImm ( fieldFromInstruction32 ( Insn , <NUM_LIT> ,


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) )


<s> DEBUG ( LRMI . dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( ESMI . dump ( ) ) ; if ( isLate && isEarly ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return


<s> PM . add ( create<ISA_LIT>ISelDag ( * this , OptLevel


<s> case E_HImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; case E_SImode : output_asm_insn ( <STR_LIT> , exops [ <NUM_LIT> ] ) ; output_asm_insn ( <STR_LIT> , exops [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } n -- ; } for ( i = <NUM_LIT> ; i < n ; i ++ ) { switch ( code ) { case LSHIFTRT : case ASHIFTRT : switch ( m ) { case E_QImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; case E_HImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; case E_SImode : output_asm_insn ( <STR_LIT> , exops [ <NUM_LIT> ] ) ; output_asm_insn ( <STR_LIT> , exops [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } break ; case ASHIFT : switch ( m ) { case E_QImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; case E_HImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; case E_SImode : output_asm_insn ( <STR_LIT> , exops [ <NUM_LIT> ] ) ; output_asm_insn ( <STR_LIT> , exops [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } break ; } } if ( ! small ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , lb ) ; } return


<s> unsigned <ISA_LIT>AsmBackend :: getMinimumNopSize ( ) const { return


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false


<s> } else if ( GET_CODE ( src ) != PLUS || ! REG_P ( XEXP ( src , <NUM_LIT> ) ) || REGNO ( XEXP ( src , <NUM_LIT> ) ) != REG_SP || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != CONST_INT || INTVAL ( XEXP ( src , <NUM_LIT> ) ) != ( i - <NUM_LIT> ) * <NUM_LIT> ) return <NUM_LIT> ; regno = REGNO ( dest ) ; if ( group == <NUM_LIT> ) { if ( regno == REG_R7 ) { group = <NUM_LIT> ; lastdreg = <NUM_LIT> ; } else if ( regno != REG_P0 + lastpreg - <NUM_LIT> ) return <NUM_LIT> ; else lastpreg -- ; } else if ( group == <NUM_LIT> ) { if ( regno != REG_R0 + lastdreg - <NUM_LIT> ) return <NUM_LIT> ; else lastdreg -- ; } } first_dreg_to_save = lastdreg ; first_preg_to_save = lastpreg ; n_regs_to_save = <NUM_LIT> - first_dreg_to_save + <NUM_LIT> - first_preg_to_save ; return <NUM_LIT>


<s> } if ( TARGET_HPUX_UNWIND_LIBRARY ) { rtx addr = gen_rtx_PLUS ( word_mode , stack_pointer_rtx , GEN_INT ( TARGET_64BIT ? - <NUM_LIT> : - <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( word_mode , addr ) , hard_frame_pointer_rtx ) ; } else emit_insn ( gen_blockage ( ) ) ; } else { if ( VAL_14_BITS_P ( actual_fsize ) && local_fsize == <NUM_LIT> ) merge_sp_adjust_with_store = <NUM_LIT> ; else set_reg_plus_d ( STACK_POINTER_REGNUM , STACK_POINTER_REGNUM , actual_fsize , <NUM_LIT> ) ; } } if ( frame_pointer_needed ) { offset = local_fsize ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i , regno ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; store_reg ( regno , offset , HARD_FRAME_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) { store_reg ( i , offset , HARD_FRAME_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } gr_saved ++ ; } else { offset = local_fsize - actual_fsize ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i , regno ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , regno , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( regno , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_regs [ i ] ) { if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , i , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } if ( merge_sp_adjust_with_store ) set_reg_plus_d ( STACK_POINTER_REGNUM , STACK_POINTER_REGNUM , actual_fsize , <NUM_LIT> ) ; } if ( flag_pic && actual_fsize != <NUM_LIT> && ! TARGET_64BIT ) { rtx addr = gen_rtx_PLUS ( word_mode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( word_mode , addr ) , pic_offset_table_rtx ) ; } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { rtx base ; if ( frame_pointer_needed ) { set_reg_plus_d ( <NUM_LIT> , HARD_FRAME_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = hard_frame_pointer_rtx ; } else { set_reg_plus_d ( <NUM_LIT> , STACK_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = stack_pointer_rtx ; } for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) { if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { rtx addr , reg ; rtx_insn * insn ; addr = gen_rtx_MEM ( DFmode , gen_rtx_POST_INC


<s> return <STR_LIT> ; case CmpInst :: ICMP_SLE : return <STR_LIT> ; case CmpInst :: ICMP_SLT : return <STR_LIT> ; case CmpInst :: ICMP_UGE : return <STR_LIT> ; case CmpInst :: ICMP_UGT : return <STR_LIT> ; case CmpInst :: ICMP_ULE : return <STR_LIT> ; case CmpInst


<s> void <ISA_LIT>SEInstrInfo :: expandEhReturn ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned ADDU = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned RA = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned T9 = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned TargetReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( ADDU ) , T9 ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( ADDU ) , RA ) . addReg ( TargetReg ) . addReg ( ZERO ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TM . getInstrInfo ( ) -> get ( ADDU ) ,

SP ) . addReg ( SP ) . addReg ( OffsetReg ) ;


<s> initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; ParseSubtargetFeatures ( CPU , FS ) ; return *


<s> Inst . addOperand ( MCOperand :: createImm ( CE -> getValue


<s> SMLoc End = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res , * RHS = nullptr ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( Lexer . getKind ( ) != AsmToken :: Identifier ) return nullptr ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return nullptr ; if ( Identifier . equals_lower ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ; else if ( Identifier . equals_lower ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { if ( Lexer . getKind ( ) != AsmToken :: LParen ) { Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Lexer . Lex ( ) ; if ( Parser . parseIdentifier ( Identifier ) ) return nullptr ; } if ( Lexer . getKind ( ) == AsmToken :: Plus && Parser . parseExpression ( RHS ) ) return nullptr ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { if ( Lexer . getKind ( ) != AsmToken :: RParen ) { Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Lexer . Lex ( ) ; } End = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( )


<s> FOR_ALL_BB_FN ( bb , fn ) { regno_map *


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter (


<s> fprintf ( file , <STR_LIT> , is_public ? <STR_LIT> : <STR_LIT> ) ; assemble_name_raw ( file , name ) ; fputc ( '\n' , file ) ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; int sz = int_size_in_bytes (


<s> PredicateOp getPredicate ( ) const { assert ( isPredicate ( )


<s> if ( Register MOReg = MO . getReg ( ) ) { if ( TRI -> regsOverlap ( MOReg , Reg ) ) { if ( MO . isUse ( ) ) Ref . Use = true ; else if ( MO . isDef ( ) ) Ref . Def = true ; } } } } return Ref


<s> if ( NumElems != <NUM_LIT> ) return false ; return isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual (

N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) ;


<s> for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) ArgTys . push_back ( CI -> getArgOperand ( I ) -> getType ( ) ) ; ArgTys . push_back ( PtrTy ) ; Name = Name + <STR_LIT> + std :: to_string ( Size ) ; auto * FTy = FunctionType :: get ( Callee -> getReturnType ( ) , ArrayRef < Type * > ( ArgTys ) , false ) ; <ISA_LIT>LibFunc NewLibFunc ( Name , FTy ) ; FunctionCallee F = <ISA_LIT>LibFunc :: getOrInsertFunction ( M , NewLibFunc ) ; if ( ! F ) return false ; auto * BCast = B . CreatePointerCast ( PtrArg , PtrTy ) ; SmallVector < Value * , <NUM_LIT> > Args ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) Args . push_back ( CI -> getArgOperand ( I ) ) ; Args . push_back ( BCast ) ; auto * NCI = B . CreateCall ( F , Args ) ; NCI -> setAttributes ( CI -> getAttributes ( ) ) ; CI -> replaceAllUsesWith ( NCI ) ; CI -> dropAllReferences ( ) ; CI -> eraseFromParent


<s> if ( x > <NUM_LIT> ) return __clz_tab [ x >> <NUM_LIT> ] + <NUM_LIT> ; return __clz_tab [ x


<s> SDValue getAddrGlobalLargeGOT ( NodeTy * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned HiFlag , unsigned LoFlag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , HiFlag ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , Ty , Hi , getGlobalReg


<s> bool alpha_const_double_ok_for_letter_p ( rtx value , int c ) { switch ( c ) { case 'G' : return ( GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_FLOAT && value == CONST0_RTX ( GET_MODE ( value ) ) ) ; case 'H' : return ( GET_MODE ( value ) == VOIDmode && zap_mask ( CONST_DOUBLE_LOW ( value ) ) && zap_mask ( CONST_DOUBLE_HIGH ( value ) ) ) ; default : return false


<s> uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; assert ( Binary < UINT8_MAX && <STR_LIT> ) ; OS << uint8_t ( Binary ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) encodeULEB128 ( MI . getNumOperands ( ) - <NUM_LIT> , OS ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; ++ i ) { const MCOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { } else if ( MO . isImm ( ) ) { if ( i < Desc . getNumOperands ( ) ) { assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ i ] ; if ( Info . OperandType == <STR_LIT> ) { encodeSLEB128 ( int32_t ( MO . getImm ( ) ) , OS ) ; } else if ( Info . OperandType == <STR_LIT> ) { encodeSLEB128 ( int64_t ( MO . getImm ( ) ) , OS ) ; } else if ( Info . OperandType == <STR_LIT> ) { Fixups . push_back ( MCFixup :: create ( OS . tell ( ) - Start , MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; encodeULEB128 ( uint64_t ( MO . getImm


<s> bool mayNeedRelaxation ( const MCInst & Inst )


<s> if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_sse = true ; cum -> warn_mmx = true ; cum -> maybe_vaarg = false ; if ( fntype && ! TARGET_64BIT ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) { cum -> nregs = <NUM_LIT> ; cum -> fastcall = <NUM_LIT> ; } else cum -> nregs = ix86_function_regparm ( fntype , fndecl ) ; } cum -> float_in_sse = ix86_function_sseregparm ( fntype , fndecl ) ; if ( cum -> nregs || cum -> mmx_nregs || cum -> sse_nregs ) { for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : <NUM_LIT> ; param != <NUM_LIT> ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == <NUM_LIT> && TREE_VALUE ( param ) != void_type_node ) { if ( ! TARGET_64BIT


<s> static unsigned getFixupKindNumBytes ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : case FK_SecRel_2 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatAtomic ( SDNode * N , SDValue Addr , SDValue & VAddr , SDValue


<s> assert ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; case <NUM_LIT> : if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits | <NUM_LIT> , <STR_LIT> ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits | <NUM_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : { uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) Val |= BitMask ; else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) return SDValue ( ) ; BitMask <<= <NUM_LIT> ; } return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } default : llvm_unreachable ( <STR_LIT> )


<s> return MI . isCall ( ) || ( ! MI . isPseudo ( ) && ! MI . isMetaInstruction (


<s> if ( decl ) sorry_at ( DECL_SOURCE_LOCATION (


<s> MachineRelocation MR = Indirect ? MachineRelocation :: getIndirectSymbol ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , MayNeedFarStub ) : MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , GV , ACPV , MayNeedFarStub ) ; MCE . addRelocation ( MR


<s> if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ; } return false


<s> if ( <STR_LIT> ( Mask . getNode ( ) ) ) return Pg ; auto Op1 = convertToScalableVector ( DAG , ContainerVT , Mask ) ; auto Op2 = DAG . getConstant (


<s> if ( BinOp == <STR_LIT> ) { CmpC = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { uint64_t NumElts = MaskSrcVT . getVectorNumElements ( ) ; assert ( NumElts <= <NUM_LIT> && <STR_LIT> ) ; CmpC = DAG . getConstant ( ( <NUM_LIT> << NumElts ) - <NUM_LIT> , DL , <STR_LIT> ) ; CondCode = <STR_LIT> :: SETEQ ; } SDValue BitcastLogicOp = DAG . getBitcast ( MaskSrcVT , Match ) ; SDValue Movmsk = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitcastLogicOp ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetccVT = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Setcc = DAG . getSetCC ( DL , SetccVT , Movmsk , CmpC , CondCode ) ; SDValue Zext = DAG . getZExtOrTrunc ( Setcc , DL , ExtractVT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , ExtractVT ) ; return DAG . getNode ( <STR_LIT> , DL , ExtractVT , Zero


<s> static void printSSEAVXCC ( int64_t Imm , raw_ostream & O ) { switch ( Imm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> return ( __m128d ) __builtin_ia32_cmpltsd ( ( __v2df )


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return


<s> bool <ISA_LIT>CallLowering :: enableBigEndian


<s> static int frv_io_handle_use_1 ( rtx * x , void * data ) { HARD_REG_SET * set = data ; unsigned int regno ; if ( REG_P ( * x ) ) FOR_EACH_REGNO ( regno , * x )


<s> return ( __m512i ) __builtin_ia32_pmovsxbw512_mask ( ( __v32qi ) __A , (


<s> if ( cl == A_REGS ) return NONPREDICATE_A_REGS ; if ( cl == B_REGS ) return NONPREDICATE_B_REGS ; if ( cl == ALL_REGS || cl == GENERAL_REGS ) return NONPREDICATE_REGS ; return


<s> return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc ( ) ,


<s> return ! ( TARGET_HITACHI || ca -> renesas_abi ) && !


<s> switch ( mode ) { case CCmode : return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V ; case CCZNCmode : return CC_FLAG_Z |


<s> if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; RC = TRI -> getSubRegClass ( RC , MO . getSubReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass (


<s> addPass ( create<ISA_LIT>ExpandAtomicPseudoPass


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( TheThumbTarget ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target


<s> void addAFGR64AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getAFGR64Reg


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII


<s> void R600MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { if ( isTexOp ( MI . getOpcode ( ) ) ) { EmitTexInstr ( MI , Fixups , OS ) ; } else if ( isFCOp ( MI . getOpcode ( ) ) ) { EmitFCInstr ( MI , OS ) ; } else if ( MI . getOpcode ( ) == AMDGPU :: RETURN || MI . getOpcode ( ) == AMDGPU :: BUNDLE || MI . getOpcode ( ) == AMDGPU :: KILL ) { return ; } else { switch ( MI . getOpcode ( ) ) { case AMDGPU :: RAT_WRITE_CACHELESS_32_eg : case AMDGPU :: RAT_WRITE_CACHELESS_128_eg : { uint64_t inst = getBinaryCodeForInstr ( MI , Fixups ) ; EmitByte ( INSTR_NATIVE , OS ) ; Emit ( inst , OS ) ; break ; } case AMDGPU :: CONSTANT_LOAD_eg : case AMDGPU :: VTX_READ_PARAM_8_eg : case AMDGPU :: VTX_READ_PARAM_16_eg : case AMDGPU :: VTX_READ_PARAM_32_eg : case AMDGPU :: VTX_READ_GLOBAL_8_eg : case AMDGPU :: VTX_READ_GLOBAL_32_eg : case AMDGPU :: VTX_READ_GLOBAL_128_eg : { uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups ) ; uint32_t InstWord2 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; EmitByte ( INSTR_VTX , OS ) ; Emit ( InstWord01 , OS ) ; Emit ( InstWord2 , OS ) ; break ; } case AMDGPU :: EG_ExportSwz : case AMDGPU :: R600_ExportSwz : case AMDGPU ::


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( skipFunction ( mf . getFunction ( ) ) ) return false ; MRI = & mf . getRegInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : mf ) if ( processMachineBasicBlock ( & MBB


<s> if ( Size <= <NUM_LIT> ) return Cost ; Cost . first += ( Size + <NUM_LIT> ) / <NUM_LIT> ; return


<s> if ( ( cond == LT || cond == GE ) && target_mode == cmp_mode && cmp_op2 == CONST0_RTX ( cmp_mode ) && op == CONST0_RTX ( target_mode ) && s390_vector_mode_supported_p ( target_mode ) && GET_MODE_CLASS ( target_mode ) == MODE_VECTOR_INT ) { rtx negop = ( cond == LT ) ? then : els ; int shift = GET_MODE_BITSIZE ( GET_MODE_INNER ( target_mode ) ) - <NUM_LIT> ; if ( negop == CONST1_RTX ( target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , LSHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } else if ( all_ones_operand ( negop , target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target ,


<s> gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= CSKY_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( <STR_LIT> , attr


<s> } HeadCond . clear ( ) ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; if ( TII -> analyzeBranch ( * Head , TBB , FBB , HeadCond ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( ! TBB || HeadCond . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( ! parseCond ( HeadCond , HeadCmpBBCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( TBB != CmpBB ) { assert ( TBB == Tail && <STR_LIT> ) ; HeadCmpBBCC = <STR_LIT> ( HeadCmpBBCC ) ; } CmpBBCond . clear ( ) ; TBB = FBB = nullptr ; if ( TII -> analyzeBranch ( * CmpBB , TBB , FBB , CmpBBCond ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( ! TBB || CmpBBCond . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( ! parseCond ( CmpBBCond , CmpBBTailCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( TBB != Tail ) CmpBBTailCC = <STR_LIT> ( CmpBBTailCC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmpBBCC ) << <STR_LIT> << <STR_LIT> ( CmpBBTailCC ) << '\n' ) ; CmpMI = findConvertibleCompare ( CmpBB ) ; if ( ! CmpMI ) return false ; if ( ! canSpeculateInstrs ( CmpBB , CmpMI ) ) { ++ NumSpeculateRejs ; return false


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> static inline unsigned getAM3IBit ( uint32_t insn ) { return ( insn >> <STR_LIT>


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName ,


<s> const <ISA_LIT>Subtarget & Subtarget = * static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ; if ( ! Subtarget . isCheri ( ) )


<s> bool isMemThumbSPI ( ) const { if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . BaseRegNum != <STR_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm


<s> auto CCNode = cast < ConstantSDNode > ( CMOV -> getOperand ( <NUM_LIT> ) ) ; auto CC = CCNode -> getAPIntValue ( ) . getLimitedValue ( ) ; SDValue CmpZ = CMOV -> getOperand ( <NUM_LIT> ) ; assert ( CmpZ -> getOpcode ( ) == <STR_LIT> ) ; SDValue And = CmpZ -> getOperand ( <NUM_LIT> ) ; if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * AndC = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC || ! AndC -> getAPIntValue ( ) . isPowerOf2 ( ) ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; APInt KnownZero , KnownOne ; computeKnownBits ( DAG , Y , KnownZero , KnownOne ) ; if ( ( OrCI & KnownZero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> getAPIntValue ( ) . logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl , VT ) ) ; } for ( unsigned BitInY = <NUM_LIT> , NumActiveBits =


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT>


<s> return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( C . CCValid , DL , <STR_LIT> ) , DAG

. getTargetConstant ( C . CCMask , DL , <STR_LIT> ) , Dest , CCReg ) ;


<s> unsigned getWarning ( ) { getErrInfo ( ) ; return CrntErrInfo . s .


<s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Src = convertToScalableVector ( ContainerVT , Src , DAG , Subtarget ) ; } SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SplatOne = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatOne ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , SplatZero ) ; if ( VecVT . isScalableVector ( ) ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ; return DAG . getSetCC ( DL , MaskVT , Trunc


<s> TII = STI . getInstrInfo ( ) ; for ( Block & MBB : MF ) { bool BlockModified = runOnBasicBlock ( MBB ) ; Modified |= BlockModified ; } return


<s> case VK_<ISA_LIT>_PC22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_PC10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_WPLT30 : closeParen = false ; break ; case VK_Sparc_R_DI<ISA_LIT>32 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_GD_CALL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_CALL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_HIX22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_LOX10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_LD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_LDX : OS <<


addRequired < AAResultsWrapperPass > ( ) ;


<s> void WaitcntBrackets :: simplifyWaitcnt ( InstCounterType T


<s> unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; struct spu_builtin_description * d ; if ( fcode < NUM_SPU_BUILTINS ) { d = & spu_builtins [ fcode


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return create<ISA_LIT>ELFObjectWriter ( OSABI


<s> addr = memory_address ( Pmode , addr ) ; retaddr = gen_reg_rtx ( Pmode ) ; emit_move_insn ( retaddr , gen_rtx_MEM ( Pmode , addr ) ) ; } result = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_fix_return_addr ( result , retaddr ) ) ; return


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; int64_t Imm ; if ( CI -> isNegative ( ) ) Imm = CI -> getSExtValue ( ) ; else Imm = CI


<s> bool OtherUsers = false , KillsAddendSrc = false ; for ( auto J = std :: prev ( I ) , JE = MachineBasicBlock :: iterator ( AddendMI ) ; J != JE ; -- J ) { if ( J -> readsVirtualRegister ( AddendMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { OtherUsers = true ; break ; } if ( J -> modifiesRegister ( AddendSrcReg , TRI ) || J -> killsRegister ( AddendSrcReg , TRI ) ) { KillsAddendSrc = true ; break ; } } if ( OtherUsers || KillsAddendSrc ) continue ; Register OldFMAReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned KilledProdOp = <NUM_LIT> , OtherProdOp = <NUM_LIT> ; Register Reg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg3 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LIS -> getInterval ( Reg2 ) . Query ( FMAIdx ) . isKill ( ) && Reg2 != OldFMAReg ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } else if ( LIS -> getInterval ( Reg3 ) . Query ( FMAIdx ) . isKill ( ) && Reg3 != OldFMAReg ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } if ( ! KilledProdOp ) continue ; if ( Register :: isVirtualRegister ( AddendSrcReg ) && ! LIS -> getInterval ( AddendSrcReg ) . liveAt ( FMAIdx ) ) continue ; Register KilledProdReg = MI . getOperand ( KilledProdOp ) . getReg ( ) ; Register OtherProdReg = MI . getOperand ( OtherProdOp ) . getReg ( ) ; unsigned AddSubReg = AddendMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned KilledProdSubReg = MI . getOperand ( KilledProdOp ) . getSubReg ( ) ; unsigned OtherProdSubReg = MI . getOperand ( OtherProdOp ) . getSubReg ( ) ; bool AddRegKill = AddendMI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool KilledProdRegKill = MI . getOperand ( KilledProdOp ) . isKill ( ) ; bool OtherProdRegKill = MI . getOperand ( OtherProdOp ) . isKill ( ) ; bool AddRegUndef = AddendMI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool KilledProdRegUndef = MI . getOperand ( KilledProdOp ) . isUndef ( ) ; bool OtherProdRegUndef = MI . getOperand (


<s> int OpNum = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { OutStreamer . EmitJumpTable8Region ( ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { OutStreamer . EmitJumpTable16Region ( ) ; } else { OutStreamer . EmitJumpTable32Region ( ) ; } MCSymbol * JTISymbol = Get<ISA_LIT>JTIPICJumpTableLabel2 ( JTI , MO2 . getImm ( ) ) ; OutStreamer . EmitLabel ( JTISymbol ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; unsigned OffsetWidth = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) OffsetWidth = <NUM_LIT> ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) OffsetWidth = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; const MCExpr * MBBSymbolExpr = MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , OutContext ) ; if ( OffsetWidth == <NUM_LIT> ) { MCInst BrInst ; BrInst . setOpcode ( <STR_LIT> ) ; BrInst . addOperand ( MCOperand :: CreateExpr ( MBBSymbolExpr ) ) ; BrInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; BrInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; OutStreamer . EmitInstruction ( BrInst )


<s> if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ; llvm_unreachable ( <STR_LIT>


<s> EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; bool UseHVX64B = Subtarget . useHVX64BOps ( ) ; if ( ! VT . isVector ( ) || ! UseHVX ) return SDValue ( ) ; EVT ResVT = Op . getValueType ( ) ; unsigned ResSize = ResVT . getSizeInBits ( ) ; unsigned VectorSizeInBits = UseHVX64B ? ( <NUM_LIT> * <NUM_LIT> ) : ( <NUM_LIT> * <NUM_LIT> ) ; unsigned OpSize = VT . getSizeInBits ( ) ; if ( ! ( ResVT . isByteSized ( ) && ResSize == VectorSizeInBits ) || ! ( VT . isByteSized ( ) && OpSize == <NUM_LIT> * VectorSizeInBits ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst ) return SDValue ( ) ; unsigned Val = Cst -> getZExtValue ( ) ; if ( Val == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResVT ,


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ; return true


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) && ! isTargetWindows

( ) && ! isTargetNaCl ( ) && ! Enable<ISA_LIT>DwarfEH ;


<s> return IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind .

isBSS ( ) || Kind . isCommon ( ) || Kind . isReadOnly ( ) ) ;


<s> rtx c = gen_int_mode ( val , GET_MODE_INNER (


<s> switch ( ( int ) n ) { case <NUM_LIT> : * total = <NUM_LIT> ; return true ; case <NUM_LIT> : case <NUM_LIT> : case - <NUM_LIT> : case - <NUM_LIT> : * total = <NUM_LIT> + ( outer_code == SET ) ; return true ; case <NUM_LIT> : case - <NUM_LIT> : if ( TARGET_H8300H || TARGET_H8300S ) * total = <NUM_LIT> + ( outer_code == SET ) ; else * total = <NUM_LIT> ; return true ; } } * total = <NUM_LIT> ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_H8300SX ) { * total = <NUM_LIT> ; return true ; } * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case AND : if ( ! h8300_dst_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) || ! h8300_src_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) ) return false ; * total = COSTS_N_INSNS ( h8300_and_costs ( x ) ) ; return true ; case MOD : case DIV : case UMOD : case UDIV : if ( TARGET_H8300SX ) switch ( GET_MODE ( x ) ) { case QImode : case HImode : * total = COSTS_N_INSNS ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ; return false ; case SImode : * total = COSTS_N_INSNS ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ; return false ; default : break ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( TARGET_H8300SX ) switch ( GET_MODE ( x ) ) { case QImode : case HImode : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case SImode : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; default : break ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( h8sx_binary_shift_operator ( x , VOIDmode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } else if ( h8sx_unary_shift_operator ( x , VOIDmode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } * total = COSTS_N_INSNS ( h8300_shift_costs ( x ) ) ; return true ; case ROTATE : case ROTATERT


<s> if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) <<


<s> case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Exclaim : case AsmToken :: Tilde : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken ::


<s> } else if ( SetCCOpcode == <STR_LIT> ) { SDValue ORD , NEQ ; ORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; NEQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ORD , NEQ ) ; } llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } unsigned Opc = <NUM_LIT> , EQOpc = <NUM_LIT> , GTOpc = <NUM_LIT> ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = EQOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; Invert = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; FlipSigns = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = GTOpc ; FlipSigns = true ; Invert = true ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( FlipSigns ) { EVT EltVT = VT . getVectorElementType ( ) ; SDValue SignBit = DAG . getConstant ( APInt :: getSignBit ( EltVT . getSizeInBits ( ) ) , EltVT ) ; std :: vector < SDValue > SignBits ( VT . getVectorNumElements ( ) , SignBit ) ; SDValue SignVec = DAG . getNode ( <STR_LIT> , dl , VT , & SignBits [ <NUM_LIT> ] , SignBits . size ( ) ) ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , SignVec ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , Op1 , SignVec ) ; } SDValue Result = DAG . getNode ( Opc , dl , VT , Op0 , Op1 ) ; if ( Invert ) Result = DAG . getNOT ( dl ,


<s> bool <ISA_LIT>GNULDBackend :: finalizeTargetSymbols ( ) { return


<s> } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; if ( LPR . contains ( SrcLo ) ) { StoreOpc = NeedAlign <= HasAlign ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; } if ( LPR . contains ( SrcHi ) ) { StoreOpc = NeedAlign <= MinAlign ( HasAlign , Size ) ? <STR_LIT>


<s> continue ; } legalizeOpWithMove ( MI , Idx ) ; } } if ( MI -> getOpcode ( ) == AMDGPU :: REG_SEQUENCE ) { const TargetRegisterClass * RC = NULL , * SRC = NULL , * VRC = NULL ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { if ( ! MI -> getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ; const TargetRegisterClass * OpRC = MRI . getRegClass ( MI -> getOperand ( i ) . getReg ( ) ) ; if ( RI . hasVGPRs ( OpRC ) ) { VRC = OpRC ; } else { SRC = OpRC ; } } if ( VRC || ! RI . isSGPRClass ( getOpRegClass ( * MI , <NUM_LIT> ) ) ) { if ( ! VRC ) { assert ( SRC ) ; VRC = RI . getEquivalentVGPRClass ( SRC ) ; } RC = VRC ; } else { RC = SRC ; } for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { if ( ! MI -> getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ; unsigned DstReg = MRI .


<s> if ( Model == TLSModel :: LocalDynamic ) Model = TLSModel :: GeneralDynamic ; } SDValue TPOff ; EVT PtrVT = getPointerTy ( ) ; SDLoc DL ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; SDValue ThreadBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue TPWithOff_lo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , ThreadBase , HiVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue TPWithOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPWithOff_lo , LoVar , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return TPWithOff ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL ,


<s> int MaskNumElts = mask -> getType ( ) -> getVectorNumElements ( ) ; if ( ( MaskNumElts & <NUM_LIT> ) != <NUM_LIT> ) { return false ; } int half_size = MaskNumElts / <NUM_LIT> ; int starts [ <NUM_LIT> ] ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { starts [ i ] = half_size * i ; } SmallVector < int , <NUM_LIT> > Indices ; ShuffleVectorInst :: getShuffleMask ( mask , Indices ) ; bool found = false ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( Indices [ <NUM_LIT> ] == starts [ i ] ) { * first = i ; found = true ; break ; } } if ( ! found ) { if ( Indices [ <NUM_LIT> ] >= <NUM_LIT> ) { return false ; } else { for ( i = <NUM_LIT> ; i < half_size ; i ++ ) { if ( Indices [ i ] >= <NUM_LIT> ) { return false ; } } * first = - <NUM_LIT>


<s> static __inline qword si_shli ( qword a , unsigned int b ) { vec_uint4 bv ; vec_uint4 mask ; bv = vec_splat ( ( vec_uint4 ) ( si_from_uint ( b ) ) ,


<s> const uint64_t F = MCII . get ( MCI .


<s> MCWinCOFFStreamer * create<ISA_LIT>WinCOFFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter ,

bool RelaxAll , bool IncrementalLinkerCompatible ) {


<s> inline SDValue getI32Imm ( unsigned Imm , SDLoc dl ) { return CurDAG -> getTargetConstant ( Imm


<s> if ( PendingLabels . empty ( ) ) { return ; } for ( MCSymbol * Sym :


<s> Parser . Lex ( ) ; const MCExpr * IdVal ; SMLoc EndLoc ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { while ( <NUM_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & nextTok = Parser . getTok ( ) ; if ( nextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += nextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ; Res = evaluateRelocExpr ( IdVal , Str ) ; return false


<s> } else { XchgPairCorrector Correct ( <NUM_LIT> , i ) ; Correct ( j ) ; Rv ( StackFixup :: xcpu (


<s> if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_long_type_node ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( type == vector_pair_type_node ) return <STR_LIT>


<s> TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend


<s> void <ISA_LIT>MachineCFGStructurizer :: ensureCondIsNotKilled ( SmallVector < MachineOperand , <NUM_LIT> > Cond ) { if ( Cond . size ( ) != <NUM_LIT> ) return ; if ( ! Cond [ <NUM_LIT> ] . isReg ( ) ) return ; Register CondReg = Cond [ <NUM_LIT> ] . getReg ( ) ; for ( auto UI = MRI -> use_begin ( CondReg ) , E = MRI -> use_end ( ) ; UI != E ; ++ UI ) { ( * UI ) .


<s> void <ISA_LIT>MCELFStreamer :: EmitSymbol ( const MCInst & Inst ) { for ( unsigned i = Inst . getNumOperands ( ) ; i -- ; ) if ( Inst . getOperand ( i ) . isExpr ( ) ) visitUsedExpr ( * Inst . getOperand ( i


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand *


<s> case <STR_LIT> : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case


<s> if ( F -> hasFnAttribute ( Attribute :: StackAlignment ) ) { if ( ! CanRealign ) DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; return CanRealign ; } unsigned StackAlignment = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; if ( MFI -> getMaxAlignment ( ) > StackAlignment ) { if ( ! CanRealign ) DEBUG ( dbgs ( ) << <STR_LIT>


<s> IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; const <ISA_LIT>CommonSubtarget & ST = <ISA_LIT>CommonSubtarget :: get ( * TM , F ) ; if ( ! ST . isPromoteAllocaEnabled ( ) ) return false ; AS = <STR_LIT> ( * F . getParent ( ) ) ; bool SufficientLDS = hasSufficientLocalMem ( F ) ; bool Changed = false ; BasicBlock & EntryBB = * F . begin ( ) ; for ( auto I = EntryBB . begin ( ) , E = EntryBB . end ( ) ; I !=


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> isStrongDefinitionForLinker ( ) ; return


<s> const Function * F = & * FI ; if ( F -> isDeclaration ( ) ) { if ( F -> use_empty ( ) ) continue ; if ( F -> getIntrinsicID ( ) ) continue ; emitDeclaration ( F , O ) ; continue ; } for ( const User * U : F -> users ( ) ) { if ( const Constant * C = dyn_cast < Constant > ( U ) ) { if ( usedInGlobalVarDef ( C ) ) { emitDeclaration ( F , O ) ; break ; } if ( useFuncSeen ( C , seenMap ) ) { emitDeclaration ( F ,


<s> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB =


<s> if ( ( GET_CODE ( op0 ) == ZERO_EXTEND && GET_CODE ( op1 ) == ZERO_EXTEND ) || ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( op1 ) == SIGN_EXTEND ) ) { cost += rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( op1 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ <NUM_LIT> ] . extend_add ; else cost += extra_cost -> mult [ <NUM_LIT> ] . extend ; } return cost ; } cost += rtx_cost ( op0 , MULT , <NUM_LIT> , speed ) + rtx_cost ( op1 , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ mode == DImode ] . add ; else cost += extra_cost -> mult [ mode == DImode ] . simple ; } return cost ; } else { if ( speed


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( Opcode == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) >=


<s> TYPE_NAME ( record ) = type_decl ; ofs = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( ofs ) = record ; base = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , ptr_type_node ) ; DECL_FIELD_CONTEXT ( base ) = record ; TREE_CHAIN ( base ) = ofs ; TYPE_FIELDS ( record ) = base ; layout_type ( record ) ; return record


<s> RegList = RRegList ; unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; unsigned RegAlign = alignTo ( Align , <NUM_LIT> ) / <NUM_LIT> ; while ( RegIdx % RegAlign != <NUM_LIT> && RegIdx < RegList . size ( ) ) State . AllocateReg ( RegList [ RegIdx ++ ] ) ; break ; } case <STR_LIT> : case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg (


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> || DestRC == <STR_LIT> || SrcRC == <STR_LIT> || SrcRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; } else if ( DestRC == <STR_LIT> || DestRC == <STR_LIT> || DestRC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )


<s> int <ISA_LIT>ConstantIslands :: findInRangeCPEntry ( CPUser & U , unsigned UserOffset ) { MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEMI , U . getMaxDisp ( ) , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs


<s> unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , TempReg ) ; unsigned Flags = getKillRegState ( New . isDead ( ) ) ; addExclusiveRegPair ( MIB , New , Flags , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB .


<s> bool <ISA_LIT>TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . flags = MachineMemOperand :: MONone ; Info . offset = <NUM_LIT> ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; MVT VT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT ScalarVT = <STR_LIT> ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = <STR_LIT> ; Info . memVT = <STR_LIT> ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = <STR_LIT> ; Info . ptrVal = nullptr ; MVT DataVT = <STR_LIT> ( I . getType ( ) ) ; MVT IndexVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) ,


<s> return D ( <STR_LIT> , <STR_LIT> , R ( b


<s> addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None

) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ;


<s> <ISA_LIT>Operand * ErrorOperand ( SMLoc Loc , StringRef Msg ) { Error ( Loc ,


<s> if ( const auto * C = dyn_cast < ConstantInt > ( MI -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValue ( ) . isPowerOf2


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI ,


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) { return ( GET_CODE ( x ) == SYMBOL_REF

&& SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ;


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_TAIL_CALL ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; OpCode = convertTailJumpOpcode ( OpCode ) ; MCInst TC


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL =


<s> APInt UndefElts ( NumMaskElts , <NUM_LIT> ) ; APInt ZeroElts ( NumMaskElts , <NUM_LIT> ) ; APInt ConstantElts ( NumMaskElts , <NUM_LIT> ) ; SmallVector < APInt , <NUM_LIT> > ConstantBitData ( NumMaskElts , APInt :: getZero ( MaskSizeInBits ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { UndefElts . setBit ( i ) ; continue ; } else if ( M == SM_SentinelZero ) { ZeroElts . setBit ( i ) ; continue ; } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx ] ) { UndefElts . setBit ( i ) ; continue ; } auto & SrcEltBits = RawBitsOps [ SrcOpIdx ] ; APInt & Bits = SrcEltBits [ SrcMaskIdx ] ; if ( ! Bits


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , MRI


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineSelectAndUseCommutative ( N , DCI , false ) ; case <STR_LIT> : return combineSelectAndUseCommutative ( N , DCI , true ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; } return SDValue (


<s> BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { unsigned MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW32 ( Ordering ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( ScratchReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * LoopHeadMBB ) ; computeAndAddLiveIns ( LiveRegs ,


<s> auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> (


<s> bool <ISA_LIT>RegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . needsFrameMoves ( )


<s> case MachineOperand :: MO_ExternalSymbol : MCO = GetSymbolRef ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; } MCI . addOperand ( MCO


<s> return __builtin_mve_vminvq_uv8hi ( __a ,


<s> return StringSwitch < ValueKind > ( BaseTypeName ) . Case ( <STR_LIT> , ValueKind :: Sampler ) . Case ( <STR_LIT> , ValueKind :: Queue ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , ValueKind :: Image ) . Default (

isa < PointerType > ( Ty ) ? ( Ty -> getPointerAddressSpace ( ) == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS ? ValueKind :: DynamicSharedPointer :


<s> fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl =


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X


<s> static DecodeStatus decodeOperand_f16kimm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { const auto * DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; return addOperand ( Inst , DAsm -> decodeMandatoryLiteralConstant


<s> if ( d -> perm [ <NUM_LIT> ] == high ) ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) high = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { unsigned elt = ( i + high ) & mask ; if ( d -> perm [ i * <NUM_LIT> ] != elt ) return false ; elt = ( elt + nelt ) & mask ; if ( d -> perm [ i * <NUM_LIT> + <NUM_LIT> ] != elt ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; if ( high ) { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4HFmode : gen = gen_aarch64_zip2v4hf ; break ; case V8HFmode : gen = gen_aarch64_zip2v8hf ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen =


<s> regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ; if ( ! TARGET_BONNELL && parts . scale == <NUM_LIT> && ( ! parts . disp || parts . disp == const0_rtx ) && ( regno0 == regno1 || regno0 == regno2 ) ) return true ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; split_cost = <NUM_LIT> ; if ( parts . base || parts . index ) { if ( regno1 != regno0 && regno2 != regno0 ) split_cost += <NUM_LIT> ; if ( parts . base && parts . index ) split_cost += <NUM_LIT> ; if ( parts . scale > <NUM_LIT> ) { if ( regno0 != regno1 ) split_cost += <NUM_LIT> ; else if ( regno2 == regno0 ) split_cost += <NUM_LIT> ; else split_cost +=


<s> addPass ( new <ISA_LIT>ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } addPass ( create<ISA_LIT>IndirectThunks (


<s> case nodeType :: LOOP : priority = <NUM_LIT> ; break ; case nodeType :: SWITCH_BRANCH : priority = <NUM_LIT> ; break ; case nodeType :: NODE : priority =


<s> if ( ExplicitArgBytes == - <NUM_LIT> ) ExplicitArgBytes = getExplicitKernArgSize ( F ) ; unsigned ExplicitOffset = getExplicitKernelArgOffset ( F ) ; uint64_t TotalSize = ExplicitOffset +


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( ( unsigned HOST_WIDE_INT ) ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + <NUM_LIT> ) >= <NUM_LIT> - extra ) && ! PAIRED_VECTOR_MODE ( mode ) ) { HOST_WIDE_INT high_int , low_int ; rtx sum ; low_int = ( ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( low_int >= <NUM_LIT> - extra ) low_int = <NUM_LIT> ; high_int = INTVAL ( XEXP ( x , <NUM_LIT> ) ) - low_int ; sum = force_operand ( gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , GEN_INT ( high_int ) ) , <NUM_LIT> ) ; return plus_constant ( Pmode , sum , low_int ) ; } else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) && ( mode == DFmode || mode == DDmode ) ) ) && ! avoiding_indexed_address_p ( mode ) ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( PAIRED_VECTOR_MODE ( mode ) ) { if ( mode == DImode ) return x ; if ( GET_CODE ( x ) == PLUS ) { rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT> ) ; rtx y ; op1 = force_reg ( Pmode , op1 ) ; op2 = force_reg ( Pmode , op2 ) ; y = gen_rtx_PLUS ( Pmode , op1 , op2 ) ; if ( ( GET_MODE_SIZE ( mode ) > <NUM_LIT> || mode == DDmode ) && REG_P ( op2 ) ) return force_reg ( Pmode , y ) ; else return y ; } return force_reg ( Pmode , x ) ; } else if ( ( TARGET_ELF || ! MACHO_DYNAMIC_NO_PIC_P ) && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic && GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_WIDE_INT && GET_CODE ( x ) != CONST_DOUBLE && CONSTANT_P ( x ) && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( ( TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ) && ( mode == DFmode || mode == DDmode ) ) ) ) { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_ELF ) emit_insn ( gen_elf_high ( reg , x ) ) ; else emit_insn ( gen_macho_high ( reg , x ) ) ; return gen_rtx_LO_SUM ( Pmode , reg


<s> unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * NewMBB ; unsigned UserOffset = GetOffsetOf ( UserMI ) + ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; int result = LookForExistingCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createConstPoolEntryUId ( ) ; if ( ! LookForWater ( U , UserOffset , & NewMBB ) ) { DOUT << <STR_LIT> ; CreateNewWater ( CPUserIndex , UserOffset , & NewMBB ) ; } MachineBasicBlock * NewIsland = MF . CreateMachineBasicBlock ( ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . CPEMI = BuildMI ( NewIsland , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; NumCPEs ++ ; BBOffsets [ NewIsland -> getNumber ( ) ] = BBOffsets [ NewMBB -> getNumber ( ) ] ; if ( isThumb && BBOffsets [ NewIsland -> getNumber ( ) ] % <NUM_LIT> != <NUM_LIT> )


<s> if ( ! Ty -> isFloatTy ( ) && ( ! Subtarget -> hasGFX90AInsts ( ) || ! Ty -> isDoubleTy ( ) ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) != <STR_LIT> ) return AtomicExpansionKind :: CmpXChg ; if ( Subtarget -> hasGFX90AInsts ( ) ) { if ( Ty -> isFloatTy ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; auto S<ISA_LIT>D = RMW -> getSyncScopeID ( ) ; if ( S<ISA_LIT>D == SyncScope :: System || S<ISA_LIT>D == RMW -> getContext ( ) . getOrInsertSyncScopeID ( <STR_LIT> ) ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind ::


<s> static DecodeStatus DecodeLoadDFP ( MCInst & Inst , unsigned insn , uint64_t Address , const void * Decoder ) { return DecodeMem ( Inst , insn , Address , Decoder , true , DecodeDFPRegsRegisterClass


<s> else if ( info2 . demand_p ( DEMAND_MASK_POLICY ) ) { set_ma ( info2 . get_ma ( ) ) ; demand ( DEMAND_MASK_POLICY ) ; } else set_ma ( get_default_ma ( ) )


<s> bool VisitNode ( MachineDomTreeNode * Node , unsigned TLSBaseAddrReg ) { MachineBasicBlock * BB = Node -> getBlock ( ) ; bool Changed = false ; for ( MachineBasicBlock :: iterator I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { switch ( I -> getOpcode ( ) ) { case


<s> case <STR_LIT> : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : { SDValue RV = performSelectCombine ( N , DCI ) ; if ( ! RV . getNode ( ) ) RV = performAcrossLaneMinMaxReductionCombine ( N , DAG , Subtarget ) ; return RV ; } case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : return performAcrossLaneAddReductionCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind ,


<s> static bool isLegalArithImmed ( uint64_t C ) { return ( C >> <NUM_LIT> == <NUM_LIT> ) || ( ( C &

<NUM_LIT> ) == <NUM_LIT> && C >> <NUM_LIT> == <NUM_LIT> ) ;


<s> OperandMatchResultTy parsePCRelTLS16 ( OperandVector & Operands ) { return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT>


<s> unsigned getStoredByValParamsPadding ( ) const { return


<s> static unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTuple ( Regs , RegClassIDs


<s> bool <ISA_LIT>InvISelDAG :: SelectT2AddrModeImm8Offset ( SDNode * Op , SDValue N , SDValue & OffImm ) { return


<s> bool isBDAddr64Disp12 ( ) const { return isMemDisp12 ( BDMem ,


<s> int regno = REGNO ( operands [ <NUM_LIT> ] ) ; regno = ( ( regno - FIRST_VFP_REGNUM ) >> <NUM_LIT> ) ; if ( lane > <NUM_LIT> && lane >= GET_MODE_NUNITS ( mode ) / <NUM_LIT> ) { operands [ <NUM_LIT> ] = gen_int_mode ( regno + <NUM_LIT> ,


<s> return ( uint32x2_t ) __builtin_neon_vshru_nv2si ( ( int32x2_t )


<s> for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseN = * I ; assert ( ! ( UseN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > OwnerN = UseN . Addr -> getOwner ( * DFG ) ; MachineInstr * UseMI = OwnerN . Addr -> getCode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << UseMI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; int UseMOnum = - <NUM_LIT> ; unsigned NumOperands = UseMI -> getNumOperands ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumOperands - <NUM_LIT> ; ++ j ) { const MachineOperand & op = UseMI -> getOperand ( j ) ; if ( op . isReg ( ) && op . isUse ( ) && DefR == op . getReg ( ) ) UseMOnum = j ; } assert ( UseMOnum >= <NUM_LIT> && <STR_LIT> ) ; if ( InstrEvalResult [ UseMI ] ) Changed |= xformUseMI (


<s> case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : return Helper . tryCombineExtendingLoads ( MI ) ; } return false


<s> bool isCCallSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr ::


<s> bool OutgoingValueHandler :: handleSplit ( SmallVectorImpl < unsigned > & VRegs , ArrayRef < CCValAssign > ArgLocs , unsigned ArgLocsStartIndex , unsigned ArgsReg ) { MIRBuilder . buildUnmerge ( VRegs , ArgsReg ) ; setMostSignificantFirst ( VRegs


<s> for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) Functions . insert ( & F ) ; } CallGraphUpdater CGUpdater ; BumpPtrAllocator Allocator ; <ISA_LIT>InformationCache InfoCache ( M , AG , Allocator , nullptr , * TM ) ; DenseSet < const char * > Allowed ( { & AAAMDAttributes :: ID , & AAUniformWorkGroupSize :: ID , & AAAMDFlatWorkGroupSize :: ID , & AACallEdges :: ID , & AAPointerInfo :: ID } ) ; AttributorConfig AC ( CGUpdater ) ; AC . Allowed = & Allowed ; AC . IsModulePass = true ; AC . DefaultInitializeLiveInternals = false ; Attributor A ( Functions , InfoCache , AC ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ; A . getOrCreateAAFor < AAUniformWorkGroupSize > ( IRPosition :: function ( F ) ) ; if ( ! <STR_LIT> ( F . getCallingConv ( ) ) ) { A . getOrCreateAAFor < AAAMDFlatWorkGroupSize > ( IRPosition


<s> return ( int8x8_t ) __builtin_neon_vreinterpretv8qidi ( ( int64x1_t


<s> <STR_LIT> ExtType = LD -> getExtensionType ( ) ; bool IsZeroExt = ( ExtType == <STR_LIT> || ExtType == <STR_LIT> ) ; bool HasVecOffset = false ; if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; else Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; else Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { HasVecOffset = true ; if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) { Opcode = <STR_LIT> ; } else Opcode = <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { HasVecOffset = true ; if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) { Opcode = <STR_LIT> ; } else Opcode = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && IsZeroExt ) return SelectIndexedLoadZeroExtend64 ( LD , Opcode


<s> if ( Res != MatchOperand_Success ) { return Res ; } <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( * Operands . back ( ) ) ; if ( Op . isImm ( ) && Op . Imm . IsFPImm ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } <ISA_LIT>Operand :: Modifiers Mods = { false , false , false } ; if ( Sext ) { if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Mods . Sext = true ; } if ( Mods . hasIntModifiers ( ) ) { Op . setModifiers ( Mods ) ; } return MatchOperand_Success


<s> const MCRegisterInfo * RI = Ctx . getRegisterInfo ( ) ; uint32_t Reg = RI -> getRegClass ( <STR_LIT> ) . getRegister (

RI -> getEncodingValue ( getReg ( ) ) ) ;


<s> PLTEntryBase * <ISA_LIT>PLT :: getPLT0 ( ) const { iterator first = m_pSectionData -> getFragmentList ( ) . begin ( ) ; assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ; PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( * first ) ) ; return


<s> bool Thumb2SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI -> getInstrInfo ( ) ) ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; OptimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; MinimizeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( )


<s> else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT>


<s> rtx sp = NULL_RTX ; rtx fp = NULL_RTX ; framesize = ( frame_info . valid ? frame_info . total_size : compute_frame_size ( get_frame_size ( ) ) ) ; if ( framesize > <NUM_LIT> || frame_pointer_needed ) sp = gen_rtx_REG ( SImode , SP_REGNUM ) ; if ( frame_pointer_needed ) fp = gen_rtx_REG ( SImode , FP_REGNUM ) ; if ( SHOULD_COMBINE_STORE_RESTORE ) { emit_insn ( gen_store_regs ( gen_rtx_REG ( SImode , frame_info . first_reg ) , gen_rtx_REG ( SImode , frame_info . last_reg ) ) ) ; } else { int rmask = frame_info


<s> if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t Val = MO . getImm ( ) ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; else if ( Val < <NUM_LIT> ) { Val *=


<s> const InstrItineraryData & getInstrItineraryData ( ) const { return InstrItins


<s> It != E ; ++ It ) { if ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT>

) return std :: prev ( It . base ( ) ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return


<s> } else if ( CONST_INT_P ( src ) ) { if ( INTVAL ( src ) < <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } else if ( MEM_P ( src ) ) { int ptrreg = - <NUM_LIT> ; int dreg = REGNO ( dst ) ; rtx inside = XEXP ( src , <NUM_LIT> ) ; switch ( GET_CODE ( inside ) ) { case REG : ptrreg = REGNO ( inside ) ; break ; case SUBREG : ptrreg = subreg_regno ( inside ) ; break ; case PLUS : ptrreg = REGNO ( XEXP ( inside , <NUM_LIT> ) ) ; gcc_assert ( ! REG_P ( XEXP ( inside , <NUM_LIT> ) ) ) ; break ; case LABEL_REF


<s> MachineInstr * AMDGPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr *


<s> void <ISA_LIT>TargetLowering :: addDRTypeForNEON ( MVT VT ) { addRegisterClass ( VT , &


<s> RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : if ( RxSBG . Opcode != <STR_LIT> ) { unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; if ( ! refineRxSBGMask ( RxSBG , allOnes ( InnerBitSize ) ) ) return false ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } LLVM_FALLTHROUGH ; case <STR_LIT> : { unsigned BitSize = N . getValueSizeInBits ( ) ; unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; if ( maskMatters ( RxSBG , allOnes ( BitSize ) - allOnes ( InnerBitSize ) ) ) { if ( RxSBG . Mask == <NUM_LIT> && RxSBG . Rotate == <NUM_LIT> ) RxSBG . Rotate += ( BitSize - InnerBitSize ) ; else return false ; } RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : { auto * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> ) { if ( maskMatters ( RxSBG , allOnes ( Count ) ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) << Count ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate + Count ) & <NUM_LIT> ; RxSBG . Input = N . getOperand (


<s> static void lm32_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int first_anon_arg ; tree fntype ; fntype = TREE_TYPE ( current_function_decl ) ; if ( stdarg_p ( fntype ) ) first_anon_arg = * cum + LM32_FIRST_ARG_REG ; else { int size = arg .


<s> bool isVCSrcF16 ( ) const { return isRegOrInlineNoMods ( <STR_LIT>


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; SDValue Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node =


<s> continue ; } if ( isUInt < <NUM_LIT> > ( OffsetNode -> getZExtValue ( ) >> <NUM_LIT> ) ) { Match = true ; Offset = CurDAG -> getTargetConstant ( OffsetNode -> getZExtValue ( ) >> <NUM_LIT> , <STR_LIT> ) ; } } return Match ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI

-> getPointerOperand ( ) , AI -> getAlign ( ) ) ;