<s> SDValue LHSL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue LHSH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RHSL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RHSH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHSL , RHSL , Zero ) ; SDValue Carry ( Lo . getNode ( ) ,


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> ,


<s> Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; MMO = LD -> getMemOperand ( ) ; if ( MMO -> getSize ( ) < <NUM_LIT> ) return SDValue ( ) ; break ; } case <STR_LIT> : { MemIntrinsicSDNode * Intrin = cast < MemIntrinsicSDNode > ( N ) ; Chain = Intrin -> getChain ( ) ; Base = Intrin -> getOperand ( <NUM_LIT> ) ; MMO = Intrin -> getMemOperand ( ) ; break ; } } MVT VecTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue LoadOps [ ] = { Chain , Base } ; SDValue Load = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VecTy , <STR_LIT> ) , LoadOps , VecTy , MMO ) ; DCI . AddToWorklist ( Load . getNode ( ) ) ; Chain = Load . getValue ( <NUM_LIT> ) ; SDValue Swap = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VecTy , <STR_LIT> ) , Chain , Load ) ; DCI . AddToWorklist ( Swap . getNode ( )


<s> is<ISA_LIT>SoloInstruction ( const MachineInstr * MI ) const


<s> fixupKills ( BB ) ; ScheduleDAGInstrs :: finishBlock


<s> if ( const Instruction * instr = dyn_cast < Instruction > ( U ) ) { if ( instr -> getParent ( ) && instr -> getParent ( ) -> getParent ( ) ) { const Function * curFunc = instr -> getParent ( ) -> getParent ( ) ; if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc =


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) &&


<s> size_t sz = Src . size ( ) ; for ( size_t i = <NUM_LIT> ; i < sz / <NUM_LIT> ; ++ i ) { NodeT * t = Src [ i ] ; Src [ i ] = Src [ sz - i


<s> layout = xstormy16_compute_stack_layout ( ) ; if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = layout . sp_minus_fp - layout . locals_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - layout . locals_size ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = - layout . fp_minus_ap ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - ( layout . sp_minus_fp + layout . fp_minus_ap ) ; else gcc_unreachable (


<s> MBBs . resize ( NumBlocks ) ; Terminators . clear ( ) ; Terminators . reserve ( NumBlocks ) ; BlockPosition Position ( MF -> getAlignment ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumBlocks ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes (


<s> else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasV6Ops ( ) ) return <NUM_LIT> ; if ( isZExt ) Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; else Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isZExt ) { Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; isBoolZext = true ; break ; } return <NUM_LIT> ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ; if ( isBoolZext ) MIB . addImm


<s> if ( ! <STR_LIT> . contains ( DstR ) || ! <STR_LIT> . contains ( SrcR ) ) return false ; unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY ) , TmpR ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY ) , DstR ) . addReg ( TmpR , RegState :: Kill ) ; NewRegs . push_back (


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || ! is<ISA_LIT>LowRegister ( Memory . BaseRegNum ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast <

MCConstantExpr > ( Memory . OffsetImm ) ) {


<s> unsigned CmpVal = MRI . createVirtualRegister ( RC ) ; unsigned SwapVal = MRI . createVirtualRegister ( RC ) ; unsigned StoreVal = MRI . createVirtualRegister ( RC ) ; unsigned RetryOldVal = MRI . createVirtualRegister ( RC ) ; unsigned RetryCmpVal = MRI . createVirtualRegister ( RC ) ; unsigned RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * SetMBB = emitBlockAfter ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , CmpVal ) . addReg ( OrigCmpVal ) . addMBB ( StartMBB ) . addReg ( RetryCmpVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , SwapVal ) . addReg ( OrigSwapVal ) . addMBB ( StartMBB ) . addReg ( RetrySwapVal ) . addMBB ( SetMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( BitSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetryCmpVal ) . addReg ( CmpVal ) . addReg ( Dest ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> - BitSize ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( RetryCmpVal ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB -> addSuccessor ( SetMBB ) ; MBB = SetMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RetrySwapVal ) . addReg ( SwapVal ) . addReg


<s> for ( unsigned Reg : BVAllocatable . set_bits ( ) ) { if ( BVCalleeSaved [ Reg ] || ! <STR_LIT> . contains ( Reg ) || MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) BVAllocatable . reset ( Reg ) ; } bool AllSpilledToReg = true ; unsigned LastVSRUsedForSpill = <NUM_LIT> ; for ( auto & CS : CSI ) { if ( BVAllocatable . none ( ) ) return false ; Register Reg = CS . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) { AllSpilledToReg = false ; continue ; } if ( LastVSRUsedForSpill != <NUM_LIT> ) { CS . setDstReg ( LastVSRUsedForSpill ) ; BVAllocatable . reset ( LastVSRUsedForSpill ) ; LastVSRUsedForSpill = <NUM_LIT> ; continue ; } unsigned VolatileVFReg = BVAllocatable . find_first ( ) ; if ( VolatileVFReg < BVAllocatable . size ( ) ) { CS . setDstReg ( VolatileVFReg ) ; LastVSRUsedForSpill =


<s> unsigned decodeLgkmcnt ( const IsaInfo :: IsaVersion & Version , unsigned Waitcnt ) { return unpackBits ( Waitcnt , getLgkmcntBitShift ( ) , getLgkmcntBitWidth


<s> MRI = & MF . getRegInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) { std :: list < std :: list < CombineInfo > > MergeableInsts ; Modified |= collectMergeableInsts ( MBB , MergeableInsts ) ; do { OptimizeAgain = false ; Modified |= optimizeBlock ( MergeableInsts


<s> static void demoteInst ( MCInst & Inst , const MCInstrInfo & InstInfo ) { unsigned NewOpc = demoteOpcode ( Inst . getOpcode ( ) ) ; Inst . setOpcode ( NewOpc ) ; const MCOperandInfo * OpInfo = InstInfo . get ( Inst . getOpcode ( )


<s> State = IES_ERROR ; break ; case IES_PLUS : case IES_NOT : State = IES_NOT


<s> } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS .


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Modifier = MCSymbolRefExpr :: VK_GOT ; IsPCRel = true ; return RT64_64 ; case FK_Data_8 : return RT64_64 ; case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_None && ! IsPCRel )


<s> static rtx_insn * arm_call_tls_get_addr ( rtx x , rtx reg , rtx * valuep , int reloc ) { rtx label , labelno , sum ; gcc_assert ( reloc != TLS_DESCSEQ ) ; start_sequence ( ) ; labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg )


<s> if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( N -> getSimpleValueType ( <NUM_LIT> ) , Subtarget , DAG , SDLoc ( N ) ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && ( VT

. getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) {


<s> int64_t Offset ; if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveR19R20X ( Offset ) ; return


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : break ; } DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeSImm < <NUM_LIT> > ( Inst , offset , Addr , Decoder ) ; if ( writeback && Rt == Rn && Rn != <NUM_LIT> ) { return SoftFail


<s> while ( ! WorkList . empty ( ) ) { auto Item = WorkList . back ( ) ; WorkList . pop_back ( ) ; IRBuilder < > IRB ( Item ) ; if ( isa < ConstantInt > ( Item -> getLength ( ) ) ) OptimizeMemCopy ( IRB , Item ) ; else if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( Item

) ) expandMemCpyAsLoop ( Memcpy , TTI ) ;


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && <STR_LIT> ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent


<s> static void expandf64Toi32 ( SDValue Op , SelectionDAG & DAG , SDValue & RetVal1 , SDValue & RetVal2 ) { if ( isFloatingPointZero ( Op ) ) { RetVal1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; RetVal2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return ; } if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) { SDValue Ptr = Ld -> getBasePtr ( ) ; RetVal1 = DAG . getLoad ( <STR_LIT> , Op . getDebugLoc ( ) , Ld -> getChain ( ) , Ptr , Ld -> getSrcValue ( ) , Ld -> getSrcValueOffset ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> getAlignment ( ) ) ; EVT PtrType = Ptr . getValueType ( ) ; unsigned NewAlign = MinAlign ( Ld -> getAlignment ( ) , <NUM_LIT> ) ; SDValue NewPtr = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , PtrType , Ptr , DAG . getConstant ( <NUM_LIT>


<s> auto Int8PtrTy = Type :: getInt8PtrTy ( Func . getContext ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ; if ( HiddenArgNumBytes >= <NUM_LIT> ) { if ( Func . getParent ( ) -> getNamedMetadata ( <STR_LIT> ) ) emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenPrintfBuffer ) ; else emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenNone ) ; } if ( HiddenArgNumBytes >= <NUM_LIT> ) { if ( Func . hasFnAttribute ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenDefaultQueue ) ; emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenCompletionAction


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> ) return nullptr ; return


<s> virtual unsigned getNumFixupKinds ( ) const


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; if ( ! Subtarget . hasE2 ( ) ) { setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( ! Subtarget . has2E3


<s> auto Prepare = [ & ] ( ) { AllocaAddr = CreateAllocaInst ( Builder , Bitcast -> getParent ( ) ) ; I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( Bitcast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src


<s> unsigned getPointerWidth ( ) { if ( is16BitMode ( ) ) return <NUM_LIT> ; if ( is32BitMode ( ) ) return


<s> if ( ! Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy (


<s> Value * <ISA_LIT>IREmitter :: visitVCGTZ ( const


<s> Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: SVEVector ; } break ; } assert ( Opc && <STR_LIT> ) ; MFI . setStackID ( FI , StackID ) ; const MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DebugLoc ( ) , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) )


<s> bool <ISA_LIT>AsmParser :: requestsDoubleOperand ( StringRef Mnemonic ) { bool IsDouble = StringSwitch < bool > ( Mnemonic . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Default ( false ) ; return IsDouble


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions &


<s> bool <ISA_LIT>TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI ,


<s> unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - <NUM_LIT> ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - <NUM_LIT> ) / <NUM_LIT> ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + <NUM_LIT> ] = Value & <NUM_LIT> ; Data [ Fixup . getOffset ( ) + <NUM_LIT> ] = Value >> <NUM_LIT> ; } else { Data [ Fixup . getOffset ( ) + <NUM_LIT>


<s> MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ) ; MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; } else { MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } else


<s> Type * RetType = F . getReturnType ( ) ; return whichFPReturnVariant ( RetType ) != NoFPRet


<s> static DecodeStatus decodeCLUIImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT>


<s> const unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & Desc = MII . get ( Opc ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <NUM_LIT> ) return true ; if ( Desc . TSFlags & <STR_LIT> ) return true ; int VDataIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdata ) ; int DMaskIdx = <STR_LIT> ( Opc , <STR_LIT> :: dmask ) ; int TFEIdx = <STR_LIT> ( Opc , <STR_LIT> :: tfe ) ; assert ( VDataIdx != - <NUM_LIT> ) ; assert ( DMaskIdx != - <NUM_LIT> ) ; assert ( TFEIdx != - <NUM_LIT> ) ; unsigned VDataSize = <STR_LIT> ( getMRI ( ) , Desc , VDataIdx ) ; unsigned TFESize = Inst . getOperand ( TFEIdx ) . getImm ( ) ?


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } StringRef Option = Tok . getIdentifier ( ) ; if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic0 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; } return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionPic2 ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot


<s> TRI = & TII -> getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsIEEEMode = ST -> enableIEEEBit ( MF ) || ! MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( <NUM_LIT> ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister


<s> if ( Ty -> isArrayTy ( ) ) return getElementAlignment ( DL , Ty -> getArrayElementType ( ) , <NUM_LIT> ) ; unsigned Alignment = DL . getABITypeAlignment ( Ty ) ; if ( n && ( Alignment > <NUM_LIT> ) ) { Type * EltTy = Ty -> getScalarType ( ) ; unsigned ffs = <NUM_LIT> ; while ( ( ( n >> ffs ) & <NUM_LIT> ) == <NUM_LIT> ) ffs ++ ; Alignment = ( DL . getABITypeAlignment ( EltTy ) * ( <NUM_LIT> << ffs ) ) & ( Alignment - <NUM_LIT> ) ; } else { if ( OpaqueType OT = GetOpaqueType ( Ty ) ) { if ( IsImage ( OT ) || OT ==


<s> SDValue Index = MGT -> getIndex ( ) ; SDValue Chain = MGT -> getChain ( ) ; SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Mask = MGT -> getMask ( ) ; SDValue BasePtr = MGT -> getBasePtr ( ) ; <STR_LIT> ExtTy = MGT -> getExtensionType ( ) ; <STR_LIT> IndexType = MGT -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IdxNeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; bool ResNeedsSignExtend = ExtTy == <STR_LIT> || ExtTy == <STR_LIT> ; EVT VT = PassThru . getSimpleValueType ( ) ; EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { VT = VT . changeVectorElementTypeToInteger ( ) ; ElementCount EC = VT . getVectorElementCount ( ) ; auto ScalarIntVT = <STR_LIT> ( <STR_LIT> / EC . getKnownMinValue ( ) ) ; PassThru = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( ScalarIntVT , EC ) , PassThru ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( PassThru . getSimpleValueType ( ) , <STR_LIT> ) ; if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getGatherVecOpcode ( IsScaled , IsSigned , IdxNeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , true , DAG ) ; if ( ResNeedsSignExtend ) Opcode

= getSignExtendedGatherOpcode ( Opcode ) ;


<s> return ( __m512d ) __builtin_ia32_pd512_pd (


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine >


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { return Subtarget -> isTargetDarwin ( ) ? LowerDarwin_VASTART ( Op

, DAG ) : LowerAAPCS_VASTART ( Op , DAG ) ;


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , (


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple ::


<s> bool Is64BitMode = TM . getSubtargetImpl ( ) -> is64Bit ( ) ; unsigned Size = GetInstSizeWithDesc ( * MI , & Desc , IsPIC , Is64BitMode ) ; if ( Desc . getOpcode ( ) == <STR_LIT> ) { Size += GetInstSizeWithDesc ( * MI , & get ( <STR_LIT> ) , IsPIC , Is64BitMode ) ; } return


<s> else { rtx tmp = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , delta ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( vcall_offset ) { rtx tmp , tmp2 ; tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; lo = ( ( vcall_offset & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; hi = ( ( ( vcall_offset - lo ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( hi + lo == vcall_offset ) { if ( hi ) emit_insn ( gen_adddi3 ( tmp , tmp , GEN_INT ( hi ) ) ) ; } else { tmp2 = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , vcall_offset ) ; emit_insn ( gen_adddi3 ( tmp , tmp , tmp2 ) ) ; lo = <NUM_LIT> ; } if ( lo ) tmp2 = gen_rtx_PLUS ( Pmode , tmp , GEN_INT ( lo ) ) ; else tmp2 = tmp ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp2 ) ) ; emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; insn = get_insns (


<s> static bool has_vtype_op ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_has_vtype_op


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate


<s> cum -> libcall = libcall ; cum -> nargs_prototype = <NUM_LIT> ; if ( incoming || cum -> prototype ) cum -> nargs_prototype = n_named_args ; if ( ( ! fntype && rs6000_default_long_calls ) || ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) ) cum -> call_cookie |= CALL_LONG ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } if ( cum -> call_cookie & CALL_LONG ) fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> , cum -> prototype , cum -> nargs_prototype ) ; } if ( TARGET_ELF && ( TARGET_64BIT || DEFAULT_ABI == ABI_V4


<s> Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM .

Align , AM . Disp , AM . SymbolFlags ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getReg (


<s> Value * MemIntrinsicsHandler :: GenMask ( IRBuilder < > & IRB , Type * SrcTy , Type * DestTy , Value * Offset , bool IsLoad ) { const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; unsigned SrcSz = DL . getTypeSizeInBits ( SrcTy ) ; unsigned DestSz = DL . getTypeSizeInBits ( DestTy ) ; return GenMask ( IRB , SrcSz ,


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> )


<s> poly8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return


<s> } Index = matchHWRegsRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFPURegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFCCRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchACRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , Identifier , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchMSA128RegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> )


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , JITCodeEmitter & JCE ) { if ( Subtarget . is<ISA_LIT>64 (


<s> auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const <ISA_LIT>Evaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry ,


<s> if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++ ; } switch ( fcode ) { case RS6000_BIF_TENDALL : case RS6000_BIF_TRESUME : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; break ; case RS6000_BIF_TSUSPEND : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; break ; default : break ; } rtx cr = NULL_RTX ; if ( uses_spr ) { machine_mode mode = TARGET_POWERPC64 ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; } else if ( bif_is_htmcr ( * bifaddr ) ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } rtx pat ; switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT>


<s> i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent


<s> SMLoc EndLoc = SMLoc :: getFromPointer ( Loc . getPointer ( ) + Str . size ( ) ) ; <ISA_LIT>Operand * Res = new <ISA_LIT>Operand ( Token , Loc , EndLoc ) ; Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str . size ( ) ; return


<s> bool isLegalMaskedStore ( Type * DataTy )


<s> return getCommonSubClass ( & AMDGPU :: VGPR_32RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_64RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_96RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_128RegClass , RC ) || getCommonSubClass ( & AMDGPU :: VReg_256RegClass , RC ) ||

getCommonSubClass ( & AMDGPU :: VReg_512RegClass , RC ) ;


<s> static DecodeStatus DecodeFPR8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = FPR8DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return


<s> else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = <NUM_LIT> , QCMP_UNORD = <NUM_LIT> , QCMP_EQ = <NUM_LIT> , QCMP_LT = <NUM_LIT> , QCMP_GT = <NUM_LIT> } ; int magic ; enum rtx_code ncode ; rtx ret ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode ,


<s> bool isRegisterReservedByUser ( Register R ) const { assert ( R < <STR_LIT> && <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , is64bit , JIT ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , std :: string ( CPU

) , std :: string ( FS ) , * this , is64bit ) , is64Bit ( is64bit ) {


<s> inline const MachineInstrBuilder & addLeaOffset ( const MachineInstrBuilder & MIB , int Offset ) { return MIB . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT>


<s> continue ; } assert ( MI . getDesc ( ) . getNumDefs ( ) <= <NUM_LIT> ) ; if ( MI . getDesc ( ) . getNumDefs ( ) == <NUM_LIT> ) { unsigned OldReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MFI . isVRegStackified ( OldReg ) ) { const TargetRegisterClass * RC = MRI . getRegClass ( OldReg ) ; unsigned NewReg = MRI . createVirtualRegister ( RC ) ; auto InsertPt = std :: next ( MachineBasicBlock :: iterator ( & MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . eraseFromParent ( ) ; Changed = true ; continue ; } if ( UseEmpty [ TargetRegisterInfo :: virtReg2Index ( OldReg ) ] ) { unsigned Opc = getDropOpcode ( RC ) ; MachineInstr * Drop = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( NewReg ) ; Drop -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; } else { unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ; unsigned Opc = getSetLocalOpcode ( RC ) ; BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . addImm ( LocalId ) . addReg ( NewReg ) ; } MI . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ; MFI . stackifyVReg ( NewReg ) ; Changed = true ; } } MachineInstr * InsertPt = & MI ; for ( MachineOperand & MO : reverse ( MI . explicit_uses ( ) ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned OldReg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { assert ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) ; unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ; MRI . removeRegOperandFromUseList ( & MO ) ; MO = MachineOperand :: CreateImm ( LocalId ) ; continue ; } if ( MFI . isVRegStackified ( OldReg ) ) { InsertPt = FindStartOfTree ( MO , MRI , MFI ) ; continue ; } if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) { unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ; MRI . removeRegOperandFromUseList ( & MO


<s> EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ; if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo .


<s> if ( FLOAT_MODE_P ( GET_MODE ( x ) ) ) return LOAD_FPU_REGS ; else return GENERAL_REGS ; } return


<s> static inline bool isLoopStart ( const MachineInstr & MI ) { return isDoLoopStart ( MI ) || isWhileLoopStart ( MI


<s> static DecodeStatus DecodeRUSInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Op1 , Op2 ; DecodeStatus S = Decode2OpInstruction ( Insn , Op1 , Op2 ) ; if ( S != MCDisassembler :: Success ) return Decode2OpInstructionFail ( Inst , Insn , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address ,


<s> const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } FirstReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SecondReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstReg == SecondReg ) return false ; BaseReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( * Op0 , PredReg ) ; dl = Op0 -> getDebugLoc ( ) ; return


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget . is64Bit ( ) ) return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT>


<s> if ( CB ) if ( CB -> arg_empty ( ) || ! CB -> paramHasAttr ( <NUM_LIT> , Attribute :: StructRet ) ||

CB -> paramHasAttr ( <NUM_LIT> , Attribute :: InReg ) || Subtarget -> isTargetMCU ( ) ) return <NUM_LIT> ;


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm


<s> } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) { PICBase = <STR_LIT> ; } unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( RC


<s> } } for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { unsigned RemainingCount = MBB -> size ( ) ; for ( MachineBasicBlock :: iterator RegionEnd = MBB -> end ( ) ; RegionEnd != MBB -> begin ( ) ; ) { MachineBasicBlock :: iterator I = RegionEnd ; for ( ; I != MBB -> begin ( ) ; -- I , -- RemainingCount ) { if ( TII -> isSchedulingBoundary ( * std :: prev ( I ) , & * MBB , Fn ) ) break ; } I = MBB -> begin ( ) ; if ( I == RegionEnd ) { RegionEnd = std :: prev ( RegionEnd ) ; -- RemainingCount ; continue ; } if ( I == std :: prev ( RegionEnd ) ) { RegionEnd = std :: prev ( RegionEnd ) ; continue ; } Packetizer . PacketizeMIs ( & * MBB , & * I , RegionEnd ) ; RegionEnd = I ; } } return true


<s> static void arm_init_builtins ( void ) { arm_init_tls_builtins ( )


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , FrameReg


<s> switch ( CC ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT>


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op ,


<s> break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , reg_names [ REGNO ( x ) + <NUM_LIT> ] ) ; break ; case MEM : { machine_mode mode = GET_MODE ( x ) ; x = XEXP ( adjust_address ( x , SImode , <NUM_LIT> ) , <NUM_LIT> ) ; v850_print_operand_address ( file , mode , x ) ; if ( GET_CODE ( x ) == CONST_INT ) fprintf ( file , <STR_LIT> ) ; } break ; case CONST_INT : { unsigned HOST_WIDE_INT v = INTVAL ( x ) ; v = v >> <NUM_LIT> ; v = v >> <NUM_LIT> ; fprintf ( file , HOST_WIDE_INT_PRINT_HEX , v ) ; break ; } case CONST_DOUBLE : fprintf ( file , HOST_WIDE_INT_PRINT_HEX , CONST_DOUBLE_HIGH ( x ) ) ; break ; default : debug_rtx ( x ) ; gcc_unreachable ( ) ; } break ; case 'S' : { if ( GET_CODE ( x ) == MEM && ep_memory_operand ( x , GET_MODE ( x ) , FALSE ) ) fputs ( <STR_LIT> , file ) ; break ; } case 'T' : { if ( GET_CODE ( x ) == MEM && ep_memory_operand ( x , GET_MODE ( x ) , TRUE ) ) fputs ( <STR_LIT> , file ) ; break ; } case 'W' : switch ( GET_MODE ( x ) ) { default : gcc_unreachable ( ) ; case E_QImode : fputs ( <STR_LIT> , file ) ; break ; case E_HImode : fputs ( <STR_LIT> , file ) ; break ; case E_SImode : fputs ( <STR_LIT> , file ) ; break ; case E_SFmode : fputs ( <STR_LIT> , file ) ; break ; } break ; case '.' : fputs ( reg_names [ <NUM_LIT> ] , file ) ; break ; case 'z' : if ( REG_P ( x ) ) fputs ( reg_names [ REGNO ( x ) ] , file ) ; else if ( ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == DFmode || GET_MODE ( x ) == SFmode ) && x == CONST0_RTX

( GET_MODE ( x ) ) ) fputs ( reg_names [ <NUM_LIT> ] , file ) ;


<s> for ( auto * Pred : MBB -> predecessors ( ) ) { if ( Pred != Flow && ! Blocks . contains ( Pred ) ) Blocks . insert ( Pred ) ; } if ( Cur < Blocks . size ( ) ) MBB = Blocks [ Cur ++ ] ; else MBB = nullptr ; } LLVM_DEBUG (


<s> SDLoc SL ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue BV = DAG . getBuildVector ( <STR_LIT> , SL , { Lo , Hi } ) ; return DAG . getNode ( <STR_LIT> ,


<s> void <ISA_LIT>DbgInfo :: EmitVarDebugInfo ( Module & M ) { DebugInfoFinder DbgFinder ; DbgFinder . processModule ( M ) ; for ( DebugInfoFinder :: iterator I = DbgFinder . global_variable_begin ( ) , E = DbgFinder . global_variable_end ( ) ; I != E ; ++ I ) { DIGlobalVariable DIGV ( * I ) ; DIType Ty = DIGV . getType ( ) ; unsigned short TypeNo = <NUM_LIT> ; bool HasAux = false ; int Aux [ <STR_LIT> ] = { <NUM_LIT>


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] =


<s> handlePredUse ( i , block , curLocs , FreeLocs ) ; auto definitions = block -> getDefinitions ( ) ; if ( ! definitions . empty ( ) ) { vector < unsigned > order ; for ( auto def : definitions ) { auto pred = def . predicate ; if ( curLocs . find ( pred ) == curLocs . end ( ) ) { order . push_back ( pred ) ; } } sortFurthestNextUse ( i , order ) ; for ( auto pred : order ) { Location l = getAvailLoc ( FreeLocs ) ; map < unsigned , Location > :: iterator findCurUseLoc = curLocs . find ( pred ) ; if ( findCurUseLoc == curLocs . end ( ) ) { curLocs . insert ( make_pair ( pred , l ) ) ; } else { findCurUseLoc -> second = l ; } if ( DefLocs . find ( pred )


<s> uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) Reloc = <STR_LIT> ; else Reloc = <STR_LIT> ; BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; GV -> setMetadata ( LLVMContext ::


<s> virtual unsigned getFunctionAlignment ( const Function * F ) const { return <NUM_LIT>


<s> bool UseFastISel = TM . Options . EnableFastISel && Subtarget . has<ISA_LIT>32 ( ) && ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . in<ISA_LIT>16Mode ( ) && ! Subtarget . inMicro<ISA_LIT>Mode ( ) ; if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) || Subtarget . useXGOT ( ) ) UseFastISel = false ; return UseFastISel ? <STR_LIT> ( funcInfo , libInfo ) :


<s> if ( argtypes == <NUM_LIT> ) args_from_decl = true ; else args = argtypes ; for ( i = return_in_mem ? <NUM_LIT> : <NUM_LIT> ; args != NULL_TREE ; args = TREE_CHAIN ( args ) ) { tree type = args_from_decl ? TREE_TYPE ( args ) : TREE_VALUE ( args ) ; machine_mode mode = TYPE_MODE ( type ) ; if ( mode == VOIDmode ) break ; if ( ! PASS_IN_REG_P ( mode , type ) ) mode = Pmode ; int count = maybe_split_mode ( & mode ) ; if ( count == <NUM_LIT> ) { if ( argtypes == NULL && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode


<s> static DecodeStatus DecodeFixedPointScaleImm64 ( llvm :: MCInst & Inst , unsigned Imm , uint64_t


<s> return create<ISA_LIT>HazardRecognizer ( II , DAG ,


<s> case Instruction :: Trunc : if ( ! selectCast ( I , <STR_LIT> ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , <STR_LIT> ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction


<s> void m68hc11_conditional_register_usage ( void ) { int i ; if ( m68hc11_soft_reg_count > SOFT_REG_LAST - SOFT_REG_FIRST ) m68hc11_soft_reg_count = SOFT_REG_LAST - SOFT_REG_FIRST ; for ( i = SOFT_REG_FIRST + m68hc11_soft_reg_count ; i < SOFT_REG_LAST ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ]


<s> TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; IsRelocPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify (


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI


<s> void <ISA_LIT>InstPrinter :: printVectorListOne ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) .


<s> bool SeenV2 = false ; for ( int i = MaskI ; i <= MaskE ; ++ i , ++ OpIdx ) { int Idx = SVOp -> getMaskElt ( i ) ; if ( Idx < <NUM_LIT>


<s> void push ( NodeAddr < DefNode * > DA ) { Stack . push_back ( DA


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return T . getArch ( ) == Triple :: r600 ? new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) : new <ISA_LIT>InstPrinter ( MAI , MII , MRI


<s> if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } return false


<s> return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment


<s> OS << <STR_LIT> ; emitParamList ( Sig ) ; OS << <STR_LIT> ; emitReturnList ( Sig ) ; OS << <STR_LIT>


<s> case scalar_store : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_store [ <NUM_LIT> ] : ix86_cost -> int_store [ <NUM_LIT> ] ) / <NUM_LIT> ; case vector_stmt : return ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op , true ) ; case vector_load : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_load [ index ] ) / <NUM_LIT> , true ) ; case vector_store : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_store [ index ] ) / <NUM_LIT> , true ) ; case vec_to_scalar : case scalar_to_vec : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case unaligned_load : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_load [ index ] ) / <NUM_LIT> , true ) ; case unaligned_store : index = sse_store_index ( mode ) ; if ( index < <NUM_LIT> ) index = <NUM_LIT> ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_store [ index ] ) / <NUM_LIT> , true ) ; case vector_gather_load : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> gather_static + ix86_cost -> gather_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / <NUM_LIT> , true ) ; case vector_scatter_store : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> scatter_static + ix86_cost -> scatter_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / <NUM_LIT> , true ) ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case vec_construct : { int cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , false ) ; if ( GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ) cost += ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; else if ( GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ) cost += <NUM_LIT> * ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; return cost ; } default : gcc_unreachable ( )


<s> case <NUM_LIT> : return false ; default : llvm_unreachable ( <STR_LIT> ) ; } uint32_t ExpStart = FracBits ; uint64_t FracMask = ( <NUM_LIT> << FracBits ) - <NUM_LIT> ; uint32_t Sign = Val . isNegative ( ) ; uint64_t Bits = Val . bitcastToAPInt ( ) . getLimitedValue ( ) ; uint64_t Fraction = Bits & FracMask ; int32_t Exponent = ( ( Bits >> ExpStart ) & ExpMask ) ; Exponent -= ExpMask >> <NUM_LIT> ; uint64_t A64FracStart = FracBits - <NUM_LIT> ; uint64_t A64FracMask = <NUM_LIT> ; if ( Fraction & ~ ( A64FracMask << A64FracStart ) ) return


<s> static bool nios2_large_constant_allowed ( void


<s> static SDValue adjustLoadValueTypeImpl ( SDValue Result , EVT LoadVT , const SDLoc & DL , SelectionDAG & DAG , bool Unpacked ) { if ( ! LoadVT . isVector ( ) ) return Result ; if ( Unpacked ) { EVT IntLoadVT = LoadVT .


<s> static rtx emit_addhi3_postreload ( rtx dest , rtx src0 , rtx src1 ) { rtx set , clobber , insn ; set = gen_rtx_SET ( VOIDmode , dest , gen_rtx_PLUS ( HImode , src0 , src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , CARRY_REGNUM ) ) ; insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; return insn


<s> void <ISA_LIT>InstPrinter :: printRel ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> case <STR_LIT> : if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OutStreamer . AddComment ( StringRef ( <STR_LIT> ) + <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI ) ; case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT>


<s> bool hasIntModifiers ( ) const { return getModifiers ( ) . hasIntModifiers


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register LaneVGPR = TRI -> findUnusedRegister ( MF . getRegInfo ( ) , & <STR_LIT> , MF , true ) ; if ( LaneVGPR == Register ( ) ) return false ; SpillVGPRs . push_back ( SGPRSpillVGPRCSR ( LaneVGPR , None ) ) ; FuncInfo -> VGPRReservedForSGPRSpill =


<s> if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>OptimizeExecMaskingID ) ; TargetPassConfig :: addPostRegAlloc


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ; return false


<s> Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( hasFP ( MF ) ) Reserved


<s> raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str


<s> if ( TT . getEnvironmentName ( ) == <STR_LIT> || TT . getEnvironmentName ( ) == <STR_LIT> )


<s> if ( NumLoads > <NUM_LIT> ) { VecTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast (


<s> return ( __m128i ) __builtin_ia32_pmovuswb256_mask ( ( __v16hi ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask16 ) -


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; } if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; } if ( NumBytes ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> )

. addReg ( <STR_LIT> ) . addImm ( NumBytes ) ;


<s> if ( Function * F = dyn_cast < Function > ( v ) ) return F ; if ( Instruction * I = dyn_cast < Instruction > ( v ) ) return I -> getParent ( ) -> getParent ( ) ; if ( BasicBlock * B = dyn_cast < BasicBlock > ( v ) ) return B -> getParent ( ) ; return


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue Res = tryCombineToBFI ( N , DCI , Subtarget ) ; if ( Res . getNode ( ) ) return Res ; Res = tryCombineToLargerBFI ( N , DCI , Subtarget ) ; if ( Res . getNode ( ) ) return Res ; Res = tryCombineToEXTR ( N , DCI ) ; if ( Res . getNode ( ) ) return Res ; if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal (


<s> return Reg == <STR_LIT> ? Reg : get<ISA_LIT>SubSuperRegister (


<s> static void nios2_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ATTRIBUTE_UNUSED , struct gcc_options * opts_set ATTRIBUTE_UNUSED ) { unsigned int


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> initMCCodeGenInfo ( RM , CM , OL


<s> bool fixCallImmediates ( ) const { return


<s> IsSgpr = TRI . isSGPRClass ( RC ) ; Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } DebugLoc DL = I . getDebugLoc ( ) ; const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; unsigned LoReg = MRI . createVirtualRegister ( RC ) ; unsigned HiReg = MRI . createVirtualRegister ( RC ) ; const APInt & Imm = APInt ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; const MachineInstr * RS = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; I . eraseFromParent ( ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( RS -> getOperand ( <NUM_LIT> ) ,


<s> if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = <STR_LIT> ; else if ( decl_readonly_section ( decl , <NUM_LIT> ) ) prefix = <STR_LIT> ; else prefix = <STR_LIT> ; len = strlen ( name )


<s> return nops == <NUM_LIT> ? ops [ <NUM_LIT> ] : ops


<s> inline ShiftOpc getAM2ShiftOpc ( unsigned AM2Opc ) { return ( ShiftOpc ) ( ( AM2Opc >>


<s> return ( cfun && cfun -> machine && cfun


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FrameIdx ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm (


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum


<s> SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal ) return Op ; if ( CTVal -> isAllOnes ( ) && CFVal -> isZero ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if ( CTVal -> isZero ( ) && CFVal -> isAllOnes ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; FVal = Other ; TVal = DAG . getNode ( <STR_LIT> , dl , Other . getValueType ( ) , Other , DAG . getConstant ( - <NUM_LIT> , dl ,


<s> static MCStreamer * createMachOStreamer ( MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && TAB , std :: unique_ptr

< MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll , bool DWARFMustBeAtTheEnd ) {


<s> HST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; HRI = HST -> getRegisterInfo ( ) ; SelectionDAGISel :: runOnMachineFunction (


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; addPass ( create<ISA_LIT>ConstantIslandPass (


<s> code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_GENERAL ; return add_builtin_function ( name , type , code , BUILT_IN_MD , NULL


<s> std :: swap ( V1 , V2 ) ; Swap = true ; } bool IsUndefOrZero = V2 . isUndef ( ) || isZerosVector ( V2 . getNode ( ) ) ; MVT IndexVT = <STR_LIT> ; unsigned IndexLen = <NUM_LIT> ; if ( Op . getValueSizeInBits ( ) == <NUM_LIT> ) { IndexVT = <STR_LIT> ; IndexLen = <NUM_LIT> ; } SmallVector < SDValue , <NUM_LIT> > TBLMask ; for ( int Val : ShuffleMask ) { for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; if ( Swap ) Offset = Offset < IndexLen ? Offset + IndexLen : Offset - IndexLen ; if ( IsUndefOrZero && Offset >= IndexLen ) Offset = <NUM_LIT> ; TBLMask . push_back ( DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; } } SDValue V1Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V1 ) ; SDValue V2Cst = DAG . getNode ( <STR_LIT> , DL , IndexVT , V2 ) ; SDValue Shuffle ; if ( IsUndefOrZero ) { if ( IndexLen == <NUM_LIT> ) V1Cst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Cst , V1Cst ) ; Shuffle = DAG . getNode ( <STR_LIT> , DL , IndexVT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , V1Cst , DAG . getBuildVector ( IndexVT , DL , makeArrayRef ( TBLMask . data ( ) , IndexLen ) ) ) ; }


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> ,


<s> static DecodeStatus DecodeInsSize ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; int Size = ( int ) Insn -


<s> bool <ISA_LIT>BaseInstrInfo :: ConvertToSetZeroFlag ( MachineInstr * MI , MachineInstr * CmpInstr ) const { if ( MI -> getParent ( ) != CmpInstr -> getParent ( ) ) return false ; MachineBasicBlock :: const_iterator I = CmpInstr , E = MI , B = MI -> getParent ( ) -> begin ( ) ; -- I ; for ( ; I != E ; -- I ) { const MachineInstr & Instr =


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return &


<s> RegisterMCAsmInfo < <ISA_LIT>65816MCAsmInfo > X ( The<ISA_LIT>65816Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>65816Target , create<ISA_LIT>65816MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>65816Target , create<ISA_LIT>65816MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>65816Target , create<ISA_LIT>65816MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>65816Target , create<ISA_LIT>65816MCSubtargetInfo ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>65816Target ,


<s> return isIntImmediate ( N . getNode (


<s> rtx memexp = XEXP ( src , <NUM_LIT> ) ; int dstreg = REGNO ( dst ) ; int basereg = - <NUM_LIT> ; if ( GET_CODE ( memexp ) == LABEL_REF ) return <STR_LIT> ; else if ( GET_CODE ( memexp ) == REG ) basereg = REGNO ( memexp ) ; else if ( GET_CODE ( memexp ) == PLUS ) { if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) basereg = REGNO ( XEXP ( memexp , <NUM_LIT> ) ) ; else if ( GET_CODE ( XEXP ( memexp , <NUM_LIT> ) ) == REG ) basereg = REGNO ( XEXP ( memexp , <NUM_LIT> ) ) ; else gcc_unreachable ( ) ; } else gcc_unreachable ( ) ; if ( dstreg == basereg ) { return <STR_LIT> ; } else return <STR_LIT> ; } else if ( GET_CODE ( src ) == CONST_INT ) { if ( TARGET_LITTLE_END ) { if ( CONST_OK_FOR_I ( INTVAL ( src ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CONST_OK_FOR_M ( INTVAL ( src ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CONST_OK_FOR_N ( INTVAL ( src ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else gcc_unreachable ( ) ; if ( INTVAL ( src ) < <NUM_LIT> ) return <STR_LIT> ; else return <STR_LIT> ; } else { if ( CONST_OK_FOR_I ( INTVAL ( src ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CONST_OK_FOR_M ( INTVAL ( src ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else if ( CONST_OK_FOR_N ( INTVAL ( src ) ) ) output_asm_insn ( <STR_LIT> , operands ) ; else gcc_unreachable ( ) ; if ( INTVAL ( src ) < <NUM_LIT>


<s> static bool areCFlagsAccessedBetweenInstrs ( MachineBasicBlock :: iterator From , MachineBasicBlock :: iterator To , const TargetRegisterInfo * TRI , const AccessKind AccessToCheck = AK_All ) { if ( To == To -> getParent ( ) -> begin ( ) ) return true ; if ( To -> getParent ( ) != From -> getParent ( ) ) return true ; assert ( std :: find_if ( ++ To . getReverse ( ) , To -> getParent ( ) -> rend ( ) , [ From ] ( MachineInstr & MI ) { return MI . getIterator ( ) == From ; } ) != To -> getParent ( ) -> rend ( ) ) ; for ( const MachineInstr & Instr : instructionsWithoutDebug ( ++ To . getReverse ( ) , From . getReverse ( ) ) ) { if ( ( ( AccessToCheck & AK_Write ) && Instr . modifiesRegister ( <STR_LIT> , TRI ) ) || ( ( AccessToCheck & AK_Read

) && Instr . readsRegister ( <STR_LIT> , TRI ) ) ) return true ;


<s> bool isUImm8 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm (


<s> } Register DestPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , DestPhiReg ) . addUse ( OpDestReg ) . addMBB ( TpEntry ) . addUse ( CurrDestReg ) . addMBB ( TpLoopBody ) ; Register LoopCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingLoopIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , LoopCounterPhiReg ) . addUse ( TotalIterationsReg ) . addMBB ( TpEntry ) . addUse ( RemainingLoopIterationsReg ) . addMBB ( TpLoopBody ) ; Register PredCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingElementsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , PredCounterPhiReg ) . addUse ( ElementCountReg ) . addMBB ( TpEntry ) . addUse ( RemainingElementsReg ) . addMBB ( TpLoopBody ) ; Register VccrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , VccrReg ) . addUse ( PredCounterPhiReg ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , RemainingElementsReg ) . addUse ( PredCounterPhiReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register SrcValueReg ; if ( IsMemcpy ) { SrcValueReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) ) . addDef ( CurrSrcReg ) . addDef ( SrcValueReg ) .

addReg ( SrcPhiReg ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addUse ( VccrReg ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = FuncInfo . EHRegNodeFrameIndex ; int EHRegSize = MFI -> getObjectSize ( FI ) ; if ( RestoreSP ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , true , - EHRegSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned UsedReg ; int EHRegOffset = getFrameIndexReference ( MF , FI , UsedReg ) ; int EndOffset = - EHRegOffset - EHRegSize ; FuncInfo . EHRegNodeEndOffset = EndOffset ; if ( UsedReg == FramePtr ) { unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ; } else if (


<s> SDValue <ISA_LIT>DAGToDAGISel :: createDTuple ( ArrayRef < SDValue > Regs ) { static unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT>


<s> bool <ISA_LIT>FastISel :: SelectCall ( const Instruction * I , const char * IntrMemName = nullptr ) { const CallInst * CI = cast < CallInst > ( I ) ; const Value * Callee = CI -> getCalledOperand ( ) ; if ( isa < InlineAsm > ( Callee ) ) return false ; if ( CI -> isTailCall ( ) ) return false ; CallingConv :: ID CC = CI -> getCallingConv ( ) ; FunctionType * FTy = CI -> getFunctionType ( ) ; bool isVarArg = FTy -> isVarArg ( ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < Register , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CI -> arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( auto ArgI = CI -> arg_begin ( ) , ArgE = CI -> arg_end ( ) ; ArgI != ArgE ; ++ ArgI ) { if ( IntrMemName && ArgE - ArgI <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned ArgIdx = ArgI - CI


<s> if ( TARGET_ISEL ) return rs6000_emit_int_cmove ( dest , op , true_cond , false_cond ) ; return false ; } is_against_zero = op1 == CONST0_RTX ( compare_mode ) ; if ( SCALAR_FLOAT_MODE_P ( compare_mode ) && flag_trapping_math && ! is_against_zero ) return false ; if ( code == UNLT || code == UNGT || code == UNORDERED || code == NE || code == LTGT || code == LT || code == UNLE ) { code = reverse_condition_maybe_unordered ( code ) ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; } if ( code == UNEQ && HONOR_NANS ( compare_mode ) ) return false ; if ( HONOR_INFINITIES ( compare_mode ) && code != GT && code != UNGE && ( ! CONST_DOUBLE_P ( op1 ) || real_isinf ( CONST_DOUBLE_REAL_VALUE ( op1 ) ) ) && ( ( ! rtx_equal_p ( op0 , false_cond ) && ! rtx_equal_p ( op1 , false_cond ) ) || ( ! rtx_equal_p ( op0 , true_cond ) && ! rtx_equal_p ( op1 , true_cond ) ) ) ) return false ; if ( compare_mode != SFmode && compare_mode != DFmode ) return false ; if ( ! is_against_zero ) { temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_MINUS ( compare_mode , op0 , op1 ) ) ) ; op0 = temp ; op1 = CONST0_RTX ( compare_mode ) ; } if ( ! HONOR_NANS ( compare_mode ) ) switch ( code ) { case GT : code = LE ; temp = true_cond ; true_cond = false_cond ; false_cond =


<s> unsigned <ISA_LIT>ParamManager :: addReturnParam ( Type *


<s> CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; if ( * pcum < CSKY_NPARM_REGS ) return gen_rtx_REG ( mode , CSKY_FIRST_PARM_REGNUM + *


<s> return ( Operand . isImm ( ) && ( Operand . getImm ( ) &


<s> static bool nvptx_use_anchors_for_symbol_p ( const_rtx ARG_UNUSED ( a ) ) { return false


<s> inline constexpr u16 BitReverse ( u16 value ) { u16 result = <NUM_LIT> ; for ( u32 i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i


<s> return expandAtomic ( MBB , MBBI , [ & ] ( MachineInstr & MI ) { auto DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto PtrOp = MI . getOperand ( <NUM_LIT> ) ; auto SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode , DstReg ) . addReg ( PtrOp . getReg ( ) ) ; buildMI ( MBB , MBBI , ArithOpcode , DstReg ) .


<s> void <ISA_LIT>AsmPrinter :: emitCallInstruction ( const MachineInstr * MI ) { assert ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCSubtargetInfo STI = getSubtargetInfo ( ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: makePreOp ( LPAC :: ADD ) ) , STI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; TmpInst . setOpcode (


<s> GlobalsEmitted = true ; } bool ret = AsmPrinter :: doFinalization ( M ) ; clearAnnotationCache ( & M ) ; if ( auto * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) { if ( HasDebugInfo ) { TS -> closeLastSection ( ) ; OutStreamer -> emitRawText ( <STR_LIT> ) ; } TS -> outputDwarfFileDirectives (


<s> right -> par = node -> par ; if ( node -> par == t -> rbt_nil ) t -> rbt_root = right ; else if ( node == node -> par -> left


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ; if ( Src . first == <NUM_LIT> ) continue ; if ( Vector [ Src . second ] [ Cycle ] < <NUM_LIT> ) Vector [ Src . second ] [ Cycle ] = Src . first ; if ( Vector [ Src . second ] [ Cycle ] != Src . first ) return IGSrcs . size ( ) - <NUM_LIT> ; } return IGSrcs .


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N )


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * UseMI = & * MRI -> use_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) != MBB ) return Reg ; while ( UseMI -> isCopy ( ) || UseMI -> isInsertSubreg ( ) ) { Reg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; UseMI = & * MRI -> use_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) != MBB ) return Reg ; } return Reg


<s> yaml :: MachineFunctionInfo * <ISA_LIT>TargetMachine :: convertFuncInfoToYAML ( const


<s> gimplify_assign ( ptr , call , & seq ) ; var = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( var ) = <NUM_LIT> ; } if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; if ( ! integer_zerop ( ref_to_res ) ) gimplify_assign ( build_simple_mem_ref ( ref_to_res ) , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq


<s> Func . enqueueExitBlock ( ) ; return true


<s> if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ; llvm_unreachable (


<s> assert ( MI . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand MOpSHMI = MI . getOperand ( <NUM_LIT> ) ; MachineOperand MOpMEMI = MI . getOperand ( <NUM_LIT> ) ; if ( ! ( MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; if ( SHMI + MEMI != <NUM_LIT> ) return false ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) return false ; MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI -> getOpcode ( ) != <STR_LIT> && SrcMI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SrcMI -> dump ( ) ) ; LLVM_DEBUG ( MI . dump ( ) ) ; MachineInstr * NewInstr = BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , SrcMI -> getOpcode ( ) == <STR_LIT> ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( SrcMI -> getOperand ( <NUM_LIT> ) ) . add ( MOpSHMI ) ; ( void )


<s> RTLIB :: Libcall LC = getDivRemLibcall ( N , N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( N , DAG . getContext ( ) , Subtarget ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; SDValue Callee = DAG . getExternalFunctionSymbol ( getLibcallName ( LC ) ) ; if ( Subtarget -> isTargetWindows ( ) ) InChain = WinDBZCheckDenominator ( DAG , N , InChain ) ; CallLoweringInfo CLI ( DAG ) ; CLI . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS , RetTy , Callee , std :: move ( Args ) ) . setSExtResult (

isSigned ) . setZExtResult ( ! isSigned ) . setDebugLoc ( SDLoc ( N ) ) ;


<s> return <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> ) >=


<s> unsigned <ISA_LIT>16InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI ,


<s> assert ( ( I . getOpcode ( ) == TargetOpcode :: G_CONSTANT ) && <STR_LIT> ) ; const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; if ( RBI . getRegBank ( DefReg , MRI , TRI ) -> getID ( ) != <STR_LIT> ) return false ; uint64_t Val = <NUM_LIT> ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; I . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Val ) ; } else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) { Val = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned


<s> return ( __m128i ) __builtin_ia32_pmovqw256_mask ( ( __v4di ) __A , ( __v8hi )


<s> CurrBase = Base ; CurrOpc = Opcode ; CurrPred = Pred ; MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } if ( CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred ) { bool Overlap = false ; if ( isLoadSingle ( Opcode ) ) { Overlap = ( Base == Reg ) ; if ( ! Overlap ) { for ( const MemOpQueueEntry & E : MemOps ) { if ( TRI -> regsOverlap ( Reg , E . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Overlap = true ; break ; } } } } if ( ! Overlap ) { if ( Offset > MemOps . back ( ) . Offset ) { MemOps . push_back ( MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } else { MemOpQueue :: iterator MI , ME ; for ( MI = MemOps . begin ( ) , ME = MemOps . end ( ) ; MI != ME ; ++ MI ) { if ( Offset < MI -> Offset ) { break ; } if ( Offset == MI -> Offset ) { MI = ME ; break ; } } if ( MI != MemOps . end ( ) ) { MemOps . insert ( MI , MemOpQueueEntry ( * MBBI , Offset , Position ) ) ; continue ; } } } } MBBI = I ; -- Position ; } else if ( MBBI -> isDebugInstr ( ) ) { continue ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { MergeBaseCandidates . push_back ( & * MBBI ) ; } if ( MemOps . size ( ) > <NUM_LIT> ) { FormCandidates ( MemOps ) ; CurrBase = <NUM_LIT> ; CurrOpc = ~ <NUM_LIT> ; CurrPred = <STR_LIT> ; MemOps . clear ( ) ; } } if ( MemOps . size ( ) > <NUM_LIT> ) FormCandidates ( MemOps


<s> GPRPad = NumGPRs % ( ( align + <NUM_LIT> ) / <NUM_LIT> ) ; StackPad = StackOffset % align ; unsigned firstGPR = NumGPRs + GPRPad ; switch ( ObjectVT . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else NeededStackSize = <NUM_LIT> ; break ; case <STR_LIT>


<s> bool <ISA_LIT>PrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , <NUM_LIT> , i , nullptr ) ; Modified = true ; } } } TFI . emitPrologue ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end


<s> FunctionPass * llvm :: create<ISA_LIT>PreAMXConfigPass ( ) { return new <ISA_LIT>PreAMXConfigPass (


<s> void HvxSelector :: selectVAlign ( SDNode * N ) { SDValue Vv = N -> getOperand ( <NUM_LIT> ) ; SDValue Vu = N -> getOperand


<s> return ( __m128i ) __builtin_ia32_cvttps2qq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8


<s> if ( ! NewMul ) { assert ( C -> getZExtValue ( ) != <NUM_LIT> && C -> getZExtValue ( ) != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ; if ( isPowerOf2_64 ( AbsMulAmt - <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( isPowerOf2_64 ( AbsMulAmt + <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , NewMul ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; } else if ( SignMulAmt >= <NUM_LIT> && isPowerOf2_64 ( AbsMulAmt - <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; } else if ( SignMulAmt >= <NUM_LIT> && isPowerOf2_64 ( AbsMulAmt + <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , N -> getOperand ( <NUM_LIT> ) ) ; NewMul = DAG . getNode ( <STR_LIT> , DL , VT ,


<s> SDValue Arg = OutVals [ RealResIdx ] ; if ( Subtarget . isAIXABI ( ) && ( VA . getLocVT ( ) . isVector ( ) || VA . getValVT ( ) . isVector ( ) ) ) report_fatal_error ( <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( Subtarget . hasSPE ( ) && VA . getLocVT ( ) == <STR_LIT> ) { bool isLittleEndian = Subtarget . isLittleEndian ( ) ; SDValue SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; SVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getIntPtrConstant ( isLittleEndian ? <NUM_LIT> : <NUM_LIT> , dl ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , SVal , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( )