<s> else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) == STACK_POINTER_REGNUM && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) + GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == FRAME_POINTER_REGNUM || REGNO ( XEXP ( x , <NUM_LIT> ) ) == ARG_POINTER_REGNUM || ( REGNO ( XEXP ( x , <NUM_LIT> ) ) >= FIRST_VIRTUAL_REGISTER && REGNO ( XEXP ( x , <NUM_LIT> ) ) <= LAST_VIRTUAL_POINTER_REGISTER ) ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_SIZE ( mode ) == <NUM_LIT> && GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x

) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getCondBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ,


<s> for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && ( Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> || Callee -> getName ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ; if ( ! Callee ) return UnknownCallOutlineType ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return UnknownCallOutlineType ; MachineFrameInfo & MFI = CalleeMF -> getFrameInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) || MFI . getStackSize ( ) > <NUM_LIT> || MFI . getNumObjects ( ) > <NUM_LIT> ) return UnknownCallOutlineType ; return outliner :: InstrType :: Legal ; } if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) || MI . readsRegister ( <STR_LIT> , TRI ) ) { bool MightNeedStackFixUp = ( Flags & ( MachineOutlinerMBBFlags :: LRUnavailableSomewhere | MachineOutlinerMBBFlags :: HasCalls ) ) ; if ( ! MightNeedStackFixUp ) return outliner :: InstrType :: Legal ; if ( MI . modifiesRegister ( <STR_LIT> , TRI ) ) return outliner :: InstrType :: Illegal ; if ( checkAndUpdateStackOffset ( & MI , Subtarget . getStackAlignment ( ) . value ( ) , false ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } if ( MI . readsRegister ( <STR_LIT> , TRI ) || MI . modifiesRegister ( <STR_LIT> , TRI ) ) return


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I


<s> static void arm_asm_emit_except_personality ( rtx personality ) { fputs ( <STR_LIT>


<s> if ( HasFP ) { BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) ) break ; FirstCSPop = PI ; } -- MBBI ; } MBBI = FirstCSPop ; if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG (


<s> MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> emitLabel ( MILabel ) ; SM . recordStackMap ( * MILabel , MI ) ; unsigned NumShadowBytes = MI . getOperand ( <NUM_LIT> ) . getImm


<s> static DecodeStatus DecodeGRH32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address


<s> unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & MCID = get ( Opc ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else BuildMI ( MBB , I , DL , MCID , DestReg ) . addReg ( SrcReg , getKillRegState


<s> if ( tmp == NULL_RTX ) return <NUM_LIT> ; tmp = PATTERN ( x ) ; note_stores ( PATTERN ( y ) , mep_insn_dependent_p_1 , & tmp ) ; if ( tmp == NULL_RTX ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( TII -> analyzeBranch ( * HBB , TBB , FBB , HeadCond ) ) { continue ; } if ( ! TBB || TBB == HBB ) { continue ; } SmallVector < MachineOperand , <NUM_LIT> > TrueCond ; MachineBasicBlock * TBB_TBB = nullptr , * TBB_FBB = nullptr ; if ( TII -> analyzeBranch ( * TBB , TBB_TBB , TBB_FBB , TrueCond ) ) { continue ; } MachineInstr * HeadCmpMI = findSuitableCompare ( HBB ) ; if ( ! HeadCmpMI ) { continue ; } MachineInstr * TrueCmpMI = findSuitableCompare ( TBB ) ; if ( ! TrueCmpMI ) { continue ; } <STR_LIT> HeadCmp ; if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { bool adjustHeadCond = ( HeadImm < TrueImm


<s> if ( c < <NUM_LIT> ) c += <NUM_LIT> ; fprintf ( file , <STR_LIT> , c ) ; if ( i < size - <NUM_LIT> ) putc


<s> return ( ( ( insn ) & <NUM_LIT> ) ==


<s> for ( auto & MO : MI -> memoperands ( ) ) if ( MO ->

isVolatile ( ) || MO -> isAtomic ( ) ) return true ;


<s> unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) ; & * I != MI ; ++ I ) { assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> getInstSizeInBytes (


<s> static inline <STR_LIT> getMemExtendType ( unsigned Imm ) { return getExtendType ( ( Imm >> <NUM_LIT> ) & <NUM_LIT>


<s> case <STR_LIT> : return lowerV4F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I8VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; default : llvm_unreachable ( <STR_LIT>


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT>


<s> std :: reverse ( RVLocs . begin ( ) , RVLocs . end (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true


<s> static inline bool equal ( tree_map * a , tree_map * b ) { return a -> base . from == b -> base


<s> return ( __m256 ) __builtin_ia32_unpckhps256_mask ( ( __v8sf ) __A , ( __v8sf ) __B , (


<s> case MachineOperand :: MO_ConstantPoolIndex : return AP . GetCPISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return AP . GetJTISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_BlockAddress : return AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; default : llvm_unreachable (


NODE_NAME_CASE ( GREVIW ) NODE_NAME_CASE ( GORCI ) NODE_NAME_CASE ( GORCIW ) }


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printS16ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << ( short ) MI -> getOperand ( OpNo ) .


<s> static bool msp430_no_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; int i ; if ( msp430_hwmult_type == NONE ) return true ; if ( msp430_hwmult_type != AUTO ) return false ; if ( target_mcu == NULL ) return true


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X (


<s> CounterPropagateAddr ( * Clause . first , CfCount ) ; MachineBasicBlock * BB = Clause . first -> getParent ( ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addImm


<s> if ( ! TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT ( decl ) )

DECL_VISIBILITY ( decl ) = VISIBILITY_HIDDEN ;


<s> instr_iterator CmpIt = CmpI , NextIt = std :: next ( CmpIt ) ; for ( instr_iterator I = NextIt , E = BB -> instr_end ( ) ; I != E ; ++ I ) { MachineInstr * In = & * I ; for ( unsigned i = <NUM_LIT> , n = In -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = In -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUse ( ) ) { if ( MO . getReg ( ) == PredR ) return false ; } } if ( In == BumpI ) { instr_iterator After =


<s> MachineInstr * MI1 = Arguments -> MI ; MachineInstr * MI2 = & * NextMII ; Register RegDstMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RegSrcMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! IsMovepSrcRegister ( RegSrcMI1 ) ) return false ; if ( ! IsMovepDestinationReg ( RegDstMI1 ) ) return false ; if ( MI2 -> getOpcode ( ) != Entry


<s> IsResolved = true ; ( void ) adjustFixupValue ( Fixup , Value , & Asm . getContext


<s> OpFlag = <STR_LIT> ; } else if ( Subtarget . isPICStyleStubNoDynamic ( ) ) { OpFlag = <STR_LIT> ; } auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget . is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false


<s> else scale = copy_to_mode_reg ( SImode , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_zero_extendpsisi2 ( temp1 , operands [ <NUM_LIT> ] ) ) ; temp2 = expand_simple_binop ( SImode , MULT , temp1 , scale , temp2 , <NUM_LIT> , OPTAB_LIB ) ; emit_insn ( gen_truncsipsi2 ( operands [ <NUM_LIT> ] , temp2 )


<s> uint8_t llvmRegnums [ ] = { ALL_REGS <NUM_LIT> } ; uint8_t llvmRegnum = llvmRegnums [ reg ] ; mcInst . addOperand ( MCOperand :: createReg ( llvmRegnum


<s> static int32_t adjustUp ( int32_t V , uint8_t A , uint8_t O ) { assert ( isPowerOf2_32 ( A


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo


<s> return ( __m256i ) __builtin_ia32_packusdw256 ( ( __v8si )


<s> SDValue getAddrLocal ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , bool IsN32OrN64 ) const { unsigned GOTFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty ,


<s> SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , OffsVT ) ; int64_t val ; switch ( N . getOpcode ( ) ) { case <STR_LIT> : val = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) -> getSExtValue ( ) ; Base = CurDAG -> getTargetConstant ( val , <STR_LIT> ) ; Index = Zero ; return true ; break ; case <STR_LIT> : case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>_CCState :: MarkAllocated ( unsigned Reg ) { UsedRegs [ Reg / <NUM_LIT> ] |= <NUM_LIT>


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> unsigned FPDiff = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>RegNumbering


<s> <ISA_LIT>_LOG ( <STR_LIT> ) ; return false


<s> <ISA_LIT>PostRASchedStrategy ( const MachineSchedContext * C ) : MLI ( C -> MLI ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( C -> MF -> getSubtarget ( ) . getInstrInfo ( ) ) ) , MBB ( nullptr ) , HazardRec ( nullptr ) { const TargetSubtargetInfo * ST = & C


<s> rtl_opt_pass * make_pass_analyze_swaps ( gcc :: context *


<s> uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; EVT VecVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; return Index / NumElemsPerChunk


<s> TypeSize <ISA_LIT>TTIImpl :: getRegisterBitWidth ( TargetTransformInfo :: RegisterKind K ) const { return TypeSize :: getFixed ( <NUM_LIT>


<s> Register CarryOut = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CarryIn = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ShiftOpcode , RotateOpcode ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ShiftOpcode = <STR_LIT> ; RotateOpcode = <STR_LIT> ; break ; case <STR_LIT> : ShiftOpcode = <STR_LIT> ; RotateOpcode = <STR_LIT> ; break ; } MachineIRBuilder Builder ( MI ) ; if ( mi_match ( CarryIn , * Builder . getMRI ( ) , m_SpecificICst ( <NUM_LIT> ) ) ) { auto Asl = Builder . buildInstr ( ShiftOpcode , { Dst , CarryOut } , { Src } ) ; if ( ! constrainSelectedInstRegOperands ( * Asl , TII , TRI , RBI ) ) return false ; } else


<s> SmallString < <NUM_LIT> > SymbolName ; getNameWithPrefix ( SymbolName , MF -> getFunction ( ) ) , getTargetStreamer ( ) . Emit<ISA_LIT>SymbolType ( SymbolName , ELF :: STT_<ISA_LIT>_HSA_KERNEL ) ; } AsmPrinter :: EmitFunctionEntryLabel


<s> bool LRUsed = MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) ; const TargetRegisterClass * RC = <STR_LIT> ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( LRUsed ) { MF . getRegInfo ( ) . setPhysRegUnused ( <STR_LIT> ) ; bool isVarArg = MF . getFunction ( ) -> isVarArg ( ) ; int FrameIdx ; if ( ! isVarArg ) { FrameIdx = MFI -> CreateFixedObject ( RC -> getSize ( ) , <NUM_LIT> , true ) ; } else { FrameIdx = MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; } XFI -> setUsesLR ( FrameIdx ) ; XFI -> setLRSpillSlot ( FrameIdx ) ; } if ( RegInfo -> requiresRegisterScavenging ( MF ) ) { RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment


<s> if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) .


<s> for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) Changed |=


<s> return gen_rtx_REG ( mode , MOXIE_R0


<s> for ( unsigned i = <NUM_LIT> , e = Use -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = Use -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Defs . count ( Reg )


<s> if ( NewOp . getNode ( ) ) return NewOp ; SDValue InputVector = N -> getOperand ( <NUM_LIT> ) ; if ( InputVector . getNode ( ) -> getOpcode ( ) == llvm :: <STR_LIT> && InputVector . getNode ( ) -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( InputVector ) , N -> getValueType ( <NUM_LIT> ) , InputVector . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( InputVector . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > Uses ; unsigned ExtractedElements = <NUM_LIT> ; for ( SDNode :: use_iterator UI = InputVector . getNode ( ) -> use_begin ( ) , UE = InputVector . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != InputVector . getResNo ( ) ) return SDValue ( ) ; SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) ->


<s> bool <ISA_LIT>HSATargetObjectFile :: isProgramAllocation ( const GlobalValue * GV ) const { return <STR_LIT> ( GV ) && ! isAgentAllocation (


<s> static unsigned size ( const GraphType & G ) { return G . getNodes ( ) .


<s> unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . addOperand ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; BuildMI ( * MBB , MI , DL , TII -> get ( IJmpOpc ) ) . addReg ( Tmp ) ; MI . eraseFromParent (


<s> void <ISA_LIT>InstPrinter :: printCCOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned CC = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT>


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask


<s> assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB

) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> BoundsInformation ( const std :: string & boundsfile ) { parseBoundsFile ( boundsfile ) ; appendDefaultConstraitns (


<s> if ( op_const & <NUM_LIT> ) return build_int_cst ( alpha_dimode_u , opint [ <NUM_LIT> ] & mask ) ; if ( op ) return fold_build2 ( BIT_AND_EXPR , alpha_dimode_u , op [ <NUM_LIT> ] , build_int_cst ( alpha_dimode_u , mask ) ) ; } else if ( ( op_const & <NUM_LIT> ) && opint [ <NUM_LIT> ] == <NUM_LIT> ) return build_int_cst ( alpha_dimode_u , <NUM_LIT> ) ; return


<s> if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return CSR_O32_SaveList


<s> void <ISA_LIT>AsmPrinter :: emitConstantPool ( ) { emitDecls ( * MMI -> getModule ( ) ) ; assert ( MF -> getConstantPool ( ) -> getConstants ( ) . empty (


<s> const MachineInstr * MI = SU -> getInstr ( ) ; return MI && TII -> isSALU ( * MI )


<s> int Elt = SV -> getMaskElt ( Index ) ; if ( Elt < <NUM_LIT> ) return DAG . getUNDEF ( VT . getVectorElementType ( ) ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? SV -> getOperand ( <NUM_LIT> ) : SV -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = V . getValueType ( ) . getSimpleVT ( ) ; unsigned NumElems = ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , ShuffleMask ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < <STR_LIT> , <NUM_LIT> > & Outs = CLI . Outs ; SmallVector < SDValue , <NUM_LIT> > & OutVals = CLI . OutVals ; SmallVector < <STR_LIT> , <NUM_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; isTailCall = false ; switch ( CallConv )


<s> bool SelectArithShiftedRegister ( SDValue N , SDValue & Reg , SDValue & Shift ) { return SelectShiftedRegister ( N , false , Reg


<s> if ( ( e . flag & FUNC_DISINTERRUPT ) && ! ( e . used & FUNC_DISINTERRUPT ) ) warning ( <NUM_LIT> , <STR_LIT> , s ) ; return <NUM_LIT>


<s> if ( ! GVKind . isGlobalWriteableData ( ) && ! GVKind . isReadOnly ( ) && ! GVKind . isThreadLocal ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( isVerbose ( ) ) { if ( GV -> hasInitializer ( ) ) { GV -> printAsOperand ( OutStreamer -> GetCommentOS ( ) , false , GV -> getParent ( ) ) ; OutStreamer -> GetCommentOS ( ) << '\n' ; } } MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GV -> hasCommonLinkage ( ) || GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getValueType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Register ResVReg = createTypeVReg ( MIRBuilder ) ; auto MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( ResVReg ) . addUse ( get<ISA_LIT>TypeID ( SampledType ) ) . addImm ( Dim ) . addImm ( Depth ) . addImm ( Arrayed ) . addImm ( Multisampled ) . addImm ( Sampled ) . addImm ( ImageFormat ) . addImm ( AccessQual ) ; DT . add ( TD , & MIRBuilder . getMF ( ) , ResVReg ) ; return MIB


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT ,

StringRef CPU , const MCTargetOptions & Options ) {


<s> MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Dest ) ; } unsigned ReturnReg = ( PtrVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock * DestMBB = cast < BasicBlockSDNode > ( Dest ) -> getBasicBlock ( ) ; BlockAddress * BA = BlockAddress :: get ( const_cast < Function * > ( MF . getFunction ( ) ) , const_cast < BasicBlock * > ( DestMBB -> getBasicBlock ( ) ) ) ; DestMBB -> setHasAddressTaken ( ) ; SDValue BlockPtr = DAG . getBlockAddress


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb1Only ( ) ? <NUM_LIT> :


<s> void <ISA_LIT>AsmBackend :: RelaxInstruction ( const MCInst & Inst , MCInst & Res ) const { Res = Inst


<s> static SDValue constructDup ( SDValue V , int Lane , SDLoc dl , EVT VT , unsigned Opcode , SelectionDAG & DAG ) { auto getScaledOffsetDup = [ ] ( SDValue BitCast , int & LaneC , MVT & CastVT ) { if ( BitCast . getOpcode ( ) != <STR_LIT> || BitCast . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Extract = BitCast . getOperand ( <NUM_LIT> ) ; unsigned ExtIdx = Extract . getConstantOperandVal ( <NUM_LIT> ) ; unsigned SrcEltBitWidth = Extract . getScalarValueSizeInBits ( ) ; unsigned ExtIdxInBits = ExtIdx * SrcEltBitWidth ; unsigned CastedEltBitWidth = BitCast . getScalarValueSizeInBits ( ) ; if ( ExtIdxInBits % CastedEltBitWidth != <NUM_LIT> ) return false ; LaneC += ExtIdxInBits / CastedEltBitWidth ; unsigned SrcVecNumElts = Extract . getOperand ( <NUM_LIT>

) . getValueSizeInBits ( ) / CastedEltBitWidth ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new


<s> std :: unique_ptr < MCObjectTargetWriter > create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return std :: make_unique < <ISA_LIT>ELFObjectWriter >


<s> unsigned addWorkGroupIDZ ( ) { WorkGroupIDZSystemSGPR = getNextSystemSGPR ( ) ; NumSystemSGPRs += <NUM_LIT>


<s> void <ISA_LIT>LowerControlFlowPass :: Branch ( MachineInstr & MI ) { if ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) == MI . getParent ( )

-> getNextNode ( ) ) MI . eraseFromParent ( ) ;


<s> if ( Subtarget . isAIXABI ( ) ) report_fatal_error ( <STR_LIT> ) ; return TOCSaveOffset


<s> unsigned int nregs = REG_NREGS ( reg ) ; while ( nregs -- > <NUM_LIT> ) if ( ( i + nregs ) == regno ) return false ; reg = crtl -> return_bnd ; if ( reg ) { i = REGNO ( reg ) ; nregs = REG_NREGS ( reg ) ; while ( nregs -- > <NUM_LIT> ) if ( ( i + nregs ) == regno ) return false ; } } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; SchedModel = MF . getSubtarget ( ) . getSchedModel ( ) ; MRI = & MF . getRegInfo (


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim (

MF ) && MFI -> adjustsStack ( ) ) return true ;


<s> static void rx_elf_asm_destructor ( rtx symbol , int priority ) { rx_elf_asm_cdtor ( symbol , priority


<s> const MCRegisterInfo * MRI = getMRI ( ) ; const MCRegisterClass & VGPR32 = MRI -> getRegClass ( <STR_LIT> ) ; const MCRegisterClass & AGPR32 = MRI -> getRegClass ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = Inst . getNumOperands ( ) ; I != E ; ++ I ) { const MCOperand & Op = Inst . getOperand ( I ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Sub = MRI -> getSubReg ( Op . getReg ( ) ,


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_CondCode , Ctx ) ; Op -> CondCode . Code =


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadInstructions ; for ( MachineInstr & MI : MBB . instrs ( ) ) { if ( isVCTP ( & MI ) ) { HasVCTP = true ; continue ; } if ( ! HasVCTP || MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; ( void ) MIBuilder ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump ( ) ) ; DeadInstructions . push_back (


<s> <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; MCRegister Reg = Op . getReg ( ) ; bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 (


<s> int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue (


<s> void setWorkItemIDY ( ArgDescriptor Arg


<s> isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs , const BranchProbability & Probability ) const { return ( NumInstrs <= <NUM_LIT>


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const { return getTargetTriple ( ) . isiOS ( ) && ! getTargetTriple

( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; return lowerShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( V2 . isUndef ( ) && ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { SDValue VPermMask = getConstVector ( Mask , <STR_LIT> , DAG , DL , true ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1


<s> if ( parseSwizzleOperands ( LANE_NUM , Lane , <NUM_LIT> , LANE_MAX , <STR_LIT> ) ) { Imm = QUAD_PERM_ENC ; for ( auto i = <NUM_LIT> ; i < LANE_NUM ; ++ i ) { Imm |= Lane [ i ] << ( LANE_SHIFT * i ) ; } return


<s> assert ( Op . getValueType ( ) == MemVT && <STR_LIT> ) ; SDValue Src2 = Node -> getVal ( ) ; SDValue NegSrc2 ; SDLoc DL ( Src2 ) ; if ( auto * Op2 = dyn_cast < ConstantSDNode > ( Src2 ) ) { int64_t Value = ( - Op2 -> getAPIntValue ( ) ) . getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Value ) || TM . getSubtargetImpl ( ) -> hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getConstant ( Value , MemVT ) ; } else if ( TM . getSubtargetImpl ( ) -> hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getNode ( <STR_LIT> , DL , MemVT , DAG . getConstant ( <NUM_LIT> , MemVT ) , Src2 ) ; if ( NegSrc2 . getNode ( ) ) return DAG . getAtomic ( <STR_LIT> , DL , MemVT , Node -> getChain ( ) , Node -> getBasePtr ( ) , NegSrc2 , Node -> getMemOperand ( ) , Node -> getOrdering ( ) , Node -> getSynchScope ( ) ) ; return


<s> SDLoc DL ( MS ) ; SDValue Value = MS -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; EVT CastVT = VT . changeVectorElementType ( EltVT ) ; Value = DAG . getBitcast ( CastVT , Value ) ; } SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT , Value , VecIndex ) ; return DAG . getStore ( MS -> getChain ( ) , DL , Extract , Addr , MS -> getPointerInfo ( ) . getWithOffset ( Offset ) , Alignment , MS -> getMemOperand ( ) ->


<s> return ; } if ( CurrCycleInstr -> isImplicitDef ( ) || CurrCycleInstr -> isDebugInstr ( ) || CurrCycleInstr -> isKill ( ) ) { CurrCycleInstr = nullptr ; return ; } if ( CurrCycleInstr -> isBundle ( ) ) { processBundle ( ) ; return ; } unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr =


<s> OS << getName ( ) << '(' ; getSubExpr ( ) -> print


<s> } maxshift = innersize * <NUM_LIT> ; if ( isleftshift ) { if ( last_elt >= maxshift ) return <NUM_LIT> ; } else { if ( last_elt == <NUM_LIT> || last_elt > maxshift ) return <NUM_LIT> ; } if ( elementwidth ) * elementwidth = innersize * <NUM_LIT> ; if ( modconst ) * modconst = CONST_VECTOR_ELT ( op , <NUM_LIT> ) ; return <NUM_LIT>


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? &


<s> bool hasBank ( ) const { return Bank != ~


<s> auto result = getScopeBlocks ( ) ; auto subheaders = Priv -> getSubheaders ( ) ; result . insert ( result . end ( ) , subheaders . begin ( ) , subheaders . end


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; unsigned Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) -> getReg ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . addReg ( Reg , getDefRegState ( ! IsStore ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMemRefs (

MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> int Imm ; unsigned Opc ; <STR_LIT> Cmp ; std :: tie ( Imm , Opc , Cmp ) = Info ; MachineBasicBlock * const MBB = CmpMI -> getParent ( ) ; BuildMI ( * MBB , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; CmpMI -> eraseFromParent ( ) ; MachineInstr * BrMI = MBB -> getFirstTerminator ( ) ; BuildMI ( * MBB , BrMI , BrMI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( Cmp ) . addOperand ( BrMI -> getOperand ( <NUM_LIT> ) ) ; BrMI -> eraseFromParent ( ) ; MBB -> updateTerminator


<s> unsigned getVmcntBitShiftLo ( unsigned VersionMajor ) { return VersionMajor >= <NUM_LIT> ? <NUM_LIT>


<s> if ( GET_CODE ( p1 ) == CONST_INT ) { if ( ( GET_CODE ( p0 ) == UNSPEC ) ) return false ; if ( ( GET_CODE ( p0 ) == SYMBOL_REF || GET_CODE ( p0 ) == LABEL_REF ) && ( microblaze_tls_symbol_p ( p0 ) || ! SMALL_INT ( p1 )


<s> uint64_t SrcB = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuSrcBStart , <ISA_LIT>II :: SpuSrcBSize ) ; uint64_t Dest = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuDestStart , <ISA_LIT>II :: SpuDestSize ) ; uint64_t OpType = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuOpTypeStart , <ISA_LIT>II :: SpuOpTypeSize ) ; uint64_t Switches = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuSwitchesStart , <ISA_LIT>II :: SpuSwitchesSize ) ; uint64_t Predicate = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuPredicateStart , <ISA_LIT>II :: SpuPredicateSize ) ; bool Polarity = ( bool ) fieldFromInstruction ( insn , <ISA_LIT>II :: SpuPolarityBit , <NUM_LIT> ) ; Inst . setOpcode (


<s> if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <=


<s> static Target The<ISA_LIT>Target ; return


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; const APFloat K0Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K0 = DAG . getConstantFP ( K0Val , <STR_LIT> ) ; const APFloat K1Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K1 = DAG . getConstantFP ( K1Val , <STR_LIT> ) ; const SDValue One = DAG . getTargetConstantFP ( <NUM_LIT> , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) ; SDValue r2 = DAG . getSetCC ( SL , SetCCVT , r1


<s> std :: pair < OutputIt1 , OutputIt2 > copy_if_else ( InputIt First , InputIt Last , OutputIt1 d1 , OutputIt2 d2 , UnaryPredicate Predicate ) { for ( InputIt I = First ; I != Last ; ++ I ) { if ( Predicate ( * I ) ) { * d1 = * I ; d1 ++ ; } else


<s> RefinementSteps = <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue (


<s> return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode (


<s> EmittedInstrs . push_front ( nullptr )


<s> case TargetOpcode :: G_SHL : return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT>


<s> return __builtin_mve_vcvtq_m_to_f_uv8hf ( __inactive ,


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseCoprocNumOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ( hasV7Ops ( ) || hasV8Ops ( ) ) && ( Num == <NUM_LIT> || Num == <NUM_LIT> ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num , S


<s> case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; case <STR_LIT> : CondCode = <STR_LIT> ; break ; } } <ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; if ( isSignedComparison ( CondCode ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS


<s> if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; } } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N ->


<s> case STACK_POINTER_REGNUM : rv += cfun -> machine -> framesize_outgoing ; rv += cfun -> machine -> framesize_locals ; case FRAME_POINTER_REGNUM : rv += cfun -> machine -> framesize_regs ; rv += <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } switch ( from ) { case FRAME_POINTER_REGNUM : rv -= <NUM_LIT> ; rv -= cfun -> machine


<s> MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BB = copy0MBB


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) { Register TempReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( DestReg ) . addGlobalAddress ( GV , <NUM_LIT> ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex


<s> return HSAMD :: Kernel :: DebugProps :: Metadata


<s> unsigned <ISA_LIT>16InstrInfo :: GetAnalyzableBrOpc ( unsigned Opc )


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> ShaderType == ShaderType :: PIXEL || MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> ShaderType == ShaderType :: GEOMETRY ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: V_CMPX_LE_F32_e32 ) , AMDGPU :: VCC ) . addImm ( <NUM_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent


<s> NVVMReflect ( ) : FunctionPass ( ID ) { initializeNVVMReflectPass ( * PassRegistry ::


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return emitAddSub_ri ( false , RetVT , LHSReg , LHSIsKill


<s> bool empty ( ) const { return TopLevelExceptions . empty (


<s> static llvm :: once_flag InitializeRegisterBankFlag ; static auto InitializeRegisterBankOnce = [ & ] ( ) { const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT>


<s> static bool isPALIGNRMask ( ArrayRef < int > Mask , MVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ( VT . is128BitVector ( ) && ! Subtarget -> hasSSSE3 ( ) ) || ( VT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) ) || VT . is512BitVector ( ) ) return false ; return isAlignrMask ( Mask , VT , false


<s> bool <ISA_LIT>AsmParser :: parseParenSuffix ( StringRef Name , OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex


<s> else { mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; } gcc_assert ( REG_P ( reg_1 ) && REG_P ( reg_2 ) ) ; if ( REGNO ( reg_1 ) != REGNO ( reg_2 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ) return false ; if ( ! extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1


<s> unsigned postOffset ( unsigned LogAlign = <NUM_LIT> ) const { unsigned PO = Offset + Size ; unsigned Align = <NUM_LIT> << LogAlign ; return ( PO + Align - <NUM_LIT> ) / Align


<s> bool AMDGPUInstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const { return false


<s> int main ( void ) { for ( const avr_mcu_t * mcu = avr_mcu_types ; mcu -> name ; mcu ++ ) print_mcu ( mcu ) ; return EXIT_SUCCESS


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X (


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Op0 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( ! Op1 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) ,


<s> assert ( Value == <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int )


<s> if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( VRM && VRM -> hasPhys ( MO . getReg ( ) ) ) { Register PhysReg = VRM -> getPhys ( MO . getReg ( ) ) ; if ( <STR_LIT> . contains ( PhysReg ) ) return & <STR_LIT> ; assert ( <STR_LIT> . contains ( PhysReg ) && <STR_LIT> ) ; return &


<s> int size ; if ( cfun -> machine -> frame_info . initialized ) return cfun -> machine -> frame_info . total_size ; frame_info = & cfun -> machine -> frame_info ; size = ARC_STACK_ALIGN ( get_frame_size ( ) ) ; var_size = size ; args_size = crtl -> outgoing_args_size ; reg_size = <NUM_LIT> ; gmask = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( arc_must_save_register ( regno , cfun ) ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } } if ( crtl -> calls_eh_return ) for ( regno = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( regno ) != INVALID_REGNUM ; regno ++ ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) || crtl -> calls_eh_return ) ; if ( optimize_size && ! TARGET_NO_MILLICODE_THUNK_SET && ! crtl -> calls_eh_return ) { if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ; } extra_size = <NUM_LIT> ; if ( arc_must_save_return_addr ( cfun ) ) extra_size = <NUM_LIT> ; if ( arc_frame_pointer_needed ( ) ) extra_size += <NUM_LIT> ; pretend_size = crtl -> args . pretend_args_size ; { unsigned int extra_plus_reg_size ; unsigned int extra_plus_reg_size_aligned ; extra_plus_reg_size = extra_size + reg_size ; extra_plus_reg_size_aligned = ARC_STACK_ALIGN ( extra_plus_reg_size ) ; reg_size = extra_plus_reg_size_aligned - extra_size ; } total_size = var_size + args_size + extra_size + pretend_size + reg_size ; gcc_assert ( total_size == ARC_STACK_ALIGN ( total_size ) ) ; reg_offset = ( total_size - ( pretend_size + reg_size + extra_size ) + ( arc_frame_pointer_needed ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; frame_info -> total_size = total_size ; frame_info -> extra_size = extra_size ; frame_info -> pretend_size = pretend_size ; frame_info -> var_size = var_size ; frame_info -> args_size = args_size ; frame_info -> reg_size = reg_size ; frame_info -> reg_offset = reg_offset ; frame_info -> gmask =


<s> if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( Op . getToken ( ) , FBS , <NUM_LIT> ) ; return Error ( IdLoc , <STR_LIT> + Suggestion ) ; } } if ( MatchResult > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IdLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( MatchResult ) { case Match_InvalidBitfield : case Match_InvalidBitfieldWidth : case Match_InvalidBitfieldOffset : case Match_InvalidPixelRotationSize : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , getMatchKindDiag ( ( <ISA_LIT>MatchResultTy ) MatchResult ) ) ; } } llvm_unreachable ( <STR_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { --


<s> if ( I -> getScalarSizeInBits ( ) * cast < FixedVectorType > ( I ) -> getNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) + getMemoryOpCost ( Instruction :: Load , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) ; } return * Cost . getValue


<s> return ( __m128i ) __builtin_ia32_cvttps2uqq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8


<s> if ( MCID . Opcode == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } unsigned Binary = getBinaryCodeForInstr ( MI


<s> static SDValue LowerVASTART ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MF . getFrameInfo ( ) -> setFrameAddressIsTaken ( true ) ; SDLoc DL ( Op ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , DL , TLI . getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , TLI .

getPointerTy ( ) ) , DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) ) ) ;


<s> Sext = true ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } auto Res = parseRegOrImm ( Operands ) ; if ( Res != MatchOperand_Success ) { return Res ; } <ISA_LIT>Operand :: Modifiers Mods = { false , false , false } ; if ( Sext ) { if ( getLexer ( ) . isNot ( AsmToken ::


<s> int first_anon_arg ; gcc_assert ( mode != BLKmode ) ; first_anon_arg = * cum + ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; if ( first_anon_arg < MAX_ARC_PARM_REGS && ! no_rtl ) { int first_reg_offset = first_anon_arg ; int size = MAX_ARC_PARM_REGS - first_reg_offset ; int align_slop =


<s> } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? <STR_LIT> : <STR_LIT> ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) . getInstr ( ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Value ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex (


<s> case CallingConv :: C : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv ::


<s> return ( m_SectionData -> size ( ) >


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > ( OpKind :: DataType


<s> while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . getOpcode ( ) == TargetInstrInfo :: INLINEASM ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( EnableRegisterScavenging ) if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } MI . getOperand ( FIOperandNo ) . ChangeToRegister ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( EnableRegisterScavenging ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg = <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addReg ( SReg , false , false , true ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetInstrInfo :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode


<s> void \ fini_section ( ) \ { \ if ( in_section != in_fini ) \ { \ fprintf ( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ; \ in_section = in_fini


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; StackPtr = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) || Subtarget -> hasAVX ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( )


<s> case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , dl , VT , R , BaseShAmt , DAG ) ; } case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , dl , VT , R , BaseShAmt , DAG ) ; } case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getTargetVShiftNode ( <STR_LIT> , dl , VT , R , BaseShAmt , DAG ) ; } } } } if ( ! Subtarget -> is64Bit ( ) && ( VT == <STR_LIT> || ( Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) ) && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue > Vals ( Ratio ) ; for ( unsigned i = <NUM_LIT> ; i != Ratio ; ++ i ) Vals [ i ] = Amt . getOperand ( i ) ; for ( unsigned i = Ratio ; i != Amt . getNumOperands ( ) ; i += Ratio ) { for ( unsigned j = <NUM_LIT> ; j != Ratio ; ++ j ) if ( Vals [ j ] != Amt . getOperand ( i + j ) ) return SDValue ( ) ; } switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , R , Op . getOperand ( <NUM_LIT> ) ) ; } } return SDValue ( )


<s> SDLoc DL ( Op ) ; AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == AtomicOrdering :: SequentiallyConsistent && FenceScope == CrossThread ) { return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand (


<s> else memindex = <NUM_LIT> , regindex = <NUM_LIT> , offset = ( index + <NUM_LIT> ) * - <NUM_LIT> ; if ( GET_CODE ( x ) == SET && GET_CODE ( XEXP ( x , regindex ) ) == REG && GET_CODE ( XEXP ( x , memindex ) ) == MEM && h8300_stack_offset_p ( XEXP ( XEXP ( x , memindex )

, <NUM_LIT> ) , offset ) ) return REGNO ( XEXP ( x , regindex ) ) ;


<s> isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB


<s> case <STR_LIT> : case <STR_LIT> : if ( shouldWidenToHvx ( ty ( Op . getOperand ( <NUM_LIT> ) ) , DAG ) ) { if ( SDValue T = WidenHvxExtend ( Op , DAG ) ) Results . push_back ( T ) ; } break ; case <STR_LIT> : if ( shouldWidenToHvx ( ty ( Op . getOperand ( <NUM_LIT> ) ) , DAG ) ) { if ( SDValue T = WidenHvxSetCC ( Op , DAG ) ) Results . push_back ( T ) ; } break ; case <STR_LIT> : if ( shouldWidenToHvx ( ty ( Op . getOperand ( <NUM_LIT> ) ) , DAG ) ) { if ( SDValue T = WidenHvxTruncate ( Op , DAG ) ) Results . push_back ( T ) ; } break ; case <STR_LIT> : { if ( shouldWidenToHvx ( ty ( cast < StoreSDNode > ( N ) -> getValue ( ) ) , DAG ) ) { SDValue Store = WidenHvxStore ( Op , DAG ) ; Results . push_back ( Store ) ; } break ; } case <STR_LIT> : if ( isHvxPairTy ( ty ( Op ) ) ) { SDValue S = SplitHvxMemOp ( Op , DAG ) ; assert ( S -> getOpcode ( ) == <STR_LIT> ) ; Results . push_back ( S . getOperand ( <NUM_LIT> ) ) ; Results . push_back ( S . getOperand ( <NUM_LIT> ) ) ; } break ; case <STR_LIT>


<s> void <ISA_LIT>HazardRecognizer :: RecedeCycle ( ) { PacketNum ++ ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PacketNum << <STR_LIT> ) ; dumpCurPacket ( ) ; clearResources (


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; const GlobalValue * GV = MO . getGlobal


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } } } return false


<s> vmode = aarch64_preferred_simd_mode ( mode ) ; rtx op_v = aarch64_simd_gen_const_vector_dup ( vmode ,


<s> static void arc_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { rtx symbol = XEXP ( rtl , <NUM_LIT> ) ; int flags = SYMBOL_REF_FLAGS ( symbol ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) : NULL_TREE ) ; tree long_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree medium_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree short_call_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( long_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_LONG_CALL ; else if ( medium_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_MEDIUM_CALL ; else if ( short_call_attr != NULL_TREE ) flags |= SYMBOL_FLAG_SHORT_CALL ; SYMBOL_REF_FLAGS ( symbol ) = flags ; } else if ( TREE_CODE ( decl ) == VAR_DECL ) { rtx symbol = XEXP ( rtl , <NUM_LIT> ) ; tree attr = ( TREE_TYPE ( decl ) != error_mark_node ? DECL_ATTRIBUTES ( decl ) : NULL_TREE ) ; tree sec_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( sec_attr ) { const char * sec_name = TREE_STRING_POINTER ( TREE_VALUE ( TREE_VALUE ( sec_attr ) ) ) ; if ( strcmp ( sec_name , <STR_LIT> ) == <NUM_LIT> || strcmp ( sec_name , <STR_LIT> ) == <NUM_LIT> || strcmp ( sec_name , <STR_LIT> ) == <NUM_LIT> )

SYMBOL_REF_FLAGS ( symbol ) |= SYMBOL_FLAG_CMEM ;


<s> if ( isCall ( Inst , & IsIndirectCall ) ) { if ( PendingCall ) report_fatal_error ( <STR_LIT> ) ; EmitBundleLock ( true ) ; if ( IsIndirectCall ) { unsigned TargetReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitMask ( TargetReg , IndirectBranchMaskReg , STI ) ; } <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; PendingCall = true ; return ; } if ( PendingCall ) { <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; EmitBundleUnlock ( )


<s> return ( __m128i ) __builtin_ia32_extracti32x4_256_mask ( ( __v8si ) __A , __imm , (

__v4si ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; EverMadeChange = false ; bool FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; bool YMMUsed = FnHasLiveInYmm ; if ( ! YMMUsed ) { const TargetRegisterClass * RC = & <STR_LIT> ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } } if ( ! YMMUsed ) { return false ; } assert ( BlockStates . empty ( ) && DirtySuccessors . empty ( ) && <STR_LIT> ) ; BlockStates . resize ( MF . getNumBlockIDs ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) processBasicBlock ( * I ) ; if ( FnHasLiveInYmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; } } BlockStates . clear


<s> assert ( MFI . getCalleeSavedInfo ( ) . empty ( ) && <STR_LIT> ) ; if ( ! needsSP ( MF , MFI ) ) return ; uint64_t StackSize = MFI . getStackSize ( ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . begin ( ) ; DebugLoc DL ; const TargetRegisterClass * PtrRC = MRI . getTargetRegisterInfo ( ) -> getPointerRegClass ( MF ) ; unsigned Zero = MRI . createVirtualRegister ( PtrRC ) ; unsigned SPReg = MRI . createVirtualRegister ( PtrRC ) ; const char * ES = <STR_LIT> ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , Zero ) . addImm ( <NUM_LIT> ) ; MachineMemOperand * LoadMMO = MF . getMachineMemOperand ( MachinePointerInfo ( MF . getPSVManager ( ) . getExternalSymbolCallEntry ( ES ) ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , StackSize ? SPReg : ( unsigned ) <STR_LIT> ) . addExternalSymbol ( SPSymbol ) . addReg ( Zero ) . addImm ( <NUM_LIT> ) . addMemOperand ( LoadMMO ) ; if ( StackSize ) { unsigned OffsetReg = MRI . createVirtualRegister (


<s> static bool s390_adjust_loop_scan_osc ( struct loop * loop ) { HARD_REG_SET modregs , newregs ; rtx_insn * insn , * store_insn = NULL ; rtx set ; struct s390_address addr_store , addr_load ; subrtx_iterator :: array_type array ; int insn_count ; CLEAR_HARD_REG_SET ( modregs ) ; insn_count = <NUM_LIT> ; FOR_BB_INSNS_REVERSE ( loop -> latch , insn ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= <NUM_LIT> ) continue ; insn_count ++ ; if ( insn_count > S390_OSC_SCAN_INSN_NUM ) return false ; find_all_hard_reg_sets ( insn , & newregs , true ) ; IOR_HARD_REG_SET ( modregs , newregs ) ; set = single_set ( insn ) ; if ( ! set


<s> Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , DAG . getUNDEF ( WideVecVT ) , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } Vec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Vec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec


<s> if ( Kind != k_Register || Reg . Kind != RegKind :: Scalar ) return DiagnosticPredicateTy :: NoMatch ; if ( isGPR64 < RegClassID > ( ) && getShiftExtendType ( ) == <STR_LIT> && getShiftExtendAmount ( ) == Log2_32 ( ExtWidth / <NUM_LIT> ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy ::


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emit<ISA_LIT>WinUnwindCode ( unsigned UnwindCode , int Reg , int Offset ) { auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; MCSymbol * Label = S . emitCFILabel ( ) ; auto Inst = WinEH :: Instruction ( UnwindCode , Label


<s> FQ -> copyFastMathFlags ( Builder . getFastMathFlags ( ) ) ; Value * FQNeg = Builder . CreateFNeg ( FQ ) ; Value * FR = Builder . CreateIntrinsic ( <STR_LIT> , { FQNeg -> getType ( ) } , { FQNeg , FB , FA } , FQ ) ; Value * IQ = IsSigned ? Builder . CreateFPTo<ISA_LIT> ( FQ , I32Ty ) : Builder . CreateFPToUI ( FQ , I32Ty ) ; FR = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FR , FQ ) ; FB = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FB , FQ ) ; Value * CV = Builder . CreateFCmpOGE ( FR , FB ) ; JQ = Builder . CreateSelect ( CV , JQ , Builder . getInt32 ( <NUM_LIT> ) ) ; Value * Div = Builder . CreateAdd ( IQ , JQ ) ; Value * Res = Div ; if ( ! IsDiv ) { Value * Rem = Builder . CreateMul ( Div , Den ) ; Res = Builder . CreateSub ( Num , Rem ) ; } if ( DivBits != <NUM_LIT> && DivBits < <NUM_LIT> ) { if ( IsSigned ) { int InRegBits = <NUM_LIT> - DivBits ; Res = Builder . CreateShl ( Res , InRegBits ) ; Res = Builder . CreateAShr ( Res , InRegBits ) ; } else { ConstantInt * TruncMask = Builder . getInt32 ( ( UINT64_C ( <NUM_LIT> ) <<


<s> switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case


<s> std :: string ArchFS = Parse<ISA_LIT>Triple ( TT , CPU ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , ArchFS


<s> unsigned GCNRegBankReassign :: getPhysRegBank ( unsigned Reg ) const { assert ( Register :: isPhysicalRegister ( Reg ) ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; if ( Size == <NUM_LIT> ) Reg = TRI -> get32BitRegister ( Reg ) ; else if ( Size > <NUM_LIT> ) Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; if ( TRI -> hasVGPRs ( RC ) ) { Reg -= <STR_LIT> ; return Reg % NUM_VGPR_BANKS ; } Reg = TRI -> getEncodingValue (


<s> initialize<ISA_LIT>LongBranchPass ( PR ) ; initialize<ISA_LIT>LDCleanupPass ( PR ) ; initialize<ISA_LIT>ShortenInstPass ( PR ) ; initialize<ISA_LIT>PostRewritePass ( PR )


<s> unsigned getMaxInterleaveFactor ( ) const { return hasVInstructions ( ) ? MaxInterleaveFactor :


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .

addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> if ( wasInITBlock && hasV8Ops ( ) && isThumb ( ) && ! isV8EligibleForIT ( & Inst ) ) { Warning ( IDLoc , <STR_LIT> ) ; } } forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ; if ( isITBlockFull ( ) || isITBlockTerminator ( Inst ) ) flushPendingInstructions ( Out ) ; } else { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV8 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_ImmRange0_239 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32


<s> if ( isRegIdx ( ) ) LLVM_DEBUG ( dbgs ( ) << __func__ << <STR_LIT> << RegIdx . RegInfo -> getName ( RegIdx . RealRegister ) << <STR_LIT> << RegIdx . RealRegister << <STR_LIT> << Result << <STR_LIT> ) ; return Result


<s> getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ; return


<s> op2 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movbisi ( op2 , gen_rtx_REG ( BImode , REG_CC ) ) ) ; } emit_insn ( gen_flag_machi_parts_acconly ( a1reg , tmp2 , tmp1 , const1_rtx , const0_rtx , a1reg , const0_rtx , GEN_INT ( MACFLAG_M ) ) ) ; emit_insn ( gen_ashrpdi3 ( a1reg , a1reg , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_sum_of_accumulators ( target , a0reg , a0reg , a1reg ) ) ; if ( fcode == BFIN_BUILTIN_MULT_1X32X32NS ) emit_insn ( gen_addsi3 ( target , target , op2 ) ) ; return target ; case BFIN_BUILTIN_CPLX_MUL_16 : case BFIN_BUILTIN_CPLX_MUL_16_S40 : arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; accvec = gen_reg_rtx ( V2PDImode ) ; icode = CODE_FOR_flag_macv2hi_parts ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != V2HImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , V2HImode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! register_operand ( op0 , GET_MODE ( op0 ) ) ) op0 = copy_to_mode_reg ( GET_MODE ( op0 ) , op0 ) ; if ( ! register_operand ( op1 , GET_MODE ( op1 ) ) ) op1 = copy_to_mode_reg ( GET_MODE ( op1 ) , op1 ) ; if ( fcode == BFIN_BUILTIN_CPLX_MUL_16 ) emit_insn ( gen_flag_macinit1v2hi_parts ( accvec , op0 , op1 , const0_rtx , const0_rtx , const0_rtx , const1_rtx , GEN_INT ( MACFLAG_W32 ) ) ) ; else emit_insn ( gen_flag_macinit1v2hi_parts ( accvec , op0 , op1 , const0_rtx , const0_rtx , const0_rtx , const1_rtx , GEN_INT ( MACFLAG_NONE ) ) ) ; emit_insn ( gen_flag_macv2hi_parts ( target , op0 , op1 , const1_rtx , const1_rtx , const1_rtx , const0_rtx , accvec , const1_rtx , const0_rtx , GEN_INT ( MACFLAG_NONE ) , accvec ) ) ; return target ; case BFIN_BUILTIN_CPLX_MAC_16 : case BFIN_BUILTIN_CPLX_MSU_16 : case BFIN_BUILTIN_CPLX_MAC_16_S40 : case BFIN_BUILTIN_CPLX_MSU_16_S40 : arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; op2 = expand_normal ( arg2 ) ; accvec = gen_reg_rtx ( V2PDImode ) ; icode = CODE_FOR_flag_macv2hi_parts ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != V2HImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , V2HImode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! register_operand ( op1 , GET_MODE ( op1 ) ) ) op1 = copy_to_mode_reg ( GET_MODE ( op1 ) , op1 ) ; if ( ! register_operand ( op2 , GET_MODE ( op2 ) ) )


<s> else if ( strncmp ( name , either_prefix , strlen ( either_prefix ) ) == <NUM_LIT> ) name += strlen ( either_prefix ) ; return default_section_type_flags ( decl , name ,


<s> EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; if ( Subtarget . isABI_N64 ( ) ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrTy , Offset ) ; Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ; return DAG . getStore ( ChainIn , DL , Value , Address , MachinePointerInfo (


<s> bool <ISA_LIT>AsmParser :: parseDirectiveObjectArch ( SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false


<s> for ( MachineInstr & MI : MRI . reg_nodbg_instructions ( Reg ) ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return true


<s> uint32_t <ISA_LIT>PrintfInfo :: getOperandID (


<s> assemble_name ( file , label ) ; fputc ( '\n' , file ) ; } while ( mi_delta != <NUM_LIT> ) { if ( ( mi_delta & ( <NUM_LIT> << shift ) ) == <NUM_LIT> ) shift += <NUM_LIT> ; else { asm_fprintf ( file , <STR_LIT> , mi_op , this_regno , this_regno , mi_delta & ( <NUM_LIT> << shift ) ) ; mi_delta &= ~ ( <NUM_LIT> << shift ) ; shift += <NUM_LIT> ; } } if ( TARGET_THUMB ) { fprintf ( file , <STR_LIT> ) ; ASM_OUTPUT_ALIGN ( file , <NUM_LIT> ) ; assemble_name ( file , label ) ; fputs ( <STR_LIT> , file ) ; assemble_integer ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> , BITS_PER_WORD , <NUM_LIT> ) ; } else { fputs ( <STR_LIT> , file ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( NEED_PLT_RELOC ) fputs ( <STR_LIT> , file ) ; fputc ( '\n' , file


<s> } } return TTI :: TCC_Basic ; } assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; auto * VTy = dyn_cast < FixedVectorType > ( Src ) ; if ( ! VTy || ! LT . second . isVector ( ) ) return LT . first * <NUM_LIT> ; bool IsLoad = Opcode == Instruction :: Load ; Type * EltTy = VTy -> getElementType ( ) ; const int EltTyBits = DL . getTypeSizeInBits ( EltTy ) ; InstructionCost Cost = <NUM_LIT> ; const unsigned SrcNumElt = VTy -> getNumElements ( ) ; int NumEltRemaining = SrcNumElt ; auto NumEltDone = [ & ] ( ) { return SrcNumElt - NumEltRemaining ; } ; const int MaxLegalOpSizeBytes = divideCeil ( LT . second . getSizeInBits ( ) , <NUM_LIT> ) ; const unsigned XMMBits = <NUM_LIT> ; if ( XMMBits % EltTyBits != <NUM_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; const int NumEltPerXMM = XMMBits / EltTyBits ; auto * XMMVecTy = FixedVectorType :: get ( EltTy , NumEltPerXMM ) ; for ( int CurrOpSizeBytes = MaxLegalOpSizeBytes , SubVecEltsLeft = <NUM_LIT> ; NumEltRemaining > <NUM_LIT> ; CurrOpSizeBytes /= <NUM_LIT> ) { if ( ( <NUM_LIT> * CurrOpSizeBytes ) % EltTyBits != <NUM_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; int CurrNumEltPerOp = ( <NUM_LIT> * CurrOpSizeBytes ) / EltTyBits ; assert ( CurrOpSizeBytes > <NUM_LIT> && CurrNumEltPerOp > <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( ( NumEltRemaining * EltTyBits ) < ( <NUM_LIT> * <NUM_LIT> * CurrOpSizeBytes ) ) || ( CurrOpSizeBytes == MaxLegalOpSizeBytes ) ) && <STR_LIT> <STR_LIT> ) ; auto * CurrVecTy = CurrNumEltPerOp > NumEltPerXMM ? FixedVectorType :: get ( EltTy , CurrNumEltPerOp ) : XMMVecTy ; assert ( CurrVecTy -> getNumElements ( ) % CurrNumEltPerOp


<s> __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2df ( __o , ( float64x2_t ) val . val


<s> if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( SubVecTy ) ) && <STR_LIT> ) ; auto Mask = SVI -> getShuffleMask ( ) ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { Int8Ptr , SubVecTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { if ( StoreCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , LaneLen * Factor ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned i = <NUM_LIT> ; i <


<s> if ( ! isa < PointerType > ( Arg -> getType ( ) ) ) { for ( Instruction :: use_iterator UI = Arg -> use_begin ( ) ; UI != Arg -> use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First


<s> if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) ) return true ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; else if ( auto * Cast = dyn_cast < CastInst > ( V ) ) { if ( isa < ZExtInst > ( Cast ) ) return Cast -> getDestTy ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ; else if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return Trunc -> getDestTy ( ) -> getScalarSizeInBits ( ) <= TypeSize ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( ! isa < BinaryOperator > ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false


<s> const MCExpr * Disp = MCConstantExpr :: create ( Offset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; EmitLEA ( * Op , <NUM_LIT> , <STR_LIT> , Out ) ; OrigSPOffset +=


<s> Inst . addOperand ( MCOperand :: CreateReg


<s> case <STR_LIT> : case <STR_LIT> : return combineSIntToFP ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineVTRUNC ( N , DAG , DCI ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineCVTPH2PS ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineEXTEND_VECTOR_INREG ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorHADDSUB ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> Vec = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; Vec = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; } else


<s> std :: vector < std :: string > max2_vtr_movh ( Bx a , Ax b , ArRn1 c , ArStep1 cs ) { return D ( <STR_LIT> , R ( a ) , R ( b ) , <STR_LIT>

, <STR_LIT> , R ( a ) , MemARS ( c , cs ) ) ;


<s> if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( got_register_rtx && regno == REGNO ( got_register_rtx ) ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM ||

regno == RETURN_ADDR_REGNUM ) ) return true ;


<s> return ( int16x4_t ) __builtin_aarch64_shaddv4hi ( __a ,


<s> Inner -> Parent = Simple ; if ( Blocks . size ( ) > <NUM_LIT> ) { Blocks . remove ( Inner ) ; GetBlocksOut ( Inner , NextEntries , & Blocks ) ; BlockSet JustInner ; JustInner . insert ( Inner ) ; for ( const auto & iter : NextEntries ) Solipsize ( iter ,

Branch :: Direct , Simple , JustInner ) ;


<s> SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = IsN64 ? <STR_LIT> : <STR_LIT> ; SDValue CP = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , GOTFlag ) ; CP = DAG . getNode ( <STR_LIT> , dl , ValTy , CP ) ; SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue CPLo = DAG . getTargetConstantPool ( C , ValTy , N -> getAlignment ( ) , N -> getOffset ( ) , OFSTFlag ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , ValTy , CPLo ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , ValTy


<s> if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; } O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << getRegisterName ( MO2 . getReg ( ) ) ; printRegImmShift ( O , <STR_LIT> ( MO3 . getImm ( ) ) , <STR_LIT> ( MO3 .


<s> DEBUG ( dbgs ( ) << <STR_LIT> << Blocks [ <NUM_LIT> ] -> getNumber ( ) ; ) ; for ( unsigned i = <NUM_LIT> , e = Blocks . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = Blocks [ i ] ; if ( A == MBB ) return false ; } MachineInstr * Def = MRI -> getVRegDef ( MO -> getReg


<s> materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { <ISA_LIT>FunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg )

. addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile *

> ( getTargetMachine ( ) . getObjFileLowering ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr ,

MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ;


<s> ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( ! mnemonicIsValid ( Name , <NUM_LIT> ) ) { Parser . eatToEndOfStatement ( ) ; return Error ( NameLoc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc ,


<s> if ( Offset == <NUM_LIT> ) return Idx -> getReg ( ) ; Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp ) . add ( * Idx ) . addImm ( Offset ) ; return Tmp


<s> unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT>


<s> if ( ! Size ) { Size = Info . Type * <NUM_LIT> ; if ( Size ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ) ; } } BaseReg = BaseReg ? BaseReg : <NUM_LIT> ; return <STR_LIT> ( SegReg , Disp , BaseReg , IndexReg , Scale ,

Start , End , Size , Identifier , Info . OpDecl ) ;


<s> if ( insn == NULL ) continue ; insn = prev_active_insn ( insn ) ; if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next ) && ( NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION || NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION ) ) insn = next ; else break ; emit_insn_after ( gen_nops ( const1_rtx ) , insn