<s> rtx temp_reg = create_temp_reg_if_possible ( Pmode , reg ) ; tilegx_compute_pcrel_address ( temp_reg , orig ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; address = temp_reg ; emit_move_insn ( reg , address ) ; return reg ; } else { rtx temp_reg = create_temp_reg_if_possible ( Pmode , reg ) ; gcc_assert ( flag_pic ) ; if ( flag_pic == <NUM_LIT> ) { if ( TARGET_32BIT ) { emit_insn ( gen_add_got16_32bit ( temp_reg , tilegx_got_rtx ( ) , orig ) ) ; } else { emit_insn ( gen_add_got16 ( temp_reg , tilegx_got_rtx ( ) , orig ) ) ; } } else { rtx temp_reg2 = create_temp_reg_if_possible ( Pmode , reg ) ; rtx temp_reg3 = create_temp_reg_if_possible ( Pmode , reg ) ; if ( TARGET_32BIT ) { emit_insn ( gen_mov_got32_step1_32bit ( temp_reg3 , orig ) ) ; emit_insn ( gen_mov_got32_step2_32bit ( temp_reg2 , temp_reg3 , orig ) ) ; } else { emit_insn ( gen_mov_got32_step1 ( temp_reg3 , orig ) ) ; emit_insn ( gen_mov_got32_step2 ( temp_reg2 , temp_reg3 , orig ) ) ; } emit_move_insn ( temp_reg , gen_rtx_PLUS ( Pmode , tilegx_got_rtx ( ) , temp_reg2 ) ) ; } address = temp_reg ; pic_ref = gen_const_mem ( Pmode , address ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; emit_move_insn ( reg ,


<s> if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT>


<s> <ISA_LIT>DisassemblerBase ( STI , Info ,


<s> case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } MachineFunction & MF = * SU -> getInstr ( ) -> getParent ( ) -> getParent ( ) ; auto & QII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == <NUM_LIT> ) continue ; if ( QII . mayBeCurLoad ( * Packet [ i ] -> getInstr ( ) ) ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return


<s> unsigned getOpSize ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved


<s> unsigned getCacheLineSize ( ) { return


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv2di ( ( int64x2_t )


<s> RegisterTargetMachine < <ISA_LIT>beTargetMachine > Y ( The<ISA_LIT>beTarget ) ; RegisterTargetMachine < <ISA_LIT>leTargetMachine > Z ( TheARM64Target ) ; auto PR = PassRegistry :: getPassRegistry ( )


<s> if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > <NUM_LIT> && CmpVal <= Low ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal < Low ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( CmpVal == Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High ) { if ( CCMask == <STR_LIT> ) return <STR_LIT> ; if ( CCMask == <STR_LIT> ) return <STR_LIT> ; } if ( Mask == Low + High ) { if ( CCMask == <STR_LIT> && CmpVal == Low ) return <STR_LIT> ; if ( CCMask == <STR_LIT> && CmpVal == Low


<s> void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const { if ( isReg ( ) )


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ; for ( unsigned J = I -> getDesc ( ) . getNumOperands ( ) , E = I -> getNumOperands ( ) ; J < E ; ++ J ) { const MachineOperand & MO = I -> getOperand ( J ) ; if ( MO . isMCSymbol ( ) && ( MO . getTargetFlags ( ) & <STR_LIT> ) ) MIB . addSym ( MO . getMCSymbol ( ) , <STR_LIT> ) ; } } else { for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps (


<s> static DecodeStatus DecodeDDDRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr ,


<s> void setVTYPE ( <STR_LIT> L , unsigned S , bool TA , bool MA ) { assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ; VLMul =


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; const unsigned NumFields = <NUM_LIT> ; SDValue Fields [ NumFields ] = { DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo ( SV , Offset ) , false , false , <NUM_LIT> ) ; Offset +=


<s> ++ i ; } if ( ( word_cnt == <NUM_LIT> ) && ( print_ra == <NUM_LIT> ) ) continue ; if ( word_cnt > <NUM_LIT> ) { sprintf ( one_inst_str , <STR_LIT> , word_cnt , reg_names [ start_reg ] ) ; if ( print_ra ) strcat ( one_inst_str , <STR_LIT> ) ; } else strcat ( one_inst_str , <STR_LIT> ) ; if ( push_or_pop == <NUM_LIT> ) { if ( print_ra && ! cr16_interrupt_function_p ( ) && ! crtl -> calls_eh_return ) strcpy ( temp_str , <STR_LIT> ) ; else strcpy ( temp_str , <STR_LIT> ) ; strcat ( temp_str , one_inst_str ) ; strcat ( return_str , temp_str ) ; } else { strcpy ( temp_str , <STR_LIT> ) ; strcat ( temp_str , one_inst_str ) ; strcat ( temp_str , return_str ) ; strcpy ( return_str , temp_str ) ; } } if ( push_or_pop == <NUM_LIT> ) { if ( cr16_interrupt_function_p ( ) ) strcat ( return_str , <STR_LIT> ) ; else if ( crtl -> calls_eh_return ) { strcat ( return_str , <STR_LIT> ) ; strcat ( return_str , <STR_LIT> ) ; strcpy ( temp_str , <STR_LIT> ) ; strcat ( temp_str , return_str ) ; strcpy ( return_str , temp_str ) ; } else if ( ! FUNC_IS_NORETURN_P ( current_function_decl ) && ! ( current_frame_info . save_regs [ RETURN_ADDRESS_REGNUM ] ) ) strcat ( return_str , <STR_LIT> ) ; } return_str += <NUM_LIT> ; return


<s> Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount = nullptr


<s> const LLT SrcTy = MRI . getType ( SrcReg ) ; unsigned SubIdx = <STR_LIT> ; if ( ! DstTy . isVector ( ) || ! SrcTy . isVector ( ) ) return false ; assert ( SrcTy . getSizeInBits ( ) > DstTy . getSizeInBits ( ) && <STR_LIT> ) ; if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else return false ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstReg , MRI ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcReg , MRI ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubIdx ) ; return


<s> int cr16_interrupt_function_p ( void ) { tree attributes ; attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; return ( lookup_attribute ( <STR_LIT> ,


<s> if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; return


<s> MCRegister DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Src2Reg == DstReg ) return true ; const MCRegisterInfo * TRI = getContext ( ) . getRegisterInfo ( ) ; if ( TRI -> getRegClass ( Desc . OpInfo [ <NUM_LIT> ] . RegClass ) . getSizeInBits ( ) <= <NUM_LIT> ) return true ; if ( isRegIntersect ( Src2Reg , DstReg , TRI ) ) { Error ( getRegLoc ( mc2PseudoReg ( Src2Reg ) , Operands ) , <STR_LIT> ) ; return false


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return


<s> TailPaddingAmount <ISA_LIT>TargetLowering :: getTailPaddingForPreciseBounds ( uint64_t Size ) const { if ( ! Subtarget . isCheri (


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int EltIdx = MaskVals [ i ] ; EltIdx = ( EltIdx < <NUM_LIT> ) ? <NUM_LIT> : EltIdx - <NUM_LIT> ; pshufbMask . push_back ( DAG . getConstant ( EltIdx , <STR_LIT> ) ) ; } V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 , V2 ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 ) ; SDValue NewV = V1 ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { int Elt0 = MaskVals [ i * <NUM_LIT> ] ; int Elt1 = MaskVals [ i * <NUM_LIT> + <NUM_LIT> ] ; if ( Elt0 < <NUM_LIT> && Elt1 < <NUM_LIT> ) continue ; if ( ( Elt0 == i * <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; SDValue Elt0Src = Elt0 < <NUM_LIT> ? V1 : V2 ; SDValue Elt1Src = Elt1 < <NUM_LIT> ? V1 : V2 ; SDValue InsElt ; if ( ( Elt0 >= <NUM_LIT> ) && ( ( Elt0 + <NUM_LIT> ) == Elt1 ) && ( ( Elt0 & <NUM_LIT> ) == <NUM_LIT> ) ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; continue ; } if ( Elt1 >= <NUM_LIT> ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; if ( ( Elt1 & <NUM_LIT> ) == <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( InsElt . getValueType ( ) ) ) ) ; else if ( Elt0 >= <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( Elt0 >= <NUM_LIT> ) { SDValue InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt0Src , DAG . getIntPtrConstant ( Elt0 / <NUM_LIT> ) ) ; if ( ( Elt0 & <NUM_LIT> ) != <NUM_LIT> ) InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt0 , DAG . getConstant (

<NUM_LIT> , TLI . getShiftAmountTy ( InsElt0 . getValueType ( ) ) ) ) ;


<s> const Function * F = MF -> getFunction ( ) ; const Type * Rt = F -> getReturnType ( ) ; if ( ! Rt -> isVoidTy ( ) || ! F -> arg_empty ( ) ) { for ( const Argument & A : F -> args ( ) ) OS << <STR_LIT> << toString ( A . getType ( ) , hasAddr64 ) << ')' ; if ( ! Rt -> isVoidTy ( ) ) OS << <STR_LIT> << toString ( Rt , hasAddr64 ) << ')' ; OutStreamer -> EmitRawText ( OS .


<s> SmallVector < MachineOperand , <NUM_LIT> > Copy ( Cond . begin ( ) , Cond . end ( ) ) ; Cond . clear ( ) ; CCPair CondTuple ; if ( Cond . size ( ) == <NUM_LIT> ) CondTuple = std :: make_tuple ( ( <STR_LIT> ) Copy [ <NUM_LIT> ] . getImm ( ) , ( bool ) Copy [ <NUM_LIT> ] . getImm ( ) , <STR_LIT> , false ) ; else if ( Cond . size ( ) == <NUM_LIT> ) CondTuple = std :: make_tuple ( ( <STR_LIT> ) Copy [ <NUM_LIT> ] . getImm ( ) , ( bool ) Copy [ <NUM_LIT> ] . getImm ( ) , ( <STR_LIT> ) Copy [ <NUM_LIT> ] . getImm ( ) , ( bool ) Copy [ <NUM_LIT> ] . getImm ( ) ) ; unsigned CPClass = CCPair2CPClass . at ( CondTuple ) ; unsigned SwappedClass = swapCPClass ( CPClass ) ; CondTuple = CPClass2CCPairs . at ( SwappedClass ) . at ( <NUM_LIT> ) ; if ( std :: get < <NUM_LIT> > ( CondTuple ) != <STR_LIT> ) { Cond . push_back ( MachineOperand :: CreateImm ( std :: get < <NUM_LIT> > ( CondTuple ) ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( std :: get < <NUM_LIT> > ( CondTuple ) ) ) ; } Cond . push_back ( MachineOperand :: CreateImm ( std :: get < <NUM_LIT> > ( CondTuple ) ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( std :: get < <NUM_LIT> >


<s> if ( ! MO . isReg ( ) ) continue ; if ( Register :: isPhysicalRegister ( Reg ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( TRI . regsOverlap ( Reg , MO . getReg ( ) ) ) return true ; } else if ( MO . getReg ( ) == Reg && Register :: isVirtualRegister ( Reg ) ) { LaneBitmask Overlap = TRI . getSubRegIndexLaneMask ( SubReg ) & TRI . getSubRegIndexLaneMask ( MO .


<s> if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = CodeModel :: Large ; else if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error (


<s> if ( const BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( BA -> getBlockAddress ( ) , Op . getValueType ( ) , <NUM_LIT> , TF ) ; if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , ES -> getValueType ( <NUM_LIT> ) , TF ) ; llvm_unreachable (


<s> parse_codes result = PC_OK ; diag = & ovld_diag ; if ( ! advance_line ( ovld_file ) ) return PC_OK ; while ( result == PC_OK ) result = parse_ovld_stanza ( ) ; if ( result ==


<s> Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = <NUM_LIT> ; if ( ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return true ; } } return false


<s> const MCInstrDesc & Desc = MII . get ( Inst . getOpcode ( ) ) ; for ( unsigned J = <NUM_LIT> ; J < Desc . getNumDefs ( ) ; ++ J ) { ( ( <ISA_LIT>Operand & ) * Operands [ I ++ ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; } if ( <STR_LIT> ( Opc , <STR_LIT> :: src0_modifiers ) != - <NUM_LIT> ) { for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( isRegOrImmWithInputMods ( Desc , Inst . getNumOperands ( ) ) ) { Op . addRegOrImmWithFPInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImmModifier ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else if ( Op . isRegOrImm ( ) ) { Op . addRegOrImmOperands ( Inst , <NUM_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } } else { for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isMod


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> APInt Imm = FPImm . bitcastToAPInt ( ) ; uint64_t Sign = Imm . lshr ( <NUM_LIT> ) . getZExtValue ( ) & <NUM_LIT> ; int64_t Exp = ( Imm . lshr ( <NUM_LIT> ) . getSExtValue ( ) & <NUM_LIT> ) - <NUM_LIT> ; uint64_t Mantissa = Imm . getZExtValue ( ) & <NUM_LIT> ; if ( Mantissa & <NUM_LIT> ) return - <NUM_LIT> ; Mantissa >>= <NUM_LIT> ; if ( ( Mantissa & <NUM_LIT> ) != Mantissa ) return - <NUM_LIT> ; if ( Exp < - <NUM_LIT> || Exp > <NUM_LIT> ) return - <NUM_LIT> ; Exp = ( ( Exp + <NUM_LIT> ) & <NUM_LIT> )


<s> static SDValue performORCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ; if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return SHFL ; } return combineSelectAndUseCommutative ( N ,


<s> if ( Flags . isByVal ( ) && VA . isMemLoc ( ) ) { const unsigned Size = alignTo ( Flags . getByValSize ( ) ? Flags . getByValSize ( ) : PtrByteSize , PtrByteSize ) ; const int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , VA . getLocMemOffset ( ) , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; continue ; } if ( Flags . isByVal ( ) ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; const MCPhysReg ArgReg = VA . getLocReg ( ) ; const <ISA_LIT>FrameLowering * FL = Subtarget . getFrameLowering ( ) ; if ( Flags . getNonZeroByValAlign ( ) > PtrByteSize ) report_fatal_error ( <STR_LIT> ) ; const unsigned StackSize = alignTo ( Flags . getByValSize ( ) , PtrByteSize ) ; const int FI = MF . getFrameInfo ( ) . CreateFixedObject ( StackSize , mapArgRegToOffsetAIX ( ArgReg , FL ) , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; const TargetRegisterClass * RegClass = Is<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; auto HandleRegLoc = [ & , RegClass , LocVT ] ( const MCPhysReg PhysReg , unsigned Offset ) { const unsigned VReg = MF . addLiveIn ( PhysReg , RegClass ) ; SDValue CopyFrom = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; SDValue Store = DAG . getStore ( CopyFrom . getValue ( <NUM_LIT> ) , dl , CopyFrom , DAG . getObjectPtrOffset ( dl , FIN , Offset ) , MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) ) ; MemOps . push_back ( Store ) ; } ; unsigned Offset = <NUM_LIT> ; HandleRegLoc ( VA . getLocReg ( ) , Offset ) ; Offset += PtrByteSize ; for ( ; Offset != StackSize && ArgLocs [ I ] . isRegLoc ( ) ; Offset += PtrByteSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; const CCValAssign RL = ArgLocs [ I ++ ] ; HandleRegLoc ( RL . getLocReg ( ) , Offset ) ; } if ( Offset != StackSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; assert ( ArgLocs [ I ] . isMemLoc ( ) && <STR_LIT> ) ; ++ I ; } continue ; } EVT ValVT = VA . getValVT ( )


<s> bool <ISA_LIT>Subtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ( ! isThumb ( ) || hasV8MBaselineOps (


<s> auto * User = cast < Instruction > ( U . getUser ( ) ) ; if ( auto * UserPN = dyn_cast < PHINode > ( User ) ) if ( UserPN -> getIncomingBlock ( U ) == & BB ) continue ; if ( DT . dominates ( & I , User ) ) continue ; SSA . AddUse ( VarID , &


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter >


<s> const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return


<s> SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , GA ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( N , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , Ty , DAG , Subtarget -> isABI_N32 ( ) || Subtarget -> isABI_N64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( ) ) ; return getAddrGlobal ( N , Ty , DAG , ( Subtarget -> isABI_N32 ( ) || Subtarget -> isABI_N64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( )


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( MO1 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << TRI -> getAsmName ( MO1 . getReg ( ) ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO2


<s> for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( Op . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( Opcode != <NUM_LIT> ) { SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumOperands ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue New = DAG . getNode ( Opcode , dl , VTs , & Ops [ <NUM_LIT> ] , NumOperands ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG .

getConstant ( <NUM_LIT> , Op . getValueType ( ) ) ) ;


<s> ~ <ISA_LIT>Disassembler ( ) override { if ( MII )


<s> SDValue FPRoundFlag = DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( Op ) ) ; SDValue FPRound = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IntToFp32 , FPRoundFlag ) ; return FPRound ; } if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP32


<s> return ( __m256i ) __builtin_ia32_expandloadqi256_maskz ( ( const __v32qi * ) __B , ( __v32qi


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( __m128i ) __builtin_ia32_vpcomfalsed ( ( __v4si ) __A , ( __v4si )


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( N -> getOperand ( i ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; return true


<s> BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII ->


<s> Result = ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( bit6 ) Result |= <NUM_LIT> << <NUM_LIT> ; else Result |= <NUM_LIT> << <NUM_LIT> ; } return APInt ( N , Result


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , MO . getExpr ( ) ,


<s> int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; int DTNumber = MBB -> getNumber ( ) ; if ( DTNumber < JTNumber ) { MachineBasicBlock * NewBB = adjustJTTargetBlockForward ( MBB , MI -> getParent ( ) ) ; if ( NewBB ) MJTI -> ReplaceMBBInJumpTable ( JTI , JTBBs [ j ] , NewBB ) ; MadeChange =


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> <STR_LIT> LCC = cast < CondCodeSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> RCC = cast < CondCodeSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; SDValue Y = RHS . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) != <STR_LIT> || Y . getOperand ( <NUM_LIT> ) != X ) return SDValue ( ) ; if ( LCC == <STR_LIT> ) { if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ; static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , X , DAG . getConstant ( Mask , <STR_LIT> ) ) ; } } } return SDValue


<s> if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) SavedRegs . set ( TRI ->


<s> F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned VR1 = RegInfo . createVirtualRegister (


<s> void emitDefCFAOffsets ( MachineBasicBlock & MBB , const DebugLoc & dl , const <ISA_LIT>BaseInstrInfo & TII , bool HasFP ) { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset += Info . SPAdjust ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , std :: next ( Info . I ) , dl , TII . get ( TargetOpcode ::

CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const MachineFunction & MF )


<s> void <ISA_LIT>FlagsCopyLoweringPass :: insertTest ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Pos , const DebugLoc & Loc , unsigned Reg ) { auto TestI = BuildMI ( MBB , Pos , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . addReg ( Reg ) ; ( void


<s> unsigned getMinNumVGPRs ( unsigned WavesPerEU ) const { return <STR_LIT> :: getMinNumVGPRs ( MCSubtargetInfo :: getFeatureBits ( )


<s> SmallCost *= PopPushCount ; uint32_t IncDecCount = std :: abs ( Offset ) % SlotSize ; SmallCost += ( OptSize || Is24Bit ? <NUM_LIT> : <NUM_LIT> ) * IncDecCount ; unsigned LargeCost = OptSize || Is24Bit ? <NUM_LIT> + SlotSize : <NUM_LIT> ; LargeCost += OptSize || Is24Bit ? <NUM_LIT> : <NUM_LIT> ; LargeCost += OptSize || Is24Bit ? <NUM_LIT> : <NUM_LIT> ; bool CanUseLEA = STI . hasE<ISA_LIT>Ops ( ) && FPOffset >= <NUM_LIT> && isInt < <NUM_LIT> > ( Offset - FPOffset ) && hasFP ( MF ) ; unsigned LEACost = CanUseLEA ? <NUM_LIT> : LargeCost ; if ( SmallCost <= LargeCost && SmallCost <= LEACost ) { while ( PopPushCount -- ) BuildMI ( MBB , MI , DL , TII . get ( Offset >= <NUM_LIT> ? ( Is24Bit ? <STR_LIT> : <STR_LIT> ) : ( Is24Bit ? <STR_LIT> : <STR_LIT> ) ) ) . addReg ( ScratchReg , getDefRegState ( Offset >= <NUM_LIT> ) | getDeadRegState ( Offset >= <NUM_LIT> ) | getUndefRegState ( Offset < <NUM_LIT> ) ) ; while ( IncDecCount -- ) BuildMI ( MBB , MI , DL , TII . get ( Offset >= <NUM_LIT> ? ( Is24Bit ? <STR_LIT> : <STR_LIT> ) : ( Is24Bit ? <STR_LIT> : <STR_LIT> ) ) ) ; return ; } if ( LargeCost <= LEACost


<s> SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSize == Offset ) return ; if ( LeftoverBytes ) { assert ( ( ByValSize > Offset ) && ( ByValSize < Offset + RegSize ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = RegSize / <NUM_LIT> , TotalSizeLoaded = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt =


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; bool isBigEndian = DAG . getDataLayout ( ) . isBigEndian ( ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( DAG . getTargetExtractSubreg ( isBigEndian ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , <STR_LIT> , SDValue ( CmpSwap , <NUM_LIT> ) ) ) ; Results . push_back ( SDValue ( CmpSwap ,


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; std :: string LayoutStr = A64VectorLayoutToString ( Layout ) ; O << <STR_LIT> ; if ( Count > <NUM_LIT> ) { bool IsVec64 = ( Layout < <STR_LIT> ) ? true : false ; unsigned SubRegIdx = IsVec64 ? <STR_LIT> : <STR_LIT> ; for ( unsigned I = <NUM_LIT> ; I < Count ; I ++ ) { std :: string Name = getRegisterName ( MRI . getSubReg ( Reg , SubRegIdx ++ ) ) ; Name [ <NUM_LIT> ] = 'v' ; O << Name << LayoutStr ; if ( I != Count - <NUM_LIT> )


<s> if ( ! VT . isVector ( ) || N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> || N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> getConstantSplatNode ( ) ) return


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) { OutStreamer -> EmitRawText ( <STR_LIT>


<s> TII = static_cast < const R600InstrInfo * > ( Fn . getTarget ( ) . getInstrInfo ( ) ) ; MRI = & ( Fn . getRegInfo ( ) ) ; for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { MachineBasicBlock * MB = MBB ; PreviousRegSeq . clear ( ) ; PreviousRegSeqByReg . clear ( ) ; PreviousRegSeqByUndefCount . clear ( ) ; for ( MachineBasicBlock :: iterator MII = MB -> begin ( ) , MIIE = MB -> end ( ) ; MII != MIIE ; ++ MII ) { MachineInstr * MI = MII ; if ( MI -> getOpcode ( ) != AMDGPU :: REG_SEQUENCE ) continue ; RegSeqInfo R<ISA_LIT> ( * MRI , MI ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! areAllUsesSwizzeable ( Reg ) ) continue ; DEBUG ( dbgs ( )


<s> return ( vector unsigned char ) __builtin_altivec_vpkshus ( ( vector signed short ) a1


<s> bool <ISA_LIT>InstructionSelector :: selectBrJT ( MachineInstr & I , MachineRegisterInfo & MRI ) { assert ( I . getOpcode ( ) == TargetOpcode :: G_BRJT && <STR_LIT> ) ; Register JTAddr = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned JTI = I . getOperand ( <NUM_LIT> ) . getIndex ( ) ; Register Index = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TargetReg = MRI . createVirtualRegister ( & <STR_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isAbsoluteSet ( const MachineInstr &


<s> static rtx mep_tp_rtx ( void ) { return get_hard_reg_initial_val ( Pmode , TP_REGNO


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( create<ISA_LIT>AbstractMemberAccess ( & get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>PreserveDIType


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand (


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { return true


<s> LowOverheadLoop ( MachineLoop & ML , MachineLoopInfo & MLI , ReachingDefAnalysis & RDA , const TargetRegisterInfo & TRI , const <ISA_LIT>BaseInstrInfo & TII ) : ML ( ML ) , MLI ( MLI ) , RDA

( RDA ) , TRI ( TRI ) , TII ( TII ) , TPNumElements ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) {


<s> case SECCAT_BSS : if ( ! prefix ) return bss_section ; base_sec_name = <STR_LIT> ; break ; case SECCAT_RODATA : if ( ! prefix ) return readonly_data_section ; base_sec_name = <STR_LIT> ; break ; case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : return default_elf_select_section ( decl , reloc , align ) ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : case SECCAT_TDATA : case SECCAT_TBSS : case SECCAT_DATA_REL : case SECCAT_DATA_REL_LOCAL : case SECCAT_DATA_REL_RO : case SECCAT_DATA_REL_RO_LOCAL : return default_select_section ( decl , reloc , align ) ; default : gcc_unreachable ( ) ; } sec_name = ACONCAT ( ( prefix , base_sec_name , DECL_SECTION_NAME ( decl ) , NULL ) ) ; return get_named_section ( decl , sec_name ,


<s> AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID (


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , false , false , isKill ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i !=

e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> void \ fini_section ( ) \ { \ if ( in_section != in_fini ) \ { \ in_section = in_fini ; \ fprintf

( asm_out_file , <STR_LIT> , FINI_SECTION_ASM_OP ) ; \ } \ }


<s> static DecodeStatus DecodeSimm23Lsl2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 <


<s> if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind


<s> if ( ix86_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( ix86_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = <NUM_LIT> ; i < ( ix86_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return


<s> rtx labelref ; int ret ; int prob = - <NUM_LIT> ; enum { UNKNOWN , BACKWARD , FORWARD } jump_type = UNKNOWN ; gcc_assert ( JUMP_P ( insn ) ) ; if ( ! any_condjump_p ( insn ) ) ret = FRV_JUMP_LIKELY ; else { labelref = condjump_label ( insn ) ; if ( labelref ) { rtx label = XEXP ( labelref , <NUM_LIT> ) ; jump_type = ( insn_current_address > INSN_ADDRESSES ( INSN_UID ( label ) ) ? BACKWARD : FORWARD ) ; } note = find_reg_note ( insn , REG_BR_PROB , <NUM_LIT> ) ; if ( ! note ) ret = ( ( jump_type == BACKWARD ) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY ) ; else { prob = XINT ( note , <NUM_LIT> ) ; ret = ( ( prob >= ( REG_BR_PROB_BASE / <NUM_LIT> ) ) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY ) ; } } if ( TARGET_DEBUG ) { char * direction ; switch ( jump_type ) { default : case UNKNOWN : direction = <STR_LIT> ; break ; case BACKWARD : direction = <STR_LIT> ; break ; case FORWARD : direction = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( current_function_decl ) ) , ( long ) INSN_UID ( insn ) , direction , prob , REG_BR_PROB_BASE , ret ) ; } return ret


<s> static unsigned getRRMOpcodeVariant ( unsigned Opcode ) { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT>


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS , StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: WebKit_JS : return CC_<ISA_LIT>_WebKit_JS ; case CallingConv :: C : case CallingConv :: Fast : if ( ! Subtarget -> isTargetDarwin (


<s> aapcs_layout_arg ( pcum , mode , type , named ) ; return pcum -> aapcs_partial ; } if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( mode ) ) return <NUM_LIT> ; if ( NUM_ARG_REGS > nregs && ( NUM_ARG_REGS < nregs + ARM_NUM_REGS2 ( mode , type ) ) && pcum -> can_split ) return ( NUM_ARG_REGS - nregs ) * UNITS_PER_WORD ; return <NUM_LIT>


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; Register CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( )


<s> O << <STR_LIT> ; O << formatDec ( Imm & <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ']' ; } else if ( ( Imm >= DppCtrl :: ROW_SHL_FIRST ) && ( Imm <= DppCtrl :: ROW_SHL_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_SHR_FIRST ) && ( Imm <= DppCtrl :: ROW_SHR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_ROR_FIRST ) && ( Imm <= DppCtrl :: ROW_ROR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == DppCtrl :: WAVE_SHL1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROL1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_SHR1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROR1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_MIRROR ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_HALF_MIRROR ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: BCAST15 ) { if ( ! <STR_LIT> ( STI ) && !


<s> static rtx mips_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { return mips_function_value_1 ( valtype , fn_decl_or_type


<s> if ( ! Section ) { getStreamer ( ) . InitSections ( ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) .


<s> updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . addOperand ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex


<s> bool hasPrivateMemoryInputPtr ( ) const { return


<s> vector_antic = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_transp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_comp = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avin = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_avout = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; vector_kill = sbitmap_vector_alloc ( last_basic_block_for_fn ( cfun ) , vector_exprs . length ( ) ) ; bitmap_vector_ones ( vector_transp , last_basic_block_for_fn ( cfun ) ) ; bitmap_vector_clear ( vector_antic , last_basic_block_for_fn ( cfun


<s> unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - <NUM_LIT> ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - <NUM_LIT> ) / <NUM_LIT> ) ; if (


<s> <ISA_LIT>PreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF ,


<s> return STI . getTargetTriple ( ) . getArch ( ) ==


<s> MCFragment * findAssociatedFragment (


<s> if ( cfun -> calls_alloca ) return true ; if ( TARGET_MIPS16 ) { mips_compute_frame_info ( ) ; if ( ! SMALL_OPERAND ( cfun -> machine -> frame . total_size ) ) return true ; } return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false


<s> addPass ( create<ISA_LIT>PromoteAlloca ( & TM ) ) ; addPass ( createSROAPass ( ) ) ; } TargetPassConfig :: addCodeGenPrepare (


<s> static void addLiveInRegs ( Iter Filler , MachineBasicBlock & MBB ) { for ( unsigned I = <NUM_LIT> , E = Filler -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = Filler -> getOperand ( I ) ; unsigned R ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! ( R = MO . getReg ( ) ) ) continue ; const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getSubtarget ( ) . getRegisterInfo ( ) -> getAllocatableSet (

MF ) . test ( R ) && <STR_LIT> <STR_LIT> ) ;


<s> if ( Subtarget . isRV64 ( ) ) if ( Subtarget . hasD ( ) ) return CSR_RV64D_SaveList ; else if ( Subtarget . hasF ( ) )


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> :


<s> if ( Cond . empty ( ) ) { if ( ! iter -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; MachineBasicBlock * CondBranchTarget = iter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( UncondBranch . first != MBB . rend ( ) ) { assert ( std :: next ( UncondBranch . first ) == iter && <STR_LIT> ) ; if ( AllowModify && MBB . isLayoutSuccessor ( CondBranchTarget ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned BNCC = GetCondBranchFromCond ( BranchCode ) ; BuildMI ( MBB , * UncondBranch . first , MBB . rfindDebugLoc ( iter ) , get ( BNCC ) ) . addMBB ( UncondBranch . second ) ; EraseList . push_back ( * iter ) ; EraseList . push_back ( * UncondBranch . first ) ; TBB = UncondBranch . second ; FBB = nullptr ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; } else { TBB = CondBranchTarget ; FBB = UncondBranch . second ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; } UncondBranch = { MBB . rend ( ) , nullptr } ; continue ; } TBB = CondBranchTarget ; FBB = nullptr ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; auto OldBranchCode = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; if ( ! iter -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; auto NewTBB = iter -> getOperand ( <NUM_LIT> ) .


<s> emit_cmp_and_jump_insns ( tmpreg , const0_rtx , EQ , <NUM_LIT> , SImode , <NUM_LIT> , align_4_label ) ; if ( TARGET_CMOVE ) { rtx reg = gen_reg_rtx ( SImode ) ; rtx reg2 = gen_reg_rtx ( Pmode ) ; emit_move_insn ( reg , tmpreg ) ; emit_insn ( gen_lshrsi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_testsi_ccno_1 ( tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_EQ ( VOIDmode , tmp , const0_rtx ) ; emit_insn ( gen_rtx_SET ( tmpreg , gen_rtx_IF_THEN_ELSE ( SImode , tmp , reg , tmpreg ) ) ) ; emit_insn ( gen_rtx_SET ( reg2 , plus_constant ( Pmode , out , <NUM_LIT> ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_EQ ( VOIDmode , tmp , const0_rtx ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_IF_THEN_ELSE ( Pmode , tmp , reg2 , out ) ) ) ; } else { rtx_code_label * end_2_label = gen_label_rtx ( ) ; emit_insn ( gen_testsi_ccno_1 ( tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp = gen_rtx_NE ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , end_2_label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = end_2_label ; emit_insn ( gen_lshrsi3 ( tmpreg , tmpreg , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_add2_insn ( out , const2_rtx ) ) ; emit_label ( end_2_label


<s> rtx limit = force_reg ( DImode , gen_int_mode ( vl , DImode ) ) ; target = aarch64_target_reg ( target ,


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { if ( VRegs . size ( ) > <NUM_LIT> )


<s> unsigned <ISA_LIT>MCInstrInfo :: getOtherReservedSlots ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst const & MCI ) { const InstrItinerary * II = STI . getSchedModel ( ) . InstrItineraries ; int SchedClass = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . getSchedClass ( ) ; unsigned Slots = <NUM_LIT> ; for ( unsigned Stage = II [ SchedClass ] . FirstStage + <NUM_LIT> ; Stage < II [ SchedClass ] . LastStage ; ++ Stage ) { unsigned Units = ( Stage +


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { AttrEmitter = new AsmAttributeEmitter ( OutStreamer ) ; emitFPU = true ; } else { MCObjectStreamer & O = static_cast < MCObjectStreamer & > ( OutStreamer ) ; AttrEmitter = new ObjectAttributeEmitter ( O ) ; } AttrEmitter -> MaybeSwitchVendor ( <STR_LIT> ) ; std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString == <STR_LIT> || Subtarget -> isCortexA8 ( ) ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT>


<s> bool isEg = ( ST -> getGeneration ( ) >= <ISA_LIT>Subtarget :: EVERGREEN ) ; switch ( CFI ) { case CF_TC : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_VC : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_CALL_FS : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_WHILE_LOOP : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_END_LOOP : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_LOOP_BREAK : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_LOOP_CONTINUE : Opcode = isEg ? <STR_LIT> :


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue Res = DCI . DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; return DCI . DAG . getMergeValues ( { Res , DCI . DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } , DL ) ; } if ( SDNode * GenericAddSub = DCI . DAG . getNodeIfExists ( <STR_LIT> , DCI . DAG . getVTList ( VT ) , { LHS , RHS } ) ) DCI . CombineTo ( GenericAddSub , SDValue ( N , <NUM_LIT> ) ) ; return SDValue


<s> return ; } unsigned Opcode = N -> getOpcode ( ) ; auto DL = CurDAG -> getDataLayout ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( DL ) ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , getTargetLowering ( ) -> getPointerTy ( DL ) , TFI ) ; return ; } case <STR_LIT> : case <STR_LIT> : { selectMultiplication ( N ) ; return ; } } SelectCode ( N ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> ; N


<s> case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( dyn_cast < ConstantFP > ( CallOperandVal ) ) { weight = CW_Constant ; } break ; case 'e' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal


<s> return ( <STR_LIT> . contains ( Reg )


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> XVECEXP ( rv , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R2_REGNO ) , GEN_INT ( <NUM_LIT> ) ) ; XVECEXP ( rv , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( HImode , R3_REGNO ) , GEN_INT ( <NUM_LIT> ) ) ; return rv ; } if ( TARGET_A24 && GET_MODE_SIZE ( mode ) > <NUM_LIT> ) { rtx rv ; rv = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( rv , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , R0_REGNO ) , GEN_INT ( <NUM_LIT> ) ) ; return


<s> SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = <NUM_LIT> ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * ( RI . getRegSizeInBits ( * DstRC ) / <NUM_LIT>


<s> if ( IdxConst -> getZExtValue ( ) == <NUM_LIT> ) E0 . push_back ( U ) ; else if ( IdxConst -> getZExtValue ( ) == <NUM_LIT> ) E1 . push_back ( U ) ; else llvm_unreachable ( <STR_LIT> ) ; } } if ( E0 . empty ( ) || E1 . empty ( ) ) return false ; unsigned Op = <STR_LIT> ; SDValue Source = Vector ; if ( Vector -> getOpcode ( ) == <STR_LIT> ) { Op = <STR_LIT> ; Source = Vector ->


<s> OffsetRange & shift ( int32_t S ) { Min += S ; Max += S ; Offset = ( Offset + S


<s> ExitSU = SUnit ( ) ; BuildSchedGraph ( AA ) ; NumFixedAnti += Broken ; } } BuildSchedGraph ( AA ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll


<s> float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT>


<s> bool hasSpilledCRs ( ) const { return HasSpilledCRs


<s> SOffsetReg = B . buildConstant ( S32 , SOffset ) . getReg ( <NUM_LIT> ) ; B . getMRI ( ) -> setRegBank ( SOffsetReg , <STR_LIT> ) ; InstOffsetVal = ImmOffset ; return <NUM_LIT> ; } if ( SOffset == <NUM_LIT> ) { VOffsetReg = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; B . getMRI ( ) -> setRegBank ( VOffsetReg , <STR_LIT> ) ; SOffsetReg = Base ; InstOffsetVal = ImmOffset ; return <NUM_LIT> ; } } MachineInstr * Add = getOpcodeDef ( <STR_LIT> , CombinedOffset , * MRI ) ; if ( Add && ( int ) Offset >= <NUM_LIT> ) { Register Src0 = getSrcRegIgnoringCopies ( * MRI , Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register Src1 = getSrcRegIgnoringCopies ( * MRI , Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const RegisterBank * Src0Bank = RBI . getRegBank ( Src0 , * MRI , * RBI . TRI ) ; const RegisterBank * Src1Bank = RBI . getRegBank ( Src1 , * MRI , * RBI . TRI ) ; if ( Src0Bank == & <STR_LIT> && Src1Bank == & <STR_LIT> ) { VOffsetReg = Src0 ; SOffsetReg = Src1 ; return <NUM_LIT>


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( unsigned I = <STR_LIT> ; I <= <STR_LIT> ; ++ I ) { MVT VT = <STR_LIT> ( I ) ; if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT>


<s> const <ISA_LIT>RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; bool NeedsStackRealignment = RegInfo . shouldRealignStack ( MF ) ; DebugLoc DL ; if ( NeedsStackRealignment && ! RegInfo . canRealignStack ( MF ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; uint64_t NumBytes = MFI . getStackSize ( ) ; if ( ! FuncInfo -> isLeafProc ( ) ) { NumBytes = STI . getAdjustedFrameSize ( NumBytes ) ; } NumBytes = alignTo ( NumBytes , MFI . getMaxAlign ( ) ) ; MFI . setStackSize ( NumBytes ) ; emitPrologueInsns ( MF , MBB , MBBI , NumBytes , true ) ; if ( ! FuncInfo -> isLeafProc ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MaybeAlign RuntimeAlign = NeedsStackRealignment ? MaybeAlign ( MFI . getMaxAlign ( ) ) : None ; assert ( ( RuntimeAlign == None || ! FuncInfo -> isLeafProc ( ) ) &&


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue LSEL = DAG . getNode ( <STR_LIT> , dl , True . getValueType ( ) , LHS , True , False , LHS . getOperand ( <NUM_LIT> ) ) ; SDValue RSEL = DAG . getNode ( <STR_LIT> , dl , True . getValueType ( ) , RHS , True , False , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Op . getOpcode ( ) , dl ,


<s> case IES_DIVIDE : case IES_LPAREN : if ( ( PrevState == IES_PLUS || PrevState == IES_MINUS || PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE || PrevState == IES_LPAREN || PrevState == IES_LBRAC ) && CurrState == IES_MINUS ) { State = IES_ERROR ; break ; } State = IES_LPAREN


<s> return isMovWSymbol ( <ISA_LIT>MCExpr


<s> const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ; MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ; const MCInstrDesc & DefDesc = DefMI -> getDesc ( ) ; for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . add ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . add ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI .

getParent ( ) ) NewMI -> clearKillInfo ( ) ;


<s> if ( M . getNamedGlobal ( Name ) ) report_fatal_error ( Twine ( <STR_LIT> ) + Name ) ; return new GlobalVariable ( M , IRB . getInt32Ty ( ) , false , GlobalValue ::


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( )


<s> return DAG -> getNode ( <STR_LIT> , dl , VT , A


<s> for ( const MachineOperand & MO : R ) { if ( ! MO . isReg ( ) ) continue ; if ( Reg . isPhysical ( ) && MO . getReg ( ) . isPhysical ( ) ) { if ( TRI -> regsOverlap ( Reg , MO .


<s> Op -> Imm . Val = Val ; Op -> Imm . IsFPImm = IsFPImm ; Op -> Imm . Type = Type ; Op -> Imm . Mods = Modifiers ( ) ; Op -> StartLoc =


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L


<s> Is64Bit = STI . is64Bit ( ) ; IsLP64 = STI . isTarget64BitLP64 ( ) ; Uses64BitFramePtr = STI . isTarget64BitLP64 ( ) || STI . isTargetNaCl64 ( ) ; StackPtr = TRI -> getStackRegister


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> isTargetMachO ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode


<s> MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! IsTruncatingStore && <STR_LIT> ) ; ( void ) IsTruncatingStore ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( VT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG ,


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShiftAmtNode = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t


<s> if ( Flags == <STR_LIT> ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags


<s> Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isAlignedMemNode ( LD ) ) { if ( LD -> isNonTemporal ( ) ) Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; else Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; } break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue IncV = CurDAG -> getTargetConstant ( Inc , dl , <STR_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; auto getExt64 = [ this , ExtType ] ( MachineSDNode * N , const SDLoc & dl ) -> MachineSDNode * { if ( ExtType == <STR_LIT> || ExtType == <STR_LIT> ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Zero , SDValue ( N , <NUM_LIT> ) ) ; } if ( ExtType == <STR_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( N , <NUM_LIT> ) ) ; return N ; } ; SDValue From [ <NUM_LIT> ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; SDValue To [ <NUM_LIT> ] ; EVT ValueVT = LD -> getValueType ( <NUM_LIT> ) ; if ( ValueVT == <STR_LIT> && ExtType != <STR_LIT> ) { assert ( LoadedVT . getSizeInBits ( ) <= <NUM_LIT> ) ; ValueVT =


<s> const MCOperand & SegReg = MI -> getOperand ( Op + <STR_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <STR_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << formatImm ( DispVal ) ; } else


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target


<s> if ( MAYBE_SSE_CLASS_P ( regclass ) || MAYBE_MMX_CLASS_P ( regclass ) ) { int mov_size = MAYBE_SSE_CLASS_P ( regclass ) && TARGET_SSE2 ? <NUM_LIT> : <NUM_LIT> ; if ( GET_MODE_SIZE ( from ) < mov_size || GET_MODE_SIZE ( to ) <


<s> if ( ! areOperandsOfVmullHighP64 ( II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ) return false ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 -> getOperand ( <NUM_LIT> ) , Ext2 -> getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I -> operands ( ) ) { if ( any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; ShuffleVectorInst * Shuffle = dyn_cast < ShuffleVectorInst > ( Op ) ; if ( ! Shuffle || ! Shuffle -> isZeroEltSplat ( ) ) continue ; Value * ShuffleOperand = Shuffle -> getOperand ( <NUM_LIT> ) ; InsertElementInst * Insert = dyn_cast < InsertElementInst > ( ShuffleOperand ) ; if ( ! Insert ) continue ; Instruction * OperandInstr = dyn_cast < Instruction > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! OperandInstr ) continue ; ConstantInt * ElementConstant = dyn_cast < ConstantInt > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! ElementConstant || ElementConstant -> getZExtValue ( )


<s> emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_CEIL ; break ; case I387_CW_MASK_PM : emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_MASK_PM ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case I387_CW_TRUNC : emit_insn ( gen_insvsi_1 ( reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_TRUNC ; break ; case I387_CW_FLOOR : emit_insn ( gen_insvsi_1 ( reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_FLOOR ; break ; case I387_CW_CEIL


<s> bool hasSDWA ( ) const { return HasSDWA


<s> RegisterTarget < Triple :: p2 , false > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT>


<s> unsigned getNumArguments ( ) { return NumArguments


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue (


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; darwin_set_default_type_attributes ( type


<s> * p = spu_sel ( * p , spu_rlmaskqwbyte ( a , shift ) , spu_rlmaskqwbyte

( spu_splats ( ( unsigned int ) <NUM_LIT> ) , shift ) ) ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ; } else printOperand ( MI ,


<s> static bool sh_rtx_costs ( rtx x , int code , int outer_code , int * total ) { switch ( code ) { case CONST_INT : if ( TARGET_SHMEDIA ) { if ( INTVAL ( x ) == <NUM_LIT> ) * total = <NUM_LIT> ; else if ( outer_code == AND && and_operand ( ( x ) , DImode ) ) * total = <NUM_LIT> ; else if ( ( outer_code == IOR || outer_code == XOR || outer_code == PLUS ) && CONST_OK_FOR_I10 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( CONST_OK_FOR_I16 ( INTVAL ( x ) ) ) * total = COSTS_N_INSNS ( outer_code != SET ) ; else if ( CONST_OK_FOR_I16 ( INTVAL ( x ) >> <NUM_LIT> ) ) * total = COSTS_N_INSNS ( ( outer_code != SET ) + <NUM_LIT> ) ; else if ( CONST_OK_FOR_I16 ( ( INTVAL ( x ) >> <NUM_LIT> ) >> <NUM_LIT> ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } if ( CONST_OK_FOR_I08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( ( outer_code == AND || outer_code == IOR || outer_code == XOR ) && CONST_OK_FOR_K08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_SHMEDIA64 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( TARGET_SHMEDIA32 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : if ( TARGET_SHMEDIA ) * total = COSTS_N_INSNS


<s> OutStreamer . EmitRawText ( PAN :: getFrameLabel ( CurrentFnSym -> getName ( ) ) + Twine ( <STR_LIT> ) ) ; const Type * RetType = F -> getReturnType ( ) ; unsigned RetSize = <NUM_LIT> ; if ( RetType -> getTypeID ( ) != Type :: VoidTyID ) RetSize = TD -> getTypeAllocSize ( RetType ) ; if ( RetSize > <NUM_LIT> ) OutStreamer . EmitRawText ( PAN :: getRetvalLabel ( CurrentFnSym -> getName ( ) ) + Twine ( <STR_LIT> ) + Twine ( RetSize ) ) ; else OutStreamer . EmitRawText ( PAN :: getRetvalLabel ( CurrentFnSym -> getName ( ) ) + Twine ( <STR_LIT> ) ) ; unsigned ArgSize = <NUM_LIT> ; for ( Function :: const_arg_iterator argi = F -> arg_begin ( ) , arge = F -> arg_end ( ) ; argi != arge ; ++ argi ) { const Type * Ty = argi -> getType


<s> int width , is_valid ; static char templ [ <NUM_LIT> ] ; is_valid = neon_immediate_valid_for_shift ( * op2 , mode , op2 , & width , isleftshift ) ; gcc_assert ( is_valid != <NUM_LIT> ) ; if ( quad ) sprintf ( templ , <STR_LIT> , mnem , sign , width ) ; else sprintf ( templ , <STR_LIT> , mnem , sign , width ) ; return


<s> if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; OffsetIsScalable =


<s> if ( count != <NUM_LIT> ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM


<s> SDValue True = CurDAG -> getTargetConstant ( T -> getZExtValue ( ) , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , True , CC


<s> MVT DstVT ; Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcEVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( Subtarget -> hasSPE ( ) ) { unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; Register DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg ) ; return true ; } if ( ! IsSigned && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { Register TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; Register DestReg = createResultReg ( RC ) ; unsigned Opc


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) != <STR_LIT> ) { return false ; } Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand


<s> bool <ISA_LIT>TargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const


<s> Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; Opcode = <STR_LIT> ; } else Opcode = <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Opcode , Op0 , Op1 , Ops [ <NUM_LIT> ]


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue

( Inst , MCOp , Fixups , SubtargetInfo ) ;


<s> int getMoveF64FrameIndex ( MachineFunction & MF ) { if ( MoveF64FrameIndex == - <NUM_LIT> ) MoveF64FrameIndex = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; return MoveF64FrameIndex


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressDarwin ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; } else { <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> ,


<s> struct constant * c ; size_t i ; for ( i = <NUM_LIT> ; i < NR_C_MODES ; i ++ ) if ( constant_modes [ i ] == mode ) break ; gcc_assert ( i != NR_C_MODES ) ; for ( c = pool -> constants [ i ] ; c != NULL ; c =

c -> next ) if ( rtx_equal_p ( val , c -> value ) ) break ;


<s> FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ) ; } } FuncInfo -> setVarArgsGPRIndex ( GPRIdx ) ; FuncInfo -> setVarArgsGPRSize ( GPRSaveSize ) ; if ( Subtarget -> hasFPARMv8 ( ) ) { static const MCPhysReg FPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumFPRArgRegs = array_lengthof ( FPRArgRegs ) ; unsigned FirstVariadicFPR = CCInfo . getFirstUnallocated ( FPRArgRegs , NumFPRArgRegs ) ; unsigned FPRSaveSize = <NUM_LIT> * ( NumFPRArgRegs - FirstVariadicFPR ) ; int FPRIdx = <NUM_LIT> ; if ( FPRSaveSize != <NUM_LIT> ) { FPRIdx = MFI -> CreateStackObject ( FPRSaveSize , <NUM_LIT> , false ) ; SDValue FIN = DAG . getFrameIndex ( FPRIdx , getPointerTy ( ) ) ; for ( unsigned i = FirstVariadicFPR ; i < NumFPRArgRegs ; ++ i ) { unsigned VReg = MF . addLiveIn ( FPRArgRegs [ i ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getStack ( i * <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , FIN , DAG . getConstant ( <NUM_LIT> , getPointerTy


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> Register AddDefR = AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UN = * I ; NodeAddr < StmtNode * > SN = UN . Addr -> getOwner ( * DFG ) ; MachineInstr * MI = SN . Addr -> getCode ( ) ; const MCInstrDesc & MID = MI -> getDesc ( ) ; if ( ( ! MID . mayLoad ( ) && ! MID . mayStore ( ) ) || HII -> getAddrMode ( * MI ) != <STR_LIT> || HII -> isHVXVec ( * MI ) ) return false ; MachineOperand BaseOp = MID . mayLoad ( ) ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; if ( ! BaseOp . isReg ( ) || BaseOp . getReg ( ) != AddDefR ) return false ; MachineOperand OffsetOp = MID . mayLoad ( ) ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; if ( ! OffsetOp . isImm ( ) ) return false ; int64_t newOffset = OffsetOp . getImm ( ) + AddMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isValidOffset ( MI , newOffset ) ) return false ; Register BaseReg = AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isSafeToExtLR ( AddSN , AddMI , BaseReg , UNodeList ) ) return false ; } bool Changed = false ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E


<s> const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ?


<s> static void vms_asm_out_destructor ( rtx symbol , int priority ATTRIBUTE_UNUSED ) { dtors_section ( ) ; assemble_align ( BITS_PER_WORD ) ; assemble_integer ( symbol , UNITS_PER_WORD , BITS_PER_WORD ,


<s> return ( int64x2_t ) __builtin_neon_vreinterpretv2diti (


<s> UP . Count = UINT_MAX ; UP . Partial = true ; for ( const BasicBlock * BB : L -> getBlocks ( ) ) { for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP ->

getAddressSpace ( ) != <STR_LIT> ) continue ;


<s> if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && REGNO ( XEXP ( addr , <NUM_LIT> ) ) != <NUM_LIT> ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && REGNO ( XEXP ( addr , <NUM_LIT> ) ) != <NUM_LIT> ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else gcc_unreachable (


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = Op . getValueType ( ) ; unsigned VTBits = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant (


<s> } else { assert ( MO . isSymbol ( ) && StringRef ( MO . getSymbolName ( ) ) == <STR_LIT> && <STR_LIT> ) ; Model = TLSModel :: GeneralDynamic ; } switch ( Model ) { case TLSModel :: InitialExec : RefFlags |= <ISA_LIT>MCExpr :: VK_GOTTPREL ; break ; case TLSModel :: LocalExec : RefFlags |= <ISA_LIT>MCExpr :: VK_TPREL ; break ; case TLSModel :: LocalDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_DTPREL ; break ; case TLSModel :: GeneralDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_TLSDESC ; break ; } } else { RefFlags |= <ISA_LIT>MCExpr :: VK_ABS ; } if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGE ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGEOFF ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G3 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G2 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G1 ; else if ( ( MO . getTargetFlags ( ) & <STR_LIT> ) == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; <ISA_LIT>MCExpr :: VariantKind RefKind ; RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( RefFlags ) ; Expr = <ISA_LIT>MCExpr :: Create ( Expr


<s> static bool expandSHXDROT ( MachineInstrBuilder & MIB , const MCInstrDesc & Desc ) { MIB -> setDesc ( Desc ) ; int64_t ShiftAmt = MIB -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( MIB . getReg ( <NUM_LIT> ) , getUndefRegState ( MIB -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ) ; MIB . addImm ( ShiftAmt ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: foldGlobalAddressImpl ( SDValue & N , SDValue & R , bool ShouldLookForGP ) { if ( N . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue N1 = N . getOperand ( <NUM_LIT> ) ; if ( ( ShouldLookForGP && ( N0 . getOpcode ( ) == <STR_LIT> ) ) || ( ! ShouldLookForGP && ( N0 . getOpcode ( ) == <STR_LIT> ) ) ) { ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( N1 ) ; GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( N0


<s> case CmpInst :: Predicate :: ICMP_NE : ExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : ExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: ICMP_ULT : case CmpInst :: Predicate :: ICMP_UGT : ExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_UGE : if ( ( ST -> hasSSE41 ( ) && MTy . getScalarSizeInBits ( ) == <NUM_LIT> ) || ( ST -> hasSSE2 ( ) && MTy . getScalarSizeInBits ( ) < <NUM_LIT> ) ) { ExtraCost = <NUM_LIT> ; } else { ExtraCost = <NUM_LIT> ; } break ; case CmpInst :: Predicate :: BAD_ICMP_PREDICATE : case CmpInst :: Predicate :: BAD_FCMP_PREDICATE : ExtraCost = <NUM_LIT> ; break ; default : break ; } } } static const CostTblEntry SLMCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ]


<s> return new <ISA_LIT>ELFStreamer ( Context , MAB , OS ,


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { expandFunctionCall ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT>


<s> int i ; if ( ! mep_get_intrinsic_insn ( intrinsic , & cgen_insn ) ) return false ; idata = & insn_data [ cgen_insn -> icode ] ; for ( i = <NUM_LIT> ; i < idata -> n_operands ; i ++ ) { newop [ i ] = mep_convert_arg ( idata -> operand [ i


<s> return <ISA_LIT>ArchVersion >= V4 &&


<s> DebugLoc DL = CI . I -> getDebugLoc ( ) ; unsigned Opcode ; if ( CI . InstClass == BUFFER_LOAD_OFFEN ) { Opcode = CI . IsX2 ? <STR_LIT> : <STR_LIT> ; } else { Opcode = CI . IsX2 ? <STR_LIT> : <STR_LIT> ; } const TargetRegisterClass * SuperRC = CI . IsX2 ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset0 , CI . Offset1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) ; if ( CI . InstClass == BUFFER_LOAD_OFFEN ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . SLC0 ) . addImm ( <NUM_LIT> ) . setMemRefs ( CI . I -> mergeMemRefsWith ( * CI . Paired ) ) ; unsigned SubRegIdx0 = CI . IsX2 ? <STR_LIT> : <STR_LIT> ; unsigned SubRegIdx1 = CI . IsX2


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crcc_w_d_w ( long int _1 , int _2 ) { return ( int ) __builtin_loongarch_crcc_w_d_w ( ( long int


<s> return ! getStackProbeSymbolName ( MF ) . empty


<s> break ; } } if ( Subtarget . has<ISA_LIT>32r6 ( ) && ( I -> getNumOperands ( ) > <NUM_LIT> ) && ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) ) return <NUM_LIT> ; if ( Subtarget . has<ISA_LIT>32r6 ( ) || canUseShortMicro<ISA_LIT>CTI ) { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( canUseShortMicro<ISA_LIT>CTI ) return <STR_LIT> ; else if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return <NUM_LIT> ; return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> bool useSSE = isScalarFPTypeInSSEReg ( DstVT ) ; if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( DstVT , <STR_LIT> ) ; SDValue FILDOps [ ] = { Chain , Pointer } ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , FILDOps , SrcVT , PtrInfo , Alignment , MachineMemOperand :: MOLoad ) ; Chain = Result . getValue ( <NUM_LIT> ) ; if ( useSSE ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned SSFISize = DstVT . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( SSFISize , SSFISize , false ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Tys = DAG . getVTList ( <STR_LIT>


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > (


<s> SDValue AMDGPUTargetLowering :: LowerIntrinsicIABS ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc DL = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , VT ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Neg , Op . getOperand ( <NUM_LIT>


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode ||


<s> MCAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU ) { if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new

Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ;