<s> } if ( lFromVEX2of2 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else if ( insn -> vexXopType == TYPE_XOP ) { switch ( ppFromXOP3of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) { case VEX_PREFIX_66 : attrMask |= ATTR_OPSIZE ; break ; case VEX_PREFIX_F3 : attrMask |= ATTR_XS ; break ; case VEX_PREFIX_F2 : attrMask |= ATTR_XD ; break ; } if ( lFromXOP3of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_ADSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( insn -> prefixPresent [ <NUM_LIT> ] && ! ( attrMask & ATTR_OPSIZE ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithOpsize ; const char * specName , * specWithOpSizeName ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithOpsize , insn , attrMask | ATTR_OPSIZE ) ) { insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specName = x86DisassemblerGetInstrName ( instructionID , miiArg ) ; specWithOpSizeName = x86DisassemblerGetInstrName ( instructionIDWithOpsize , miiArg ) ; if ( is16BitEquivalent ( specName , specWithOpSizeName ) ) { insn -> instructionID = instructionIDWithOpsize ; insn -> spec = specifierForUID ( instructionIDWithOpsize ) ; } else { insn -> instructionID = instructionID ; insn -> spec = spec ; } return <NUM_LIT> ; } if ( insn -> opcodeType == ONEBYTE && insn -> opcode == <NUM_LIT> && insn -> rexPrefix & <NUM_LIT> ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithNewOpcode ; const struct InstructionSpecifier * specWithNewOpcode ; spec = specifierForUID ( instructionID ) ; insn -> opcode = <NUM_LIT> ; if ( getIDWithAttrMask ( & instructionIDWithNewOpcode , insn , attrMask ) ) { insn -> opcode = <NUM_LIT> ; insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specWithNewOpcode = specifierForUID ( instructionIDWithNewOpcode ) ; insn -> opcode = <NUM_LIT> ; insn -> instructionID


<s> bool <ISA_LIT>Subtarget :: isPC32DBLSymbol ( const GlobalValue * GV , Reloc

:: Model RM , CodeModel :: Model CM ) const {


<s> } sbuf [ s ] = <NUM_LIT> ; fprintf ( stream , <STR_LIT> , sbuf ) ; l += s + <NUM_LIT> ; if ( TARGET_TI && l >= <NUM_LIT> && len > <NUM_LIT> ) { fprintf ( stream , <STR_LIT> ) ; first = <NUM_LIT> ; l = <NUM_LIT> ; } s = <NUM_LIT> ; } if ( onlys ) continue ; if ( first ) first = <NUM_LIT> ; else { fputc ( ',' , stream ) ; l ++ ; } fprintf ( stream , <STR_LIT> , * ptr ) ; l += <NUM_LIT> ; if ( TARGET_TI && l >= <NUM_LIT> && len


<s> static rtx_insn * mips16_emit_constants_1 ( machine_mode mode , rtx value , rtx_insn * insn ) { if ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) { rtx size = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; return emit_insn_after ( gen_consttable_int ( value , size ) , insn ) ; } if ( SCALAR_FLOAT_MODE_P ( mode ) ) return emit_insn_after ( gen_consttable_float ( value )


<s> return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) &&

( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> Amount /= <NUM_LIT> ; bool isU6 = isImmU6 ( Amount ) ; if ( ! isU6 && ! isImmU16 ( Amount ) ) { errs ( ) << <STR_LIT> << Amount << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT> ) ; int Opcode = isU6 ?


<s> SDLoc dl ( Op ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; unsigned JTI = JT -> getIndex ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , <STR_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JTE = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JTE [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; MBB -> setHasAddressTaken ( ) ; BlockAddress :: get ( const_cast < BasicBlock * > ( MBB -> getBasicBlock ( ) ) ) ; } SDValue JumpTableBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , TargetJT ) ; SDValue ShiftIndex = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue JTAddress = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JumpTableBase , ShiftIndex ) ; SDValue LoadTarget = DAG . getLoad ( <STR_LIT> , dl , Chain , JTAddress , MachinePointerInfo (

) , false , false , false , <NUM_LIT> ) ;


<s> int BlackfinRegisterInfo :: getDwarfRegNum ( unsigned RegNum ,


<s> switch ( Opcode ) { case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT>


<s> if ( TYPE_MODE ( type ) != BLKmode && ! AGGREGATE_TYPE_P ( type ) ) return false ; size = int_size_in_bytes ( type ) ; return size < <NUM_LIT> || size > <NUM_LIT>

|| ( size % UNITS_PER_WORD ) != <NUM_LIT> ;


<s> if ( ( IDVal . lower ( ) == <STR_LIT> ) || ( IDVal . lower ( ) == <STR_LIT> ) ) return ParseDirectiveComm ( true , DirectiveID . getLoc ( ) ) ; if ( ( IDVal . lower ( ) == <STR_LIT> ) || ( IDVal . lower ( ) == <STR_LIT> ) ) return ParseDirectiveComm ( false


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( x & ( ( unsigned short )


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> static DecodeStatus DecodeBlezlGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt )


<s> StringRef getPassName ( ) const override { return


<s> SDValue LoweredLogical = computeLogicOpInGPR ( SDValue ( N , <NUM_LIT> ) ) ; if ( ! LoweredLogical ) return false ; SDLoc dl ( N ) ; bool IsBitwiseNegate = LoweredLogical . getMachineOpcode ( ) == <STR_LIT> ; unsigned SubRegToExtract = IsBitwiseNegate ? <STR_LIT> : <STR_LIT> ; SDValue CR0Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue LHS = LoweredLogical . getOperand ( <NUM_LIT> ) ; SDValue RHS = LoweredLogical . getOperand ( <NUM_LIT> ) ; SDValue WideOp ; SDValue OpToConvToRecForm ; if ( IsBitwiseNegate && LoweredLogical . getOperand ( <NUM_LIT> ) . getMachineOpcode ( ) == <STR_LIT> ) OpToConvToRecForm = LoweredLogical . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else if ( IsBitwiseNegate ) OpToConvToRecForm = LoweredLogical . getOperand ( <NUM_LIT> ) ; else OpToConvToRecForm = LoweredLogical ; uint16_t NonRecOpc = OpToConvToRecForm . getMachineOpcode ( ) ; int NewOpc = <ISA_LIT>InstrInfo :: getRecordFormOpcode ( NonRecOpc ) ; if ( NewOpc != - <NUM_LIT> && IsBitwiseNegate ) { assert ( LoweredLogical . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; std :: vector < SDValue > Ops ; for ( int i = <NUM_LIT> , e = OpToConvToRecForm . getNumOperands ( ) ; i < e ; i ++ ) Ops . push_back ( OpToConvToRecForm . getOperand ( i ) ) ; WideOp = SDValue ( CurDAG -> getMachineNode ( NewOpc , dl , OpToConvToRecForm . getValueType ( ) , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { assert ( ( NewOpc != - <NUM_LIT> || ! IsBitwiseNegate ) && <STR_LIT> ) ; WideOp = SDValue ( CurDAG -> getMachineNode ( NewOpc == - <NUM_LIT> ? <STR_LIT> : NewOpc , dl , <STR_LIT> , <STR_LIT> , LHS , RHS ) , <NUM_LIT> ) ; } SDValue SRIdxVal = CurDAG -> getTargetConstant ( SubRegToExtract , dl , <STR_LIT> ) ; SDValue CRBit = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , CR0Reg , SRIdxVal , WideOp . getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ; ReplaceNode ( N , CRBit . getNode ( ) ) ; return true


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( getMemDisp


<s> nf . getLeads ( ) [ <NUM_LIT> ] . PtrKind = <ISA_LIT>LibFunc :: getEPtrKindFromAddrSpace ( <ISA_LIT>AS :: FLAT_ADDRESS ) ; Function * Fsincos = dyn_cast_or_null < Function > ( getFunction ( M , nf ) ) ; if ( ! Fsincos ) return false ; BasicBlock :: iterator ItOld = B . GetInsertPoint ( ) ; AllocaInst * Alloc = insertAlloca ( UI , B , <STR_LIT> ) ; B . SetInsertPoint ( UI ) ; Value * P = Alloc ; Type * PTy = Fsincos -> getFunctionType ( ) -> getParamType ( <NUM_LIT> ) ; if ( PTy -> getPointerAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) P = B . CreateAddrSpaceCast ( Alloc , PTy ) ; CallInst * Call = CreateCallEx2 ( B , Fsincos , UI -> getArgOperand ( <NUM_LIT> ) , P ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * UI << <STR_LIT> << * Call << <STR_LIT> ) ; if ( ! isSin ) { B . SetInsertPoint ( & * ItOld ) ; UI -> replaceAllUsesWith ( & * Call ) ; Instruction * Reload = B . CreateLoad ( Alloc ) ; CI -> replaceAllUsesWith ( Reload ) ; UI -> eraseFromParent ( ) ; CI -> eraseFromParent ( ) ; } else { Instruction * Reload = B . CreateLoad ( Alloc ) ; UI -> replaceAllUsesWith ( Reload ) ; CI -> replaceAllUsesWith (


<s> if ( c == REG ) return <NUM_LIT> ; if ( c == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) return <NUM_LIT> ; return <NUM_LIT>


<s> auto NamePair = Name . split ( '.' ) ; if ( NamePair . second . empty ( ) ) std :: swap ( NamePair . first , NamePair . second ) ; while ( Lexer . isNot ( AsmToken :: EndOfStatement ) ) { auto & Tok = Lexer . getTok ( ) ; switch ( Tok . getKind ( ) ) { case AsmToken :: Identifier : { auto & Id = Lexer . getTok ( ) ; const MCExpr * Val ; SMLoc End ; if ( Parser . parsePrimaryExpr ( Val , End ) ) return Error ( <STR_LIT> , Lexer . getTok ( ) ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Id . getLoc ( ) , Id . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; break ; } case AsmToken ::


<s> SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackPtrOffsetReg ( ) && <STR_LIT> ) ; MachineOperand * OffsetOp = TII -> getNamedOperand (


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> ) return & <STR_LIT> ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) return & <STR_LIT> ; return RC


<s> auto & MFI = MF . getFrameInfo ( ) ; return MFI . getStackSize ( ) || MFI . adjustsStack ( ) || hasFP


<s> return COSTS_N_INSNS ( microblaze_address_insns ( addr ,


<s> } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; if ( ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) || ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ; Index = N ; return true ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> || Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op1 ) ; int32_t offset = int32_t ( CN -> getSExtValue ( ) ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op0 ) ; int FI = int ( FIN -> getIndex ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << offset << <STR_LIT> << FI << <STR_LIT> ) ; if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op0 ; return true ; } } else if ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 ) ; int32_t offset = int32_t ( CN -> getSExtValue ( ) ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op1 ) ; int FI = int ( FIN -> getIndex ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << offset << <STR_LIT> << FI << <STR_LIT> ) ; if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op1 ; return true ; } } } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> )


<s> std :: vector < std :: string > exchange_rjai ( Axh a , ArpRn2 b , ArpStep2 bsi , ArpStep2 bsj ) { return D ( <STR_LIT> , R ( a ) , MemARPSI ( b , bsi ) , MemARPSJ ( b ,


<s> assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } bool FallThru = FBB == nullptr ; unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned Opc = GetCondBranchFromCond ( CC ) ; BuildMI ( & MBB , DL , get ( Opc ) ) . addMBB ( TBB ) ; ++ Count ; if ( ! FallThru ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++


<s> mem2 = copy_rtx ( operands [ <NUM_LIT> ] ) ; if ( mode == SImode ) format = <STR_LIT> ; else format = <STR_LIT> ; } split_plus ( XEXP ( mem1 , <NUM_LIT> ) , & base1 , & offset1 ) ; split_plus ( XEXP ( mem2 , <NUM_LIT> ) , & base2 , & offset2 ) ; gcc_assert ( rtx_equal_p ( base1 , base2 ) ) ; auto size1 = MEM_SIZE ( mem1 ) ; auto size2 = MEM_SIZE ( mem2 ) ; gcc_assert ( known_eq ( size1 , size2 ) ) ; gcc_assert ( known_eq ( offset1 + size1 , offset2 ) ) ; HOST_WIDE_INT imm2 = offset1 >> shamt ; gcc_assert ( imm2 >= <NUM_LIT> && imm2 < <NUM_LIT> ) ; gcc_assert ( ( imm2 << shamt ) == offset1 ) ; gcc_assert ( REG_P ( reg1 ) ) ; gcc_assert ( REG_P ( reg2 ) ) ; gcc_assert ( REG_P ( base1 ) ) ; if ( load_p ) { gcc_assert ( REGNO ( reg1 ) != REGNO ( reg2 ) ) ; gcc_assert ( REGNO ( reg1 ) != REGNO ( base1 ) ) ; gcc_assert ( REGNO ( reg2 ) != REGNO ( base1 ) ) ; } output_operands [ <NUM_LIT> ] = copy_rtx ( reg1 ) ; output_operands [ <NUM_LIT> ] = copy_rtx (


<s> return ; } assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isFLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isFLDM ) ; } else O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << TRI -> getAsmName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ; } O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg


<s> if ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT> ) return <NUM_LIT> + std :: abs ( Imm ) ; return <NUM_LIT>


<s> unsigned Align = TFI -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( MBB , I , TII , dl , * this ,


<s> if ( ! named || mode == VOIDmode ) return <NUM_LIT> ; if ( targetm . calls . must_pass_in_stack ( mode


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; int Amount = TII . getFrameSize ( MI ) ; if ( Amount != <NUM_LIT> && ! hasReservedCallFrame (


<s> if ( tmv != NULL_TREE && CLASSTYPE_TYPEINFO_VAR ( tmv ) != NULL_TREE ) { tree na , ti_decl = CLASSTYPE_TYPEINFO_VAR ( tmv ) ; na = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , NULL_TREE ) ; decl_attributes ( & ti_decl , na , <NUM_LIT> ) ; } for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; for ( member = TYPE_METHODS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == FUNCTION_DECL ) { tree thunk ; maybe_add_dllexport ( member ) ; for ( thunk = DECL_THUNKS ( member ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) maybe_add_dllexport ( thunk ) ; } for ( member = CLASSTYPE_VTABLES ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllexport ( member ) ; } else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( t ) ) != NULL_TREE ) { for ( member = TYPE_FIELDS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == VAR_DECL ) maybe_add_dllimport ( member ) ; for ( member = TYPE_METHODS ( t ) ; member ; member = DECL_CHAIN ( member ) ) if ( TREE_CODE ( member ) == FUNCTION_DECL ) { tree thunk


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { printOperand ( MI ,


<s> case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc


<s> bool isCC = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( isCC ? <NUM_LIT> : <NUM_LIT> ) ; bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 . cloneMemRefs ( MI ) ; HI16 . cloneMemRefs ( MI ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT>


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsSHL ( uint64_t Imm , unsigned RemSize , InstSeqLs & SeqLs ) { unsigned Shamt = countTrailingZeros ( Imm ) ; GetInstSeqLs ( Imm >> Shamt , RemSize - Shamt ,


<s> switch ( mi -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( mi -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; if ( mi -> getOperand ( <NUM_LIT> ) . getMBB ( ) == OldSucc ) { mi -> getOperand ( <NUM_LIT> ) . setMBB ( NewSucc ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( mi -> getNumOperands ( ) == <NUM_LIT> ) ; unsigned index = mi -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; MJTI -> ReplaceMBBInJumpTable ( index , OldSucc , NewSucc ) ; break ; } case <STR_LIT> : case <STR_LIT> : case


<s> EVT Ty = Op . getValueType ( ) ; if ( GlobalAddressSDNode * N = dyn_cast < GlobalAddressSDNode > ( Op ) ) return DAG . getTargetGlobalAddress ( N -> getGlobal ( ) , SDLoc ( Op ) , Ty , <NUM_LIT> , Flag ) ; if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , <NUM_LIT> , Flag ) ; if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ; if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ; llvm_unreachable ( <STR_LIT> ) ; return SDValue (


<s> static bool isFlatGlobalAddrSpace ( unsigned AS ) { return AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS

:: CONSTANT_ADDRESS || AS > <ISA_LIT>AS :: MAX_<ISA_LIT>_ADDRESS ;


<s> StringRef getPassName ( ) const override { return


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Enable<ISA_LIT>TailCalls && ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return


<s> if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != <NUM_LIT> || maybe_gt ( initial_adjust , <NUM_LIT> ) ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; cfi_ops = NULL ; } aarch64_add_sp ( tmp0_rtx , tmp1_rtx , initial_adjust , ( ! can_inherit_p || ! crtl -> is_leaf || df_regs_ever_live_p ( EP0_REGNUM ) ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) = cfi_ops ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( aarch64_return_address_signing_enabled ( ) && ( for_sibcall || ! TARGET_ARMV8_3 || crtl -> calls_eh_return ) ) { switch ( aarch64_ra_sign_key ) { case AARCH64_KEY_A : insn = emit_insn ( gen_autiasp ( ) ) ; break ; case AARCH64_KEY_B : insn = emit_insn ( gen_autibsp ( ) ) ; break ; default : gcc_unreachable ( ) ; } add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn )


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget <


<s> void <ISA_LIT>IntelInstPrinter :: printSTiRegOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & OS ) { const MCOperand & Op = MI ->


<s> DecodeStatus status ; unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pos2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pos1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; status = DecodeDataRegsRegisterClass ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( pos1 ) ) ; status = DecodeDataRegsRegisterClass ( Inst , s2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo (


<s> RelocOut . outword ( BR24 . getPackedFields ( ) ) ; ++ NumRelocs ; } Addr -= MR . getMachineCodeOffset ( ) ; Addr >>= <NUM_LIT> ; Addr &= <NUM_LIT> ; Addr <<= <NUM_LIT> ; Addr |= ( SecOut [ MR . getMachineCodeOffset ( ) ] << <NUM_LIT> ) ; Addr |= ( SecOut [ MR . getMachineCodeOffset ( ) + <NUM_LIT> ] & <NUM_LIT> ) ; SecOut . fixword ( Addr , MR . getMachineCodeOffset ( ) ) ; break ; } case <STR_LIT> : { Addr -= MR . getMachineCodeOffset ( ) ; Addr &= <NUM_LIT> ; SecOut . fixhalf ( Addr , MR . getMachineCodeOffset ( ) + <NUM_LIT> ) ; break ; } case <STR_LIT> : { MachORelocation HA16 ( MR . getMachineCodeOffset ( ) , ToIdx , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_HA16 ) ; MachORelocation PAIR ( Addr & <NUM_LIT> , <NUM_LIT> , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_PAIR ) ; NumRelocs = <NUM_LIT> ; RelocOut . outword ( HA16 . getRawAddress ( ) ) ; RelocOut . outword ( HA16 . getPackedFields ( ) ) ; RelocOut . outword ( PAIR . getRawAddress ( ) ) ; RelocOut . outword ( PAIR . getPackedFields ( ) ) ; Addr += <NUM_LIT> ; SecOut . fixhalf ( Addr >> <NUM_LIT> , MR . getMachineCodeOffset ( ) + <NUM_LIT> ) ; break ; } case <STR_LIT> : { MachORelocation LO16 ( MR . getMachineCodeOffset ( ) , ToIdx , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_LO16 ) ; MachORelocation PAIR ( Addr >> <NUM_LIT> , <NUM_LIT> , false , <NUM_LIT> , isExtern , <ISA_LIT>_RELOC_PAIR ) ; NumRelocs = <NUM_LIT> ; RelocOut . outword ( LO16 . getRawAddress ( ) ) ; RelocOut . outword ( LO16 . getPackedFields ( ) ) ; RelocOut . outword ( PAIR . getRawAddress ( ) ) ; RelocOut . outword ( PAIR . getPackedFields (


<s> static bool IsVUZPShuffleNode ( SDNode * N ) { if ( N -> getOpcode ( ) == <STR_LIT>


<s> OutStreamer . EmitRawText ( Twine ( <STR_LIT> + ST . getTargetString ( ) + ( ST . supportsDouble ( ) ? <STR_LIT> : <STR_LIT> ) ) ) ; if ( ST . supports<ISA_LIT>23 ( ) ) { std :: string addrSize = ST . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; OutStreamer . EmitRawText ( Twine ( <STR_LIT> + addrSize ) ) ; } OutStreamer . AddBlankLine ( ) ; DebugInfoFinder DbgFinder ; DbgFinder . processModule ( M ) ; for ( DebugInfoFinder :: iterator I = DbgFinder . compile_unit_begin ( ) , E = DbgFinder . compile_unit_end ( ) ; I != E ; ++ I ) { DICompileUnit DIUnit ( * I ) ; StringRef FN = DIUnit . getFilename ( ) ; StringRef Dir = DIUnit . getDirectory ( ) ; GetOrCreateSourceID ( FN


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI


<s> NodeAddr < FuncNode * > DataFlowGraph :: newFunc ( MachineFunction * MF ) { NodeAddr < FuncNode * > FA = newNode ( NodeAttrs :: Code | NodeAttrs :: Func ) ; FA . Addr -> setCode ( MF


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _rdpkru_u32 ( void ) { return __builtin_ia32_rdpkru (


<s> <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT>


<s> while ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef ID = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Lex ( ) ; if ( ID == <STR_LIT> )


<s> I ++ ; MachineBasicBlock & MBB = * MIB -> getParent ( ) ; MachineOperand MO = MIB -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; if ( isPush ) { BuildMI ( MBB , I , DL , Desc ) . addReg ( RI .


<s> else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; return MIN ( STACK_BOUNDARY , MAX ( PARM_BOUNDARY ,


<s> } else { assert ( VA . isMemLoc ( ) ) ; ResultMemLocs . push_back ( std :: make_pair ( VA . getLocMemOffset ( ) , InVals . size ( ) ) ) ; InVals . push_back ( SDValue ( ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( unsigned i = <NUM_LIT> , e = ResultMemLocs . size ( ) ; i != e ; ++ i ) { int offset = ResultMemLocs [ i ] . first ; unsigned index = ResultMemLocs [ i ] . second ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( offset / <NUM_LIT> , <STR_LIT> ) } ; SDValue load = DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ; InVals [ index ] = load ; MemOpChains . push_back ( load . getValue ( <NUM_LIT> ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; return Chain


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) return false ; Imm = M [ <NUM_LIT> ] ; unsigned ExpectedElt = Imm ; for ( unsigned i = <NUM_LIT> ; i < NumElts


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; } Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base


<s> SDValue VQ = compressHvxPred ( Val , dl , WordTy , DAG ) ; unsigned BitWidth = ResTy . getSizeInBits ( ) ; if ( BitWidth < <NUM_LIT> ) { SDValue W0 = extractHvxElementReg ( VQ , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , dl , <STR_LIT> , DAG ) ; if ( BitWidth == <NUM_LIT> ) return W0 ; assert ( BitWidth < <NUM_LIT> ) ; return DAG . getZExtOrTrunc ( W0 , dl , ResTy ) ; } assert ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Words ; for ( unsigned i = <NUM_LIT> ; i != BitWidth / <NUM_LIT> ; ++ i ) { SDValue W = extractHvxElementReg ( VQ , DAG . getConstant ( i , dl , <STR_LIT> ) , dl , <STR_LIT> , DAG ) ; Words . push_back ( W ) ; } SmallVector < SDValue , <NUM_LIT> > Combines ; assert ( Words . size ( ) % <NUM_LIT> == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Words . size ( ) ; i < e ; i += <NUM_LIT> ) { SDValue C = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Words [ i + <NUM_LIT> ] , Words [ i ] } ) ; Combines . push_back ( C ) ; } if ( BitWidth == <NUM_LIT> ) return Combines [ <NUM_LIT> ] ; return DAG . getNode ( <STR_LIT> , dl , ResTy , Combines ) ; } if ( isHvxBoolTy ( ResTy ) && ValTy . isScalarInteger ( ) ) { unsigned BitWidth = ValTy . getSizeInBits ( ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( BitWidth == HwLen ) ; MVT ValAsVecTy = <STR_LIT> ( <STR_LIT> , BitWidth / <NUM_LIT> ) ; SDValue ValAsVec = DAG . getBitcast ( ValAsVecTy , Val ) ; SmallVector < SDValue , <NUM_LIT> > Bytes ; SmallVector < SDValue , <NUM_LIT> > Tmp ; for ( unsigned I = <NUM_LIT> ; I != HwLen / <NUM_LIT> ; ++ I ) { SDValue Idx = DAG . getConstant ( I , dl , <STR_LIT> ) ; SDValue Byte = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValAsVec , Idx ) ; for ( unsigned J = <NUM_LIT> ; J != <NUM_LIT> ; ++ J ) { Bytes . push_back ( Byte


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind


<s> Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( <STR_LIT> ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult


<s> if ( LoopFixer ( MF , MLI , nullptr ) . run ( ) ) { return true ; } SmallVector < MachineLoop * , <NUM_LIT> > Worklist ( MLI . begin ( ) , MLI . end ( ) ) ; while ( ! Worklist . empty ( ) ) { MachineLoop * Loop = Worklist . pop_back_val ( ) ; Worklist . append ( Loop -> begin ( ) , Loop -> end ( ) ) ; if ( LoopFixer ( MF , MLI , Loop ) . run ( ) ) { return true


<s> if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; return EncVal


<s> return ( vector unsigned char ) __builtin_altivec_vaddubs ( ( vector signed char ) a1


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; Register DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; Register DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; Register FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . insert ( & LoHalf ) ; Worklist . insert ( & HiHalf ) ; addUsersToMoveToVALUWorklist ( FullDestReg , MRI , Worklist


<s> LoadInst * getBaseLoad ( ) const { return VecLd . front (


<s> return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegExtendLarge : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed3SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1SImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm10 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2UImm5 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1UImm6 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT>


<s> std :: fill ( Aquired . begin ( ) + V . TopIdx , Aquired . begin ( ) + V .


<s> if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) ) adjustWritemask ( Node , DAG ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 =


<s> vld1q_dup_u32 ( const uint32_t * __a ) { return vdupq_n_u32 (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case


<s> return ! ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC ==


<s> int NumOp = MI . getNumExplicitOperands ( ) ; return MI . getOperand ( NumOp -


<s> unsigned <ISA_LIT>TTIImpl :: getRegisterBitWidth ( bool Vector ) { return Vector ? <NUM_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! MF . getFunction ( ) -> isVarArg ( ) ) { LRSpillSlot = MFI . CreateFixedObject ( RC -> getSize ( ) , <NUM_LIT> , true ) ; } else { LRSpillSlot = MFI . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment (


<s> if ( ! Desc . isCommutable ( ) ) return false ; unsigned Opc = Desc . getOpcode ( ) ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return false ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx ,


<s> processSwitches ( M , MAI , MMI ) ; processDefInstrs ( M ) ; numberRegistersGlobally ( M ) ; processOtherInstrs ( M ) ; if ( MAI . MS [ <STR_LIT> ] . empty ( ) ) MAI

. Reqs . addCapability ( Capability :: Linkage ) ;


<s> return TargetTriple . isOSBinFormatMachO


<s> MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; bool NeedsAligna = needsAligna ( MF ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; bool UseAligned = ! NeedsAligna && ( NeedAlign <= HasAlign ) ; unsigned StoreOpc = UseAligned


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == <NUM_LIT> && ( ! Alignment || * Alignment >= <NUM_LIT> ) ) || ( EltWidth == <NUM_LIT> && ( ! Alignment ||

* Alignment >= <NUM_LIT> ) ) || EltWidth == <NUM_LIT> ) ;


<s> default : return false ; case AMDGPU :: CUBE_r600_pseudo : case AMDGPU :: CUBE_r600_real : case AMDGPU :: CUBE_eg_pseudo : case AMDGPU :: CUBE_eg_real : return


<s> void printlea64mem ( const MCInst * MI , unsigned OpNo ,


<s> if ( ! readInstruction16 ( Bytes , Address , Size , insn16 ) ) { return Fail ; } DecodeStatus Result = decodeInstruction ( DecoderTable16 , instr , insn16 , Address , this , STI ) ; if ( Result != Fail ) { Size = <NUM_LIT> ; return Result


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; } if ( Inst . getOpcode ( ) != <STR_LIT> ) { unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( featureBits [ <STR_LIT> ] && ! featureBits [ <STR_LIT> ] ) { if ( Rt == <NUM_LIT> || Rt == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ; } else Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; } if ( featureBits [ <STR_LIT> ] ) { Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { unsigned pred = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT>


<s> StringRef getPassName ( ) const override { return


<s> if ( Sz == <NUM_LIT> ) return xchgTop ( <NUM_LIT> ) ; return reverse ( Sz


<s> SDValue Odd0 = DAG . getVectorShuffle ( VT , dl , Op0 , Op0 , Mask ) ; SDValue Odd1 = DAG . getVectorShuffle ( VT , dl , Op1 , Op1 , Mask ) ; MVT MulVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget . hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt


<s> return ( STI . getFeatureBits ( ) & <STR_LIT>


<s> bool <ISA_LIT>BitSimplify :: getSubregMask ( const BitTracker :: RegisterRef & RR , unsigned & Begin , unsigned & Width , MachineRegisterInfo & MRI ) { const TargetRegisterClass * RC = MRI . getRegClass ( RR . Reg ) ; if ( RC == & <STR_LIT> ) { assert ( RR . Sub == <NUM_LIT> ) ; Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } if ( RC == & <STR_LIT> ) { if ( RR . Sub == <NUM_LIT> ) { Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } assert ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) ; Width = <NUM_LIT> ; Begin = ( RR . Sub == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return true ; } return false


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT>


<s> return MCDisassembler :: Fail ; } unsigned Reg = GPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler


<s> uint64_t CurrBlockFreq = MBFI -> getBlockFreq ( MI -> getParent ( ) ) . getFrequency ( ) ; if ( CurrBlockFreq > EntryFreq || MPDT -> dominates ( MI -> getParent ( ) , Entry ) ) FI -> setMustSaveTOC ( true ) ; if ( FI -> mustSaveTOC ( ) ) { for ( auto & TOCSave : TOCSaves ) TOCSave . second = false ; TOCSaves [ MI ] = false ; return ; } bool Keep = true ; for ( auto It = TOCSaves . begin ( ) ; It != TOCSaves . end ( ) ; It ++ ) { MachineInstr * CurrInst = It -> first ; if ( It -> second && MDT -> dominates ( MI , CurrInst ) ) It -> second = false ; if ( MDT -> dominates ( CurrInst , MI ) ) { Keep = false ; break ; } } TOCSaves [ MI ]


<s> bool <ISA_LIT>PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false


<s> void <ISA_LIT>CodeEmitter :: emitGlobalAddress ( GlobalValue * GV , unsigned Reloc


<s> return new <ISA_LIT>Z80ELFStreamer ( S , STI


<s> static inline uint32_t helper_reencode_add_imm ( uint32_t pInst , uint32_t pImm ) { return ( pInst & ~ ( get_mask ( <NUM_LIT> ) << <NUM_LIT> ) ) | (

( pImm & get_mask ( <NUM_LIT> ) ) << <NUM_LIT> ) ;


<s> SDLoc DL ( N ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode ( <STR_LIT> , DL , Ty ,


<s> void <ISA_LIT>PostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; HazardRec . setDAG ( dag ) ; HazardRec . Reset


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>V8TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y (


<s> } } for ( MachineInstr & MI : llvm :: make_range ( InsertPt , EntryMBB . end ( ) ) ) { if ( IsArgument ( MI ) ) { EntryMBB . insert ( InsertPt , MI . removeFromParent (


<s> virtual const InstrItineraryData * getInstrItineraryData ( )


<s> const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; bool IsThreadLocal = GVar && GVar -> isThreadLocal


<s> static SDValue LowerScalarVariableShift ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned <ISA_LIT>OpcV = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Amt = peekThroughEXTRACT_SUBVECTORs ( Amt ) ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) { if ( SDValue BaseShAmt = IsSplatValue ( VT , Amt , dl , DAG , Subtarget , Opcode ) ) { MVT EltVT = VT . getVectorElementType ( ) ; assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , Subtarget , DAG ) ; } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ; std :: vector < SDValue > Vals


<s> scratch_reg = clearing_reg ; } mask = ( ~ padding_bits_to_clear [ i ] ) & <NUM_LIT> ; emit_move_insn ( scratch_reg , gen_int_mode ( mask , SImode ) ) ; mask = ( ~ padding_bits_to_clear [ i ] ) >> <NUM_LIT> ; rtx16 = gen_int_mode ( <NUM_LIT> , SImode ) ; dest = gen_rtx_ZERO_EXTRACT ( SImode , scratch_reg , rtx16 , rtx16 ) ; if ( mask ) emit_insn ( gen_rtx_SET ( dest , gen_int_mode ( mask , SImode ) ) ) ; emit_insn ( gen_andsi3 ( cleared_reg , cleared_reg , scratch_reg ) ) ; } if ( saved_clearing ) emit_move_insn ( clearing_reg , saved_clearing_reg ) ; if ( TARGET_HAVE_FPCXT_CMSE ) { rtvec vunspec_vec ; int i , j , k , nb_regs ; rtx use_seq , par , reg , set , vunspec ; int to_clear_bitmap_size = SBITMAP_SIZE ( to_clear_bitmap ) ; auto_sbitmap core_regs_bitmap ( to_clear_bitmap_size ) ; auto_sbitmap to_clear_core_bitmap ( to_clear_bitmap_size ) ; for ( i = FIRST_VFP_REGNUM ; i <= maxregno ; i += nb_regs ) { for ( ; i <= maxregno && ! bitmap_bit_p ( to_clear_bitmap , i ) ; i ++ ) ; if ( i > maxregno ) break ; for ( j = i ; j <= maxregno && bitmap_bit_p ( to_clear_bitmap , j ) ; j ++ ) ; nb_regs = j - i ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nb_regs + <NUM_LIT> ) ) ; vunspec_vec = gen_rtvec ( <NUM_LIT> , gen_int_mode ( <NUM_LIT> , SImode ) ) ; vunspec = gen_rtx_UNSPEC_VOLATILE ( SImode , vunspec_vec , VUNSPEC_VSCCLRM_VPR ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = vunspec ; start_sequence ( ) ; for ( k = <NUM_LIT> , j = i ; j <= maxregno && k < nb_regs + <NUM_LIT> ; j ++ ) { if ( ! bitmap_bit_p ( to_clear_bitmap ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG


<s> if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) return ; BuildMI ( MBB , MBB . begin ( ) , MBB . findDebugLoc ( MBB . begin ( ) ) , TII ->

get ( <STR_LIT> ) ) . addImm ( HintNum ) ;


<s> bool <ISA_LIT>TargetLowering :: enableAggressiveFMAFusion (


<s> for ( MachineInstr & MI : llvm :: reverse ( B ) ) Instrs . push_back ( & MI ) ; bool Changed = false ; for ( auto I : Instrs ) { unsigned Opc = I ->


<s> if ( isStore ) { if ( PtrReg == <STR_LIT> && ! PostPtrDead && ( isPostInc || isPostDec ) ) { IsPostOpc = true ; return isPostInc ? <STR_LIT> : <STR_LIT> ; } return


<s> SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , DL , TheVT , Value , ThreshVal ) ; Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Value = DAG . getSelect ( DL , TheVT , Cmp , Value , Sub ) ; } if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( MF , SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , DstTy , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , SSFI ) , MachineMemOperand :: MOStore , MemSize , MemSize ) ; if ( UnsignedFixup ) { SDValue FistOps [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getMemIntrinsicNode ( Opc , DL , DAG . getVTList ( <STR_LIT> ) , FistOps , DstTy , MMO ) ; SDValue Low32 = DAG . getLoad ( <STR_LIT> , DL , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue HighAddr = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , DL ) ; SDValue High32 = DAG . getLoad ( <STR_LIT> , DL , FIST , HighAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; High32 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High32 , Adjust ) ; if ( Subtarget . is64Bit ( ) ) { Low32 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low32


<s> if ( VT . isScalarInteger ( ) ) { if ( ! Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) ) return false ; if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { if ( ConstNode -> getAPIntValue ( ) . getBitWidth ( )

> <NUM_LIT> * sizeof ( int64_t ) ) return false ;


<s> return ( __m128 ) __builtin_ia32_cvtdq2ps128_mask ( ( __v4si ) __A , ( __v4sf ) _mm_setzero_ps ( )


<s> bool isStub = ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] == <NUM_LIT> ; RetAddr -- ; RetAddr -= <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << ( void * ) RetAddr << <STR_LIT> << ( void * ) StackPtr << <STR_LIT> << TheVM -> getFunctionReferencedName ( ( void * ) RetAddr ) << <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; assert ( isStub && <STR_LIT> <STR_LIT> ) ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ; if ( diff >= - <NUM_LIT> && diff <= <NUM_LIT> ) { * ( unsigned char * ) ( RetAddr - <NUM_LIT> ) = <NUM_LIT> ; * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = diff & <NUM_LIT> ; } else { * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = NewVal ; ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] = ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveCodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { if ( ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) || TT .

isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) {


<s> case 'd' : case 'f' : case 'h' : case 'r' : case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Immediate ; default : break ; } } else if ( Constraint . size ( ) == <NUM_LIT> && Constraint [ <NUM_LIT> ] == 'Z' ) { switch ( Constraint [


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator InsPt = Def && Def -> getParent ( ) == & MBB ? std :: next ( MachineBasicBlock :: iterator ( Def ) ) : MBB . begin ( ) ; MachineInstr * NewMI = BuildMI ( MBB , InsPt , DL , TII -> get ( OrOpc ) , Exec ) . addReg ( Exec ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps (


<s> continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; EVT VT = VA . getLocVT ( ) ; if ( VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = Splits [ i ] . VT ; SDValue Arg = LowerParameter ( DAG , VT , MemVT , DL , DAG . getRoot ( ) , <NUM_LIT> + VA . getLocMemOffset ( ) , Ins [ i ] . Flags . isSExt ( ) ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; unsigned Reg = VA . getLocReg ( ) ; if ( VT == <STR_LIT> ) { Reg = TRI -> getMatchingSuperReg ( Reg , AMDGPU :: sub0 , & AMDGPU :: SReg_64RegClass ) ; Reg = MF . addLiveIn ( Reg , & AMDGPU :: SReg_64RegClass ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ) ; continue ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; Reg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; if ( Arg . VT . isVector ( ) ) { Type * ParamType = FType -> getParamType ( Arg . OrigArgIndex ) ; unsigned NumElements = ParamType -> getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Regs ; Regs . push_back ( Val ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { Reg = ArgLocs [ ArgIdx ++ ] . getLocReg ( ) ; Reg = MF . addLiveIn ( Reg , RC ) ; Regs . push_back ( DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ) ; } NumElements = Arg . VT . getVectorNumElements ( ) - NumElements ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) Regs . push_back ( DAG . getUNDEF ( VT ) ) ; InVals . push_back ( DAG . getNode ( <STR_LIT> , DL , Arg . VT , Regs ) ) ; continue ; } InVals . push_back ( Val


<s> <STR_LIT> TD ( <ISA_LIT>ToLLVMType . lookup ( MIRBuilder . getMF ( ) . getRegInfo ( ) . getVRegDef ( ImageType -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) , ImageType ) ; if ( auto * Res = checkSpecialInstr ( TD , MIRBuilder ) ) return Res ; Register ResVReg = createTypeVReg (


<s> void <ISA_LIT>AsmPrinter :: emitJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned JTI ) { const MCExpr * Value = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Size = AFI -> getJumpTableEntrySize ( JTI ) ; if ( Size ==


<s> if ( TARGET_ARCH64 && type != <NUM_LIT> && AGGREGATE_TYPE_P


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( MemOp . getAlignment ( ) < Ty . getSizeInBits ( ) / <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlignment ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB ,


<s> Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; if ( SrcVT == <STR_LIT> ) { unsigned ResultReg = createResultReg ( &


<s> void printARII16Mem ( const MCInst * MI , unsigned opNum , raw_ostream & O ) { printARIIMem ( MI , opNum , O


<s> return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) +

<NUM_LIT> ) >= <NUM_LIT> && ( INTVAL ( mask ) & ( ( <NUM_LIT> << INTVAL ( shft_amnt ) ) - <NUM_LIT> ) ) == <NUM_LIT> ;


<s> return gen_nvptx_barsync ( lock , GEN_INT


<s> ( * lang_hooks . types . register_builtin_type ) ( float_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( double_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( intTI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intQI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intHI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intSI_type_node , <STR_LIT> ) ; ( * lang_hooks . types . register_builtin_type ) ( unsigned_intDI_type_node


<s> machine_mode result_mode ; rtx result_target ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode cmp_mode = GET_MODE ( cmp_op1 ) ; rtx op = ( cond == LT ) ? els : then ; if ( ( cond == LT || cond == GE ) && target_mode == cmp_mode && cmp_op2 == CONST0_RTX ( cmp_mode ) && op == CONST0_RTX ( target_mode ) && s390_vector_mode_supported_p ( target_mode ) && GET_MODE_CLASS ( target_mode ) == MODE_VECTOR_INT ) { rtx negop = ( cond == LT ) ? then : els ; int shift = GET_MODE_BITSIZE ( GET_MODE_INNER ( target_mode ) ) - <NUM_LIT> ; if ( negop == CONST1_RTX ( target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , LSHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } else if ( all_ones_operand ( negop , target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } } result_mode = mode_for_int_vector ( cmp_mode ) . require ( ) ; result_target = gen_reg_rtx ( result_mode ) ; if ( ! REG_P ( cmp_op1 ) ) cmp_op1 = force_reg ( GET_MODE ( cmp_op1 ) , cmp_op1 ) ; if ( ! REG_P ( cmp_op2 ) ) cmp_op2 = force_reg ( GET_MODE ( cmp_op2 ) , cmp_op2 ) ; s390_expand_vec_compare ( result_target , cond , cmp_op1 , cmp_op2 ) ; if ( all_ones_operand ( then , GET_MODE ( then ) ) && const0_operand ( els


<s> SDValue StoredVal = St -> getValue ( ) ; if ( StoredVal . getValueType ( ) . isVector ( ) && StoredVal . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { assert ( StoredVal . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ! St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( )


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ?


<s> bool OptimizeReturned :: runOnFunction ( Function & F ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << F . getName ( ) << '\n' ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; visit (


<s> static DecodeStatus DecodeShiftRight16Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Val


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; return <STR_LIT>


<s> texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; return ( _TEXASRU_EXTRACT_BITS ( texasru , <NUM_LIT> , <NUM_LIT> )


<s> unsigned VF = VecTy -> getVectorNumElements ( ) / Factor ; Type * ScalarTy = VecTy -> getVectorElementType ( ) ; unsigned VecTySize = DL . getTypeStoreSize ( VecTy ) ; unsigned LegalVTSize = LegalVT . getStoreSize ( ) ; unsigned NumOfMemOps = ( VecTySize + LegalVTSize - <NUM_LIT> ) / LegalVTSize ; Type * SingleMemOpTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , Alignment , AddressSpace ) ; VectorType * VT = VectorType :: get ( ScalarTy , VF ) ; EVT ETy = TLI -> getValueType ( DL , VT ) ; if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( Opcode == Instruction


<s> assemble_name ( file , fnname ) ; putc ( '\n' , file ) ; } inside_function = FALSE ; if ( TARGET_ABI_UNICOSMK ) { unicosmk_output_ssib ( file ,


<s> return GV -> getType ( ) -> getAddressSpace ( )


<s> return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> EVT SubVT = SubVec . getValueType ( ) ; if ( ! VecVT . isFixedLengthVector ( ) || ! DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VecVT ) || ! DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( SubVT ) ) return SDValue ( ) ; if ( IdxVal == <NUM_LIT> && Vec . isUndef ( ) ) return SDValue ( ) ; unsigned NumSubElts = SubVT . getVectorNumElements ( ) ; if ( ( SubVT . getSizeInBits ( ) * <NUM_LIT> ) != VecVT . getSizeInBits ( ) || ( IdxVal != <NUM_LIT> && IdxVal != NumSubElts ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue Lo , Hi ; if ( IdxVal == <NUM_LIT> )


<s> void <ISA_LIT>ConstantIslands :: doInitialPlacement ( std :: vector < MachineInstr * > & CPEMIs ) { MachineBasicBlock * BB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( BB ) ; unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( AlignConstantIslands ? MaxAlign : <NUM_LIT> ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getTarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ; CPEntries . push_back ( CPEs ) ; ++ NumCPEs ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } DEBUG ( BB ->


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops ( get<ISA_LIT>TargetMachine ( )


<s> if ( VT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) ) return Lower256IntArith ( Op , DAG ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { assert ( Subtarget -> hasSSE2 ( ) && ! Subtarget -> hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getNode ( <STR_LIT> , dl , VT , Evens ) ; Odds = DAG . getNode ( <STR_LIT> , dl , VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; EVT MulVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; A = DAG . getNode ( <STR_LIT> , dl , MulVT , A ) ; B = DAG . getNode ( <STR_LIT> , dl , MulVT , B ) ; Ahi = DAG . getNode ( <STR_LIT> , dl , MulVT , Ahi ) ; Bhi = DAG . getNode ( <STR_LIT> , dl , MulVT , Bhi


<s> case AVR_BUILTIN_NOP : emit_insn ( gen_nopv ( GEN_INT ( <NUM_LIT> ) ) ) ; return <NUM_LIT> ; case AVR_BUILTIN_DELAY_CYCLES : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) error ( <STR_LIT> , bname ) ; else avr_expand_delay_cycles ( op0 ) ; return NULL_RTX ; } case AVR_BUILTIN_NOPS : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) error ( <STR_LIT> , bname ) ; else avr_expand_nops ( op0 ) ; return NULL_RTX ; } case AVR_BUILTIN_INSERT_BITS : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) { error ( <STR_LIT> <STR_LIT> , bname ) ; return target ; } break ; } case AVR_BUILTIN_ROUNDHR : case AVR_BUILTIN_ROUNDUHR : case AVR_BUILTIN_ROUNDR : case AVR_BUILTIN_ROUNDUR : case AVR_BUILTIN_ROUNDLR : case AVR_BUILTIN_ROUNDULR : case AVR_BUILTIN_ROUNDLLR : case AVR_BUILTIN_ROUNDULLR : case AVR_BUILTIN_ROUNDHK : case AVR_BUILTIN_ROUNDUHK : case AVR_BUILTIN_ROUNDK : case AVR_BUILTIN_ROUNDUK : case AVR_BUILTIN_ROUNDLK : case AVR_BUILTIN_ROUNDULK : case AVR_BUILTIN_ROUNDLLK : case AVR_BUILTIN_ROUNDULLK : if ( TREE_CODE ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) != INTEGER_CST ) break ; int rbit = ( int ) TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( rbit >= ( int ) GET_MODE_FBIT ( mode ) ) { warning ( OPT_Wextra , <STR_LIT> <STR_LIT> , rbit , GET_MODE_FBIT ( mode ) ) ; return expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) , NULL_RTX , mode , EXPAND_NORMAL ) ; } else if ( rbit <= - ( int ) GET_MODE_IBIT ( mode ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; return CONST0_RTX ( mode ) ; } break ; } if ( d -> icode == CODE_FOR_nothing && DECL_ASSEMBLER_NAME ( get_callee_fndecl ( exp ) ) != NULL_TREE ) { return expand_call ( exp , target , ignore ) ; } gcc_assert ( d -> icode != CODE_FOR_nothing ) ; gcc_assert ( d -> n_args == call_expr_nargs ( exp ) ) ; if ( d -> n_args == <NUM_LIT> ) { emit_insn ( ( GEN_FCN ( d -> icode ) ) ( target ) ) ; return NULL_RTX


<s> int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value <


<s> bool is64bit = VT == <STR_LIT> || VT == <STR_LIT> ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return


<s> auto * Src1Imm = getImmOrMaterializedImm ( * MRI , * Src1 ) ; if ( ! Src1Imm -> isIdenticalTo ( * Src0Imm ) ) return false ; } int Src1ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src1_modifiers ) ; int Src0ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src0_modifiers ) ; if ( ( Src1ModIdx != - <NUM_LIT> && MI . getOperand ( Src1ModIdx ) . getImm ( ) != <NUM_LIT> ) || ( Src0ModIdx != - <NUM_LIT> && MI . getOperand ( Src0ModIdx ) . getImm ( ) != <NUM_LIT> ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <<


<s> case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit


<s> if ( CmpOp0 . getValueType ( ) == <STR_LIT> ) { SDValue H0 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp0 ) ; SDValue L0 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp0 ) ; SDValue H1 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp1 ) ; SDValue L1 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp1 ) ; SDValue HRes = DAG . getNode ( Opcode , DL , <STR_LIT> , H0 , H1 ) ; SDValue LRes = DAG . getNode ( Opcode , DL , <STR_LIT> , L0 , L1


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target


<s> ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI != E ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; if ( isMatchingUpdateInsn ( I , MI , BaseReg , UnscaledOffset ) ) return MBBI ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] || UsedRegs [ BaseReg ] ) return E ; } return E


<s> if ( CS -> arg_size ( ) != CallerFn -> arg_size ( ) ) return false ; ImmutableCallSite :: arg_iterator CalleeArgIter = CS -> arg_begin ( ) ; ImmutableCallSite :: arg_iterator CalleeArgEnd = CS -> arg_end ( ) ; Function :: const_arg_iterator CallerArgIter = CallerFn -> arg_begin ( ) ; for ( ; CalleeArgIter != CalleeArgEnd ; ++ CalleeArgIter , ++ CallerArgIter ) { const Value * CalleeArg


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( Size == <NUM_LIT> && <STR_LIT> ) ; auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad ,


<s> const DataLayout * DL = TLI -> getDataLayout ( ) ; if ( Alignment == <NUM_LIT> && ! Subtarget -> isTargetDarwin ( ) ) Alignment = DL -> getABITypeAlignment ( GV -> getType ( ) -> getElementType ( ) ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC >> Scale , <STR_LIT> ) ; return true ; } } } if ( SelectAddrModeUnscaled ( N , Size , Base , OffImm ) ) return false ; Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> oldval = convert_modes ( SImode , mode , oldval , <NUM_LIT> ) ; if ( ! TARGET_SYNC_HI_QI ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; oldval = expand_simple_binop ( SImode , ASHIFT , oldval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; newval = convert_modes ( SImode , mode , newval , <NUM_LIT> ) ; newval = expand_simple_binop ( SImode , ASHIFT , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } else if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; if ( mode != TImode && ! reg_or_short_operand ( oldval , mode ) ) oldval = copy_to_mode_reg ( mode , oldval ) ; if ( reg_overlap_mentioned_p ( retval , newval ) ) newval = copy_to_reg ( newval ) ; mem = rs6000_pre_atomic_barrier ( mem , mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; cond = gen_reg_rtx (


<s> static DecodeStatus DecodeOperandRegister ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , RegNo , Address , Decoder ) ; if ( status == MCDisassembler ::


<s> vcreate_u64 ( uint64_t __a ) { return ( uint64x1_t ) {


<s> Chain = DAG . getCopyToReg ( <ISA_LIT> . getValue ( <NUM_LIT> ) , dl , <ISA_LIT>Reg , New<ISA_LIT> ) ; unsigned regSpillArea = Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; regSpillArea += Subtarget -> getStackPointerBias ( ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , dl , VT , New<ISA_LIT> , DAG . getConstant ( regSpillArea


<s> ++ OpOffset ; } Register RSrc = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; const unsigned NumVIndexOps = IsCmpSwap ? <NUM_LIT> : <NUM_LIT> ; const bool HasVIndex = MI . getNumOperands ( ) == NumVIndexOps ; Register VIndex ; if ( HasVIndex ) { VIndex = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; ++ OpOffset ; } Register VOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; unsigned AuxiliaryData = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; unsigned ImmOffset ; unsigned TotalOffset ; std :: tie ( VOffset , ImmOffset , TotalOffset ) = splitBufferOffsets ( B , VOffset ) ; if ( TotalOffset != <NUM_LIT> ) MMO = B . getMF ( ) . getMachineMemOperand ( MMO , TotalOffset , MMO -> getSize


<s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ) ; } } if ( isVarArg ) { static const unsigned GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumGPRs = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned VARegSize = ( <NUM_LIT> - NumGPRs ) * <NUM_LIT> ; unsigned VARegSaveSize = ( VARegSize + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ; unsigned ArgOffset = CCInfo . getNextStackOffset ( ) ; if ( VARegSaveSize ) { AFI -> setVarArgsRegSaveSize ( VARegSaveSize ) ; VarArgsFrameIndex = MFI -> CreateFixedObject ( VARegSaveSize , ArgOffset + VARegSaveSize - VARegSize , true , false ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( ; NumGPRs < <NUM_LIT> ; ++ NumGPRs


<s> insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; } } return true


<s> llvm :: call_once ( InitGroupsOnceFlag , [ ] ( ) { get<ISA_LIT>InstrFMA3Info ( ) -> initGroupsOnceImpl (


<s> bool <ISA_LIT>TargetLowering :: isCtlzFast ( ) const { return Subtarget . hasFastLZCNT ( )


<s> tree decl ; decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && TREE_SYMBOL_REFERENCED ( DECL_ASSEMBLER_NAME ( decl ) ) ) { TREE_ASM_WRITTEN ( decl ) = <NUM_LIT> ; i386_pe_declare_function_type ( asm_out_file , p -> name ,


<s> emit_insn ( gen_strmov ( destptr , dest , srcptr , src ) ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } } else { rtx offset = force_reg ( Pmode , const0_rtx ) ; rtx tmp ; if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; src = change_address ( srcmem , SImode , srcptr ) ; dest = change_address ( destmem , SImode , destptr ) ; emit_move_insn ( dest , src ) ; tmp = expand_simple_binop ( Pmode , PLUS , offset , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_LIB_WIDEN ) ; if ( tmp != offset ) emit_move_insn ( offset , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; tmp = gen_rtx_PLUS ( Pmode , srcptr , offset ) ; src = change_address ( srcmem , HImode , tmp ) ; tmp = gen_rtx_PLUS ( Pmode , destptr , offset ) ; dest = change_address ( destmem , HImode , tmp ) ; emit_move_insn ( dest , src ) ; tmp = expand_simple_binop ( Pmode , PLUS , offset , GEN_INT ( <NUM_LIT> ) , tmp , true , OPTAB_LIB_WIDEN ) ; if ( tmp != offset ) emit_move_insn ( offset , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; tmp = gen_rtx_PLUS ( Pmode , srcptr , offset ) ; src = change_address ( srcmem , QImode , tmp ) ; tmp = gen_rtx_PLUS ( Pmode , destptr , offset ) ; dest = change_address ( destmem , QImode , tmp ) ; emit_move_insn ( dest , src ) ; emit_label (


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Bits = getBinaryCodeForInstr ( MI ,


<s> static bool isCPUValid ( std :: string CPU ) { std :: vector < std :: string > table { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SDValue Operands [ ] = { Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT>


<s> if ( sh_multcost >= <NUM_LIT> ) return sh_multcost ; if ( TARGET_SHMEDIA ) return optimize_size ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_SH2 ) { if ( optimize_size ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( optimize_size ) return <NUM_LIT>


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase &


<s> for ( int Index = Begin ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VGPR_32RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_64RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_96RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <=

End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_128RegClass . getRegister ( Index ) ) ;


<s> if ( mode == DImode && ne == <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && nb == <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - ne ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && GET_CODE ( operands [ <NUM_LIT> ] ) != LSHIFTRT && CONST_INT_P ( operands [ <NUM_LIT> ] ) && ne == INTVAL ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( nb < <NUM_LIT> && ne < <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT>


<s> return std :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit


<s> static void set_reg ( struct unw_reg_info * reg , enum unw_where where , int when ,


<s> if ( <ISA_LIT>TII -> getMemOperandWithOffset ( * SU -> getInstr ( ) , BaseLatOp , OffLatReg , OffsetIsScalable , TRI ) ) LowLatencyOffset [ i ] = OffLatReg ; } else if ( <ISA_LIT>TII -> isHighLatencyDef ( SU -> getInstr ( ) -> getOpcode ( ) ) ) IsHighLatencySU [ i ] = <NUM_LIT> ; } <ISA_LIT>Scheduler Scheduler ( this ) ; Best = Scheduler . scheduleVariant ( <STR_LIT> , <STR_LIT> ) ; if ( Best . MaxVGPRUsage > <NUM_LIT> ) { static const std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > Variants [ ] = { { LatenciesAlone , BlockRegUsageLatency } , { LatenciesGrouped , BlockLatencyRegUsage } , { LatenciesAlonePlusConsecutive , BlockLatencyRegUsage } , } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } if ( Best . MaxVGPRUsage > <NUM_LIT> ) { static const std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > Variants [ ] = { { LatenciesAlone , BlockRegUsage } , { LatenciesGrouped , BlockRegUsageLatency } , { LatenciesGrouped , BlockRegUsage } , { LatenciesAlonePlusConsecutive , BlockRegUsageLatency } , { LatenciesAlonePlusConsecutive , BlockRegUsage } } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } ScheduledSUnits = Best . SUs ; ScheduledSUnitsInv . resize ( SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ( unsigned ) SUnits . size ( ) ; i != e ; ++ i ) { ScheduledSUnitsInv [ ScheduledSUnits [ i ] ] = i ; } moveLowLatencies ( ) ; assert ( TopRPTracker . getPos ( ) == RegionBegin && <STR_LIT> ) ; TopRPTracker . setPos ( CurrentTop ) ; for ( unsigned I : ScheduledSUnits ) { SUnit * SU = & SUnits [ I ] ; scheduleMI ( SU , true ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << * SU -> getInstr ( ) ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * begin ( ) -> getParent (


<s> } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; if ( B . mayHaveInlineAsmBr ( ) ) DefaultToAll = true ; if ( ! DefaultToAll ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( const MachineBasicBlock * SB : B . successors ( ) ) Targets . insert ( SB ) ; } for ( const MachineBasicBlock * TB : Targets ) FlowQ . push ( CFGEdge ( ThisN


<s> if ( TARGET_WINDOWED_ABI ) emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode


<s> unsigned ShiftValue = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { OS << uint8_t (


<s> void addImm ( int64_t imm ) { Imm += imm


<s> return ( __m128i ) __builtin_ia32_pmuludq128 ( ( __v4si ) __A , ( __v4si )


<s> if ( auto * VecTy = dyn_cast < VectorType > ( Ty ) ) return ConstantVector :: getSplat ( VecTy -> getElementCount ( ) , Minus1 ) ; return Minus1


<s> return create<ISA_LIT>ELFStreamer ( T , Context , std :: move ( MAB ) , OS


<s> void <ISA_LIT>InstPrinter :: printSVEImm ( T Value , raw_ostream & O ) { typename std :: make_unsigned < T > :: type HexValue = Value ; if ( getPrintImmHex ( ) ) O << '#' << formatHex ( ( uint64_t ) HexValue ) ; else O << '#' << formatDec ( Value ) ; if ( CommentStream ) { if ( getPrintImmHex ( ) ) * CommentStream << '=' << formatDec ( HexValue ) << '\n' ; else * CommentStream << '=' << formatHex ( ( uint64_t ) Value ) <<