<s> if ( ! TARGET_64BIT && ( cfun_fpr_save_p ( FPR4_REGNUM ) || cfun_fpr_save_p ( FPR6_REGNUM ) ) ) return false ; if ( cfun -> machine -> base_reg && ! call_really_used_regs [ REGNO ( cfun -> machine -> base_reg ) ] ) return false ; return cfun_frame_layout .


<s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( FuncInfo


<s> if ( VT . isVector ( ) ) return LowerVSETCC ( Op , Subtarget , DAG ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerAndToBT ( Op0 , CC , dl , DAG ) ) return NewSetCC ; } if ( SDValue NewSetCC = EmitKTEST ( Op0 , Op1 , CC , dl , DAG , Subtarget ) ) return NewSetCC ; if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant (


<s> if ( pdp10_arch && TARGET_CPU == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , pdp10_arch ) ; if ( pdp10_tune && target_tune == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , pdp10_tune ) ; if ( TARGET_CPU == <NUM_LIT> ) target_flags = ( target_flags & ~ CPU_MASK ) | CPU_XKL1 ; if ( target_tune == <NUM_LIT> ) target_tune = CPU_XKL1 ; if ( ( target_flags & OPT_EXTENDED ) && ( target_flags & OPT_UNEXTENDED ) ) fprintf ( stderr , <STR_LIT> ) ; if ( target_flags & OPT_EXTENDED ) target_flags |= CPU_EXTENDED ; if ( target_flags & OPT_UNEXTENDED ) target_flags &= ~ CPU_EXTENDED ; if ( pdp10_model ) { if ( strcmp ( pdp10_model , <STR_LIT> ) == <NUM_LIT> ) target_model = MODEL_SMALL ; else if ( strcmp ( pdp10_model , <STR_LIT> ) == <NUM_LIT> ) target_model = MODEL_SMALLISH ; else if ( strcmp ( pdp10_model , <STR_LIT> ) == <NUM_LIT> ) target_model = MODEL_MEDIUM ; else if ( strcmp ( pdp10_model , <STR_LIT> ) == <NUM_LIT> ) target_model = MODEL_LARGE ; else fprintf ( stderr , <STR_LIT> , pdp10_model ) ; } if ( target_model == MODEL_NONE ) { if ( TARGET_EXTENDED ) { if ( TARGET_XKL1 || TARGET_XKL2 ) target_model = MODEL_SMALLISH ; else target_model = MODEL_LARGE ; } else target_model = MODEL_SMALL ; } if ( TARGET_EXTENDED ) { if ( ! pdp10_text_psect ) pdp10_text_psect = ( char * ) <STR_LIT> ; pdp10_text_section_asm_op = xmalloc ( <NUM_LIT> + strlen ( pdp10_text_psect ) ) ; sprintf ( pdp10_text_section_asm_op , <STR_LIT> , pdp10_text_psect ) ; if ( ! pdp10_rodata_psect ) pdp10_rodata_psect = ( char * ) <STR_LIT> ; pdp10_rodata_section_asm_op = xmalloc ( <NUM_LIT> + strlen ( pdp10_rodata_psect ) ) ; sprintf ( pdp10_rodata_section_asm_op , <STR_LIT> , pdp10_rodata_psect ) ; if ( ! pdp10_data_psect ) pdp10_data_psect = ( char * ) <STR_LIT> ; pdp10_data_section_asm_op = xmalloc ( <NUM_LIT> + strlen ( pdp10_data_psect ) ) ; sprintf ( pdp10_data_section_asm_op , <STR_LIT> , pdp10_data_psect ) ; if ( ! pdp10_bss_psect ) pdp10_bss_psect = ( char


<s> if ( f == NULL ) goto fallback_cpu ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) if ( startswith ( buf , <STR_LIT> ) ) { if ( strstr ( buf , <STR_LIT> ) != NULL || strstr ( buf , <STR_LIT> ) != NULL || strstr ( buf , <STR_LIT> ) != NULL ) cpu = <STR_LIT> ; else if ( strstr ( buf , <STR_LIT> ) != NULL || strstr ( buf , <STR_LIT> ) != NULL || strstr ( buf , <STR_LIT> ) != NULL ) cpu = <STR_LIT> ; else if ( strstr ( buf , <STR_LIT> ) != NULL || strstr ( buf , <STR_LIT> ) != NULL || strstr ( buf , <STR_LIT> ) != NULL ) cpu = <STR_LIT> ; else if ( strstr ( buf , <STR_LIT> ) != NULL ) cpu = <STR_LIT> ; else if ( strstr ( buf , <STR_LIT> ) != NULL ) cpu = <STR_LIT> ; else if ( strstr ( buf , <STR_LIT> ) != NULL


<s> SavedVGPRs . clearBitsNotInMask ( TRI -> getAllVectorRegMask ( ) ) ; if ( ! ST . hasGFX90AInsts ( ) ) SavedVGPRs . clearBitsInMask ( TRI -> getAllAGPRRegMask ( ) ) ; const bool WillHaveFP = FrameInfo . hasCalls ( ) && ( SavedVGPRs . any ( ) || ! allStackObjectsAreDead ( FrameInfo ) ) ; for ( auto SSpill : MFI -> getSGPRSpillVGPRs ( ) ) SavedVGPRs . reset ( SSpill . VGPR ) ; LivePhysRegs LiveRegs ; LiveRegs . init ( * TRI ) ; if ( WillHaveFP || hasFP ( MF ) ) { assert ( ! MFI -> SGPRForFPSaveRestoreCopy && ! MFI -> FramePointerSaveIndex && <STR_LIT>


<s> else if ( el_mode == SFmode && n == <NUM_LIT> ) { name [ <NUM_LIT> ] = 's' ; name [ <NUM_LIT> ] = '4' ; } else return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( el_mode == DFmode ? double_type_node : float_type_node , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; sprintf ( name + <NUM_LIT> , <STR_LIT> , bname + <NUM_LIT> ) ; arity = <NUM_LIT> ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ; args = TREE_CHAIN


<s> if ( TARGET_LS64 ) aarch64_init_ls64_builtins ( )


<s> unsigned <ISA_LIT>FastISel :: materialize32BitInt ( int64_t Imm , const TargetRegisterClass * RC ) { unsigned ResultReg = createResultReg ( RC ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) { unsigned Opc = <STR_LIT> ; emitInst ( Opc , ResultReg ) . addReg ( <STR_LIT> ) . addImm ( Imm ) ; return ResultReg ; } else if ( isUInt < <NUM_LIT> > ( Imm ) ) { emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) .


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional <


<s> FrameReg = RI -> getFrameRegister ( MF ) ; return MF . getFrameInfo ( ) . getObjectOffset ( FI


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) return true ; if ( Opcode == <STR_LIT> ) { auto F = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; if ( F . isNaN ( ) && F . isSignaling ( ) ) return false ; return ! F . isDenormal ( ) || denormalsEnabledForType ( MRI . getType ( Reg ) , MF ) ; } if ( MaxDepth == <NUM_LIT> ) return false ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> supportsMinMaxDenormModes ( ) || denormalsEnabledForType ( MRI . getType ( Reg )


<s> if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , FnSection . getUniqueID ( ) , & FnSection ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection


<s> SDValue Arg = isFNEG ( DAG , N ) ; if ( ! Arg ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = Arg . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; SDLoc DL ( N ) ; if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) . hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ; return DAG . getBitcast ( OrigVT , NewNode ) ; } bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand


<s> if ( useskip ) strcpy ( buf , <STR_LIT> ) ; else strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( useskip ) strcat ( buf , <STR_LIT> ) ; else if ( nullify ) { if ( branch_needs_nop_p ( insn ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else strcat ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( dbr_sequence_length ( ) != <NUM_LIT> && ! forward_branch_p ( insn ) && nullify ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; strcat ( buf , <STR_LIT> ) ; } else if ( dbr_sequence_length ( ) == <NUM_LIT> && ! forward_branch_p ( insn ) && INSN_ADDRESSES_SET_P ( ) && VAL_14_BITS_P ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( insn ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) - <NUM_LIT> ) ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf ,


<s> BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return ; } MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( Src . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <STR_LIT> )

. addReg ( TmpReg ) . addImm ( <STR_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand ::


<s> _Unwind_Reason_Code __gnu_Unwind_Resume ( _Unwind_Control_Block * ucbp , phase2_vrs * entry_vrs ) { _Unwind_Reason_Code pr_result ; entry_vrs -> core . r [ R_PC ] = UCB_SAVED_CALLSITE_ADDR ( ucbp ) ; if ( UCB_FORCED_STOP_FN ( ucbp


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { return TargetLowering :: getConstraintType (


<s> return ( arg . mode == BLKmode || ( arg . type && TREE_CODE ( arg . type ) == RECORD_TYPE ) || ( arg . type && TREE_CODE ( arg . type


<s> if ( desc . hasDelaySlot ( ) || desc . isBranch ( ) || isDelayFiller ( MBB , I ) || desc . isCall ( ) || desc . isReturn ( ) || desc . isBarrier ( ) || desc . hasUnmodeledSideEffects ( ) ) break ; if ( hasImmInstruction ( I ) || delayHasHazard ( I


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C


<s> bool IsOptimizingSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; bool HasFastHOps = Subtarget . hasFastHorizontalOps ( ) ; return ! IsSingleSource || IsOptimizingSize


<s> const BasicBlockInfo & BBI = BBInfo [ U . MI -> getParent ( ) -> getNumber ( ) ] ; unsigned KnownBits = BBI


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo (


<s> const <ISA_LIT>InstrInfo * getInstrInfo


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT>


<s> bool IsSafe = false ; MachineBasicBlock :: iterator E = CmpInstr . getParent ( ) -> end ( ) ; for ( ++ I ; I != E ; ++ I ) { const MachineInstr & Instr = * I ; bool ModifiesFlags = Instr . modifiesRegister ( <STR_LIT> , TRI ) ; bool UsesFlags = Instr . readsRegister ( <STR_LIT> , TRI ) ; if ( ModifiesFlags && ! UsesFlags ) { IsSafe = true ; break ; } if ( ! ModifiesFlags && ! UsesFlags ) { continue ; } if ( IsCmpZero ) { <STR_LIT> OldCC ; switch ( Instr . getOpcode ( ) ) { default : OldCC = <STR_LIT> ; break ; case <STR_LIT> : OldCC = static_cast < <STR_LIT> > ( Instr . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OldCC = <STR_LIT> ; break ; } switch ( OldCC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } if ( ModifiesFlags || Instr . killsRegister ( <STR_LIT> , TRI ) ) { IsSafe = true ; break ; } } if ( IsCmpZero && ! IsSafe ) { MachineBasicBlock * MBB = CmpInstr . getParent ( ) ; for ( MachineBasicBlock * Successor : MBB -> successors ( ) ) if ( Successor -> isLiveIn ( <STR_LIT> ) ) { return false ; } } if ( IsCmpZero ) { SubInstr = MI ; } unsigned i = <NUM_LIT> , e = SubInstr -> getNumOperands ( ) ; for ( ; i != e ; ++ i ) { MachineOperand & MO = SubInstr -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { MO . setIsDead ( false ) ; break ; } } assert ( i != e && <STR_LIT> ) ; CmpInstr . eraseFromParent ( ) ; return true ; switch ( CmpInstr . getOpcode ( ) ) { default : return false ; case <STR_LIT> : if ( ! CmpInstr . getOperand ( <NUM_LIT> ) . getImm ( ) ) { CmpInstr . setDesc ( get ( <STR_LIT> ) ) ; CmpInstr . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; return true ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT>


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = STI . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * STI . getInstrInfo


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg (


<s> virtual const <ISA_LIT>65816RegisterInfo & getRegisterInfo ( ) const { return RI


<s> if ( Code16GCC ) SwitchMode ( <STR_LIT> ) ; unsigned rv = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MissingFeatures , matchingInlineAsm , VariantID ) ; if ( Code16GCC ) SwitchMode ( <STR_LIT> ) ; return


<s> if ( this -> <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; } else { return


<s> SmallVector < Register , <NUM_LIT> > Ops ; if ( Is64 ) { auto Unmerge = B . buildUnmerge ( { S32 , S32 } , NodePtr ) ; Ops . push_back ( Unmerge . getReg ( <NUM_LIT> ) ) ; Ops . push_back ( Unmerge . getReg ( <NUM_LIT> ) ) ; } else { Ops . push_back ( NodePtr ) ; } Ops . push_back ( RayExtent ) ; auto packLanes = [ & Ops , & S32 , & B ] ( Register Src ) { auto Unmerge = B . buildUnmerge ( { S32 , S32 , S32 , S32 } , Src ) ; Ops . push_back ( Unmerge . getReg ( <NUM_LIT> ) ) ; Ops . push_back ( Unmerge . getReg ( <NUM_LIT> ) ) ; Ops . push_back ( Unmerge . getReg ( <NUM_LIT> ) ) ; } ; packLanes ( RayOrigin ) ; if ( IsA16 ) { auto UnmergeRayDir = B . buildUnmerge ( { S16 , S16 , S16 , S16 } , RayDir ) ; auto UnmergeRayInvDir = B . buildUnmerge ( { S16 , S16 , S16 , S16 } , RayInvDir ) ; Register R1 = MRI . createGenericVirtualRegister ( S32 ) ; Register R2 = MRI . createGenericVirtualRegister ( S32 ) ; Register R3 = MRI . createGenericVirtualRegister ( S32 ) ; B . buildMerge ( R1 , { UnmergeRayDir . getReg ( <NUM_LIT> ) , UnmergeRayDir . getReg ( <NUM_LIT> ) } ) ; B . buildMerge ( R2 , { UnmergeRayDir . getReg ( <NUM_LIT> ) , UnmergeRayInvDir . getReg ( <NUM_LIT> ) } ) ; B . buildMerge ( R3 , { UnmergeRayInvDir . getReg ( <NUM_LIT> ) , UnmergeRayInvDir . getReg ( <NUM_LIT> ) } ) ; Ops . push_back


<s> static Target The<ISA_LIT>beTarget ; return The<ISA_LIT>beTarget


<s> unsigned Align = MF . getDataLayout ( ) . getPrefTypeAlignment ( CPTy ) ; if ( Align == <NUM_LIT> ) Align = MF . getDataLayout ( ) . getTypeAllocSize


<s> return ( __m128d ) __builtin_ia32_cmpunordpd ( ( __v2df ) __A , (


<s> inline bool isImmPCRel ( uint64_t TSFlags ) { switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false


<s> auto TypeEntry = llvm :: make_unique < BTFTypeDerived > ( DTy , Tag ) ; TypeId = addType ( std :: move ( TypeEntry ) , DTy ) ; } else if ( Tag != dwarf :: DW_TAG_member ) { return ; } uint32_t TempTypeId =


<s> _mm_cvtsh_u64 ( __m128h __A ) { return ( long long ) __builtin_ia32_vcvtsh2usi64_round ( __A ,


<s> case SSA_NAME : case REAL_CST : case MEM_REF : case VIEW_CONVERT_EXPR : if ( TYPE_MODE ( TREE_TYPE ( * tp ) ) == SDmode ) return * tp ; break ; default : break ; } return


<s> struct riscv_arg_info info ; if ( arg . end_marker_p ( ) ) return NULL ; return riscv_get_arg_info ( & info , cum , arg . mode , arg .


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Address ) ) if ( C -> getSExtValue ( ) == <NUM_LIT> && AM . Segment . getNode ( ) == nullptr && ( Subtarget -> isTargetGlibc ( ) || Subtarget -> isTargetAndroid

( ) || Subtarget -> isTargetFuchsia ( ) ) ) switch ( N -> getPointerInfo ( ) . getAddrSpace ( ) ) {


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( new <ISA_LIT>ExecutionDepsFix ( ) ) ; if ( UseVZeroUpper ) addPass

( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ;


<s> case AMDGPU :: S_LOAD_DWORDX4_SGPR : { if ( NewOpcode == N -> getMachineOpcode ( ) ) { NewOpcode = AMDGPU :: BUFFER_LOAD_DWORDX4_ADDR64 ; } if ( fitsRegClass ( DAG , N -> getOperand ( <NUM_LIT> ) , AMDGPU :: SReg_64RegClassID ) ) { return N ; } ConstantSDNode * Offset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const SDValue Zero64 = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ptr ( DAG . getMachineNode ( AMDGPU :: S_MOV_B64 , DL , <STR_LIT> , Zero64 ) , <NUM_LIT> ) ; MachineSDNode * RSrc = wrapAddr64Rsrc ( DAG , DL , Ptr ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( SDValue ( RSrc , <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextI ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { nextI = std :: next ( I ) ; MachineOperand & Use = I . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( UseMI == MI ) continue ; if ( Use . isDebug ( ) ) UseMI -> getOperand ( <NUM_LIT> ) . setReg ( <NUM_LIT> ) ; } } MI -> eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> ; i < DeadPhis . size ( ) ; ++ i ) DeadPhis [ i ]


<s> return __builtin_loongson_pandn_ub ( s ,


<s> return EnableEmEH && ( areAllExceptionsAllowed ( ) || EHAllowlistSet . count ( std :: string (


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; } else if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } else { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( Subtarget . isABI_N32 ( ) ) { const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg


<s> continue ; } MachineInstr & MI1 = * SUa -> getInstr ( ) ; if ( ( TII -> isVMEM ( MI1 ) && TII -> isVMEM ( MI2 ) ) || ( TII -> isFLAT ( MI1 ) && TII -> isFLAT ( MI2 ) ) || ( TII -> isSMRD ( MI1 ) && TII -> isSMRD ( MI2 ) ) || ( TII -> isDS ( MI1 ) && TII -> isDS ( MI2 ) ) ) { SU . addPredBarrier ( SUa ) ; for ( const SDep & <ISA_LIT> : SU . Preds ) { if ( <ISA_LIT> . getSUnit ( ) != SUa ) SUa -> addPred ( SDep ( <ISA_LIT> . getSUnit ( ) , SDep :: Artificial ) ) ; } if ( & SU != & DAG -> ExitSU ) { for ( const SDep & <ISA_LIT> : SUa -> Succs ) { if ( <ISA_LIT> . getSUnit ( ) != & SU ) <ISA_LIT> . getSUnit ( ) -> addPred ( SDep ( & SU , SDep :: Artificial ) ) ; } } } SUa = &


<s> static uint32_t swapHalfWords ( uint32_t Value , bool IsLittleEndian ) { if ( IsLittleEndian ) { uint32_t Swapped = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; Swapped |= ( Value & <NUM_LIT> ) << <NUM_LIT> ; return Swapped ; } else return Value


<s> MCOperand segmentReg ; uint64_t pcrel = <NUM_LIT> ; if ( insn . eaBase == EA_BASE_sib || insn . eaBase == EA_BASE_sib64 ) { if ( insn . sibBase != SIB_BASE_NONE ) { switch ( insn . sibBase ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_BASE_ ## x : \ baseReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; ALL_SIB_BASES } } else { baseReg = MCOperand :: createReg ( <STR_LIT> ) ; } if ( insn . sibIndex != SIB_INDEX_NONE ) { switch ( insn . sibIndex ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_INDEX_ ## x : \ indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM REGS_ZMM } } else { if ( ! ForceSIB && ( insn . sibScale != <NUM_LIT> || ( insn . sibBase == SIB_BASE_NONE && insn . mode != MODE_64BIT ) || ( insn . sibBase != SIB_BASE_NONE && insn . sibBase != SIB_BASE_ESP && insn . sibBase != SIB_BASE_RSP && insn . sibBase != SIB_BASE_R12D && insn . sibBase != SIB_BASE_R12 ) ) ) { indexReg = MCOperand :: createReg ( insn . addressSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else indexReg = MCOperand :: createReg ( <STR_LIT> ) ; } scaleAmount = MCOperand :: createImm ( insn . sibScale ) ; } else { switch ( insn . eaBase ) { case EA_BASE_NONE : if ( insn . eaDisplacement == EA_DISP_NONE ) { debug ( <STR_LIT> ) ; return true ; } if ( insn . mode == MODE_64BIT ) { pcrel = insn . startLocation + insn . displacementOffset + insn . displacementSize ; tryAddingPcLoadReferenceComment ( insn . startLocation + insn . displacementOffset , insn . displacement + pcrel , Dis ) ; baseReg = MCOperand :: createReg ( insn . addressSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BX_SI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BX_DI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_SI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_DI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; default : indexReg = MCOperand :: createReg ( <STR_LIT> ) ; switch ( insn . eaBase


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget * Subtarget = & MF

. getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> if ( MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getShaderType ( ) != ShaderType :: PIXEL || ! shouldSkip ( & MBB , & MBB . getParent ( ) -> back ( ) ) ) return ; MachineBasicBlock :: iterator Insert = & MI ; ++ Insert ; BuildMI ( MBB , Insert , DL , TII -> get ( AMDGPU :: S_CBRANCH_EXECNZ )

) . addImm ( <NUM_LIT> ) . addReg ( AMDGPU :: EXEC ) ;


<s> return ( float32x4_t ) __builtin_neon_vreinterpretv4sfv2di (


<s> SmallVector < unsigned , <NUM_LIT> > SGPRIndexes ; for ( int I = NumDefs , NumOps = MI . getNumOperands ( ) ; I != NumOps ; ++ I ) { if ( ! MI . getOperand ( I ) . isReg ( ) ) continue ; if ( I == RsrcIdx || I == RsrcIdx + <NUM_LIT> ) SGPRIndexes . push_back (


<s> static std :: string computeDataLayout ( bool is64Bit ) { std :: string Ret = <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( is64Bit ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; } switch ( Opcode ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( offset ) ) ; if ( IsLoad && Rt == Rt2


<s> if ( is_arch ) fprintf ( f , <STR_LIT> , arch -> name ) ; else fprintf ( f , <STR_LIT> , mcu -> name , arch -> name , sp8 ? <NUM_LIT> : <NUM_LIT> , rcall ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , header ) ; if ( is_device ) fprintf ( f , <STR_LIT> , help_copy_paste ) ; if ( is_device ) { fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , mcu -> name ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , mcu -> name ) ; fprintf ( f , <STR_LIT> ) ; } int n_flash = <NUM_LIT> + ( mcu -> flash_size - <NUM_LIT> ) / <NUM_LIT> ; fprintf ( f , <STR_LIT> <STR_LIT> , n_flash ) ; fprintf ( f , <STR_LIT> , rmw ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , errata_skip ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , absdata ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , arch -> name ) ; fprintf ( f , <STR_LIT> , ASM_RELAX_SPEC ) ; fprintf ( f , <STR_LIT> , rmw ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , errata_skip ? <STR_LIT> : <STR_LIT> ) ; int wrap_k = mcu -> flash_size == <NUM_LIT> ? <NUM_LIT> : mcu -> flash_size == <NUM_LIT> ? <NUM_LIT> : mcu -> flash_size == <NUM_LIT> ? <NUM_LIT> : mcu -> flash_size == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; fprintf ( f , <STR_LIT> ) ; if ( wrap_k == <NUM_LIT> ) fprintf ( f , <STR_LIT> ) ; else if ( wrap_k > <NUM_LIT> ) fprintf ( f , <STR_LIT> , wrap_k ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , LINK_RELAX_SPEC ) ; fprintf ( f , <STR_LIT> , LINK_ARCH_SPEC ) ; if ( is_device ) { fprintf ( f , <STR_LIT> ) ; if ( mcu -> data_section_start != arch -> default_data_section_start ) fprintf ( f , <STR_LIT> , <NUM_LIT> + mcu -> data_section_start ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; if ( mcu -> text_section_start != <NUM_LIT> ) fprintf ( f , <STR_LIT> , <NUM_LIT> + mcu -> text_section_start ) ; fprintf ( f , <STR_LIT> ) ; } if ( is_device ) { fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , arch -> name ) ; fprintf ( f , <STR_LIT> , rcall_spec ) ; fprintf ( f , <STR_LIT> , sp8_spec ) ; fprintf ( f , <STR_LIT>


<s> printReturnValStr ( F , O ) ; O << * Mang -> getSymbol ( F ) << <STR_LIT> ; emitFunctionParamList ( F


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst ) ; else Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; return DAG . getNode ( <STR_LIT> ,


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { Triple TheTriple ( TT ) ; RM = TheTriple . isOSDarwin ( ) ? Reloc :: PIC_ : Reloc :: DynamicNoPIC ; } X -> InitMCCodeGenInfo ( RM , CM


<s> return ( ( __a & __b ) != __AARCH64_UINT64_C ( <NUM_LIT>


<s> virtual unsigned getFrameRegister ( const MachineFunction


<s> FunctionPass * llvm :: createCookieSetterPass ( ) { return new CookieSetter


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { return <STR_LIT>


<s> OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Weak ) ; OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Hidden ) ; OutStreamer -> EmitLabel ( Sym ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) , * STI ) ; MCSymbol * HandleMismatchSym = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( HandleMismatchSym


<s> if ( ( Mnemonic . equals_lower ( <STR_LIT> ) || Mnemonic . equals_lower ( <STR_LIT> ) || Mnemonic . equals_lower ( <STR_LIT> ) || Mnemonic . equals_lower ( <STR_LIT> ) || Mnemonic . equals_lower ( <STR_LIT> ) ) && ( Switch . equals_lower ( <STR_LIT> ) || Switch . equals_lower ( <STR_LIT> ) ) ) { auto Accumulator = <STR_LIT> ( Range . Start , Range . End ) ; TempOperand = Accumulator . get ( ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , std :: move ( Accumulator ) ) ; Result = true ; } else if ( Switch . equals_lower ( <STR_LIT> ) ) { auto Rhaz = <STR_LIT> ( <NUM_LIT> , Range . Start , Range . End ) ; TempOperand = Rhaz . get ( ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , std :: move ( Rhaz ) ) ; Result = true ; } else if ( Switch . equals_lower ( <STR_LIT> ) && ( Mnemonic . equals_lower ( <STR_LIT> ) || Mnemonic . equals_lower ( <STR_LIT> ) || Mnemonic . equals_lower ( <STR_LIT> ) ) ) { auto X2 = <STR_LIT> ( <ISA_LIT>II :: SW_X2_ARITHMETIC , Range . Start , Range . End ) ; TempOperand = X2 . get ( ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , std :: move ( X2 ) ) ; Result = true ; } else if ( ( ( Switch . equals_lower ( <STR_LIT> ) && ( SwitchValue & <ISA_LIT>II :: SW_MDG_TYPE_MASK ) == <ISA_LIT>II :: SW_MDG_TYPE_ALL ) || Switch . equals_lower ( <STR_LIT> ) ) && Mnemonic . equals_lower ( <STR_LIT> ) ) { auto MovDGAll = <STR_LIT> ( <ISA_LIT>II :: SW_MDG_TYPE_ALL , Range . Start , Range . End ) ; TempOperand = MovDGAll . get ( ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , std :: move ( MovDGAll ) ) ; } else if ( ( ( Switch . equals_lower ( <STR_LIT> ) && ( SwitchValue & <ISA_LIT>II :: SW_MDG_TYPE_MASK ) == <ISA_LIT>II :: SW_MDG_TYPE_PACK ) || Switch . equals_lower ( <STR_LIT> ) ) && Mnemonic . equals_lower ( <STR_LIT> ) ) { auto MovDGPack = <STR_LIT> ( <ISA_LIT>II :: SW_MDG_TYPE_PACK , Range . Start , Range . End ) ; TempOperand = MovDGPack . get ( ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , std :: move ( MovDGPack ) ) ; } else if ( Switch . equals_lower ( <STR_LIT> ) && ( SwitchValue & <ISA_LIT>II :: SW_MDG_TYPE_MASK ) == <ISA_LIT>II :: SW_MDG_TYPE_UNPACK && Mnemonic . equals_lower ( <STR_LIT> ) ) { auto MovDGUnpack = <STR_LIT> ( <ISA_LIT>II :: SW_MDG_TYPE_UNPACK , Range . Start , Range . End ) ; TempOperand = MovDGUnpack . get ( ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , std :: move ( MovDGUnpack ) ) ; } } if ( SpecialOperand &&


<s> Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && Alignment > Align ( <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } } else if ( Alignment == Align ( <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } else { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes , dl ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , dl , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } bool Use64BitRegs = Subtarget . isTarget64BitLP64 ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT AddrVT = Dst . getValueType (


<s> switch ( CM ) { default : break ; case CodeModel :: Default : case CodeModel :: JITDefault : CM = CodeModel :: Small ; break ; } X -> InitMCCodeGenInfo ( RM ,


<s> initialize<ISA_LIT>BoolRetToIntPass ( * PassRegistry :: getPassRegistry (


<s> bool hasNoSdstCMPX ( ) const { return HasNoSdstCMPX


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; return std :: make_pair ( Lo , Hi


<s> } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; switch ( form_int ) { case <NUM_LIT> : emit_insn ( gen_move_from_CR_ov_bit ( target , scratch ) ) ; return target ; case <NUM_LIT> : code = EQ ; break ; case <NUM_LIT> : code = LT ; break ; case <NUM_LIT> : code = GT ; break ; default : error ( <STR_LIT> ) ; return


<s> } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState ( isKill ) ) ; NewMIs . push_back ( MIB


<s> MaxLoadSize = <NUM_LIT> ; return true


<s> static inline unsigned char getBaseOpcodeFor (


<s> if ( a >= - ( SFtype ) ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) return ( SItype ) ( a + ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT> << ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - ( - ( ( SItype ) ( ( ( USItype ) <NUM_LIT>

<< ( ( <NUM_LIT> * <NUM_LIT> ) - <NUM_LIT> ) ) - <NUM_LIT> ) ) - <NUM_LIT> ) ;


<s> OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D1 ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D2 ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_piece ) ; EmitULEB128 ( <NUM_LIT>


<s> } unsigned ABIAlignment = getTargetData ( ) -> getABITypeAlignment ( ST -> getMemoryVT ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( ST -> getAlignment ( ) >= ABIAlignment ) { return SDValue ( ) ; } SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ST -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry


<s> if ( Bytes . size ( ) < <NUM_LIT> ) return Fail ; Size = <NUM_LIT> ; uint32_t Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return decodeInstruction ( DecoderTable32 , MI , Insn , Address , this


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo (


<s> xops [ <NUM_LIT> ] = stack_pointer_rtx ; xops [ <NUM_LIT> ] = reg ; xops [ <NUM_LIT> ] = const0_rtx ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg ; xops [ <NUM_LIT> ] = end ; output_asm_insn ( <STR_LIT> , xops


<s> } else if ( MO . isImm ( ) ) { if ( i < Desc . getNumOperands ( ) ) { assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ i ] ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << int ( Info . OperandType ) << <STR_LIT> ) ; if ( Info . OperandType == <STR_LIT> ) { encodeSLEB128 ( int32_t ( MO . getImm ( ) ) , OS ) ; } else if ( Info . OperandType == <STR_LIT> ) { encodeULEB128 ( uint32_t ( MO . getImm ( ) ) , OS ) ; } else if ( Info . OperandType == <STR_LIT> ) { encodeSLEB128 ( int64_t ( MO . getImm ( ) ) , OS ) ; } else if ( Info . OperandType == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( Info . OperandType == <STR_LIT> ) { OS << uint8_t ( MO . getImm ( ) ) ; } else { encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else { assert ( Desc . TSFlags == ( <STR_LIT> | <STR_LIT> ) ) ; encodeULEB128 ( uint64_t ( MO . getImm ( ) ) , OS ) ; } } else if ( MO . isFPImm ( ) ) { assert ( i < Desc . getNumOperands ( ) && <STR_LIT> ) ; assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ i ] ; if ( Info . OperandType == <STR_LIT> ) { float f = float ( MO . getFPImm ( ) ) ; <STR_LIT> :: write < float > ( OS , f , <STR_LIT> ) ; } else { assert ( Info . OperandType == <STR_LIT> ) ; double d = MO . getFPImm ( ) ; <STR_LIT> :: write < double > ( OS , d , <STR_LIT> ) ; } } else if ( MO . isExpr ( ) ) { const MCOperandInfo & Info = Desc . OpInfo [ i ] ; llvm :: MCFixupKind FixupKind ; size_t PaddedSize = <NUM_LIT> ; if ( Info . OperandType == <STR_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else if ( Info . OperandType == <STR_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; PaddedSize = <NUM_LIT> ; } else if ( Info . OperandType == <STR_LIT> || Info . OperandType == <STR_LIT> || Info . OperandType == <STR_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else if ( Info . OperandType == <STR_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Fixups . push_back ( MCFixup :: create ( OS . tell ( ) - Start , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; ++


<s> AU . addPreserved < DominatorTreeWrapperPass >


<s> bool isEnvironmentMusl ( ) const { return TargetTriple . getEnvironment ( ) ==


<s> const LLT S16 = LLT :: scalar ( <NUM_LIT> ) ; LLT StoreVT = MRI . getType ( Reg ) ; if ( ! StoreVT . isVector ( ) || StoreVT . getElementType ( ) != S16 ) return Reg ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; SmallVector < Register , <NUM_LIT> > WideRegs


<s> if ( ! Ty . isVector ( ) ) return false ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto UShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg ,


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn (

<STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ;


<s> void arm_pr_long_calls_off ( struct cpp_reader * pfile ATTRIBUTE_UNUSED


<s> if ( MRI . getRegClass ( NewReg ) != MRI . getRegClass ( OldReg ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; Changed |= MaybeRewriteToDrop ( OldReg , NewReg , MO , MFI , MRI ) ; } } } break ; } case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI ,


<s> break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; } } return true


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned CC = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( IsIntegerCC ( CC ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( CC ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm (


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI ->

getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ;


<s> void <ISA_LIT>WinCOFFStreamer :: FinishImpl ( ) { EmitFrames ( nullptr


<s> bool IsTailPredicationLegal ( ) const { return ! Revert && FoundAllComponents ( ) && VCTP && ! CannotTailPredicate


<s> ExceptionsType = ExceptionHandling :: None ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; PrivateGlobalPrefix =


<s> assert ( ES -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetExternalSymbol

( ES -> getSymbol ( ) , VT , <NUM_LIT> ) ) ;


<s> int64_t <ISA_LIT>GNULDBackend :: maxFwdBranchOffset ( ) const { if ( m_pAttrData -> usingThumb2 ( ) ) { return THM2_MAX_FWD_BRANCH_OFFSET ; } else { return THM_MAX_FWD_BRANCH_OFFSET


<s> return ( int64x2_t ) __builtin_aarch64_ashlv2di (


<s> MachineModuleInfo * MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; assert ( MMI ) ; DwarfWriter * DW = getAnalysisIfAvailable < DwarfWriter > ( ) ; assert ( DW && <STR_LIT> ) ; DW -> BeginModule ( & M , MMI , O , this , TAI ) ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { I -> setSection ( TAI -> SectionForGlobal ( I ) -> getName ( ) ) ; } EmitFunctionDecls ( M ) ; EmitUndefinedVars ( M ) ; EmitDefinedVars ( M ) ; EmitIData ( M ) ; EmitUData ( M


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return &


<s> switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; Value = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Mask = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( RegCtx . AddressReg ( <STR_LIT> ) ) ) ; } const std :: string & Fn = FuncName ( AccessSize , IsWrite ) ; MCSymbol * FnSym = Ctx . getOrCreateSymbol ( StringRef ( Fn ) ) ; const MCSymbolRefExpr * FnExpr = MCSymbolRefExpr :: create ( FnSym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr (


<s> <ISA_LIT>AsmBackend ( const Target & T , StringRef CPU ) : MCAsmBackend ( ) , CPU ( CPU ) , MaxNopLength ( ( CPU == <STR_LIT> || CPU == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) { HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU

!= <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } assert ( RI . hasVGPRs (


<s> if ( ! sparc_tls_symbol ) sparc_tls_symbol = gen_rtx_SYMBOL_REF ( Pmode ,


<s> std :: string TT = M . getTargetTriple ( ) ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( M . getEndianness ( ) == Module :: BigEndian && M . getPointerSize ( ) == Module :: Pointer64 ) return <NUM_LIT> ; else if ( M . getEndianness ( ) != Module :: AnyEndianness || M . getPointerSize ( ) !=

Module :: AnyPointerSize ) return <NUM_LIT> ;


<s> auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { if ( isa < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { return getExprOpValue ( MO . getExpr ( ) , Fixups


<s> SDValue <ISA_LIT>TargetLowering :: LowerSampleIntrinsic ( unsigned Opcode , const SDValue & Op , SelectionDAG & DAG ) const { return DAG . getNode ( Opcode , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand

( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return *


<s> Register ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getSimpleValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcVT == <STR_LIT> ) { ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Register Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ; } else if ( DstVT == <STR_LIT> ) { Register Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , Result32 , true , <STR_LIT> ) ; } else if (


<s> } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { return ; } switch ( BasicInstType ) { case <STR_LIT> : { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstSel , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstUnused , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , <NUM_LIT> ) ; break ; } case <STR_LIT> : { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand


<s> } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; bool UseOpcodeThatLoads = Indirect && ! STI . isThumb ( ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . MOV_ga_pcrel ) : ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . LDRLIT_ga_pcrel ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ; if ( Indirect ) { if ( ! UseOpcodeThatLoads ) { auto ResultReg = MIB . getReg ( <NUM_LIT> ) ; auto AddressReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( AddressReg ) ; auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto MIBLoad = BuildMI ( MBB , InsertBefore , MIB -> getDebugLoc ( ) , TII . get ( Opcodes . LOAD32 ) ) . addDef ( ResultReg ) . addReg ( AddressReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; addGOTMemOperand ( MIBLoad ) ; if ( ! constrainSelectedInstRegOperands ( * MIBLoad , TII , TRI , RBI ) ) return false ; } else { addGOTMemOperand ( MIB ) ; } } return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } bool isReadOnly = STI . getTargetLowering ( ) -> isReadOnly ( GV ) ; if ( STI . isROPI ( ) && isReadOnly ) { unsigned Opc = UseMovt ? Opcodes . MOV_ga_pcrel : Opcodes . LDRLIT_ga_pcrel ; MIB -> setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Medium ) , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> static int aarch64_sched_issue_rate (


<s> if ( GET_CODE ( x ) == POST_MODIFY ) return ( RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) ; } if ( GET_CODE ( x ) != PLUS ) return false ; base = XEXP ( x , <NUM_LIT> ) ; index = XEXP ( x , <NUM_LIT> ) ; if ( ! REG_P ( base ) ) return false ; if ( REG_P ( index ) ) { if ( ! TARGET_AM33 ) return false ; return ( REGNO_GENERAL_P ( REGNO ( base ) , strict ) && REGNO_GENERAL_P ( REGNO ( index ) , strict ) ) ; } if ( ! REGNO_STRICT_OK_FOR_BASE_P ( REGNO ( base ) , strict ) ) return false ; if ( CONST_INT_P ( index ) ) return IN_RANGE ( INTVAL ( index ) , - <NUM_LIT> - <NUM_LIT> , <NUM_LIT> ) ; if ( CONSTANT_ADDRESS_P ( index ) ) return ! flag_pic || mn10300_legitimate_pic_operand_p ( index ) ; return false


<s> for ( auto X : reverse ( Stack ) ) { if ( X . first == MBB )


<s> SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasSSE2 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasInt256 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasBWI ( ) ) ) { if ( matchShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { if ( matchShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) { SrcVT = DstVT = MaskVT ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) SrcVT = DstVT = ( <NUM_LIT> == EltSizeInBits ? <STR_LIT> : <STR_LIT> ) ; return true ; } } if ( ( EltSizeInBits % V1 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> && ( EltSizeInBits % V2 . getScalarValueSizeInBits ( ) ) == <NUM_LIT> ) { bool IsBlend = true ; unsigned NumV1Elts = V1 . getValueType ( ) . getVectorNumElements ( ) ; unsigned NumV2Elts = V2 . getValueType ( ) . getVectorNumElements ( ) ; unsigned Scale1 = NumV1Elts / NumMaskElts ; unsigned Scale2 = NumV2Elts / NumMaskElts ; APInt DemandedZeroV1 = APInt :: getNullValue ( NumV1Elts ) ; APInt DemandedZeroV2 = APInt :: getNullValue ( NumV2Elts ) ; for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; if ( M == SM_SentinelZero ) { DemandedZeroV1 . setBits ( i * Scale1 , ( i + <NUM_LIT> ) * Scale1 ) ; DemandedZeroV2 . setBits ( i * Scale2 , ( i + <NUM_LIT> ) * Scale2 ) ; continue ; } if ( M == ( int ) i ) { DemandedZeroV2 . setBits ( i * Scale2 , ( i + <NUM_LIT> ) * Scale2 ) ; continue ; } if ( M == ( int ) ( i + NumMaskElts ) ) { DemandedZeroV1 . setBits ( i * Scale1 , ( i + <NUM_LIT> ) *


<s> const MCExpr * Disp = MCConstantExpr :: create ( ImmDisp , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , ImmDispToken . getEndLoc ( ) , Size ) ; } } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Start , ImmDisp , Size ) ; const MCExpr * Val ; SMLoc End ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; return <STR_LIT> ( getPointerWidth ( ) , Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier


<s> Val = - Val ; } } if ( <STR_LIT> ( AsmParser -> getMII ( ) -> get ( Inst . getOpcode ( ) ) , Inst . getNumOperands ( ) ) ) { addLiteralImmOperand ( Inst , Val ) ; } else { Inst . addOperand ( MCOperand :: createImm (


<s> int short_memory_operand ( rtx x , enum machine_mode mode ) { if ( ! memory_operand ( x , mode )


<s> if ( CONST_INT_P ( src ) ) { HOST_WIDE_INT val = INTVAL ( src ) ; emit_set_insn ( dest , GEN_INT ( val & <NUM_LIT> ) ) ; if ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) { emit_set_insn ( gen_rtx_ZERO_EXTRACT ( SImode , dest , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , GEN_INT ( ( val >> <NUM_LIT> ) & <NUM_LIT> ) ) ; insn = get_last_insn ( ) ; set_unique_reg_note ( insn , REG_EQUAL , copy_rtx ( src ) ) ; } return ; } emit_set_insn ( dest , gen_rtx_HIGH ( SImode , src ) ) ; emit_set_insn ( dest , gen_rtx_LO_SUM ( SImode ,


<s> rtx sh_gen_truncate ( machine_mode mode , rtx x , int need_sign_ext ) { enum rtx_code code = TRUNCATE ; if ( GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) { rtx inner = XEXP ( x , <NUM_LIT> ) ; machine_mode inner_mode = GET_MODE ( inner ) ; if ( inner_mode == mode ) return inner ; else if ( GET_MODE_SIZE ( inner_mode ) >= GET_MODE_SIZE


<s> for ( unsigned I = <NUM_LIT> ; I < NumAttr ; ++ I ) { F . removeFnAttr ( AttributeNames [ I ] ) ; if ( NewAttrs [ I ] ) { LLVM_DEBUG ( dbgs ( ) << '\t' << NewAttrs [ I ] -> getAsString ( ) <<


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , IsModuleEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF

. getTarget ( ) . Options . NoSignedZerosFPMath ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> )


<s> bool <ISA_LIT>Operand :: isSMEMOffset ( )


<s> mode = mode_for_size ( GET_MODE_UNIT_BITSIZE ( mode ) , MODE_INT , <NUM_LIT> ) ; for ( i = bytes ; i < <NUM_LIT> ; i += bytes ) for ( j = <NUM_LIT> ; j < bytes ; j ++ ) if ( arr [ j ] != arr [ i + j ] ) return <NUM_LIT> ; val = arr [ <NUM_LIT> ] ; for ( j = <NUM_LIT> ; j < bytes ; j ++ ) val = ( val << <NUM_LIT> ) | arr [ j ] ; val = trunc_int_for_mode ( val , mode ) ; return val >= low &&


<s> if ( NumElts == <NUM_LIT> || ! isPowerOf2_32 ( NumElts ) ) return SDValue ( ) ; SDLoc dl ( N ) ; if ( NumElts < <NUM_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstantFP ( <NUM_LIT> , dl , SrcVT ) ) ; EVT CvtVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , std :: max ( <NUM_LIT> , NumElts ) ) ; SDValue Cvt = DAG . getNode ( <STR_LIT> , dl , CvtVT , Src , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT>


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString


<s> if ( ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) || ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) ) return false ; if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ; return KnownBits -> signBitIsZero ( Base . getReg


<s> MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( Is64Bit ) ; return createWinCOFFObjectWriter ( MOTW ,


<s> void msp430_expand_eh_return ( rtx eh_handler ) { rtx ap , sa , ra , tmp ; ap = arg_pointer_rtx ; sa = msp430_eh_return_stackadj_rtx ( ) ; ra = eh_handler ; tmp = ap ; tmp = gen_rtx_PLUS ( Pmode , ap , sa ) ; tmp = plus_constant ( Pmode , tmp , TARGET_LARGE ? - <NUM_LIT> : - <NUM_LIT> ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( tmp , ra


<s> unsigned StoreSize = getStoreSizeInBytes ( SI ) ; if ( StoreSize != unsigned ( std :: abs ( Stride ) ) ) return false ; LoadInst * LI = dyn_cast < LoadInst > ( SI -> getValueOperand ( ) ) ; if ( ! LI || ! LI -> isSimple ( ) ) return false ; Value * LoadPtr = LI -> getPointerOperand ( ) ; auto * LoadEv = dyn_cast < SCEVAddRecExpr > ( SE -> getSCEV ( LoadPtr ) ) ; if ( ! LoadEv || LoadEv -> getLoop ( ) != CurLoop || ! LoadEv -> isAffine ( ) ) return false ; if ( StoreEv -> getOperand ( <NUM_LIT> ) != LoadEv -> getOperand ( <NUM_LIT>


<s> LastMI = <NUM_LIT> ; FpMLxStalls = <NUM_LIT> ; ScoreboardHazardRecognizer :: Reset ( )


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , StackSlot } ; SDValue Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT>

) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection


<s> bool <ISA_LIT>PacketizerList :: hasDualStoreDependence ( const MachineInstr & I , const MachineInstr & J ) { bool SysI = isSystemInstr ( I ) , SysJ = isSystemInstr ( J ) ; bool StoreI = I . mayStore ( ) , StoreJ = J . mayStore ( ) ; if ( ( SysI && StoreJ ) || ( SysJ && StoreI ) ) return true ; if ( StoreI && StoreJ ) { if ( HII -> isNewValueInst ( J ) || HII -> isMemOp ( J ) || HII -> isMemOp ( I ) ) return true ; } else { bool MopStI = HII -> isMemOp ( I ) || StoreI ; bool MopStJ = HII -> isMemOp ( J ) || StoreJ ; if ( MopStI && MopStJ ) return true ; } return ( StoreJ && HII -> isDeallocRet ( I ) ) || ( StoreI && HII -> isDeallocRet


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { return <NUM_LIT>


<s> static rtx ft32_function_value ( const_tree valtype , const_tree fntype_or_decl ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( TYPE_MODE ( valtype )


<s> else if ( match_type == last_match_type ) num_matches ++ ; } if ( last_match_type == INT_MAX ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } else if ( num_matches > <NUM_LIT> ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( ! TARGET_VXE && bflags_overloaded_builtin_var [ last_match_index ] & B_VXE ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( bflags_overloaded_builtin_var [ last_match_index ] & B_DEP ) warning_at ( loc , <NUM_LIT> , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; if ( bt_for_overloaded_builtin_var [ last_match_index ] == S390_BUILTIN_MAX ) target_builtin_decl = ob_fndecl ; else target_builtin_decl = s390_builtin_decls [ bt_for_overloaded_builtin_var [ last_match_index ] ] ; all_op_flags = opflags_overloaded_builtin_var [ last_match_index ] ; return_type = s390_builtin_types [ s390_builtin_ov_types [ last_match_fntype_index ] [ <NUM_LIT> ] ] ; for ( i = <NUM_LIT> ; i < ob_args_num ; i ++ ) { unsigned int op_flags = all_op_flags & ( ( <NUM_LIT> << O_SHIFT ) - <NUM_LIT> ) ; tree arg = ( * arglist ) [ i ] ; tree type = s390_builtin_types [ s390_builtin_ov_types [ last_match_fntype_index ] [ i + <NUM_LIT> ] ] ; all_op_flags = all_op_flags >> O_SHIFT ; if ( op_flags == O_ELEM ) { int n_elem = s390_vec_n_elem ( target_builtin_decl ) ; gcc_assert ( n_elem > <NUM_LIT> ) ; gcc_assert ( type == integer_type_node ) ; ( * arglist ) [ i ] = build2 ( BIT_AND_EXPR , integer_type_node , fold_convert ( integer_type_node , arg ) , build_int_cst ( NULL_TREE , n_elem - <NUM_LIT> ) ) ; } if ( TREE_CODE ( arg ) != INTEGER_CST || ! O_IMM_P ( op_flags ) ) continue ; if ( ( TYPE_UNSIGNED ( type ) && ! int_fits_type_p ( arg , c_common_unsigned_type ( type ) ) ) || ( ! TYPE_UNSIGNED ( type ) && ! int_fits_type_p ( arg , c_common_signed_type ( type ) ) ) ) { error ( <STR_LIT> <STR_LIT> , i + <NUM_LIT> , target_builtin_decl ) ; return


<s> Op1 = DAG . getNode ( Extend , DL , <STR_LIT> , Op1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X


<s> int64_t Size ; if ( parseImmExpr ( Size


<s> case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : Takes12BitImm = true ; break ; case Instruction :: Sub : case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : Takes12BitImm = true ; ImmArgIdx = <NUM_LIT> ; break ; default : break ; } if ( Takes12BitImm ) { if ( Instruction :: isCommutative ( Opcode ) ||


<s> bool GCNPassConfig :: addPreRewrite ( ) { if ( EnableRegReassign ) addPass ( &


<s> switch ( <STR_LIT> ( Imm ) ) { case <STR_LIT> :: Void : break ; case <STR_LIT> :: I32 : O << <STR_LIT> ; break ; case <STR_LIT> :: I64 : O << <STR_LIT> ; break ; case <STR_LIT> :: F32 : O << <STR_LIT> ; break ; case <STR_LIT> :: F64 : O << <STR_LIT> ; break ; case <STR_LIT> :: I8x16 : O << <STR_LIT> ; break ; case <STR_LIT> :: I16x8 : O << <STR_LIT> ; break ; case <STR_LIT> :: I32x4 : O << <STR_LIT> ; break ; case <STR_LIT> :: F32x4 : O <<


<s> default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == VAR_DECL && ( TREE_STATIC ( decl ) || DECL_EXTERNAL ( decl )

) ) v850_encode_data_area ( decl , XEXP ( rtl , <NUM_LIT> ) ) ;


<s> } PhiRegisters . insert ( DstReg ) ; MachineBasicBlock * PostDomBound = & MBB ; for ( MachineInstr & Use : MRI -> use_instructions ( DstReg ) ) { PostDomBound = PDT -> findNearestCommonDominator ( PostDomBound , Use . getParent ( ) ) ; } unsigned FoundLoopLevel = LF . findLoop ( PostDomBound ) ; SSAUpdater . Initialize ( DstReg ) ; if ( FoundLoopLevel ) { LF . addLoopEntries ( FoundLoopLevel , SSAUpdater , IncomingBlocks ) ; for ( unsigned i = <NUM_LIT> ; i < IncomingRegs . size ( ) ; ++ i ) { IncomingUpdated . push_back ( createLaneMaskReg ( * MF ) ) ; SSAUpdater . AddAvailableValue ( IncomingBlocks [ i ] , IncomingUpdated . back ( ) ) ; } for ( unsigned i = <NUM_LIT> ; i < IncomingRegs . size ( ) ; ++ i ) { MachineBasicBlock & IMBB = * IncomingBlocks [ i ] ; buildMergeLaneMasks ( IMBB , getSaluInsertionAtEnd ( IMBB ) , { } , IncomingUpdated [ i ] , SSAUpdater . GetValueInMiddleOfBlock ( & IMBB ) , IncomingRegs [ i ] ) ; } } else { PIA . analyze ( MBB , IncomingBlocks ) ; for ( MachineBasicBlock * MBB : PIA . predecessors ( ) ) SSAUpdater . AddAvailableValue ( MBB , insertUndefLaneMask ( * MBB ) ) ; for ( unsigned i = <NUM_LIT> ; i < IncomingRegs . size ( ) ; ++ i ) { MachineBasicBlock & IMBB = * IncomingBlocks [ i ] ; if ( PIA . isSource ( IMBB ) ) { IncomingUpdated . push_back ( <NUM_LIT> ) ; SSAUpdater . AddAvailableValue ( & IMBB , IncomingRegs [ i ] ) ; } else { IncomingUpdated . push_back ( createLaneMaskReg ( * MF ) ) ; SSAUpdater . AddAvailableValue ( & IMBB , IncomingUpdated . back ( ) ) ; } } for ( unsigned i = <NUM_LIT> ; i < IncomingRegs . size ( ) ; ++ i ) { if ( ! IncomingUpdated [ i ] ) continue ; MachineBasicBlock & IMBB = * IncomingBlocks [ i ] ; buildMergeLaneMasks ( IMBB , getSaluInsertionAtEnd ( IMBB ) , { } , IncomingUpdated [ i ] , SSAUpdater . GetValueInMiddleOfBlock ( & IMBB ) , IncomingRegs [ i ] ) ; } } unsigned NewReg = SSAUpdater . GetValueInMiddleOfBlock ( & MBB ) ; if ( NewReg != DstReg ) { MRI -> replaceRegWith ( NewReg , DstReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; DeadPhis . push_back ( & MI ) ; } IncomingBlocks . clear ( ) ; IncomingRegs . clear ( ) ; IncomingUpdated . clear ( ) ; } for ( MachineInstr * MI : DeadPhis ) MI -> eraseFromParent (


<s> hint = emit_insn_before ( gen_hbr ( branch_label , target ) , before ) ; recog_memoized ( hint ) ; INSN_LOCATION ( hint ) = INSN_LOCATION ( branch ) ; HINTED_P ( branch ) = <NUM_LIT> ; if ( GET_CODE ( target ) == LABEL_REF ) HINTED_P ( XEXP ( target , <NUM_LIT> ) ) = <NUM_LIT> ; else if ( tablejump_p ( branch , <NUM_LIT> , & table ) ) { rtvec vec ; int j ; if ( GET_CODE ( PATTERN ( table ) ) == ADDR_VEC ) vec = XVEC ( PATTERN ( table ) , <NUM_LIT> ) ; else vec = XVEC ( PATTERN ( table ) , <NUM_LIT> ) ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) HINTED_P ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) = <NUM_LIT> ; } if ( distance >= <NUM_LIT> ) { insn = emit_insn_before ( gen_blockage ( ) , hint ) ; recog_memoized ( insn ) ; INSN_LOCATION ( insn ) = INSN_LOCATION ( hint ) ; } else if ( distance <= <NUM_LIT> * <NUM_LIT>


<s> switch ( Kind ) { default : break ; case MCK__35_0 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__35_8 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__35_16 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK_ModImm : if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return Match_rGPR ; case MCK_GPRPair : if ( Op . isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) .

contains ( Op . getReg ( ) ) ) return Match_Success ;


<s> else if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return ParseDirectiveTLSDescCall ( DirectiveID


<s> inline bool is_st_l ( const MCInstrDesc & MCInstD ) { if ( ! isStoreInst ( MCInstD ) ) return false ; switch ( getSlotOpCode ( MCInstD ) ) { case ST_L : return true ; } return false


<s> return <STR_LIT> ( MCII . get ( MI . getOpcode ( ) ) .


<s> mOperands . resize ( ( unsigned ) ( idx + <NUM_LIT> ) ) ; mOperands [ ( unsigned ) idx ]


<s> print ( dbgs ( ) , ValueMap , <STR_LIT> ) ; dbgs ( ) << '\n' ; print ( dbgs ( ) , MetadataMap , <STR_LIT> ) ; dbgs ( ) <<


<s> static void avr_register_passes ( void ) { register_pass ( new avr_pass_recompute_notes ( g , <STR_LIT> ) , PASS_POS_INSERT_BEFORE , <STR_LIT>


<s> StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Chain = Store -> getChain ( ) ; if ( ( Store -> getAddressSpace ( ) == <STR_LIT> || Store -> getAddressSpace ( ) == <STR_LIT> ) && Store -> getValue ( ) . getValueType ( ) . isVector ( ) ) { return SplitVectorStore ( Op , DAG ) ; } EVT MemVT = Store -> getMemoryVT ( ) ; if ( Store -> getAddressSpace ( ) == <STR_LIT> && MemVT . bitsLT ( <STR_LIT> ) ) { unsigned Mask = <NUM_LIT> ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant


<s> int s0 = mep_section_tag ( operands [ <NUM_LIT> ] ) == 'f' ; int s1 = mep_section_tag ( operands [ <NUM_LIT> ] ) == 'f' ; int c0 = mep_nongeneral_reg ( operands [ <NUM_LIT> ] ) ; int c1 = mep_nongeneral_reg ( operands [ <NUM_LIT> ] ) ; int which = ( s0 ? <NUM_LIT> : <NUM_LIT> ) + ( c0 ? <NUM_LIT> : <NUM_LIT> ) + ( s1 ? <NUM_LIT> : <NUM_LIT> ) + ( c1 ? <NUM_LIT> : <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> , mode_name [ mode ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; switch ( which ) { case <NUM_LIT> : case <NUM_LIT> : emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT>


<s> void Emitter < CodeEmitter > :: emitMachineBasicBlock ( MachineBasicBlock * BB , unsigned


<s> static const char * GetArchDefaultCPUName ( unsigned ID ) { switch ( ID )


<s> auto ZExt = cast < ZExtInst > ( V ) ; if ( ZExt -> getDestTy ( ) != ExtTy ) continue ; Value * Src = ZExt -> getOperand ( <NUM_LIT> ) ; if ( ZExt -> getSrcTy ( ) == ZExt -> getDestTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ZExt << <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Src ) ; continue ; } if ( NewInsts . count ( Src ) && isa < TruncInst > ( Src ) && Src -> getType ( ) == OrigTy ) { auto * Trunc = cast < TruncInst > ( Src ) ; assert ( Trunc -> getOperand ( <NUM_LIT> ) -> getType ( ) == ExtTy && <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Trunc -> getOperand ( <NUM_LIT> ) ) ; } } for ( auto * I : InstsToRemove ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; I -> dropAllReferences ( ) ; I -> eraseFromParent ( ) ; } InstsToRemove . clear ( ) ; NewInsts . clear ( ) ; TruncTysMap . clear ( ) ; Promoted . clear ( ) ; SafeToPromote -> clear (


<s> return aarch64_sve_inc_dec_immediate_p ( x , NULL


<s> if ( ! VT . isVector ( ) ) return ! isa < ConstantSDNode > ( Y ) && hasAndNotCompare ( Y ) ; if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) <


<s> for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) Tmp . push_back ( ConstantInt :: get ( Int8Ty , <NUM_LIT> << j ) ) ; } Constant * CV = ConstantVector :: get ( Tmp ) ; unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , ByteTy , Align ) , DAG ) ; SDValue Bytes = DAG . getLoad ( ByteTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; SDValue Sel = DAG . getSelect ( dl , VecTy , VecQ , DAG . getBitcast ( VecTy , Bytes ) , getZero ( dl , VecTy , DAG ) ) ; SDValue All1 = DAG . getSplatBuildVector ( <STR_LIT> , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Vrmpy = getInstr ( <STR_LIT> , dl , ByteTy , { Sel , All1 } , DAG ) ; SDValue Rot = getInstr ( <STR_LIT> , dl , ByteTy , { Vrmpy , Vrmpy , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue Vor = DAG . getNode ( <STR_LIT> , dl , ByteTy , { Vrmpy , Rot } ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> ; i != HwLen ; ++ i ) Mask . push_back ( ( <NUM_LIT> * i ) % HwLen + i / ( HwLen / <NUM_LIT> ) ) ; SDValue Collect = DAG . getVectorShuffle ( ByteTy , dl , Vor


<s> drap_ok = drap_ok && drap_align >= align_reqested ; sp_ok = sp_ok && sp_align >= align_reqested ; } if ( m -> use_fast_prologue_epilogue ) { if ( hfp_ok ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( drap_ok ) { base_reg = crtl -> drap_reg ; base_offset = <NUM_LIT> - cfa_offset ; } else if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = <NUM_LIT> , tlen ; if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( drap_ok ) { toffset = <NUM_LIT> - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( hfp_ok ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; len =


<s> return new <ISA_LIT>ExpandAtomicPseudo


<s> for ( MachineBasicBlock :: reverse_iterator I ( slot ) ; I != MBB . rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; MachineBasicBlock :: iterator FI ( llvm :: next ( I ) . base ( ) ) ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isLabel ( ) || FI == LastFiller || I -> getDesc ( ) . isPseudo ( ) ) break ; if ( delayHasHazard ( FI , sawLoad , sawStore , RegDefs , RegUses ) ) { insertDefsUses ( FI , RegDefs ,


<s> void <ISA_LIT>InstPrinter :: printExpSrc0 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseGPRSeqPair ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned FirstReg ; OperandMatchResultTy Res = tryParseScalarRegister ( FirstReg ) ; if ( Res != MatchOperand_Success ) return MatchOperand_ParseFail ; const MCRegisterClass & WRegClass = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; const MCRegisterClass & XRegClass = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; bool isXReg = XRegClass . contains ( FirstReg ) , isWReg = WRegClass . contains ( FirstReg ) ; if ( ! isXReg &&


<s> const bool InvalidPacket = ( ( Summary . load0 > <NUM_LIT> || Summary . store0 > <NUM_LIT> || ! ValidHVXMem ) || ( Summary . duplex > <NUM_LIT> || ( Summary . duplex && Summary . memory ) ) ) ; return !


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) )


<s> Value * Cond = Term -> getCondition ( ) ; Term -> setCondition ( BoolTrue ) ; Value * Arg = handleLoopCondition ( Cond , Broken , L , Term , LoopPhiConditions ) ; for ( BasicBlock * Pred : predecessors ( Target ) ) Broken -> addIncoming ( Pred == BB ? Arg : Int64Zero , Pred ) ; Term -> setCondition ( CallInst :: Create ( Loop , Arg


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , InFlag ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> , TPR . getValue ( <NUM_LIT> ) ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) ; } InVals . push_back ( RetVal . getValue ( <NUM_LIT> ) ) ; Chain = RetVal . getValue (


<s> OutStreamer -> EmitRawText ( <STR_LIT>


<s> return ( ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align ( mode , type ) ? DOUBLEWORD_ALIGNMENT :


<s> & <STR_LIT> ) ; unsigned LOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned CSOpcode = BitSize <= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; LOpcode = TII -> getOpcodeForOffset ( LOpcode , Disp ) ; CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize < <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( uint32_t ( ~ <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ) ; else if ( BitSize == <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( ~ uint32_t ( <NUM_LIT> ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 )


<s> const SDLoc & dl ( Op ) ; StoreSDNode * SN = cast < StoreSDNode > ( Op . getNode ( ) ) ; SDValue Val = SN -> getValue ( ) ; MVT Ty = ty ( Val ) ; bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; SDValue NS = DAG . getStore ( SN -> getChain ( ) , dl , TC , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ; if ( SN -> isIndexed ( ) ) { NS = DAG . getIndexedStore ( NS , dl , SN -> getBasePtr ( ) , SN -> getOffset ( ) , SN -> getAddressingMode ( ) ) ; } SN = cast < StoreSDNode > ( NS . getNode ( ) ) ; } unsigned ClaimAlign = SN -> getAlignment ( ) ; SDValue Ptr = SN -> getBasePtr ( ) ; validateConstPtrAlignment ( Ptr ,


<s> TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( getMalkrzFromFiMalkrz ( I -> getOpcode ( ) ) == <STR_LIT> && <STR_LIT> ) ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( I -> getOpcode ( ) ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; i ++ ) { Cond . push_back ( I -> getOperand


<s> unsigned Op = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Opc ; Type * OpTy = I -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy -> isFloatTy ( ) ) Opc = <STR_LIT> ; else if ( OpTy -> isDoubleTy ( ) )


<s> AsmPrinter :: printPICJumpTableSetLabel ( uid , uid2 , MBB


<s> MCContext & Ctx = getContext ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Major , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Minor


<s> val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; switch ( code ) { case IOR : case XOR : mask = NULL ; break ; case AND : x = gen_rtx_NOT ( SImode , mask ) ; x = gen_rtx_IOR ( SImode , x , val ) ; emit_insn ( gen_rtx_SET ( val , x ) ) ; mask = NULL ; break ; case NOT : case PLUS : case MINUS : break ; default : gcc_unreachable ( ) ; } before = gen_reg_rtx ( SImode ) ; if ( after ) after = gen_reg_rtx ( SImode ) ; store_mode = mode = SImode ; } } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = expand_simple_binop ( mode , AND , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_simple_unop ( mode , NOT , x , after , <NUM_LIT> ) ; } else { after = expand_simple_binop ( mode , code , before , val , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = after ; if ( mask ) { x = expand_simple_binop ( SImode , AND , after , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = rs6000_mask_atomic_subword ( before , x , mask ) ; } else if ( store_mode != mode ) x = convert_modes ( store_mode , mode , x , <NUM_LIT> ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( store_mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ; rs6000_post_atomic_barrier ( model ) ; if ( shift ) { if ( orig_before ) rs6000_finish_atomic_subword ( orig_before , before


<s> bool <ISA_LIT>SEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func -> hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> )

. setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> SubIdx = <STR_LIT> ; } unsigned Dst = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Dst != Src && <STR_LIT> ) ; auto TRI = getRegisterInfo ( ) ; auto RCDst = TRI . getMaximalPhysRegClass ( Dst , MVTDst ) ; auto RCSrc = TRI . getMaximalPhysRegClass ( Src , MVTSrc ) ; assert ( RCDst && RCSrc && <STR_LIT> ) ; assert ( RCDst != RCSrc &&


<s> default : llvm_unreachable ( <STR_LIT> ) ; case TargetOpcode :: CFI_INSTRUCTION : case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } case <STR_LIT> : switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } case <STR_LIT> : return <NUM_LIT>


<s> if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) { bool IsError = parseSysAlias ( Head , NameLoc , Operands ) ; if ( IsError && getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) Parser . eatToEndOfStatement ( ) ; return IsError ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , false , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ; <STR_LIT> CC = parseCondCodeString ( Head ) ; if ( CC == <STR_LIT> ) return Error ( SuffixLoc , <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , true , SuffixLoc , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , NameLoc , NameLoc , getContext ( ) ) ) ; } while ( Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start , Next ) ; SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , true , SuffixLoc , getContext (


<s> return getSubtargetImpl ( ) -> getDataLayout (


<s> MIB . setMemRefs ( MI -> memoperands ( ) ) ; if ( unsigned OldInstrNum = MI -> peekDebugInstrNum ( ) ) { unsigned Subreg = TRI -> getSubRegIndex ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned NewInstrNum = MIB -> getDebugInstrNum ( * MF


<s> unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; if ( CModel == CodeModel :: Large || ( GV -> getType ( ) -> getElementType ( ) -> isFunctionTy ( ) && ! GV -> isStrongDefinitionForLinker ( ) ) || GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( )

) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ;


<s> static int mips_sign_extend_cost ( machine_mode mode , rtx op ) { if ( MEM_P ( op ) ) return <NUM_LIT> ; if ( TARGET_64BIT && mode == DImode && GET_MODE ( op ) == SImode ) return <NUM_LIT> ; if ( ISA_HAS_SEB_SEH || GENERATE_MIPS16E ) return COSTS_N_INSNS (


<s> if ( ( int32_t ) Overflow < <NUM_LIT> ) { Overflow += ImmOffset ; ImmOffset = <NUM_LIT> ; } C1 = ImmOffset ; if ( Overflow != <NUM_LIT> ) { if ( ! BaseReg ) BaseReg = B . buildConstant ( S32 , Overflow ) . getReg ( <NUM_LIT> ) ; else { auto OverflowVal = B . buildConstant ( S32 , Overflow ) ; BaseReg = B . buildAdd ( S32 , BaseReg , OverflowVal ) . getReg ( <NUM_LIT> ) ; } } } if ( ! BaseReg ) BaseReg = B . buildConstant (

S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < size ; i ++ ) { if ( i ) O << <STR_LIT> ; O << ( unsigned int ) buffer [ i ] ; } } else { unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . Mang -> getSymbol ( GVar ) ; O << * Name ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ; } else llvm_unreachable ( <STR_LIT> ) ; nSym ++ ; if ( nSym >= numSymbols ) nextSymbolPos = size +


<s> const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return <NUM_LIT> ; switch ( MBBI -> getOpcode ( ) ) { default : return <NUM_LIT> ; case TargetOpcode :: PATCHABLE_RET : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( shiftLo >> <NUM_LIT> == <NUM_LIT> ) return Fail ; DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rm , Addr , Decoder ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi == <NUM_LIT> ) return Fail ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder