<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> const GlobalValue * gv = mo . getGlobal ( ) ; TM . getNameWithPrefix ( name , gv , Mang ) ; } else { assert ( mo . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( name , mo . getSymbolName ( ) , ap . getDataLayout ( ) ) ; } return ap . OutContext . getOrCreateSymbol ( name


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT> )


<s> Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn ,


<s> enum rtx_code cmp_code = * code ; * code = NE ; * op0 = loongarch_allocate_fcc ( FCCmode ) ; * op1 = const0_rtx ; loongarch_emit_binary ( cmp_code , * op0


<s> Switches . erase ( std :: remove_if ( Switches . begin ( ) , Switches . end ( ) , [ & ] ( const SwitchInfo * E ) -> bool { return ( E -> Options & OptAlias ) || ! E -> fitsTargetFeatures ( Features ) || ( E -> OpType & T_Type ) == <NUM_LIT> ; } ) , Switches . end ( ) ) ; return Switches


<s> MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; SOffset = isStackPtrRelative ( PtrInfo ) ? CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) ,


<s> bool Filler :: findDelayInstr ( MachineBasicBlock & MBB , MachineBasicBlock :: instr_iterator Slot , MachineBasicBlock :: instr_iterator & Filler ) { SmallSet < unsigned , <NUM_LIT> > RegDefs ; SmallSet < unsigned , <NUM_LIT> > RegUses ; insertDefsUses ( Slot , RegDefs , RegUses ) ; bool SawLoad = false ; bool SawStore = false ; for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugInstr (


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; if ( TheTriple . isOSIAMCU ( ) ) return new ELF<ISA_LIT>_IAMCUAsmBackend ( T


<s> legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } addDescImplicitUseDef ( NewDesc , Inst ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( RI . hasVGPRs ( NewDstRC ) ) continue ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) continue ; break ; default : break ; } unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; legalizeOperands ( Inst ) ; for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( NewDstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr & UseMI = * I -> getParent


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return TargetOpcode :: REG_SEQUENCE ; case <STR_LIT> : return TargetOpcode :: REG_SEQUENCE ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy


<s> if ( ET == <STR_LIT> ) ET = <STR_LIT> ; unsigned Imm = <STR_LIT> ( ET , getShiftExtendAmount ( ) ) ; Inst . addOperand ( MCOperand :: createImm (


<s> static void rs6000_xcoff_unique_section ( tree decl , int reloc ATTRIBUTE_UNUSED ) { const char


<s> void <ISA_LIT>InstPrinter :: printGDS ( const MCInst * MI , unsigned OpNo


<s> int getLRSpillSlot ( ) const { return


<s> emitConstant ( DispVal , <NUM_LIT> ) ; return ; } if ( RelocOp -> isGlobal ( ) ) { unsigned rt = Is64BitMode ? <STR_LIT> : ( IsPIC ? <STR_LIT> : <STR_LIT> ) ; bool NeedStub = isa < Function > ( RelocOp -> getGlobal ( ) ) ; bool Indirect = gvNeedsNonLazyPtr ( RelocOp -> getGlobal ( ) ) ; emitGlobalAddress ( RelocOp -> getGlobal ( ) , rt , RelocOp -> getOffset


<s> MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase (


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) <ISA_LIT>MCInstrInfo


<s> bool pa_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( from == to ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return true ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return true ; return


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( ! MI -> mayLoad ( ) && ! MI ->


<s> if ( flags & SECTION_TLS ) fputs ( <STR_LIT> , asm_out_file ) ; if ( flags & SECTION_CODE ) fputs ( <STR_LIT> , asm_out_file ) ; fputc ( '\n'


<s> MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isBundle ( ) ) return NoHazard ; if ( <ISA_LIT>InstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ( <ISA_LIT>InstrInfo :: isVMEM ( * MI ) || <ISA_LIT>InstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( checkFPAtomicToDenormModeHazard ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( <ISA_LIT>InstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( <ISA_LIT>InstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( <ISA_LIT>InstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ( <ISA_LIT>InstrInfo :: isVMEM ( * MI ) || <ISA_LIT>InstrInfo :: isFLAT ( * MI ) || <ISA_LIT>InstrInfo :: isDS ( * MI ) )

&& checkMAILdStHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;


<s> return <STR_LIT> ( Imm , Subtarget ->


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; return TargetLowering :: allowsMemoryAccess ( Context , DL , VT , AddrSpace , Alignment


<s> case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaDstSel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc0Sel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc1Sel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyDim : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128A16 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ; case ImmTyExpCompr : OS << <STR_LIT> ; break ; case ImmTyExpVM : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ; case ImmTyInterpSlot : OS << <STR_LIT> ; break


<s> unsigned <ISA_LIT>RegisterInfo :: getHWRegIndex ( unsigned Reg )


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; ResultVals . push_back ( Chain . getValue ( <NUM_LIT> )


<s> } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ; if ( ! DAG . isKnownNeverSNaN ( Var ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SL , K0 -> getValueType ( <NUM_LIT> ) , Var , SDValue ( K0 ,

<NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ;


<s> return ( __m128i ) __builtin_ia32_pmovqd128_mask ( ( __v2di ) __A , (


<s> case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: SwiftTail : return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_SaveList : CSR_64_SwiftError_SaveList ; if ( IsWin64 ) return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList ; if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList


<s> Stream << TargetTriple . getArchName ( ) << '-' << TargetTriple . getVendorName ( ) << '-' << TargetTriple . getOSName ( ) << '-' << TargetTriple . getEnvironmentName ( ) << '-' << <STR_LIT> << Version . Major << Version . Minor << Version . Stepping ; if ( hasXNACK ( * STI


<s>
bool
<ISA_LIT>MCAsmStreamer
::
EmitDwarfFileDirective
(
unsigned
FileNo
,
StringRef
Filename
)
{
OS
<<
<STR_LIT>
<<
FileNo
<<
' '
;
PrintQuotedString
(
Filename
,
OS
)
;
EmitEOL
(
)
;
return
this
->
MCStreamer
::
EmitDwarfFileDirective


<s> bool <ISA_LIT>DAGToDAGISel :: trySelect (


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties


<s> for ( MachineBasicBlock * B : POT ) { SetVector < const MachineBasicBlock * > Targets ; bool HaveTargets = computeBlockSuccessors ( B , Targets ) ; for ( MachineInstr & MI : llvm :: reverse ( * B ) ) { if ( InstrExec . count ( & MI ) ) { if ( MI . isBranch ( ) && ! HaveTargets ) continue ; Changed |= MCE . rewrite ( MI , Cells ) ; } } for ( auto I = B -> begin ( ) , E = B -> end ( ) ; I != E ; ++ I ) { if ( I -> isPHI ( ) )


<s> static DecodeStatus s12ImmDecoder ( MCInst & MI , unsigned tmp ,


<s> static bool ShouldXformToMOVHLPS ( ShuffleVectorSDNode * Op ) { if ( Op -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT>


<s> if ( rgn == CONTAINING_RGN ( e -> src -> index ) && BLOCK_TO_BB ( bb -> index ) > BLOCK_TO_BB ( e -> src -> index ) ) add_dependee_for_func_arg ( first_arg , e -> src ) ; } } insn = first_arg ; if ( insn == head ) break ; } } else if ( first_arg ) avoid_func_arg_motion (


<s> static void aarch64_parse_fuse_string ( const char * fuse_string , struct tune_params * tune ) { tune -> fusible_ops = aarch64_parse_boolean_options ( fuse_string , aarch64_fusible_pairs ,


<s> result = ( ( __vector unsigned long long ) vec_vbpermq ( ( __vector unsigned char ) __A , ( __vector unsigned char ) perm_mask ) ) ; return result [ <NUM_LIT>


<s> void <ISA_LIT>TargetELFStreamer :: EmitAMDKernelCodeT ( const amd_kernel_code_t & Header ) { MCStreamer & OS = getStreamer ( ) ; OS . PushSection ( ) ; OS . EmitBytes ( StringRef ( ( const char * ) & Header , sizeof ( Header ) ) ) ; OS . PopSection


<s> static void sparc_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno , padding ; function_arg_slotno ( cum , mode , type , named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ; else { if ( type && ( AGGREGATE_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type


<s> void printARIPI8Mem ( const MCInst * MI , int opNum , raw_ostream & O ) { printARIPIMem ( MI , opNum ,


<s> <ISA_LIT>GenExtract ( ) : FunctionPass ( ID


<s> if ( Offset != FoldedOffset ) { SDValue Remaining = DAG . getConstant ( Offset - FoldedOffset , <STR_LIT> ) ; GA = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA , Remaining ) ; } return GA ; } else { Type * Ty = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; Constant * GA = ConstantExpr :: getBitCast ( const_cast < GlobalValue * > ( GV ) , Ty ) ; Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Constant * Idx = ConstantInt :: get ( Ty , Offset ) ; Constant * GAI = ConstantExpr :: getGetElementPtr ( GA , Idx


<s> assert ( ( Kind == k_Immediate ) && <STR_LIT> ) ; return Imm .


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << k << <STR_LIT> << j << <STR_LIT> ) ; bisReversable = false ; } if ( <ISA_LIT>MCInstrInfo :: isMemReorderDisabled ( MCB ) ) bisReversable = false ; if ( isOrderedDuplexPair ( MCII , * MCB . getOperand ( k ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , k - <NUM_LIT> ) , * MCB . getOperand ( j ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , j - <NUM_LIT> ) , bisReversable , STI ) ) { unsigned iClass = iClassOfDuplexPair ( getDuplexCandidateGroup ( * MCB . getOperand ( k ) . getInst ( ) ) , getDuplexCandidateGroup ( * MCB . getOperand ( j ) . getInst ( ) ) ) ; duplexToTry . push_back ( DuplexCandidate ( j , k , iClass ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << j << <STR_LIT> << k << <STR_LIT> << MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> << MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> ) ; continue ; } else


<s> unsigned VecWidth = DataType -> getPrimitiveSizeInBits ( ) ; return VecWidth == <NUM_LIT> ; } Type * ScalarTy = DataType -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return


<s> SelectionDAG & DAG = CLI . DAG ; SDLoc DL = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & IsTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsPIC = isPositionIndependent ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; <STR_LIT> SpecialCallingConv = getSpecialCallingConv ( Callee ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo , SpecialCallingConv ) ; <ISA_LIT>CCInfo . analyzeCallOperands ( Outs , IsVarArg , Subtarget . abiUsesSoftFloat ( ) , Callee . getNode ( ) , CLI . getArgs ( ) ) ; unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; if ( IsTailCall ) IsTailCall = isEligibleForTailCallOptimization ( <ISA_LIT>CCInfo , NextStackOffset , * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ) ; if ( ! IsTailCall && CLI . CS && CLI . CS . isMustTailCall ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( IsTailCall ) ++ NumTailCalls ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , DL , true ) ; if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffset , <NUM_LIT> , DL ) ; SDValue StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; std :: deque < std :: pair < unsigned , SDValue >> RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; <STR_LIT> ByValArg = <ISA_LIT>CCInfo . byval_begin


<s> TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( )


<s> assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset +

i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_cvttpd2uqq128_mask ( ( __v2df ) __A ,


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > X ( The<ISA_LIT>Target ) ; RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > Y ( The<ISA_LIT>V9Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target ,


<s> LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; if ( ExtType == <STR_LIT> && MemVT . getSizeInBits ( ) < <NUM_LIT> ) { if ( MemVT == <STR_LIT> && isTypeLegal ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; MachineMemOperand * MMO = Load -> getMemOperand ( ) ; EVT RealMemVT = ( MemVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , RealMemVT , MMO ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , MemVT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( ! MemVT . isVector ( ) ) return SDValue ( ) ; assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned Alignment = Load -> getAlignment ( ) ; unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Alignment ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = MemVT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { if ( ! Op -> isDivergent ( ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) return SDValue ( ) ; } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) { if ( Subtarget -> getScalarizeGlobalBehavior ( ) && ! Op -> isDivergent ( ) && ! Load -> isVolatile ( ) && isMemOpHasNoClobberedMemOperand ( Load ) && Alignment >= <NUM_LIT> && NumElements < <NUM_LIT> ) return SDValue ( ) ; } if ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; } if ( AS == <ISA_LIT>AS


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT MaskEltVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1


<s> return selectFlatOffsetImpl < false > ( Root


<s> WidenedLoad ( SmallVectorImpl < LoadInst * > & Lds , LoadInst * Wide ) : NewLd ( Wide ) { for ( auto * I : Lds ) Loads . push_back (


<s> if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> EmitCodeObjectMetadata ( CodeObjectMetadataStreamer . toYamlString ( )


<s> case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return true ; case MachineOperand :: MO_RegisterMask : case MachineOperand :: MO_RegisterLiveOut : return false ; case MachineOperand :: MO_Metadata : case MachineOperand :: MO_MCSymbol : return true ; case MachineOperand :: MO_CFIIndex : return false ; case MachineOperand :: MO_IntrinsicID : case MachineOperand ::


<s> int result = MatchInstructionImpl ( InstOperands , MCI , ErrorInfo , MatchingInlineAsm ) ; if ( result == Match_Success ) { MCI . setLoc ( IDLoc ) ; MustExtend = mustExtend ( InstOperands ) ; canonicalizeImmediates ( MCI ) ; result = processInstruction ( MCI , InstOperands , IDLoc , MustExtend ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MCI . dump_pretty ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCI . setLoc ( IDLoc


<s> } else { const MachineOperand & OffsetOp = MI . getOperand ( OffsetPos ) ; if ( ! OffsetOp . isImm ( ) ) return nullptr ; Offset = OffsetOp . getImm ( ) ; } const MachineOperand & BaseOp = MI . getOperand ( BasePos ) ; if ( BaseOp . getSubReg ( ) != <NUM_LIT>


<s> EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger (


<s> if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; if ( ! emitFPCompare ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg1 , MRI , TRI ) ; auto ValAndVReg = getConstantVRegValWithLookThrough (


<s> } else { lo_half [ num ] = simplify_gen_subreg ( DImode , op , TImode , <NUM_LIT> ) ; hi_half [ num ] = simplify_gen_subreg ( DImode ,


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * mi , int & fi ) const { if ( ( mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> ) && mi -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { assert ( <NUM_LIT> ) ; fi = mi -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return mi -> getOperand ( <NUM_LIT> ) . getReg


<s> auto & Prob = getAnalysis < MachineBranchProbabilityInfo > ( ) ; MachineBasicBlock * S = * std :: max_element ( B . succ_begin ( ) , B . succ_end ( ) , [ & ] ( const MachineBasicBlock * Dst0 , const MachineBasicBlock * Dst1 ) { return Prob . getEdgeProbability ( & B , Dst0 ) < Prob .


<s> static bool IsBitwiseBinaryOperator ( unsigned Opcode ) { switch ( Opcode ) { default : return Instruction :: isShift ( Opcode


<s> for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI


<s> machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; int form_int ; enum rtx_code code ; if ( TREE_CODE ( form ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCFPmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; switch ( form_int ) { case <NUM_LIT> : code = LT ; break ; case <NUM_LIT> : code = GT ; break ; case <NUM_LIT> : code =


<s> if ( count != <NUM_LIT> ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; if ( AP . lowerOperand ( MO , MCOp ) ) OutMI . addOperand (


<s> } MachineFunction * MF = BB -> getParent ( ) ; MachineBasicBlock * SplitBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; replaceSuccessorPhisWith ( * BB , * SplitBB ) ; MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ; SplitBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( SplitBB


<s> for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) StoreVal |= ByteVal << ( I * <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , DAG . getConstant ( StoreVal , DL , <STR_LIT> ( Size * <NUM_LIT> ) ) ,


<s> SS << <STR_LIT> << SU -> NodeNum << <STR_LIT> << SU -> Latency


<s> default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT


<s> static SDValue PerformShuffleVMOVNCombine ( ShuffleVectorSDNode * N , SelectionDAG & DAG ) { SDValue Trunc = N -> getOperand ( <NUM_LIT> ) ; EVT VT = Trunc . getValueType ( ) ; if ( Trunc . getOpcode ( ) != <STR_LIT> || ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SDLoc DL ( Trunc ) ; if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , false ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , true ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return SDValue ( )


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable ,


<s> uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt


<s> for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; assert ( Reg != <STR_LIT> && ! ( Reg == <STR_LIT> && hasFP ( * MF ) ) && <STR_LIT> ) ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , I . getFrameIdx ( ) , RC , TRI ) ; if ( emitFrameMoves


<s> int dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest


<s> LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { if ( MI != MBB . end ( ) ) { MIB . copyImplicitOps ( * MI ) ; MI -> eraseFromParent ( ) ; } } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . setMIFlags ( MachineInstr :: FrameDestroy ) ; if ( LdrOpc == <STR_LIT> || LdrOpc


<s> SmallVector < unsigned , <NUM_LIT> > NewRegs ; expandSpillMacros ( MF , NewRegs ) ; if ( OptimizeSpillSlots && ! isOptNone ( MF ) ) optimizeSpillSlots ( MF , NewRegs ) ; if ( ! NewRegs . empty ( ) ) { MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SetVector < const TargetRegisterClass * > SpillRCs ; SpillRCs . insert ( & <STR_LIT> ) ; for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = RC == & <STR_LIT> ? NumberScavengerSlots : <NUM_LIT> ; unsigned S = RC -> getSize ( ) , A = RC -> getAlignment ( ) ; for ( unsigned i = <NUM_LIT> ; i < Num


<s> OutStreamer . SwitchSection ( TLOFMacho . getTextSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getConstTextCoalSection ( ) ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } } } O << <STR_LIT> ; if ( Subtarget -> isTargetELF ( ) ) { std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString != <STR_LIT> ) O << <STR_LIT> << CPUString << '\n' ; if ( Subtarget -> hasVFP2 ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( ! UnsafeFPMath ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( FiniteOnlyFPMath ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; else O << <STR_LIT> << <STR_LIT>


<s> } const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT ,


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t Value = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: CreateImm ( ( ~ Value


<s> for ( unsigned L = <NUM_LIT> ; L < NUM_BANKS ; ++ L ) if ( FreeBanks & ( <NUM_LIT> << L ) )


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT>


<s> <ISA_LIT>TargetLowering :: <STR_LIT> <ISA_LIT>TargetLowering :: getSpecialCallingConv ( SDValue Callee ) const { <STR_LIT> SpecialCallingConv = <STR_LIT> ; return


<s> int pos ; int i ; rtx_insn * tmp ; rtx load_mem , str_mem ; if ( is_store_insn ( last_scheduled_insn , & str_mem ) ) load_store_pendulum -- ; else if ( is_load_insn ( last_scheduled_insn , & load_mem ) ) load_store_pendulum ++ ; else return cached_can_issue_more ; if ( ( load_store_pendulum == <NUM_LIT> ) || ( * pn_ready <= <NUM_LIT> ) ) return cached_can_issue_more ; if ( load_store_pendulum == <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ * pn_ready - <NUM_LIT> ] = tmp ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( tmp ) ) INSN_PRIORITY ( tmp ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { int first_store_pos = - <NUM_LIT> ; pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) ) { rtx str_mem2 ; if ( first_store_pos == - <NUM_LIT> ) first_store_pos = pos ; if ( is_store_insn ( last_scheduled_insn , & str_mem2 ) && adjacent_mem_locations ( str_mem , str_mem2 ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ]


<s> return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoPIC ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; ParserOptions . IsPicEnabled = false ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveOptionNoRelax ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveOptionCapMode ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveOptionNoCapMode ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> ,


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm12OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) ->

addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFP_TO_SINTCombine ( N , DAG ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG ,


<s> MachineInstr * MI = & * I ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case TargetOpcode :: COPY : if ( isPredReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { RegisterSubReg RD = MI ->


<s> if ( ! BV -> getConstantSplatNode ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getNode ( <STR_LIT> , DL , IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , MaskConst ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd ) ; return Res


<s> SDNode * node = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , CPIdx , CurDAG -> getEntryNode ( ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; cast < MachineSDNode > ( node ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return node ; } break ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT>


<s> const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) { unsigned ArgReg = ByValArgRegs [ FirstReg + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * GPRSizeInBytes ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , FIN , DAG . getConstant ( Offset , DL , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , DL , DAG . getRegister ( VReg , RegTy

) , StorePtr , MachinePointerInfo ( FuncArg , Offset ) , false , false , <NUM_LIT> ) ;


<s> break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( * MCII , RF . getSubtargetInfo ( ) , Inst , Inst , * Asm . getContext ( ) . getRegisterInfo ( ) ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } } bool Error = <ISA_LIT>MCShuffle ( true , * MCII , RF . getSubtargetInfo ( ) , Inst ) ; ( void ) Error


<s> BB -> addSuccessor ( copy0MBB ) ; } BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( sinkMBB ) ; } copy0MBB -> addSuccessor ( sinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = sinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ; MIB = BuildMI ( * sinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( copy0MBB ) . addReg ( Op2Reg ) . addMBB ( thisMBB ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } if ( CascadedCMOV ) { MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( jcc1MBB ) ; BuildMI ( * sinkMBB , std :: next ( MachineBasicBlock :: iterator ( MIB . getInstr ( ) ) ) , DL , TII -> get ( TargetOpcode :: COPY ) , CascadedCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; CascadedCMOV -> eraseFromParent ( ) ; } for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ) ( MIIt ++ ) -> eraseFromParent ( ) ; return sinkMBB


<s> return new AMDGPUCFGStructurizer ( )


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; if ( CPU . empty ( ) ) CPU = <STR_LIT> ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU


<s> return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( II -> getRegisterInfo ( ) . getEncodingValue ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } } const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( ( MCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { emitWordLE ( Binary | getMachineSoRegOpValue ( MI ,


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned opc [ <NUM_LIT> ] ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned Reg = Cond [ <NUM_LIT> ] . getReg ( ) ; if ( IsIntegerCC ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { if ( TRI -> getRegSizeInBits ( Reg , MRI ) == <NUM_LIT> ) { opc [ <NUM_LIT> ] = <STR_LIT> ; opc [ <NUM_LIT> ] = <STR_LIT> ; } else { opc [ <NUM_LIT> ] = <STR_LIT> ; opc [ <NUM_LIT> ] = <STR_LIT> ; } } else


<s> return true ; case <STR_LIT> : lowerLongBranchLUi ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ) ; return true ; case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) ; return true ; case <STR_LIT> : unsigned TargetFlags = MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI

, <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ) ;


<s> extern_symbol * p = VEC_safe_push ( extern_symbol , gc , extern_symbols , NULL ) ; gcc_assert ( file == asm_out_file ) ; p -> decl = decl ; p -> name


<s> insn = NEXT_INSN ( insn ) ; if ( insn == <NUM_LIT> || ( active_insn_p ( insn ) && NONDEBUG_INSN_P ( insn ) && ! NOTE_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != UNSPEC_VOLATILE && GET_CODE ( PATTERN ( insn ) ) != PARALLEL ) ) break ; } return insn


<s> if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue


<s> void <ISA_LIT>InstPrinter :: printNFMT ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU8ImmDecOperand ( MI , OpNo ,


<s> case MachineOperand :: MO_Immediate : { auto Expr = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( MO . getImm ( ) , AP . OutContext ) , AP . OutContext ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * Expr , MustExtend ) ; MCO = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_MachineBasicBlock : { MCExpr const * Expr = MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , AP . OutContext ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * Expr , MustExtend ) ; MCO = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_GlobalAddress : MCO = GetSymbolRef ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP , MustExtend ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCO = GetSymbolRef ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP , MustExtend ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , MustExtend ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , MustExtend ) ; break ; case MachineOperand ::


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . useSoftFloat ( ) && STI . hasVFP2 ( ) && ! STI . isThumb1Only ( ) ) return CSR_NoRegs_RegMask ; else return CSR_FPRegs_RegMask


<s> <ISA_LIT>_64ATTAsmParser ( const Target & T , MCAsmParser & Parser , TargetMachine & TM ) : <ISA_LIT>ATTAsmParser


<s> if ( mode == AVX_U128_CLEAN ) ix86_avx_emit_vzeroupper ( regs_live ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable (


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( ! N -> hasOneUse ( ) ) return false ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> ) Cond = Cond .


<s> MVT RetVT ; const Function * Callee = II -> getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( <NUM_LIT> ) ; if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; <STR_LIT> TmpCC ; switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : TmpCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TmpCC = <STR_LIT> ; break ; } if ( II -> getParent ( ) != I -> getParent ( ) ) return false ; BasicBlock :: const_iterator Start = I ; BasicBlock :: const_iterator End = II ; for ( auto Itr = std :: prev ( Start ) ; Itr != End ; -- Itr ) { if ( ! isa < ExtractValueInst > ( Itr ) ) return


<s> CPUser ( MachineInstr * mi , MachineInstr * cpemi , unsigned maxdisp , bool neg , bool soimm ) : MI ( mi ) , CPEMI ( cpemi ) , MaxDisp ( maxdisp

) , NegOk ( neg ) , IsSoImm ( soimm ) , KnownAlignment ( false ) {


<s> if ( ! ST . hasCaymanISA ( ) && ! branchStackContains ( CFStack :: FIRST_NON_WQM_PUSH ) ) Item = CFStack :: FIRST_NON_WQM_PUSH ; else if ( CurrentEntries > <NUM_LIT> && ST . getGeneration ( ) > AMDGPUSubtarget :: EVERGREEN && ! ST . hasCaymanISA ( ) && ! branchStackContains ( CFStack :: FIRST_NON_WQM_PUSH_W_FULL_ENTRY ) ) Item = CFStack :: FIRST_NON_WQM_PUSH_W_FULL_ENTRY ; else Item = CFStack :: SUB_ENTRY ; } else Item = CFStack :: ENTRY ; break ; } BranchStack . push_back


<s> bool has<ISA_LIT>32r6 ( ) const { return STI . getFeatureBits (


<s> OperandSignedness LHSSign ; if ( ! IsMulWideOperandDemotable ( LHS , OptSize , LHSSign ) ) return false ; if ( LHSSign == Unknown ) return false ; IsSigned = ( LHSSign == Signed ) ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( RHS ) ) { APInt Val = CI ->


<s> void LLVMInitialize<ISA_LIT>Z80Target (


<s> return ( dead_or_set_p ( insn , reg ) || ( REG_P ( reg )

&& _reg_unused_after ( insn , reg ) ) ) ;


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == <NUM_LIT> ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; unsigned PC ; if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( <STR_LIT> ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addImm ( <NUM_LIT> ) ; if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } return true


<s> if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( Subtarget -> isFPOnlySP ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasFP16 ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasMPExtension ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasDivideIn<ISA_LIT>Mode ( ) && ! Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasTrustZone ( ) && Subtarget -> hasVirtualization ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasTrustZone ( ) ) ATS . emitAttribute ( <STR_LIT>


<s> if ( ! MI . mayLoad ( ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; bool AllDefsAreGPR = llvm :: all_of ( MI . defs ( ) , [ & ] ( MachineOperand & Op ) { return Op . isReg ( ) && ( <STR_LIT> . contains ( Op . getReg ( ) ) || <STR_LIT> . contains ( Op . getReg ( ) ) ) ; } ) ; bool HardenLoadedData = AllDefsAreGPR ; bool HardenAddressLoadedFrom = ! HardenLoadedData ; for ( MachineOperand Op : MI . defs ( ) ) for ( MCRegAliasIterator AI ( Op . getReg ( ) , TRI , true ) ; AI . isValid ( ) ; ++ AI ) RegsAlreadyMasked . reset ( * AI ) ; if ( HardenLoadedData ) for ( auto Def : MI . defs ( ) ) { if ( Def . isDead ( ) ) continue ; Modified |= makeGPRSpeculationSafe ( MBB , NextMBBI , MI , Def . getReg ( ) ) ; } if ( HardenAddressLoadedFrom ) for ( auto Use : MI . uses ( ) ) { if ( ! Use . isReg ( ) ) continue ; unsigned Reg = Use . getReg ( ) ; if ( ! ( <STR_LIT> . contains ( Reg ) ||

<STR_LIT> . contains ( Reg ) ) ) continue ;


<s> cum -> ints = <NUM_LIT> ; for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : <NUM_LIT> ; param != ( tree ) <NUM_LIT> ; param


<s> for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return


<s> if ( TARGET_VIS ) switch ( mode ) { case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case


<s> MachineBasicBlock :: iterator <ISA_LIT>PacketizerList :: addToPacket ( MachineInstr * MI ) { MachineBasicBlock :: iterator MII = MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; if ( GlueToNewValueJump ) { ++ MII ; MachineInstr * nvjMI = MII ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources ( MI ) ; if ( ( QII -> isExtended ( MI ) || QII -> isConstExtended ( MI ) ) && ! tryAllocateResourcesForConstExt ( MI ) ) { endPacket ( MBB , MI ) ; ResourceTracker -> reserveResources ( MI ) ; assert ( canReserveResourcesForConstExt ( MI ) && <STR_LIT> ) ; reserveResourcesForConstExt ( MI ) ; assert ( canReserveResourcesForConstExt ( MI ) && <STR_LIT> ) ; reserveResourcesForConstExt ( nvjMI ) ; assert ( ResourceTracker -> canReserveResources ( nvjMI


<s> return ( __m512d ) __builtin_ia32_gatherdiv8df ( ( __v8df ) v1_old , __addr , (


<s> if ( ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand


<s> bool <ISA_LIT>FixupHwLoops :: runOnMachineFunction ( MachineFunction &


<s> if ( ! MEM_P ( op ) ) return false ; if ( offsettable_address_p ( strict , GET_MODE ( op ) , XEXP (


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ( ! Subtarget -> hasFMA ( ) && ! Subtarget -> hasFMA4 ( ) ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode (


<s> mem_hi = adjust_address ( mem , QImode , byte_offset + <NUM_LIT> ) ; lo = gen_reg_rtx ( mode ) ; emit_insn ( gen_zero_extendqisi2 ( lo , mem_lo ) ) ; if ( sign ) { rtx tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_ashlsi3 ( gen_lowpart ( SImode , tmp ) , gen_lowpart ( SImode , hi ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_iorsi3 ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , lo ) , gen_lowpart ( SImode , tmp ) ) ) ; } else { emit_insn ( gen_zero_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_insn_intlb ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , hi ) , gen_lowpart ( SImode , lo ) ) ) ; } return ; } mema = XEXP ( mem , <NUM_LIT> ) ; addr_lo = force_reg ( Pmode , plus_constant ( Pmode , mema , byte_offset ) ) ; mem_lo = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_lo , GEN_INT ( - <NUM_LIT> ) ) ) ; set_mem_alias_set ( mem_lo , <NUM_LIT> )


<s> static SDValue performDivRemCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT Ty = N -> getValueType ( <NUM_LIT> ) ; unsigned LO = <STR_LIT> ; unsigned HI = <STR_LIT> ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue DivRem = DAG . getNode ( Opc , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue InGlue = DivRem ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , DL , LO , Ty ,


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return ParseMemOperand ( <NUM_LIT> , Parser . getTok ( ) . getLoc ( ) ) ; case AsmToken :: Percent : { unsigned RegNo ; SMLoc Start , End ; if ( ParseRegister ( RegNo , Start , End ) ) return <NUM_LIT> ; if ( RegNo == <STR_LIT> || RegNo == <STR_LIT> ) { Error ( Start , <STR_LIT> ) ; return <NUM_LIT> ; } if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; getParser ( ) .


<s> <ISA_LIT>ParamManager ( const DataLayout * _DL ) : DL


<s> if ( ( old_flags ^ target_flags ) & ( MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH4 ) ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_HITACHI ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_LITTLE_ENDIAN ) return _ ( <STR_LIT> ) ; return NULL


<s> <ISA_LIT>Lowering = TM . getSubtargetImpl ( ) -> getTargetLowering ( ) ; <ISA_LIT>SubTarget = TM . getSubtargetImpl ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! <ISA_LIT>SubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true


<s> if ( TARGET_PORTABLE_RUNTIME ) return <NUM_LIT> ; if ( ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) && ! optimize_size ) return <NUM_LIT> ; if ( ! TARGET_LONG_CALLS && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < <NUM_LIT> ) || distance < MAX_PCREL17F_OFFSET ) ) return <NUM_LIT> ; if ( ! flag_pic ) return <NUM_LIT> ; if ( TARGET_NO_SPACE_REGS || TARGET_PA_20 ) return <NUM_LIT> ; if ( ! optimize_size ) return <NUM_LIT> ; return <NUM_LIT>


<s> if ( MemType -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE1 ( )

|| Subtarget . hasX87 ( ) ) ) return AtomicExpansionKind :: None ;


<s> <ISA_LIT>PacketizerList :: <ISA_LIT>PacketizerList ( MachineFunction & MF , MachineLoopInfo & MLI , AAResults * AA , const MachineBranchProbabilityInfo * MBPI ) : VLIWPacketizerList ( MF , MLI , AA ) , MBPI ( MBPI ) , MLI ( & MLI ) { HII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; Dependence = false ; PacketNum = <NUM_LIT> ; addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: <ISA_LIT>DAGMutation >


<s> NewOpcode = IsAdd ? <STR_LIT> : <STR_LIT> ; break ; } SDLoc dl ( Op ) ; SDValue Add = DAG . getNode ( NewOpcode , dl , <STR_LIT> , DAG . getSExtOrTrunc ( Op -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> ) , DAG . getSExtOrTrunc ( Op -> getOperand ( <NUM_LIT> ) , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl


<s> switch ( mode ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : return true ; case E_SFmode : case E_DFmode : return


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> )


<s> if ( ! arg . named || arg . end_marker_p ( ) ) return <NUM_LIT> ; if ( targetm . calls . must_pass_in_stack ( arg


<s> } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = alignTo ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( * FuncInfo . MF , Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ; ( void ) ( MMO ) ; return false


<s> bool <ISA_LIT>ExpandCondsets :: coalesceRegisters ( RegisterRef R1 , RegisterRef R2 ) { if ( CoaLimitActive ) { if ( CoaCounter >= CoaLimit ) return false ; CoaCounter ++ ; } unsigned BW1 , BW2 ; if ( ! isIntReg ( R1 , BW1 ) || ! isIntReg ( R2 , BW2 ) || BW1 != BW2 ) return false ; if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return


<s> rtx eh_ofs = EH_RETURN_STACKADJ_RTX ; if ( Pmode == DImode ) emit_insn ( gen_adddi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; else emit_insn ( gen_addsi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; tsize_rtx = eh_ofs ; } emit_insn ( gen_blockage ( ) ) ; if ( tsize != <NUM_LIT> || current_function_calls_eh_return ) { if ( ! TARGET_MIPS16 ) { if ( Pmode == DImode ) emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; else emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; } else { rtx g6_rtx = gen_rtx ( REG , Pmode , GP_REG_FIRST + <NUM_LIT> ) ; if ( Pmode == DImode ) { emit_insn ( gen_movdi ( g6_rtx , stack_pointer_rtx ) ) ; emit_insn ( gen_adddi3 ( g6_rtx , g6_rtx , tsize_rtx ) ) ; emit_insn ( gen_movdi ( stack_pointer_rtx , g6_rtx ) ) ; } else { emit_insn ( gen_movsi ( g6_rtx , stack_pointer_rtx ) ) ; emit_insn ( gen_addsi3 ( g6_rtx , g6_rtx , tsize_rtx ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx ,


<s> bool <ISA_LIT>Operand :: isReg ( ) const { return Kind == Kind :: MemOp && MemOp


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) .


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return Success


<s> assert ( GlueChain -> getNumValues ( ) == <NUM_LIT> ) ; SDVTList VTList = DAG . getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } return DAG . getNode ( Opcode , SL , VTList , { GlueChain . getValue ( <NUM_LIT> ) , A , B , GlueChain . getValue ( <NUM_LIT> )


<s> unsigned int \ current_section_flags ( ) \ { \ switch ( in_section ) \ { \ case no_section : return <NUM_LIT> ; \ case in_text : return SECTION_CODE ; \ case in_data : return SECTION_WRITE ; \ case in_sdata : return SECTION_WRITE | SECTION_SMALL ; \ case in_bss : return SECTION_WRITE

| SECTION_BSS ; \ case in_rdata : \ case in_const : return <NUM_LIT> ; \ case in_named : return get_named_section_flags ( in_named_name ) ; \ } \ abort ( ) ; \ }


<s> int Idx = getOperandIdx ( * MI , Op ) ; assert ( Idx != - <NUM_LIT> && <STR_LIT> ) ; assert ( MI -> getOperand ( Idx ) . isImm ( ) ) ; MI -> getOperand ( Idx ) .


<s> ChangeStatus manifest ( Attributor & A ) override { SmallVector < Attribute , <NUM_LIT> > AttrList ; LLVMContext & Ctx = getAssociatedFunction ( ) -> getContext ( ) ; for ( StringRef AttrName : Attributes ) AttrList . push_back ( Attribute :: get ( Ctx


<s> std :: vector < std :: string > mov_memsp_r6 ( ) { return D ( <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> Type * I32Ty = getI32Ty ( Builder , I . getType ( ) ) ; Value * ExtOp0 = nullptr ; Value * ExtOp1 = nullptr ; Value * ExtRes = nullptr ; Value * TruncRes = nullptr ; if ( isSigned ( I ) ) { ExtOp0 = Builder . CreateSExt ( I . getOperand ( <NUM_LIT> ) , I32Ty ) ; ExtOp1 = Builder . CreateSExt ( I . getOperand ( <NUM_LIT> ) , I32Ty


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target


<s> return hash_combine ( DenseMapInfo < const MCSymbol * > :: getHashValue ( V . sym ) , DenseMapInfo <


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftLeftImm8 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo &


<s> return isMesa3DOS ( ) && ! <STR_LIT> ( MF . getFunction ( ) ->


<s> if ( ! STI . hasFeature ( <STR_LIT> ) && ! STI . hasFeature ( <STR_LIT> ) ) return <NUM_LIT> ; if ( STI . getFeatureBits ( )


<s> } if ( swap ) { code = swap_condition ( code ) ; tmp = op0 , op0 = op1 , op1 = tmp ; } if ( ! reg_or_0_operand ( op0 , cmp_mode ) ) op0 = force_reg ( cmp_mode , op0 ) ; if ( ! CONST_INT_P ( op1 ) && ! register_operand ( op1 , cmp_mode ) ) op1 = force_reg ( cmp_mode , op1 ) ; emit_insn ( gen_rtx_SET ( res , gen_rtx_fmt_ee ( code , DImode ,


<s> static bool isOpcWithIntImmediate ( SDNode * N , unsigned Opc , unsigned & Imm ) { return N -> getOpcode ( ) == Opc && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> APInt ShAmt = N1C -> getAPIntValue ( ) ; Mask = Mask . shl ( ShAmt ) ; if ( Mask != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N00 , DAG . getConstant ( Mask , VT ) ) ; } } if ( auto * N1BV = dyn_cast < BuildVectorSDNode > ( N1 ) ) if ( auto * N1SplatC = N1BV -> getConstantSplatNode ( ) ) { assert ( N0 . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; if ( N1SplatC -> getZExtValue ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N0 ) ; } return SDValue (


<s> LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) . addImm ( <STR_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg )


<s> if ( HasFP ) { unsigned DwFPReg = HRI . getDwarfRegNum ( HRI . getFrameRegister ( ) , true ) ; unsigned DwRAReg = HRI . getDwarfRegNum ( HRI . getRARegister ( ) , true ) ; auto DefCfa = MCCFIInstruction :: createDefCfa ( FrameLabel , DwFPReg , - <NUM_LIT> ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MF . addFrameInst ( DefCfa ) ) ; auto OffR31 = MCCFIInstruction :: createOffset ( FrameLabel , DwRAReg , - <NUM_LIT> ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MF . addFrameInst ( OffR31 ) ) ; auto OffR30 = MCCFIInstruction :: createOffset ( FrameLabel , DwFPReg , - <NUM_LIT> ) ; BuildMI ( MBB , At , DL , CFID ) . addCFIIndex ( MF . addFrameInst ( OffR30 ) ) ; } static unsigned int RegsToMove [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( unsigned i = <NUM_LIT> ; RegsToMove [ i ] != <STR_LIT> ; ++ i ) { unsigned Reg = RegsToMove [ i ] ; auto IfR = [ Reg ] ( const CalleeSavedInfo &


<s> int i ; if ( TARGET_G10 ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) fprintf ( asm_out_file , <STR_LIT> , i , <NUM_LIT> + i ) ; } else { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { fprintf ( asm_out_file , <STR_LIT> , <NUM_LIT> + i , <NUM_LIT> + i ) ; fprintf ( asm_out_file , <STR_LIT> , <NUM_LIT> + i , <NUM_LIT> + i ) ; fprintf ( asm_out_file , <STR_LIT> , <NUM_LIT> + i , <NUM_LIT> + i ) ; } } opt_pass * rl78_devirt_pass = make_pass_rl78_devirt


<s> int <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace , const Instruction * I ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) { return LT .


<s> for ( const MachineOperand & MO : MI . implicit_operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) ) if ( TRI -> regsOverlap ( Reg , MO .


<s> Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; PtrInOperand = true ; } Start = Tok . getLoc ( ) ; if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , End ) ; unsigned RegNo = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) { return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; } return <STR_LIT> ( RegNo , Start , End ) ; } return ParseIntelSegmentOverride ( RegNo , Start , Size ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( <NUM_LIT> , Start , <NUM_LIT> , false , Size ) ; AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; bool isSymbol = SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) != MCExpr :: Constant ; int64_t Imm = SM . getImm ( ) ; if ( SM . getSym ( ) && SM . getSym ( ) -> getKind ( ) == MCExpr :: Constant ) SM . getSym ( ) -> evaluateAsAbsolute ( Imm ) ; if ( StartTok . isNot ( AsmToken :: Identifier ) && StartTok . isNot ( AsmToken :: String ) && isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> emplace_back ( AOK_ImmPrefix , Start ) ; else InstInfo -> AsmRewrites -> emplace_back ( AOK_Imm , Start , Len , Imm ) ; } if ( getLexer ( ) . isNot ( AsmToken


<s> rtx temp = reload_in_progress ? operands [ <NUM_LIT> ] : gen_reg_rtx ( Pmode ) ; gcc_assert ( ! TARGET_FDPIC || ! ( reload_in_progress || reload_completed ) ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = force_reg ( SImode , operands [ <NUM_LIT> ] ) ; else operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , temp , TARGET_FDPIC ? OUR_FDPIC_REG :


<s> return ( ( GET_MODE_SIZE ( mode ) + rs -


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case


<s> if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) if ( MemRefsFixed || isVolatileInstr ( MI ) ) return true ; if ( MI -> isDebugInstr ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return true ; case TargetOpcode :: PHI : case TargetOpcode :: COPY : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> unsigned encodeExpcnt ( IsaVersion Version , unsigned Waitcnt , unsigned Expcnt ) { return packBits ( Expcnt , Waitcnt , getExpcntBitShift (


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Src0 . isReg ( ) && RI . isVGPR ( MRI , Src0 . getReg ( ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src0 ) ; Src0 . ChangeToRegister ( Reg , false ) ; } if ( Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } return ; } if ( Src0 . isReg ( ) && RI . isAGPR ( MRI , Src0 . getReg ( ) ) ) legalizeOpWithMove ( MI , Src0Idx ) ; if ( Src1 . isReg ( ) && RI . isAGPR ( MRI , Src1 . getReg ( ) ) ) legalizeOpWithMove ( MI , Src1Idx ) ; if ( isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src1 ) ) return ; if ( Opc == <STR_LIT> && Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; return ; } if ( HasImplicitSGPR || ! MI . isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } MI . setDesc ( get ( CommutedOpc ) ) ; Register Src0Reg = Src0 . getReg ( ) ; unsigned Src0SubReg = Src0 . getSubReg ( ) ; bool Src0Kill = Src0 . isKill ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1


<s> } else { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; setOperationAction ( <STR_LIT> , VT , Promote ) ; AddPromotedToType ( <STR_LIT> , VT , PromotedBitwiseVT ) ; } setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> ,


<s> for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & DefMI = * MII ; if ( ! isNopInstr ( & DefMI ) ) { dbgs ( ) << <STR_LIT> <<


<s> } ; auto IsVMLAV = [ & ] ( MVT RetTy , unsigned ExtendCode , ArrayRef < MVT > ExtTypes , SDValue & A , SDValue & B ) { if ( ResVT != RetTy || N0 -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue ExtA = N0 -> getOperand ( <NUM_LIT> ) ; SDValue ExtB = N0 -> getOperand ( <NUM_LIT> ) ; if ( ExtA -> getOpcode ( ) != ExtendCode && ExtB -> getOpcode ( ) != ExtendCode ) return false ; A = ExtA -> getOperand ( <NUM_LIT> ) ; B = ExtB -> getOperand ( <NUM_LIT> ) ; if ( A . getValueType ( ) == B . getValueType ( ) && llvm :: any_of ( ExtTypes , [ & A ] ( MVT Ty ) { return A . getValueType ( ) == Ty ; } ) ) return true ; return false ; } ; auto Create64bitNode = [ & ] ( unsigned Opcode , ArrayRef < SDValue > Ops ) { SDValue Node = DAG . getNode ( Opcode , dl , { <STR_LIT> , <STR_LIT> } , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node , SDValue ( Node . getNode ( ) , <NUM_LIT> ) ) ; } ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A ) ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A ) ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> } ) ) return Create64bitNode ( <STR_LIT> , { A } ) ; if ( SDValue A = IsVADDV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> } ) ) return Create64bitNode ( <STR_LIT> , { A } ) ; SDValue A , B ; if ( IsVMLAV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } , A , B ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A , B ) ; if ( IsVMLAV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } , A , B ) ) return DAG . getNode ( <STR_LIT> , dl , ResVT , A , B ) ; if ( IsVMLAV ( <STR_LIT> , <STR_LIT> , { <STR_LIT> , <STR_LIT> } , A , B ) ) return Create64bitNode (


<s> if ( ShiftExtend . ShiftType != <STR_LIT> ) return false ; return ! ShiftExtend . ImplicitAmount && ShiftExtend .


<s> ++ NumFunctionsConsidered ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; const auto & MDT = getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; std :: unique_ptr < MachineGadgetGraph > Graph = getGadgetGraph ( MF , MLI , MDT , MDF ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Graph == nullptr ) return false ; if ( EmitDotVerify ) { writeGadgetGraph ( outs ( ) , MF , Graph . get ( ) ) ; return false ; } if ( EmitDot || EmitDotOnly ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; std :: error_code FileError ; std :: string FileName = <STR_LIT> ; FileName += MF . getName ( ) ; FileName +=


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; if ( ! IgnoreSPUpdates && ! hasReservedCallFrame ( MF ) )


<s> bool MadeChange = false ; MachineBasicBlock * MBB ; unsigned int Cycles = <NUM_LIT> ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue (


<s> bool isMemWithSimmOffset ( ) const { return isMem ( ) && isConstantMemOff ( ) && isInt < Bits


<s> bool allowsUnalignedFPAccess ( ) const { return AllowsUnalignedFPAccess


<s> <ISA_LIT>FI -> setCallsEhReturn ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT Ty = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned OffsetReg = IsN64 ? <STR_LIT> : <STR_LIT> ; unsigned AddrReg = IsN64 ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , OffsetReg , Offset , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , AddrReg , Handler , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getRegister ( OffsetReg , Ty

) , DAG . getRegister ( AddrReg , getPointerTy ( ) ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( Op , Mask17 ) ) return Op ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op , DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> && VT . getSizeInBits ( ) <= <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; if ( Src . getScalarValueSizeInBits ( ) < <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) { EVT ExtVT = VT . changeVectorElementType ( <STR_LIT> ) ; Src = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , ExtVT , Src ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } } if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && Op . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ; } ; SDValue ZeroN0 = GetZeroableOp ( N0 ) ; SDValue ZeroN1 = GetZeroableOp ( N1 ) ; if ( ! ZeroN0 && ! ZeroN1 ) return SDValue


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X )


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange ( Mask [

i ] , NumOps , NumOps * <NUM_LIT> ) ) || ( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ;


<s> static rtx restore_fpr ( rtx base , int offset , int regnum ) { rtx addr ; addr = gen_rtx_MEM ( DFmode , plus_constant ( Pmode , base , offset ) ) ; set_mem_alias_set ( addr ,


<s> HasRt = true ; } if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; if ( HasRt ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler