<s> if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; SDLoc dl ( InputVector ) ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InputVector ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; EVT ElementType = InputVector . getValueType ( ) . getVectorElementType


<s> SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , B , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AloBhi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AhiBlo , DAG . getConstant ( <NUM_LIT>


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , TAB


<s> int rl78_one_far_p ( rtx * operands , int n ) { rtx which = NULL ; int i , c = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < n ; i ++ )


<s> case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectG_ADD_SUB ( I ) ) return true ; LLVM_FALLTHROUGH ; default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode ::


<s> Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getVectorElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( VecTy -> getVectorElementType ( ) , BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Builder . CreateBitCast ( BaseAddr , PtrTy ) , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple . getArch ( ) == Triple :: aarch64_32 ) ; else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) MAI = new <ISA_LIT>MCAsmInfoMicrosoftCOFF ( ) ; else if ( TheTriple . isOSBinFormatCOFF ( ) ) MAI = new <ISA_LIT>MCAsmInfoGNUCOFF


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ( TRI -> getSubRegIdxSize ( Idx ) ) , DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op , DAG . getConstant ( TRI ->

getSubRegIdxOffset ( Idx ) , DL , <STR_LIT> ) ) ) ;


<s> computeSignatureVTs ( F . getFunctionType ( ) , F , TM , Params , Results ) ; auto * Sym = cast < MCSymbolWasm > ( getSymbol ( & F ) ) ; Sym -> setType ( <STR_LIT> ) ; if ( ! Sym -> getSignature ( ) ) { auto Signature = signatureFromMVTs ( Results , Params ) ; Sym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; } getTargetStreamer ( ) -> emitFunctionType ( Sym ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatWasm ( ) && F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportModule ( Name ) ; getTargetStreamer ( ) -> emitImportModule ( Sym , Name ) ; } if ( TM . getTargetTriple ( ) . isOSBinFormatWasm ( ) && F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportName ( Name ) ; getTargetStreamer ( ) -> emitImportName ( Sym , Name ) ; } } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) ,

MCConstantExpr :: create ( Size , OutContext ) ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetConstant ( Pattern , DL ,


<s> static bool isVectorShift ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG , bool

& isLeft , SDValue & ShVal , unsigned & ShAmt ) {


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( )


<s> return __builtin_aarch64_reduc_smax_scal_v4hi (


<s> HOST_WIDE_INT words , n_gpr , n_fpr ; tree f_gpr , f_fpr , f_ovf , f_sav ; tree gpr , fpr , ovf , sav , t ; if ( ! TARGET_64BIT ) { std_expand_builtin_va_start ( valist , nextarg ) ; return ; } f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = TREE_CHAIN ( f_gpr ) ; f_ovf = TREE_CHAIN ( f_fpr ) ; f_sav = TREE_CHAIN ( f_ovf ) ; valist = build1 ( INDIRECT_REF , TREE_TYPE ( TREE_TYPE ( valist ) ) , valist ) ; gpr = build ( COMPONENT_REF , TREE_TYPE ( f_gpr ) , valist , f_gpr , NULL_TREE ) ; fpr = build ( COMPONENT_REF , TREE_TYPE ( f_fpr ) , valist , f_fpr , NULL_TREE ) ; ovf = build ( COMPONENT_REF , TREE_TYPE ( f_ovf ) , valist , f_ovf , NULL_TREE ) ; sav = build ( COMPONENT_REF , TREE_TYPE ( f_sav ) , valist , f_sav , NULL_TREE ) ; words = current_function_args_info . words ; n_gpr = current_function_args_info . regno ; n_fpr = current_function_args_info . sse_regno ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , ( int ) words , ( int ) n_gpr , ( int ) n_fpr ) ; if ( cfun -> va_list_gpr_size ) { t = build ( MODIFY_EXPR , TREE_TYPE ( gpr ) , gpr , build_int_cst ( NULL_TREE , n_gpr * <NUM_LIT> ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } if ( cfun -> va_list_fpr_size


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass


<s> return decodeRegisterClass ( Inst , RegNo , VSFRegs


<s> static SDValue LowerCTPOP ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Op . getSimpleValueType ( ) . isVector


<s> unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst


<s> if ( GET_CODE ( op ) == SUBREG && ( mode == DFmode || mode == TFmode || mode == IFmode || mode == KFmode ) && REG_P ( SUBREG_REG ( op ) ) && ( GET_MODE ( SUBREG_REG ( op ) ) == DImode || GET_MODE ( SUBREG_REG ( op ) ) == TImode || GET_MODE ( SUBREG_REG ( op ) ) == PTImode || GET_MODE ( SUBREG_REG ( op ) ) == DDmode || GET_MODE (

SUBREG_REG ( op ) ) == TDmode ) ) return true ;


<s> VLIWMachineScheduler ( MachineSchedContext * C ,


<s> bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasF128 . clear (


<s> static bool isIntraBin ( const MachineInstr & MI ,


<s> EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; updateValueMap ( I , SrcReg ) ; return true


<s> if ( SDNode * Dest = isBLACompatibleAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ; needIndirectCall = false ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( ! DAG . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isJITCodeModel ( ) ) { unsigned OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && <ISA_LIT>SubTarget . getDarwinVers ( ) < <NUM_LIT> && ( G -> getGlobal ( ) -> isDeclaration ( ) || G -> getGlobal ( ) -> isWeakForLinker ( ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , Callee . getValueType ( ) , <NUM_LIT> , OpFlags ) ; needIndirectCall = false ; } } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && <ISA_LIT>SubTarget . getDarwinVers ( ) < <NUM_LIT> ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl


<s> if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( M . getModuleFlag ( <STR_LIT> ) ) ) { StringRef ModuleABIName = ModuleTargetABI -> getString ( ) ; if ( ! ABIName . empty ( ) && ModuleABIName != ABIName ) report_fatal_error ( <STR_LIT> ) ; if ( ABIName . empty ( ) ) Options .

MCOptions . ABIName = ModuleABIName . str ( ) ;


<s> DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( isVSFRCRegClass ( RC ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else { DestReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg )


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & C , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . useCRBits ( ) ? <STR_LIT>


<s> int RegNum = - <NUM_LIT> ; APInt IntVal ( <NUM_LIT> , - <NUM_LIT> ) ; if ( ! DefSymbol . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) ) RegNum = matchRegisterByNumber ( IntVal . getZExtValue ( ) , is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; else { switch ( Kind ) { case <STR_LIT> : case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) , FP_FORMAT_D ) ; break ; case <STR_LIT> : RegNum = matchFPURegisterName ( DefSymbol . substr ( <NUM_LIT> ) , FP_FORMAT_S ) ; break ; case <STR_LIT> : case <STR_LIT> : default : RegNum = matchRegisterName ( DefSymbol . substr ( <NUM_LIT> ) , is<ISA_LIT>64 ( ) ) ; break ; } } if ( RegNum > - <NUM_LIT> ) { Parser . Lex ( ) ; <ISA_LIT>Operand * op = <STR_LIT> ( RegNum , S , Parser . getTok ( ) . getLoc ( ) ) ; op -> setRegKind ( Kind


<s> if ( isGPR ( reg ) && ! ( I -> mayLoad ( ) && ! opcount ) ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg ( reg ) ) ; MBB -> insert ( I , cmpInst ) ; MachineInstr * MItest = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( ErrorBB ) ; MBB -> insert ( I


<s> void <ISA_LIT>AsmPrinter :: lowerImageHandleSymbol ( unsigned Index , MCOperand & MCOp ) { TargetMachine & TM = const_cast < TargetMachine & > ( MF -> getTarget ( ) ) ; <ISA_LIT>TargetMachine & nvTM = static_cast < <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const char * Sym = MFI ->


<s> sprintf ( buf , <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; section = buf ; } switch_to_section ( get_section ( section , <NUM_LIT> , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT ,


<s> memcpy ( have_regs_of_mode , m_old_have_regs_of_mode , sizeof ( have_regs_of_mode ) ) ; maximum_field_alignment =


<s> if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == TgtReg && ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT>

) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) {


<s> void <ISA_LIT>TargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned EFlags = MCA


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal


<s> R600ControlFlowFinalizer ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( <NUM_LIT> ) , TRI ( <NUM_LIT> ) , ST ( tm . getSubtarget < AMDGPUSubtarget > ( ) ) { const AMDGPUSubtarget & ST = tm . getSubtarget < AMDGPUSubtarget > ( ) ; MaxFetchInst = ST . getTexVTXClauseSize (


<s> DecodeStatus S = MCDisassembler :: Success ; const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ( RegNo == <NUM_LIT> && ! featureBits [ <STR_LIT> ] ) || RegNo == <NUM_LIT>


<s> unsigned getSORegImmOpValue ( const MachineInstr &


<s> maybeCompressInstr ( prevInst , true ) ; Out . EmitInstruction ( prevInst , STI ) ; flushPendingLabels ( Out ) ; maybeCompressInstr ( Inst , true ) ; Out . EmitInstruction ( Inst , STI ) ; pInst = nullptr ; } else { flushPendingLabels ( Out ) ; prevInst = Inst ; pInst = & prevInst


<s> static void report_neither_nor ( location_t location , tree fndecl , unsigned int argno , HOST_WIDE_INT actual ,


<s> bool hasNegativeScratchOffsetBug ( )


<s> return * ( RegInfo -> getRegClass ( RC


<s> return riscv_address_insns ( addr , mode ,


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , false ) ; if ( ! handleAssignments ( MIRBuilder , OutArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , InArgs , Handler ) ) return false ; } if ( Info . SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( Info . SwiftErrorVReg , Register ( <STR_LIT> ) ) ; } uint64_t CalleePopBytes = doesCalleeRestoreStack ( Info . CallConv , MF . getTarget ( ) .

Options . GuaranteedTailCallOpt ) ? alignTo ( Handler . StackSize , <NUM_LIT> ) : <NUM_LIT> ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; MCContext & Ctx = Asm . getContext ( ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; Value = adjustFixupValue ( Fixup , Target , Value , Ctx , TheTriple , IsResolved ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes ( Fixup . getKind ( ) ) ; if ( FulleSizeInBytes == <NUM_LIT>


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . OffsetRegNum ) return false ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( ( Val & <NUM_LIT> ) == <NUM_LIT> )

) || Val == std :: numeric_limits < int32_t > :: min ( ) ;


<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT FloatTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : FloatTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT


<s> return ( uint16x4_t ) __builtin_neon_vcgtv4hi ( __b ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { return makeAddress ( Op , DAG


<s> static const TargetRegisterClass * getMinClassForRegBank ( const RegisterBank & RB , unsigned SizeInBits , bool GetAllRegSet = false ) { unsigned RegBankID = RB . getID ( ) ; if ( RegBankID == <STR_LIT> ) { if ( SizeInBits <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> :


<s> if ( TARGET_FMA ) { x = validize_mem ( force_const_mem ( SFmode , x ) ) ; fp_hi = gen_rtx_FMA ( SFmode , fp_hi , x , fp_lo ) ; emit_move_insn ( target , fp_hi ) ; } else { fp_hi = expand_simple_binop ( SFmode , MULT , fp_hi , x , fp_hi , <NUM_LIT> , OPTAB_DIRECT ) ; fp_hi = expand_simple_binop ( SFmode , PLUS , fp_hi , fp_lo , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( ! rtx_equal_p ( target , fp_hi ) ) emit_move_insn ( target ,


<s> std :: vector < GlobalAlias * > AliasesToRemove ; std :: vector < Function * > FuncsToClone ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( Function & F : M ) { if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone


<s> void <ISA_LIT>TargetLowering :: addQRTypeForNEON ( MVT VT ) { addRegisterClass ( VT ,


<s> } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } Error ( Loc , <STR_LIT> ) ; return false ; case IS_VGPR : case IS_SGPR : case IS_AGPR : case IS_TTMP : if ( Reg1 != Reg + RegWidth / <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return false ; } RegWidth += <NUM_LIT> ; return true


<s> static DecodeStatus DecodePowerTwoOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; if ( Val < MinLog || Val > MaxLog ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> << Val ) ) ; return S


<s> ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; return


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false ,


<s> State = IES_GT ; IC . pushOperator ( IC_GT ) ; break ; } PrevState = CurrState


<s> i = __builtin_spe_mfspefscr ( ) ; i &= ~ __SPEFSCR_FRMC ; i |= rnd ; __builtin_spe_mtspefscr (


<s> if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && ( LastMI -> mayLoad ( ) || LastMI -> mayStore ( ) ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = std :: prev ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TII . getRegisterInfo


<s> inline static <STR_LIT> A64StringToCondCode ( StringRef CondStr ) { return StringSwitch < <STR_LIT> > ( CondStr . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) .

Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ; SupportsDebugInformation = true


<s> spu_builtin_types [ SPU_BTI_INTDI ] = global_trees [ TI_INTDI_TYPE ] ; spu_builtin_types [ SPU_BTI_UINTQI ] = global_trees [ TI_UINTQI_TYPE ] ; spu_builtin_types [ SPU_BTI_UINTHI ] = global_trees [ TI_UINTHI_TYPE ] ; spu_builtin_types [ SPU_BTI_UINTSI ] = global_trees [ TI_UINTSI_TYPE ] ; spu_builtin_types [ SPU_BTI_UINTDI ] = global_trees [ TI_UINTDI_TYPE ] ; spu_builtin_types [ SPU_BTI_FLOAT ] = global_trees [ TI_FLOAT_TYPE ] ; spu_builtin_types [ SPU_BTI_DOUBLE ] = global_trees [ TI_DOUBLE_TYPE ] ; spu_builtin_types [ SPU_BTI_VOID ] = global_trees [ TI_VOID_TYPE ] ; spu_builtin_types [ SPU_BTI_PTR ] = build_pointer_type ( build_qualified_type ( void_type_node , TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE ) ) ; for ( i = <NUM_LIT> , d = spu_builtins ; i < NUM_SPU_BUILTINS ; i ++ , d ++ ) { tree p ; char name [ <NUM_LIT> ] ; int parm ; if ( d -> name == <NUM_LIT> ) continue ; for ( parm = <NUM_LIT> ; d -> parm [ parm ] != SPU_BTI_END_OF_PARAMS ; parm ++ ) ; p = void_list_node ; while ( parm > <NUM_LIT> ) p = tree_cons ( NULL_TREE , spu_builtin_types [ d -> parm [ -- parm ] ] , p ) ; p = build_function_type ( spu_builtin_types [ d -> parm [ <NUM_LIT> ] ] , p ) ; sprintf ( name , <STR_LIT> , d -> name


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode ,


<s> case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MRI , MF ) ; case TargetOpcode :: G_CONSTANT : return selectConstant ( I , MRI , MF ) ; case TargetOpcode :: G_FCONSTANT : return materializeFP ( I , MRI , MF ) ; case TargetOpcode :: G_PTRTOINT : case TargetOpcode :: G_TRUNC : return selectTruncOrPtrToInt ( I , MRI , MF ) ; case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_MERGE_VALUES : return selectMergeValues ( I , MRI , MF , CoverageInfo ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode :: G_PHI : return selectImplicitDefOrPHI ( I , MRI ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return selectShift ( I , MRI , MF ) ; case TargetOpcode :: G_SDIV


<s> bool <ISA_LIT>MCChecker :: checkBranches ( ) { <ISA_LIT>MCErrInfo errInfo ; if ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) { bool hasConditional = false ; unsigned Branches = <NUM_LIT> , Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE , Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE ; for ( unsigned i = <ISA_LIT>MCInstrInfo :: bundleInstructionsOffset ; i < MCB . size ( ) ; ++ i ) { MCInst const & MCI = * MCB . begin ( ) [ i ] . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( MCI ) ) continue ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isCall ( ) ) { ++ Branches ; if ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) { hasConditional = true ; Conditional = i ; } else


<s> SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( Op , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( Op , DAG , Has<ISA_LIT>64 ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( Op , DAG , <STR_LIT> , <STR_LIT> ) ; return getAddrGlobal ( Op , DAG , Has<ISA_LIT>64 ? <STR_LIT>


<s> getNumDecoderSlots ( SUnit * SU ) const { const MCSchedClassDesc * SC = DAG -> getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; if ( SC -> BeginGroup ) { if ( ! SC -> EndGroup ) return <NUM_LIT> ; else return


<s> return real_equal ( r , & dconst0 ) &&


<s> case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op ,


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; bool Changed = false ; SmallVector < int , <NUM_LIT> > MaskVec ; SVOp -> getMask ( MaskVec ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i


<s> assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const MachineOperand & DestReg = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & BaseReg = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Scale = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>AnnotateControlFlow :: isTopOfStack ( BasicBlock * BB ) { return ! Stack . empty ( ) && Stack


<s> if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p )


<s> if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CompareOpcode ) ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( KeepOldMask ) . addMBB ( UpdateMBB ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB -> addSuccessor ( UseAltMBB ) ; MBB = UseAltMBB ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedAltVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB = UpdateMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addMBB ( LoopMBB ) . addReg ( RotatedAltVal ) . addMBB ( UseAltMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . add ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MI . eraseFromParent ( ) ; return DoneMBB


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveCode ( StringRef IDVal , SMLoc L ) { if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is16BitMode ( ) ) { SwitchMode ( <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ; } } else if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; if ( ! is32BitMode ( ) ) { SwitchMode (


<s> rtx t1 = arc_delegitimize_address_0 ( XEXP ( op , <NUM_LIT> ) ) ; rtx t2 = XEXP ( op , <NUM_LIT> ) ; if ( t1 && t2 ) return gen_rtx_PLUS ( GET_MODE ( op ) , t1 , t2 ) ; break ; } default : break ; } return NULL_RTX


<s> return ( __mmask32 ) __builtin_ia32_kaddsi ( ( __mmask32 ) __A ,


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * <ISA_LIT>SubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( <ISA_LIT>Lowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == <STR_LIT> ) { if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { GlobalBaseReg = <STR_LIT> ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define


<s> if ( OutStreamer . hasRawTextSupport ( ) ) return ; Subtarget -> getMReginfo ( ) . emit<ISA_LIT>ReginfoSectionCG ( OutStreamer , getObjFileLowering ( ) ,


<s> SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode ::


<s> else cr = gen_reg_rtx ( cmpmode ) ; rtx label_ref = gen_rtx_LABEL_REF ( VOIDmode , true_label ) ; if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref ,


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return SDValue ( ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> ; if ( ! IsSigned && DstTy != <STR_LIT> ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getStoreSize ( ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( MemSize , Align ( MemSize ) , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; EVT ResVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) ; SDValue Cmp ; if ( IsStrict ) { Cmp = DAG . getSetCC ( DL , ResVT , Value , ThreshVal , <STR_LIT> , Chain , true ) ; Chain = Cmp . getValue ( <NUM_LIT> ) ; }


<s> } else { if ( TREE_CODE ( * node ) == FUNCTION_TYPE || TREE_CODE ( * node ) == METHOD_TYPE ) { if ( arm_isr_value ( args ) == ARM_FT_UNKNOWN ) { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ; } } else if ( TREE_CODE ( * node ) == POINTER_TYPE && ( TREE_CODE ( TREE_TYPE ( * node ) ) == FUNCTION_TYPE || TREE_CODE ( TREE_TYPE ( * node ) ) == METHOD_TYPE ) && arm_isr_value ( args ) != ARM_FT_UNKNOWN ) { * node = build_variant_type_copy ( * node ) ; TREE_TYPE ( * node ) = build_type_attribute_variant ( TREE_TYPE ( * node ) , tree_cons ( name , args , TYPE_ATTRIBUTES ( TREE_TYPE ( * node ) ) ) ) ; * no_add_attrs = true ; } else { if ( flags & ( ( int ) ATTR_FLAG_DECL_NEXT | ( int ) ATTR_FLAG_FUNCTION_NEXT | ( int ) ATTR_FLAG_ARRAY_NEXT ) ) { * no_add_attrs = true ; return tree_cons ( name , args , NULL_TREE


<s> SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceUses ( N , Result_3 ) ; return Result_3 ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDNode * RsPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; ReplaceUses ( N , RsPd ) ; return RsPd ; } assert ( <NUM_LIT> && <STR_LIT> ) ; } } return SelectCode (


<s> MemSDNode * MN = cast < MemSDNode > ( N ) ; unsigned AS = MN -> getAddressSpace ( ) ; if ( OldSize >= <NUM_LIT> && NewSize < <NUM_LIT> && MN -> getAlignment ( ) >= <NUM_LIT> && ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || ( isa < LoadSDNode > ( N ) && AS == <ISA_LIT>AS :: GLOBAL_ADDRESS && MN -> isInvariant ( ) ) ) && <ISA_LIT>InstrInfo :: isUniformMMO

( MN -> getMemOperand ( ) ) ) return false ;


<s> if ( Info -> getFrameOffsetReg ( ) != <STR_LIT> ) MRI . replaceRegWith ( <STR_LIT> , Info -> getFrameOffsetReg ( ) ) ; Info -> limitOccupancy ( MF ) ; if ( ST . isWave32 ( ) && ! MF . empty ( ) ) { for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { TII -> fixImplicitOperands ( MI ) ; } } } if ( ST . needsAlignedVGPRs ( ) ) { for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { const Register Reg = Register :: index2VirtReg ( I ) ; const TargetRegisterClass * RC = MRI . getRegClassOrNull ( Reg ) ; if ( ! RC ) continue ; int NewClassID = getAlignedAGPRClassID ( RC -> getID ( ) ) ; if ( NewClassID != - <NUM_LIT> ) MRI . setRegClass ( Reg , TRI -> getRegClass ( NewClassID ) ) ; } } TargetLoweringBase :: finalizeLowering ( MF


<s> return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_3 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_4 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_5 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_32 : case llvm :: ELF :: EF_MIPS_ARCH_32R2 : case llvm :: ELF :: EF_MIPS_ARCH_32R6 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_64 : case llvm :: ELF :: EF_MIPS_ARCH_64R2 : case llvm :: ELF ::


<s> return Subtarget -> isTargetDarwin ( ) ? LowerDarwin_VASTART ( Op , DAG ) :


<s> static void arm_option_restore ( struct gcc_options *


<s> va_start ( ap , format ) ; ( void ) vsnprintf ( buffer , sizeof (


<s> else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) D_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) T_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) O_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_FLOAT : case MODE_COMPLEX_FLOAT : if ( GET_MODE_SIZE ( i ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) DF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) TF_MODE ; else if ( GET_MODE_SIZE ( i ) == <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) OF_MODE ; else arc_mode_class [ i ] = <NUM_LIT> ; break ; case MODE_CC : arc_mode_class [ i ] = <NUM_LIT> << ( int ) C_MODE ; break ; default : arc_mode_class [ i ]


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCRegisterInfo & MRI


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE ->


<s> void <ISA_LIT>TargetAsmStreamer :: emitCCTopFunction ( StringRef Name ) { OS <<


<s> if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; Ops . push_back ( Inc ) ; } Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; SmallVector < EVT , <NUM_LIT> > ResTys ; if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( VT ) ; else if ( NumVecs == <NUM_LIT> ) ResTys . push_back ( <STR_LIT> ) ; else { EVT ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , is64BitVector ? NumVecs : NumVecs * <NUM_LIT> ) ; ResTys . push_back ( ResTy ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDLoc dl ( N ) ; SDNode * VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo


<s> bool AMDGPUDAGToDAGISel :: SelectGlobalValueVariableOffset ( SDValue Addr , SDValue & BaseReg , SDValue & Offset ) { if ( ! isa < ConstantSDNode > ( Addr ) ) { BaseReg = Addr


arm_lang_output_object_attributes_hook ( ) ;


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum

) . getImm ( ) << markup ( <STR_LIT> ) ;


<s> rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( <STR_LIT> ) ) ; set_new_first_and_last_insn ( NULL , NULL ) ; machine_mode mode ; FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_INT ) \ { \ if ( riscv_v_ext_vector_mode_p ( mode ) ) \ { \ rtx_insn * insn ; \ rtx src ; \ scalar_mode inner_mode = GET_MODE_INNER ( mode ) ; \ \ start_sequence ( ) ; \ rtx addr = gen_reg_rtx ( Pmode ) ; \ rtx mem = gen_rtx_MEM ( inner_mode , addr ) ; \ expand_vector_broadcast ( mode , mem ) ; \ insn = get_last_insn ( ) ; \ src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; \ ASSERT_TRUE ( MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) ; \ ASSERT_TRUE ( \ rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; \ end_sequence ( ) ; \ \ start_sequence ( ) ; \ rtx reg = gen_reg_rtx ( inner_mode ) ; \ expand_vector_broadcast ( mode , reg ) ; \ insn = get_last_insn

( ) ; \ src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; \ ASSERT_TRUE ( REG_P ( XEXP ( src , <NUM_LIT> ) ) ) ; \ ASSERT_TRUE ( \ rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; \ end_sequence ( ) ; \ }


<s> const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( create<ISA_LIT>IndirectThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( create<ISA_LIT>AvoidTrailingCallPass ( ) ) ; if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ; if ( TT . isOSWindows ( ) ) addPass


<s> while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) )


<s> if ( IsMasked ( & I ) ) { FixedVectorType * VecTy = getVectorType ( cast < IntrinsicInst > ( & I ) ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; } else if ( auto * Int = dyn_cast < IntrinsicInst > ( & I ) ) { if ( Int -> getIntrinsicID ( ) == <STR_LIT> ) continue ; for ( auto & U : Int


<s> switch ( RelTy ) { case ELF :: R_MICROBLAZE_32_PCREL : case ELF :: R_MICROBLAZE_64_PCREL : case ELF :: R_MICROBLAZE_32_PCREL_LO : case ELF


<s> bool <ISA_LIT>InstructionSelector :: selectShift ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_SHL || I . getOpcode ( ) == TargetOpcode :: G_ASHR || I . getOpcode ( ) == TargetOpcode :: G_LSHR ) && <STR_LIT> ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const static struct ShiftEntry { unsigned SizeInBits ; unsigned OpLSHR ; unsigned OpASHR ; unsigned OpSHL ; } OpTable [ ] = { { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; if ( DstRB . getID ( )


<s> LLT NewTy = LLT :: scalar ( <NUM_LIT> ) ; Register PtrReg = Store . getPointerReg ( ) ; auto Zero = B . buildConstant ( NewTy , <NUM_LIT> ) ; auto HighPtr = B . buildPtrAdd ( MRI . getType ( PtrReg ) , PtrReg , B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) ) ; auto & MF = * MI . getMF ( ) ; auto * LowMMO = MF . getMachineMemOperand ( & Store . getMMO ( ) , <NUM_LIT> , NewTy ) ; auto * HighMMO = MF . getMachineMemOperand ( & Store . getMMO ( ) , <NUM_LIT> , NewTy ) ; B . buildStore ( Zero , PtrReg , *


<s> Flags . setOrigAlign ( DL . getABITypeAlignment ( CurOrigArg -> getType ( ) ) ) ; if ( F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS && ! OrigArg . Flags . isInReg ( ) && ! OrigArg . Flags . isByVal ( ) && P<ISA_LIT>nputNum <= <NUM_LIT> ) { if ( CurOrigArg -> use_empty ( ) && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ) { Skipped . set ( i ) ; ++ P<ISA_LIT>nputNum ; continue ; } Info -> markP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ! CurOrigArg -> use_empty ( ) ) Info -> markP<ISA_LIT>nputEnabled ( P<ISA_LIT>nputNum ) ; ++ P<ISA_LIT>nputNum ; } CCAssignFn * AssignFn = CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; if ( ValEVT . isVector ( ) ) { EVT ElemVT = ValEVT . getVectorElementType ( ) ; if ( ! ValEVT . isSimple ( ) ) return false ; MVT ValVT = ElemVT . getSimpleVT ( ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , OrigArg . Flags , CCInfo ) ; if ( ! Res ) return false ; } else { MVT ValVT = ValEVT . getSimpleVT ( ) ; if ( ! ValEVT . isSimple ( ) ) return false ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , OrigArg . Flags , CCInfo ) ; if ( Res ) return false ; } } Function :: const_arg_iterator Arg = F . arg_begin ( ) ; if ( F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_VS || F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ) { for ( unsigned i = <NUM_LIT> , OrigArgIdx = <NUM_LIT> ; OrigArgIdx != NumArgs && i != ArgLocs . size ( ) ; ++ Arg , ++ OrigArgIdx ) { if ( Skipped . test ( OrigArgIdx ) ) continue ; CCValAssign & VA = ArgLocs [ i ++ ] ; MRI . addLiveIn ( VA . getLocReg ( ) , VRegs [ OrigArgIdx ] ) ; MIRBuilder . getMBB ( ) . addLiveIn ( VA . getLocReg ( ) ) ; MIRBuilder . buildCopy ( VRegs [ OrigArgIdx ]


<s> CallingConv :: ID CC = TLI . getLibcallCallingConv ( Call ) ; if ( FuncInfo . MF -> getFunction ( ) . isPagerando ( ) ) return false ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , false ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( I -> getNumOperands ( ) ) ; ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( Value * Op : I -> operands


<s> if ( ReduceMI ( MBB , MI , LiveCPSR , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = std :: prev ( NextMII ) ; MI = & * I ; if ( NextInSameBundle && ! NextMII -> isBundledWithPred ( ) ) NextMII -> bundleWithPred ( ) ; } if ( ! NextInSameBundle && MI -> isInsideBundle ( ) ) { if ( BundleMI -> killsRegister ( <STR_LIT> ) ) LiveCPSR = false ; MachineOperand * MO = BundleMI -> findRegisterDefOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isDead ( ) ) LiveCPSR = true ; MO = BundleMI -> findRegisterUseOperand ( <STR_LIT> ) ; if ( MO && ! MO -> isKill ( ) ) LiveCPSR = true ; } bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> isCall ( ) ) { CPSRDef = nullptr ; HighLatencyCPSR = false ; IsSelfLoop = false


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedInt < N - <NUM_LIT> ,


<s> assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Offset ; if ( MFI -> LocalMemoryObjects . count ( GV ) == <NUM_LIT> ) { uint64_t Size = TD -> getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; Offset = MFI -> LDSSize ; MFI -> LocalMemoryObjects [ GV ] = Offset ; MFI -> LDSSize += Size ; } else { Offset = MFI -> LocalMemoryObjects [ GV ] ; } return DAG . getConstant ( Offset , getPointerTy ( G -> getAddressSpace ( ) ) ) ; } case <STR_LIT> : { MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; Type * EltType = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypeAllocSize ( EltType ) ; unsigned Alignment = TD -> getPrefTypeAlignment ( EltType ) ; const GlobalVariable * Var = cast < GlobalVariable > ( GV ) ; const Constant * Init = Var -> getInitializer ( ) ; int FI = FrameInfo -> CreateStackObject ( Size , Alignment , false ) ; SDValue InitPtr = DAG . getFrameIndex ( FI , getPointerTy ( <STR_LIT> ) ) ; SmallVector < SDNode * , <NUM_LIT> > WorkList ; for ( SDNode :: use_iterator I = DAG . getEntryNode ( ) -> use_begin ( ) , E = DAG . getEntryNode ( ) -> use_end


<s> unsigned e = static_cast < unsigned > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> ( e


<s> const Module * M = MMI -> getModule ( ) ; for ( const Function & F : M -> functions ( ) ) { const DISubprogram * SP = F . getSubprogram ( ) ; if ( ! SP || SP -> isDefinition ( ) ) continue ; uint32_t ProtoTypeId ; const std :: unordered_map < uint32_t


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; MCFixupKind FixupKind = static_cast < MCFixupKind > ( <STR_LIT> ) ; unsigned Offset = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> ) { FixupKind = FK_Data_2 ; Offset = <NUM_LIT> ; } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { switch ( MI .


<s> unsigned int __w = ( unsigned char ) __b << <NUM_LIT> | ( unsigned char ) __b ; unsigned int __i = __w << <NUM_LIT> | __w ; return _mm_set1_pi32 ( __i


<s> static int round_frame_size ( int size ) { return ( ( size + STACK_BOUNDARY / BITS_PER_UNIT - <NUM_LIT> ) & - STACK_BOUNDARY /


<s> if ( ent == NULL ) return NULL ; else return ( void * ) ( segment_base +


<s> return isThumb ( STI ) && ( STI . getFeatureBits ( ) & <STR_LIT> )


<s> unsigned regno = store_order [ i ] ; if ( ( ( mask >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) continue ; ++ count ; x = plus_constant ( Pmode , stack_pointer_rtx , count * - <NUM_LIT> ) ; x = gen_frame_mem ( SImode , x ) ; x = gen_rtx_SET ( x , gen_rtx_REG ( SImode , regno ) ) ; elts [ count ] = F ( x ) ; mask &= ~ ( <NUM_LIT> << regno ) ; } gcc_assert ( mask


<s> return ( poly64x2_t ) __builtin_neon_vextv2di ( ( int64x2_t ) __a , ( int64x2_t )


<s> if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; } else { int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) EmitAlignment ( <NUM_LIT> ) ; printInstruction ( MI )


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; Spill . FullyAllocated = true ; BitVector OtherUsedRegs ; OtherUsedRegs . resize ( TRI -> getNumRegs ( ) ) ; const uint32_t * CSRMask = TRI -> getCallPreservedMask ( MF , MF . getFunction ( ) . getCallingConv ( ) ) ; if ( CSRMask ) OtherUsedRegs . setBitsInMask ( CSRMask ) ; for ( MCPhysReg Reg : SpillAGPR ) OtherUsedRegs . set ( Reg ) ; for ( MCPhysReg Reg : SpillVGPR ) OtherUsedRegs . set ( Reg ) ; SmallVectorImpl < MCPhysReg > :: const_iterator NextSpillReg = Regs . begin ( ) ; for ( int I = NumLanes - <NUM_LIT> ; I >= <NUM_LIT> ; -- I ) { NextSpillReg = std :: find_if ( NextSpillReg , Regs . end ( ) , [ & MRI , & OtherUsedRegs ] ( MCPhysReg Reg ) { return MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) && ! OtherUsedRegs [ Reg ] ; } )


<s> PendingBA -> setLastFragment ( CF ) ; PendingBA = nullptr ; if ( isa_and_nonnull < MCDataFragment > ( CF ) ) OS . insert ( new MCDataFragment ( ) ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ; if ( AlignBoundary . value ( ) > Sec -> getAlignment ( ) ) Sec


<s> for ( auto & I : * BB ) { if ( I . mayWriteToMemory ( ) ) Writes . push_back ( & I ) ; auto * Ld = dyn_cast < LoadInst > ( & I ) ; if ( ! Ld || ! Ld -> isSimple ( ) || ! Ld -> hasOneUse ( ) || ! isa < SExtInst > ( Ld -> user_back ( ) ) ) continue ; Loads . push_back ( Ld ) ; } using InstSet = std :: set < Instruction * > ; using DepMap = std :: map < Instruction * , InstSet > ; DepMap RAWDeps ; const auto Size = LocationSize :: unknown ( ) ; for ( auto Read : Loads ) { for ( auto Write : Writes ) { MemoryLocation ReadLoc = MemoryLocation ( Read -> getPointerOperand ( ) , Size ) ; if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( DT -> dominates ( Write , Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) { LoadInst * Dominator = DT -> dominates ( Base , Offset )


<s> setCC ( <STR_LIT> , Builder -> CreateICmpEQ ( LHS , RHS ) ) ; setCC ( <STR_LIT> , Builder -> CreateICmpNE ( LHS , RHS ) ) ; return computeEFLAGSForDef ( Builder -> CreateSub ( LHS , RHS ) , OldEFLAGS ) ; } else { setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpUEQ ( LHS , RHS ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpUNO ( LHS , RHS ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpULT (


<s> return pcum -> aapcs_partial ; } if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( arg . mode ) ) return <NUM_LIT> ; if ( NUM_ARG_REGS > nregs && ( NUM_ARG_REGS < nregs + ARM_NUM_REGS2 ( arg . mode , arg . type ) ) && pcum -> can_split ) return ( NUM_ARG_REGS - nregs ) * UNITS_PER_WORD ; return


<s> if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Op . getImm ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Op . getImm ( ) ) ) { const <ISA_LIT>MCExpr * LHSSymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ; return ( LHSSymbolRefExpr && LHSSymbolRefExpr -> getKind ( )

== <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ;


<s> machine_mode mode2 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( VECTOR_MODE_P ( mode2 ) ) op2 = safe_vector_operand ( op2 , mode2 ) ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; if ( builtin_sha1cpm_p ) op3 = GEN_INT ( TARGET_BIG_END ? <NUM_LIT> :


<s> Function * FreeF = M . getFunction ( <STR_LIT> ) ; if ( Callee == SetjmpF || Callee == MallocF || Callee == FreeF ) return false ; if ( Callee == ResumeF || Callee == EHTypeIDF || Callee == SaveSetjmpF || Callee == TestSetjmpF ) return false ; if ( Callee -> getName ( ) . startswith ( FindMatchingCatchPrefix ) ) return false ; Function * BeginCatchF = M . getFunction ( <STR_LIT> ) ; Function * EndCatchF = M . getFunction ( <STR_LIT> ) ; Function * AllocExceptionF = M . getFunction ( <STR_LIT> ) ; Function * ThrowF = M . getFunction ( <STR_LIT> ) ; Function * TerminateF = M . getFunction ( <STR_LIT> ) ; if ( Callee == BeginCatchF || Callee == EndCatchF || Callee == AllocExceptionF || Callee == ThrowF || Callee == TerminateF ) return false ; return true


<s> if ( MemOpIndex + <NUM_LIT> >= Desc . getNumOperands ( ) ) return None ; const MCOperand & MO1 = Inst . getOperand ( MemOpIndex ) ; const MCOperand & MO2 = Inst . getOperand ( MemOpIndex + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) || MO1 . getReg ( ) != <STR_LIT> || ! MO2 . isImm ( ) ) return None ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; <STR_LIT> Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Op == <STR_LIT> ) return Addr -


<s> if ( strcmp ( name , sec -> name ) == <NUM_LIT> ) return ; sec = sec -> next ; } new_section = ( arc_jli_section * ) xmalloc ( sizeof ( arc_jli_section ) ) ; gcc_assert ( new_section != NULL ) ; new_section -> name = name ; new_section -> next =


<s> TruncTysMap [ ZExt ] = TruncTysMap [ V ] ; } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto V : Sources ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) InsertZExt ( I , I ) ; else if ( auto * Arg = dyn_cast < Argument > ( V ) ) { BasicBlock & BB = Arg -> getParent ( ) -> front ( ) ; InsertZExt ( Arg , & * BB . getFirstInsertionPt ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Promoted . insert ( V ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; auto * I = cast < Instruction > ( V ) ; if ( Sinks . count ( I ) ) continue ; for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Op = I -> getOperand ( i ) ; if ( ( Op -> getType ( ) == ExtTy ) || ! isa < IntegerType > ( Op -> getType ( ) ) ) continue ; if ( auto * Const = dyn_cast < ConstantInt > ( Op ) ) FixConst ( Const , I ) ; else if ( isa < UndefValue > ( Op ) ) I -> setOperand ( i , UndefValue :: get ( ExtTy ) ) ; } if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I ) ; } } for ( auto * V : Visited ) { if ( Sources . count ( V ) ) continue ; if ( ! shouldPromote ( V ) || isPromotedResultSafe ( V ) ) continue ; assert ( EnableDSP && <STR_LIT> ) ; InsertDSPIntrinsic ( cast < Instruction > ( V ) ) ; } auto InsertTrunc = [ & ] ( Value * V ) -> Instruction * { if ( ! isa < Instruction > ( V ) || ! isa < IntegerType > ( V -> getType ( ) ) ) return nullptr ; if ( ( ! Promoted . count ( V ) && ! NewInsts . count ( V ) ) || ! TruncTysMap . count ( V ) || Sources . count ( V ) ) return nullptr ; Type * TruncTy = TruncTysMap [ V ] ; if ( TruncTy == ExtTy ) return


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) << std :: setfill ( '0' ) << ( unsigned ) (

Binary >> <NUM_LIT> ) << std :: dec << <STR_LIT> ;


<s> if ( CopyBuffer && CopyBufferFirst ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchRsrcReg ) . addReg ( PreloadedPrivateBufferReg , RegState :: Kill ) ; } if ( OffsetRegUsed && PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ; } if ( CopyBuffer && ! CopyBufferFirst ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchRsrcReg ) . addReg ( PreloadedPrivateBufferReg , RegState :: Kill ) ; } if ( ResourceRegUsed && ( ST . isMesaGfxShader ( MF ) || ( PreloadedPrivateBufferReg == <STR_LIT> ) ) ) { assert ( ! ST . isAmdCodeObjectV2 ( MF ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; unsigned Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; if ( MFI -> hasPrivateMemoryInputPtr ( ) ) { unsigned Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) -> getCallingConv ( ) ) ) { const MCInstrDesc & Mov64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , Mov64 , Rsrc01 ) . addReg ( PreloadedPrivateBufferReg ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else { const MCInstrDesc & LoadDwordX2 = TII -> get ( <STR_LIT> ) ; PointerType * PtrTy = PointerType :: get ( Type :: getInt64Ty ( MF . getFunction ( ) -> getContext ( ) ) , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , LoadDwordX2 , Rsrc01 ) . addReg ( PreloadedPrivateBufferReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } } else { unsigned Rsrc0 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc1 = TRI -> getSubReg


<s> } } return false ; } switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { const unsigned Offset = State . AllocateStack ( PtrByteSize , PtrByteSize ) ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , RegVT , LocInfo ) ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; const unsigned Offset = State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , <NUM_LIT> ) ; unsigned FReg = State . AllocateReg ( FPR ) ; if ( FReg ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , FReg , LocVT , LocInfo ) ) ; for ( unsigned I = <NUM_LIT> ; I < StoreSize ; I += PtrByteSize ) { if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { assert ( FReg && <STR_LIT> ) ; if ( State . isVarArg ( ) ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; } } else { State . addLoc ( FReg ? CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) : CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; break ; } } return


<s> bool <ISA_LIT>TargetLowering :: shouldConvertPhiType ( Type * From , Type * To ) const { if ( ! Subtarget . is64Bit ( ) )


<s> unsigned BitWidth = Op1 . getValueSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , Log2_32 ( BitWidth ) ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( Op1 , DemandedMask , TLO ) || TLI . SimplifyDemandedBits ( Op1 , DemandedMask , KnownZero , KnownOne , TLO ) ) DCI . CommitTargetLoweringOpt ( TLO ) ; } return SDValue (


<s> else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex (


<s> FeatureBitStack . push_back ( getSTI ( ) . getFeatureBits ( ) ) ; ParserOptionsStack . push_back (


<s> return MCSymbolRefExpr :: create ( getSymbol ( GV ) , MCSymbolRefExpr :: VK_<ISA_LIT>_FUNCTION , OutContext ) ; } return AsmPrinter :: lowerConstant


<s> FunctionPass * llvm :: create<ISA_LIT>MISimplifyPatchablePass


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF ,


<s> IsTopNode = true ; if ( Available . empty ( ) ) return nullptr ; if ( Available . size ( ) == <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ; HazardRec . dumpSU ( * Available . begin ( ) , dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; ) ; return * Available . begin ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ; Available . dump ( HazardRec ) ; ) ; Candidate Best ; for ( auto * SU : Available ) { Candidate c ( SU , HazardRec ) ; if ( Best . SU == nullptr || c < Best ) { Best = c ; DEBUG ( dbgs ( ) << <STR_LIT> ; HazardRec . dumpSU ( Best . SU , dbgs ( ) ) ; if ( Best . GroupingCost != <NUM_LIT> ) dbgs ( ) << <STR_LIT> << Best . GroupingCost ; if ( Best . ResourcesCost != <NUM_LIT> ) dbgs ( ) << <STR_LIT> << Best . ResourcesCost ; dbgs ( ) << <STR_LIT> << Best . SU -> getHeight ( ) ; dbgs ( ) << <STR_LIT> ; ) ; } if ( ! SU -> isScheduleHigh && Best . noCost ( ) ) break ; } assert ( Best . SU !=


<s> if ( CurrentColoring [ SU -> NodeNum ] <= ( int ) DAGSize ) continue ; for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( SuccDep . isWeak ( ) || Succ -> NodeNum >= DAGSize ) continue ; hasSuccessor =


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( TM . getSubtargetImpl ( ) -> isDarwin ( ) && <STR_LIT> ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; SpillsVRS = true ; } else { llvm_unreachable ( <STR_LIT> ) ; } return false


<s> auto InstType = IsHazardInst ( * MI ) ; if ( ! InstType ) return false ; auto IsExpiredFn = [ & IsHazardInst ] ( const MachineInstr & I , int ) { return IsHazardInst ( I ) || ( I . getOpcode ( ) == <STR_LIT> && I . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ! I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } ; auto IsHazardFn = [ InstType , & IsHazardInst ] ( const MachineInstr & I ) { if ( ! I . isBranch ( ) ) return false ; auto IsHazardFn = [ InstType , IsHazardInst ] ( const MachineInstr & I ) { auto InstType2 = IsHazardInst ( I ) ; return InstType2 && InstType != InstType2 ; } ; auto IsExpiredFn = [ InstType , & IsHazardInst ] ( const MachineInstr & I , int ) { auto InstType2 = IsHazardInst ( I ) ; if ( InstType == InstType2 ) return true ; return I . getOpcode ( ) == <STR_LIT> && I . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ! I . getOperand ( <NUM_LIT> ) . getImm ( ) ; } ; return :: getWaitStatesSince ( IsHazardFn , & I , IsExpiredFn ) != std :: numeric_limits < int > :: max ( ) ; } ; if ( :: getWaitStatesSince ( IsHazardFn , MI , IsExpiredFn ) == std :: numeric_limits < int > :: max ( ) ) return false ; const <ISA_LIT>InstrInfo * TII = ST


<s> } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getNumOperands ( ) > <NUM_LIT> ) { const MachineOperand & PossiblePred = MI . getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) ; const MachineOperand & PossiblePol = MI . getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) ; if ( ! PossiblePol . isImm ( ) || ! PossiblePred . isReg ( ) ) return false ; Register PReg = PossiblePred . getReg ( ) ; if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) return false ; const TargetRegisterClass * RC ; if ( PReg . isPhysical ( )


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( Subtarget . hasStandardEncoding ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ; return true


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . hasTinyEncoding ( ) ) return AFI -> isInterruptOrSignalHandler ( )


<s> static BasicBlock :: iterator first_use_of_in_block ( T & Values , BasicBlock * B ) { BasicBlock :: iterator FirstUse = B -> end ( ) , BEnd = B -> end ( ) ; using iterator = typename T :: iterator ; for ( iterator I = Values . begin ( ) , E = Values . end


<s> bool Reg1IsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI . getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == SubReg1 && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MB == <NUM_LIT> && ME == <NUM_LIT> ) return nullptr ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI . getDebugLoc ( ) , MI . getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI . getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI . getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ; } MI . getOperand ( <NUM_LIT> ) . setReg


<s> const int shiftl = ( __N & <NUM_LIT> ) * <NUM_LIT> ; const __m64 shiftD = ( const __m64 ) __D << shiftl ; const __m64 mask = <NUM_LIT> << shiftl ; __m64 result = ( __A & ( ~ mask


<s> MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MI -> eraseFromParent (


<s> virtual unsigned getSOPPBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT>


<s> MAI -> getGlobalDirective ( ) ; O << directive << Sym -> getName ( ) << <STR_LIT> ; O << directive << PAN :: getRetvalLabel ( Sym -> getName ( ) ) << <STR_LIT> ; O << directive << PAN :: getArgsLabel ( Sym -> getName ( ) ) << <STR_LIT> ; } O << MAI -> getCommentString ( ) << <STR_LIT>


<s> int Size = Ty . isSized ( ) ? Ty . getSizeInBits ( ) : <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MI . getNumOperands ( ) ; ++ Idx ) Mapping . setOperandMapping (


<s> void ScheduleDAGPostRA :: observe ( MachineInstr * MI


<s> Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset == INT32_MIN ) { Offset = <NUM_LIT> ; isAdd = false ; } else if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd = false ; } Imm12 = Offset ; } } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm12 , Fixups , STI ) ; uint32_t Binary = Imm12 & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg <<


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) .


<s> static void mips_adjust_block_mem ( rtx mem , HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) { * loop_reg = copy_addr_to_reg ( XEXP ( mem ,


<s> if ( Idx == <STR_LIT> :: SReg_32 ) return getRegPressureLimit ( & <STR_LIT> , const_cast < MachineFunction & > ( MF ) ) ; llvm_unreachable (


<s> static __inline qword si_sfi ( qword a , int b ) { return ( ( qword ) ( vec_sub ( vec_splat ( ( vec_int4 ) ( si_from_int ( b ) ) , <NUM_LIT> )


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSet ( ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) ==


<s> rtx nsse_reg ; int set ; tree fntype ; int stdarg_p ; int i ; if ( ! TARGET_64BIT ) return ; if ( ! cfun -> va_list_gpr_size && ! cfun -> va_list_fpr_size ) return ; ix86_save_varrargs_registers = <NUM_LIT> ; cfun -> stack_alignment_needed = <NUM_LIT> ; fntype = TREE_TYPE ( current_function_decl ) ; stdarg_p = ( TYPE_ARG_TYPES ( fntype ) != <NUM_LIT> && ( TREE_VALUE ( tree_last ( TYPE_ARG_TYPES ( fntype ) ) ) != void_type_node ) ) ; next_cum = * cum ; if ( stdarg_p ) function_arg_advance ( & next_cum , mode , type , <NUM_LIT> ) ; if ( ! no_rtl ) save_area = frame_pointer_rtx ; set = get_varargs_alias_set ( ) ; for ( i = next_cum . regno ; i < ix86_regparm && i < next_cum . regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( save_area , i * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , x86_64_int_parameter_registers [ i ] ) ) ; } if ( next_cum . sse_nregs && cfun -> va_list_fpr_size ) { label = gen_label_rtx ( ) ; label_ref = gen_rtx_LABEL_REF ( Pmode , label ) ; tmp_reg = gen_reg_rtx ( Pmode ) ; nsse_reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_zero_extendqidi2 ( nsse_reg , gen_rtx_REG ( QImode , <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg , gen_rtx_MULT ( Pmode , nsse_reg , GEN_INT ( <NUM_LIT> ) ) ) ) ; if ( next_cum . sse_regno ) emit_move_insn ( nsse_reg , gen_rtx_CONST ( DImode , gen_rtx_PLUS ( DImode , label_ref , GEN_INT ( next_cum . sse_regno * <NUM_LIT> ) ) ) ) ; else emit_move_insn ( nsse_reg , label_ref )


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _addcarryx_u64 ( unsigned char __CF , unsigned long long __X , unsigned long long __Y , unsigned long long * __P ) { return __builtin_ia32_addcarryx_u64 ( __CF , __X , __Y ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CalleeCC ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallerCC ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( Outs . empty ( ) )


<s> return insertVector ( Op . getOperand ( <NUM_LIT> ) , ValV , Op . getOperand ( <NUM_LIT> )


<s> bool Mask = ( Chan != TRI . getHWRegChan ( DstReg ) ) ; unsigned SubDstReg = <STR_LIT> . getRegister ( ( DstBase * <NUM_LIT> ) + Chan ) ; MachineInstr * BMI = TII -> buildSlotOfVectorInstruction ( MBB , & MI , Chan , SubDstReg ) ; if ( Chan > <NUM_LIT> ) { BMI -> bundleWithPred ( ) ; } if ( Mask ) { TII -> addFlag ( * BMI , <NUM_LIT> , MO_FLAG_MASK ) ; } if ( Chan != <NUM_LIT> ) TII -> addFlag ( * BMI , <NUM_LIT> , MO_FLAG_NOT_LAST ) ; unsigned Opcode = BMI -> getOpcode ( ) ; unsigned Src0 = BMI -> getOperand ( TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) ) . getReg ( ) ; unsigned Src1 = BMI -> getOperand ( TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) ) . getReg ( ) ; ( void ) Src0 ; ( void ) Src1 ; if ( ( TRI . getEncodingValue ( Src0 ) & <NUM_LIT> ) < <NUM_LIT> && ( TRI . getEncodingValue ( Src1 ) & <NUM_LIT> ) < <NUM_LIT> ) assert ( TRI . getHWRegChan ( Src0 ) == TRI . getHWRegChan ( Src1 ) ) ; } MI . eraseFromParent ( ) ; continue ; } } bool IsReduction = TII -> isReductionOp ( MI . getOpcode ( ) ) ; bool IsVector = TII -> isVector ( MI ) ; bool IsCube = TII -> isCubeOp ( MI . getOpcode ( ) ) ; if ( ! IsReduction && ! IsVector && ! IsCube ) { continue ; } for ( unsigned Chan = <NUM_LIT> ; Chan < <NUM_LIT> ; Chan ++ ) { unsigned DstReg = MI . getOperand ( TII -> getOperandIdx ( MI , <STR_LIT> :: dst ) ) . getReg ( ) ; unsigned Src0 = MI . getOperand ( TII -> getOperandIdx ( MI , <STR_LIT> :: src0 ) ) . getReg ( ) ; unsigned Src1 = <NUM_LIT> ; if ( ! IsCube ) { int Src1Idx = TII -> getOperandIdx ( MI , <STR_LIT> :: src1 ) ; if ( Src1Idx != - <NUM_LIT> ) { Src1 = MI . getOperand ( Src1Idx ) . getReg ( ) ; } } if ( IsReduction ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Chan ) ; Src0 = TRI . getSubReg ( Src0 , SubRegIndex ) ; Src1 = TRI . getSubReg ( Src1 , SubRegIndex ) ; } else if ( IsCube ) { static const int CubeSrcSwz [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned SubRegIndex0 = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( CubeSrcSwz [ Chan ] ) ; unsigned SubRegIndex1 = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( CubeSrcSwz [ <NUM_LIT> - Chan ] ) ; Src1 = TRI . getSubReg ( Src0 , SubRegIndex1 ) ; Src0 = TRI . getSubReg ( Src0 , SubRegIndex0 ) ; } bool Mask = false ; bool NotLast = true ; if ( IsCube


<s> if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } } if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } else if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } } } if ( check ( Reg < First || Reg > RangeEnd , Start , Twine ( <STR_LIT> ) + <ISA_LIT>InstPrinter :: getRegisterName ( First ) + <STR_LIT> + <ISA_LIT>InstPrinter :: getRegisterName (


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredCatchPad ( MachineInstr & MI , MachineBasicBlock


<s> bool AlwaysInstrument = Attr . isStringAttribute ( ) && Attr . getValueAsString ( ) == <STR_LIT> ; Sleds . emplace_back ( XRayFunctionEntry { Sled , CurrentFnSym , Kind , AlwaysInstrument


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR64DecoderTable [ RegNo


<s> rtx rmask [ MAX_VECT_LEN ] , mask ; gcc_checking_assert ( ! BYTES_BIG_ENDIAN ) ; mask = GEN_INT ( one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rmask [ i ] = mask ; mask = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rmask ) ) ; sel = expand_simple_binop ( vmode , AND , sel

, mask , NULL , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;


<s> for ( auto & MI : MRI -> use_nodbg_instructions ( SrcReg ) ) { if ( MI . isBundle ( ) ) continue ; if ( ! Visited . insert ( & MI ) . second


<s> vld1_u8 ( const uint8_t * a ) { return ( uint8x8_t ) __builtin_aarch64_ld1v8qi ( ( const


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <NUM_LIT> ) continue ; if ( MO . isDef ( ) )


<s> void setGISelAccessor ( GISelAccessor &


<s> else { q = a - z ; zz = q + c + ( a - ( q + z ) ) + aa + cc ; if ( zz == <NUM_LIT> ) return z ; xh = z + zz ; if ( nonfinite ( xh ) ) return xh ; x . dval [ <NUM_LIT> ] = xh ; x . dval [ <NUM_LIT> ] = z - xh


<s> machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( VECTOR_TYPE_P ( TREE_TYPE ( field ) ) && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = <NUM_LIT> ; } else nregs = <NUM_LIT> ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX -


<s> bool ImmediateOffsetNeedsLowering = false ; bool RegisterOffsetNeedsLowering = false ; int64_t Offset = Addr . getOffset ( ) ; if ( ( ( Offset < <NUM_LIT> ) || ( Offset & ( ScaleFactor - <NUM_LIT> ) ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) ImmediateOffsetNeedsLowering = true ; else if ( Offset > <NUM_LIT> && ! ( Offset & ( ScaleFactor - <NUM_LIT> ) ) && ! isUInt < <NUM_LIT> > ( Offset / ScaleFactor ) ) ImmediateOffsetNeedsLowering = true ; if ( ! ImmediateOffsetNeedsLowering && Addr . getOffset ( ) && Addr . isRegBase ( ) && Addr . getOffsetReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( Addr . isRegBase ( ) && Addr . getOffsetReg ( ) && ! Addr . getReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( ImmediateOffsetNeedsLowering && Addr . isFIBase ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( RegisterOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , <STR_LIT> , Addr . getShift ( ) ) ; } else { if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> ,

Addr . getOffsetReg ( ) , false , Addr . getShift ( ) , true ) ;


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm


<s> return Waitcnt ( std :: min ( VmCnt , Other . VmCnt ) , std :: min ( ExpCnt , Other .

ExpCnt ) , std :: min ( LgkmCnt , Other . LgkmCnt ) ) ;


<s> if ( __count >= <NUM_LIT> ) { if ( __count >= <NUM_LIT> ) { const __v16qu zero = { <NUM_LIT> } ; return ( __m128i ) zero ; } else { const __v16qu __shift = vec_splats ( ( unsigned char ) ( ( __count - <NUM_LIT> ) * <NUM_LIT> ) ) ; return ( __m128i ) vec_sro ( ( __v16qu ) __A , __shift ) ; return ( __m128i ) vec_slo ( ( __v16qu ) __A , __shift ) ; } } else { const __v16qu __shiftA = vec_splats ( ( unsigned char ) ( ( <NUM_LIT> - __count )


<s> static DecodeStatus DecodeThumbBLXOffset ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> ,

Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false


<s> static void s390_emit_stack_tie ( void ) { rtx mem = gen_frame_mem ( BLKmode , gen_rtx_REG ( Pmode


<s> signedDecoder < <NUM_LIT> > ( MI , tmp


<s> BlockISELList & CurrentISELList = BlockList . second ; auto I = CurrentISELList . begin ( ) ; auto E = CurrentISELList . end ( ) ; while ( I != E ) { assert ( isISEL ( * * I ) && <STR_LIT> ) ; MachineOperand & Dest = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; if ( useSameRegister ( Dest , TrueValue ) && useSameRegister ( Dest , FalseValue ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; NumRemoved ++ ; ( * I ) -> eraseFromParent ( ) ; I ++ ; } else if ( useSameRegister ( TrueValue , FalseValue ) ) { MachineBasicBlock * MBB = ( * I ) -> getParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; NumFolded ++ ; BuildMI ( * MBB , ( * I ) , dl , TII -> get ( isISEL8 ( * * I ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( FalseValue ) ; ( * I ) -> eraseFromParent ( ) ; I ++ ; } else if ( ExpandISELEnabled ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; BlockISELList SubISELList ; SubISELList . push_back ( * I ++ ) ; while ( I != E && canMerge ( SubISELList . back ( ) , * I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; SubISELList . push_back ( * I ++ ) ; } expandMergeableISELs ( SubISELList ) ; } else { I


<s> case <STR_LIT> : case <STR_LIT> : assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CC = <STR_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CC =


<s> const MachineOperand & BaseOp1 = * BaseOps1 . front ( ) ; const MachineOperand & BaseOp2 = * BaseOps2 . front ( ) ; const MachineInstr & FirstLdSt = * BaseOp1 . getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOp2 . getParent ( ) ; if ( BaseOp1 . getType ( ) != BaseOp2 . getType ( ) ) return false ; assert ( ( BaseOp1 . isReg ( ) || BaseOp1 . isFI ( ) ) && <STR_LIT> ) ; if ( BaseOp1 . isReg ( ) && BaseOp1 . getReg ( ) != BaseOp2 . getReg ( ) ) return false ; if ( NumLoads > <NUM_LIT> ) return false ; if ( ! isPairableLdStInst ( FirstLdSt ) || ! isPairableLdStInst ( SecondLdSt ) ) return false ; unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; if ( BaseOp1 . isFI ( ) ) { assert ( ( ! BaseOp1 . isIdenticalTo ( BaseOp2 ) || Offset1 <= Offset2 ) && <STR_LIT> ) ; const MachineFrameInfo & MFI = FirstLdSt . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; return shouldClusterFI ( MFI , BaseOp1 . getIndex ( ) , Offset1 , FirstOpc , BaseOp2 . getIndex ( ) ,


<s> const <ISA_LIT>Z80RegisterInfo & getRegisterInfo ( ) const { return


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) { unsigned TempReg = createResultReg ( RC ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; DestReg = TempReg


<s> return createELFStreamer ( Ctx , std :: move ( MAB ) , std :: move

( OW ) , std :: move ( Emitter ) , RelaxAll ) ;


<s> for ( res_set_t :: const_iterator I = set . begin ( ) , E = set . end ( ) ; I != E ; ++ I ) if ( ( * I & <NUM_LIT> ) == side ) return * I ; return -


<s> bool SelectAddrPCRel ( SDValue N , SDValue & Base


<s> case REG : print_operand ( file , addr , <NUM_LIT> ) ; break ; case PLUS : { rtx base , index ; if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && REG_OK_FOR_BASE_P ( XEXP ( addr , <NUM_LIT> ) ) ) base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ; else if ( REG_P ( XEXP ( addr , <NUM_LIT> ) ) && REG_OK_FOR_BASE_P ( XEXP ( addr , <NUM_LIT> ) ) ) base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ; else gcc_unreachable ( )


<s> NodeAddr < UseNode * > UA = newNode ( NodeAttrs :: Ref | NodeAttrs :: Use | Flags ) ; UA . Addr -> setRegRef


<s> void addCheriAsmRegOperands ( MCInst & Inst


<s> if ( TARGET_SSE4_1 ) { emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse4_1_pinsrd ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; } else if ( TARGET_INTER_UNIT_MOVES_TO_VEC ) { rtx tmp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) ) ) ; } else { rtx tmp = assign_386_stack_local ( DImode , SLOT_TEMP ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg ,


<s> bool isTargetILP32 ( ) const { return TargetTriple . isArch32Bit ( ) || TargetTriple .

getEnvironment ( ) == Triple :: GNUILP32 ;


<s> case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : case


<s> void <ISA_LIT>AsmParser :: eatComma ( ) { if ( Parser . getTok ( ) . is


<s> } mask = force_reg ( SImode , gen_rtx_NOT ( SImode , mask ) ) ; op2 = copy_to_mode_reg ( SImode , gen_lowpart ( SImode , op2 ) ) ; op2 = force_reg ( SImode , gen_rtx_AND ( SImode , op2 , mask ) ) ; if ( op1 == CONST0_RTX ( SFmode ) ) x = op2 ; else x = force_reg ( SImode , gen_rtx_IOR ( SImode , op1 , op2 ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_lowpart ( SFmode ,


<s> unsigned RegElts = TableEntry -> RegElts ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( TableEntry -> RealOpc ) ) ; unsigned OpIdx = <NUM_LIT> ; unsigned Lane = MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; assert ( RegSpc != OddDblSpc && <STR_LIT> ) ; if ( RegSpc == EvenDblSpc && Lane >= RegElts ) { RegSpc = OddDblSpc ; Lane -= RegElts ; } assert ( Lane < RegElts && <STR_LIT> ) ; unsigned D0 = <NUM_LIT> , D1 = <NUM_LIT> , D2 = <NUM_LIT> , D3 = <NUM_LIT> ; unsigned DstReg = <NUM_LIT> ; bool DstIsDead = false ; if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MachineOperand MO = MI . getOperand ( OpIdx ++ ) ; if ( ! TableEntry -> IsLoad ) GetDSubRegs ( MO . getReg ( ) , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; unsigned SrcFlags = ( getUndefRegState ( MO . isUndef ( ) ) | getKillRegState ( MO . isKill ( ) ) ) ; MIB . addReg ( D0 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , SrcFlags ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , SrcFlags ) ; MIB . addImm ( Lane ) ; OpIdx += <NUM_LIT>


<s> rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_CODE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE ) ; emit_move_insn ( mem ,


<s> } if ( Reg2NumMap . find ( Reg ) != Reg2NumMap . end ( ) ) { Nums . push_back ( Reg2NumMap [ Reg ] ) ; } else { Reg2NumMap [ Reg ] = Num ; Num2ValMap [ Num ] = NULL ; Nums . push_back ( Num ) ; Num ++ ; } } else if ( Operand . isImm ( ) ) { int64_t Imm = Operand . getImm ( ) ; if ( Imm2NumMap . find ( Imm ) != Imm2NumMap . end ( ) ) { Nums . push_back ( Imm2NumMap [ Imm ] ) ; } else { Imm2NumMap [ Imm ] = Num ; Num2ValMap [ Num ] = NULL ; Nums . push_back ( Num ) ; Num ++ ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( DefReg != <NUM_LIT> ) { if ( Reg2NumMap . find ( DefReg ) != Reg2NumMap . end ( ) ) { unsigned int Num = Reg2NumMap [ DefReg ] ; Val * Val = Num2ValMap [ Num ] ; if ( Val != NULL && Val -> Nums . size ( ) == Nums . size ( ) && std :: equal ( Val -> Nums . begin ( ) , Val -> Nums . end (