<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vcfux || icode == CODE_FOR_altivec_vcfsx || icode == CODE_FOR_altivec_vctsxs || icode == CODE_FOR_altivec_vctuxs || icode == CODE_FOR_altivec_vspltb || icode == CODE_FOR_altivec_vsplth || icode == CODE_FOR_altivec_vspltw || icode == CODE_FOR_spe_evaddiw || icode == CODE_FOR_spe_evldd || icode == CODE_FOR_spe_evldh || icode == CODE_FOR_spe_evldw || icode == CODE_FOR_spe_evlhhesplat || icode == CODE_FOR_spe_evlhhossplat || icode == CODE_FOR_spe_evlhhousplat || icode == CODE_FOR_spe_evlwhe || icode == CODE_FOR_spe_evlwhos || icode == CODE_FOR_spe_evlwhou || icode == CODE_FOR_spe_evlwhsplat || icode == CODE_FOR_spe_evlwwsplat || icode == CODE_FOR_spe_evrlwi || icode == CODE_FOR_spe_evslwi || icode == CODE_FOR_spe_evsrwis || icode == CODE_FOR_spe_evsubifw || icode == CODE_FOR_spe_evsrwiu ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg1 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfptstsfi_eq_dd || icode == CODE_FOR_dfptstsfi_lt_dd || icode == CODE_FOR_dfptstsfi_gt_dd || icode == CODE_FOR_dfptstsfi_unordered_dd || icode == CODE_FOR_dfptstsfi_eq_td || icode == CODE_FOR_dfptstsfi_lt_td || icode == CODE_FOR_dfptstsfi_gt_td || icode == CODE_FOR_dfptstsfi_unordered_td ) { STRIP_NOPS ( arg0 ) ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg0 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_xststdcdp || icode == CODE_FOR_xststdcsp || icode == CODE_FOR_xvtstdcdp || icode == CODE_FOR_xvtstdcsp ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg1 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode )


<s> for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( ! MRI . reg_nodbg_empty ( <STR_LIT> + i ) ) { FPIsUsed = true ; break ; } if ( ! FPIsUsed ) return false ; Bundles = & getAnalysis < EdgeBundles > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; df_iterator_default_set < MachineBasicBlock * > Processed ; MachineBasicBlock * Entry = & MF . front ( ) ; LiveBundle & Bundle = LiveBundles [ Bundles -> getBundle ( Entry -> getNumber ( ) , false ) ] ; if ( ( Entry -> getParent ( ) -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_RegCall ) && ( Bundle . Mask && ! Bundle . FixCount ) ) { assert ( ( Bundle . Mask & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Bundle . FixCount = <NUM_LIT> ; Bundle . FixStack [ <NUM_LIT> ] = <NUM_LIT> ; } bool Changed = false


<s> unsigned getReg ( ) const override { assert ( Kind == Register


<s> void <ISA_LIT>DAGToDAGISel :: PreprocessISelDAG ( ) { auto getNodes = [ this ] ( ) -> std :: vector < SDNode * > { std :: vector < SDNode * > T ; T . reserve ( CurDAG -> allnodes_size ( ) ) ; for ( SDNode & N : CurDAG -> allnodes ( ) ) T . push_back ( & N ) ; return T ; } ; ppSimplifyOrSelect0 ( getNodes ( ) ) ; ppAddrReorderAddShl ( getNodes ( ) ) ; ppAddrRewriteAndSrl ( getNodes ( ) ) ; ppHoistZextI1 ( getNodes ( ) ) ; DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( )


<s> __builtin_neon_vst1v8hi ( ( __builtin_neon_hi * ) __a ,


<s> SDValue BT = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , BitNo ) ; <STR_LIT> Cond = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Cond ,


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranch16TargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO


<s> bool isf32Imm ( ) const { return false


<s> assert ( I . getParent ( ) -> getParent ( ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * I . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_BR : { bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None ; if ( EnableOpt || ! MBB . isLayoutSuccessor ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) return false ; I . eraseFromParent ( ) ; return true ; } case TargetOpcode :: G_SHL : return earlySelectSHL ( I , MRI ) ; case TargetOpcode :: G_CONSTANT : { bool IsZero = false ; if ( I . getOperand ( <NUM_LIT> ) . isCImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) == <NUM_LIT> ; else if ( I . getOperand ( <NUM_LIT> ) . isImm ( ) ) IsZero = I . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; if ( ! IsZero ) return false ; Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { I . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else return false ; I . setDesc ( TII . get (


<s> return ( int32x4_t ) __builtin_neon_vqdmulh_lanev4si ( __a ,


<s> virtual int getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const { return <NUM_LIT>


<s> const value_var * get ( ) const { return this


<s> bool <ISA_LIT>TargetLowering :: allowsHvxMisalignedMemoryAccesses ( MVT VecTy , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( ! Subtarget . isHVXVectorType ( VecTy ) ) return false ; if ( Fast ) * Fast = true ; return true


<s> void <ISA_LIT>InstPrinter :: printSelectionControl ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( OpNo < MI -> getNumOperands ( )


<s> LH = treeRunner ( ptr -> getOperand ( <NUM_LIT> ) ) ; RH = treeRunner ( ptr -> getOperand ( <NUM_LIT> ) ) ; return p_SEL -> getMulExpr ( LH , RH ) ; } if ( const SCEVUDivExpr * ptr = dyn_cast < SCEVUDivExpr > ( s ) ) { LH = treeRunner ( ptr -> getLHS ( ) ) ; RH = treeRunner ( ptr -> getRHS ( ) ) ; return p_SEL -> getUDivExpr ( LH , RH ) ; } if ( const SCEVZeroExtendExpr * ptr = dyn_cast < SCEVZeroExtendExpr > ( s ) ) { return p_SEL -> getZeroExtendExpr ( treeRunner ( ptr -> getOperand ( ) ) , ptr -> getType ( ) ) ; } if ( const SCEVTruncateExpr * ptr = dyn_cast < SCEVTruncateExpr > ( s ) ) { return p_SEL -> getTruncateExpr ( treeRunner ( ptr -> getOperand ( ) ) , ptr -> getType ( ) ) ; } if ( const SCEVCommutativeExpr * ptr = dyn_cast < SCEVCommutativeExpr > ( s ) ) { LH = treeRunner ( ptr -> getOperand ( <NUM_LIT> ) ) ; RH = treeRunner ( ptr -> getOperand ( <NUM_LIT> ) ) ; if ( isa < SCEVSMaxExpr > ( ptr ) ) return p_SEL -> getSMaxExpr ( LH , RH ) ; if ( isa < SCEVUMaxExpr > ( ptr ) ) return p_SEL -> getUMaxExpr ( LH , RH ) ; } if ( const SCEVConstant * ptr = dyn_cast < SCEVConstant > ( s ) ) return ptr ; if ( const SCEVSignExtendExpr * ptr = dyn_cast < SCEVSignExtendExpr > ( s ) ) { dbgs ( ) << <STR_LIT> ; return ptr ; } if ( const SCEVUnknown * ptr = dyn_cast < SCEVUnknown > ( s ) ) { if ( Instruction * ins = dyn_cast < Instruction > ( m_SCE . visit ( ptr ) ) ) { if ( m_InsVec2 . size ( ) > <NUM_LIT> && ins == m_InsVec2 [ m_InsVec2 . size ( ) - <NUM_LIT> ] ) return p_SEL -> getZero ( Type :: getInt32Ty ( ins -> getContext ( ) ) ) ; else return ptr ; } else return p_SEL -> getZero ( s -> getType ( ) ) ; } if ( ! Result ) errs ( ) << <STR_LIT> ; return Result


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; BuildMI ( * BB , MI -> getIterator ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MI -> eraseFromParent ( ) ; break ; } case <STR_LIT> : return BB ; case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo


<s> SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FirstInsertedMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; FirstInsertedMBB -> addSuccessor ( SecondInsertedMBB ) ; FirstInsertedMBB -> addSuccessor ( SinkMBB ) ; SecondInsertedMBB -> addSuccessor ( SinkMBB ) ; <STR_LIT> FirstCC = <STR_LIT> ( FirstCMOV . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( ThisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( FirstCC ) ; <STR_LIT> SecondCC = <STR_LIT> ( SecondCascadedCMOV . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( FirstInsertedMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SinkMBB ) . addImm ( SecondCC ) ; Register DestReg = FirstCMOV . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = FirstCMOV . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2Reg = FirstCMOV . getOperand (


<s> use_vector_set = TARGET_AVX ; gen_vec_set_0 = gen_vec_setv8si_0 ; break ; case E_V8SFmode : use_vector_set = TARGET_AVX ; gen_vec_set_0 = gen_vec_setv8sf_0 ; break ; case E_V4DFmode : use_vector_set = TARGET_AVX ; gen_vec_set_0 = gen_vec_setv4df_0 ; break ; case E_V4DImode : use_vector_set = TARGET_AVX && TARGET_64BIT ; gen_vec_set_0 = gen_vec_setv4di_0 ; break ; case E_V16SImode : use_vector_set = TARGET_AVX512F && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv16si_0 ; break ; case E_V16SFmode : use_vector_set = TARGET_AVX512F && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv16sf_0 ; break ; case E_V8DFmode : use_vector_set = TARGET_AVX512F && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv8df_0 ; break ; case E_V8DImode : use_vector_set = TARGET_AVX512F && TARGET_64BIT && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv8di_0 ; break ; case E_V8HFmode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv8hf_0 ; break ; case E_V16HFmode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv16hf_0 ; break ; case E_V32HFmode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv32hf_0 ; break ; case E_V32HImode : use_vector_set = TARGET_AVX512FP16 && one_var == <NUM_LIT> ; gen_vec_set_0 = gen_vec_setv32hi_0 ; default : break ; } if ( use_vector_set ) { if ( gen_vec_set_0 && one_var == <NUM_LIT> ) { var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; emit_insn ( gen_vec_set_0 ( target , CONST0_RTX ( mode ) , var ) ) ; return true ; } emit_insn ( gen_rtx_SET ( target , CONST0_RTX ( mode ) ) ) ; var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } switch ( mode ) { case E_V2SFmode : case E_V2SImode : if ( ! mmx_ok ) return false ; case E_V2DFmode : case E_V2DImode : if ( one_var != <NUM_LIT> ) return false ; var = force_reg ( GET_MODE_INNER ( mode ) , var ) ; x = gen_rtx_VEC_CONCAT ( mode , var , CONST0_RTX ( GET_MODE_INNER ( mode ) ) ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; return true


<s> MCInst const & MCI = * I . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isDuplex ( MII , MCI ) ) { printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; OS << '\v' ; HasExtender = false ; printInstruction ( MCI . getOperand ( <NUM_LIT> ) . getInst ( ) , OS ) ; } else printInstruction ( & MCI , OS ) ; setExtender ( MCI


<s> return op_info -> ret . get_tree_type ( type .


<s> emitAlignment ( align ) ; } if ( isFStart ( & MBB ) && ( MBB . getParent ( ) -> getBlockNumbered ( <NUM_LIT> ) != & MBB ) ) { assert ( ! MBB . pred_empty ( ) && <STR_LIT> ) ; MCSymbol * SymStart = MBB . getSymbol ( ) ; CurrCodeEnd = OutContext .


<s> return unpackBits ( Waitcnt , getExpcntBitShift ( ) ,


<s> return true ; } if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ; } return false


<s> static DecodeStatus DecodeGPRwithZRnospRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler ::


<s> assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID (


<s> } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } alignLoadVec = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , SN -> getSrcValue ( ) , SN -> getSrcValueOffset ( ) , SN -> isVolatile ( ) , SN -> isNonTemporal ( ) , <NUM_LIT> ) ; the_chain = alignLoadVec . getValue ( <NUM_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( alignLoadVec ) ; SDValue theValue = SN -> getValue ( ) ; SDValue result ; if ( StVT != VT && ( theValue . getOpcode ( ) == <STR_LIT> || theValue . getOpcode ( ) == <STR_LIT> ) ) { theValue = theValue . getOperand ( <NUM_LIT> ) ; } if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { errs ( ) << <STR_LIT> ; basePtr . getNode ( ) -> dump ( & DAG ) ; errs ( ) << <STR_LIT> ; } SDValue insertEltOp = DAG . getNode ( <STR_LIT> , dl , vecVT , insertEltOffs ) ; SDValue vectorizeOp = DAG . getNode ( <STR_LIT> , dl , vecVT , theValue ) ; result = DAG . getNode ( <STR_LIT> , dl , vecVT , vectorizeOp , alignLoadVec , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , insertEltOp ) ) ; result = DAG . getStore ( the_chain , dl , result , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , LN -> getAlignment ( ) ) ; if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { const SDValue & currentRoot = DAG . getRoot ( ) ; DAG . setRoot ( result ) ; errs ( ) << <STR_LIT> ; DAG . dump ( ) ; errs ( ) << <STR_LIT> ; DAG . setRoot ( currentRoot ) ; } return result ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { std :: string msg


<s> if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; <ISA_LIT>AddressMode AM


<s> return false ; } if ( needsLowering ) { uint64_t UnscaledOffset = Addr . getOffset ( ) * ScaleFactor ; unsigned ResultReg = FastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . getReg ( ) , false , UnscaledOffset , <STR_LIT> ) ; if ( ResultReg == <NUM_LIT> ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffset ( <NUM_LIT> ) ; } return true


<s> imm_size = get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , group_name [ group ] , path , byte_len ) ; fprintf ( file , <STR_LIT> , num_imm_operand , num_imm32_operand , num_imm64_operand ,


<s> unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd , Addr ,


<s> Results . push_back ( RTB ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( NewInt ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue FPreg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPreg , FPreg ) ) ; return ; } case <STR_LIT> : case


<s> for ( auto & B : MF ) { for ( auto & MI : B ) { if ( ! MI . isBranch ( ) || ! isJumpOutOfRange ( MI , BlockToInstOffset ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << HII -> isExtendable ( MI ) << <STR_LIT> << HII -> isConstExtended ( MI ) << <STR_LIT> << MI ) ; if ( ! HII -> isExtendable ( MI ) && ! HII -> isExtended ( MI ) ) { LLVM_DEBUG ( dbgs ( ) <<


<s> else { MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , CSI [ CSIIndex ] . getFrameIdx ( ) ) ) ; RestoreOp = <STR_LIT> ; MoveReg = <STR_LIT> ; } if ( CR2Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR3Spilled && ! CR4Spilled ) ) ) ; if ( CR3Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR4Spilled ) ) ) ; if ( CR4Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII .

get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( true ) ) ) ;


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } if ( ! FBB ) return <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) .


<s> return true ; } auto * TLI = & IC . getTargetLibraryInfo ( ) ; if ( isKnownNeverInfinity ( Op0 , TLI ) && isKnownNeverNaN ( Op0 , TLI ) && isKnownNeverInfinity ( Op1 , TLI ) && isKnownNeverNaN ( Op1 , TLI ) ) { return true ; } return


<s> assert ( Inst . getOperand ( OpNum - <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( OpNum - <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( OpNum < <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) <= <NUM_LIT> && Inst . getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( OpNum - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) { if ( inMicro<ISA_LIT>Mode ( ) && has<ISA_LIT>32r6 ( ) ) NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else NewOpcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } Inst . setOpcode ( NewOpcode ) ; Instructions . push_back (


<s> if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( *


<s> case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case MODE_COMPLEX_FLOAT : return riscv_pass_fpr_pair ( mode , fregno , GET_MODE_INNER ( mode ) , <NUM_LIT> , fregno + <NUM_LIT> , GET_MODE_INNER ( mode


<s> if ( MO . isImm ( ) ) { uint64_t Val = MO . getImm ( ) ; uint64_t Pow = <NUM_LIT> ; uint64_t Octal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( Val == <NUM_LIT> ) break ; Octal += ( Val %


<s> static void signedDecoder ( MCInst & MI , unsigned tmp , const void * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 < T


<s> warning ( <NUM_LIT> , <STR_LIT> , name ) ; * no_add = true ; } else if ( args == NULL_TREE && TREE_CODE ( * node ) == VAR_DECL ) { if ( ! ( TREE_PUBLIC ( * node ) || TREE_STATIC ( * node ) ) ) { warning ( <NUM_LIT> , <STR_LIT> ) ; * no_add = true ; } if ( TREE_TYPE ( * node ) && TREE_CODE ( TREE_TYPE ( * node ) ) == POINTER_TYPE ) { warning ( <NUM_LIT> , <STR_LIT> ) ; * no_add = true ; } } return


<s> return ( REG_P ( x ) && riscv_regno_mode_ok_for_base_p ( REGNO ( x ) ,


<s> static void LookThroughSetCC ( SDValue & LHS , SDValue & RHS , <STR_LIT> CC , unsigned & <ISA_LIT>CC ) { if ( isNullConstant ( RHS ) && CC == <STR_LIT> && ( ( ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( LHS . getOpcode ( ) == <STR_LIT> && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) && isOneConstant ( LHS . getOperand ( <NUM_LIT> ) ) && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) ) { SDValue CMPCC = LHS . getOperand ( <NUM_LIT> ) ; <ISA_LIT>CC = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; LHS = CMPCC . getOperand ( <NUM_LIT> ) ; RHS = CMPCC . getOperand ( <NUM_LIT>


<s> ElemSize esize = Opcode == <STR_LIT> ? ESize8 : ( Opcode == <STR_LIT> ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd (


<s> bool R600InstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return false ; -- I ; while ( I -> isDebugValue ( ) ) { if ( I == MBB . begin ( ) ) return false ; -- I ; } if ( ! isJump ( static_cast < MachineInstr * > ( I ) -> getOpcode ( ) ) ) { return false ; } MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == AMDGPU :: JUMP ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == AMDGPU :: JUMP_COND ) { MachineInstr * predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( AMDGPU :: PRED_SEL_ONE , false ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( SecondLastOpc == AMDGPU :: JUMP_COND && LastOpc == AMDGPU


<s> ++ Depth ; } assert ( Depth < Stack . size ( ) && <STR_LIT> ) ; return Depth


<s> break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , Mask ) ; IsUnary = IsFakeUnary = N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePALIGNRMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; break ; case <STR_LIT> : case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : { IsUnary = true ; SDValue MaskNode = N -> getOperand ( <NUM_LIT> ) ; while ( MaskNode -> getOpcode ( ) == <STR_LIT> ) MaskNode = MaskNode -> getOperand ( <NUM_LIT> ) ; if ( MaskNode -> getOpcode ( ) == <STR_LIT> ) { EVT VT = MaskNode . getValueType ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; if ( ! VT . isInteger ( ) ) return false ; int NumBytesPerElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; for ( int i = <NUM_LIT> , e = MaskNode -> getNumOperands ( ) ; i < e ; ++ i ) { SDValue Op = MaskNode -> getOperand ( i ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { RawMask . push_back ( ( uint64_t ) SM_SentinelUndef ) ; continue ; } auto * CN = dyn_cast < ConstantSDNode > ( Op . getNode ( ) ) ; if ( ! CN ) return false ; APInt MaskElement = CN -> getAPIntValue ( ) ; for ( int j = <NUM_LIT> ; j < NumBytesPerElement ; ++ j ) { RawMask . push_back ( MaskElement . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) ; MaskElement = MaskElement . lshr ( <NUM_LIT> ) ; } } DecodePSHUFBMask ( RawMask , Mask ) ; break ; } auto * MaskLoad = dyn_cast < LoadSDNode > ( MaskNode


<s> unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; static unsigned QSubs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) { SDValue NV = CurDAG -> getTargetExtractSubreg ( QSubs [ i ] , dl , WideVT , SuperReg ) ; if ( Narrow ) NV = NarrowVector ( NV


<s> bool isAISrc_128B16 ( ) const { return isRegOrInlineNoMods ( <STR_LIT>


<s> static bool ge_sew_unavailable_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if ( ! info2 . demand_p ( DEMAND_LMUL ) && ! info2 . demand_p ( DEMAND_RATIO ) && info2 . demand_p ( DEMAND_GE_SEW ) ) return info1 . get_sew ( ) < info2 . get_sew ( ) ; return


<s> if ( mode != BLKmode ) type_size = GET_MODE_BITSIZE ( mode ) ; else type_size = int_size_in_bytes ( type ) * BITS_PER_UNIT ; remaining_size = BITS_PER_WORD * ( MAX_REG_FOR_PASSING_ARGS - ( MIN_REG_FOR_PASSING_ARGS + cum -> ints ) + <NUM_LIT> ) ; if ( ( remaining_size >= type_size ) && ( type_size <= <NUM_LIT> * BITS_PER_WORD ) ) return ( type_size + BITS_PER_WORD - <NUM_LIT> ) / BITS_PER_WORD ; return


<s> __o = __builtin_aarch64_ld2rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; return ret


<s> switch ( Kind ) { case Kind :: Invalid : OS << <STR_LIT> ; break ; case Kind :: Token : OS << <STR_LIT> << Token << <STR_LIT> ; break ; case Kind ::


short __q2 , short __q3 , short __q4 , short __q5 , short __q6 , short __q7 ) {


<s> case <STR_LIT> :: I8x16 : O << <STR_LIT> ; break ; case <STR_LIT> :: I16x8 : O << <STR_LIT> ; break ; case <STR_LIT> :: I32x4 : O << <STR_LIT> ; break ; case <STR_LIT> :: F32x4 : O << <STR_LIT> ; break ; case <STR_LIT> :: B8x16 : O << <STR_LIT> ; break ; case <STR_LIT> :: B16x8 : O << <STR_LIT> ; break ; case <STR_LIT> :: B32x4 : O


<s> int msp430_arg_partial_bytes ( cumulative_args_t cap , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( cap ) ; msp430_evaluate_arg ( cap , arg . mode , arg . type , arg .


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; } if ( Subtarget . is<ISA_LIT>64 ( )


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { RegisterBankInfo :: InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : case TargetOpcode :: G_GEP : case TargetOpcode :: G_MUL : case TargetOpcode :: G_SDIV : case TargetOpcode :: G_UDIV : case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameKindOfOperandsMapping ( MI ) ; case TargetOpcode :: G_BITCAST : { LLT DstTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT SrcTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Size = DstTy . getSizeInBits ( ) ; bool DstIsGPR = ! DstTy . isVector ( ) ; bool SrcIsGPR = ! SrcTy . isVector ( ) ; const RegisterBank & DstRB = DstIsGPR ? <STR_LIT> : <STR_LIT> ; const RegisterBank & SrcRB = SrcIsGPR ? <STR_LIT> : <STR_LIT> ; return InstructionMapping { DefaultMappingID , copyCost ( DstRB , SrcRB , Size ) , getCopyMapping ( DstRB . getID ( ) , SrcRB . getID ( ) , Size ) , <NUM_LIT> } ; } case TargetOpcode :: G_SEQUENCE : return InstructionMapping ( ) ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < unsigned , <NUM_LIT> > OpSize ( NumOperands ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumOperands ; ++ Idx ) { auto & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; LLT Ty = MRI . getType ( MO . getReg ( ) ) ; OpSize [ Idx ] = Ty . getSizeInBits ( ) ; if ( Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ) OpRegBankIdx [ Idx ] = PMI_FirstFPR ; else OpRegBankIdx [ Idx ] = PMI_FirstGPR ; } unsigned Cost = <NUM_LIT> ; switch ( Opc ) { case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : { OpRegBankIdx = { PMI_FirstFPR , PMI_FirstGPR } ; break ; } case TargetOpcode :: G_FPTOSI : case TargetOpcode :: G_FPTOUI


<s> PersonalityIndex = <STR_LIT> :: NUM_PERSONALITY_INDEX ; size_t TotalSize = Ops . size ( ) + <NUM_LIT> ; size_t RoundUpSize = ( TotalSize + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> ; Result . resize ( RoundUpSize ) ; OpStreamer . EmitSize ( RoundUpSize ) ; } else { if ( PersonalityIndex == <STR_LIT> :: NUM_PERSONALITY_INDEX ) PersonalityIndex = ( Ops . size ( ) <= <NUM_LIT> ) ? <STR_LIT> :: AEABI_UNWIND_CPP_PR0 : <STR_LIT> :: AEABI_UNWIND_CPP_PR1 ; if ( PersonalityIndex ==


<s> bool RelaxCandidate = false ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT>


<s> return __builtin_mve_vqrdmulhq_sv4si ( __a ,


<s> const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 .


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs ) ; auto EmitMI = [ & ] ( const RegPairInfo & RPI ) { unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned LdrOpc ; if ( RPI . IsGPR ) LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; else LdrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( )

<< <STR_LIT> << printReg ( Reg2 , TRI ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c )


<s> EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SrcVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; int NumMaskElts = ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ; if ( ! ResVT . isVector ( ) || NumMaskElts == <NUM_LIT> ) return SDValue ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext


<s> static bool isPromotableZeroStoreOpcode ( MachineInstr * MI ) { return isPromotableZeroStoreOpcode ( MI -> getOpcode


<s> } IncrementOffset = getAddSubImmediate ( * Increment ) ; unsigned NewPostIncOpcode = getPostIndexedLoadStoreOpcode ( BaseAccess -> getOpcode ( ) , IncrementOffset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( ! isLegalAddressImm ( NewPostIncOpcode , IncrementOffset , TII ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( PrePostInc ) { if ( Increment ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Base . virtRegIndex ( ) << <STR_LIT> ) ; int BaseOp = getBaseOperandIndex ( * PrePostInc ) ; IncrementOffset = PrePostInc -> getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) ; BaseAccess = PrePostInc ; NewBaseReg = PrePostInc -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else return false ; SmallPtrSet < MachineInstr * , <NUM_LIT> > SuccessorAccesses ; int CodesizeEstimate = - <NUM_LIT> ; for ( auto * Use : OtherAccesses ) { if ( DT -> dominates ( BaseAccess , Use ) ) { SuccessorAccesses . insert ( Use ) ; unsigned BaseOp = getBaseOperandIndex ( * Use ) ; if ( ! isLegalOrConvertableAddressImm ( Use -> getOpcode ( ) , Use -> getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) - IncrementOffset , TII , CodesizeEstimate ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( ! DT -> dominates ( Use , BaseAccess ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } if ( STI -> hasMinSize ( ) && CodesizeEstimate > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! PrePostInc ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BaseAccess -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Increment


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; Register FPReg = <STR_LIT> ; Register SPReg = <STR_LIT> ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( hasFramePointer ) StackSize ++ ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , RI -> getDwarfRegNum ( Reg , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFramePointer ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) .

addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - <NUM_LIT> ) ;


<s> if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == ST -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS || Load -> getPointerAddressSpace ( ) == ST -> get<ISA_LIT>AS ( ) . FLAT_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return <STR_LIT> (


<s> return createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < <ISA_LIT>AAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } )


<s> ResolveInfo :: Desc getSymDesc ( uint16_t shndx ) const { if ( shndx >= llvm :: ELF :: SHN_HEXAGON_SCOMMON && shndx <= llvm :: ELF :: SHN_HEXAGON_SCOMMON_8


<s> MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; } unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit


<s> MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( needsRegArgSlots && TFI . hasReservedCallFrame ( MF ) ) MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; } if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> ,


<s> SDValue NewMask = DAG . getConstant ( Mask >> ShiftAmt , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; AM . Scale = <NUM_LIT> <<


<s> if ( ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER


<s> assert ( VecTy == Src0 -> getType ( ) && VecTy == Src1 -> getType ( ) ) ; unsigned NumElt = VecTy -> getVectorNumElements ( ) ; Value * Res = UndefValue :: get ( VecTy ) ; Value * Srcs [ <NUM_LIT> ] = { Src0 , Src1 } ; for ( int opi = <NUM_LIT> , ope = <NUM_LIT> ; opi != ope ; ++ opi ) { for ( int i = <NUM_LIT> , e = NumElt / <NUM_LIT> ; i != e


<s> unsigned <ISA_LIT>MCCodeEmitter :: adjustPqBitsSpls ( const MCInst & Inst , unsigned Value


<s> mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( maybe_ne ( wi :: to_poly_wide ( TYPE_SIZE ( type ) ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( maybe_ne ( wi :: to_poly_wide ( TYPE_SIZE ( type ) ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field )


<s> if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) , DestinationRegister ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> )


<s> DOP_ENTRY_HSD ( ps , inst , ty ) { <STR_LIT> ## _S , { <STR_LIT> ## _S , <STR_LIT> ##


<s> for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { if ( Ps == ConstantProperties :: Unknown ) break ; Ps &= ConstantProperties :: deduce ( Values [ i ] ) ; } return Ps


<s> MachineFunctionProperties getClearedProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root ,

SmallVectorImpl < MachineCombinerPattern > & Patterns ) const {


<s> bool <ISA_LIT>AsmParser :: ParseIntelInlineAsmIdentifier ( const MCExpr * & Val , StringRef & Identifier , InlineAsmIdentifierInfo & Info , bool IsUnevaluatedOperand , SMLoc & End , bool IsParsingOffsetOperator ) { MCAsmParser & Parser = getParser ( ) ; assert ( isParsingMSInlineAsm ( ) && <STR_LIT> ) ; Val = nullptr ; StringRef LineBuf ( Identifier . data ( ) ) ; SemaCallback -> LookupInlineAsmIdentifier ( LineBuf , Info , IsUnevaluatedOperand ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; do { End = Tok . getEndLoc (


<s> if ( ( Opc == Instruction :: URem || Opc == Instruction :: UDiv || Opc == Instruction :: SRem || Opc == Instruction :: SDiv ) && Ty -> getScalarSizeInBits ( ) <= <NUM_LIT> ) { Value * Num = I . getOperand ( <NUM_LIT> ) ; Value * Den = I . getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( & I ) ; Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewDiv = UndefValue :: get ( VT ) ; for ( unsigned N = <NUM_LIT> , E = VT -> getNumElements ( ) ; N != E ; ++ N ) { Value * NumEltN = Builder . CreateExtractElement ( Num , N ) ; Value * DenEltN = Builder . CreateExtractElement ( Den , N ) ; Value * NewElt = expandDivRem32 ( Builder , I , NumEltN , DenEltN ) ; if ( ! NewElt ) NewElt = Builder . CreateBinOp ( Opc ,


<s> return ( __m128i ) vec_subs ( ( __v16qu ) __A ,


<s> while ( X . getValueType ( ) != VT && X -> getOpcode ( ) == <STR_LIT> ) X = X -> getOperand ( <NUM_LIT> ) ; if ( X . getValueType ( ) == VT ) return X ; } if ( Op0 -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> ) < Op0 . getNumOperands ( ) ) { return Op0 . getOperand ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; } if ( Op0 . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue BV = Op0 . getOperand ( <NUM_LIT> ) ; unsigned Offset = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue MOV = BV . getOperand ( Offset < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( MOV . getOpcode ( ) == <STR_LIT> ) return MOV . getOperand ( ST -> isLittle ( ) ? Offset % <NUM_LIT> : <NUM_LIT> - Offset % <NUM_LIT> ) ; } if ( SDValue R = PerformExtractEltToVMOVRRD ( N , DCI ) ) return R ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { unsigned Idx = N -> getConstantOperandVal ( <NUM_LIT> ) ; unsigned Vec = Idx / Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; unsigned SubIdx = Idx % Op0 -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op0 . getOperand ( Vec ) , DCI . DAG . getConstant ( SubIdx , dl , <STR_LIT> ) ) ; } return SDValue


<s> } PrevNode = Node ; } else { BasicBlock * Flow = needPrefix ( false ) ; BasicBlock * Entry = Node -> getEntry ( ) ; BasicBlock * Next = needPostfix ( Flow , ExitUseAllowed ) ; Conditions . push_back ( BranchInst :: Create ( Entry , Next , BoolUndef , Flow ) ) ; addPhiValues ( Flow , Entry ) ; DT -> changeImmediateDominator ( Entry , Flow ) ; PrevNode = Node ; while ( ! Order . empty ( ) && ! Visited . count ( LoopEnd ) && dominatesPredicates ( Entry , Order . back ( ) ) ) { handleLoops ( false , LoopEnd ) ; } changeExit ( PrevNode ,


<s> if ( F -> hasFnAttribute ( <STR_LIT> ) && F -> hasFnAttribute ( <STR_LIT> ) ) { removeUseSoftFloat ( * F ) ; continue ; } if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) continue ; Modified |= fixupFPReturnAndCall ( * F , & M , TM ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V != NoSig


<s> enum machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , flags , tmp


<s> for ( unsigned u = i ; u > BestPos ; -- u ) { ++ ScheduledSUnitsInv [ ScheduledSUnits [ u - <NUM_LIT> ] ] ; ScheduledSUnits [ u ] = ScheduledSUnits [ u - <NUM_LIT> ] ; } ScheduledSUnits [ BestPos ] = SU -> NodeNum ; ScheduledSUnitsInv [ SU -> NodeNum ] = BestPos ; } LastLowLatencyPos = BestPos ; if ( IsLowLatencyUser ) LastLowLatencyUser = BestPos ; } else if ( IsLowLatencyUser ) { LastLowLatencyUser = i ; } else if ( SU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> ) { bool CopyForLowLat = false ; for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( <ISA_LIT>TII -> isLowLatencyInstruction ( * Succ -> getInstr ( ) ) ) { CopyForLowLat = true ; } } if ( ! CopyForLowLat ) continue ; if ( MinPos < i ) { for ( unsigned u = i ; u >


<s> CondCodeSDNode * CC = cast < CondCodeSDNode > ( SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( CC -> get ( ) == <STR_LIT> ) ; Intr = SetCC -> getOperand ( <NUM_LIT> ) . getNode ( ) ; } else { BR = findUser ( BRCOND , <STR_LIT> ) ; Target = BR -> getOperand ( <NUM_LIT> ) ; } assert ( Intr -> getOpcode ( ) == <STR_LIT> ) ; SmallVector < EVT , <NUM_LIT> > Res ; for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) ; i != e ; ++ i ) Res . push_back ( Intr -> getValueType ( i ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( BRCOND . getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Intr -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Intr -> getOperand ( i ) ) ; Ops . push_back ( Target ) ; SDNode * Result = DAG . getNode ( Res . size ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( Res . data ( ) , Res . size ( ) ) , Ops . data ( ) , Ops . size ( ) ) . getNode ( ) ; if ( BR ) { SDValue Ops [ ] = { BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand


<s> if ( SP_REG_P ( src ) && Z_REG_P ( dst ) ) emit_insn_after ( gen_addhi3 ( dst , dst , const2_rtx ) , insn ) ; } if ( ! validate_replace_rtx ( z_reg , replace_reg , insn ) ) { INSN_CODE ( insn ) = - <NUM_LIT> ; if ( ! validate_replace_rtx ( z_reg , replace_reg , insn ) ) fatal_insn ( <STR_LIT> , insn ) ; } if ( reg_mentioned_p ( z_reg , insn ) ) { if ( replace_reg_qi == NULL_RTX ) replace_reg_qi = gen_rtx_REG ( QImode , REGNO ( replace_reg ) ) ; validate_replace_rtx ( z_reg_qi , replace_reg_qi , insn ) ; } for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , <NUM_LIT> ) ) { if ( REG_NOTE_KIND ( note ) == REG_INC && GET_CODE ( XEXP ( note , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( note , <NUM_LIT> ) ) == REGNO ( z_reg ) ) { XEXP ( note , <NUM_LIT> ) = replace_reg ; } } } if ( GET_CODE ( insn ) == CALL_INSN || GET_CODE ( insn ) == JUMP_INSN ) break ; } if ( insn && info . need_save_z && ! info . must_push_reg ) { rtx save_pos_insn = insn ; if ( info . save_before_last ) save_pos_insn = PREV_INSN ( save_pos_insn ) ; emit_insn_before ( gen_movhi ( gen_rtx_REG ( HImode , SOFT_Z_REGNUM ) , gen_rtx_REG ( HImode , info . regno ) ) , save_pos_insn ) ; } if ( info . must_push_reg && info . last ) { rtx new_body , body ; body = PATTERN ( info . last ) ; new_body = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , body , gen_rtx_USE ( VOIDmode , replace_reg ) , gen_rtx_USE ( VOIDmode , gen_rtx_REG ( HImode , SOFT_Z_REGNUM ) ) ) ) ; PATTERN ( info . last ) = new_body ; INSN_CODE ( insn ) = - <NUM_LIT> ; if ( ! validate_replace_rtx ( z_reg , replace_reg , info . last ) ) { fatal_insn ( <STR_LIT> , insn ) ; } insn = NEXT_INSN ( info . last ) ; } if ( insn && info . must_restore_reg && ! info . must_push_reg ) { rtx dst ; if ( info . must_push_reg && <NUM_LIT> ) dst = gen_rtx_MEM ( HImode , gen_rtx_POST_INC ( HImode , gen_rtx_REG ( HImode , HARD_SP_REGNUM ) ) ) ; else dst = gen_rtx_REG ( HImode ,


<s> tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , addr ) , unspec ) ; new_rtx = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , picreg , tmp ) ) ; emit_move_insn ( reg , new_rtx ) ; } if ( picreg == pic_offset_table_rtx ) crtl -> uses_pic_offset_table = <NUM_LIT> ; return reg ; } else if ( GET_CODE ( addr ) == CONST || GET_CODE ( addr ) == PLUS ) { rtx base ; if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( addr ) == PLUS ) ; } if ( XEXP ( addr , <NUM_LIT> ) == picreg ) return orig ; if ( reg == <NUM_LIT> ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } base = legitimize_pic_address ( XEXP ( addr , <NUM_LIT> ) , reg , picreg ) ; addr = legitimize_pic_address ( XEXP ( addr , <NUM_LIT> ) , base == reg ? NULL_RTX : reg , picreg ) ; if ( GET_CODE ( addr ) == CONST_INT ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; addr = force_reg ( Pmode , addr ) ; } if ( GET_CODE ( addr ) == PLUS && CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) { base = gen_rtx_PLUS ( Pmode , base , XEXP ( addr , <NUM_LIT> ) ) ; addr = XEXP ( addr


<s> MRI = & MF . getRegInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed = false ; for ( auto & MBB : MF ) processMachineBasicBlock ( MBB ) ; return Changed


<s> virtual const AMDGPURegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( )


<s> AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage (


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; GlobalAddressSDNode * GlobalAddr = cast < GlobalAddressSDNode > ( Op . getNode ( ) ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue TargetAddr = DAG . getTargetGlobalAddress ( GlobalAddr -> getGlobal ( ) , Op ,


<s> void <ISA_LIT>LowerControlFlow :: splitBlockLiveIns ( const MachineBasicBlock & MBB , const MachineInstr & MI , MachineBasicBlock & LoopBB , MachineBasicBlock & RemainderBB , unsigned SaveReg , const MachineOperand & IdxReg ) { LivePhysRegs RemainderLiveRegs ( TRI ) ; RemainderLiveRegs . addLiveOuts ( MBB ) ; for ( MachineBasicBlock :: const_reverse_iterator I = MBB . rbegin ( ) , E ( & MI ) ; I != E ; ++ I ) { RemainderLiveRegs . stepBackward ( * I ) ; } RemainderLiveRegs . addReg ( SaveReg ) ; if ( const MachineOperand * Val = TII -> getNamedOperand ( MI , <STR_LIT> :: val ) ) { if ( ! Val -> isUndef (


<s> auto NextBB = std :: next ( MBBI ) ; if ( NextBB == MBB . getParent ( ) -> end ( ) ) return false ; return MBB . isSuccessor (


<s> static int readMaskRegister ( struct InternalInstruction * insn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( insn -> vectorExtensionType != TYPE_EVEX


<s> while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneUse ( CondDefReg ) ) { for ( auto UI = MRI . use_instr_begin ( CondDefReg ) , UE = MRI . use_instr_end ( ) ; UI != UE ; ++ UI ) { if ( CondDef == & * UI ) continue ; if ( UI -> getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { CondCode = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( ! emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else { <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CondDef -> getOperand ( <NUM_LIT> ) .

getPredicate ( ) , CondCode , CondCode2 ) ;


<s> SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI , VT ) ; Chain = DAG . getStore ( Chain , dl , RetAddrFrIdx , NewRetAddrFrIdx , PseudoSourceValue :: getFixedStack ( NewReturnAddrFI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; return


<s> switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> static inline vec_bint4 vec_unpackl (


<s> std :: vector < std :: string > add_sub ( ArpRn1 a , ArpStep1 asi , ArpStep1 asj , Ab b ) { return D ( <STR_LIT> , MemARPSJ ( a , asj ) , MemARPSI ( a , asi ) , R (


<s> else if ( bytes < GET_MODE_SIZE ( SImode ) && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Ptr = Op . getOperand ( <NUM_LIT> ) ; if ( StoreNode -> getAddressSpace ( ) == <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) { Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType (

) , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ;


<s> return MI . getOperand ( TII -> getOperandIdx ( MI . getOpcode ( ) , <STR_LIT> :: COUNT


<s> SCCInfos :: const_iterator tmp ( Infos . find ( function ) ) ; assert ( tmp != Infos . end (


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; WinEHEncodingType = WinEH :: EncodingType ::


<s> MachineBasicBlock * EndBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBB ) ; MF -> insert ( It , EndBB ) ; EndBB -> splice ( EndBB -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; int ScratchFI = MF -> getFrameInfo ( ) -> CreateSpillStackObject ( <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfFalseReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CondCode ) . addMBB ( TrueBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndBB ) ; MBB -> addSuccessor ( TrueBB ) ; MBB -> addSuccessor ( EndBB ) ; BuildMI ( TrueBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IfTrueReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ; TrueBB -> addSuccessor ( EndBB ) ; if ( ! NZCVKilled ) EndBB -> addLiveIn ( <STR_LIT> ) ; MachineInstr * StartOfEnd = EndBB -> begin ( ) ; BuildMI ( * EndBB , StartOfEnd , DL , TII -> get ( <STR_LIT>

) , DestReg ) . addFrameIndex ( ScratchFI ) . addImm ( <NUM_LIT> ) ;


<s> bool isICmp = true ; bool needsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ; AddOptionalDefs ( MIB ) ; } if ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt

, DbgLoc , TII . get ( <STR_LIT> ) ) ) ;


<s> case IES_AND : case IES_EQ : case IES_NE : case IES_LT : case IES_LE : case IES_GT : case IES_GE : case IES_LSHIFT : case IES_RSHIFT : case IES_DIVIDE : case IES_MOD : case IES_MULTIPLY : case IES_LPAREN : case IES_INIT : case IES_LBRAC : State = IES_INTEGER ; if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { if ( IndexReg ) return regsUseUpError ( ErrMsg ) ; IndexReg = TmpReg ; Scale = TmpInt ; if ( checkScale ( Scale , ErrMsg ) ) return true ; IC . popOperator ( ) ; } else { IC . pushOperand ( IC_IMM , TmpInt ) ; } break ; } PrevState = CurrState


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase &


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> insertPass ( & MachineSchedulerID , & <ISA_LIT>FixControlFlowLiveIntervalsID ) ; insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID , false ) ; TargetPassConfig :: addOptimizedRegAlloc ( RegAllocPass


<s> void setIfReturnsVoid ( bool Value ) { ReturnsVoid = Value


<s> if ( mdep_reorg_phase > SH_FIXUP_PCLOAD ) { int slot , credit ; bool jump_to_next = false ; rtx_insn * prev = prev_real_insn ( prev_active_insn ( barrier_or_label ) ) ; for ( slot = <NUM_LIT> , credit = ( <NUM_LIT> << ( CACHE_LOG - <NUM_LIT> ) ) + <NUM_LIT> ; credit >= <NUM_LIT> && prev && NONJUMP_INSN_P ( prev ) ; prev = prev_real_insn ( prev ) ) { jump_to_next = false ; if ( GET_CODE ( PATTERN ( prev ) ) == USE || GET_CODE ( PATTERN ( prev ) ) == CLOBBER ) continue ; if ( rtx_sequence * prev_seq = dyn_cast < rtx_sequence * > ( PATTERN ( prev ) ) ) { prev = prev_seq -> insn ( <NUM_LIT> ) ; if ( INSN_UID ( prev ) == INSN_UID ( next ) ) { jump_to_next = true ; continue ; } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = <NUM_LIT> ; credit -= get_attr_length ( prev ) ; } if ( prev && jump_to_label_p ( prev ) ) { rtx_insn * x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN


<s> switch ( RegKind ) { case IS_SGPR : usesSgprAt ( DwordRegIndex + RegWidth - <NUM_LIT> ) ; break ; case IS_AGPR


<s> if ( vr4130_swap_insns_p ( ready [ nready - <NUM_LIT> ] , ready [ nready - <NUM_LIT> ]

) ) mips_promote_ready ( ready , nready - <NUM_LIT> , nready - <NUM_LIT> ) ;


<s> bool <ISA_LIT>PeepholeSDWA :: runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasSDWA ( ) || ! <STR_LIT> ( ST ) ) { return false ; } MRI = & MF . getRegInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; matchSDWAOperands ( MF )


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' : return C_RegisterClass


<s> return createRegOperand ( <STR_LIT> , Val & <NUM_LIT>


<s> if ( LS1 . isProperty ( ) ) return false ; APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateZEXTi ( A , Width , Bits , XA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst


<s> return new <ISA_LIT>EncodeLiteralsPass ( )


<s> while ( CmpMI != Br -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; if ( CmpMI -> readsRegister ( <STR_LIT> , TRI ) ) break ; } if ( CmpMI -> getOpcode ( ) != <STR_LIT> && CmpMI -> getOpcode ( ) != <STR_LIT> ) return nullptr ; unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred != <STR_LIT> || CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return nullptr ; if ( ! is<ISA_LIT>LowRegister ( Reg )


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; else GVSym = getSymbol ( GV ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) GVSym = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) + GVSym -> getName ( ) ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) GVSym


<s> static bool mips_near_type_p ( const_tree


<s> } if ( RelocOp -> isGlobal ( ) ) { unsigned rt = Is64BitMode ? ( IsPCRel ? <STR_LIT> : <STR_LIT> ) : ( IsPIC ? <STR_LIT> : <STR_LIT> ) ; bool NeedStub = isa < Function > ( RelocOp -> getGlobal ( ) ) ; bool Indirect = gvNeedsNonLazyPtr ( * RelocOp , TM ) ; emitGlobalAddress ( RelocOp -> getGlobal ( ) , rt , RelocOp -> getOffset ( ) , Adj , NeedStub , Indirect ) ; } else if ( RelocOp -> isCPI ( ) ) { unsigned rt = Is64BitMode ? ( IsPCRel ? <STR_LIT> : <STR_LIT> ) : ( IsPCRel ? <STR_LIT> : <STR_LIT> ) ; emitConstPoolAddress ( RelocOp -> getIndex ( ) , rt , RelocOp ->


<s> if ( ( II . Needs & Flag ) == Flag ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintState ( Flag ) << <STR_LIT> << MI ) ; II . Needs |= Flag ; Worklist . push_back ( & MI


<s> assert ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 ,

Op1 , DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ) ;


<s> unsigned getRegisterBitWidthUpperBound (


<s> return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } MCExpr const * InnerExpression ; if ( getParser ( ) . parseExpression ( InnerExpression ) ) return true ; assert ( Parser . getTok ( ) . getKind ( ) == AsmToken :: RParen ) ; Parser . Lex ( ) ; MCExpr const * Expression = <ISA_LIT>MCExpr :: create ( ModifierKind , InnerExpression , isNegated , getContext ( ) ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( Expression , S , E ) ) ; return false


<s> if ( ST -> getCPUDirective ( ) == <STR_LIT> ) { UP . Partial = UP


<s> RegisterTargetMachine < MDSPTargetMachine >


<s> static <ISA_LIT>Operand * CreateMSA128Reg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc

S , SMLoc E , <ISA_LIT>AsmParser & Parser ) {


<s> MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ; if ( IsPreIdx ) DEBUG ( dbgs ( ) << <STR_LIT>


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { if ( IsILP32 ) return create<ISA_LIT>MachObjectWriter ( MachO :: CPU_TYPE_ARM64_32 , MachO ::


<s> static bool isValidIdAtStart ( StringRef Name ) { return StringSwitch < bool > ( Name . lower ( ) ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) . Case ( <STR_LIT> , true ) .

Case ( <STR_LIT> , true ) . Default ( false ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , RA ) ; <ISA_LIT>_MC :: initLLVMToSEHAndCVRegMapping ( X ) ; return X


<s> void setPICStyle ( PICStyles :: Style


<s> const TargetFrameInfo & TFI = * TM . getFrameInfo ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , StackSlot ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Chain , StackSlot , NULL , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ?

<STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ;


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property


<s> if ( GO && Subtarget . useSmallData ( ) && HLOF . isGlobalInSmallSection ( GO , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } bool UsePCRel = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Off = DAG . getConstant ( Offset , dl


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const


<s> static inline bool isCC ( const TargetRegisterClass


<s> EVT InVT = VT . changeVectorElementTypeToInteger ( ) ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( ElemBytes * <NUM_LIT> ) , <STR_LIT> / ElemBytes / <NUM_LIT> ) ; if ( VT != InVT ) { Op1 = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , InVT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; } SDValue Op = DAG . getNode ( Opcode , SDLoc ( N ) , OutVT , Op1 ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N


<s> else bss_data = IRBuilder :: CreateSectionData ( * bss_sect_hdr ) ; uint32_t addralign = config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , pSym . size ( ) ) ; uint64_t size = ObjectBuilder :: AppendFragment ( * frag , * bss_data , addralign ) ; bss_sect_hdr -> setSize ( bss_sect_hdr -> size ( ) + size ) ; ResolveInfo :: Binding binding = ( ResolveInfo :: Binding ) pSym . binding ( ) ; if ( binding == ResolveInfo :: Weak ) binding = ResolveInfo :: Global ; LDSymbol * cpy_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( pSym . name ( ) , ( ResolveInfo :: Type ) pSym . type ( ) , ResolveInfo :: Define , binding , pSym . size ( ) , <NUM_LIT> , FragmentRef :: Create ( * frag , <NUM_LIT> ) , ( ResolveInfo :: Visibility ) pSym . other ( ) ) ; return *


<s> bool inLoopLevel ( MachineBasicBlock & MBB , unsigned LoopLevel , ArrayRef < MachineBasicBlock * > Blocks ) const { auto DomIt = Visited . find ( & MBB ) ; if ( DomIt != Visited . end ( ) && DomIt


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetFI , EVT PtrVT , unsigned SlotSize , int


<s> if ( DEFAULT_ABI != ABI_V4 ) return <NUM_LIT> ; if ( TARGET_SPE && ( SPE_VECTOR_MODE ( mode ) || FLOAT_MODE_P ( mode ) ) ) return <NUM_LIT> ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; else { rtx sum = XEXP ( op , <NUM_LIT> ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , <NUM_LIT> ) ) ; if ( summand < <NUM_LIT> || summand > g_switch_value ) return <NUM_LIT> ; sym_ref = XEXP ( sum , <NUM_LIT> ) ; } return SYMBOL_REF_SMALL_P (


<s> else if ( asm_noperands ( body ) >= <NUM_LIT> ) templ = decode_asm_operands ( body , NULL , NULL , NULL , NULL , NULL ) ; else templ = NULL ; return ( templ && templ [ <NUM_LIT> ] ==


<s> bool <ISA_LIT>ConstantIslands :: fixupUnconditionalBr ( ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! isThumb1 )


<s> return ( unsigned long long ) __builtin_usaddv8qi3 ( ( v8qi ) mm , (


<s> if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO .


<s> Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue (


<s> Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( searchSymbolAlias ( Operands , <STR_LIT> ) )


<s> DenseMap < unsigned , unsigned > SwizzleRemap ; BuildVector = CompactSwizzlableVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = dyn_cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , <STR_LIT> ) ; } SwizzleRemap . clear ( ) ; BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = dyn_cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue


<s> return ( __m128i ) __builtin_ia32_vcvtph2dq128_mask ( __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8


<s> llvm :: copy ( Mask , RMask . begin ( ) ) ; } else { C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( A != C ) { std :: swap ( C , D ) ; ShuffleVectorSDNode :: commuteMask ( RMask ) ; } if ( ! ( A == C && B == D ) ) return false ; unsigned Num128BitChunks = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumEltsPer128BitChunk = NumElts / Num128BitChunks ; assert ( ( NumEltsPer128BitChunk % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j != NumElts ; j += NumEltsPer128BitChunk ) { for ( unsigned i = <NUM_LIT> ; i != NumEltsPer128BitChunk ; ++ i ) { int LIdx = LMask [ i + j ] , RIdx = RMask [ i + j ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ; unsigned NumEltsPer64BitChunk = NumEltsPer128BitChunk


<s> const Align KernArgBaseAlign ( <NUM_LIT> ) ; const unsigned BaseOffset = Subtarget -> getExplicitKernelArgOffset ( F ) ; uint64_t ExplicitArgOffset = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; unsigned AllocSize = DL . getTypeAllocSize ( ArgTy ) ; if ( AllocSize == <NUM_LIT> ) continue ; unsigned ABIAlign = DL . getABITypeAlignment ( ArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + BaseOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + AllocSize ; ArrayRef < Register > OrigArgRegs = VRegs [ i ] ; Register ArgReg = OrigArgRegs . size ( ) == <NUM_LIT> ? OrigArgRegs [ <NUM_LIT> ] : MRI . createGenericVirtualRegister ( getLLTForType ( * ArgTy , DL ) ) ; Align Alignment = commonAlignment ( KernArgBaseAlign , ArgOffset ) ; ArgOffset = alignTo ( ArgOffset , DL . getABITypeAlignment ( ArgTy ) ) ; lowerParameter ( B , ArgTy , ArgOffset , Alignment , ArgReg ) ; if ( OrigArgRegs . size ( ) > <NUM_LIT> ) unpackRegs ( OrigArgRegs , ArgReg , ArgTy , B ) ; ++ i


<s> if ( TREE_CODE ( * node ) != FUNCTION_TYPE && TREE_CODE ( * node ) != FIELD_DECL && TREE_CODE ( * node ) != TYPE_DECL ) { warning ( OPT_Wattributes , <STR_LIT>


<s> LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ; } ) ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto & MI


<s> int DataWidth = ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= <NUM_LIT> && ST -> hasAVX2 (


<s> EVT IntTy = Ty . changeVectorElementTypeToInteger ( ) ; EVT ExtIntTy = getPackedSVEVectorVT ( IntTy . getVectorElementCount ( ) ) ; if ( ExtIntTy . getVectorElementType ( ) . getScalarSizeInBits ( ) < IntTy . getVectorElementType ( ) . getScalarSizeInBits ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue LHS = DAG . getAnyExtOrTrunc ( DAG . getBitcast ( IntTy , N -> getOperand ( <NUM_LIT> ) )


<s> virtual const TargetRegisterInfo & getRegisterInfo (


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Zero , Zero , LHS , RHS ) ; SDValue Lo ( Hi . getNode ( ) ,


<s> if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) return tryReplaceLoad ( <STR_LIT> , MI ) ; break ; case


<s> if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp , C . CCMask & <STR_LIT> ) ; } SDValue CCReg = emitCmp ( DAG , DL , C ) ; SDValue Ops [ ] = { TrueOp , FalseOp , DAG . getTargetConstant ( C . CCValid , DL , <STR_LIT> ) , DAG . getTargetConstant ( C . CCMask , DL , <STR_LIT> ) , CCReg } ; return DAG . getNode ( <STR_LIT> , DL ,


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK


<s> unsigned Size = getSizeInBits ( Reg , MRI , TRI ) ; return <STR_LIT> ( <STR_LIT> , Size


<s> unsigned Expcnt = ( <ISA_LIT>mm16 >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lgkmcnt = ( <ISA_LIT>mm16 >> <NUM_LIT> ) & <NUM_LIT> ; bool NeedSpace = false ; if ( Vmcnt != <NUM_LIT> ) { O << <STR_LIT> << Vmcnt << ')' ; NeedSpace = true ; } if ( Expcnt != <NUM_LIT> ) { if ( NeedSpace ) O


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified =


<s> assert ( ! FuncTy -> isVarArg ( ) && <STR_LIT> ) ; FunctionType * NewFuncTy = FunctionType :: get ( FuncTy -> getReturnType ( ) , Arguments , FuncTy -> isVarArg ( ) ) ; Function * NewFunc = Function :: Create ( NewFuncTy , Func -> getLinkage ( ) , Func -> getAddressSpace ( ) ) ; M . getFunctionList ( ) . insertAfter ( Func -> getIterator ( ) , NewFunc ) ; if ( KeepOriginal ) { NewFunc -> setName ( Func -> getName ( ) + <STR_LIT> ) ; ValueToValueMapTy VMap ; for ( Function :: arg_iterator FuncArg = Func -> arg_begin ( ) , FuncEnd = Func -> arg_end ( ) , NewFuncArg = NewFunc -> arg_begin ( ) ; FuncArg != FuncEnd ; ++ FuncArg , ++ NewFuncArg ) { VMap [ FuncArg ] = NewFuncArg ; } SmallVector < ReturnInst * , <NUM_LIT> > Returns ; CloneFunctionInto ( NewFunc , Func , VMap , CloneFunctionChangeType :: GlobalChanges , Returns ) ; } else { NewFunc -> copyAttributesFrom ( Func ) ; NewFunc -> setComdat ( Func -> getComdat ( ) ) ; NewFunc -> setAttributes ( NAttrs ) ; NewFunc -> takeName ( Func ) ; NewFunc -> getBasicBlockList ( ) . splice ( NewFunc -> begin ( ) , Func -> getBasicBlockList ( ) ) ; for ( Function :: arg_iterator FuncArg = Func -> arg_begin ( ) , FuncEnd = Func -> arg_end ( ) , NewFuncArg = NewFunc -> arg_begin ( ) ; FuncArg != FuncEnd ; ++ FuncArg , ++ NewFuncArg ) { FuncArg -> replaceAllUsesWith ( NewFuncArg ) ; } SmallVector < std :: pair < unsigned , MDNode * > , <NUM_LIT> > MDs ; Func -> getAllMetadata ( MDs ) ; for ( auto MD : MDs ) NewFunc -> addMetadata ( MD . first , * MD . second ) ; } Value * ImplicitOffset = NewFunc -> arg_begin ( ) + ( NewFunc -> arg_size (


<s> SDValue SP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; Chain = SP . getValue ( <NUM_LIT> ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SP , Size ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP ) ; SDValue Ops [ <NUM_LIT> ] = { NewVal , Chain


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return I -> getFlag ( MachineInstr :: FrameSetup ) || I -> getFlag ( MachineInstr


<s> ConstantInt * One = Builder . getInt32 ( <NUM_LIT> ) ; Value * JQ = One ; if ( IsSigned ) { JQ = Builder . CreateXor ( Num , Den ) ; JQ = Builder . CreateAShr ( JQ , Builder . getInt32 ( <NUM_LIT> ) ) ; JQ = Builder . CreateOr ( JQ , One ) ; } Value * IA = Num ; Value * IB = Den ; Value * FA = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IA , F32Ty ) : Builder . CreateUIToFP ( IA , F32Ty ) ; Value * FB = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IB , F32Ty ) : Builder . CreateUIToFP ( IB , F32Ty ) ; Value * RCP = Builder . CreateFDiv ( ConstantFP :: get ( F32Ty , <NUM_LIT> ) , FB ) ; Value * FQM = Builder . CreateFMul ( FA , RCP ) ; CallInst * FQ = Builder . CreateIntrinsic ( <STR_LIT> , { FQM } ) ; FQ -> copyFastMathFlags ( Builder . getFastMathFlags ( ) ) ; Value * FQNeg = Builder . CreateFNeg ( FQ ) ; Value * FR = Builder . CreateIntrinsic ( <STR_LIT> , { FQNeg , FB , FA } , FQ ) ; Value * IQ = IsSigned ? Builder . CreateFPTo<ISA_LIT> ( FQ , I32Ty ) : Builder . CreateFPToUI ( FQ , I32Ty ) ; FR = Builder . CreateIntrinsic ( <STR_LIT> , { FR } , FQ ) ; FB = Builder . CreateIntrinsic ( <STR_LIT> , { FB } , FQ ) ; Value * CV = Builder . CreateFCmpOGE (


<s> return __builtin_ia32_vtestnzcpd ( ( __v2df ) __M , (


<s> return ( int16x4_t ) __builtin_aarch64_sqshrn_nv4si (


<s> union { vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] * bb .


<s> Subtarget ( * this , M , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , TLInfo ( * this ) { if ( Subtarget . hasABICall ( ) ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getCodeModel ( ) == CodeModel :: Default ) setCodeModel (


<s> SDVTList VTList = DAG . getVTList ( VT , <STR_LIT> ) ; if ( Offset ) Ptr = DAG . getNode ( <STR_LIT> , DL , BasePtrVT , Ptr , DAG . getConstant ( Offset , BasePtrVT ) ) ; SDValue Ops [ ] = {


<s> switch ( Kind ) { case FK_SecRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_SecRel_4 : case FK_Data_4 : case FK_PCRel_4 : return <NUM_LIT> ; case FK_SecRel_8 : case FK_Data_8 : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> debug ( <STR_LIT> ) ; return true ; } mcInst . setOpcode ( insn . instructionID ) ; int index ; insn . numImmediatesTranslated = <NUM_LIT> ; for ( index = <NUM_LIT> ; index < <ISA_LIT>_MAX_OPERANDS ; ++ index ) { if ( insn . operands [ index ] . encoding != ENCODING_NONE ) { if ( translateOperand ( mcInst , insn . operands [ index ] , insn , Dis ) ) { return true ; } } } return


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const


<s> static void BuildEntryBlock ( Function & F ) { BasicBlock & EntryBlock = F . getEntryBlock ( ) ; BasicBlock * BB = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F , & EntryBlock ) ; BuildSignature ( * BB , F ) ; BranchInst :: Create ( & EntryBlock


<s> return std :: max ( Log2 ( std :: max ( PostAlign


<s> case <STR_LIT> : return - ( int8_t ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return - <NUM_LIT> ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return <NUM_LIT> ; break ; case <STR_LIT> : { MachineInstr * Prev = MI -> getPrevNode ( ) ; assert ( Prev -> getOpcode ( ) == <STR_LIT> && Prev -> getOperand ( <NUM_LIT> ) .

getReg ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ( Value & ( <NUM_LIT> << Shift ) ) >> Shift ) ) ) ; tmpInst . setLoc


<s> } SmallVector < unsigned , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = Call -> getNumArgOperands ( ) ; i < e ; ++ i ) { Value * V = Call -> getArgOperand ( i ) ; <STR_LIT> ArgTy = getSimpleType ( V -> getType ( ) ) ; if ( ArgTy == <STR_LIT> ) return false ; const AttributeList & Attrs = Call -> getAttributes ( ) ; if ( Attrs . hasParamAttribute ( i , Attribute :: ByVal ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftSelf ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftError ) || Attrs . hasParamAttribute ( i , Attribute :: InAlloca ) || Attrs . hasParamAttribute ( i , Attribute :: Nest ) ) return false ; unsigned Reg ; if ( Attrs . hasParamAttribute ( i , Attribute :: SExt ) ) Reg = getRegForSignedValue ( V ) ; else if ( Attrs . hasParamAttribute ( i , Attribute :: ZExt ) ) Reg = getRegForUnsignedValue ( V ) ; else Reg = getRegForValue ( V ) ; if ( Reg == <NUM_LIT> ) return false ; Args . push_back ( Reg ) ; } auto MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; if ( ! IsVoid ) MIB . addReg ( ResultReg , RegState :: Define ) ; if ( IsDirect ) MIB . addGlobalAddress ( Func ) ; else MIB . addReg ( getRegForValue ( Call -> getCalledValue ( ) ) ) ; for ( unsigned ArgReg : Args ) MIB .


<s> Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; bool UseAligned = ! NeedsAligna && ( NeedAlign <= HasAlign ) ; unsigned StoreOpc = UseAligned ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcR , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ; B . erase


<s> case AMDGPU :: V_MOV_B32_e32 : case AMDGPU :: V_MOV_B32_e64 : return true ; default : return


<s> I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) != <STR_LIT> ) continue ; assert ( N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDValue Lo = N -> getOperand ( <NUM_LIT> ) ; SDValue Hi = N -> getOperand ( <NUM_LIT> ) ; SDValue VL = N -> getOperand ( <NUM_LIT> ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && VT . isScalableVector ( ) && Lo . getValueType ( ) == <STR_LIT> && Hi . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( N ) ; int FI = FuncInfo -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ; SDValue StackSlot = CurDAG -> getFrameIndex ( FI , TLI . getPointerTy ( CurDAG -> getDataLayout ( ) , CurDAG -> getDataLayout ( )


<s> } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <STR_LIT> FPOpToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( Subtarget . hasStdExtF ( ) && Subtarget . is64Bit ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget . hasStdExtD ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto Op : FPOpToExtend ) setOperationAction ( Op , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . isInteger ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ; Entry . isSExt


<s> if ( Invert ) { Register Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . add ( Src2 ) ; if ( BitSize <= <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( - <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ; else { Register Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp2 ) . addImm ( - <NUM_LIT> ) ; } } else if ( BinOpcode ) BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . add ( Src2 ) ; else if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> - BitSize ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . add ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor (


<s> static bool isInt32Immediate ( SDValue N , unsigned & Imm ) { return isInt32Immediate ( N . getNode ( ) , Imm


<s> if ( IsPIC && AttachToOperandIdx ) ErrMsg = <STR_LIT> ; else ErrMsg =