<s> if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isBottom ( ) || LS1 . isProperty ( ) ) return false ; APInt A , SA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateSplati ( A , Bits , Count , SA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( SA


<s> if ( ! getCell ( R1 , Inputs , LS1 ) || ! getCell ( R2 , Inputs , LS2 ) ) return false ; if ( LS1 . isProperty ( ) ) { if ( LS1 . properties ( ) & ConstantProperties :: Zero ) return ! ( Result = LS2 ) . isBottom ( ) ; return false ; } if ( LS2 . isProperty ( ) ) { if ( LS2 . properties ( ) & ConstantProperties :: Zero ) return ! ( Result = LS1 ) . isBottom ( ) ; return false


<s> if ( LS1 . isProperty ( ) ) return false ; APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateZEXTi ( A , Width , Bits , XA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst


<s> RC = L ; return ! RC . isBottom ( ) ; } bool Eval = evaluate ( R , L , RC ) ; return Eval && ! RC .


<s> APInt <ISA_LIT>ConstEvaluator :: getCmpImm ( unsigned Opc , unsigned OpX , const MachineOperand & MO ) { bool Signed = false ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : Signed = true ; break ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Signed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool has ( Register R ) const { if ( ! R . isVirtual ( ) ) return true ; MapType :: const_iterator F = Map . find ( R


<s> uint32_t N = L . IsSpecial ? sizeof L . Properties : L . Size * sizeof ( const Constant * ) ; memcpy ( Values , L . Values , N ) ; Kind = L


<s> uint32_t N = L . IsSpecial ? sizeof L . Properties : L . Size * sizeof ( const Constant * ) ; memcpy ( Values , L . Values , N ) ; Kind = L . Kind


<s> From -> removeSuccessor ( To ) ; for ( MachineInstr & PN : To -> phis ( ) ) { int N = PN . getNumOperands ( ) - <NUM_LIT> ; while ( N > <NUM_LIT> ) { if ( PN . getOperand ( N + <NUM_LIT> ) . getMBB ( ) == From ) { PN . removeOperand ( N


<s> void MachineConstPropagator :: removeCFGEdge ( MachineBasicBlock * From , MachineBasicBlock * To ) { From -> removeSuccessor ( To ) ; for ( MachineInstr & PN : To -> phis ( ) ) { int N = PN . getNumOperands ( ) - <NUM_LIT> ; while ( N > <NUM_LIT> ) { if ( PN . getOperand ( N + <NUM_LIT> ) . getMBB ( ) == From ) { PN . removeOperand ( N


<s> void <ISA_LIT>ConstEvaluator :: replaceWithNop ( MachineInstr & MI ) { MI . setDesc ( HII . get ( <STR_LIT> ) ) ; while ( MI . getNumOperands ( ) > <NUM_LIT>


<s> if ( InstrExec . count ( & MI ) ) { if ( MI . isBranch ( ) && ! HaveTargets ) continue ; Changed |= MCE . rewrite ( MI , Cells ) ; } } for ( auto I = B -> begin ( ) , E = B -> end ( ) ; I != E ; ++ I ) { if ( I -> isPHI ( ) ) continue ; auto P = I ; while ( ++ P != E ) if ( P -> isPHI ( ) ) break ; if ( P == E ) break ; B -> splice ( I , B , P ) ; -- I ; } if ( HaveTargets ) { SmallVector < MachineBasicBlock * , <NUM_LIT> > ToRemove ; for ( MachineBasicBlock * SB : B -> successors ( ) ) { if ( ! Targets . count ( SB ) ) ToRemove . push_back (

const_cast < MachineBasicBlock * > ( SB ) ) ;


<s> void update ( Register R , const LatticeCell


<s> while ( It != End ) { const MachineInstr & MI = * It ; InstrExec . insert ( & MI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( EvalOk ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printMBBReference ( B ) << <STR_LIT> << MI ) ; EvalOk = EvalOk && MCE . evaluate ( MI , Cells , Targets , FallsThru ) ; if ( ! EvalOk ) FallsThru = true ; if ( ! FallsThru ) break ; ++ It ; } if ( B . mayHaveInlineAsmBr ( ) ) EvalOk = false ; if ( EvalOk ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThru ) { const MachineFunction & MF = * B . getParent ( ) ; MachineFunction :: const_iterator BI = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BI ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { Targets . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; for ( const MachineBasicBlock * SB : B . successors ( ) ) Targets . insert ( SB ) ; } for ( const MachineBasicBlock * TB : Targets ) { unsigned TBN = TB -> getNumber ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( B ) << <STR_LIT> << printMBBReference ( * TB ) <<


<s>
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
Outputs
)
dbgs
(
)
<<
' '
<<
I
.
second
;
dbgs
(
)
<<
'\n'
;
}
}
)
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
MO
.
isDef
(
)
)
continue
;
RegisterSubReg
DefR
(
MO
)
;
if
(
!
DefR
.
Reg
.
isVirtual
(
)
)
continue
;
bool
Changed
=
false
;
if
(
!
Eval
)
{
const
LatticeCell
&
T
=
Cells
.
get
(
DefR
.
Reg
)
;
Changed
=
!
T
.
isBottom
(
)
;
Cells
.
update
(
DefR
.
Reg
,
Bottom
)
;
}
else


<s> return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printMBBReference ( * MB ) << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; RegisterSubReg UseR ( SO ) ; if ( ! UseR . Reg . isVirtual ( ) ) goto Bottomize ; if ( ! Cells . has ( UseR . Reg ) ) continue ; LatticeCell SrcC ; bool Eval = MCE . evaluate ( UseR , Cells . get ( UseR . Reg ) , SrcC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printReg ( UseR . Reg , & MCE . TRI , UseR . SubReg ) << SrcC << '\n' ) ; Changed |= Eval ? DefC . meet ( SrcC ) : DefC . setBottom ( ) ; Cells . update ( DefR . Reg , DefC


<s> SmallVector < APInt , <NUM_LIT> > LoVs ( LN ) , HiVs ( HN ) ; for ( unsigned i = <NUM_LIT> ; i < LN ; ++ i ) { bool Eval = constToInt ( LSL . Values [ i ] , LoVs [ i ] ) ; if ( ! Eval ) return false ; assert ( LoVs [ i ] . getBitWidth ( ) == <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < HN ; ++ i ) { bool Eval = constToInt ( LSH . Values [ i ] , HiVs [ i ] ) ; if ( ! Eval ) return false ; assert ( HiVs [ i ] . getBitWidth ( ) == <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < HiVs . size ( ) ; ++ i ) { APInt HV = HiVs [ i ] . zextOrSelf ( <NUM_LIT> )


<s> if ( F != Map . end ( ) ) return F -> second ; return Top


<s> const LatticeCell & get ( unsigned R ) const { if ( ! Register :: isVirtualRegister ( R


<s> bool MachineConstEvaluator :: getCell ( const RegisterSubReg & R , const CellMap & Inputs , LatticeCell & RC ) { if ( ! Register :: isVirtualRegister ( R . Reg ) ) return false ; const LatticeCell & L = Inputs .


<s> if ( ! Register :: isVirtualRegister ( R ) ) return true ; MapType :: const_iterator F = Map . find ( R


<s> dbgs ( ) << '\n' ; } } ) ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterSubReg DefR ( MO ) ; if ( ! Register :: isVirtualRegister ( DefR . Reg ) ) continue ; bool Changed = false ; if ( ! Eval ) { const LatticeCell & T = Cells . get ( DefR . Reg ) ; Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; } else { if ( ! Outputs . has ( DefR . Reg ) ) continue ; LatticeCell RC = Cells . get ( DefR . Reg ) ; Changed = RC . meet ( Outputs . get ( DefR . Reg )


<s> bool Changed = false ; if ( DefR . SubReg ) { Bottomize : const LatticeCell & T = Cells . get ( DefR . Reg ) ; Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; if ( Changed ) visitUsesOf ( DefR . Reg ) ; return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printMBBReference ( * MB ) << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; RegisterSubReg UseR ( SO ) ; if ( ! Register :: isVirtualRegister ( UseR . Reg ) ) goto Bottomize ; if ( ! Cells . has ( UseR . Reg ) ) continue ; LatticeCell SrcC ; bool Eval = MCE . evaluate ( UseR , Cells . get ( UseR . Reg ) , SrcC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printReg ( UseR . Reg , & MCE . TRI , UseR . SubReg ) << SrcC << '\n' ) ; Changed |= Eval ? DefC . meet ( SrcC ) : DefC . setBottom ( ) ; Cells . update ( DefR . Reg ,


<s> LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printMBBReference ( * MB ) << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; RegisterSubReg UseR ( SO ) ; if ( ! Register :: isVirtualRegister ( UseR . Reg ) ) goto Bottomize ; if ( ! Cells . has ( UseR . Reg )


<s> bool MachineConstPropagator :: run ( MachineFunction & MF ) { DEBUG ( MF . print ( dbgs ( ) << <STR_LIT> , nullptr ) ) ; MRI = & MF . getRegInfo ( ) ; Cells . clear ( ) ; EdgeExec . clear ( ) ; InstrExec . clear ( ) ; assert ( FlowQ . empty ( ) ) ; propagate ( MF ) ; bool Changed = rewrite ( MF ) ; DEBUG


<s> MachineBasicBlock :: const_iterator It = SB -> begin ( ) , End = SB -> end ( ) ; while ( It != End && It -> isPHI ( ) ) { InstrExec . insert ( & * It ) ; visitPHI ( * It ) ; ++ It ; } while ( It != End && It -> isDebugValue ( ) ) ++ It ; assert ( It == End || ! It -> isPHI ( ) ) ; if ( It != End && InstrExec . count ( & * It ) ) continue ; while ( It != End && ! It -> isBranch ( ) ) { if ( ! It -> isDebugValue ( ) ) { InstrExec . insert ( & * It ) ; visitNonBranch ( * It ) ; } ++ It ; } if ( It


<s> if ( DefR . SubReg ) { Bottomize : const LatticeCell & T = Cells . get ( DefR . Reg ) ; Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; if ( Changed ) visitUsesOf ( DefR . Reg ) ; return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN


<s> void MachineConstPropagator :: visitUsesOf ( unsigned Reg ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , & MCE . TRI ) << Cells . get ( Reg ) << '\n' ) ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( Reg ) ) { if ( ! InstrExec . count ( & MI ) ) continue ; if ( MI . isPHI ( ) ) visitPHI ( MI ) ; else if ( ! MI . isBranch


<s> if ( ! InstrExec . count ( & MI ) ) continue ; if ( MI . isPHI ( ) ) visitPHI ( MI ) ; else if ( ! MI . isBranch ( ) ) visitNonBranch


<s> FallsThru = ! BrI . isUnconditionalBranch ( ) ; return false ; } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( <NUM_LIT> ) ; Register PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; if ( Props & ConstantProperties :: Zero ) CFalse = true ; else if ( Props & ConstantProperties :: NonZero ) CTrue = true ; if ( ! CTrue && ! CFalse )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> LatticeCell ( ) : Kind ( Top ) , Size ( <NUM_LIT> ) ,


<s> void print ( const TargetRegisterInfo * TRI = nullptr )


<s> unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } unsigned NumOp = MI . getNumOperands ( ) ; if ( NumOp == <NUM_LIT> ) return false ; bool AllDefs , Changed ; Changed = rewriteHexConstDefs ( MI , Inputs , AllDefs ) ; if ( ! AllDefs ) Changed |=


<s> case <STR_LIT> : case <STR_LIT> : Signed = true ; break ; } Register DefR ( MI . getOperand ( <NUM_LIT> ) ) ; unsigned BW = getRegBitWidth ( DefR . Reg ) ; LatticeCell RC = Outputs . get ( DefR . Reg ) ; bool Eval = Signed ? evaluateSEXTr ( R1 , BW , Bits , Inputs , RC ) : evaluateZEXTr ( R1 , BW , Bits , Inputs , RC ) ; if ( ! Eval ) return false ; Outputs . update ( DefR


<s> unsigned Opc = MI . getOpcode ( ) ; unsigned Bits ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } bool Signed = false ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Signed = true ; break ; } Register DefR ( MI . getOperand ( <NUM_LIT> ) ) ; unsigned BW = getRegBitWidth ( DefR . Reg ) ; LatticeCell RC = Outputs . get ( DefR . Reg ) ; bool Eval = Signed ? evaluateSEXTr ( R1 , BW , Bits , Inputs , RC

) : evaluateZEXTr ( R1 , BW , Bits , Inputs , RC ) ;


<s> bool MachineConstEvaluator :: getCell ( const RegisterSubReg & R , const CellMap & Inputs , LatticeCell & RC ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( R . Reg ) ) return false ; const LatticeCell & L = Inputs . get ( R . Reg ) ; if ( ! R . SubReg


<s> bool MachineConstEvaluator :: getCell ( const RegisterSubReg & R , const CellMap & Inputs , LatticeCell & RC ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( R . Reg ) ) return false ; const LatticeCell & L = Inputs . get ( R . Reg ) ; if ( ! R . SubReg ) { RC = L ; return ! RC . isBottom


<s>
CellMap
Outputs
;
bool
Eval
=
MCE
.
evaluate
(
MI
,
Cells
,
Outputs
)
;
LLVM_DEBUG
(
{
if
(
Eval
)
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
Outputs
)
dbgs
(
)
<<
' '
<<
I
.
second
;
dbgs
(
)
<<
'\n'
;
}
}
)
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
MO
.
isDef
(
)
)
continue
;
RegisterSubReg
DefR
(
MO
)


<s> const MachineBasicBlock * MB = PN . getParent ( ) ; unsigned MBN = MB -> getNumber ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MB ) << <STR_LIT> << PN ) ; const MachineOperand & MD = PN . getOperand ( <NUM_LIT> ) ; RegisterSubReg DefR ( MD ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( DefR . Reg ) ) ; bool Changed = false ; if ( DefR . SubReg ) { Bottomize : const LatticeCell & T = Cells . get ( DefR . Reg ) ; Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; if ( Changed ) visitUsesOf ( DefR . Reg ) ; return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printMBBReference ( * MB ) << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; RegisterSubReg UseR ( SO ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( UseR . Reg ) ) goto Bottomize ; if ( ! Cells . has ( UseR . Reg ) ) continue ; LatticeCell


<s> for ( MachineBasicBlock * B : POT ) { SetVector < const MachineBasicBlock * > Targets ; bool HaveTargets = computeBlockSuccessors ( B , Targets ) ; for ( MachineInstr & MI : llvm :: reverse ( * B ) ) { if ( InstrExec . count ( & MI ) ) { if ( MI . isBranch ( ) && ! HaveTargets ) continue ; Changed |= MCE . rewrite ( MI , Cells ) ; } } for ( auto I = B -> begin ( ) , E = B -> end ( ) ; I != E ; ++ I ) { if ( I -> isPHI (


<s> bool Changed = convertToProperty ( ) ; uint32_t Ps = properties ( ) ; if ( Ps == ( Ps & Property ) ) return


<s> const_iterator begin ( ) const { return Map .


<s> bool MachineConstPropagator :: computeBlockSuccessors ( const MachineBasicBlock * MB , SetVector < const MachineBasicBlock * > & Targets ) { MachineBasicBlock :: const_iterator FirstBr = MB -> end ( ) ; for ( const MachineInstr & MI : * MB ) { if ( MI . isDebugValue ( ) ) continue ; if ( MI . isBranch ( ) ) { FirstBr = MI . getIterator ( ) ; break ; } } Targets . clear ( ) ; MachineBasicBlock :: const_iterator End = MB -> end ( ) ; bool DoNext = true ; for ( MachineBasicBlock :: const_iterator I = FirstBr ; I != End ; ++ I ) { const MachineInstr & MI = * I ; if ( MI . isDebugValue ( ) ) continue ; if ( ! InstrExec . count ( & MI ) ) continue ; bool Eval = MCE . evaluate ( MI , Cells , Targets , DoNext ) ; if ( ! Eval ) return false ; if ( ! DoNext )


<s> bool LatticeCell :: convertToProperty ( ) { if ( isProperty ( ) ) return false ; uint32_t Everything = ConstantProperties :: Everything ; uint32_t Ps = ! isTop ( ) ? properties ( ) :


<s> bool LatticeCell :: convertToProperty ( ) { if ( isProperty ( ) ) return false ; uint32_t Everything = ConstantProperties :: Everything ; uint32_t Ps = ! isTop ( ) ? properties ( ) : Everything ; if ( Ps != ConstantProperties :: Unknown ) { Properties = Ps


<s> if ( CI -> isNegative ( ) ) return Props | NegOrZero ; return Props | PosOrZero ; } if ( isa < ConstantFP > ( C ) ) { const ConstantFP * CF = cast < ConstantFP > ( C ) ; uint32_t Props = CF -> isNegative ( ) ? ( NegOrZero | NonZero ) : PosOrZero ; if ( CF -> isZero ( ) ) return ( Props & ~ NumericProperties ) | ( Zero | Finite ) ; Props = ( Props & ~ NumericProperties ) | NonZero ; if ( CF -> isNaN ( ) ) return ( Props & ~ NumericProperties ) | NaN ; const APFloat & Val = CF -> getValueAPF ( ) ; if ( Val . isInfinity ( ) ) return ( Props & ~ NumericProperties ) | Infinity ; Props |= Finite ; return


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( CI -> isZero ( ) ) return Zero | PosOrZero | NegOrZero | Finite ; uint32_t Props = ( NonZero | Finite ) ; if ( CI -> isNegative ( ) ) return Props | NegOrZero ; return Props | PosOrZero ; } if ( isa < ConstantFP > ( C ) ) { const ConstantFP * CF = cast < ConstantFP > ( C ) ; uint32_t Props = CF -> isNegative ( ) ? ( NegOrZero | NonZero ) : PosOrZero ; if ( CF -> isZero ( ) ) return ( Props & ~ NumericProperties ) | ( Zero | Finite ) ; Props = ( Props & ~ NumericProperties ) | NonZero ; if ( CF -> isNaN ( ) ) return ( Props & ~ NumericProperties ) | NaN ; const APFloat & Val = CF -> getValueAPF ( ) ; if ( Val . isInfinity ( ) ) return ( Props & ~ NumericProperties ) | Infinity ; Props |= Finite ; return Props ; } return Unknown


<s> Targets . insert ( BrI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : Undetermined : FallsThru = ! BrI . isUnconditionalBranch ( ) ; return false ; } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( <NUM_LIT> ) ; Register PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; ; if ( Props & ConstantProperties :: Zero ) CFalse =


<s> bool MachineConstEvaluator :: evaluateANDii ( const APInt & A1 , const APInt & A2 , APInt & Result ) { Result = A1 &


<s> bool MachineConstEvaluator :: evaluateANDii ( const APInt & A1 , const APInt & A2 , APInt & Result ) { Result = A1 & A2 ; return true


<s> bool MachineConstEvaluator :: evaluateANDri ( const Register & R1 , const APInt & A2 , const CellMap & Inputs , LatticeCell & Result ) { assert ( Inputs . has ( R1 . Reg ) ) ; if ( A2 == - <NUM_LIT> ) return getCell ( R1 , Inputs , Result ) ; if ( A2 == <NUM_LIT> )


<s> if ( LS2 . isBottom ( ) || LS2 . isProperty ( ) ) return false ; APInt A ; for ( unsigned i = <NUM_LIT> ; i < LS2 . size ( ) ; ++ i ) { LatticeCell RC ; bool Eval = constToInt ( LS2 . Values [ i ] , A ) && evaluateANDri ( R1 , A , Inputs , RC ) ; if ( ! Eval )


<s> bool MachineConstEvaluator :: evaluateCLBi ( const APInt & A1 , bool Zeros , bool Ones , APInt & Result ) { unsigned BW = A1 . getBitWidth ( ) ; if ( ! Zeros && ! Ones ) return false ; unsigned Count = <NUM_LIT> ; if ( Zeros && ( Count == <NUM_LIT> ) ) Count = A1 . countLeadingZeros ( ) ; if ( Ones && ( Count == <NUM_LIT> ) )


<s> Result = false ; unsigned W1 = A1 . getBitWidth ( ) ; unsigned W2 = A2 . getBitWidth ( ) ; unsigned MaxW = ( W1 >= W2 ) ? W1 : W2 ; if ( Cmp & Comparison :: U ) { const APInt Zx1 = A1 . zextOrSelf ( MaxW ) ; const APInt Zx2 = A2 . zextOrSelf ( MaxW ) ; if ( Cmp & Comparison :: L ) Result = Zx1 . ult ( Zx2 ) ; else if ( Cmp & Comparison :: G ) Result =


<s> if ( Cmp & Comparison :: EQ ) { if ( APInt :: isSameValue ( A1 , A2 ) ) return ( Result = true ) ; } assert ( ( Cmp & ( Comparison :: L | Comparison :: G ) ) && <STR_LIT> ) ; Result = false ; unsigned W1 = A1 . getBitWidth ( ) ; unsigned W2 = A2 . getBitWidth ( ) ; unsigned MaxW = ( W1 >= W2 ) ? W1 : W2 ; if ( Cmp & Comparison ::


<s> if ( Props & ConstantProperties :: Zero ) Result = ( Cmp & Comparison :: EQ ) ; else if ( Props & ConstantProperties :: NonZero ) Result = ( Cmp & Comparison :: G ) || ( Cmp == Comparison :: NE ) ; else return false ; return true ; } if ( Props & ConstantProperties :: Zero ) { Result = ( Cmp & Comparison :: L ) || ( Cmp == Comparison :: NE ) ; return true ; } return false ; } if ( Props & ConstantProperties :: Zero ) { if ( A2 == <NUM_LIT> ) Result = ( Cmp & Comparison :: EQ ) ; else Result = ( Cmp == Comparison :: NE ) || ( ( Cmp & Comparison :: L ) && ! A2 . isNegative ( ) ) || ( ( Cmp & Comparison :: G ) && A2 . isNegative ( ) ) ; return true ; } if ( Props & ConstantProperties :: PosOrZero ) { if ( ! A2 . isNegative ( ) ) return false ; Result = ( Cmp & Comparison :: G ) || ( Cmp == Comparison :: NE ) ; return


<s> } return false ; } bool Poz1 = ( Props1 & P :: PosOrZero ) , Poz2 = ( Props2 & P :: PosOrZero ) ; bool Nez1 = ( Props1 & P :: NegOrZero ) , Nez2 = ( Props2 & P :: NegOrZero ) ; if ( Nez1 && Poz2 ) { if ( NonZero1 || NonZero2 ) { Result = ( Cmp & Comparison :: L ) ; return true ; } if ( ( Cmp & Comparison :: EQ ) && ( Cmp & Comparison :: L ) ) return ( Result = true ) ; } if ( Poz1 && Nez2 ) { if ( NonZero1 || NonZero2 ) { Result = ( Cmp & Comparison :: G ) ; return true


<s> bool IsTrue = true , IsFalse = true ; for ( unsigned i = <NUM_LIT> ; i < LS . size ( ) ; ++ i ) { bool Res ; bool Computed = constToInt ( LS . Values [ i ] , A ) && evaluateCMPpi ( NegCmp , Props2 , A , Res ) ; if ( ! Computed ) return false ; IsTrue &= Res ; IsFalse &= ! Res ; } assert ( ! IsTrue || ! IsFalse


<s> if ( ! getCell ( R1 , Inputs , LS1 ) || ! getCell ( R2 , Inputs , LS2 ) ) return false ; bool IsProp1 = LS1 . isProperty ( ) ; bool IsProp2 = LS2 . isProperty ( ) ; if ( IsProp1 ) { uint32_t Prop1 = LS1 . properties ( ) ; if ( IsProp2 ) return evaluateCMPpp ( Cmp , Prop1 , LS2 . properties ( ) , Result ) ; uint32_t NegCmp = Comparison :: negate ( Cmp ) ; return evaluateCMPrp ( NegCmp , R2 , Prop1


<s> unsigned BW = A1 . getBitWidth ( ) ; if ( ! Zeros && ! Ones ) return false ; unsigned Count = <NUM_LIT> ; if ( Zeros && ( Count == <NUM_LIT> ) ) Count = A1 . countTrailingZeros ( ) ; if ( Ones && ( Count == <NUM_LIT> ) ) Count = A1 . countTrailingOnes ( ) ; Result = APInt ( BW , static_cast < uint64_t > ( Count ) , false ) ; return


<s> return true ; } return false ; } APInt A , CA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateEXTRACTi ( A , Bits , Offset , Signed , CA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( CA ) ; Result . add


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Classic = true ; break ; default : return false ; } if ( Classic ) { const MachineOperand & Src1 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Src2 = MI . getOperand ( <NUM_LIT> ) ; bool


<s> assert ( Inputs . has ( CR . Reg ) ) ; LatticeCell LS ; if ( ! getCell ( CR , Inputs , LS ) ) return false ; uint32_t Ps = LS . properties ( ) ; unsigned TakeOp ; if ( Ps & ConstantProperties :: Zero ) TakeOp = <NUM_LIT> ; else if ( Ps & ConstantProperties :: NonZero ) TakeOp = <NUM_LIT> ; else return false ; const MachineOperand & ValOp = MI . getOperand ( TakeOp ) ; Register DefR ( MI . getOperand ( <NUM_LIT> ) ) ; LatticeCell RC = Outputs . get ( DefR . Reg ) ; if ( ValOp . isImm ( ) ) { int64_t V = ValOp . getImm ( ) ; unsigned W = getRegBitWidth ( DefR . Reg ) ; APInt A ( W , V , true ) ; const Constant * C = intToConst ( A ) ; RC . add ( C ) ; Outputs . update ( DefR . Reg , RC ) ; return true ; } if ( ValOp . isReg ( ) ) { Register R ( ValOp ) ; const LatticeCell & LR = Inputs .


<s> APInt A ( <NUM_LIT> , Src2 . getImm ( ) , true ) ; Eval = evaluateANDri ( R1 , A , Inputs , RC ) ; break ; } case <STR_LIT> : case <STR_LIT> : Eval = evaluateORrr ( R1 , Register ( Src2 ) , Inputs , RC ) ; break ; case <STR_LIT> : { APInt A ( <NUM_LIT> , Src2 . getImm ( ) , true ) ; Eval = evaluateORri ( R1 , A , Inputs , RC ) ; break ; } case <STR_LIT> : case


<s> for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateORii ( A , A2 , ResA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( ResA ) ; Result . add


<s> for ( unsigned i = <NUM_LIT> ; i < LS2 . size ( ) ; ++ i ) { LatticeCell RC ; bool Eval = constToInt ( LS2 . Values [ i ] , A ) && evaluateORri ( R1 , A , Inputs , RC ) ; if ( ! Eval ) return false ; Result . meet ( RC ) ; } return ! Result . isBottom (


<s> break ; default : V = ( V << ( <NUM_LIT> - Bits ) ) >> ( <NUM_LIT> - Bits ) ; break ; } Result = APInt ( Width , V , true ) ; return true ; } if ( Bits < BW ) Result = A1 . trunc ( Bits ) . sext ( Width ) ; else Result = A1 . sext ( Width


<s> if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isBottom ( ) || LS1 . isProperty ( ) ) return false ; APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateSEXTi ( A , Width , Bits , XA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( XA ) ; Result . add (


<s> APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateSEXTi ( A , Width , Bits , XA ) ; if ( ! Eval


<s> bool MachineConstEvaluator :: evaluateXORii ( const APInt & A1 , const APInt & A2 , APInt & Result ) { Result = A1 ^ A2


<s> if ( LS1 . properties ( ) & ConstantProperties :: Zero ) { const Constant * C = intToConst ( A2 ) ; Result . add ( C ) ; return ! Result . isBottom ( ) ; } return false ; } APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateXORii ( A , A2 , XA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( XA ) ; Result . add ( C ) ; } return ! Result . isBottom (


<s> if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isProperty ( ) ) { if ( LS1 . properties ( ) & ConstantProperties :: Zero ) { const Constant * C = intToConst ( A2 ) ; Result . add ( C ) ; return ! Result . isBottom ( ) ; } return false ; } APInt A


<s> if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isProperty ( ) ) return false ; APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return Bottom ; MapType :: const_iterator F = Map . find ( R


<s> return ! RC . isBottom ( ) ; } bool Eval = evaluate ( R , L , RC ) ; return Eval && ! RC


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R . Reg ) ) return false ; const LatticeCell & L = Inputs . get ( R . Reg ) ; if ( ! R


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <NUM_LIT> ; llvm_unreachable (


<s> PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>ConstPropagationPass (


<s> const ConstantInt * MachineConstEvaluator :: intToConst (


<s> MachineConstPropagator ( MachineConstEvaluator & E ) :


<s> return true ; } if ( L . isProperty ( ) ) return add ( L . properties ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < L . size ( ) ; ++ i ) { const Constant * LC = L . Values [ i


<s> if ( Ps & ConstantProperties :: NaN ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: PosOrZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NegOrZero ) os << <STR_LIT> ; os << '}' ; return ; } os << <STR_LIT> ; if ( isBottom ( ) ) { os << <STR_LIT> ; } else if ( isTop ( ) ) { os << <STR_LIT> ; } else { for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { const Constant * C = Values [ i ] ; if ( i != <NUM_LIT> )


<s> if ( isProperty ( ) ) { os << <STR_LIT> ; uint32_t Ps = properties ( ) ; if ( Ps & ConstantProperties :: Zero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NonZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: Finite ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: Infinity ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NaN ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: PosOrZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NegOrZero ) os << <STR_LIT> ; os << '}' ; return ; } os << <STR_LIT> ; if ( isBottom ( ) ) { os << <STR_LIT> ; } else if ( isTop ( ) ) { os << <STR_LIT> ; } else { for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { const Constant * C = Values [ i ] ; if ( i != <NUM_LIT> ) os << <STR_LIT> ; C -> print ( os ) ; } } os <<


<s> CFGEdge Edge = FlowQ . front ( ) ; FlowQ . pop ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Edge . first << <STR_LIT> << Edge . second << '\n' ) ; if ( Edge . first != EntryNum ) if ( EdgeExec . count ( Edge ) ) continue ; EdgeExec . insert ( Edge ) ; MachineBasicBlock * SB = MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = SB -> begin ( ) , End = SB -> end ( ) ; while ( It != End && It -> isPHI ( ) ) { InstrExec . insert ( & * It ) ; visitPHI ( * It ) ; ++ It ; } while ( It != End && It -> isDebugValue ( ) ) ++ It ; assert ( It == End || ! It -> isPHI ( ) ) ; if ( It != End && InstrExec . count ( & * It ) ) continue ; while ( It != End && ! It -> isBranch ( ) ) { if ( ! It -> isDebugValue ( ) ) { InstrExec . insert ( & * It ) ; visitNonBranch ( * It ) ; } ++ It ; } if ( It != End ) { visitBranchesFrom ( * It ) ; } else { unsigned SBN = SB -> getNumber ( ) ; for ( const MachineBasicBlock * SSB : SB -> successors ( ) ) FlowQ . push ( CFGEdge ( SBN , SSB -> getNumber ( ) ) ) ; } } DEBUG ( { dbgs ( ) << <STR_LIT> ; Cells . print ( dbgs ( ) , MCE . TRI ) ; dbgs ( ) << <STR_LIT> ; for ( const MachineBasicBlock & B : MF ) { unsigned BN = B . getNumber ( ) ; for ( const MachineBasicBlock * SB : B . successors


<s> if ( isProperty ( ) ) return Properties ; assert ( ! isTop ( ) && <STR_LIT> ) ; if ( isBottom ( ) ) return ConstantProperties :: Unknown ; assert ( size ( ) > <NUM_LIT> && <STR_LIT> ) ; uint32_t Ps = ConstantProperties :: deduce ( Values [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> ; i < size ( )


<s> for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { if ( Ps == ConstantProperties :: Unknown ) break ; Ps &= ConstantProperties :: deduce ( Values [ i ] ) ; } return


<s> MI . setDesc ( HII . get ( <STR_LIT> ) ) ; while ( MI . getNumOperands ( ) > <NUM_LIT>


<s> MRI = & MF . getRegInfo ( ) ; Cells . clear ( ) ; EdgeExec . clear ( ) ; InstrExec . clear ( ) ; assert ( FlowQ . empty ( ) ) ; propagate ( MF ) ; bool Changed = rewrite ( MF ) ; DEBUG ( { dbgs ( ) << <STR_LIT> << Changed << <STR_LIT> ; if ( Changed ) MF . print ( dbgs (


<s> const Function * F = MF . getFunction ( ) ; if ( ! F ) return


<s> bool Changed = ( Kind != Bottom ) ; Kind = Bottom ; Size = <NUM_LIT>


<s> unsigned size ( ) const { return Size


<s> void update ( unsigned R , const LatticeCell &


<s> InstrExec . insert ( & MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( EvalOk ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << MBN << <STR_LIT> << MI ) ; EvalOk = EvalOk && MCE . evaluate ( MI , Cells , Targets , FallsThru ) ; if ( ! EvalOk ) FallsThru = true ; if ( ! FallsThru ) break ; ++ It ; } if ( EvalOk ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThru ) { const MachineFunction & MF = * B . getParent ( ) ; MachineFunction :: const_iterator BI = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BI ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { Targets . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; for ( const MachineBasicBlock * SB : B . successors ( ) ) Targets . insert ( SB ) ; } for ( const MachineBasicBlock * TB : Targets ) { unsigned TBN = TB -> getNumber ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBN << <STR_LIT> << TBN


<s> assert ( TargetRegisterInfo :: isVirtualRegister ( DefR . Reg ) ) ; bool Changed = false ; if ( DefR . SubReg ) { Bottomize : const LatticeCell & T = Cells . get ( DefR . Reg ) ; Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; if ( Changed ) visitUsesOf ( DefR . Reg ) ; return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PBN << <STR_LIT> << MBN << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; Register UseR ( SO


<s> Changed = ! T . isBottom ( ) ; Cells . update ( DefR . Reg , Bottom ) ; if ( Changed ) visitUsesOf ( DefR . Reg ) ; return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PBN << <STR_LIT> << MBN << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; Register UseR ( SO ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( UseR . Reg ) ) goto Bottomize ; if ( ! Cells . has ( UseR . Reg ) ) continue ; LatticeCell SrcC ; bool Eval = MCE . evaluate ( UseR , Cells . get ( UseR . Reg ) , SrcC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PBN << <STR_LIT> << PrintReg ( UseR . Reg , & MCE . TRI ,


<s> for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( Reg ) ) { if ( ! InstrExec . count ( & MI ) ) continue ; if ( MI . isPHI ( ) ) visitPHI ( MI ) ; else if ( ! MI . isBranch ( ) ) visitNonBranch


<s> } else llvm_unreachable ( <STR_LIT> ) ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , SubLo , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt ,

DoubleRegDest , HiOperand , LoOperand ) ;


<s> assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt ,


<s> if ( HiOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addBlockAddress ( HiOperand . getBlockAddress ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ; return ; } if ( HiOperand . isJTI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addJumpTableIndex ( HiOperand . getIndex ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ; return ; } if ( HiOperand . isCPI


<s> if ( LoOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addBlockAddress ( LoOperand . getBlockAddress ( ) , LoOperand . getOffset ( ) , LoOperand . getTargetFlags ( ) ) ; return ; } if ( LoOperand . isJTI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiOperand

. getReg ( ) , HiRegKillFlag ) . addJumpTableIndex ( LoOperand . getIndex ( ) , LoOperand . getTargetFlags ( ) ) ;


<s> void <ISA_LIT>CopyToCombine :: emitCombineRR ( MachineBasicBlock :: iterator & InsertPt , unsigned DoubleDestReg , MachineOperand & HiOperand , MachineOperand & LoOperand ) { unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; Register LoReg = LoOperand . getReg ( ) ; Register HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc (


<s> Register HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; unsigned NewOpc ; if ( <STR_LIT> . contains ( DoubleDestReg ) ) { NewOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains


<s> assert ( LoOperand . isImm ( ) && HiOperand . isImm ( ) && <STR_LIT> ) ; int64_t V = HiOperand . getImm ( ) ; V = ( V << <NUM_LIT> ) | ( <NUM_LIT> & LoOperand . getImm ( ) ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) .


<s> MachineInstr * <ISA_LIT>CopyToCombine :: findPairable ( MachineInstr & I1 , bool & DoInsertAtI1 , bool AllowC64 ) { MachineBasicBlock :: iterator I2 = std :: next ( MachineBasicBlock :: iterator ( I1 ) ) ; while ( I2 != I1 . getParent ( ) -> end ( ) && I2 -> isDebugInstr ( ) ) ++ I2 ; Register I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 . getParent (


<s> for ( MachineInstr & MI : BB ) { if ( MI . isDebugInstr ( ) ) continue ; if ( TII -> mayBeNewStore ( MI ) ) { for ( const MachineOperand & Op : MI . operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || ! Op . getReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; MachineInstr * DefInst = LastDef [ Reg ] ; if ( ! DefInst ) continue ; if ( ! isCombinableInstType ( * DefInst , TII , ShouldCombineAggressively ) ) continue ; MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) { if ( ! It -> isDebugInstr ( )


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; Register DestReg = Op0 . getReg ( ) ; Register SrcReg = Op1 . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI .


<s> if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; llvm_unreachable ( <STR_LIT>


<s> if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return ( Reg


<s> const MachineOperand & Op = I . getOperand ( <NUM_LIT> ) ; return ! Op . isImm ( ) || ! isInt < N > ( Op . getImm ( ) ) ; } return


<s> } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; Register I1UseReg = UseReg ( I1 . getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { MachineInstr & MI = * I ; if ( MI . isDebugInstr ( ) ) { if ( MI . readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( & MI ) ; continue ; } if ( isUnsafeToMoveAcross ( MI , I1UseReg , I1DestReg , TRI ) || ( ! MI . killsRegister ( I1UseReg ) && MI . killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && MI . killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & MI ; } } if ( KillingInstr ) { removeKillInfo ( * KillingInstr , KilledOperand


<s> return ( UseReg && ( MI . modifiesRegister ( UseReg , TRI ) ) ) || MI . modifiesRegister ( DestReg , TRI ) || MI . readsRegister ( DestReg , TRI ) || MI . hasUnmodeledSideEffects ( )

|| MI . isInlineAsm ( ) || MI . isMetaInstruction ( ) ;


<s> for ( MachineOperand & Op : MI . operands ( ) ) if ( Op . isReg ( ) && Op . getReg ( ) == RegNotKilled && Op . isKill ( )


<s> TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineBasicBlock & MBB : MF ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( MBB ) ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , End = MBB . end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 ,

TII , ShouldCombineAggressively ) ) continue ;


<s> bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineBasicBlock & MBB : MF ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( MBB ) ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , End = MBB . end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true


<s> static Register UseReg ( const MachineOperand & MO ) { return MO . isReg ( ) ? MO . getReg


<s> static Register UseReg ( const MachineOperand & MO ) { return MO . isReg ( ) ? MO . getReg (


<s> unsigned LoOpc = LowRegInst -> getOpcode ( ) ; ( void ) HiOpc ; ( void ) LoOpc ; assert ( ( HiOpc == <STR_LIT> || HiOpc == <STR_LIT> ) && ( LoOpc == <STR_LIT> || LoOpc == <STR_LIT> ) && <STR_LIT> ) ; if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) )


<s> MachineOperand & LoOperand = IsI1Loreg ? I1 -> getOperand ( <NUM_LIT> ) : I2 -> getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 -> getOperand ( <NUM_LIT> ) : I1 -> getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; I1 -> eraseFromParent ( ) ; I2 -> eraseFromParent (


<s> FunctionPass * llvm :: create<ISA_LIT>CopyToCombine


<s> void <ISA_LIT>CopyToCombine :: emitCombineRR ( MachineBasicBlock :: iterator & InsertPt , unsigned DoubleDestReg , MachineOperand & HiOperand , MachineOperand & LoOperand ) { unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned LoReg = LoOperand . getReg ( ) ; unsigned HiReg = HiOperand . getReg (


<s> if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return I2 ; break ; } return


<s> unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 )


<s> MachineFunctionPass :: getAnalysisUsage ( AU


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> initialize<ISA_LIT>CopyToCombinePass ( * PassRegistry :: getPassRegistry (


<s> <ISA_LIT>CopyToCombine ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>CopyToCombinePass ( * PassRegistry :: getPassRegistry (


<s> assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; unsigned SrcReg = Op1 . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg ) &&

( ShouldCombineAggressively || NotExt ) ;


<s> static bool isEvenReg ( unsigned Reg ) { assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) &&


<s> if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = I -> getOperand ( <NUM_LIT> ) ; return ! Op . isImm ( ) || ! isInt < N > ( Op


<s> { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && I -> killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & * I ; } } if ( KillingInstr ) { removeKillInfo ( KillingInstr , KilledOperand ) ; bool Added = I1 -> addRegisterKilled ( KilledOperand , TRI ) ; ( void )


<s> return ( UseReg && ( I -> modifiesRegister ( UseReg , TRI ) ) ) || I -> modifiesRegister ( DestReg , TRI ) || I -> readsRegister ( DestReg , TRI ) || I -> hasUnmodeledSideEffects (

) || I -> isInlineAsm ( ) || I -> isDebugValue ( ) ;


<s> for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) != RegNotKilled || ! Op . isKill ( ) ) continue ; Op . setIsKill


<s> MachineOperand & Op = MI -> getOperand ( I ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) != RegNotKilled || ! Op . isKill (


<s> } if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return ( HighRegInst . getOperand ( <NUM_LIT> ) . isImm ( ) && LowRegInst . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI

< <NUM_LIT> > ( LowRegInst ) ) return false ;


<s> unsigned SubLo ; const TargetRegisterClass * SuperRC = nullptr ; if ( <STR_LIT> . contains ( LoRegDef ) ) { SuperRC = & <STR_LIT> ; SubLo = <STR_LIT> ; } else if ( <STR_LIT> . contains ( LoRegDef ) ) { assert ( ST -> useHVXOps ( ) ) ; SuperRC = & <STR_LIT> ; SubLo = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , SubLo , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest


<s> assert ( ST -> useHVXOps ( ) ) ; NewOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( NewOpc ) , DoubleDestReg )

. addReg ( HiReg , HiRegKillFlag ) . addReg ( LoReg , LoRegKillFlag ) ;


<s> bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; bool IsI2LowReg = ( I1DestReg - I2DestReg ) == <NUM_LIT> ; unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , * I2 , AllowC64 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI ,


<s> if ( ! It -> isDebugInstr ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( MachineOperand & Op : MI . operands ( ) ) { if ( Op . isReg ( ) ) { if ( ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) LastDef [ * SubRegs ] = & MI ; } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = & MI ; } else if ( Op . isRegMask ( ) ) { for ( unsigned Reg : <STR_LIT> ) if ( Op . clobbersPhysReg ( Reg ) ) LastDef [ Reg ] =


<s> const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; unsigned SrcReg = Op1 . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT>


<s> assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg )

&& ( ShouldCombineAggressively || NotExt ) ;


<s> if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 . getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { MachineInstr & MI = * I ; if ( MI . isDebugInstr ( ) ) { if ( MI . readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( & MI ) ; continue ; } if ( isUnsafeToMoveAcross ( MI , I1UseReg , I1DestReg , TRI ) || ( ! MI . killsRegister ( I1UseReg ) && MI . killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && MI . killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & MI ; } } if ( KillingInstr ) { removeKillInfo ( * KillingInstr , KilledOperand ) ; bool Added = I1 . addRegisterKilled ( KilledOperand , TRI ) ; ( void ) Added ; assert ( Added &&


<s> static void removeKillInfo ( MachineInstr & MI , unsigned RegNotKilled ) { for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I


<s> bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End


<s> case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT>


<s> static bool isGreaterThan6BitTFRI ( MachineInstr * I ) { return I -> getOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( I

-> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> return I -> getOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( I ->

getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> static bool isGreaterThan8BitTFRI ( MachineInstr * I ) { return I -> getOpcode ( ) == <STR_LIT> && ! isInt < <NUM_LIT>

> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> return I -> getOpcode ( ) == <STR_LIT> && ! isInt < <NUM_LIT> >

( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; MachineInstr * I2 = findPairable ( I1 ,


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 ,


<s> unsigned HiOpc = HighRegInst . getOpcode ( ) ; unsigned LoOpc = LowRegInst . getOpcode ( ) ; ( void ) HiOpc ; ( void ) LoOpc ; assert ( ( HiOpc == <STR_LIT> || HiOpc == <STR_LIT> ) && ( LoOpc == <STR_LIT> || LoOpc == <STR_LIT> ) && <STR_LIT> ) ; if ( !


<s> unsigned I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned I2DestReg = I2 . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1Loreg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , <STR_LIT> , & <STR_LIT> ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest


<s> return ( UseReg && ( MI . modifiesRegister ( UseReg , TRI ) ) ) || MI . modifiesRegister ( DestReg , TRI ) || MI . readsRegister ( DestReg , TRI ) || MI . hasUnmodeledSideEffects ( ) || MI . isInlineAsm ( )


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1


<s> V = ( V << <NUM_LIT> ) | ( <NUM_LIT> & LoOperand . getImm ( ) ) ; BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg


<s> MachineInstr * <ISA_LIT>CopyToCombine :: findPairable ( MachineInstr & I1 , bool & DoInsertAtI1 , bool AllowC64 ) { MachineBasicBlock :: iterator I2 = std :: next ( MachineBasicBlock :: iterator ( I1 ) ) ; while ( I2 != I1 . getParent ( ) -> end ( ) && I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 . getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( * I2 , TII , ShouldCombineAggressively ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & * I2 ) ) continue ; unsigned I2DestReg = I2 -> getOperand (


<s> MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) { if ( ! It -> isDebugValue ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( MachineOperand & Op : MI . operands ( ) ) { if ( Op . isReg ( ) ) { if ( ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) LastDef [ * SubRegs ] = & MI ; } else if ( <STR_LIT> . contains ( Reg ) ) LastDef [ Reg ] = & MI ; } else if ( Op . isRegMask ( ) ) { for ( unsigned Reg : <STR_LIT> ) if ( Op . clobbersPhysReg


<s> bool <ISA_LIT>CopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) .

getOptLevel ( ) <= CodeGenOpt :: Default ;


<s> if ( ! AllowC64 ) { if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ; } if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return ( HighRegInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && LowRegInst -> getOperand ( <NUM_LIT> )


<s> } if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return ( HighRegInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && LowRegInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> >


<s> if ( ( MachineInstr * ) MI == I2 ) ++ MI ; unsigned I1DestReg = I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1Loreg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg ; unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , <STR_LIT> , & <STR_LIT> ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 -> getOperand ( <NUM_LIT> ) : I2 -> getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 -> getOperand ( <NUM_LIT> ) : I1 -> getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest


<s> while ( I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 -> getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( I2 , TII , ShouldCombineAggressively ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I2 )


<s> if ( I -> isDebugValue ( ) ) continue ; if ( isUnsafeToMoveAcross ( & * I , I2UseReg , I2DestReg , TRI ) ) { isSafe = false ; break ; } if ( ! KillingInstr && KilledOperand && I -> readsRegister ( KilledOperand , TRI ) ) KillingInstr = & * I ; } if ( isSafe ) { if ( KillingInstr ) { bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( I -> isDebugValue ( ) ) { if ( I -> readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( I ) ; continue ; } if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg

) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ;


<s> if ( ! isCombinableInstType ( * DefInst , TII , ShouldCombineAggressively ) ) continue ; MachineBasicBlock :: iterator It ( DefInst ) ; unsigned NumInstsToDef = <NUM_LIT> ; while ( & * It != & MI ) { if ( ! It -> isDebugValue ( ) ) ++ NumInstsToDef ; ++ It ; } if ( NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR ) continue ; PotentiallyNewifiableTFR . insert ( DefInst ) ; } continue ; } for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || ! Op . getReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; if ( <STR_LIT> . contains ( Reg )


<s> const char * getPassName ( ) const { return


<s> removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; IsImmUseReg = I1 -> getOperand ( <NUM_LIT> ) . isImm ( ) || I1 -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ; unsigned I1UseReg = IsImmUseReg ? <NUM_LIT> : I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * KillingInstr = <NUM_LIT> ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && I -> killsRegister ( I1UseReg ) ) { assert ( KillingInstr == <NUM_LIT> && <STR_LIT> ) ; KilledOperand =


<s> } unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , <STR_LIT> , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; if ( ! DoInsertAtI1 && DbgMItoMove . size ( ) != <NUM_LIT> ) { MachineBasicBlock * BB = InsertPt -> getParent ( ) ; for ( auto NewMI


<s> MachineInstr * <ISA_LIT>CopyToCombine :: findPairable ( MachineInstr & I1 , bool & DoInsertAtI1 , bool AllowC64 ) { MachineBasicBlock :: iterator I2 = std :: next ( MachineBasicBlock :: iterator ( I1 ) ) ; if ( I2 != I1 . getParent ( ) -> end ( ) ) while ( I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 . getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( * I2 , TII , ShouldCombineAggressively ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & * I2 ) ) continue ; unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; bool IsI2LowReg = ( I1DestReg -


<s> const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI


<s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count (


<s> static bool areCombinableOperations ( const TargetRegisterInfo * TRI , MachineInstr * HighRegInst , MachineInstr * LowRegInst ) { assert ( ( HighRegInst -> getOpcode ( ) == <STR_LIT> || HighRegInst -> getOpcode ( ) == <STR_LIT> || HighRegInst -> getOpcode ( ) == <STR_LIT> ) && ( LowRegInst -> getOpcode ( ) ==

<STR_LIT> || LowRegInst -> getOpcode ( ) == <STR_LIT> || LowRegInst -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt


<s> if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return false ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) ; } default : break ; } return false


<s> if ( ! QRI -> Subtarget . hasV4TOps ( ) ) return HighRegInst -> getOpcode ( ) == LowRegInst -> getOpcode ( ) && ! isGreaterThan8BitTFRI ( HighRegInst ) && ! isGreaterThan6BitTFRI ( LowRegInst ) ; if ( ( HighRegInst -> getOpcode ( ) == <STR_LIT> || isGreaterThan8BitTFRI ( HighRegInst ) ) && ( LowRegInst -> getOpcode ( ) == <STR_LIT> || isGreaterThan6BitTFRI ( LowRegInst ) ) ) return false ; return true


<s> unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt -> getParent ( ) ; if ( LoOperand . isGlobal ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addReg ( HiReg , HiRegKillFlag ) . addGlobalAddress ( LoOperand . getGlobal ( ) , LoOperand . getOffset ( ) ,


<s> void <ISA_LIT>CopyToCombine :: emitCombineRR ( MachineBasicBlock :: iterator & InsertPt , unsigned DoubleDestReg , MachineOperand & HiOperand , MachineOperand & LoOperand ) { unsigned LoRegKillFlag = getKillRegState ( LoOperand . isKill ( ) ) ; unsigned HiRegKillFlag = getKillRegState ( HiOperand . isKill ( ) ) ; unsigned LoReg = LoOperand . getReg ( ) ; unsigned HiReg = HiOperand . getReg ( ) ; DebugLoc DL = InsertPt -> getDebugLoc ( ) ; MachineBasicBlock * BB = InsertPt


<s> } case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return


<s> return I -> getOpcode ( ) == <STR_LIT> && ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) .


<s> bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; IsImmUseReg = I1 -> getOperand ( <NUM_LIT> ) . isImm ( ) || I1 -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ; unsigned I1UseReg = IsImmUseReg ? <NUM_LIT> : I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { if ( isUnsafeToMoveAcross ( I , I1UseReg , I1DestReg , TRI ) || ( ! I -> killsRegister ( I1UseReg ) && I -> killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && I -> killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & * I ; } } if ( KillingInstr ) { removeKillInfo ( KillingInstr , KilledOperand ) ; bool Added = I1 -> addRegisterKilled (


<s> bool <ISA_LIT>CopyToCombine :: runOnMachineFunction ( MachineFunction & MF ) { if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr * I1 = MI ++ ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1


<s> static DecodeStatus s30_2ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void *


<s> static DecodeStatus s31_1ImmDecoder ( MCInst & MI , unsigned tmp ,


<s> static DecodeStatus s31_1ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI


<s> static DecodeStatus s3_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler ::


<s> static DecodeStatus s4_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp ,


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler ::


<s> case <STR_LIT> :: tc_3bea1824 : case <STR_LIT> :: tc_e836c161 : case <STR_LIT> :: tc_f1aa2cdb : return true ; default : return false


<s> inline bool is_TC4x ( unsigned SchedClass ) { switch ( SchedClass ) { case <STR_LIT> :: tc_2f7c551d : case <STR_LIT> :: tc_2ff964b4 : case <STR_LIT> ::


<s> switch ( SchedClass ) { case <STR_LIT> :: tc_09c86199 : case <STR_LIT> :: tc_2d1e6f5c : case <STR_LIT> :: tc_2e55aa16 : case <STR_LIT> :: tc_3bea1824 : case <STR_LIT>


<s> DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const Target & pTarget , const std :: string & pTriple ) { return new DWARFLineInfo


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>Target

, mcld :: create<ISA_LIT>DiagLineInfo ) ;


<s> opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT> : opcode = <STR_LIT> ; break ; case <STR_LIT>


<s> if ( Bits == <NUM_LIT> ) Bits = <NUM_LIT> ; uint32_t FullValue = fullValue ( * Disassembler . MCII , * * Disassembler . CurrentBundle , MI , SignExtend64 ( tmp , Bits ) ) ; int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> ,

<NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo ::

addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT>


<s> Value |= ( ( insn & <NUM_LIT> ) << <NUM_LIT> ) ; MI . setOpcode ( <STR_LIT> ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , Value ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodePredRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value ) ) ; break ; case ( <STR_LIT> ) : ++ shift ; case <STR_LIT> : case <STR_LIT> : ++ shift ; case <STR_LIT> : case <STR_LIT> : Value |= insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; break ; case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; break ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; break ; case <STR_LIT> : ++ shift ; case <STR_LIT> : ++ shift ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr


<s> static DecodeStatus DecodeVecPredRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg VecPredRegDecoderTable [ ] = { <STR_LIT> ,


<s> unsigned Alignment = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MI ) ; uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Extender -> getOperand ( <NUM_LIT> ) . getExpr


<s> unsigned Alignment = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MI ) ; uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Extender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success ) ; ( void ) Success ; uint32_t Upper26 = static_cast < uint32_t


<s> else if ( encoded_dreg < <NUM_LIT> ) return <STR_LIT> +


<s> Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; <ISA_LIT>MCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check ( )


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice


<s> static unsigned getRegFromSubinstEncoding ( unsigned encoded_reg ) { if ( encoded_reg < <NUM_LIT> ) return <STR_LIT> + encoded_reg ; else if ( encoded_reg < <NUM_LIT> ) return <STR_LIT> + encoded_reg + <NUM_LIT> ; return <STR_LIT>


<s> static DecodeStatus s11_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t


<s> static DecodeStatus s11_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t ,


<s> static DecodeStatus s12_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t ,


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success


<s> static DecodeStatus s3_6ImmDecoder ( MCInst & MI , unsigned tmp ,


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder


<s> static DecodeStatus s4_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler


<s> static DecodeStatus s4_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler ::


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder


<s> int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext (


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( * Disassembler . MCII , * * Disassembler . CurrentBundle , MI , tmp ) ; assert ( FullValue >= <NUM_LIT> &&


<s> SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , C6 , C7 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> return * static_cast < <ISA_LIT>Disassembler const * >


<s> MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; <ISA_LIT>MCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check (


<s> MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice (


<s> void signedDecoder ( MCInst & MI , unsigned tmp , const void * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( * Disassembler . MCII , * * Disassembler . CurrentBundle


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg (


<s> if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT>


<s> static DecodeStatus DecodePredRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , void const * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = PredRegDecoderTable [


<s> static DecodeStatus DecodeRegisterClass ( MCInst & Inst , unsigned RegNo , const uint16_t Table [ ] , size_t Size ) { if ( RegNo < Size


<s> uint32_t insn = llvm :: <STR_LIT> :: read < uint32_t , llvm :: <STR_LIT> , llvm :: <STR_LIT> > ( Bytes . data ( ) ) ; insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ; DecodeStatus Result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; <ISA_LIT>MCInstrInfo :: AppendImplicitOperands ( MI


<s> insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ; DecodeStatus Result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; <ISA_LIT>MCInstrInfo :: AppendImplicitOperands ( MI ) ; return Result


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target ,


<s> uint64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 ( tmp , Bits ) ) ; uint32_t Extended = FullValue + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ; return MCDisassembler :: Success


<s> if ( Bits == <NUM_LIT> ) Bits = <NUM_LIT> ; uint64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 ( tmp , Bits ) ) ; uint32_t Extended = FullValue + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> ,


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { using namespace <ISA_LIT> ; static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> ,


<s> static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> ,


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { static const MCPhysReg DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


RegNo , GeneralDoubleLow8RegDecoderTable ) ;


<s> static DecodeStatus DecodeGeneralSubRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { static const MCPhysReg GeneralSubRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> static DecodeStatus DecodeGeneralSubRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { static const MCPhysReg GeneralSubRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; return DecodeRegisterClass ( Inst , RegNo ,


<s> using namespace <ISA_LIT> ; static const MCPhysReg GuestReg64DecoderTable [ ] = { G1_0 , <NUM_LIT> , G3_2 , <NUM_LIT> , G5_4 , <NUM_LIT> , G7_6 , <NUM_LIT> , G9_8 , <NUM_LIT> , G11_10 , <NUM_LIT> , G13_12 , <NUM_LIT> , G15_14 , <NUM_LIT> , G17_16 , <NUM_LIT> , G19_18 , <NUM_LIT> , G21_20 , <NUM_LIT> , G23_22 , <NUM_LIT> , G25_24 , <NUM_LIT> , G27_26 , <NUM_LIT> , G29_28 , <NUM_LIT> , G31_30 , <NUM_LIT> } ; if ( RegNo >= array_lengthof ( GuestReg64DecoderTable ) ) return MCDisassembler :: Fail ; if ( GuestReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GuestReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg


<s> GELR , GSR , GOSP , G3 , G4 , G5 , G6 , G7 , G8 , G9 , G10 , G11 , G12 , G13 , G14 , G15 , GPMUCNT4 , GPMUCNT5 , GPMUCNT6 , GPMUCNT7 , G20 , G21 , G22 , G23 , GPCYCLELO , GPCYCLEHI , GPMUCNT0 , GPMUCNT1 , GPMUCNT2 , GPMUCNT3 , G30 , G31 } ; if ( RegNo >= array_lengthof ( GuestRegDecoderTable ) ) return MCDisassembler :: Fail ; if ( GuestRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GuestRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler ::


<s> static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo , HvxQRDecoderTable


<s> LLVM_ATTRIBUTE_UNUSED static DecodeStatus DecodeHvxVQRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { static const MCPhysReg HvxVQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo >>


<s> static DecodeStatus DecodeHvxWRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { static const MCPhysReg HvxWRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; return DecodeRegisterClass ( Inst , RegNo


<s> static DecodeStatus DecodeIntRegsLow8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler


<s> static DecodeStatus DecodeIntRegsLow8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address


<s> static DecodeStatus DecodeIntRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { static const MCPhysReg IntRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo ,


<s> static const MCPhysReg PredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo , PredRegDecoderTable


<s> static DecodeStatus DecodePredRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder


<s> static DecodeStatus DecodeSysRegs64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const MCDisassembler * Decoder ) { RegNo = RegNo >> <NUM_LIT> ; if ( RegNo >= sizeof ( SysReg64DecoderTable ) / sizeof ( SysReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( SysReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SysReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand ::


<s> if ( RegNo >= sizeof ( SysRegDecoderTable ) / sizeof ( SysRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( SysRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SysRegDecoderTable [ RegNo


<s> Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = <ISA_LIT>_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Disassembler ( )


<s> static void signedDecoder ( MCInst & MI , unsigned tmp , const MCDisassembler * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 < T > ( tmp


<s> DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; return MCDisassembler ::


<s> static const uint16_t CtrlReg64DecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> static const uint16_t PredRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo , PredRegDecoderTable , sizeof (