<s> MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg (


<s> const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = & * MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue &


<s> unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; Register DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get (

<STR_LIT> ) , DestHi ) . addImm ( HighWord ) ;


<s> unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT>


<s> if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData


<s> const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT>


<s> const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = & * MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ||


<s> uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; Register DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestHi ) .


<s> continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = Fn . getSubtarget ( ) . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = Fn . getSubtarget ( ) . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm (


<s> const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc ==


<s> FunctionPass * llvm :: create<ISA_LIT>SplitConst32AndConst64 ( ) { return new <ISA_LIT>SplitConst32AndConst64 (


<s> return new <ISA_LIT>SplitConst32AndConst64 (


<s> if ( TLOF . IsSmallDataEnabled ( ) ) return true ; const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MachineBasicBlock :: iterator MIE = MBB -> end ( ) ; while ( MII != MIE ) { MachineInstr * MI = MII ; int Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isBlockAddress ( ) ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Symbol = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addOperand ( Symbol ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue ; if ( Opc == <STR_LIT> ) { APFloat Val = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; ImmValue = * Val . bitcastToAPInt ( ) . getRawData ( ) ; } else ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg (


<s> UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) continue ; const UUPair & Pr = F -> second ; Register NewDR = MRI -> createVirtualRegister ( DoubleRC ) ; BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , NewDR ) . addReg ( Pr . first ) . addImm ( <STR_LIT> ) . addReg ( Pr . second ) . addImm ( <STR_LIT> ) ; Op . setReg ( NewDR


<s> Register R = Op . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ; if ( MRI -> getRegClass ( R ) != DoubleRC || Op . getSubReg ( ) ) continue ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) continue ; const UUPair & Pr = F -> second ; Register NewDR = MRI -> createVirtualRegister ( DoubleRC ) ; BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , NewDR ) . addReg ( Pr . first ) . addImm ( <STR_LIT> ) . addReg ( Pr . second ) .


<s> using LoopVector = std :: vector < MachineLoop * > ; LoopVector WorkQ ; append_range ( WorkQ , * MLI ) ; for ( unsigned i = <NUM_LIT> ; i < WorkQ . size ( ) ; ++ i ) append_range ( WorkQ , * WorkQ [ i ] ) ; USet Rs ; for ( unsigned i = <NUM_LIT> , n = WorkQ . size ( ) ; i < n ; ++ i ) { MachineLoop * L = WorkQ [ i ] ; Rs . clear ( ) ; collectIndRegsForLoop ( L


<s> if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; Register R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; Register T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true ; } ; UVect :: iterator End = llvm :: remove_if ( DP , NoIndOp ) ; Rs . insert ( DP . begin ( ) , End ) ; Rs . insert ( CmpR1 ) ; Rs . insert ( CmpR2 ) ; LLVM_DEBUG (


<s> if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; Register R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; Register T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true ; } ; UVect :: iterator End = llvm :: remove_if ( DP , NoIndOp ) ; Rs . insert ( DP . begin ( ) , End ) ; Rs . insert ( CmpR1 ) ; Rs . insert ( CmpR2 ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * HB ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Rs , * TRI ) ; dbgs ( ) <<


<s> case TargetOpcode :: PHI : case TargetOpcode :: COPY : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>SplitDoubleRegs :: collapseRegPairs ( MachineInstr * MI , const UUPairMap & PairMap ) { MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) != DoubleRC || Op . getSubReg ( ) ) continue ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end (


<s> int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E =


<s> bool isKill = Op . isKill ( ) ; if ( isVirtReg && MRI -> getRegClass ( R ) == DoubleRC ) { isKill = false ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) { SR = SubR ; } else { const UUPair & P = F -> second ; R = ( SubR == <STR_LIT> ) ? P . first : P . second ; SR = <NUM_LIT> ; } } auto CO = MachineOperand :: CreateReg ( R , Op . isDef ( ) , Op . isImplicit ( ) , isKill , Op . isDead ( ) , Op . isUndef ( ) , Op . isEarlyClobber ( ) , SR , Op . isDebug ( ) ,


<s> <ISA_LIT>SplitDoubleRegs ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>SplitDoubleRegsPass ( * PassRegistry :: getPassRegistry


<s> MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; int32_t P = profit ( DefI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; if ( isInduction ( DR , IRM ) ) TotalP -= <NUM_LIT> ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) { MachineInstr * UseI = U -> getParent ( ) ; if ( isFixedInstr ( UseI ) ) { FixedNum ++ ; for ( auto & Op : UseI -> operands ( ) ) { if ( Op . isReg ( ) && Part . count ( Op . getReg ( ) ) ) if ( Op . getSubReg ( ) ) TotalP -= <NUM_LIT> ; } continue ; } if ( UseI -> isPHI ( ) ) { const MachineBasicBlock * PB = UseI -> getParent ( ) ; const MachineLoop * L = MLI -> getLoopFor


<s>
using
UUMap
=
std
::
map
<
unsigned
,
unsigned
>
;
using
UVect
=
std
::
vector
<
unsigned
>
;
unsigned
NumRegs
=
MRI
->
getNumVirtRegs
(
)
;
BitVector
DoubleRegs
(
NumRegs
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
<
NumRegs
;
++
i
)
{
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
i
)
;
if
(
MRI
->
getRegClass
(
R
)
==
DoubleRC
)
DoubleRegs
.
set
(
i
)
;
}
BitVector
FixedRegs
(
NumRegs
)
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x
)
;
MachineInstr
*
DefI
=
MRI
->
getVRegDef
(
R
)
;
if
(
!
DefI
||
isFixedInstr
(
DefI
)
)
FixedRegs
.
set
(
x
)
;
}
UUSetMap
AssocMap
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
if
(
FixedRegs
[
x
]
)
continue
;
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x
)
;
DEBUG
(
dbgs
(
)
<<
PrintReg
(
R
,
TRI
)
<<
<STR_LIT>
)
;
USet
&
Asc
=
AssocMap
[
R
]
;
for
(
auto
U
=
MRI
->
use_nodbg_begin
(
R
)
,
Z
=
MRI
->
use_nodbg_end
(
)
;
U
!=
Z
;
++
U
)
{
MachineOperand
&
Op
=
*
U
;
MachineInstr
*
UseI
=
Op
.
getParent
(
)
;
if
(
isFixedInstr
(
UseI
)
)
continue
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
UseI
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
{
MachineOperand
&
MO
=
UseI
->
getOperand
(
i
)
;
if
(
&
MO
==
&
Op
||
!
MO
.
isReg
(
)
||
MO
.
getSubReg
(
)
)
continue
;
unsigned
T
=
MO
.
getReg
(
)
;
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
T
)
)
{
FixedRegs
.
set
(
x
)
;
continue
;
}
if
(
MRI
->
getRegClass
(
T
)
!=
DoubleRC
)
continue
;
unsigned
u
=
TargetRegisterInfo
::
virtReg2Index
(
T
)
;
if
(
FixedRegs
[
u
]
)
continue
;
DEBUG
(
dbgs
(
)
<<
' '
<<
PrintReg
(
T
,
TRI
)
)
;
Asc
.
insert
(
T
)
;
AssocMap
[
T
]
.
insert
(
R
)
;
}
}
DEBUG
(
dbgs
(
)
<<
'\n'
)
;
}
UUMap
R2P
;
unsigned
NextP
=
<NUM_LIT>
;
USet
Visited
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || ! Op . getSubReg ( ) ) continue ; unsigned R = Op . getReg ( ) ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) continue ; const UUPair & P = F -> second ; switch ( Op . getSubReg ( ) ) { case <STR_LIT> : Op . setReg ( P . first ) ; break ; case <STR_LIT> : Op . setReg ( P . second ) ; break ; } Op . setSubReg ( <NUM_LIT>


<s> MachineOperand & Op3 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) && Op1 . isReg ( ) && Op2 . isReg ( ) && Op3 . isImm ( ) ) ; int64_t Sh64 = Op3 . getImm ( ) ; assert ( Sh64 >= <NUM_LIT> && Sh64 < <NUM_LIT> ) ; unsigned S = Sh64 ; UUPairMap :: const_iterator F = PairMap . find ( Op0 . getReg ( ) ) ; assert ( F != PairMap . end ( ) ) ; const UUPair & P = F -> second ; unsigned LoR = P . first ; unsigned HiR = P . second ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned RS1 = getRegState ( Op1 ) ; unsigned RS2 = getRegState ( Op2 ) ; const TargetRegisterClass * IntRC = & IntRegsRegClass ; unsigned LoSR = isub_lo ; unsigned HiSR = isub_hi ; if ( S == <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( A2_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , HiR ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) ; } else if ( S < <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) ; unsigned TmpR1 = MRI -> createVirtualRegister ( IntRC ) ; BuildMI ( B , MI , DL , TII -> get ( S2_extractu ) , TmpR1 ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm


<s> case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p : case S2_asr_i_p : case S2_lsr_i_p : splitShift ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p_or : splitAslOr ( MI , PairMap ) ; Split = true ; break ; default : llvm_unreachable (


<s> using MISet = std :: set < MachineInstr * > ; const TargetRegisterClass * IntRC = & <STR_LIT> ; bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Part , * TRI ) ; dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DR , TRI ) << <STR_LIT> << PrintReg ( HiR , TRI ) << ':' << PrintReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent ( ) ; B -> erase ( MI ) ; } return Changed


<s> dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DR , TRI ) << <STR_LIT> << PrintReg ( HiR , TRI ) << ':' << PrintReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses


<s> if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true ; } ; UVect :: iterator End = llvm :: remove_if ( DP , NoIndOp ) ; Rs . insert ( DP . begin ( ) , End ) ; Rs . insert ( CmpR1 ) ; Rs . insert ( CmpR2 ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * HB ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Rs , * TRI ) ; dbgs ( ) <<


<s> if ( MI -> isDebugInstr ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return true ; case TargetOpcode :: PHI : case TargetOpcode :: COPY : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>SplitDoubleRegs :: partitionRegisters ( UUSetMap & P2Rs ) { using UUMap = std :: map < unsigned , unsigned > ; using UVect = std :: vector < unsigned > ; unsigned NumRegs = MRI -> getNumVirtRegs ( ) ; BitVector DoubleRegs ( NumRegs ) ; for ( unsigned i = <NUM_LIT> ; i < NumRegs ; ++ i ) { unsigned R = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DoubleRegs . set ( i ) ; } BitVector FixedRegs ( NumRegs ) ; for ( int x = DoubleRegs . find_first ( ) ; x >= <NUM_LIT> ; x = DoubleRegs . find_next ( x ) ) { unsigned R = TargetRegisterInfo :: index2VirtReg ( x ) ; MachineInstr * DefI = MRI -> getVRegDef ( R ) ; if ( ! DefI || isFixedInstr ( DefI ) ) FixedRegs . set ( x ) ; } UUSetMap AssocMap ; for ( int x = DoubleRegs . find_first ( ) ; x >= <NUM_LIT> ; x = DoubleRegs . find_next ( x ) ) { if ( FixedRegs [ x ] ) continue ; unsigned R = TargetRegisterInfo :: index2VirtReg ( x ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( R , TRI ) << <STR_LIT> ) ; USet & Asc = AssocMap [ R ] ; for ( auto U = MRI -> use_nodbg_begin ( R ) , Z = MRI -> use_nodbg_end ( ) ; U != Z ; ++ U ) { MachineOperand & Op = * U ; MachineInstr * UseI = Op . getParent ( ) ; if ( isFixedInstr ( UseI ) ) continue ; for ( unsigned i = <NUM_LIT> , n = UseI -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = UseI -> getOperand ( i ) ; if ( & MO == & Op || ! MO . isReg ( ) || MO . getSubReg ( ) ) continue ; unsigned T = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( T ) ) { FixedRegs . set ( x ) ; continue ; } if ( MRI -> getRegClass ( T ) != DoubleRC ) continue ; unsigned u = TargetRegisterInfo :: virtReg2Index ( T ) ; if ( FixedRegs [ u


<s>
if
(
!
DefI
||
isFixedInstr
(
DefI
)
)
FixedRegs
.
set
(
x
)
;
}
UUSetMap
AssocMap
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
if
(
FixedRegs
[
x
]
)
continue
;
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
printReg
(
R
,
TRI
)
<<
<STR_LIT>
)
;
USet
&
Asc
=
AssocMap
[
R
]
;
for
(
auto
U
=
MRI
->
use_nodbg_begin
(
R
)
,
Z
=
MRI
->
use_nodbg_end
(
)
;
U
!=
Z
;
++
U
)
{
MachineOperand
&
Op
=
*
U
;
MachineInstr
*
UseI
=
Op
.
getParent
(
)
;
if
(
isFixedInstr
(
UseI
)
)
continue
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
UseI
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
{
MachineOperand
&
MO
=
UseI
->
getOperand
(
i
)
;
if
(
&
MO
==
&
Op
||
!
MO
.
isReg
(
)
||
MO
.
getSubReg
(
)
)
continue
;
unsigned
T
=
MO
.
getReg
(
)
;
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
T
)
)
{
FixedRegs
.
set
(
x
)
;
continue
;
}
if
(
MRI
->
getRegClass
(
T
)
!=
DoubleRC
)
continue
;
unsigned
u
=
TargetRegisterInfo
::
virtReg2Index
(
T
)
;
if
(
FixedRegs
[
u
]
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
' '
<<
printReg
(
T
,
TRI
)
)
;
Asc
.
insert
(
T
)
;
AssocMap
[
T
]
.
insert
(
R
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
'\n'
)
;
}
UUMap
R2P
;
unsigned
NextP
=
<NUM_LIT>
;
USet
Visited


<s> int32_t <ISA_LIT>SplitDoubleRegs :: profit ( unsigned Reg ) const { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; const MachineInstr * DefI = MRI -> getVRegDef ( Reg ) ; switch ( DefI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return profit ( DefI ) ; default : break ; } return


<s> createHalfInstr ( A2_and , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_and , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_orp : createHalfInstr ( A2_or , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_or , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_xorp : createHalfInstr ( A2_xor , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_xor , MI , PairMap , isub_hi ) ; Split = true ; break ; case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ; Split =


<s> collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent ( ) ; B -> erase ( MI ) ; } return Changed


<s> dump_partition ( dbgs ( ) , Part , * TRI ) ; dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DR , TRI ) << <STR_LIT> << printReg ( HiR , TRI ) << ':' << printReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase


<s> MachineBasicBlock * TmpLB = const_cast < MachineBasicBlock * > ( LB ) ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool BadLB = TII -> analyzeBranch ( * TmpLB , TB , FB , Cond , false ) ; if ( BadLB || Cond . size ( ) != <NUM_LIT> ) return ; if ( ! TII -> PredOpcodeHasJMP_c ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return ; if ( TB != HB && FB != HB ) return ; assert ( Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 )


<s> unsigned FixedNum = <NUM_LIT> , SplitNum = <NUM_LIT> , LoopPhiNum = <NUM_LIT> ; int32_t TotalP = <NUM_LIT> ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; int32_t P = profit ( DefI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; if ( isInduction ( DR , IRM ) ) TotalP -= <NUM_LIT> ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++


<s> USet Rs ; for ( MachineLoop * L : WorkQ ) { Rs . clear ( ) ; collectIndRegsForLoop ( L , Rs ) ; if ( ! Rs . empty ( ) ) IRM . insert ( std ::


<s> append_range ( WorkQ , * MLI ) ; for ( unsigned i = <NUM_LIT> ; i < WorkQ . size ( ) ; ++ i ) append_range ( WorkQ , * WorkQ [ i ] ) ; USet Rs ; for ( MachineLoop * L : WorkQ ) { Rs . clear ( ) ; collectIndRegsForLoop ( L , Rs ) ; if ( ! Rs . empty ( ) ) IRM . insert


<s>
Register
T
=
MO
.
getReg
(
)
;
if
(
!
T
.
isVirtual
(
)
)
{
FixedRegs
.
set
(
x
)
;
continue
;
}
if
(
MRI
->
getRegClass
(
T
)
!=
DoubleRC
)
continue
;
unsigned
u
=
Register
::
virtReg2Index
(
T
)
;
if
(
FixedRegs
[
u
]
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
' '
<<
printReg
(
T
,
TRI
)
)
;
Asc
.
insert
(
T
)
;
AssocMap
[
T
]
.
insert
(
R
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
'\n'
)
;
}
UUMap
R2P
;
unsigned
NextP
=
<NUM_LIT>
;
USet
Visited
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
Register
R
=
Register
::
index2VirtReg
(
x
)
;
if
(
Visited
.
count
(
R
)
)
continue
;
unsigned
ThisP
=
FixedRegs
[
x
]
<NUM_LIT>
:
NextP
++
;
UVect
WorkQ
;
WorkQ
.
push_back
(
R
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
<
WorkQ
.
size
(
)
;
++
i
)
{
unsigned
T
=
WorkQ
[


<s> if ( ! Op . isReg ( ) ) { NewI -> addOperand ( Op ) ; continue ; } Register R = Op . getReg ( ) ; unsigned SR = Op . getSubReg ( ) ; bool isVirtReg = Register :: isVirtualRegister ( R ) ; bool isKill = Op . isKill ( ) ; if ( isVirtReg && MRI -> getRegClass ( R ) == DoubleRC ) { isKill = false ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) { SR = SubR ; } else { const UUPair & P = F -> second ; R = ( SubR == <STR_LIT> ) ? P . first : P . second ; SR =


<s>
for
(
auto
I
:
Part
)
dbgs
(
)
<<
' '
<<
printReg
(
I
,
&
TRI
)
;
dbgs
(
)


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>SplitDoubleRegs :: isFixedInstr ( const MachineInstr * MI ) const { if ( MI -> mayLoadOrStore ( ) ) if ( MemRefsFixed || isVolatileInstr ( MI ) ) return true ; if ( MI -> isDebugInstr ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return true ; case TargetOpcode :: PHI : case TargetOpcode :: COPY : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case


<s> } if ( UseI -> isPHI ( ) ) { const MachineBasicBlock * PB = UseI -> getParent ( ) ; const MachineLoop * L = MLI -> getLoopFor ( PB ) ; if ( L && L -> getHeader ( ) == PB ) LoopPhiNum ++ ; } int32_t P = profit ( UseI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; } } if ( FixedNum > <NUM_LIT> && LoopPhiNum > <NUM_LIT> ) TotalP -=


<s> for ( auto & MO : MI -> memoperands ( ) ) if (

MO -> isVolatile ( ) || MO -> isAtomic ( ) ) return true ;


<s> for ( auto & MO : MI -> memoperands ( ) ) if ( MO -> isVolatile ( )


<s> int32_t P = <NUM_LIT> ; if ( Imm == <NUM_LIT> || Imm == <NUM_LIT> ) P += <NUM_LIT> ; return P


<s> void <ISA_LIT>SplitDoubleRegs :: replaceSubregUses ( MachineInstr * MI , const UUPairMap & PairMap ) { for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || ! Op . getSubReg ( ) ) continue ; Register R = Op . getReg ( )


<s> partitionRegisters ( P2Rs ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { dbgs ( ) << '#' << I -> first << <STR_LIT> ; dump_partition ( dbgs ( ) , I -> second , * TRI ) ; dbgs ( ) << '\n' ; } } ) ; bool Changed = false ; int Limit = MaxHSDR ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs .


<s> break ; } case A2_andp : createHalfInstr ( A2_and , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_and , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_orp : createHalfInstr ( A2_or , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_or , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_xorp : createHalfInstr ( A2_xor , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_xor , MI , PairMap , isub_hi ) ; Split = true ; break ; case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p : case S2_asr_i_p : case S2_lsr_i_p : splitShift ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p_or : splitAslOr ( MI , PairMap ) ; Split = true ; break ; default : llvm_unreachable ( <STR_LIT> ) ; return false ; } return Split


<s> const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . first ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off ) ; HighI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off + <NUM_LIT> ) ; } else { const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off ) . addReg ( P . first ) ; HighI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off + <NUM_LIT> ) . addReg ( P . second ) ; } if ( PostInc ) { int64_t Inc = Load ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand & UpdOp = Load ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( UpdOp . getReg ( ) ) ; Register NewR = MRI -> createVirtualRegister ( RC ) ; assert ( ! UpdOp . getSubReg ( ) && <STR_LIT> ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , NewR ) . addReg ( AdrOp . getReg ( ) , RSA ) . addImm ( Inc ) ; MRI -> replaceRegWith ( UpdOp . getReg ( ) , NewR ) ; } MachineFunction & MF = * B . getParent ( ) ; for ( auto & MO : MI -> memoperands ( ) ) { const MachinePointerInfo & Ptr = MO -> getPointerInfo ( ) ; MachineMemOperand :: Flags F = MO -> getFlags ( ) ; Align A = MO -> getAlign ( ) ; auto * Tmp1 = MF . getMachineMemOperand ( Ptr , F , <NUM_LIT> , A ) ; LowI -> addMemOperand ( MF ,


<s> MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; Register LoR = MRI -> createVirtualRegister ( IntRC ) ; Register HiR = MRI -> createVirtualRegister ( IntRC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DR , TRI ) << <STR_LIT> << printReg ( HiR , TRI ) << ':' << printReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI


<s> Register PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; Register R = Op . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) ) return true ; } return false


<s> if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) if ( MemRefsFixed || isVolatileInstr ( MI ) ) return true ; if ( MI -> isDebugInstr ( ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : return true ; case TargetOpcode :: PHI : case TargetOpcode :: COPY : break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) break ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> void <ISA_LIT>SplitDoubleRegs :: splitMemRef ( MachineInstr * MI , const UUPairMap & PairMap ) { bool Load = MI -> mayLoad ( ) ; unsigned OrigOpc = MI -> getOpcode ( ) ; bool PostInc = ( OrigOpc == <STR_LIT> || OrigOpc == <STR_LIT> ) ; MachineInstr * LowI , * HighI ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned AdrX = PostInc ? ( Load ? <NUM_LIT> : <NUM_LIT> ) : ( Load ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand & AdrOp = MI -> getOperand ( AdrX ) ; unsigned RSA = getRegState ( AdrOp ) ; MachineOperand & ValOp = Load ? MI -> getOperand ( <NUM_LIT> ) : ( PostInc ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ) ; UUPairMap :: const_iterator F = PairMap . find ( ValOp . getReg ( ) ) ; assert ( F != PairMap . end ( ) ) ; if ( Load ) { const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . first ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off ) ; HighI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off + <NUM_LIT> ) ; } else { const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp

. getSubReg ( ) ) . addImm ( Off ) . addReg ( P . first ) ;


<s> SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool BadLB = TII -> AnalyzeBranch ( * TmpLB , TB , FB , Cond , false ) ; if ( BadLB || Cond . size ( ) != <NUM_LIT> ) return ; if ( ! TII -> PredOpcodeHasJMP_c ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return ; if ( TB != HB && FB != HB ) return ; assert ( Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; typedef std :: vector < unsigned > UVect ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI


<s> const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off ) . addReg ( P . first ) ; HighI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off + <NUM_LIT> ) . addReg ( P . second ) ; } if ( PostInc ) { int64_t Inc = Load ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand & UpdOp = Load ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( UpdOp . getReg ( ) ) ; unsigned NewR = MRI -> createVirtualRegister ( RC ) ; assert ( ! UpdOp . getSubReg ( ) && <STR_LIT> ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , NewR ) . addReg ( AdrOp . getReg ( ) , RSA ) . addImm ( Inc ) ; MRI -> replaceRegWith ( UpdOp . getReg ( ) , NewR ) ; } MachineFunction & MF = * B . getParent ( ) ; for ( auto & MO : MI -> memoperands ( ) ) { const MachinePointerInfo & Ptr = MO -> getPointerInfo


<s> } if ( PostInc ) { int64_t Inc = Load ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand & UpdOp = Load ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( UpdOp . getReg ( ) ) ; unsigned NewR = MRI -> createVirtualRegister ( RC ) ; assert ( ! UpdOp . getSubReg ( ) && <STR_LIT> ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , NewR ) . addReg ( AdrOp . getReg ( ) , RSA ) . addImm ( Inc ) ; MRI -> replaceRegWith ( UpdOp . getReg ( ) , NewR ) ; } MachineFunction & MF = * B . getParent ( ) ; for ( auto & MO : MI -> memoperands ( ) ) { const MachinePointerInfo & Ptr = MO -> getPointerInfo ( ) ; unsigned F = MO -> getFlags ( ) ; int A = MO -> getAlignment ( ) ; auto * Tmp1 = MF . getMachineMemOperand ( Ptr , F , <NUM_LIT> , A ) ; LowI -> addMemOperand ( MF , Tmp1 ) ; auto * Tmp2 = MF . getMachineMemOperand ( Ptr , F , <NUM_LIT> ,


<s> if ( ! HB || ! LB ) return ; MachineBasicBlock * TB = <NUM_LIT> , * FB = <NUM_LIT> ; MachineBasicBlock * TmpLB = const_cast < MachineBasicBlock * > ( LB ) ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool BadLB = TII -> analyzeBranch ( * TmpLB , TB , FB , Cond , false ) ; if ( BadLB || Cond . size ( ) != <NUM_LIT> ) return ; if ( ! TII -> PredOpcodeHasJMP_c ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return ; if ( TB != HB && FB != HB ) return ; assert ( Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; typedef std :: vector < unsigned > UVect ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true


<s> bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return false ; } return true ; } ; UVect :: iterator End = llvm :: remove_if ( DP


<s> if ( BadLB || Cond . size ( ) != <NUM_LIT> ) return ; if ( ! TII -> PredOpcodeHasJMP_c ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return ; if ( TB != HB && FB != HB ) return ; assert ( Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; unsigned PR = Cond [ <NUM_LIT> ] . getReg ( ) ; assert ( MRI -> getRegClass ( PR ) == & <STR_LIT> ) ; unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; using UVect = std :: vector < unsigned > ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI


<s>
USet
&
Asc
=
AssocMap
[
R
]
;
for
(
auto
U
=
MRI
->
use_nodbg_begin
(
R
)
,
Z
=
MRI
->
use_nodbg_end
(
)
;
U
!=
Z
;
++
U
)
{
MachineOperand
&
Op
=
*
U
;
MachineInstr
*
UseI
=
Op
.
getParent
(
)
;
if
(
isFixedInstr
(
UseI
)
)
continue
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
UseI
->
getNumOperands
(
)
;
i
<
n
;
++
i
)
{
MachineOperand
&
MO
=
UseI
->
getOperand
(
i
)
;
if
(
&
MO
==
&
Op
||
!
MO
.
isReg
(
)
||
MO
.
getSubReg
(
)
)
continue
;
unsigned
T
=
MO
.
getReg
(
)
;
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
T
)
)
{
FixedRegs
.
set
(
x
)
;
continue
;
}
if
(
MRI
->
getRegClass
(
T
)
!=
DoubleRC
)
continue
;
unsigned
u
=
TargetRegisterInfo
::
virtReg2Index
(
T
)
;
if
(
FixedRegs
[
u
]
)
continue
;
DEBUG
(
dbgs
(
)
<<
' '
<<
printReg
(
T
,
TRI
)
)
;
Asc
.
insert
(
T
)
;
AssocMap
[
T
]
.
insert
(
R
)
;
}
}
DEBUG
(
dbgs
(
)
<<
'\n'
)
;
}
UUMap
R2P
;
unsigned
NextP
=
<NUM_LIT>
;
USet
Visited
;
for
(
int
x
=
DoubleRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
DoubleRegs
.
find_next
(
x
)
)
{
unsigned
R
=
TargetRegisterInfo
::
index2VirtReg
(
x
)
;
if
(
Visited
.
count
(
R
)
)
continue
;
unsigned
ThisP
=
FixedRegs
[
x
]
<NUM_LIT>
:
NextP
++
;
UVect
WorkQ
;
WorkQ
.
push_back
(
R
)
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
<
WorkQ
.
size
(
)
;
++
i
)
{
unsigned
T
=
WorkQ
[
i
]
;
if
(
Visited
.
count
(
T
)
)
continue
;
R2P
[
T
]
=
ThisP
;
Visited
.
insert
(
T
)
;
USet
&
Asc
=
AssocMap
[
T
]
;
for
(
USet
::
iterator
J
=
Asc
.
begin
(
)
,
F
=
Asc
.
end
(
)
;
J
!=
F
;
++
J
)
WorkQ
.
push_back
(
*
J
)
;
}
}
for
(
auto
I
:
R2P
)
P2Rs
[
I
.
second
]
.
insert
(
I
.


<s> TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; UUSetMap P2Rs ; LoopRegMap IRM ; collectIndRegs ( IRM ) ; partitionRegisters ( P2Rs ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { dbgs ( ) << '#' << I -> first << <STR_LIT> ; dump_partition ( dbgs ( ) , I -> second , * TRI ) ; dbgs ( ) << '\n' ; } } ) ; bool Changed = false ; int Limit = MaxHSDR ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { if ( I -> first == <NUM_LIT> ) continue ; if ( Limit >= <NUM_LIT> && Counter >= Limit ) break ; USet & Part = I -> second ; DEBUG ( dbgs ( ) << <STR_LIT> << I -> first << '\n' ) ; if ( ! isProfitable ( Part , IRM ) ) continue ; Counter ++


<s> for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DR , TRI ) << <STR_LIT> << printReg ( HiR , TRI ) << ':' << printReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Part , * TRI ) ; dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DR , TRI ) << <STR_LIT> << printReg ( HiR , TRI ) << ':' << printReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent (


<s> unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; typedef std :: vector < unsigned > UVect ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI =


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : { ImmX ++ ; int64_t V = MI -> getOperand ( ImmX ) . getImm ( ) ; if ( V == <NUM_LIT> || V == - <NUM_LIT> ) return <NUM_LIT> ; LLVM_FALLTHROUGH ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return profit ( Rs ) + profit ( Rt ) ; } case <STR_LIT> : { unsigned S = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( S == <NUM_LIT> || S == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT>


<s> if ( Hi == <NUM_LIT> || Hi == <NUM_LIT> ) P += <NUM_LIT> ; return


<s> static inline int32_t profitImm ( unsigned Lo , unsigned Hi ) { int32_t P = <NUM_LIT> ; if ( Lo == <NUM_LIT> || Lo == <NUM_LIT> ) P += <NUM_LIT> ; if ( Hi == <NUM_LIT> || Hi == <NUM_LIT> ) P +=


<s> int Limit = MaxHSDR ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { if ( I -> first == <NUM_LIT> ) continue ; if ( Limit >= <NUM_LIT> && Counter >= Limit ) break ; USet & Part = I -> second ; DEBUG ( dbgs ( ) << <STR_LIT> << I -> first << '\n' ) ; if ( ! isProfitable ( Part , IRM ) ) continue ; Counter ++ ; Changed |= splitPartition ( Part


<s> bool <ISA_LIT>SplitDoubleRegs :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; auto & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST . getRegisterInfo ( ) ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; UUSetMap P2Rs ; LoopRegMap IRM ; collectIndRegs ( IRM ) ; partitionRegisters ( P2Rs ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { dbgs ( ) << '#' << I ->


<s> static inline uint32_t getRegState ( const MachineOperand & R ) { assert ( R . isReg ( ) ) ; return getDefRegState ( R . isDef ( ) ) | getImplRegState ( R . isImplicit ( ) ) | getKillRegState ( R . isKill ( ) ) | getDeadRegState ( R . isDead ( ) ) | getUndefRegState ( R . isUndef ( ) ) | getInternalReadRegState ( R . isInternalRead ( ) ) | ( R . isDebug (


<s> MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) )


<s> if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; typedef std :: vector < unsigned > UVect ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( T == CmpR1 || T == CmpR2 ) return


<s> unsigned R = Op . getReg ( ) ; unsigned SR = Op . getSubReg ( ) ; bool isVirtReg = TargetRegisterInfo :: isVirtualRegister ( R ) ; bool isKill = Op . isKill ( ) ; if ( isVirtReg && MRI -> getRegClass ( R ) == DoubleRC ) { isKill = false ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) { SR = SubR ; } else { const UUPair & P = F -> second ; R = ( SubR == <STR_LIT> ) ?


<s> return new <ISA_LIT>SplitDoubleRegs (


<s> <ISA_LIT>SplitDoubleRegs ( ) : MachineFunctionPass ( ID ) , TRI ( nullptr ) , TII ( nullptr ) { initialize<ISA_LIT>SplitDoubleRegsPass ( * PassRegistry :: getPassRegistry (


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { uint64_t D = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo = D & <NUM_LIT> ; unsigned Hi = D >> <NUM_LIT> ; return profitImm ( Lo , Hi ) ; } case <STR_LIT> : case <STR_LIT> : return profitImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : ImmX ++ ; case <STR_LIT> : { ImmX ++ ; int64_t V = MI -> getOperand ( ImmX ) . getImm ( ) ; if ( V == <NUM_LIT> || V == - <NUM_LIT> ) return <NUM_LIT> ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT>


<s> case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { uint64_t D = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo = D & <NUM_LIT> ; unsigned Hi = D >> <NUM_LIT> ; return profitImm ( Lo , Hi ) ; } case <STR_LIT> : case <STR_LIT> : return profitImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : ImmX ++ ; case <STR_LIT> : { ImmX ++ ; int64_t V = MI -> getOperand ( ImmX ) . getImm ( ) ; if ( V == <NUM_LIT> || V == - <NUM_LIT> ) return <NUM_LIT> ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { unsigned S = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( S == <NUM_LIT> || S == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } case <STR_LIT>


<s> if ( Hi == <NUM_LIT> || Hi == <NUM_LIT> ) P += <NUM_LIT> , HiZ1 = true ; if ( ! LoZ1 && ! HiZ1 && Lo == Hi ) P += <NUM_LIT> ; return P


<s> dbgs ( ) << <STR_LIT> ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { dbgs ( ) << '#' << I -> first << <STR_LIT> ; dump_partition ( dbgs ( ) , I -> second , * TRI ) ; dbgs ( ) << '\n' ; } } ) ; bool Changed = false ; int Limit = MaxHSDR ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { if ( I -> first == <NUM_LIT> ) continue ; if ( Limit >= <NUM_LIT> && Counter >= Limit ) break ; USet & Part = I -> second ; DEBUG ( dbgs ( ) << <STR_LIT> << I -> first << '\n' ) ; if ( ! isProfitable ( Part , IRM ) ) continue ; Counter ++ ; Changed |= splitPartition ( Part


<s> unsigned HiSR = subreg_hireg ; if ( S == <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( A2_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , HiR ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) ; } else if ( S < <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) ; unsigned TmpR1 = MRI -> createVirtualRegister ( IntRC ) ; BuildMI ( B , MI , DL , TII -> get ( S2_extractu ) , TmpR1 ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) . addImm ( <NUM_LIT> - S ) ; unsigned TmpR2 = MRI -> createVirtualRegister ( IntRC ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , TmpR2 ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( TmpR1 ) ; BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , HiR ) . addReg ( TmpR2 ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) . addImm ( S ) ; } else if ( S == <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: COPY ) , LoR ) . addReg (

Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) ;


<s> if ( Op1 . isImm ( ) ) { BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addImm ( Op1 . getImm ( ) ) ; } else if ( Op1 . isReg ( ) ) { BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: COPY ) , P . second ) . addReg ( Op1 . getReg ( ) , getRegState ( Op1 ) , Op1 . getSubReg ( ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( Op2 . isImm ( )


<s> assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; UUPairMap :: const_iterator F = PairMap . find ( Op0 . getReg ( ) ) ; assert ( F != PairMap . end ( ) ) ; const UUPair & P = F -> second ; unsigned RS = getRegState ( Op1 ) ; BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: COPY ) , P . first ) . addReg ( Op1 .

getReg ( ) , RS & ~ RegState :: Kill , Op1 . getSubReg ( ) ) ;


<s> BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . first ) . addImm ( int32_t ( V & <NUM_LIT> ) ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addImm ( int32_t (


<s> case A2_xorp : createHalfInstr ( A2_xor , MI , PairMap , subreg_loreg ) ; createHalfInstr ( A2_xor , MI , PairMap , subreg_hireg ) ; Split = true ; break ; case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64_Int_Real : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p : case S2_asr_i_p : case S2_lsr_i_p : splitShift ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p_or : splitAslOr ( MI , PairMap


<s> assert ( F != PairMap . end ( ) ) ; if ( Load ) { const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . first ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off ) ; HighI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off + <NUM_LIT> ) ; } else { const UUPair & P = F -> second ; int64_t Off = PostInc ? <NUM_LIT> : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LowI = BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( AdrOp . getReg ( ) , RSA & ~ RegState :: Kill , AdrOp . getSubReg ( ) ) . addImm ( Off


<s> unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DR , TRI ) << <STR_LIT> << PrintReg ( HiR , TRI ) << ':' << PrintReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI ->


<s> if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent ( ) ; B -> erase (


<s> const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>SplitTFRCondSets :: ID , <NUM_LIT> , false , false ) ; Registry . registerPass ( *


<s> PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>SplitTFRCondSets :: ID , <NUM_LIT>


<s> FunctionPass * llvm :: create<ISA_LIT>SplitTFRCondSets


<s> <ISA_LIT>SplitTFRCondSets ( ) : MachineFunctionPass ( ID


<s> for ( MachineFunction :: iterator MBBb = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MII != MBB -> end ( ) ; ++ MII ) { MachineInstr * MI = MII ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != SrcReg1 ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SrcReg1 ) ; } BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MII = MBB -> erase


<s> FunctionPass * llvm :: create<ISA_LIT>SplitTFRCondSets (


<s> FunctionPass * llvm :: create<ISA_LIT>SplitTFRCondSets ( const <ISA_LIT>TargetMachine & TM


<s> MachineFunctionPass ( ID ) , QTM ( TM ) , QST ( * TM . getSubtargetImpl ( ) ) { initialize<ISA_LIT>SplitTFRCondSetsPass ( * PassRegistry :: getPassRegistry (


<s> static void initializePassOnce ( PassRegistry & Registry ) { const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>SplitTFRCondSets :: ID , nullptr , false


<s> auto & ST = MFn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MRI = & MFn . getRegInfo


<s> if ( skipFunction ( * MFn . getFunction ( ) ) ) return false ; MF = & MFn ; auto & ST = MFn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo (


<s> Group . push_back ( MI ) ; * I = nullptr ; continue ; } } if ( MI -> isCall ( ) || MI -> hasUnmodeledSideEffects ( ) ) return ; if ( MI -> mayLoadOrStore ( ) ) { if ( MI -> hasOrderedMemoryRef ( ) || instrAliased ( Group , MI ) ) return ; Other . push_back ( MI


<s> Shift += NBits ; } MachineInstr * FirstSt = OG . front ( ) ; DebugLoc DL = OG . back ( ) -> getDebugLoc ( ) ; const MachineMemOperand & OldM = getStoreTarget ( FirstSt ) ; MachineMemOperand * NewM = MF -> getMachineMemOperand ( OldM . getPointerInfo ( ) , OldM . getFlags ( ) , TotalSize , OldM . getAlign ( ) , OldM . getAAInfo ( ) ) ; if ( Acc < <NUM_LIT> ) { unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; int Val = ( TotalSize == <NUM_LIT> ) ? int16_t ( Acc ) : int ( Acc ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR . getSubReg ( ) ) . addImm ( Off ) . addImm ( Val ) ; StI -> addMemOperand ( * MF , NewM ) ; NG . push_back ( StI ) ; } else { const MCInstrDesc & TfrD = TII -> get ( <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TfrD , <NUM_LIT> , TRI , * MF ) ; Register VReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * TfrI = BuildMI ( * MF , DL , TfrD , VReg ) . addImm ( int ( Acc ) ) ; NG . push_back ( TfrI ) ; unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR

. getSubReg ( ) ) . addImm ( Off ) . addReg ( VReg , RegState :: Kill ) ;


<s> if ( ! MMO . getValue ( ) ) return true ; MemoryLocation L ( MMO . getValue ( ) , MMO . getSize ( ) , MMO . getAAInfo ( ) ) ; for ( auto SI : Stores ) { const MachineMemOperand & SMO = getStoreTarget ( SI ) ; if ( ! SMO . getValue ( ) ) return true ; MemoryLocation SL ( SMO . getValue ( ) , SMO . getSize ( ) , SMO . getAAInfo ( ) ) ; if ( ! AA -> isNoAlias ( L , SL ) ) return true ; } return


<s> for ( auto SI : Stores ) { const MachineMemOperand & SMO = getStoreTarget ( SI ) ; if ( ! SMO . getValue ( ) ) return true ; MemoryLocation SL ( SMO . getValue ( ) , SMO . getSize ( ) , SMO . getAAInfo ( ) ) ; if ( ! AA -> isNoAlias ( L ,


<s> OG . push_back ( FirstMI ) ; MachineInstr * S1 = FirstMI ; unsigned Pow2Num = <NUM_LIT> ; unsigned Pow2Size = SizeAccum ; for ( InstrGroup :: iterator I = Begin + <NUM_LIT> ; I != End ; ++ I ) { MachineInstr * S2 = * I ; if ( ! storesAreAdjacent ( S1 , S2 ) ) break ; unsigned S2Size = getStoreTarget ( S2 ) . getSize ( ) ; if ( SizeAccum + S2Size > std :: min ( MaxSize , Alignment ) ) break ; OG . push_back ( S2 ) ; SizeAccum += S2Size ; if ( isPowerOf2_32 ( SizeAccum ) ) { Pow2Num = OG . size ( ) ; Pow2Size = SizeAccum ; } if ( ( <NUM_LIT> * Pow2Size - <NUM_LIT> ) & FirstOffset ) break ; S1 = S2 ; } if ( Pow2Num <= <NUM_LIT> ) { OG . clear (


<s> assert ( ! FirstMI -> memoperands_empty ( ) && <STR_LIT> ) ; const MachineMemOperand & FirstMMO = getStoreTarget ( FirstMI ) ; unsigned Alignment = FirstMMO . getAlign ( ) . value ( ) ; unsigned SizeAccum = FirstMMO . getSize ( ) ; unsigned FirstOffset = getStoreOffset ( FirstMI ) ; assert ( isPowerOf2_32 ( SizeAccum ) && <STR_LIT> ) ; if ( SizeAccum >= MaxSize ) return false ; if ( SizeAccum >= Alignment ) return false ; if ( ( <NUM_LIT> * SizeAccum - <NUM_LIT> ) & FirstOffset ) return false ; OG . push_back ( FirstMI ) ; MachineInstr * S1 =


<s> unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; int Val = ( TotalSize == <NUM_LIT> ) ? int16_t ( Acc ) : int ( Acc ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR . getSubReg ( ) ) . addImm ( Off ) . addImm ( Val ) ; StI -> addMemOperand ( * MF , NewM ) ; NG . push_back ( StI ) ; } else { const MCInstrDesc & TfrD = TII -> get ( <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TfrD , <NUM_LIT> , TRI , * MF ) ; Register VReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * TfrI = BuildMI ( * MF , DL , TfrD , VReg ) . addImm ( int ( Acc ) ) ; NG . push_back ( TfrI ) ; unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> :


<s> assert ( Begin != End && <STR_LIT> ) ; assert ( OG . empty ( ) && <STR_LIT> ) ; if ( std :: distance ( Begin , End ) <= <NUM_LIT> ) return false ; MachineInstr * FirstMI = * Begin ; assert ( ! FirstMI -> memoperands_empty ( ) && <STR_LIT> ) ; const MachineMemOperand & FirstMMO = getStoreTarget ( FirstMI ) ; unsigned Alignment = FirstMMO . getAlignment ( ) ; unsigned SizeAccum = FirstMMO . getSize ( ) ; unsigned FirstOffset = getStoreOffset ( FirstMI ) ; assert ( isPowerOf2_32 ( SizeAccum ) && <STR_LIT> ) ; if ( SizeAccum >= MaxSize ) return false ; if ( SizeAccum >= Alignment ) return false ; if ( ( <NUM_LIT> * SizeAccum - <NUM_LIT> ) & FirstOffset ) return false ; OG . push_back ( FirstMI ) ; MachineInstr * S1 = FirstMI ; unsigned Pow2Num = <NUM_LIT> ; unsigned Pow2Size


<s> bool Changed = false ; createStoreGroups ( MBB , SGs ) ; auto Less = [ ] ( const MachineInstr * A , const MachineInstr * B ) -> bool { return getStoreOffset ( A ) < getStoreOffset ( B ) ; } ; for ( auto & G : SGs ) { assert ( G . size ( ) > <NUM_LIT> && <STR_LIT> ) ; llvm :: sort ( G . begin ( ) , G . end ( ) , Less ) ; Changed |= processStoreGroup ( G ) ; } return Changed


<s> unsigned BaseReg = getBaseAddressRegister ( BaseStore ) ; InstrGroup Other ; Group . push_back ( BaseStore ) ; for ( auto I = Begin ; I != End ; ++ I ) { MachineInstr * MI = * I ; if ( ! MI ) continue ; if ( handledStoreType ( MI ) ) { if ( instrAliased ( Group , getStoreTarget ( MI ) ) ) return ; if ( instrAliased ( Other , getStoreTarget ( MI ) ) ) return ; unsigned BR = getBaseAddressRegister ( MI ) ; if ( BR == BaseReg ) { Group . push_back ( MI ) ; * I = <NUM_LIT> ; continue ; } } if ( MI -> isCall ( ) || MI -> hasUnmodeledSideEffects ( ) ) return ; if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) { if ( MI -> hasOrderedMemoryRef ( ) || instrAliased ( Group , MI )


<s> for ( auto I = Begin ; I != End ; ++ I ) { MachineInstr * MI = * I ; if ( ! MI ) continue ; if ( handledStoreType ( MI ) ) { if ( instrAliased ( Group , getStoreTarget ( MI ) ) ) return ; if ( instrAliased ( Other , getStoreTarget ( MI ) ) ) return ; unsigned BR = getBaseAddressRegister (


<s> const MachineMemOperand & OldM = getStoreTarget ( FirstSt ) ; MachineMemOperand * NewM = MF -> getMachineMemOperand ( OldM . getPointerInfo ( ) , OldM . getFlags ( ) , TotalSize , OldM . getAlignment ( ) , OldM . getAAInfo ( ) ) ; if ( Acc < <NUM_LIT> ) { unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; int Val = ( TotalSize == <NUM_LIT> ) ? int16_t ( Acc ) : int ( Acc ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) ) . addImm ( Off ) . addImm ( Val ) ; StI -> addMemOperand ( * MF , NewM ) ; NG . push_back ( StI ) ; } else { const MCInstrDesc & TfrD = TII -> get ( <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TfrD , <NUM_LIT> , TRI , * MF ) ; unsigned VReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * TfrI = BuildMI ( * MF , DL , TfrD , VReg ) . addImm ( int ( Acc ) ) ; NG . push_back ( TfrI ) ; unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm (


<s> unsigned getBaseAddressRegister ( const MachineInstr * MI ) { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; return MO . getReg (


<s> unsigned getBaseAddressRegister ( const MachineInstr * MI ) { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; return MO . getReg


<s> const MachineMemOperand & getStoreTarget ( const MachineInstr *


<s> return getStoreOffset ( A ) < getStoreOffset ( B ) ; } ; for ( auto & G : SGs ) { assert ( G . size ( ) > <NUM_LIT> && <STR_LIT> ) ; std :: sort ( G . begin ( ) , G . end ( ) , Less ) ; Changed |= processStoreGroup ( G


<s> AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Changed = false ; for ( auto & B : MFn ) Changed |= processBasicBlock ( B ) ; return Changed


<s> FunctionPass * llvm :: create<ISA_LIT>StoreWidening ( ) { return new <ISA_LIT>StoreWidening


<s> Group . push_back ( BaseStore ) ; for ( auto I = Begin ; I != End ; ++ I ) { MachineInstr * MI = * I ; if ( ! MI ) continue ; if ( handledStoreType ( MI ) ) { if ( instrAliased ( Group , getStoreTarget ( MI ) ) ) return ; if ( instrAliased ( Other , getStoreTarget ( MI ) ) ) return ; unsigned BR = getBaseAddressRegister ( MI ) ; if ( BR == BaseReg ) { Group . push_back ( MI ) ; * I = nullptr ; continue ; } } if ( MI -> isCall ( ) || MI -> hasUnmodeledSideEffects ( ) ) return ; if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) { if ( MI -> hasOrderedMemoryRef ( ) || instrAliased


<s> for ( auto & I : MBB ) AllInsns . push_back ( & I ) ; for ( auto I = AllInsns . begin ( ) , E = AllInsns . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; if ( ! MI || ! handledStoreType ( MI ) ) continue ; InstrGroup G


<s> MachineInstr * MI = * I ; const MachineMemOperand & MMO = getStoreTarget ( MI ) ; MachineOperand & SO = MI -> getOperand ( <NUM_LIT> ) ; assert ( SO . isImm ( ) && <STR_LIT> ) ; unsigned NBits = MMO . getSize ( ) * <NUM_LIT> ; unsigned Mask = ( <NUM_LIT> >> ( <NUM_LIT> - NBits ) ) ; unsigned Val = ( SO . getImm ( ) & Mask ) << Shift ; Acc |= Val ; Shift += NBits ; } MachineInstr * FirstSt = OG . front ( ) ; DebugLoc DL = OG . back ( ) -> getDebugLoc ( ) ; const MachineMemOperand & OldM = getStoreTarget ( FirstSt ) ; MachineMemOperand * NewM = MF -> getMachineMemOperand ( OldM . getPointerInfo ( ) , OldM . getFlags ( ) , TotalSize , OldM . getAlignment ( ) , OldM . getAAInfo ( ) ) ; if ( Acc < <NUM_LIT> ) { unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT>


<s> if ( Acc < <NUM_LIT> ) { unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; int Val = ( TotalSize == <NUM_LIT> ) ? int16_t ( Acc ) : int ( Acc ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR . getSubReg ( ) ) . addImm ( Off ) . addImm ( Val ) ; StI -> addMemOperand ( * MF , NewM ) ; NG . push_back ( StI ) ; } else { const MCInstrDesc & TfrD = TII -> get ( <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TfrD , <NUM_LIT> , TRI , * MF ) ; unsigned VReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * TfrI = BuildMI ( * MF , DL , TfrD , VReg ) . addImm ( int ( Acc ) ) ; NG . push_back ( TfrI ) ; unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc &&


<s> AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addPreserved < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> static int64_t getStoreOffset ( const MachineInstr * MI ) { unsigned OpC = MI -> getOpcode ( ) ; assert ( <ISA_LIT>StoreWidening :: handledStoreType ( MI ) && <STR_LIT> ) ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm ( ) ; } } dbgs ( )


<s> static const MachineMemOperand & getStoreTarget ( const MachineInstr * MI


<s> assert ( ! MI -> memoperands_empty (


<s> <ISA_LIT>StoreWidening ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>StoreWideningPass ( * PassRegistry :: getPassRegistry (


<s> bool <ISA_LIT>StoreWidening :: instrAliased ( InstrGroup & Stores , const MachineInstr * MI ) { for ( auto & I : MI -> memoperands ( ) ) if ( instrAliased ( Stores , * I )


<s> assert ( OG . size ( ) > <NUM_LIT> && <STR_LIT> ) ; assert ( distance ( I , E ) + <NUM_LIT> >= int ( OG . size ( ) ) && <STR_LIT> ) ; I += OG . size ( ) - <NUM_LIT> ; Changed =


<s> dbgs ( ) << <STR_LIT> ; for ( auto I : OG ) dbgs ( ) << <STR_LIT> << * I ; dbgs ( ) << <STR_LIT>


<s> if ( SizeAccum >= MaxSize ) return false ; if ( SizeAccum >= Alignment ) return false ; if ( ( <NUM_LIT> * SizeAccum - <NUM_LIT> ) & FirstOffset ) return false ; OG . push_back ( FirstMI ) ; MachineInstr * S1 = FirstMI , * S2 = * ( Begin + <NUM_LIT> ) ; InstrGroup :: iterator I = Begin + <NUM_LIT> ; unsigned Pow2Num = <NUM_LIT> ; unsigned Pow2Size = SizeAccum ; while ( I != End ) { S2 = * I ; if ( ! storesAreAdjacent ( S1 , S2 ) ) break ; unsigned S2Size = getStoreTarget ( S2 ) . getSize ( ) ; if ( SizeAccum + S2Size > std :: min ( MaxSize , Alignment ) ) break ; OG . push_back ( S2 ) ; SizeAccum += S2Size ; if ( isPowerOf2_32 ( SizeAccum ) ) { Pow2Num = OG . size ( ) ; Pow2Size = SizeAccum ; } if ( ( <NUM_LIT> * Pow2Size - <NUM_LIT> ) & FirstOffset ) break ; S1 = S2 ; ++ I ; } if ( Pow2Num <= <NUM_LIT> ) { OG . clear (


<s> int Off2 = S2 -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Off1 >= <NUM_LIT> ) ? Off1 + S1MO . getSize ( ) == unsigned ( Off2 ) : int (


<s> I . setLatency ( Lat ) ; T . setSUnit ( Src ) ; auto F = find ( Dst -> Preds , T ) ; assert ( F != Dst -> Preds .


<s> bool enableMachineSchedDefaultSched ( ) const


<s> AntiDepBreakMode getAntiDepBreakMode ( ) const override { return


<s> const std :: string & getCPUString ( ) const { return


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins


<s> unsigned <ISA_LIT>Subtarget :: getL1CacheLineSize ( )


<s> Mutations . push_back ( std :: make_unique < UsrOverflowMutation > ( ) ) ; Mutations . push_back ( std :: make_unique < HVXMemLatencyMutation > ( ) ) ; Mutations . push_back ( std :: make_unique <


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return &


<s> unsigned getTypeAlignment ( MVT Ty ) const { if ( isHVXVectorType ( Ty , true ) ) return getVectorLength ( ) ; return Ty . getSizeInBits ( ) /


<s> assert ( useHVXOps ( ) ) ; if ( useHVX64BOps ( ) )


<s> unsigned getVectorLength ( ) const { assert ( useHVXOps ( ) ) ; if ( useHVX64BOps ( ) ) return <NUM_LIT> ; if ( useHVX128BOps ( ) ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT>


<s> for ( auto & I : Deps ) if ( I . isAssignedRegDep ( ) && I . getLatency ( ) == <NUM_LIT> && ! I . getSUnit ( ) -> getInstr ( ) -> isPseudo ( ) ) return I . getSUnit ( ) ; return nullptr


<s> bool hasMemNoShuf ( ) const { return


<s> bool hasReservedR19 ( ) const { return


<s> bool hasV55OpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) == <STR_LIT>


<s> return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT> ::


<s> bool hasV60OpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) ==


<s> bool hasV60OpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( )


<s> bool hasV62OpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) ==


<s> bool hasV65Ops ( ) const { return get<ISA_LIT>ArchVersion ( ) >=


<s> bool hasV66Ops ( ) const { return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT> ::


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , OptLevel ( TM . getOptLevel ( ) ) , CPUString ( std :: string ( <ISA_LIT>_MC :: select<ISA_LIT>CPU ( CPU ) ) ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) , InstrItins ( getInstrItineraryForCPU ( CPUString ) ) { <ISA_LIT>_MC :: addArchSubtarget ( this , FS ) ; assert ( InstrItins . Itineraries != nullptr && <STR_LIT>


<s> return F == <STR_LIT> || F == <STR_LIT> ; } ; if ( ! llvm :: count_if ( Features . getFeatures ( ) , IsQFloatFS ) ) { auto getHvxVersion = [ & Features ] ( StringRef FS ) -> StringRef { for ( StringRef F : llvm :: reverse ( Features . getFeatures ( ) ) ) { if ( F . startswith ( <STR_LIT> ) ) return F ; } for ( StringRef F : llvm :: reverse ( Features . getFeatures ( ) ) ) { if ( F == <STR_LIT> ) return StringRef ( ) ; if ( F . startswith ( <STR_LIT> ) || F == <STR_LIT> ) return F . take_front ( <NUM_LIT> ) ; } return StringRef ( ) ; } ; bool AddQFloat = false ; StringRef HvxVer = getHvxVersion ( FS ) ; if ( HvxVer . startswith ( <STR_LIT> ) ) { int Ver = <NUM_LIT> ; if ( ! HvxVer . drop_front ( <NUM_LIT> ) . consumeInteger ( <NUM_LIT> , Ver ) && Ver >= <NUM_LIT> ) AddQFloat = true ; } else if ( HvxVer == <STR_LIT> ) { if ( hasV68Ops ( ) )


<s> if ( Best != Dst ) return false ; if ( ( Src == SrcBest && Dst == DstBest ) || ( SrcBest == nullptr && Dst == DstBest ) || ( Src == SrcBest && Dst == nullptr ) ) return true ; if ( SrcBest != nullptr ) { if ( ! hasV60Ops ( ) ) changeLatency ( SrcBest , Dst , <NUM_LIT> ) ; else restoreLatency ( SrcBest , Dst ) ; } if ( DstBest != nullptr ) { if ( ! hasV60Ops ( ) ) changeLatency ( Src , DstBest , <NUM_LIT> ) ; else restoreLatency ( Src , DstBest ) ; } if ( SrcBest && DstBest ) changeLatency ( SrcBest , DstBest , <NUM_LIT> ) ; else if ( DstBest ) { ExclSrc . insert ( Src ) ; for ( auto & I : DstBest -> Preds ) if ( ExclSrc . count ( I . getSUnit ( ) ) == <NUM_LIT> && isBestZeroLatency ( I . getSUnit ( ) , DstBest , TII , ExclSrc , ExclDst ) ) changeLatency ( I . getSUnit ( ) , DstBest , <NUM_LIT> ) ; } else if ( SrcBest ) { ExclDst . insert ( Dst


<s> unsigned NumElems = VecTy . getVectorNumElements ( ) ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; if ( IncludeBool && ElemTy == <STR_LIT> ) { if ( <NUM_LIT> * HwLen == NumElems ) return true ; for ( MVT T : ElemTypes ) if ( NumElems * T . getSizeInBits ( ) == <NUM_LIT> * HwLen ) return true ; return


<s> bool <ISA_LIT>Subtarget :: isTypeForHVX ( Type * VecTy , bool IncludeBool ) const { if ( ! VecTy -> isVectorTy ( ) || isa < ScalableVectorType > ( VecTy ) ) return false ; Type * ScalTy = VecTy -> getScalarType ( ) ; if ( ! ScalTy -> isIntegerTy ( ) && ! ( ScalTy -> isFloatingPointTy ( ) &&

useHVXFloatingPoint ( ) ) ) return false ;


<s> int <ISA_LIT>Subtarget :: updateLatency ( MachineInstr & SrcInst , MachineInstr & DstInst , bool IsArtificial , int Latency ) const { if ( IsArtificial )


<s> if ( OptLevel != CodeGenOpt :: None ) return true ; return false


<s> bool <ISA_LIT>Subtarget :: useAA ( ) const { if ( OptLevel != CodeGenOpt :: None ) return true ; return false


<s> bool <ISA_LIT>Subtarget :: usePredicatedCalls ( ) const { return


<s> bool <ISA_LIT>Subtarget :: enableMachineScheduler ( ) const { if ( Disable<ISA_LIT>MISched . getNumOccurrences (


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( ) { initializeEnvironment ( ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ; else ModeIEEERndNear = false ; UseBSBScheduling = hasV60TOps ( )


<s> static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , } ; auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVXOps = false ; UseHVXDblOps = false ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( Enable<ISA_LIT>HVX . getPosition ( )


<s> Mutations . push_back ( llvm :: make_unique < <ISA_LIT>Subtarget


<s> void <ISA_LIT>Subtarget :: getSMSMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation >> & Mutations ) const { Mutations . push_back ( llvm :: make_unique <

<ISA_LIT>Subtarget :: <ISA_LIT>DAGMutation > ( ) ) ;


<s> return get<ISA_LIT>ArchVersion ( ) ==


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU )

, InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVXOps = false ; UseHVXDblOps = false ; UseLongCalls = false ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( Enable<ISA_LIT>HVX . getPosition ( ) ) UseHVXOps = Enable<ISA_LIT>HVX ; if ( Enable<ISA_LIT>HVXDouble . getPosition ( ) ) UseHVXDblOps = Enable<ISA_LIT>HVXDouble ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls


<s> SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( ( Src == SrcBest && Dst == DstBest ) || ( SrcBest == nullptr && Dst == DstBest ) || ( Src == SrcBest && Dst == nullptr ) ) return true ; if ( SrcBest != nullptr ) { if ( ! hasV60TOps ( ) ) changeLatency ( SrcBest , Dst , <NUM_LIT> ) ; else restoreLatency ( SrcBest , Dst ) ; } if ( DstBest != nullptr ) { if ( ! hasV60TOps ( ) ) changeLatency ( Src , DstBest , <NUM_LIT> ) ; else restoreLatency ( Src , DstBest ) ; } if ( SrcBest && DstBest ) changeLatency ( SrcBest , DstBest , <NUM_LIT> ) ; else if ( DstBest ) { ExclSrc . insert ( Src ) ; for ( auto & I : DstBest -> Preds ) if ( ExclSrc . count ( I . getSUnit ( ) ) == <NUM_LIT> && isBestZeroLatency ( I . getSUnit ( ) , DstBest , TII , ExclSrc , ExclDst ) ) changeLatency ( I . getSUnit ( ) , DstBest , <NUM_LIT> ) ; } else if ( SrcBest ) { ExclDst . insert ( Dst ) ; for ( auto & I : SrcBest -> Succs ) if ( ExclDst . count ( I . getSUnit ( ) ) == <NUM_LIT> && isBestZeroLatency ( SrcBest , I . getSUnit ( ) , TII , ExclSrc , ExclDst ) ) changeLatency ( SrcBest , I . getSUnit ( ) , <NUM_LIT> ) ; } return true


<s> if ( ! I . isAssignedRegDep ( ) || I . getSUnit ( ) != Dst ) continue ; unsigned DepR = I . getReg ( ) ; int DefIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < SrcI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = SrcI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == DepR ) DefIdx = OpNum ; } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; if ( Latency <= <NUM_LIT> ) Latency = <NUM_LIT> ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } } for ( auto & J : Dst -> Preds ) { if ( J . getSUnit (


<s> void <ISA_LIT>Subtarget :: updateLatency ( MachineInstr & SrcInst , MachineInstr & DstInst , SDep & Dep ) const { if ( Dep . isArtificial ( ) ) { Dep . setLatency (


<s> if ( ! VecTy -> isVectorTy ( ) || isa < ScalableVectorType > ( VecTy ) ) return false ; if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT Ty = EVT :: getEVT ( VecTy , false ) ; if ( Ty . getSizeInBits ( ) <= <NUM_LIT> || ! Ty . getVectorElementType ( )


<s> if ( ! I . isAssignedRegDep ( ) || I . getSUnit ( ) != Dst ) continue ; Register DepR = I . getReg ( ) ; int DefIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < SrcI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = SrcI -> getOperand ( OpNum ) ; bool IsSameOrSubReg = false ; if ( MO . isReg ( ) ) { Register MOReg = MO . getReg ( ) ; if ( DepR . isVirtual ( ) ) { IsSameOrSubReg = ( MOReg == DepR ) ; } else { IsSameOrSubReg = getRegisterInfo ( ) -> isSubRegisterEq ( DepR , MOReg ) ; } if ( MO . isDef ( ) && IsSameOrSubReg ) DefIdx = OpNum ; } } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; SDep T = I ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; Latency = std :: max ( Latency , <NUM_LIT> ) ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } } T . setSUnit ( Src ) ; auto F = find ( Dst