<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ||


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isNewValue ( const MachineInstr & MI


<s> bool <ISA_LIT>InstrInfo :: isNewValueInst ( const MachineInstr & MI ) const { return isNewValueJump ( MI ) ||


<s> bool <ISA_LIT>InstrInfo :: isNewValueJump ( const MachineInstr


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> )


<s> bool <ISA_LIT>InstrInfo :: isOperandExtended ( const MachineInstr & MI , unsigned OperandNum ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ==


<s> if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ; for ( auto I : MBB -> successors ( ) ) if


<s> bool <ISA_LIT>InstrInfo :: isSolo ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT>


<s> const uint64_t F = MI . getDesc ( ) .


<s> for ( auto & Op : MI . operands ( ) ) if ( Op . isGlobal ( ) || Op . isSymbol (


<s> bool <ISA_LIT>InstrInfo :: isTailCall ( const MachineInstr & MI ) const { if ( ! MI . isBranch ( )


<s> bool <ISA_LIT>InstrInfo :: isTC1 ( const MachineInstr & MI ) const { unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; return is_TC1 (


<s> bool <ISA_LIT>InstrInfo :: isTC1 ( const MachineInstr & MI ) const { unsigned SchedClass = MI . getDesc ( ) . getSchedClass (


<s> bool <ISA_LIT>InstrInfo :: isTC2Early ( const


<s> unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; return is_TC2early ( SchedClass


<s> bool <ISA_LIT>InstrInfo :: isTC4x ( const MachineInstr & MI


<s> } if ( mayBeNewStore ( MI2 ) ) if ( MI2 . getOpcode ( ) == <STR_LIT> ) if ( MI1 . getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 . getOperand ( <NUM_LIT> ) . isReg ( ) &&

MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) == MI2 . getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ;


<s> case <STR_LIT> : return isInt < <NUM_LIT> > ( Count ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( Count ) ; default : break ; } llvm_unreachable (


<s> case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > (


<s> bool <ISA_LIT>InstrInfo :: isVecAcc ( const MachineInstr & MI ) const { return isHVXVec ( MI ) && isAccumulator ( MI


<s> bool <ISA_LIT>InstrInfo :: isVecAcc ( const MachineInstr & MI ) const { return isHVXVec ( MI ) &&


<s> const uint64_t F = get ( MI . getOpcode ( ) ) . TSFlags ; const uint64_t V = ( ( F >> <STR_LIT> ) &


<s> bool <ISA_LIT>InstrInfo :: isVecALU ( const MachineInstr & MI ) const { const uint64_t F = get ( MI . getOpcode ( ) ) . TSFlags ; const uint64_t V = ( ( F >> <STR_LIT> )


<s> if ( EnableACCForwarding && isVecAcc ( ProdMI ) && isVecAcc ( ConsMI ) ) return true ; if ( EnableALUForwarding && ( isVecALU ( ConsMI ) || isLateSourceInstr ( ConsMI ) ) ) return true ; if ( mayBeNewStore ( ConsMI ) ) return


<s> if ( EnableACCForwarding && isVecAcc ( ProdMI ) && isVecAcc ( ConsMI ) ) return true ; if ( EnableALUForwarding && ( isVecALU ( ConsMI ) || isLateSourceInstr (


<s> return ( ( F >> <STR_LIT> ) & <STR_LIT> ) && Subtarget . hasV60Ops


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI ) const { if ( MI . mayStore ( ) && ! Subtarget . useNewValueStores ( ) ) return false ; const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> )


<s> for ( ; MIB != MIE ; ++ MIB ) { if ( ! MIB -> isDebugInstr ( ) )


<s> bool <ISA_LIT>InstrInfo :: PredOpcodeHasJMP_c ( unsigned Opcode ) const { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode

== <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> unsigned <ISA_LIT>InstrInfo :: reduceLoopCount ( MachineBasicBlock & MBB , MachineInstr * IndVar , MachineInstr & Cmp , SmallVectorImpl < MachineOperand > & Cond , SmallVectorImpl < MachineInstr * > & PrevInsts , unsigned Iter , unsigned MaxIter ) const { assert ( ( ! IndVar ) && isEndLoopN ( Cmp . getOpcode ( ) ) && <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; DebugLoc DL = Cmp . getDebugLoc ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( & MBB , Cmp . getOpcode ( ) , Cmp . getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( ! Loop ) return <NUM_LIT> ; if ( Loop -> getOpcode ( ) == <STR_LIT> || Loop -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ; PrevInsts . clear (


<s> DebugLoc DL = Cmp . getDebugLoc ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( & MBB , Cmp . getOpcode ( ) , Cmp . getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( ! Loop ) return <NUM_LIT> ; if ( Loop -> getOpcode ( ) == <STR_LIT> || Loop -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( NewCmp -> getOperand (


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back


<s> if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back (


<s> if ( Cond . empty ( ) ) return true ; assert ( Cond [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ; unsigned opcode = Cond [ <NUM_LIT>


<s> assert ( get ( opcode ) . isBranch ( ) && <STR_LIT> ) ; if ( isEndLoopN ( opcode ) ) return true ; unsigned NewOpcode = getInvertedPredicatedOpcode ( opcode ) ; Cond [ <NUM_LIT> ] . setImm (


<s> bool <ISA_LIT>InstrInfo :: reversePredSense ( MachineInstr & MI ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; MI . setDesc ( get ( getInvertedPredicatedOpcode ( MI .


<s> assert ( MIB -> isBundle ( ) ) ; MachineOperand & Operand = MIB -> getOperand ( <NUM_LIT> ) ; if ( Operand . isImm ( ) ) Operand . setImm ( Operand


<s> MachineOperand & Operand = MIB -> getOperand ( <NUM_LIT> ) ; if ( Operand . isImm ( ) ) Operand . setImm ( Operand


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq (


<s> if ( isV60VectorInstruction ( MI1 ) && isV60VectorInstruction ( MI2 ) ) if ( ! isVecUsableNextPacket ( MI1 , MI2


<s> bool <ISA_LIT>InstrInfo :: addLatencyToSchedule ( const MachineInstr * MI1 , const MachineInstr * MI2 ) const { if ( isV60VectorInstruction ( MI1 ) && isV60VectorInstruction ( MI2 ) ) if ( ! isVecUsableNextPacket


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: analyzeLoop ( MachineLoop & L , MachineInstr * & IndVarInst , MachineInstr * & CmpInst ) const { MachineBasicBlock * LoopEnd = L . getBottomBlock ( ) ; MachineBasicBlock :: iterator I = LoopEnd


<s> if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second -> getOperand ( Second -> getNumOperands ( ) - <NUM_LIT> ) ; if ( ! Stored . isReg ( ) ) return


<s> bool <ISA_LIT>InstrInfo :: canExecuteInBundle ( const MachineInstr * First , const MachineInstr * Second ) const { if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second -> getOperand ( Second -> getNumOperands ( ) - <NUM_LIT> ) ; if ( ! Stored . isReg ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = First -> getNumOperands ( ) ; i < e


<s> if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains


<s> ScheduleHazardRecognizer * <ISA_LIT>InstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData *


<s> return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II


<s> TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; }


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const TargetRegisterClass * TRC ; if ( VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC =


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI . getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI . getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return


<s> } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return <NUM_LIT> ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; } return


<s> int LOOPr ; if ( EndLoopOp == <STR_LIT> ) { LOOPi = <STR_LIT> ; LOOPr = <STR_LIT> ; } else { LOOPi = <STR_LIT> ; LOOPr = <STR_LIT> ; } for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return <NUM_LIT>


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr


<s> short <ISA_LIT>InstrInfo :: getAbsoluteForm ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode


<s> const uint64_t F = MI -> getDesc ( )


<s> short <ISA_LIT>InstrInfo :: getBaseWithLongOffset ( const MachineInstr * MI ) const { return <STR_LIT> ( MI ->


<s> short <ISA_LIT>InstrInfo :: getBaseWithRegOffset ( const MachineInstr *


<s> short <ISA_LIT>InstrInfo :: getBaseWithRegOffset ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode (


<s> -- I ; if ( I -> isEHLabel ( ) ) return Jumpers ; } while ( I != MBB . instr_begin ( ) ) ; I = MBB . instr_end ( ) ; -- I ; while ( I -> isDebugValue ( ) ) { if ( I == MBB . instr_begin ( ) ) return Jumpers ; -- I ; } if ( ! isUnpredicatedTerminator ( * I ) ) return Jumpers ; MachineInstr * LastInst = & * I ; Jumpers . push_back ( LastInst ) ; MachineInstr * SecondLastInst = nullptr ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( * I ) ) { if ( ! SecondLastInst ) { SecondLastInst = & * I ; Jumpers . push_back ( SecondLastInst ) ; } else return Jumpers ; } if ( I == MBB . instr_begin ( ) ) break ; --


<s> unsigned <ISA_LIT>InstrInfo :: getCExtOpNum ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) &


<s> if ( ( GA -> getOpcode ( ) != <STR_LIT> ) || ( GB -> getOpcode ( ) != <STR_LIT> ) ) return - <NUM_LIT> ; unsigned DestReg = GA -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! GB -> readsRegister ( DestReg ) )


<s> enum <STR_LIT> inPredSense ; inPredSense = invertPredicate ? <STR_LIT> : <STR_LIT> ; int CondOpcode = <STR_LIT> ( Opc , inPredSense ) ; if ( CondOpcode >= <NUM_LIT> ) return CondOpcode ; switch ( Opc ) { case <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return


<s> if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool taken = false ; const MachineBasicBlock * Src = MI -> getParent ( ) ; const MachineOperand * BrTarget = & MI -> getOperand ( <NUM_LIT> ) ; const MachineBasicBlock * Dst = BrTarget -> getMBB ( ) ; const BranchProbability Prediction = MBPI -> getEdgeProbability ( Src , Dst ) ; if ( Prediction >= BranchProbability ( <NUM_LIT> , <NUM_LIT> ) ) taken


<s> case <STR_LIT> : case <STR_LIT> : return getDotNewPredJumpOp ( MI , MBPI ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } return <NUM_LIT>


<s> int NewOp = opc ; if ( isPredicated ( NewOp ) && isPredicatedNew ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; assert ( NewOp >= <NUM_LIT> &&


<s> short <ISA_LIT>InstrInfo :: getEquivalentHWInstr ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT>


<s> for ( auto MII = BB -> instr_begin ( ) , End = BB -> instr_end ( ) ; MII != End ; MII ++ ) { MachineInstr * MI = & * MII ; if ( MI -> isDebugValue ( ) ) continue ; return MI ; } return


<s> unsigned AccessSize ; return getBaseAndOffset ( MI , Value , AccessSize ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { Value = MI -> getOperand ( <NUM_LIT> ) .


<s> atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) , strlen ( MAI . getCommentString ( ) ) ) == <NUM_LIT> ) atInsnStart = false ; } StringRef Occ ( <STR_LIT> ) ; Length += AStr . count ( Occ ) * <NUM_LIT> ; return Length


<s> if ( ! ItinData ) return getInstrLatency ( ItinData , * MI ) ; if ( MI -> isTransient ( ) ) return <NUM_LIT> ; unsigned Latency = ItinData -> getStageLatency ( MI -> getDesc ( ) . getSchedClass (


<s> unsigned <ISA_LIT>InstrInfo :: getInstrTimingClassLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI ) const { if ( ! ItinData ) return getInstrLatency ( ItinData , * MI ) ; if ( MI -> isTransient ( ) ) return <NUM_LIT> ; unsigned Latency = ItinData -> getStageLatency ( MI -> getDesc ( ) . getSchedClass ( ) ) ; if ( ! EnableTimingClassLatency || MI -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . useBSBScheduling ( ) ) if (

Latency > <NUM_LIT> ) Latency = <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: getInvertedPredSense ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . empty ( ) ) return false ; unsigned Opc = getInvertedPredicatedOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( Opc ) ; return true


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) &


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned AccessSize =


<s> unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F >> <STR_LIT>


<s> short NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( )


<s> short <ISA_LIT>InstrInfo :: getPseudoInstrPair ( const MachineInstr *


<s> short <ISA_LIT>InstrInfo :: getRegForm ( const MachineInstr * MI ) const { return <STR_LIT> ( MI -> getOpcode ( )


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI


<s> for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) assert ( NumDefs != MI -> getNumOperands ( ) - <NUM_LIT> && <STR_LIT> ) ; assert ( MI -> getOperand ( NumDefs ) . isSymbol ( ) && <STR_LIT> ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; Size = getInlineAsmLength ( AsmStr , * MAI


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> )


<s> unsigned <ISA_LIT>InstrInfo :: getUnits ( const MachineInstr * MI ) const { const TargetSubtargetInfo & ST = MI -> getParent ( )


<s> unsigned <ISA_LIT>InstrInfo :: getValidSubTargets ( const unsigned Opcode


<s> const uint64_t F = get ( Opcode ) . TSFlags ; return ( F >>


<s> bool <ISA_LIT>InstrInfo :: hasEHLabel ( const MachineBasicBlock * B ) const { for ( auto & I : * B ) if


<s> for ( auto & I : * B ) if ( I . isEHLabel ( ) ) return true ; return false


<s> if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( )


<s> return <STR_LIT> ( MI -> getOpcode ( ) ,


<s> if ( I -> isBarrier ( ) ) return true ; ++ I ; } return false


<s> RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT>


<s> unsigned NewOpcode = getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; int TargetPos = MI -> getNumOperands ( ) - <NUM_LIT> ; while ( ( TargetPos > - <NUM_LIT> ) && ! MI -> getOperand ( TargetPos ) . isMBB ( ) ) -- TargetPos ; assert ( ( TargetPos >= <NUM_LIT> ) && MI -> getOperand


<s> bool <ISA_LIT>InstrInfo :: isAbsoluteSet ( const MachineInstr * MI ) const { return ( getAddrMode ( MI ) == <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isAccumulator ( const MachineInstr * MI ) const { const uint64_t F = MI ->


<s> bool <ISA_LIT>InstrInfo :: isComplex ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo


<s> return ( MI -> isBranch ( ) && isPredicated ( * MI ) ) || isConditionalTransfer ( MI ) || isConditionalALU32 ( MI ) || isConditionalLoad ( MI ) || ( MI -> mayStore ( ) && isPredicated ( * MI ) && ! isNewValueStore ( MI ) && !


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> int PNewOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; return PNewOpcode >=


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isConditionalTransfer ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue (


<s> return isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) && isIntRegForSubInst

( HRI . getSubReg ( Reg , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isDotCurInst ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>InstrInfo :: isDotNewInst ( const MachineInstr * MI ) const { if ( isNewValueInst ( MI ) || ( isPredicated ( * MI ) && isPredicatedNew (


<s> bool <ISA_LIT>InstrInfo :: isDotNewInst ( const MachineInstr * MI ) const { if ( isNewValueInst ( MI ) || ( isPredicated ( * MI ) && isPredicatedNew ( * MI ) )


<s> <STR_LIT> MIbG = getDuplexCandidateGroup ( MIb ) ; return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch


<s> bool <ISA_LIT>InstrInfo :: isDuplexPair ( const MachineInstr * MIa , const MachineInstr * MIb ) const { <STR_LIT> MIaG = getDuplexCandidateGroup


<s> case <STR_LIT> : return ( Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> ) ; case <STR_LIT> : return ( Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> || Gb == <STR_LIT> ) ; case <STR_LIT> : return ( Gb == <STR_LIT> ) ; case <STR_LIT> : return ( Gb == <STR_LIT> ) ; } return false


<s> if ( ! MI ) return false ; if ( MI -> mayLoad ( ) || MI -> mayStore ( ) || MI -> isCompare ( ) ) return true ; unsigned SchedClass = MI -> getDesc ( ) . getSchedClass ( ) ; if ( SchedClass == <STR_LIT> :: M_tc_3or4x_SLOT23 ) return true ; return


<s> bool <ISA_LIT>InstrInfo :: isEarlySourceInstr ( const MachineInstr * MI ) const { if ( ! MI ) return false ; if ( MI -> mayLoad ( ) || MI -> mayStore

( ) || MI -> isCompare ( ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isExtended ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ; for ( MachineInstr :: const_mop_iterator I = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; I != E ; ++ I ) { if ( I -> getTargetFlags ( ) && <STR_LIT> ) return true ; } return


<s> bool <ISA_LIT>InstrInfo :: isFloat ( const MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ; const uint64_t F = get ( Opcode ) .


<s> if ( ! isV60VectorInstruction ( I ) ) return false ; if ( ! I -> mayLoad ( ) && ! I -> mayStore ( ) ) return false ; return J -> isIndirectBranch ( ) || isIndirectCall ( J ) || isIndirectL4Return (


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isIndirectCall ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return


<s> bool <ISA_LIT>InstrInfo :: isIndirectL4Return ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) || ( Reg >= <STR_LIT> && Reg


<s> bool <ISA_LIT>InstrInfo :: isJumpR ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case


<s> return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> >


<s> DEBUG ( LRMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( ESMI -> dump ( ) ) ; if ( isLate && isEarly ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } return


<s> return MI -> getDesc ( ) . getSchedClass ( ) ==


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT>


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>InstrInfo :: isNewValue ( unsigned Opcode ) const { const uint64_t F = get ( Opcode


<s> const uint64_t F = get ( Opcode ) . TSFlags ; return ( F >> <STR_LIT> )


<s> bool <ISA_LIT>InstrInfo :: isNewValueJump ( unsigned Opcode ) const { return isNewValue ( Opcode ) && get ( Opcode ) . isBranch ( ) && isPredicated


<s> bool <ISA_LIT>InstrInfo :: isOperandExtended ( const MachineInstr * MI ,


<s> bool <ISA_LIT>InstrInfo :: isPostIncrement ( const MachineInstr *


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( unsigned Opcode ) const { const uint64_t F = get ( Opcode


<s> const uint64_t F = get ( Opcode ) . TSFlags ; assert ( isPredicated ( Opcode ) ) ; return ( F >> <STR_LIT>


<s> const uint64_t F = get ( Opcode ) . TSFlags ; assert ( ( F >> <STR_LIT> )


<s> bool <ISA_LIT>InstrInfo :: isPredicateLate ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ; return ~ ( F >> <STR_LIT> ) &


<s> assert ( get ( Opcode ) . isBranch ( ) && ( isPredicatedNew

( Opcode ) || isNewValue ( Opcode ) ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return nonDbgBBSize ( & TMBB ) <= <NUM_LIT> && nonDbgBBSize ( & FMBB


<s> return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode

( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isSaveCalleeSavedRegsCall ( const MachineInstr * MI ) const { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( )

== <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return true ; if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isSolo ( const MachineInstr


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! MI -> isBranch ( ) ) return false ; for ( auto & Op : MI -> operands ( ) ) if ( Op . isGlobal ( ) || Op . isSymbol ( ) ) return true ; return false


<s> bool <ISA_LIT>InstrInfo :: isTailCall ( const MachineInstr * MI ) const { if ( ! MI -> isBranch ( ) )


<s> if ( ! MI ) return false ; unsigned SchedClass = MI -> getDesc ( )


<s> const uint64_t V = getType ( MI ) ; return <STR_LIT> <= V && V


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN_128B ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX_128B ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! MI ) return false ; const uint64_t F = get ( MI -> getOpcode ( ) ) . TSFlags ; const uint64_t V = ( ( F >> <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isVecUsableNextPacket ( const MachineInstr * ProdMI , const MachineInstr * ConsMI ) const { if ( EnableACCForwarding && isVecAcc ( ProdMI ) && isVecAcc ( ConsMI ) ) return true ; if ( EnableALUForwarding && ( isVecALU ( ConsMI ) || isLateSourceInstr ( ConsMI ) )


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) .


getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr * MI ) const { auto & HST = MI -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const uint64_t F = MI -> getDesc


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr *


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr


<s> unsigned <ISA_LIT>InstrInfo :: nonDbgBBSize ( const MachineBasicBlock * BB ) const { return nonDbgMICount ( BB -> instr_begin ( ) , BB ->


<s> unsigned <ISA_LIT>InstrInfo :: nonDbgBBSize ( const MachineBasicBlock * BB


<s> for ( ; MIB != MIE ; ++ MIB ) { if ( ! MIB -> isDebugValue ( ) )


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg


<s> while ( NOp < NumOps ) { MachineOperand & Op = MI . getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI . getOperand ( NOp ++ ) ) ; MI . setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI . getNumOperands ( ) ) MI . RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI . addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo


<s> bool <ISA_LIT>InstrInfo :: PredOpcodeHasJMP_c ( unsigned Opcode ) const { return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> )

|| ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: predOpcodeHasNot ( ArrayRef < MachineOperand > Cond ) const { if ( Cond . empty ( ) || ! isPredicated ( Cond [ <NUM_LIT> ] . getImm ( ) )


<s> MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , getRegisterInfo ( ) ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ; Cond . push_back ( MachineOperand :: CreateImm


<s> assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , getRegisterInfo ( ) ) ; PrevInsts . clear ( )


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . empty ( ) ) return true ; assert ( Cond [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ; unsigned opcode = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( get ( opcode ) . isBranch ( ) && <STR_LIT> ) ; if ( isEndLoopN ( opcode ) ) return true ; unsigned NewOpcode = getInvertedPredicatedOpcode ( opcode ) ; Cond [ <NUM_LIT> ] . setImm (


<s> unsigned <ISA_LIT>InstrInfo :: reversePrediction ( unsigned Opcode ) const { int PredRevOpcode = - <NUM_LIT> ; if ( isPredictedTaken ( Opcode ) ) PredRevOpcode = <STR_LIT> ( Opcode ) ; else PredRevOpcode = <STR_LIT> ( Opcode ) ; assert ( PredRevOpcode > <NUM_LIT> ) ; return


<s> MI -> setDesc ( get ( getInvertedPredicatedOpcode ( MI -> getOpcode (


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; unsigned KillFlag = getKillRegState ( isKill ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) .


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand >

Pred1 , ArrayRef < MachineOperand > Pred2 ) const {


<s> bool <ISA_LIT>InstrInfo :: validateBranchCond ( const ArrayRef < MachineOperand >


<s> return Cond . empty ( ) || ( Cond [ <NUM_LIT> ] . isImm ( ) && (


<s> return <STR_LIT> ( MI -> getOpcode (


<s> return <STR_LIT> ( MI -> getOpcode ( )


<s> if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB


<s> unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ; } return false


<s> } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { unsigned LoSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; unsigned HiSrc = HRI . getSubReg ( SrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HiSrc , KillFlag ) . addReg ( LoSrc , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { llvm_unreachable ( <STR_LIT> )


<s> ScheduleHazardRecognizer * <ISA_LIT>InstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( UseDFAHazardRec ) { auto & HST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return new <ISA_LIT>HazardRecognizer ( II , this , HST


<s> if ( UseDFAHazardRec ) { auto & HST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return new <ISA_LIT>HazardRecognizer ( II , this , HST ) ; } return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer (


<s> void <ISA_LIT>InstrInfo :: genAllInsnTimingClasses ( MachineFunction & MF ) const { MachineFunction :: iterator A = MF . begin ( ) ; MachineBasicBlock & B = * A ; MachineBasicBlock :: iterator I = B . begin ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstr * NewMI ; for ( unsigned insn = TargetOpcode :: GENERIC_OP_END + <NUM_LIT> ; insn < <STR_LIT> ; ++ insn ) { NewMI = BuildMI ( B , I , DL , get ( insn ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getName ( NewMI -> getOpcode ( ) ) << <STR_LIT> << NewMI -> getDesc ( ) .


<s> assert ( getMemAccessSize ( MI ) && <STR_LIT> ) ; AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned basePos = <NUM_LIT> , offsetPos = <NUM_LIT> ; if ( ! getBaseAndOffsetPosition ( MI , basePos , offsetPos ) ) return <NUM_LIT> ; if ( isPostIncrement ( MI ) ) Offset = <NUM_LIT> ; else { Offset = MI . getOperand ( offsetPos ) . getImm ( ) ; } return MI . getOperand ( basePos ) .


<s> if ( getAddrMode ( MI ) != <STR_LIT> && getAddrMode ( MI ) != <STR_LIT> && ! isMemOp ( MI ) && ! isPostIncrement ( MI ) ) return <NUM_LIT> ; assert ( getMemAccessSize ( MI ) && <STR_LIT> ) ; AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned basePos = <NUM_LIT> , offsetPos = <NUM_LIT> ; if ( ! getBaseAndOffsetPosition ( MI ,

basePos , offsetPos ) ) return <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: getBaseAndOffsetPosition ( const MachineInstr & MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( isMemOp ( MI ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI . mayStore ( ) ) { BasePos = <NUM_LIT> ; OffsetPos =


<s> short <ISA_LIT>InstrInfo :: getBaseWithLongOffset ( const MachineInstr & MI ) const { return <STR_LIT> ( MI .


<s> short <ISA_LIT>InstrInfo :: getBaseWithRegOffset ( const MachineInstr & MI ) const { return <STR_LIT> ( MI .


<s> SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && isIntRegForSubInst ( Src1Reg ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Src1Reg ) && ( <STR_LIT> == Src1Reg || <STR_LIT> == Src1Reg


<s> if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : llvm :: report_fatal_error ( std :: string ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) . c_str ( ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> default : llvm :: report_fatal_error ( std :: string ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) . c_str ( ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> : NewOp = <STR_LIT> ; break ; } } assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ; } if ( isNewValueStore ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ; } if ( HST . hasV60TOps ( ) ) return NewOp ; switch ( NewOp ) { case <STR_LIT> : return <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: getIncrementValue ( const MachineInstr & MI , int & Value ) const { if ( isPostIncrement ( MI ) ) { unsigned AccessSize ; return getBaseAndOffset ( MI , Value , AccessSize ) ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { Value = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; } return false


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned AccessSize =


<s> if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode


<s> if ( MI . isDebugValue ( ) || MI . isPosition ( ) ) return <NUM_LIT> ; unsigned Size = MI . getDesc ( ) . getSize ( ) ; if ( ! Size ) Size = HEXAGON_INSTR_SIZE ; if ( isConstExtended ( MI ) || isExtended ( MI ) ) Size += HEXAGON_INSTR_SIZE ; if ( BranchRelaxAsmLarge && MI . getOpcode ( ) == <STR_LIT> ) { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; unsigned NumDefs = <NUM_LIT> ; for ( ; MI . getOperand ( NumDefs ) . isReg ( ) && MI . getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) assert ( NumDefs != MI . getNumOperands ( ) - <NUM_LIT> && <STR_LIT> ) ; assert ( MI . getOperand ( NumDefs ) . isSymbol ( ) && <STR_LIT> ) ; const char * AsmStr = MI . getOperand (


<s> const TargetSubtargetInfo & ST = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) ; const InstrItineraryData & II = *


<s> const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits


<s> if ( <STR_LIT> ( MI . getOpcode ( ) ) >= <NUM_LIT> ) return true ; if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; default : return false ; } if ( NonExtOpcode < <NUM_LIT> ) return false ; return


<s> if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; break ; case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI .


<s> DEBUG ( dbgs ( ) << <STR_LIT> << NewTarget -> getNumber ( ) ; MI . dump ( ) ; ) ; assert ( MI . isBranch ( ) ) ; unsigned NewOpcode = getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; int TargetPos = MI . getNumOperands ( ) - <NUM_LIT> ; while ( ( TargetPos > - <NUM_LIT> ) && ! MI . getOperand ( TargetPos


<s> if ( ! isExtendable ) return false ; if ( MI . isCall ( ) ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI . getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) || MO . isFPImm ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI )


<s> if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) || MO . isFPImm ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI ) ; int MaxValue = getMaxValue ( MI ) ; int ImmValue = MO


<s> bool <ISA_LIT>InstrInfo :: isDependent ( const MachineInstr & ProdMI , const MachineInstr & ConsMI ) const { if ( ! ProdMI . getDesc ( ) . getNumDefs ( ) ) return false ; auto & HRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ; } return


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ; for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( I -> getTargetFlags ( ) && <STR_LIT>


<s> for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( I -> getTargetFlags ( ) && <STR_LIT> ) return true ; } return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> DEBUG ( LRMI . dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( ESMI . dump ( ) ) ; if ( isLate && isEarly ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true


<s> switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case


<s> bool <ISA_LIT>InstrInfo :: isMemOp ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . usePredicatedCalls ( ) ) return false ; } return true


<s> if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ; for ( auto I : MBB -> successors ( ) ) if ( I ->


<s> if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . isInlineAsm ( ) && !


<s> bool <ISA_LIT>InstrInfo :: isValidOffset ( unsigned Opcode , int Offset , bool Extend ) const { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN_128B ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX_128B ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr & MI ) const { auto & HST = MI . getParent ( ) -> getParent (

) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI


<s> int Opc = MI . getOpcode ( ) ; assert ( isPredicable ( MI ) && <STR_LIT> ) ; bool invertJump = predOpcodeHasNot ( Cond ) ; MachineBasicBlock & B = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI . getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI . getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . add ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . add ( MI . getOperand ( NOp ++ ) ) ; MI . setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI . getNumOperands ( ) ) MI . RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI . addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase


<s> MachineBasicBlock :: const_instr_iterator MII = BII ; MachineBasicBlock :: const_instr_iterator MIE = MII -> getParent ( ) -> instr_end ( ) ; if ( ! ( * MII ) . isBundle ( ) ) { const MachineInstr & J = * MII ; return producesStall ( J , MI ) ; } for ( ++ MII ; MII != MIE && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & J = * MII ; if ( producesStall ( J , MI ) ) return true ; } return false


<s> if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count ; } return Count


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB . end ( ) ; ++ Count


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ) ; MI . setDesc ( get ( getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ) ) ; return true


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; MI .


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) Align = HFI . getStackAlignment ( ) ; unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; }


<s> MachineInstr * SecondLastInst = NULL ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( I ) ) { if ( ! SecondLastInst ) SecondLastInst = I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } while ( I ) ; int LastOpcode = LastInst -> getOpcode ( ) ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return


<s> bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } return true


<s> return changeAddrMode_abs_io ( MI . getOpcode


<s> short changeAddrMode_io_abs ( const MachineInstr & MI ) const { return changeAddrMode_io_abs ( MI .


<s> short changeAddrMode_io_abs ( const MachineInstr &


<s> return changeAddrMode_io_rr ( MI . getOpcode ( )


<s> short changeAddrMode_io_rr ( const MachineInstr


<s> short changeAddrMode_rr_ur ( const MachineInstr &


<s> return changeAddrMode_rr_ur ( MI . getOpcode ( )


<s> return changeAddrMode_ur_rr ( MI . getOpcode ( )


<s> return TM -> getSubtarget < <ISA_LIT>GenSubtargetInfo > ( ) .


<s> CreateTargetScheduleState ( const TargetMachine * TM ,


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned >


<s> int <ISA_LIT>InstrInfo :: GetDotNewOp ( const MachineInstr * MI ) const { int NVOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT>


<s> int <ISA_LIT>InstrInfo :: getDotNewPredJumpOp ( MachineInstr * MI , const MachineBranchProbabilityInfo * MBPI ) const { bool taken = false ; MachineBasicBlock * Src = MI -> getParent ( ) ; MachineOperand * BrTarget = & MI -> getOperand ( <NUM_LIT> ) ; MachineBasicBlock * Dst = BrTarget -> getMBB (


<s> int <ISA_LIT>InstrInfo :: GetDotOldOp ( const int opc ) const { int NewOp = opc ; if ( isPredicated ( NewOp ) && isPredicatedNew (


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> int <ISA_LIT>InstrInfo :: getMaxValue ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F


<s> unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isSigned ) return - <NUM_LIT> << ( bits - <NUM_LIT> ) ; else return <NUM_LIT>


<s> int <ISA_LIT>InstrInfo :: getMinValue ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( )


<s> if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , <NUM_LIT> , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ regPos ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ regPos


<s> bool <ISA_LIT>InstrInfo :: isConditionalALU32 ( const MachineInstr * MI ) const { const <ISA_LIT>RegisterInfo & QRI = getRegisterInfo ( ) ; switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> if ( ! Subtarget . hasV4TOps ( ) ) return false ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isExtended = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isExtended ) return true ; unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI ) ; int MaxValue = getMaxValue (


<s> bool <ISA_LIT>InstrInfo :: isConstExtended ( MachineInstr * MI ) const { if ( ! Subtarget . hasV4TOps ( ) ) return false ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isExtended = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isExtended ) return true ; unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) ) return true ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int MinValue = getMinValue ( MI ) ; int MaxValue = getMaxValue ( MI


<s> bool <ISA_LIT>InstrInfo :: isDeallocRet ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs , const BranchProbability & Probability ) const { return ( NumInstrs <= <NUM_LIT>


<s> isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs , const BranchProbability & Probability


<s> isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles

, const BranchProbability & Probability ) const {


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , const BranchProbability & Probability ) const { return true


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue (


<s> if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) return true ; return false


<s> case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( ( F >> <STR_LIT> ) & <STR_LIT> & QRI . Subtarget . hasV4TOps (


<s> for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand & MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else if ( MO . isGlobal ( ) ) { assert ( hasGAOpnd == false && <STR_LIT> ) ; tmpOpnds . push_back ( MO ) ; hasGAOpnd = true ; GAIdx = oper ; continue ; } else { assert ( false && <STR_LIT> ) ; } } } int regPos = invertJump ? <NUM_LIT> :


<s> return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode

== <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> return ( Opcode == <STR_LIT> ) || ( Opcode ==

<STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> .


<s> DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg


<s> SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 ,

const SmallVectorImpl < MachineOperand > & Pred2 ) const {


<s> short <ISA_LIT>InstrInfo :: getNonExtOpcode ( const MachineInstr * MI ) const { short NonExtOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI -> getOpcode ( ) ) ; default : return - <NUM_LIT> ; } } return - <NUM_LIT>


<s> MachineBasicBlock * NextBB = & * ++ MBB . getIterator ( ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO .


<s> while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ; MRI . clearKillFlags ( PredReg


<s> bool invertJump = predOpcodeHasNot ( Cond ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent


<s> Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( * SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcodeHasNVJump && ( SecondLastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst -> getIterator ( ) ; if ( AllowModify ) I -> eraseFromParent ( ) ; return


<s> if ( ! OffsetOp . isImm ( ) ) return <NUM_LIT> ; Offset = OffsetOp . getImm ( ) ; } const MachineOperand & BaseOp = MI . getOperand ( BasePos ) ; if ( BaseOp . getSubReg ( ) != <NUM_LIT> ) return <NUM_LIT> ; return BaseOp .


<s> if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx = Idx ; break ; } } } } int Latency = TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! Latency


<s> bool <ISA_LIT>InstrInfo :: hasLoadFromStackSlot ( const MachineInstr & MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ; } return TargetInstrInfo :: hasLoadFromStackSlot ( MI ,


<s> const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ; } return TargetInstrInfo :: hasStoreToStackSlot ( MI , MMO , FrameIndex


<s> int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , Cond [ <NUM_LIT> ] . getMBB ( ) , VisitedBBs ) ; assert ( Loop != nullptr && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm (

Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ;


<s> bool <ISA_LIT>InstrInfo :: invertAndChangeJumpTarget ( MachineInstr & MI , MachineBasicBlock * NewTarget ) const { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * NewTarget ) ; MI . dump ( ) ; ) ; assert ( MI . isBranch ( ) ) ; unsigned NewOpcode = getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; int TargetPos = MI . getNumOperands ( )


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { if ( ! Subtarget . usePredicatedCalls ( ) ) return false ; } if ( ! Subtarget . hasV62TOps ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } if ( ! Subtarget . hasV62TOps ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT>


<s> if ( Offset % Size != <NUM_LIT> ) return false ; int Count = Offset / Size ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( Count ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : { unsigned VectorSize = TRI -> getSpillSize ( <STR_LIT> ) ; assert ( isPowerOf2_32 ( VectorSize ) ) ; if ( Offset & ( VectorSize - <NUM_LIT> ) ) return false ; return isInt < <NUM_LIT> > ( Offset >> Log2_32 ( VectorSize ) ) ; } case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) .