<s> assert ( Register :: isPhysicalRegister ( RS . Reg ) ) ; PhysR = RS . Reg ; } Register PhysS = ( RS . Sub == <NUM_LIT> ) ? PhysR : TRI -> getSubReg ( PhysR , RS . Sub ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( PhysS ) ; switch ( TRI -> getRegSizeInBits ( * RC ) ) { case <NUM_LIT> : return IfTrue ? A2_tfrt : A2_tfrf ; case <NUM_LIT> : return IfTrue ? A2_tfrpt : A2_tfrpf ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( SO . getType


<s> assert ( Register :: isVirtualRegister ( Reg ) ) ; return Sub != <NUM_LIT> ? TRI -> getSubRegIndexLaneMask ( Sub ) : MRI -> getMaxLaneMaskForVReg (


<s> assert ( Register :: isVirtualRegister ( Reg ) ) ; return Sub != <NUM_LIT> ? TRI -> getSubRegIndexLaneMask ( Sub ) : MRI ->


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HasDef ) return false ; HasDef = true ; } for ( auto & Mo : MI -> memoperands ( ) ) if ( Mo -> isVolatile ( ) || Mo -> isAtomic ( ) ) return false ; return


<s> if ( MI -> hasUnmodeledSideEffects ( ) || MI -> mayStore ( ) ) return false ; bool HasDef = false ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op .


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , nullptr ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! Register :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; if ( Op . isDef ( ) && Op . isUndef ( ) ) { assert ( RR . Sub && <STR_LIT> ) ; RR . Sub = <NUM_LIT> ; } addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD = MD ; bool CanUp = canMoveOver ( TfrI , Defs , Uses ) ; bool CanDown = canMoveOver ( * DefI , Defs , Uses ) ; if ( DefI -> mayLoad ( ) || DefI -> mayStore ( ) ) if ( ! canMoveMemTo ( * DefI , TfrI , true ) ) CanDown = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( CanUp ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( CanDown ? <STR_LIT> : <STR_LIT> ) ) ; MachineBasicBlock :: iterator PastDefIt = std :: next ( DefIt ) ; if ( CanUp ) predicateAt ( MD , * DefI , PastDefIt


<s> auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState ( ST ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( MI . getNumOperands ( ) -


<s> bool <ISA_LIT>ExpandCondsets :: split ( MachineInstr & MI , std :: set < unsigned > & UpdRegs ) { if ( TfrLimitActive ) { if ( TfrCounter >= TfrLimit ) return false ; TfrCounter ++ ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MI . getParent ( ) ) << <STR_LIT> << MI ) ; MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & MP = MI . getOperand ( <NUM_LIT> ) ; assert ( MD . isDef ( ) ) ; Register DR = MD . getReg ( ) , DSR = MD . getSubReg ( ) ; bool ReadUndef = MD . isUndef ( ) ; MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op .


<s> for ( unsigned R : RegSet ) { if ( ! Register :: isVirtualRegister ( R ) ) { assert ( Register :: isPhysicalRegister ( R ) ) ; assert ( MRI -> isReserved ( R )


<s> if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! RR . Reg . isVirtual ( ) ) return false ; if ( isRefInMap ( RR , Defs , Exec_Then ) ) return


<s> unsigned BW1 , BW2 ; if ( ! isIntReg ( R1 , BW1 ) || ! isIntReg ( R2 , BW2 ) || BW1 != BW2 ) return false ; if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << printReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; using ValueInfoMap = DenseMap < VNInfo * , VNInfo * > ; ValueInfoMap VM ; for ( LiveRange :: Segment & I : L2 ) { VNInfo * NewVN , * OldVN = I . valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I . valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I . start , I . end , NewVN ) ) ; } while ( ! L2 . empty ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; LIS -> removeInterval ( R2 . Reg ) ; updateKillFlags ( R1 . Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << L1 <<


<s> MachineOperand & S1 = MI -> getOperand ( <NUM_LIT> ) , & S2 = MI -> getOperand ( <NUM_LIT> ) ; if ( ! S1 . isReg ( ) && ! S2 . isReg ( ) ) continue ; TwoRegs . push_back ( MI ) ; } bool Changed = false ; for ( MachineInstr * CI : TwoRegs ) { RegisterRef RD = CI -> getOperand ( <NUM_LIT> ) ; RegisterRef RP = CI -> getOperand ( <NUM_LIT> ) ; MachineOperand & S1 = CI -> getOperand ( <NUM_LIT> ) , & S2 = CI -> getOperand ( <NUM_LIT> ) ; bool Done = false ; if ( S1 . isReg ( ) ) { RegisterRef RS


<s> } else { PhysR = RS . Reg ; } MCRegister PhysS = ( RS . Sub == <NUM_LIT> ) ? PhysR : TRI -> getSubReg ( PhysR , RS . Sub ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( PhysS ) ; switch ( TRI -> getRegSizeInBits ( * RC ) ) { case <NUM_LIT> : return IfTrue ? A2_tfrt : A2_tfrf ; case <NUM_LIT> : return IfTrue ? A2_tfrpt : A2_tfrpf ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( SO . getType ( ) ) { case MachineOperand :: MO_Immediate : case MachineOperand :: MO_FPImmediate : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return IfTrue ? C2_cmoveit : C2_cmoveif ; default : break ; } llvm_unreachable ( <STR_LIT> )


<s> if ( ! RR . Reg . isVirtual ( ) ) return false ; const TargetRegisterClass * RC = MRI -> getRegClass


<s> void <ISA_LIT>ExpandCondsets :: recalculateLiveInterval ( Register Reg ) { LIS -> removeInterval (


<s> MDT = & getAnalysis < MachineDominatorTree > ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; LLVM_DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( ) ) ) ; bool Changed = false ; std :: set < Register > CoalUpd , PredUpd ; SmallVector < MachineInstr * , <NUM_LIT> > Condsets ; for ( auto & B : MF ) for ( auto & I : B ) if ( isCondset ( I ) ) Condsets . push_back ( & I ) ; Changed |= coalesceSegments ( Condsets , CoalUpd ) ; std :: set < Register > KillUpd ; for ( MachineInstr * MI : Condsets ) for ( MachineOperand & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) ) if ( ! CoalUpd . count ( Op

. getReg ( ) ) ) KillUpd . insert ( Op . getReg ( ) ) ;


<s> MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState ( ST ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . removeOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineInstrBuilder ( MF , MI ) . addReg ( RT . Reg , S ,


<s> if ( ! DR . isVirtual ( ) || DR != Reg ) return { false , false } ; LaneBitmask SLM = getLaneMask ( DR , DSR ) ; LaneBitmask A = SLM & LM ; return { A . any ( ) , A == SLM } ; } ; auto Dominate = [ this ] ( SetVector < MachineBasicBlock * > & Defs , MachineBasicBlock * Dest ) -> bool { for ( MachineBasicBlock * D : Defs ) if ( D != Dest && MDT -> dominates ( D , Dest ) ) return true ; MachineBasicBlock * Entry = & Dest -> getParent ( ) -> front ( ) ; SetVector < MachineBasicBlock * > Work ( Dest -> pred_begin ( ) , Dest -> pred_end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < Work . size ( ) ; ++ i ) { MachineBasicBlock * B = Work [ i ] ; if ( Defs . count ( B ) ) continue ; if ( B == Entry ) return false ; for ( auto * P : B -> predecessors ( ) ) Work . insert ( P ) ; } return true ; } ; SetVector < MachineBasicBlock * > Defs ; SmallVector < SlotIndex , <NUM_LIT> > PredDefs ; for ( auto & Seg : Range ) { if ( ! Seg . start . isRegister ( ) ) continue ; MachineInstr * DefI = LIS -> getInstructionFromIndex ( Seg . start ) ; Defs . insert ( DefI -> getParent ( ) ) ; if ( HII -> isPredicated ( * DefI ) ) PredDefs . push_back ( Seg . start ) ; } SmallVector < SlotIndex ,


<s> } if ( Recalc ) recalculateLiveInterval ( R ) ; if ( UpdateKills ) MRI -> clearKillFlags ( R ) ; if ( UpdateDeads ) updateDeadFlags ( R ) ; if ( UpdateKills ) updateKillFlags


<s> MachineBasicBlock * PB = LIS -> getMBBFromIndex ( PE ) ; if ( PB != MB && ! LIS -> isLiveInToMBB ( LID , MB ) ) Undef = true ; } if ( ! Undef ) { makeUndead ( DefR , P -> valno -> def ) ; P -> end = MX ; } else { ImpUse . setIsUndef ( true ) ; } if ( ! MI -> readsRegister ( DefR ) ) MI -> addOperand ( ImpUse ) ; if ( N != LID . end ( ) ) makeDefined ( DefR , N -> start , true ) ; } LiveRange :: Segment NR = LiveRange :: Segment ( MX , EX , VN ) ; LID . addSegment ( NR ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NR << <STR_LIT> << LID << <STR_LIT> ) ; shrinkToUses ( DefR , LID ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; LID . verify ( ) ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . isImplicit ( ) || Op . isUndef ( ) ) continue ; unsigned UseR = Op . getReg ( ) ; LiveInterval & LIU = LIS -> getInterval ( UseR ) ; LiveInterval :: iterator P = LIU . FindSegmentContaining ( MX ) ; if ( P == LIU . end ( ) ) P = prevSegment ( LIU , MX ) ; assert ( P != LIU . end ( ) && <STR_LIT> ) ; SlotIndex EX = P -> end ; if ( EX > MX ) { Op . setIsKill ( false )


<s> if ( TheI -> hasUnmodeledSideEffects ( ) ) return false ; MachineBasicBlock :: iterator StartI = IsDown ? TheI : ToI ; MachineBasicBlock :: iterator EndI = IsDown ? ToI : TheI ; bool Ordered = TheI -> hasOrderedMemoryRef ( ) ; for ( MachineBasicBlock :: iterator I = std :: next ( StartI ) ; I != EndI ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> hasUnmodeledSideEffects ( ) ) return false ; bool L = MI -> mayLoad ( ) , S = MI -> mayStore ( ) ; if ( ! L && ! S ) continue ; if ( Ordered && MI -> hasOrderedMemoryRef ( ) ) return false ; bool Conflict = ( L && IsStore ) || S ; if ( Conflict ) return false


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; if ( isRefInMap ( RR , Defs , Exec_Then ) ) return false ; if ( Op . isDef ( ) && isRefInMap (

RR , Uses , Exec_Then ) ) return false ;


<s> if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; typedef DenseMap < VNInfo * , VNInfo * > ValueInfoMap ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS ->


<s> for ( MachineBasicBlock :: iterator J = B . begin ( ) , F = B . end ( ) ; J != F ; ++ J ) { MachineInstr * MI = & * J ; if ( ! isCondset ( MI ) ) continue ; MachineOperand & S1 = MI -> getOperand ( <NUM_LIT> ) , & S2 = MI -> getOperand ( <NUM_LIT> ) ; if ( ! S1 . isReg ( ) && ! S2 . isReg ( ) ) continue ; Condsets . push_back ( MI ) ; } } bool Changed = false ; for ( unsigned i = <NUM_LIT> , n = Condsets . size ( ) ; i < n ; ++ i ) { MachineInstr * CI = Condsets [ i ] ; RegisterRef RD = CI -> getOperand ( <NUM_LIT> ) ; RegisterRef RP = CI -> getOperand ( <NUM_LIT> ) ; MachineOperand & S1 = CI -> getOperand ( <NUM_LIT> ) , & S2 = CI -> getOperand ( <NUM_LIT> ) ; bool Done = false ; if ( S1 . isReg ( ) ) { RegisterRef RS = S1 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg , true ) ; if ( ! RDef || ! HII -> isPredicable ( * RDef ) ) Done = coalesceRegisters ( RD , RegisterRef ( S1 ) ) ; } if ( ! Done && S2


<s> RegisterRef RD = CI -> getOperand ( <NUM_LIT> ) ; RegisterRef RP = CI -> getOperand ( <NUM_LIT> ) ; MachineOperand & S1 = CI -> getOperand ( <NUM_LIT> ) , & S2 = CI -> getOperand ( <NUM_LIT> ) ; bool Done = false ; if ( S1 . isReg ( ) ) { RegisterRef RS = S1 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg , true ) ; if ( ! RDef || ! HII -> isPredicable ( * RDef ) ) Done = coalesceRegisters ( RD , RegisterRef ( S1 ) ) ; } if ( ! Done && S2 . isReg ( ) ) { RegisterRef RS = S2 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg


<s> AU . addPreserved < SlotIndexes > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved <


<s> using namespace <ISA_LIT> ; if ( SO . isReg ( ) ) { unsigned PhysR ; RegisterRef RS = SO ; if ( TargetRegisterInfo :: isVirtualRegister ( RS . Reg ) ) { const TargetRegisterClass * VC = MRI -> getRegClass ( RS . Reg ) ; assert ( VC -> begin ( ) != VC -> end ( ) && <STR_LIT> ) ; PhysR = * VC ->


<s> return Sub_Low ; case <STR_LIT> : return Sub_High ; case <STR_LIT> : return Sub_None ; } llvm_unreachable ( <STR_LIT> )


<s> bool PredValid = true ; do { -- I ; MachineInstr * MI = & * I ; if ( PredValid && HII -> isPredicated ( * MI ) ) { if ( MI -> readsRegister ( PredR ) && ( Cond != HII -> isPredicatedTrue ( * MI ) ) ) continue ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; RegisterRef RR = Op ; if ( RR . Reg ==


<s> bool PredValid = true ; do { -- I ; MachineInstr * MI = & * I ; if ( PredValid && HII -> isPredicated ( * MI ) ) { if ( MI -> readsRegister ( PredR ) && ( Cond != HII -> isPredicatedTrue ( * MI ) ) ) continue ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; RegisterRef RR = Op ; if ( RR . Reg


<s> <ISA_LIT>ExpandCondsets ( ) : MachineFunctionPass ( ID ) , HII ( <NUM_LIT> ) , TRI ( <NUM_LIT> ) , MRI ( <NUM_LIT> ) , LIS ( <NUM_LIT>

) , CoaLimitActive ( false ) , TfrLimitActive ( false ) , CoaCounter ( <NUM_LIT> ) , TfrCounter ( <NUM_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; break ; } return false


<s> unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse (

) || Op . getReg ( ) != Reg ) continue ;


<s> LiveInterval & LI = LIS -> getInterval ( Reg ) ; for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI . end ( ) ; I != E ; ++ I ) { if ( ! I -> start . isRegister ( ) || ! I -> end . isBlock ( ) ) continue ; MachineInstr * MI = LIS -> getInstructionFromIndex ( I -> start ) ; Defs . push_back ( MI ) ; } } else if ( S . isRegister ( ) ) { MachineInstr * MI = LIS -> getInstructionFromIndex ( S ) ; Defs . push_back ( MI ) ; } for ( unsigned i = <NUM_LIT> , n = Defs . size ( ) ; i < n ; ++ i ) { MachineInstr * MI = Defs [ i ] ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op .


<s> MachineInstr * MI = & * I ; RegisterSet Undefs ; for ( unsigned i = MI -> getNumOperands ( ) ; i > <NUM_LIT> ; -- i ) { MachineOperand & MO = MI -> getOperand ( i - <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . isImplicit ( ) && MO . isUndef ( ) ) { MI -> RemoveOperand ( i - <NUM_LIT> ) ; Undefs . insert ( MO . getReg (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , <NUM_LIT> ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD = MD ; bool CanUp = canMoveOver ( TfrI , Defs , Uses ) ; bool CanDown = canMoveOver ( DefI , Defs , Uses ) ; if ( DefI -> mayLoad ( ) || DefI -> mayStore ( ) ) if ( ! canMoveMemTo ( DefI , TfrI , true ) ) CanDown = false ; DEBUG ( dbgs ( ) << <STR_LIT> << ( CanUp ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( CanDown ? <STR_LIT> : <STR_LIT> ) ) ; MachineBasicBlock :: iterator PastDefIt = std :: next ( DefIt ) ; if ( CanUp ) predicateAt ( RD , DefI


<s> for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , <NUM_LIT> ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD =


<s> for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI .


<s> void <ISA_LIT>ExpandCondsets :: removeImplicitUses ( MachineBasicBlock & B ) { for ( MachineInstr & MI : B ) if ( HII -> isPredicated ( MI


<s> unsigned DefR = Op . getReg ( ) ; LiveInterval & LID = LIS -> getInterval ( DefR ) ; LiveInterval :: iterator LT = LID . FindSegmentContaining ( MX ) ; assert ( LT != LID . end ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MX << <STR_LIT> << PrintReg ( DefR , TRI ) << <STR_LIT> << LID << <STR_LIT> ) ; if ( LT -> start != MX ) continue ; VNInfo * MVN = LT -> valno ; if ( LT != LID . begin ( ) ) { LiveInterval :: iterator P = std :: prev ( LT ) ; SlotIndex PE = P -> end . isBlock ( ) ? P -> end . getPrevIndex ( ) : P -> end ; MachineBasicBlock * MB = MI -> getParent ( ) ; MachineBasicBlock * PB = LIS -> getMBBFromIndex ( PE ) ; if ( PB != MB && ! LIS -> isLiveInToMBB ( LID , MB ) ) { makeDefined ( DefR , LT -> end , false ) ; LID . removeSegment ( * LT ) ; } else { P -> end = LT -> start ; makeUndead ( DefR , P -> valno -> def ) ; LID . MergeValueNumberInto ( MVN , P -> valno ) ; } } else { LiveInterval :: iterator N = std :: next ( LT ) ; LiveInterval :: iterator RmB = LT , RmE = N ; while ( N != LID . end ( ) ) { LiveInterval :: iterator Next = std :: next ( N ) ; if ( N -> start . isRegister ( ) ) { makeDefined ( DefR , N -> start , false ) ; break ; } if ( N -> end . isRegister ( ) ) { makeDefined ( DefR , N -> end , false ) ; RmE = Next ; break ; } RmE = Next ; N = Next ; } LID . segments . erase ( RmB , RmE ) ; } bool VNUsed = false ; for ( LiveInterval :: iterator I = LID . begin ( ) , E = LID . end ( ) ; I != E ; ++ I ) { if ( I -> valno != MVN ) continue ; VNUsed = true ; break ; } if ( ! VNUsed ) MVN -> markUnused ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ! LID . empty ( ) ) { DEBUG ( dbgs ( ) << LID << <STR_LIT> ) ; LID . verify ( ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; LIS -> removeInterval ( DefR ) ; } } SmallVector < unsigned ,


<s> RmE = Next ; break ; } RmE = Next ; N = Next ; } LID . segments . erase ( RmB , RmE ) ; } bool VNUsed = false ; for ( LiveInterval :: iterator I = LID . begin ( ) , E = LID . end ( ) ; I != E ; ++ I ) { if ( I -> valno != MVN ) continue ; VNUsed = true ; break ; } if ( ! VNUsed ) MVN -> markUnused ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ! LID . empty ( ) ) { DEBUG ( dbgs ( ) << LID << <STR_LIT> ) ; LID . verify ( ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; LIS -> removeInterval ( DefR ) ; } } SmallVector < unsigned , <NUM_LIT> > Uses ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; Uses . push_back ( R ) ; } LIS -> RemoveMachineInstrFromMaps ( * MI ) ; MI -> eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> , n = Uses . size ( ) ; i < n ; ++ i ) { LiveInterval & LI = LIS -> getInterval (


<s> } LiveInterval :: iterator End = LI . end ( ) ; SlotIndex S = LIS -> getInstructionIndex ( * MI ) . getRegSlot ( ) ; LiveInterval :: iterator T = LI . FindSegmentContaining ( S ) ; assert ( T != End ) ; LiveInterval :: iterator N = std :: next ( T ) ; if ( N != End ) T -> end = N ->


<s> MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next ( I ) ; if ( isCondset ( I ) )


<s> bool Changed = false ; MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next (


<s> if ( ! EX . isBlock ( ) ) return ; VNInfo * NewVN = <NUM_LIT> ; for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI . end ( ) ; I != E ; ++ I ) { if ( ! I -> start . isBlock ( )


<s> void <ISA_LIT>ExpandCondsets :: updateKillFlags ( unsigned Reg , LiveInterval & LI ) { MRI -> clearKillFlags ( Reg ) ; for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI . end ( ) ; I != E ; ++ I ) { SlotIndex EX = I -> end ; if ( ! EX . isRegister ( ) ) continue ; MachineInstr * MI = LIS -> getInstructionFromIndex ( EX ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . getReg ( ) != Reg ) continue ; Op . setIsKill ( true


<s> Register DR = MD . getReg ( ) , DSR = MD . getSubReg ( ) ; bool ReadUndef = MD . isUndef ( ) ; MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState


<s> unsigned DefR = Defs [ i ] . Reg ; LiveInterval & LID = LIS -> getInterval ( DefR ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DefR , TRI ) << <STR_LIT> << LID << <STR_LIT> ) ; LiveInterval :: iterator LT = LID . FindSegmentContaining ( MX ) ; if ( LT != LID . end ( ) ) terminateSegment ( LT , MX , LID ) ; DEBUG ( dbgs ( ) << <STR_LIT> << LID << <STR_LIT> ) ; LiveInterval :: iterator P = prevSegment ( LID , MX ) , N = nextSegment ( LID , MX ) ; SlotIndex EX ; VNInfo * VN = LID . getNextValue ( MX , LIS -> getVNInfoAllocator ( ) ) ; if ( N == LID . end ( ) ) { EX = LIS -> getMBBEndIdx ( MB ) ; } else { EX = N -> start . isBlock ( ) ? N -> start . getPrevIndex ( ) : N -> start ; } if ( Predicated ) { MachineOperand ImpUse = MachineOperand :: CreateReg ( DefR , false , true ) ; ImpUse . setSubReg ( Defs [ i ] . Sub ) ; bool Undef = false ; if ( P == LID . end ( ) ) Undef = true ; else { SlotIndex PE = P -> end . isBlock ( ) ? P -> end . getPrevIndex ( ) : P -> end ; MachineBasicBlock * PB = LIS -> getMBBFromIndex ( PE ) ; if ( PB != MB && ! LIS -> isLiveInToMBB ( LID , MB ) ) Undef = true ; } if ( ! Undef ) { makeUndead ( DefR , P -> valno -> def ) ; P -> end = MX ; } else { ImpUse . setIsUndef ( true ) ; } if ( ! MI -> readsRegister ( DefR ) ) MI -> addOperand ( ImpUse ) ; if ( N != LID . end ( ) ) makeDefined ( DefR , N -> start , true ) ; } LiveRange :: Segment NR = LiveRange :: Segment ( MX , EX , VN ) ; LID . addSegment ( NR ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NR << <STR_LIT> << LID << <STR_LIT> ) ; shrinkToUses ( DefR , LID ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI


<s> if ( ! isCondset ( MI ) ) continue ; MachineOperand & S1 = MI -> getOperand ( <NUM_LIT> ) , & S2 = MI -> getOperand ( <NUM_LIT> ) ; if ( ! S1 . isReg ( ) && ! S2 . isReg ( ) ) continue ; Condsets . push_back ( MI ) ; } } bool Changed = false ; for ( unsigned i = <NUM_LIT> , n = Condsets . size ( ) ; i < n ; ++ i ) { MachineInstr * CI = Condsets [ i ] ; RegisterRef RD = CI -> getOperand ( <NUM_LIT> ) ; RegisterRef RP = CI -> getOperand ( <NUM_LIT> ) ; MachineOperand & S1 = CI -> getOperand ( <NUM_LIT> ) , & S2 = CI -> getOperand ( <NUM_LIT> ) ; bool Done = false ; if ( S1 . isReg ( ) ) { RegisterRef RS = S1 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg , true ) ; if ( ! RDef || ! HII -> isPredicable ( RDef ) ) Done

= coalesceRegisters ( RD , RegisterRef ( S1 ) ) ;


<s> if ( MI -> readsRegister ( PredR ) && ( Cond != HII -> isPredicatedTrue ( MI ) ) ) continue ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; RegisterRef RR = Op ; if ( RR . Reg == PredR ) { PredValid = false ; continue ; } if ( RR . Reg != RD . Reg ) continue ; if ( RR . Sub == RD . Sub ) return MI ; if ( RR . Sub == <NUM_LIT> || RD . Sub == <NUM_LIT> ) return <NUM_LIT> ; } } while ( I != S


<s> DEBUG ( dbgs ( ) << <STR_LIT> << ( Cond ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * TfrI ) ; MachineOperand & MD = TfrI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MP = TfrI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MS = TfrI -> getOperand ( <NUM_LIT> ) ; if ( ! MS . isKill ( ) ) return false ; RegisterRef RT ( MS ) ; unsigned PredR = MP . getReg ( ) ; MachineInstr * DefI = getReachingDefForPred ( RT , TfrI , PredR , Cond ) ; if ( ! DefI || ! isPredicable ( DefI ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , <NUM_LIT> ) ) continue ; PredValid =


<s> MachineInstr * DefI = getReachingDefForPred ( RT , TfrI , PredR , Cond ) ; if ( ! DefI || ! isPredicable ( DefI ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , <NUM_LIT> ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD = MD ; bool CanUp = canMoveOver ( TfrI , Defs , Uses ) ; bool CanDown = canMoveOver ( DefI , Defs , Uses ) ; if ( DefI -> mayLoad ( ) || DefI -> mayStore ( ) ) if ( ! canMoveMemTo ( DefI , TfrI , true ) ) CanDown = false ; DEBUG ( dbgs ( ) << <STR_LIT> << ( CanUp ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( CanDown ? <STR_LIT> :


<s> void <ISA_LIT>ExpandCondsets :: removeImplicitUses ( MachineBasicBlock & B ) { for ( MachineBasicBlock :: iterator I = B . begin ( ) , E = B . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = &


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . getReg ( ) != Reg ) continue ; Op . setIsDead ( false ) ; } LiveInterval :: iterator End = LI . end ( ) ; SlotIndex S = LIS -> getInstructionIndex ( MI ) . getRegSlot


<s> if ( CoaLimitActive ) { if ( CoaCounter >= CoaLimit ) return false ; CoaCounter ++ ; } unsigned BW1 , BW2 ; if ( ! isIntReg ( R1 , BW1 ) || ! isIntReg ( R2 , BW2 ) || BW1 != BW2 ) return false ; if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; using ValueInfoMap = DenseMap < VNInfo * , VNInfo *


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << ( Cond ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * TfrI ) ; MachineOperand & MD = TfrI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MP = TfrI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MS = TfrI -> getOperand ( <NUM_LIT> ) ; if ( ! MS . isKill ( ) ) return false ; if ( MD . getSubReg ( ) ) return false ; RegisterRef RT ( MS ) ; unsigned PredR = MP . getReg ( ) ; MachineInstr * DefI = getReachingDefForPred ( RT , TfrI , PredR , Cond ) ; if ( ! DefI || ! isPredicable ( DefI ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , <NUM_LIT> ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg


<s> MachineOperand & MO = MI -> getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . addOperand ( MO ) ; Ox ++ ; } MachineFunction & MF = * B . getParent ( ) ; MachineInstr :: mmo_iterator I = MI -> memoperands_begin ( ) ; unsigned NR = std :: distance ( I , MI -> memoperands_end ( ) ) ; MachineInstr :: mmo_iterator MemRefs = MF . allocateMemRefsArray ( NR ) ; for ( unsigned i = <NUM_LIT> ; i < NR ; ++ i ) MemRefs [ i ] = * I ++ ; MB . setMemRefs ( MemRefs ,


<s> MRI = & MF . getRegInfo ( ) ; DEBUG ( MF . print ( dbgs ( ) << <STR_LIT> , LIS -> getSlotIndexes ( ) ) ) ; bool Changed = false ; Changed |= coalesceSegments ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { Changed |= splitInBlock ( * I ) ; Changed |= predicateInBlock (


<s> if ( ! DefI || ! isPredicable ( DefI ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , nullptr ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! Register :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; if ( Op . isDef ( ) && Op . isUndef ( ) ) { assert ( RR . Sub && <STR_LIT> ) ; RR . Sub = <NUM_LIT> ; } addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD = MD ; bool CanUp = canMoveOver ( TfrI , Defs , Uses ) ; bool CanDown = canMoveOver ( * DefI


<s> if ( ! isIntReg ( R1 , BW1 ) || ! isIntReg ( R2 , BW2 ) || BW1 != BW2 ) return false ; if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; typedef DenseMap < VNInfo * , VNInfo * > ValueInfoMap ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I -> start , I -> end , NewVN ) ) ; } while ( L2 . begin ( ) != L2 . end ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; updateKillFlags ( R1 . Reg ) ; DEBUG ( dbgs ( ) << <STR_LIT> << L1 << <STR_LIT> ) ; L1 . verify (


<s> } } bool Changed = false ; for ( unsigned i = <NUM_LIT> , n = Condsets . size ( ) ; i < n ; ++ i ) { MachineInstr * CI = Condsets [ i ] ; RegisterRef RD = CI -> getOperand ( <NUM_LIT> ) ; RegisterRef RP = CI -> getOperand ( <NUM_LIT> ) ; MachineOperand & S1 = CI -> getOperand ( <NUM_LIT> ) , & S2 = CI -> getOperand ( <NUM_LIT> ) ; bool Done = false ; if ( S1 . isReg ( ) ) { RegisterRef RS = S1 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg , true ) ; if ( ! RDef || ! HII -> isPredicable ( * RDef ) ) Done = coalesceRegisters ( RD , RegisterRef ( S1 ) ) ; } if ( ! Done && S2 . isReg ( ) ) { RegisterRef RS = S2


<s> MachineInstr * <ISA_LIT>ExpandCondsets :: genCondTfrFor ( MachineOperand & SrcOp , MachineBasicBlock :: iterator At , unsigned DstR , unsigned DstSR , const MachineOperand & PredOp , bool PredSense , bool ReadUndef , bool ImpUse ) { MachineInstr * MI = SrcOp . getParent ( ) ; MachineBasicBlock & B = * At -> getParent ( ) ; const DebugLoc & DL = MI ->


<s> const char * getPassName ( ) const override { return <STR_LIT>


<s> } ; Range . segments . erase ( std :: remove_if ( Range . begin ( ) , Range . end ( ) , StartImpDef )


<s> unsigned NewSR = <NUM_LIT> ; MachineBasicBlock :: iterator DefAt = At ; bool SameReg = ( MS1 . isReg ( ) && DR == MS1 . getReg ( ) ) || ( MS2 . isReg ( ) && DR == MS2 . getReg ( ) ) ; if ( SameReg ) { NewSR = ( DSR == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ( MS1 . isReg ( ) && NewSR == MS1 . getSubReg ( ) ) || ( MS2 . isReg ( ) && NewSR == MS2 . getSubReg ( ) ) ) ++ DefAt ; } MachineBasicBlock & B = * At -> getParent ( ) ; DebugLoc DL = At -> getDebugLoc ( ) ; auto ImpD = BuildMI ( B , DefAt , DL , HII -> get ( TargetOpcode :: IMPLICIT_DEF ) ) . addReg ( DR , RegState :: Define , NewSR ) ; LIS -> InsertMachineInstrInMaps ( * ImpD ) ; LocalImpDefs . insert ( & * ImpD ) ; } MachineInstr * TfrT = genCondTfrFor ( MI . getOperand ( <NUM_LIT> ) , At , DR , DSR , MP , true , ReadUndef , false ) ; MachineInstr * TfrF = genCondTfrFor ( MI . getOperand ( <NUM_LIT> ) , At , DR , DSR , MP , false , ReadUndef ,


<s> bool <ISA_LIT>ExpandCondsets :: splitInBlock ( MachineBasicBlock & B , std :: set < unsigned > & UpdRegs ) { bool Changed = false ; MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next ( I ) ; if ( isCondset ( * I ) ) Changed |= split ( * I , UpdRegs ) ; } return Changed


<s> for ( auto & Seg : Range ) { if ( ! Seg . start . isRegister ( ) ) continue ; MachineInstr * DefI = LIS -> getInstructionFromIndex ( Seg . start ) ; if ( LocalImpDefs . count ( DefI ) ) continue ; for ( auto & Op : DefI -> operands ( ) ) { if ( Seg . start . isDead ( ) || ! IsRegDef ( Op ) ) continue ; DefRegs . insert ( Op ) ; Op . setIsDead ( false ) ; } } removeImpDefSegments ( Range ) ; for ( auto & Seg : Range ) { if ( ! Seg . start . isRegister ( ) || ! Range . liveAt ( Seg . start . getPrevSlot ( ) ) ) continue ; MachineInstr * DefI = LIS -> getInstructionFromIndex ( Seg . start ) ; if ( ! HII -> isPredicated ( * DefI ) ) continue ; MachineFunction & MF = * DefI -> getParent ( ) -> getParent ( ) ; std :: set < RegisterRef > ImpUses ; for ( auto & Op : DefI -> operands ( ) ) if ( Op . isReg ( ) && Op . isDef ( ) && DefRegs . count ( Op ) ) ImpUses . insert ( Op ) ; for ( RegisterRef R : ImpUses ) MachineInstrBuilder ( MF , DefI ) . addReg (

R . Reg , RegState :: Implicit , R . Sub ) ;


<s> if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; typedef DenseMap < VNInfo * , VNInfo * > ValueInfoMap ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I -> start , I -> end , NewVN ) ) ; } while ( L2 . begin ( ) != L2 . end ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; updateKillFlags ( R1 . Reg ) ; DEBUG ( dbgs ( ) << <STR_LIT> << L1


<s> if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; typedef DenseMap < VNInfo * , VNInfo * > ValueInfoMap ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I -> start , I -> end , NewVN ) ) ; } while ( L2 . begin ( ) != L2 . end ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; updateKillFlags ( R1 . Reg ) ; DEBUG ( dbgs ( ) << <STR_LIT> << L1 << <STR_LIT> ) ; L1 . verify ( ) ; return


<s> void <ISA_LIT>ExpandCondsets :: removeImpDefSegments ( LiveRange & Range ) { auto StartImpDef = [ this ] ( LiveRange :: Segment & S )


<s> LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << printReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; using ValueInfoMap = DenseMap < VNInfo * , VNInfo * > ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I -> start , I -> end , NewVN ) ) ; } while ( ! L2 . empty ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; LIS -> removeInterval ( R2 . Reg ) ; updateKillFlags ( R1 . Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << L1 << <STR_LIT> ) ; L1 . verify ( ) ; return true


<s> if ( CoaCounter >= CoaLimit ) return false ; CoaCounter ++ ; } unsigned BW1 , BW2 ; if ( ! isIntReg ( R1 , BW1 ) || ! isIntReg ( R2 , BW2 ) || BW1 != BW2 ) return false ; if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 <<

<STR_LIT> << printReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ;


<s> break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD = MD ; bool CanUp = canMoveOver ( TfrI , Defs , Uses ) ; bool CanDown = canMoveOver ( DefI , Defs , Uses ) ; if ( DefI -> mayLoad ( ) || DefI -> mayStore ( ) ) if ( ! canMoveMemTo ( DefI , TfrI , true ) ) CanDown = false ; DEBUG ( dbgs ( ) << <STR_LIT> << ( CanUp ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( CanDown ? <STR_LIT> : <STR_LIT> ) ) ; MachineBasicBlock :: iterator PastDefIt = std :: next ( DefIt ) ; if ( CanUp ) predicateAt ( MD , DefI , PastDefIt , MP , Cond , UpdRegs ) ; else if ( CanDown ) predicateAt ( MD , DefI , TfrIt , MP , Cond


<s> unsigned Opc = MI -> getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI -> getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI -> getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ; while ( Ox < NP ) { MachineOperand & MO = MI -> getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . addOperand ( MO ) ; Ox ++ ; } MachineFunction & MF = * B . getParent ( ) ; MachineInstr :: mmo_iterator I = MI -> memoperands_begin ( ) ; unsigned NR = std :: distance ( I , MI -> memoperands_end ( ) ) ; MachineInstr :: mmo_iterator MemRefs = MF . allocateMemRefsArray ( NR ) ; for ( unsigned i = <NUM_LIT> ; i < NR ; ++ i ) MemRefs [ i ] = * I ++ ; MB . setMemRefs ( MemRefs , MemRefs + NR ) ; MachineInstr * NewI = MB ; NewI -> clearKillInfo ( ) ; LIS -> InsertMachineInstrInMaps ( * NewI ) ; for ( auto & Op : NewI -> operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg


<s> MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B .


<s> MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next


<s> for ( MachineBasicBlock :: iterator I = std :: next ( StartI ) ; I != EndI ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> hasUnmodeledSideEffects ( ) ) return false ; bool L = MI -> mayLoad ( ) , S = MI -> mayStore ( ) ; if ( ! L &&


<s> bool IsLoad = TheI -> mayLoad ( ) , IsStore = TheI -> mayStore ( ) ; if ( ! IsLoad && ! IsStore ) return true ; if ( HII -> areMemAccessesTriviallyDisjoint ( * TheI , * ToI ) ) return true ; if ( TheI -> hasUnmodeledSideEffects ( ) ) return false ; MachineBasicBlock :: iterator StartI = IsDown ? TheI : ToI ; MachineBasicBlock :: iterator EndI = IsDown ? ToI : TheI ; bool Ordered = TheI -> hasOrderedMemoryRef ( ) ; for ( MachineBasicBlock :: iterator I = std :: next ( StartI )


<s> unsigned Mask = getMaskForSub ( RR . Sub ) | Exec ; ReferenceMap :: iterator F = Map .


<s> LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << printReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; using ValueInfoMap = DenseMap < VNInfo * , VNInfo * > ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN


<s> AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree >


<s> AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes >


<s> return IfTrue ? A2_tfrt : A2_tfrf ; case <NUM_LIT> : return IfTrue ? A2_tfrpt : A2_tfrpf ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( SO . getType ( ) ) { case MachineOperand :: MO_Immediate : case MachineOperand :: MO_FPImmediate : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_TargetIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_BlockAddress : return IfTrue ? C2_cmoveit


<s> LaneBitmask <ISA_LIT>ExpandCondsets :: getLaneMask ( unsigned Reg , unsigned Sub ) { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; return Sub != <NUM_LIT> ? TRI -> getSubRegIndexLaneMask ( Sub ) : MRI ->


<s> switch ( Sub ) { case <STR_LIT> : case <STR_LIT> : return Sub_Low ; case <STR_LIT>


<s> StringRef getPassName ( ) const override { return


<s> if ( I == S ) return nullptr ; bool PredValid = true ; do { -- I ; MachineInstr * MI = & * I ; if ( PredValid && HII -> isPredicated ( * MI ) ) { if ( MI -> readsRegister ( PredR ) && ( Cond != HII -> isPredicatedTrue ( * MI ) ) ) continue ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; RegisterRef RR = Op ; if ( RR . Reg == PredR ) { PredValid = false ; continue ; } if ( RR . Reg != RD . Reg ) continue ; if ( RR . Sub == RD . Sub ) return MI ; if ( RR . Sub == <NUM_LIT> || RD . Sub


<s> <ISA_LIT>ExpandCondsets ( ) : MachineFunctionPass ( ID ) { if ( OptCoaLimit . getPosition ( ) ) CoaLimitActive = true , CoaLimit = OptCoaLimit ; if ( OptTfrLimit . getPosition ( ) ) TfrLimitActive


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI . end ( ) ; I != E ; ++ I ) { LiveRange :: Segment & LR = * I ; if ( ! LR . start . isRegister ( ) ) return false ; if ( ! LR . end . isRegister ( ) && ! LR . end . isDead ( ) ) return false ; } return


<s> if ( RC == & <STR_LIT> ) { BW = <NUM_LIT> ; return true ; } if ( RC == & <STR_LIT> ) { BW = ( RR . Sub != <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HasDef ) return false ; HasDef = true ; } for ( auto & Mo : MI -> memoperands ( ) ) if ( Mo -> isVolatile ( ) ) return false ; return


<s> bool <ISA_LIT>ExpandCondsets :: isRefInMap ( RegisterRef RR , ReferenceMap & Map , unsigned Exec ) { ReferenceMap :: iterator F = Map . find ( RR . Reg ) ; if ( F == Map . end ( )


<s> Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . add ( MO ) ; Ox ++ ; } MachineFunction & MF = * B . getParent ( ) ; MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) ; unsigned NR = std :: distance ( I , MI . memoperands_end ( ) ) ; MachineInstr :: mmo_iterator MemRefs = MF . allocateMemRefsArray ( NR ) ; for ( unsigned i = <NUM_LIT> ; i < NR ; ++ i ) MemRefs [


<s> for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next ( I ) ; unsigned Opc = I -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { bool Done = predicate ( * I , ( Opc == <STR_LIT> ) , UpdRegs ) ; if ( ! Done ) { if ( RegisterRef ( I -> getOperand ( <NUM_LIT> ) ) == RegisterRef ( I -> getOperand ( <NUM_LIT> ) ) ) { for ( auto & Op : I -> operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; removeInstr ( * I ) ; } } Changed |= Done ; } } return


<s> bool <ISA_LIT>ExpandCondsets :: predicateInBlock ( MachineBasicBlock & B , std :: set < unsigned > & UpdRegs ) { bool Changed = false ; MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next


<s> void <ISA_LIT>ExpandCondsets :: recalculateLiveInterval ( unsigned


<s> LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent


<s> void <ISA_LIT>ExpandCondsets :: renameInRange ( RegisterRef RO , RegisterRef RN , unsigned PredR , bool Cond , MachineBasicBlock :: iterator First , MachineBasicBlock :: iterator Last ) { MachineBasicBlock :: iterator End = std :: next ( Last ) ; for ( MachineBasicBlock :: iterator I = First ; I != End ; ++ I ) { MachineInstr * MI = & * I ; if ( ! HII -> isPredicated ( * MI ) ) continue ; if ( ! MI -> readsRegister ( PredR ) || ( Cond != HII -> isPredicatedTrue ( * MI ) ) ) continue ; for ( auto & Op : MI


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; MRI = & MF . getRegInfo ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( ) ) ) ; bool Changed = false ; std :: set < unsigned > CoalUpd , PredUpd ; SmallVector < MachineInstr * , <NUM_LIT> > Condsets ; for ( auto & B : MF ) for ( auto & I : B ) if ( isCondset ( I ) ) Condsets . push_back ( & I ) ; Changed |= coalesceSegments ( Condsets , CoalUpd ) ; std :: set < unsigned > KillUpd ; for ( MachineInstr * MI : Condsets ) for ( MachineOperand & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) ) if ( ! CoalUpd . count ( Op . getReg ( ) ) ) KillUpd . insert ( Op . getReg ( ) ) ; updateLiveness ( KillUpd , false , true , false ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( ) ) ) ; for ( MachineInstr * MI : Condsets ) Changed |= split ( * MI , PredUpd ) ; Condsets . clear ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( ) ) ) ; for ( auto & B : MF ) Changed |= predicateInBlock ( B , PredUpd ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( ) ) ) ; PredUpd . insert ( CoalUpd . begin ( ) , CoalUpd . end ( )


<s> Changed |= coalesceSegments ( Condsets , CoalUpd ) ; std :: set < unsigned > KillUpd ; for ( MachineInstr * MI : Condsets ) for ( MachineOperand & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) ) if ( ! CoalUpd . count ( Op . getReg ( ) ) ) KillUpd . insert ( Op . getReg ( ) ) ; updateLiveness ( KillUpd , false , true , false ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) . getParent ( ) ) ) ; for ( MachineInstr * MI : Condsets ) Changed |= split ( * MI , PredUpd ) ; Condsets . clear ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF .


<s> MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState ( ST ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineInstrBuilder ( MF , MI ) . addReg ( RT . Reg , S , RT . Sub ) ; return true ; } } MachineInstr * TfrT = genCondTfrFor ( ST , At , DR , DSR , MP , true , ReadUndef , false ) ; MachineInstr * TfrF = genCondTfrFor ( SF , At , DR , DSR , MP , false , ReadUndef , true ) ; LIS -> InsertMachineInstrInMaps ( * TfrT ) ; LIS -> InsertMachineInstrInMaps ( * TfrF ) ; updateRegs ( MI ) ; removeInstr ( MI ) ; return true


<s> LiveInterval & LI = LIS -> getInterval ( Reg ) ; if ( LI . hasSubRanges ( ) ) { for ( LiveInterval :: SubRange & S : LI . subranges ( ) ) { updateDeadsInRange ( Reg , S . LaneMask


<s> if ( LI . hasSubRanges ( ) ) { for ( LiveInterval :: SubRange & S : LI . subranges ( ) ) { updateDeadsInRange ( Reg , S . LaneMask , S ) ; LIS -> shrinkToUses ( S , Reg ) ; } LI . clear ( ) ; LIS -> constructMainRangeFromSubranges ( LI ) ; }


<s> if ( UpdateKills ) MRI -> clearKillFlags ( R ) ; if ( UpdateDeads ) updateDeadFlags ( R ) ; if ( UpdateKills ) updateKillFlags


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPredSpillCode ( <ISA_LIT>TargetMachine


<s> const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>ExpandPredSpillCode


<s> BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( FP ) . addImm ( Offset ) . addReg ( HEXAGON_RESERVED_REG_2 ) ; } MII = MBB -> erase ( MI ) ; -- MII ; } else if ( Opc == <STR_LIT> ) { int DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( DstReg ) && <STR_LIT> ) ; unsigned FP = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( FP == QTM . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getFrameRegister ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; int Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! TII -> isValidOffset ( <STR_LIT> , Offset ) ) { if ( ! TII -> isValidOffset ( <STR_LIT> , Offset ) ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , HEXAGON_RESERVED_REG_1 ) . addImm ( Offset ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , HEXAGON_RESERVED_REG_1 ) . addReg ( FP ) . addReg ( HEXAGON_RESERVED_REG_1 ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , HEXAGON_RESERVED_REG_2 ) . addReg ( HEXAGON_RESERVED_REG_1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( HEXAGON_RESERVED_REG_2 ) ; } else { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , HEXAGON_RESERVED_REG_1 ) . addReg ( FP ) . addImm ( Offset ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , HEXAGON_RESERVED_REG_2 ) . addReg ( HEXAGON_RESERVED_REG_1


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPredSpillCode (


create<ISA_LIT>ExpandPredSpillCode ( ) {


<s> PassRegistry & Registry = * PassRegistry :: getPassRegistry (


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPredSpillCode ( const <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>ExpandPredSpillCode (


<s> const char * getPassName ( ) const override { return


<s> <ISA_LIT>ExpandPredSpillCode ( const <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) , QTM ( TM ) , QST ( * TM .


<s> const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>ExpandPredSpillCode :: ID , nullptr , false , false ) ; Registry . registerPass ( * PI


<s> static void initializePassOnce ( PassRegistry & Registry ) { const char * Name =


<s> DebugLoc DL = MII -> getDebugLoc ( ) ; unsigned Scratch = RS . scavengeRegister ( & <STR_LIT> , MII , <NUM_LIT> ) ; if ( MII -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( MII -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addImm ( MII -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Scratch ) ; } BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addMBB ( MII -> getOperand (


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock * MBB = MII -> getParent ( ) ; DebugLoc DL = MII -> getDebugLoc ( ) ; unsigned Scratch = RS . scavengeRegister ( & <STR_LIT> , MII , <NUM_LIT> ) ; if ( MII -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( MII -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addImm

( MII -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode (


<s> unsigned InstOffset = <NUM_LIT> ; DenseMap < const MachineBasicBlock * , unsigned > BlockToInstOffset ; const <ISA_LIT>InstrInfo * HII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; for ( const MachineBasicBlock & MBB : MF ) { if ( MBB . getLogAlignment ( ) ) { int ByteAlign = ( <NUM_LIT> << MBB . getLogAlignment ( ) ) - <NUM_LIT> ; InstOffset = ( InstOffset + ByteAlign ) & ~ ( ByteAlign ) ; } BlockToInstOffset [ & MBB ] = InstOffset ; for ( const MachineInstr & MI : MBB ) InstOffset += HII -> getSize ( MI ) ; } bool Changed = false


<s> unsigned InstOffset = <NUM_LIT> ; DenseMap < const MachineBasicBlock * , unsigned > BlockToInstOffset ; const <ISA_LIT>InstrInfo * HII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; for ( const MachineBasicBlock & MBB : MF ) { if ( MBB . getLogAlignment ( ) ) { int ByteAlign = ( <NUM_LIT> << MBB . getLogAlignment ( ) ) - <NUM_LIT> ; InstOffset = ( InstOffset + ByteAlign ) & ~ ( ByteAlign ) ; } BlockToInstOffset [ & MBB ] =


<s> if ( skipFunction ( MF . getFunction ( ) ) )


<s> bool <ISA_LIT>FixupHwLoops :: runOnMachineFunction (


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock * MBB = MII -> getParent ( ) ; DebugLoc DL = MII -> getDebugLoc ( ) ; MachineInstrBuilder MIB ; unsigned newOp ; switch ( MII -> getOpcode ( ) ) { case <STR_LIT> : newOp = <STR_LIT> ; break ; case <STR_LIT> : newOp = <STR_LIT> ; break ; case <STR_LIT> : newOp = <STR_LIT> ; break ; case <STR_LIT> : newOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } MIB = BuildMI ( * MBB , MII , DL , TII -> get (


<s> InstOffset = alignTo ( InstOffset , MBB . getAlignment ( ) ) ; } BlockToInstOffset [ & MBB ] = InstOffset ; for ( const MachineInstr & MI : MBB ) InstOffset += HII -> getSize ( MI ) ; } bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { InstOffset = BlockToInstOffset [ & MBB ] ; MachineBasicBlock :: iterator MII = MBB . begin ( ) ; MachineBasicBlock :: iterator MIE = MBB . end ( ) ; while ( MII != MIE ) { unsigned InstSize = HII -> getSize ( * MII ) ; if ( MII -> isMetaInstruction ( )


<s> for ( const MachineInstr & MI : MBB ) InstOffset += HII -> getSize ( MI ) ; } bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { InstOffset = BlockToInstOffset [ & MBB ] ; MachineBasicBlock :: iterator MII = MBB . begin ( ) ; MachineBasicBlock :: iterator MIE = MBB . end ( ) ; while ( MII != MIE ) { unsigned InstSize = HII -> getSize ( * MII ) ; if ( MII -> isMetaInstruction ( ) ) { ++ MII ; continue ; } if ( isHardwareLoop ( * MII ) ) { assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; MachineBasicBlock * TargetBB = MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned Diff = AbsoluteDifference ( InstOffset , BlockToInstOffset [ TargetBB ] ) ; if ( Diff > MaxLoopRange ) { useExtLoopInstr ( MF ,


<s> unsigned InstSize = HII -> getSize ( * MII ) ; if ( MII -> isMetaInstruction ( ) ) { ++ MII ; continue ; } if ( isHardwareLoop ( * MII ) ) { assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; MachineBasicBlock * TargetBB = MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned Diff = AbsoluteDifference ( InstOffset , BlockToInstOffset [ TargetBB ] ) ; if ( Diff > MaxLoopRange ) { useExtLoopInstr ( MF , MII ) ; MII = MBB . erase ( MII ) ; Changed = true ; } else { ++ MII


<s> static bool isHardwareLoop ( const MachineInstr & MI ) { return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) ==

<STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; return fixupLoopInstrs (


<s> static bool isHardwareLoop ( const MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI ->


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU )


<s> const char * getPassName ( ) const { return


<s> bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { InstOffset = BlockToInstOffset [ & MBB ] ; MachineBasicBlock :: iterator MII = MBB . begin ( ) ; MachineBasicBlock :: iterator MIE = MBB . end ( ) ; while ( MII != MIE ) { InstOffset += HII -> getSize ( & * MII ) ; if ( MII -> isDebugValue ( ) ) { ++ MII ; continue ; } if ( isHardwareLoop ( MII ) ) { assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; int diff = InstOffset - BlockToInstOffset [ MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ] ; if ( ( unsigned ) abs ( diff ) > MaxLoopRange ) { useExtLoopInstr ( MF , MII ) ; MII = MBB . erase ( MII ) ; Changed = true ; } else


<s> if ( MII -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( MII -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addImm ( MII -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * MBB , MII , DL , TII -> get

( <STR_LIT> ) , <STR_LIT> ) . addReg ( Scratch ) ;


<s> } else { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addImm ( MII -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Scratch ) ; } BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addMBB ( MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg


<s> RS . forward ( MII ) ; assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; int Sub = InstOffset - BlockToInstOffset [ MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ] ; unsigned Dist = Sub > <NUM_LIT> ? Sub : - Sub ; if ( Dist > MAX_LOOP_DISTANCE ) { convertLoopInstr ( MF , MII , RS ) ; MII = MBB -> erase ( MII ) ; Changed = true ; }


<s> <ISA_LIT>FixupHwLoops ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>FixupHwLoopsPass ( * PassRegistry ::


<s> static bool isHardwareLoop ( const MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode


<s> bool <ISA_LIT>FixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = fixupLoopInstrs ( MF ) ; return


<s> bool <ISA_LIT>FixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = fixupLoopInstrs ( MF


<s>
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
S
->
Reg
)
;
int
FI
=
MFI
->
CreateFixedSpillStackObject
(
RC
->
getSize
(
)
,
S
->
Offset
)
;
MinOffset
=
std
::
min
(
MinOffset
,
S
->
Offset
)
;
CSI
.
push_back
(
CalleeSavedInfo
(
S
->
Reg
,
FI
)
)
;
SRegs
[
S
->
Reg
]
=
false
;
}
for
(
int
x
=
SRegs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
SRegs
.
find_next
(
x
)
)
{
unsigned
R
=
x
;
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
R
)
;
int
Off
=
MinOffset
RC
->
getSize
(
)
;
unsigned
Align
=
std
::
min
(
RC
->
getAlignment
(
)
,
getStackAlignment
(
)
)
;
assert
(
isPowerOf2_32
(
Align
)
)
;
Off
&=
Align
;
int
FI
=
MFI
->
CreateFixedSpillStackObject
(
RC
->
getSize
(
)
,
Off
)
;
MinOffset
=
std
::
min
(
MinOffset
,
Off
)
;
CSI
.
push_back
(
CalleeSavedInfo
(
R
,
FI
)
)
;
SRegs
[
R
]
=
false
;
}
DEBUG
(
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
,
n
=
CSI
.
size
(
)
;
i
<
n
;
++
i
)
{
int
FI
=
CSI
[
i
]
.
getFrameIdx
(
)
;
int
Off
=
MFI
->
getObjectOffset
(
FI
)
;
dbgs
(
)
<<
' '
<<
PrintReg
(
CSI
[
i
]
.
getReg
(
)
,
TRI
)
<<
<STR_LIT>
<<
FI
<<
<STR_LIT>
;
if
(
Off
>=
<NUM_LIT>
)
dbgs
(
)
<<
'+'
;
dbgs
(
)
<<


<s> ( void ) Opc ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; MBB . erase (


<s> assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; MBB . erase ( I


<s> insertPrologueInBlock ( * PrologB ) ; if ( EpilogB ) { insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ; insertEpilogueInBlock ( * EpilogB ) ; } else { for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertCSRRestoresInBlock ( B , CSI , HRI ) ; for ( auto & B : MF ) if ( B .

isReturnBlock ( ) ) insertEpilogueInBlock ( B ) ;


<s> MachineBasicBlock :: iterator FindAllocFrame ( MachineBasicBlock & B ) { for ( auto & I : B ) if


<s> for ( auto & I : B ) if ( IsAllocFrame ( I


<s> } SmallVector < MachineBasicBlock * , <NUM_LIT> > SFBlocks ; BitVector CSR ( <STR_LIT> ) ; for ( const MCPhysReg * P = HRI . getCalleeSavedRegs ( & MF ) ; * P ; ++ P ) CSR [ * P ] = true ; for ( auto & I : MF ) if ( needsStackFrame ( I , CSR ) ) SFBlocks . push_back ( & I ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( auto & B : SFBlocks ) dbgs ( ) << <STR_LIT> << B -> getNumber ( ) ; dbgs ( ) <<


<s> for ( auto & B : MF ) for ( auto & I : B ) if ( I . getOpcode ( ) == <STR_LIT> ) return & I ; return


<s> for ( auto & B : MF ) for ( auto & I : B ) if ( I . getOpcode ( ) == <STR_LIT> )


<s> bool HasAlloca = MFI . hasVarSizedObjects ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool NoOpt = MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ; unsigned SP = HRI . getStackRegister ( ) , FP = HRI . getFrameRegister ( ) ; unsigned AP = <NUM_LIT> ; if ( const MachineInstr * AI = getAlignaInstr ( MF ) ) AP = AI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; bool UseFP = false , UseAP = false ; if ( NoOpt && !


<s> bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( ( HasFixed || HasPrealloc ) && ( HasAlloca || HasExtraAlign ) ) return true ; if ( MFI . getStackSize (


<s> for ( auto I = MBB . getFirstTerminator ( ) , E = MBB . end ( ) ; I != E ; ++ I ) if ( I


<s> <ISA_LIT>CallFrameInformation ( ) : MachineFunctionPass ( ID ) { PassRegistry & PR = * PassRegistry :: getPassRegistry


<s> } for ( unsigned i = <NUM_LIT> , n = CSI . size ( ) ; i < n ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsKill = ! HRI . isEHReturnCalleeSaveReg ( Reg ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( Reg ) ; HII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , FI , RC , & HRI ) ; if ( IsKill ) MBB . addLiveIn ( Reg ) ; } return true


<s> const char * SpillFun = getSpillFunctionFor ( MaxReg , SK_ToMem ) ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineInstr * SaveRegsCall = BuildMI ( MBB , MI , DL , HII . get ( <STR_LIT> ) ) . addExternalSymbol ( SpillFun ) ; addCalleeSaveRegistersAsImpOperand ( SaveRegsCall , MaxReg , false ) ; for ( unsigned I = <NUM_LIT> ; I < CSI . size ( ) ; ++ I ) MBB . addLiveIn ( CSI [ I ] . getReg ( ) ) ; return true ; } for ( unsigned i = <NUM_LIT> , n = CSI . size ( ) ; i < n ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsKill = ! HRI . isEHReturnCalleeSaveReg ( Reg ) ; int FI = CSI [ i ] .


<s> break ; } unsigned RetOpc = RetI ? RetI -> getOpcode ( ) : <NUM_LIT> ; MachineBasicBlock :: iterator InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; else if ( ! MBB . empty ( ) ) DL = std :: prev ( MBB . end ( ) ) -> getDebugLoc ( ) ; if ( RetOpc == <STR_LIT> ) { BuildMI ( MBB , InsertPt , DL , HII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , InsertPt , DL , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( <STR_LIT> ) ; return ; } if ( RetOpc == <STR_LIT> ) { MachineBasicBlock :: iterator It = RetI ; ++ It ; while ( It != MBB . end


<s> unsigned NumBytes = MFI -> getStackSize ( ) ; unsigned SP = HRI . getStackRegister ( ) ; unsigned MaxCF = MFI -> getMaxCallFrameSize ( ) ; MachineBasicBlock :: iterator InsertPt = MBB . begin ( ) ; auto * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto & AdjustRegs = FuncInfo -> getAllocaAdjustInsts ( ) ; for ( auto MI : AdjustRegs ) { assert ( ( MI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; expandAlloca ( MI , HII , SP , MaxCF ) ; MI -> eraseFromParent ( ) ; } if ( ! hasFP ( MF ) ) return ; const unsigned int ALLOCFRAME_MAX = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; unsigned CallerSavedReg = HRI . getFirstCallerSavedNonParamReg ( ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , CallerSavedReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( CallerSavedReg ) ; } else { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( NumBytes ) . addMemOperand ( MMO ) ; } if (


<s> auto End = It -> getParent ( ) -> instr_end ( ) ; MachineBasicBlock :: const_instr_iterator I = It . getInstrIterator ( ) ; while ( ++ I != End && I -> isBundled ( ) ) if ( I -> getOpcode ( ) == <STR_LIT> ) return true ; return


<s> return MF . getFunction ( ) -> optForMinSize


<s> inline static bool isMinSize ( const MachineFunction


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! MFI -> hasVarSizedObjects ( ) ) return


<s> int Offset = - LFS ; for ( int i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( ! MFI -> isSpillSlotObjectIndex ( i ) || MFI -> isDeadObjectIndex ( i ) ) continue ; int S = MFI -> getObjectSize ( i ) ; LFS += S ; Offset -= S ; MFI -> mapLocalFrameObject ( i , Offset ) ; } MFI -> setLocalFrameSize ( LFS ) ; unsigned A = MFI -> getLocalFrameMaxAlign ( ) ; assert ( A <= <NUM_LIT>


<s> Offset -= S ; MFI -> mapLocalFrameObject ( i , Offset ) ; } MFI -> setLocalFrameSize ( LFS ) ; unsigned A = MFI -> getLocalFrameMaxAlign ( ) ; assert ( A <= <NUM_LIT> && <STR_LIT> ) ; if ( A == <NUM_LIT> ) MFI -> setLocalFrameMaxAlign ( <NUM_LIT> ) ; MFI -> setUseLocalStackAllocationBlock (


<s> bool NeedCFI = MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) -> needsUnwindTableEntry ( ) ; if ( ! NeedCFI )


<s> bool <ISA_LIT>FrameLowering :: shouldInlineCSR ( MachineFunction & MF , const CSIVect & CSI ) const { if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ) return true ; if ( ! isOptSize ( MF ) && ! isMinSize ( MF ) ) if ( MF . getTarget ( ) . getOptLevel ( ) > CodeGenOpt :: Default ) return true ; BitVector Regs ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = CSI . size ( ) ; i < n ; ++ i ) { unsigned R = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( R ) ) return true ; Regs [ R ] = true ; } int F = Regs . find_first ( ) ; if ( F != <STR_LIT> ) return true ; while ( F >= <NUM_LIT> )


<s> unsigned Threshold = isOptSize ( MF ) ? SpillFuncThresholdOs - <NUM_LIT> : SpillFuncThreshold ; return Threshold < NumCSI


<s> bool <ISA_LIT>FrameLowering :: useSpillFunction ( MachineFunction & MF , const CSIVect & CSI ) const { if ( shouldInlineCSR ( MF , CSI ) ) return false ; unsigned NumCSI = CSI . size ( ) ; if ( NumCSI <= <NUM_LIT> ) return false ; unsigned Threshold = isOptSize ( MF

) ? SpillFuncThresholdOs : SpillFuncThreshold ;


<s> private : typedef std :: vector < CalleeSavedInfo > CSIVect ; void expandAlloca ( MachineInstr * AI , const <ISA_LIT>InstrInfo & TII , unsigned SP , unsigned CF ) const ; void insertPrologueInBlock ( MachineBasicBlock & MBB ) const ; void insertEpilogueInBlock ( MachineBasicBlock & MBB ) const ; bool insertCSRSpillsInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const <ISA_LIT>RegisterInfo & HRI ) const ; bool insertCSRRestoresInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const <ISA_LIT>RegisterInfo & HRI ) const ; void insertCFIInstructionsAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator At ) const ; void adjustForCalleeSavedRegsSpillCall ( MachineFunction & MF ) const ; bool replacePredRegPseudoSpillCode ( MachineFunction & MF ) const ; bool replaceVecPredRegPseudoSpillCode ( MachineFunction & MF ) const ; void findShrunkPrologEpilog ( MachineFunction & MF , MachineBasicBlock * & PrologB , MachineBasicBlock * & EpilogB ) const ; bool shouldInlineCSR ( llvm :: MachineFunction & MF , const CSIVect


<s> bool restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override { return true


<s> bool spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override { return true


<s> bool spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override { return


<s> void <ISA_LIT>FrameLowering :: addCalleeSaveRegistersAsImpOperand ( MachineInstr * MI , const CSIVect & CSI , bool IsDef


<s> } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dump_registers ( TmpSup , * TRI ) ; dbgs ( ) << <STR_LIT> ) ; SRegs |= TmpSup ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dump_registers ( SRegs , * TRI ) ; dbgs ( ) << <STR_LIT> ) ; for ( int x = SRegs . find_first ( ) ; x >= <NUM_LIT> ; x = SRegs . find_next ( x ) ) { unsigned R = x ; for ( MCSuperRegIterator SR ( R , TRI ) ; SR . isValid ( ) ; ++ SR ) { if ( ! SRegs [ * SR ] ) continue ; SRegs [ R ] = false ; break ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dump_registers ( SRegs , * TRI ) ; dbgs ( ) << <STR_LIT> ) ; CSI . clear ( ) ; using SpillSlot = TargetFrameLowering :: SpillSlot ; unsigned NumFixed ; int MinOffset = <NUM_LIT> ; const SpillSlot * FixedSlots = getCalleeSavedSpillSlots ( NumFixed ) ; for ( const SpillSlot * S = FixedSlots ; S != FixedSlots + NumFixed ; ++ S ) { if ( ! SRegs [ S -> Reg ] ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( S -> Reg ) ; int FI = MFI . CreateFixedSpillStackObject ( TRI -> getSpillSize ( * RC ) , S -> Offset ) ; MinOffset = std :: min ( MinOffset , S -> Offset ) ; CSI . push_back ( CalleeSavedInfo ( S -> Reg , FI ) ) ; SRegs [ S -> Reg ] = false ; } for ( int x = SRegs . find_first ( ) ; x >= <NUM_LIT> ; x = SRegs . find_next ( x ) ) { unsigned R = x ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass


<s> bool canSimplifyCallFramePseudos ( const MachineFunction & MF )


<s> for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : Num = NumberScavengerSlots ; break ; case <STR_LIT> : Num = <NUM_LIT> ; break ; } unsigned S = HRI . getSpillSize ( * RC ) , A = HRI . getSpillAlignment ( * RC ) ; for ( unsigned i = <NUM_LIT> ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A


<s> for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : Num = NumberScavengerSlots ; break ; case <STR_LIT> : Num = <NUM_LIT> ; break ; } unsigned S = HRI . getSpillSize ( * RC ) , A = HRI . getSpillAlignment ( * RC ) ; for ( unsigned i = <NUM_LIT> ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ; RS -> addScavengingFrameIndex ( NewFI


<s>
dbgs
(
)
<<
'{'
;
for
(
int
x
=
Regs
.
find_first
(
)
;
x
>=
<NUM_LIT>
;
x
=
Regs
.
find_next
(
x
)
)
{
unsigned
R
=
x
;
dbgs
(
)
<<
' '
<<
printReg
(


<s> unsigned Opc = MI . getOpcode ( ) ; ( void ) Opc ; assert ( ( Opc == <STR_LIT> || Opc ==


<s> assert ( ! MFI . hasVarSizedObjects ( ) && ! HST . getRegisterInfo ( ) -> needsStackRealignment ( MF ) ) ; return F . hasFnAttribute ( Attribute :: NoReturn ) && F . hasFnAttribute ( Attribute :: NoUnwind ) && ! F . hasFnAttribute ( Attribute :: UWTable ) && HST . noreturnStackElim

( ) && MFI . getStackSize ( ) == <NUM_LIT> ;


<s> const auto & F = MF . getFunction ( ) ; const auto & MFI = MF . getFrameInfo ( ) ; const auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; assert ( ! MFI . hasVarSizedObjects ( ) && ! HST . getRegisterInfo ( ) -> needsStackRealignment ( MF ) ) ; return F . hasFnAttribute ( Attribute :: NoReturn ) && F . hasFnAttribute ( Attribute :: NoUnwind ) && ! F . hasFnAttribute ( Attribute :: UWTable ) && HST . noreturnStackElim ( ) &&


<s> const auto & F = MF . getFunction ( ) ; assert ( F . hasFnAttribute ( Attribute :: NoReturn ) && F . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) && ! F . getFunction ( ) . hasFnAttribute ( Attribute


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; Register DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstR ) || ! <STR_LIT> . contains ( SrcR ) ) return false ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY ) , TmpR ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY ) , DstR ) . addReg (


<s> bool <ISA_LIT>FrameLowering :: expandCopy ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineInstr * MI = & * It ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstR ) || ! <STR_LIT> . contains ( SrcR ) ) return false ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY ) , TmpR ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY

) , DstR ) . addReg ( TmpR , RegState :: Kill ) ;


<s> int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) , TmpR ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; unsigned TfrOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( TfrOpc ) , DstR ) .


<s> if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; bool NeedsAligna = needsAligna ( MF ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI .


<s> auto UseAligned = [ & ] ( unsigned NeedAlign , unsigned HasAlign ) { return ! NeedsAligna && ( NeedAlign <= HasAlign ) ; } ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstHi )

. addFrameIndex ( FI ) . addImm ( Size ) . cloneMemRefs ( * MI ) ;


<s> bool NeedsAligna = needsAligna ( MF ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc ; auto UseAligned = [ & ] ( unsigned NeedAlign , unsigned HasAlign ) { return ! NeedsAligna && ( NeedAlign <= HasAlign ) ; } ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> :


<s> MachineFunction & MF = * B . getParent ( ) ; auto * HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; HII . loadRegFromStackSlot ( B , It , TmpR1 , FI , RC , HRI ) ; expandLoadVec ( B , std :: prev ( It ) , MRI , HII , NewRegs ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) , DstR ) . addReg ( TmpR1 , RegState :: Kill ) . addReg ( TmpR0 , RegState :: Kill ) ; NewRegs . push_back ( TmpR0 ) ; NewRegs . push_back ( TmpR1 ) ; B . erase ( It ) ; return true


<s> bool Changed = false ; for ( auto & B : MF ) { MachineBasicBlock :: iterator NextI ; for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { MachineInstr * MI = & * I ; NextI = std :: next ( I ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: COPY : Changed |= expandCopy ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandStoreInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandStoreVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandLoadVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandLoadVec2 ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandStoreVec2 ( B , I , MRI , HII , NewRegs ) ; break ; } } } return


<s> for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { MachineInstr * MI = & * I ; NextI = std :: next ( I ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: COPY : Changed |= expandCopy ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandStoreInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandStoreVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandLoadVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandLoadVec2 ( B , I , MRI


<s> unsigned Opc = MI -> getOpcode ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned TfrOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( TfrOpc ) , TmpR ) . addReg ( SrcR , getKillRegState ( IsKill ) ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( TmpR , RegState :: Kill ) . cloneMemRefs ( * MI ) ; NewRegs . push_back (


<s> bool <ISA_LIT>FrameLowering :: expandStoreInt ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Opc = MI -> getOpcode ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT>


<s> Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; bool UseAligned = ! NeedsAligna && ( NeedAlign <= HasAlign ) ; unsigned StoreOpc = UseAligned ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcR , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ; B . erase (


<s> MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; bool NeedsAligna = needsAligna ( MF ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; bool UseAligned = ! NeedsAligna && ( NeedAlign <= HasAlign ) ; unsigned StoreOpc = UseAligned ? <STR_LIT> :


<s> bool <ISA_LIT>FrameLowering :: expandStoreVec2 ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineFunction & MF = * B . getParent ( ) ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; LivePhysRegs LPR ( HRI ) ; LPR . addLiveIns ( B ) ; SmallVector < std :: pair < MCPhysReg , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( auto R = B . begin ( ) ; R != It ; ++ R ) { Clobbers . clear ( ) ; LPR . stepForward ( * R , Clobbers ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; Register SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool NeedsAligna = needsAligna ( MF ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; auto UseAligned = [ & ] ( unsigned NeedAlign , unsigned HasAlign ) { return ! NeedsAligna && ( NeedAlign <= HasAlign ) ; } ; if ( LPR . contains ( SrcLo ) ) { StoreOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ; } if ( LPR . contains ( SrcHi ) ) { StoreOpc = UseAligned ( NeedAlign , HasAlign )


<s> bool HasCall = false , HasAllocFrame = false ; auto T = It . getInstrIterator ( ) ; while ( ++ T != End && T -> isBundled ( ) ) { if ( T -> getOpcode ( ) == <STR_LIT> ) HasAllocFrame = true ; else if ( T -> isCall (


<s> auto F = DeadMap . find ( { Reg , <NUM_LIT> } ) ; if ( F == DeadMap . end ( ) ) return false ; for ( auto & DR : F -> second ) if ( DR . contains ( FIR ) ) return true ; return false ; } ; for ( unsigned Reg : RC -> getRawAllocationOrder ( MF ) ) { bool Dead = true ; for ( auto R : <ISA_LIT>BlockRanges :: expandToSubRegs ( { Reg , <NUM_LIT> } , MRI , HRI ) ) { if ( isDead ( R . Reg ) ) continue ; Dead =


<s> unsigned RPON = <NUM_LIT> ; for ( RPOTType :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) RPO [ ( * I ) -> getNumber ( ) ] = RPON ++ ; for ( auto & I : MF ) { unsigned BN = RPO [ I . getNumber ( ) ] ; for ( auto SI = I . succ_begin ( ) , SE = I . succ_end ( ) ; SI != SE ; ++ SI ) { if ( RPO [ ( * SI ) -> getNumber ( ) ] <= BN ) return ; } } SmallVector < MachineBasicBlock * , <NUM_LIT> > SFBlocks ; BitVector CSR ( <STR_LIT> ) ; for ( const MCPhysReg * P = HRI . getCalleeSavedRegs ( & MF ) ; * P ; ++ P ) for ( MCSubRegIterator S ( * P , & HRI , true ) ; S . isValid ( ) ; ++ S ) CSR [ * S ] = true ; for ( auto & I : MF ) if ( needsStackFrame ( I , CSR , HRI ) ) SFBlocks . push_back ( & I ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( auto & B : SFBlocks ) dbgs ( ) << <STR_LIT> <<


<s> using UnsignedMap = DenseMap < unsigned , unsigned > ; using RPOTType = ReversePostOrderTraversal < const MachineFunction * > ; UnsignedMap RPO ; RPOTType RPOT ( & MF ) ; unsigned RPON = <NUM_LIT> ; for ( RPOTType :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) RPO [ ( * I ) -> getNumber ( ) ] = RPON ++ ; for ( auto & I : MF ) { unsigned BN = RPO [ I . getNumber ( ) ] ; for ( auto SI = I . succ_begin ( ) , SE = I . succ_end ( ) ; SI != SE ; ++ SI ) { if ( RPO [ ( * SI ) -> getNumber ( ) ] <= BN ) return ; } } SmallVector < MachineBasicBlock * , <NUM_LIT> > SFBlocks ; BitVector CSR ( <STR_LIT> ) ; for ( const MCPhysReg * P = HRI . getCalleeSavedRegs ( & MF ) ; * P ; ++ P ) for ( MCSubRegIterator S ( * P , & HRI , true ) ; S . isValid ( ) ; ++ S ) CSR [ * S ] = true ; for ( auto & I : MF ) if ( needsStackFrame ( I , CSR ,


<s> const MachineInstr * <ISA_LIT>FrameLowering :: getAlignaInstr ( const MachineFunction & MF ) const { for ( auto & B : MF ) for ( auto & I : B ) if ( I . getOpcode ( )


<s> bool expandStoreInt ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadInt ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandStoreVecPred ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadVecPred ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandStoreVec2 ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadVec2 ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandStoreVec ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandLoadVec ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ; bool expandSpillMacros ( MachineFunction & MF , SmallVectorImpl < unsigned > & NewRegs ) const ; unsigned findPhysReg ( MachineFunction & MF , <ISA_LIT>BlockRanges :: IndexRange & FIR , <ISA_LIT>BlockRanges :: InstrIndexMap & IndexMap ,

<ISA_LIT>BlockRanges :: RegToRangeMap & DeadMap , const TargetRegisterClass * RC ) const ;


<s> if ( * SubRegs > RegNo ) RegNo = * SubRegs ; } else { if ( ! RegNo || * SubRegs < RegNo ) RegNo = * SubRegs ; } } return RegNo


<s> if ( Reg < <STR_LIT> || Reg > <STR_LIT> ) return Reg ; unsigned RegNo = <NUM_LIT> ; for ( MCSubRegIterator SubRegs ( Reg , & TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) { if ( hireg ) { if ( * SubRegs > RegNo


<s> static unsigned getMaxCalleeSavedReg ( const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo & TRI ) { static_assert ( <STR_LIT> > <NUM_LIT> , <STR_LIT> ) ; if ( CSI . empty ( ) ) return <NUM_LIT> ; unsigned Max = getMax32BitSubRegister ( CSI [ <NUM_LIT> ] . getReg ( ) , TRI ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size


<s> unsigned Max = getMax32BitSubRegister ( CSI [ <NUM_LIT> ] . getReg ( ) , TRI ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I < E ; ++ I ) { unsigned Reg = getMax32BitSubRegister ( CSI [ I ] . getReg ( ) , TRI ) ; if ( Reg > Max ) Max = Reg ; } return


<s> static MachineInstr * getReturn ( MachineBasicBlock & MBB ) { for ( auto & I : MBB ) if ( I . isReturn ( ) ) return


<s> auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; bool HasExtraAlign = HRI . needsStackRealignment ( MF ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; if ( MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return true ; if ( HasAlloca || HasExtraAlign ) return true ; if ( MFI . getStackSize (


<s> if ( HasAlloca || HasExtraAlign ) return true ; if ( MFI . getStackSize ( ) > <NUM_LIT> ) { const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . Options . DisableFramePointerElim ( MF ) || ! EliminateFramePointer ) return true ; if ( EnableStackOVFSanitizer ) return true ; } const auto & HMFI = * MF .

getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> bool hasReservedCallFrame ( const MachineFunction & MF )


<s> bool hasReservedCallFrame ( const MachineFunction &


<s> static bool hasReturn ( const MachineBasicBlock & MBB ) { for ( auto I = MBB . getFirstTerminator ( ) , E = MBB . end ( ) ;

I != E ; ++ I ) if ( I -> isReturn ( ) ) return true ;


<s> MachineBasicBlock :: const_iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB .


<s> unsigned SP = HRI . getStackRegister ( ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addDef ( SP ) . addReg ( SP ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; unsigned SP = HRI . getStackRegister ( ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addImm ( - int ( NumBytes ) ) ; } else