<s> if ( All0 ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; if ( All1 ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; SDValue Rs [ <NUM_LIT> ] ; SDValue Z = getZero ( dl , <STR_LIT> , DAG ) ; unsigned Rep = <NUM_LIT> / VecTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SDValue S = DAG . getConstant ( <NUM_LIT> << i , dl , <STR_LIT> ) ; Rs [ i ] = DAG . getSelect ( dl , <STR_LIT> , Ops [ i / Rep ] , S , Z ) ; } for ( ArrayRef < SDValue > A ( Rs ) ; A . size ( ) != <NUM_LIT> ; A = A . drop_back ( A . size ( ) / <NUM_LIT> ) ) { for ( unsigned i = <NUM_LIT> , e = A . size ( ) / <NUM_LIT> ; i != e ; ++ i ) Rs [ i ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Rs [ <NUM_LIT> * i ] , Rs [ <NUM_LIT> * i + <NUM_LIT> ] ) ; } return getInstr ( <STR_LIT> , dl , VecTy , { Rs [ <NUM_LIT> ] } , DAG ) ; } return SDValue


<s> if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; Register PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; Chain = TPR . getValue ( <NUM_LIT> ) ; }


<s> bool isVTi1Type = false ; if ( auto * CV = dyn_cast < ConstantVector > ( CPN -> getConstVal ( ) ) ) { if ( cast < VectorType > ( CV -> getType ( ) ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { IRBuilder < > IRB ( CV -> getContext ( ) ) ; SmallVector < Constant * , <NUM_LIT> > NewConst ; unsigned VecLen = CV -> getNumOperands ( ) ; assert ( isPowerOf2_32 ( VecLen ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < VecLen ; ++ i ) NewConst . push_back ( IRB . getInt8 ( CV -> getOperand


<s> unsigned char TF = IsPositionIndependent ? <STR_LIT> : <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Alignment , Offset , TF ) ; else if ( isVTi1Type ) T = DAG . getTargetConstantPool ( CVal , ValTy , Alignment , Offset , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Alignment , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op


<s> SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlign ( ) . value


<s> const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; Register VReg = MRI . createVirtualRegister ( RC ) ; SDValue Copy = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getValVT ( ) == <STR_LIT> ) { assert ( RegVT . getSizeInBits ( ) <= <NUM_LIT> ) ; SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; HFL . FirstVarArgSavedReg = NextSingleReg ( * RC , VA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { SDValue L = DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI , <NUM_LIT> ) ) ; InVals . push_back ( L ) ; } } } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { for ( int i = HFL . FirstVarArgSavedReg ; i < <NUM_LIT> ; i ++ ) MRI . addLiveIn ( <STR_LIT> + i ) ; } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { HMFI . setFirstNamedArgFrameIndex ( HMFI . getFirstNamedArgFrameIndex ( ) - <NUM_LIT> ) ; HMFI . setLastNamedArgFrameIndex ( - int ( MFI . getNumFixedObjects ( ) ) ) ; int NumVarArgRegs = <NUM_LIT> - HFL . FirstVarArgSavedReg ; bool RequiresPadding = ( NumVarArgRegs & <NUM_LIT> ) ; int RegSaveAreaSizePlusPadding = RequiresPadding ? ( NumVarArgRegs + <NUM_LIT> ) * <NUM_LIT> : NumVarArgRegs * <NUM_LIT> ; if ( RegSaveAreaSizePlusPadding > <NUM_LIT> ) { int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo . getNextStackOffset ( ) ; if ( ! ( RegAreaStart % <NUM_LIT> ) ) RegAreaStart

= ( RegAreaStart + <NUM_LIT> ) & - <NUM_LIT> ;


<s> void <ISA_LIT>TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( isHvxOperation ( N ,


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DestPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op


<s> auto & FuncInfo = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto & HFL = * Subtarget . getFrameLowering ( ) ; SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue SavedRegAreaStartFrameIndex = DAG . getFrameIndex ( FuncInfo . getRegSavedAreaStartFrameIndex ( ) , <STR_LIT> ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( HFL . FirstVarArgSavedReg & <NUM_LIT> ) SavedRegAreaStartFrameIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getFrameIndex ( FuncInfo . getRegSavedAreaStartFrameIndex ( ) , <STR_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , SavedRegAreaStartFrameIndex , FIN , MachinePointerInfo ( SV ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getFrameIndex ( FuncInfo . getVarArgsFrameIndex ( ) , PtrVT ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back (


<s> MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getFrameIndex ( FuncInfo . getVarArgsFrameIndex ( ) , PtrVT ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getFrameIndex ( FuncInfo . getVarArgsFrameIndex ( ) , PtrVT


<s> assert ( ElemTy . isScalarInteger ( ) ) ; MVT WideTy = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> * ElemTy . getSizeInBits ( ) ) , OpTy . getVectorNumElements ( ) ) ; return DAG . getSExtOrTrunc ( DAG . getSelect ( dl , WideTy , PredOp , DAG . getSExtOrTrunc ( Op1 , dl ,

WideTy ) , DAG . getSExtOrTrunc ( Op2 , dl , WideTy ) ) , dl , OpTy ) ;


<s> SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , TF ) ; if ( RM == Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ; return DAG . getNode ( <STR_LIT> , SDLoc


<s> SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ; DEBUG ( { dbgs ( ) << LLVM_FUNCTION_NAME << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( ) << <STR_LIT> ; } ) ; SDValue AC = DAG . getConstant ( A , dl


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst


<s> int64_t Offset = GAN -> getOffset ( ) ; auto & HLOF = * HTM . getObjFileLowering ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; if ( HLOF . isGlobalInSmallSection ( GV , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl


<s> EVT VT = Op . getValueType ( ) ; int Idx = cast < JumpTableSDNode > ( Op ) -> getIndex ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: PIC_


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; int Idx = cast < JumpTableSDNode > ( Op ) -> getIndex ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: PIC_ ) { SDValue T = DAG . getTargetJumpTable ( Idx


<s> unsigned ValWidth = ValTy . getSizeInBits ( ) ; unsigned ElemWidth = VecTy . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( ( VecWidth % ElemWidth ) == <NUM_LIT> ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV ) ; if ( ElemWidth == <NUM_LIT> ) { assert ( VecWidth == VecTy . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; if ( IdxN ) { if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , IdxV ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * Scale , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : break ; } return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerUnalignedLoad ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op


<s> case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerUnalignedLoad ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE (


<s> SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Cmp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cmp ) -> get ( ) ; EVT VT = Op . getValueType ( ) ; EVT LHSVT = LHS . getValueType ( ) ; EVT RHSVT = RHS . getValueType ( ) ; if ( LHSVT == <STR_LIT> ) { assert ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) || <STR_LIT> ( CC ) ) ; unsigned ExtOpc = <STR_LIT> ( CC ) ? <STR_LIT> : <STR_LIT> ; SDValue LX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , LHS ) ; SDValue RX = DAG . getNode ( ExtOpc , dl , <STR_LIT> , RHS ) ; SDValue SC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LX , RX , Cmp ) ; return SC ; } if ( VT . isVector ( ) ) return Op ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && ( RHSVT == <STR_LIT> || RHSVT == <STR_LIT> ) && ( LHSVT == <STR_LIT> || LHSVT == <STR_LIT> ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( C && C -> getAPIntValue ( ) . isNegative ( ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ; } if ( isSExtFree ( LHS )


<s> if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMemoryAccess ( SVT , Alignment , Flags , Fast ) ; return TargetLoweringBase :: allowsMemoryAccess ( Context , DL , VT

, AddrSpace , Alignment , Flags , Fast ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMemoryAccess ( LLVMContext & Context , const DataLayout & DL , EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT (


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Alignment , Flags


<s> ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * HwLen ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ; } if ( ElemTy == <STR_LIT> && VecLen == <NUM_LIT> * HwLen

) return TargetLoweringBase :: TypeSplitVector ;


<s> if ( VecLen == <NUM_LIT> || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned HwLen = Subtarget . getVectorLength ( ) ; ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * HwLen ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase ::


<s> switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; HFL . FirstVarArgSavedReg = NextSingleReg ( * RC , VA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { SDValue L = DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI , <NUM_LIT> ) ) ; InVals . push_back ( L ) ; } } } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { for ( int i = HFL . FirstVarArgSavedReg ; i < <NUM_LIT> ; i ++ ) MRI . addLiveIn ( <STR_LIT> + i ) ; } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { HMFI . setFirstNamedArgFrameIndex ( HMFI . getFirstNamedArgFrameIndex ( ) - <NUM_LIT> ) ; HMFI . setLastNamedArgFrameIndex ( - int ( MFI . getNumFixedObjects ( ) ) ) ; int NumVarArgRegs = <NUM_LIT> - HFL . FirstVarArgSavedReg ; bool RequiresPadding = ( NumVarArgRegs & <NUM_LIT> ) ; int RegSaveAreaSizePlusPadding = RequiresPadding ? ( NumVarArgRegs + <NUM_LIT> ) * <NUM_LIT> : NumVarArgRegs * <NUM_LIT> ; if ( RegSaveAreaSizePlusPadding > <NUM_LIT> ) { int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo . getNextStackOffset ( ) ; if ( ! ( RegAreaStart % <NUM_LIT> ) ) RegAreaStart = ( RegAreaStart + <NUM_LIT> ) & - <NUM_LIT> ; int RegSaveAreaFrameIndex = MFI . CreateFixedObject ( RegSaveAreaSizePlusPadding , RegAreaStart , true ) ; HMFI . setRegSavedAreaStartFrameIndex ( RegSaveAreaFrameIndex ) ; int Offset = RegAreaStart +


<s> case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , DAG ) ; case <STR_LIT> : return LowerStore ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUAddSubO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAddSubCarry ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerUnalignedLoad ( SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * LN = cast < LoadSDNode > ( Op . getNode ( ) ) ; MVT LoadTy = ty ( Op ) ; unsigned NeedAlign = Subtarget . getTypeAlignment ( LoadTy ) ; unsigned HaveAlign = LN -> getAlignment ( ) ; if ( HaveAlign >= NeedAlign ) return Op ; const SDLoc & dl ( Op ) ; const DataLayout & DL = DAG . getDataLayout ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; bool DoDefault = false ; if ( ! LN -> isUnindexed ( ) ) DoDefault = true ; if ( ! AlignLoads ) { if ( allowsMemoryAccessForAlignment ( Ctx , DL , LN -> getMemoryVT ( ) , * LN -> getMemOperand ( ) ) ) return Op ; DoDefault = true ; } if ( ! DoDefault && ( <NUM_LIT> * HaveAlign ) == NeedAlign ) { MVT PartTy = HaveAlign <= <NUM_LIT> ? <STR_LIT> ( <NUM_LIT> * HaveAlign ) : <STR_LIT> ( <STR_LIT> , HaveAlign ) ; DoDefault = allowsMemoryAccessForAlignment ( Ctx , DL , PartTy , * LN -> getMemOperand ( ) ) ; } if ( DoDefault ) { std :: pair < SDValue , SDValue > P = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( { P . first , P . second } , dl ) ; } assert ( LoadTy . getSizeInBits ( ) == <NUM_LIT> * NeedAlign ) ; unsigned LoadLen = NeedAlign ; SDValue Base = LN -> getBasePtr ( ) ; SDValue Chain = LN -> getChain ( ) ; auto BO = getBaseAndOffset ( Base ) ; unsigned BaseOpc = BO . first . getOpcode ( ) ; if ( BaseOpc == <STR_LIT> && BO . second % LoadLen == <NUM_LIT> ) return Op ; if ( BO . second % LoadLen != <NUM_LIT> ) { BO . first = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( BO . second % LoadLen , dl , <STR_LIT> ) ) ; BO . second -= BO . second % LoadLen ; } SDValue BaseNoOff = ( BaseOpc != <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first ,

DAG . getConstant ( NeedAlign , dl , <STR_LIT> ) ) : BO . first ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { auto Aligned = [ ] ( unsigned GivenA , unsigned MinA ) -> bool { return ( GivenA % MinA ) == <NUM_LIT> ; } ; if ( Size >= <NUM_LIT> && Aligned ( DstAlign , <NUM_LIT> ) && ( IsMemset || Aligned ( SrcAlign , <NUM_LIT> )


<s> <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) , MF . getFunction ( ) . getFunctionType ( ) -> getNumParams ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool ByVal = Flags . isByVal ( ) ; if ( VA . isRegLoc ( ) && ByVal && Flags . getByValSize ( ) <= <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool InReg = VA . isRegLoc ( ) && ( ! ByVal || ( ByVal && Flags . getByValSize ( ) > <NUM_LIT> ) ) ; if ( InReg ) { MVT RegVT = VA . getLocVT ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) RegVT = VA . getValVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; Register VReg = MRI . createVirtualRegister ( RC ) ; SDValue Copy = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getValVT ( ) == <STR_LIT> ) { assert ( RegVT . getSizeInBits ( ) <= <NUM_LIT> ) ; SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID (


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Subtarget . hasV5Ops (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT


<s> int FI ; if ( ( VA . isRegLoc ( ) && ! Flags . isByVal ( ) ) || ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) > <NUM_LIT> ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; } StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; FI = MFI -> CreateFixedObject ( ObjSize , StackLocation ,


<s> } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; } StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; FI = MFI -> CreateFixedObject ( ObjSize , StackLocation , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ) ; } } } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode (


<s> const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType (


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI ->


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; switch ( Node -> getOpcode ( ) ) { case <STR_LIT> : { unsigned NumOps = Node -> getNumOperands ( ) ; if ( Node -> getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { if ( FuncInfo -> hasClobberLR ( ) ) break ; unsigned Flags = cast < ConstantSDNode > ( Node -> getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_Mem : { for ( ; NumVals ; -- NumVals , ++ i ) { } break ; } case InlineAsm :: Kind_RegDefEarlyClobber : { for ( ; NumVals ; -- NumVals , ++ i


<s> Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg


<s> LoadSDNode * LN = cast < LoadSDNode > ( Op . getNode ( ) ) ; MVT LoadTy = ty ( Op ) ; unsigned NeedAlign = Subtarget . getTypeAlignment ( LoadTy ) ; unsigned HaveAlign = LN -> getAlignment ( ) ; if ( HaveAlign >= NeedAlign ) return Op ; const SDLoc & dl ( Op ) ; const DataLayout & DL = DAG . getDataLayout ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; bool DoDefault = false ; if ( ! LN -> isUnindexed ( ) ) DoDefault = true ; if ( ! AlignLoads ) { if ( allowsMemoryAccessForAlignment ( Ctx , DL , LN -> getMemoryVT ( ) , * LN -> getMemOperand ( ) ) ) return Op ; DoDefault = true ; } if ( ! DoDefault && ( <NUM_LIT> * HaveAlign ) == NeedAlign ) { MVT PartTy = HaveAlign <= <NUM_LIT> ? <STR_LIT> ( <NUM_LIT> * HaveAlign ) : <STR_LIT> ( <STR_LIT> , HaveAlign ) ; DoDefault = allowsMemoryAccessForAlignment ( Ctx , DL , PartTy , * LN -> getMemOperand ( ) ) ; } if ( DoDefault ) { std :: pair < SDValue , SDValue > P = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( { P . first , P . second } , dl ) ; } assert ( LoadTy . getSizeInBits ( ) == <NUM_LIT> * NeedAlign ) ; unsigned LoadLen = NeedAlign


<s> SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , HRI . getStackRegister ( ) , PtrVT ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: BCvt : case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue MemAddr = DAG . getConstant ( LocMemOffset , dl , StackPtr . getValueType ( ) ) ; MemAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , MemAddr ) ; if ( Flags . isByVal ( ) ) { MemOpChains . push_back ( CreateCopyOfByValArgument ( Arg , MemAddr , Chain , Flags , DAG , dl ) ) ; } else { MachinePointerInfo LocPI = MachinePointerInfo :: getStack ( LocMemOffset ) ; SDValue S = DAG . getStore ( Chain , dl , Arg , MemAddr , LocPI , false , false , <NUM_LIT> ) ; MemOpChains . push_back ( S ) ; } continue ; } if ( VA . isRegLoc ( ) ) RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; if ( ! isTailCall ) { SDValue C = DAG . getConstant ( NumBytes , dl , PtrVT , true ) ; Chain = DAG . getCALLSEQ_START ( Chain , C , dl ) ; } SDValue InFlag ; if ( ! isTailCall ) { for ( unsigned i = <NUM_LIT> , e = RegsToPass . size


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getType ( ) -> getPrimitiveSizeInBits ( )


<s> return LI -> getType ( ) -> getPrimitiveSizeInBits


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT .


<s> static bool classof ( const DiagnosticInfo * DI ) { return DI -> getKind ( ) ==


<s> Value * <ISA_LIT>TargetLowering :: emitLoadLinked ( IRBuilderBase & Builder , Type * ValueTy , Value * Addr , AtomicOrdering Ord ) const { BasicBlock * BB = Builder . GetInsertBlock ( ) ; Module * M = BB -> getParent ( ) -> getParent ( ) ; unsigned SZ = ValueTy -> getPrimitiveSizeInBits ( ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; auto PtrTy = cast < PointerType > ( Addr -> getType ( ) ) ; PointerType * NewPtrTy = Builder . getIntNTy ( SZ ) -> getPointerTo


<s> Module * M = BB -> getParent ( ) -> getParent ( ) ; Type * Ty = Val -> getType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; Type * CastTy = Builder . getIntNTy ( SZ ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; unsigned AS = Addr -> getType ( ) -> getPointerAddressSpace ( ) ; Addr = Builder . CreateBitCast ( Addr , CastTy -> getPointerTo ( AS ) ) ; Val = Builder . CreateBitCast ( Val , CastTy ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * Ext = Builder . CreateZExt ( Cmp , Type :: getInt32Ty ( M -> getContext ( ) ) ) ; return


<s> Value * <ISA_LIT>TargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { BasicBlock * BB = Builder . GetInsertBlock ( ) ; Module * M = BB -> getParent ( ) -> getParent ( ) ; Type * Ty = Val -> getType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; Type * CastTy = Builder . getIntNTy ( SZ ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; unsigned AS = Addr -> getType ( ) -> getPointerAddressSpace ( ) ; Addr = Builder . CreateBitCast ( Addr , CastTy -> getPointerTo ( AS ) ) ; Val = Builder . CreateBitCast ( Val


<s> if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ <NUM_LIT> ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == <STR_LIT> ) return TargetLoweringBase ::


<s> if ( GO && Subtarget . useSmallData ( ) && HLOF . isGlobalInSmallSection ( GO , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } bool UsePCRel = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Off = DAG . getConstant ( Offset , dl ,


<s> bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue NL = DAG . getLoad ( LN -> getAddressingMode ( ) , LN -> getExtensionType ( ) , <STR_LIT> , dl , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getOffset ( ) , LN -> getPointerInfo ( ) , <STR_LIT> , LN -> getAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) , LN -> getAAInfo ( ) , LN -> getRanges ( ) ) ; LN = cast < LoadSDNode > ( NL . getNode ( ) ) ; } Align ClaimAlign = LN -> getAlign ( ) ; if ( ! validateConstPtrAlignment ( LN -> getBasePtr ( ) , ClaimAlign , dl , DAG ) ) return replaceMemWithUndef ( Op , DAG ) ; SDValue LU = LowerUnalignedLoad ( SDValue ( LN , <NUM_LIT> ) , DAG ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , Ty , LU ) ; SDValue Ch = cast < LoadSDNode > ( LU . getNode ( ) ) -> getChain ( ) ; return DAG . getMergeValues ( { TC , Ch } , dl ) ; } return LU


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerStore ( SDValue Op , SelectionDAG & DAG ) const { const SDLoc & dl ( Op ) ; StoreSDNode * SN = cast < StoreSDNode > ( Op . getNode ( ) ) ; SDValue Val = SN -> getValue ( ) ; MVT Ty = ty ( Val ) ; bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; SDValue NS = DAG . getStore ( SN -> getChain ( ) , dl , TC , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ; if ( SN -> isIndexed ( ) ) { NS = DAG . getIndexedStore ( NS , dl , SN -> getBasePtr ( ) , SN

-> getOffset ( ) , SN -> getAddressingMode ( ) ) ;


<s> if ( ! DoDefault && ( <NUM_LIT> * HaveAlign ) == NeedAlign ) { MVT PartTy = HaveAlign <= <NUM_LIT> ? <STR_LIT> ( <NUM_LIT> * HaveAlign ) : <STR_LIT> ( <STR_LIT> , HaveAlign ) ; DoDefault = allowsMemoryAccessForAlignment ( Ctx , DL , PartTy , * LN -> getMemOperand ( ) ) ; } if ( DoDefault ) { std :: pair < SDValue , SDValue > P = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( { P . first , P . second } , dl ) ; } assert ( LoadTy . getSizeInBits ( ) == <NUM_LIT> * NeedAlign ) ; unsigned LoadLen = NeedAlign ; SDValue Base = LN -> getBasePtr ( ) ; SDValue Chain = LN -> getChain ( ) ; auto BO = getBaseAndOffset ( Base ) ; unsigned BaseOpc = BO . first . getOpcode ( ) ; if ( BaseOpc == <STR_LIT> && BO . second % LoadLen == <NUM_LIT> ) return Op ; if ( BO . second % LoadLen != <NUM_LIT> ) { BO . first = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( BO . second % LoadLen , dl , <STR_LIT> ) ) ; BO . second -= BO . second % LoadLen ; } SDValue BaseNoOff = ( BaseOpc != <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( NeedAlign , dl , <STR_LIT> ) ) : BO . first ; SDValue Base0 = DAG . getMemBasePlusOffset ( BaseNoOff , TypeSize :: Fixed ( BO . second ) , dl ) ; SDValue Base1 = DAG . getMemBasePlusOffset ( BaseNoOff , TypeSize :: Fixed ( BO . second + LoadLen ) , dl ) ; MachineMemOperand * WideMMO = nullptr ; if ( MachineMemOperand * MMO = LN -> getMemOperand ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; WideMMO = MF . getMachineMemOperand ( MMO -> getPointerInfo ( ) , MMO -> getFlags ( ) , <NUM_LIT> * LoadLen , Align ( LoadLen ) , MMO -> getAAInfo ( ) , MMO -> getRanges ( ) , MMO -> getSyncScopeID ( ) , MMO ->

getSuccessOrdering ( ) , MMO -> getFailureOrdering ( ) ) ;


<s> void print ( DiagnosticPrinter & DP ) const override { DP << Msg


<s> void print ( DiagnosticPrinter & DP ) const override { DP <<


<s> assert ( ! LS -> isIndexed ( ) && <STR_LIT> ) ; SDValue Chain = LS -> getChain ( ) ; SDValue Trap = DAG . getNode ( <STR_LIT> , dl , <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: validateConstPtrAlignment ( SDValue Ptr , Align NeedAlign , const SDLoc & dl , SelectionDAG & DAG ) const { auto * CA = dyn_cast < ConstantSDNode > ( Ptr ) ; if ( ! CA ) return true ; unsigned Addr = CA -> getZExtValue ( ) ; Align HaveAlign = Addr != <NUM_LIT> ? Align ( <NUM_LIT> << countTrailingZeros ( Addr ) ) : NeedAlign ; if ( HaveAlign >= NeedAlign ) return true ; static int DK_MisalignedTrap = llvm :: getNextAvailablePluginDiagnosticKind ( ) ; struct DiagnosticInfoMisalignedTrap : public DiagnosticInfo { DiagnosticInfoMisalignedTrap ( StringRef M ) : DiagnosticInfo ( DK_MisalignedTrap , DS_Remark ) , Msg ( M ) { } void print ( DiagnosticPrinter & DP ) const override { DP << Msg ; } static bool classof ( const DiagnosticInfo * DI ) { return DI -> getKind ( ) == DK_MisalignedTrap ; } StringRef Msg ; } ; std :: string


<s> case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , DAG ) ; case <STR_LIT> : return LowerStore ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUAddSubO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAddSubCarry ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE


<s> SDValue <ISA_LIT>TargetLowering :: LowerVACOPY ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget . isEnvironmentMusl ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DestPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset


<s> static const uint16_t RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> ,


<s> <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return


<s> static bool CC_<ISA_LIT>_VarArg ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { assert ( ( NumNamedVarArgParams > <NUM_LIT> ) && <STR_LIT> ) ; if ( ( int ) ValNo < NumNamedVarArgParams ) { return CC_<ISA_LIT> ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; } unsigned ofst ; if ( ArgFlags . isByVal ( ) ) { assert ( ( ArgFlags . getByValSize ( ) > <NUM_LIT> ) && <STR_LIT> ) ; ofst = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack (


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat &


<s> if ( Flags . isByVal ( ) ) { MemOpChains . push_back ( CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ) ; } else { MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } continue ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } } if ( ! MemOpChains . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; } if ( ! isTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , dl ) ; SDValue InFlag ; if ( ! isTailCall ) { for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } } if ( isTailCall ) { InFlag = SDValue ( ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } InFlag = SDValue ( ) ; } if ( flag_aligned_memcpy ) { const char * MemcpyName = <STR_LIT> ; Callee = DAG . getTargetExternalSymbol ( MemcpyName , getPointerTy ( ) ) ; flag_aligned_memcpy = false ; } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) .


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , TM . getRegisterInfo ( ) -> getStackRegister ( ) , Sub ) ; SDValue Ops [ <NUM_LIT> ] = { ArgAdjust , CopyChain


<s> const <ISA_LIT>RegisterInfo * TRI = TM . getRegisterInfo ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ,


<s> case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN (


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op ,


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain


<s> SDLoc dl ( Op ) ; SDNode * OpNode = Op . getNode ( ) ; EVT SVT = OpNode -> getValueType ( <NUM_LIT> ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , CC ) ; return DAG . getNode ( <STR_LIT> , dl , SVT ,


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return LowerINLINEASM ( Op , DAG ) ; if ( isHvxOperation ( Op ) ) { if ( SDValue V = LowerHvxOperation ( Op , DAG ) ) return V ; } switch ( Opc ) { default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , DAG ) ; case <STR_LIT> : return LowerStore ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAddSubCarry ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op ,


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto & MF = State . getMachineFunction ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseHVX = HST . useHVXOps ( ) ; bool UseHVXDbl = HST . useHVXDblOps ( ) ; if ( ( UseHVX && ! UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstS ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( ( UseHVX && ! UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT>


<s> State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( ( UseHVX && UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstD ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( ( UseHVX && UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstS ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack (


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> ,


<s> } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; if ( ST -> getValue ( ) . getValueType ( ) == <STR_LIT> && ST -> isTruncatingStore ( ) ) return false ; } else { return false ; } bool IsInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , Base , Offset ,


<s> bool isLegal = getIndexedAddressParts ( Op , VT , Base , Offset , IsInc , DAG ) ; if ( isLegal ) { auto & HII = * Subtarget . getInstrInfo ( ) ; int32_t OffsetVal = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; if ( HII . isValidAutoIncImm ( VT , OffsetVal ) ) { AM = IsInc ? <STR_LIT> : <STR_LIT> ; return true


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'q' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) { bool R = ( CallerCC == CallingConv :: C || CallerCC == CallingConv :: Fast ) ; bool E = ( CalleeCC == CallingConv :: C || CalleeCC == CallingConv :: Fast ) ; if ( ! R || ! E ) return false ; } if ( isVarArg


<s> if ( Ty -> isSized ( ) ) { unsigned A = DL . getABITypeAlignment ( Ty ) ; if ( ( AM . BaseOffs % A ) != <NUM_LIT> ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs >> Log2_32 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ; default : return false ; } return true


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( Ty -> isSized ( ) ) { unsigned A = DL . getABITypeAlignment ( Ty ) ; if ( ( AM . BaseOffs % A ) != <NUM_LIT> ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs >> Log2_32 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ; default : return false


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { if ( Subtarget . useHVXOps ( ) ) return isStridedLoad (

Mask ) != StridedLoadKind :: NoPattern ;


<s> for ( auto idx : Mask ) { if ( ( idx - odd_start ) == <NUM_LIT> ) odd_start = idx ; else break ; } if ( odd_start == ( int ) ( mask_len * <NUM_LIT> ) - <NUM_LIT> ) return StridedLoadKind :: Odd ; return StridedLoadKind


<s> if ( ( idx - even_start ) == <NUM_LIT> ) even_start = idx ; else break ; } if ( even_start == ( int ) ( mask_len * <NUM_LIT> ) - <NUM_LIT> ) return StridedLoadKind :: Even ; for ( auto idx : Mask ) { if ( ( idx - odd_start ) == <NUM_LIT> ) odd_start = idx ; else


<s> } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { SDValue V0 = BVN -> getOperand ( <NUM_LIT> ) ; SDValue V1 = BVN -> getOperand ( <NUM_LIT> ) ; if ( V0 . isUndef ( ) ) V0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( V1 . isUndef ( ) ) V1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( V0 ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( V1 ) ; if ( ! C0 || ! C1 ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; if ( isInt < <NUM_LIT> > ( C0 -> getSExtValue ( ) ) || isInt < <NUM_LIT> > ( C1 -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i ) . isUndef ( ) ) continue ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( i ) ) ; if ( ! Cst ) { SDValue pack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BVN -> getOperand ( <NUM_LIT> ) , BVN -> getOperand ( <NUM_LIT> ) ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , pack ) ; } } } uint64_t Res = <NUM_LIT> ; unsigned EltSize = Size / NElts ; SDValue ConstVal ; uint64_t Mask = ~ uint64_t ( <NUM_LIT> ) >> ( <NUM_LIT> - EltSize ) ; bool HasNonConstantElements = false ; for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { unsigned OpIdx = NElts - i - <NUM_LIT> ; SDValue Operand = BVN -> getOperand ( OpIdx ) ; if ( Operand . isUndef ( ) ) continue ; int64_t Val = <NUM_LIT> ; if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Operand ) ) Val = Cst -> getSExtValue ( ) ; else HasNonConstantElements = true ; Val &= Mask


<s> if ( ! C0 || ! C1 ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; if ( isInt < <NUM_LIT> > ( C0 -> getSExtValue ( ) ) || isInt < <NUM_LIT> > ( C1 -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i ) . isUndef ( ) ) continue ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( i ) ) ; if ( ! Cst ) { SDValue pack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BVN -> getOperand ( <NUM_LIT> ) , BVN -> getOperand ( <NUM_LIT> ) ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , pack ) ; } } } uint64_t Res = <NUM_LIT> ; unsigned EltSize = Size / NElts ; SDValue ConstVal ; uint64_t Mask = ~ uint64_t ( <NUM_LIT> ) >> ( <NUM_LIT> - EltSize ) ; bool HasNonConstantElements = false ; for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { unsigned OpIdx = NElts - i - <NUM_LIT> ; SDValue Operand = BVN -> getOperand ( OpIdx ) ; if ( Operand . isUndef ( ) ) continue ; int64_t Val = <NUM_LIT> ; if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Operand ) ) Val = Cst -> getSExtValue ( ) ; else HasNonConstantElements = true ; Val &= Mask ; Res = ( Res << EltSize ) | Val ; } if ( Size > <NUM_LIT> ) return


<s> if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ; Glue = RetVal . getValue ( <NUM_LIT>


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT>


<s> unsigned Width = VecVT . getSizeInBits ( ) ; if ( NElts == <NUM_LIT> ) { MVT ST = VecVT . getSimpleVT ( ) ; if ( ST == <STR_LIT> || ST == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Vec0 ) ; if ( UseHVX ) { assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXSglOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXDblOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V = C0 ; for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { unsigned N = NElts - i - <NUM_LIT> ; SDValue OpN = Op . getOperand ( N ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && OpN . getValueSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; OpN = DAG . getNode ( <STR_LIT> , dl , VT , C , OpN ) ; } SDValue Idx = DAG . getConstant ( N , dl , <STR_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , W ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , S , Offset ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { V , OpN , Or } ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; EVT VT = Op . getValueType ( ) ; unsigned NElts = Op . getNumOperands ( ) ; SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec0 . getValueType ( ) ; unsigned Width = VecVT . getSizeInBits ( ) ; if ( NElts == <NUM_LIT> ) { MVT ST = VecVT . getSimpleVT ( ) ; if ( ST == <STR_LIT> || ST == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Vec0 ) ; if ( UseHVX ) { assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXSglOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXDblOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V = C0


<s> else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc


<s> if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , Offset , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) ==


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR_HVX ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; bool UseHVXSgl = Subtarget . useHVXSglOps ( ) ; if ( ! VT . isVector ( ) || ! UseHVX ) return SDValue ( ) ; EVT ResVT = Op . getValueType ( ) ; unsigned ResSize = ResVT . getSizeInBits ( ) ; unsigned VectorSizeInBits = UseHVXSgl ? ( <NUM_LIT> * <NUM_LIT> ) : ( <NUM_LIT> * <NUM_LIT> ) ; unsigned OpSize = VT . getSizeInBits ( ) ; if ( ! ( ResVT . isByteSized ( ) && ResSize == VectorSizeInBits ) || ! ( VT . isByteSized ( ) && OpSize == <NUM_LIT> * VectorSizeInBits ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > (


<s> SDValue N ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; else return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N ) ; } SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , DAG . getConstant ( EltSize , dl , <STR_LIT> ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted , Offset ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Val . getValueSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , VT , C , Val ) ; } const SDValue Ops [ ] = { Vec , Val


<s> SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; int EltSize = EltVT . getSizeInBits ( ) ; SDValue Width = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? EltSize : VTN * EltSize , dl , <STR_LIT> ) ; if ( ConstantSDNode * C = cast < ConstantSDNode > ( Idx ) ) { SDValue Offset = DAG . getConstant ( C -> getSExtValue ( ) * EltSize , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { Vec , Val , Width , Offset } ; SDValue N ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N =


<s> Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , Alignment , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue ShiftAmount = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ <NUM_LIT> ] , ShiftAmount ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Tmp1 , Loads [ <NUM_LIT> ] ) ; Increment = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Base . getValueType ( ) , Base , Increment ) ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , Alignment , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; Increment = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Base . getValueType ( ) , Base , Increment ) ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , Alignment , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; Tmp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ <NUM_LIT> ] , ShiftAmount ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Tmp1 , Loads [ <NUM_LIT> ] ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Tmp4 , Tmp2 ) ; LoadChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) ) ; } else { Result = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , LoadNode -> getPointerInfo ( ) , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; LoadChain = Result . getValue ( <NUM_LIT> ) ; } } else llvm_unreachable ( <STR_LIT>


<s> SDLoc dl ( GA ) ; int64_t Offset = GA -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , <STR_LIT> ) ; SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( TGA , DAG ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl


<s> SDLoc dl ( GA ) ; int64_t Offset = GA -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , <STR_LIT> ) ; SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( TGA ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerVECTOR_SHIFT ( SDValue Op , SelectionDAG & DAG ) const { BuildVectorSDNode * BVN = nullptr ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDValue V3 ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V1 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V2 ; else if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V2 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V1 ; else return SDValue ( ) ; SDValue CommonSplat = BVN -> getOperand ( <NUM_LIT> ) ; SDValue Result ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; default : return SDValue ( ) ; } } else if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; default : return SDValue ( ) ; } } else { return SDValue (


<s> EVT VT = Op . getValueType ( ) ; if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V1 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V2 ; else if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V2 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V1 ; else return SDValue ( ) ; SDValue CommonSplat = BVN -> getOperand ( <NUM_LIT> ) ; SDValue Result ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case


<s> bool UseHVX = Subtarget . useHVXOps ( ) ; if ( V2 . isUndef ( ) ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return createSplat ( DAG , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! V1 . getOperand ( i ) . isUndef ( ) ) { IsScalarToVector = false ; break ; } } if ( IsScalarToVector ) return createSplat ( DAG , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; } return createSplat ( DAG , dl , VT , DAG . getConstant ( Lane , dl , <STR_LIT> ) ) ; } if ( UseHVX ) { ArrayRef < int > Mask = SVN -> getMask ( ) ; size_t MaskLen = Mask . size ( ) ; int ElemSizeInBits = VT . getScalarSizeInBits ( ) ; if ( ( Subtarget . useHVXSglOps ( ) && ( ElemSizeInBits * MaskLen ) == <NUM_LIT> * <NUM_LIT> ) || ( Subtarget . useHVXDblOps ( ) && ( ElemSizeInBits * MaskLen ) == <NUM_LIT> * <NUM_LIT> ) ) { StridedLoadKind Pattern = isStridedLoad


<s> if ( ElemWidth == <NUM_LIT> ) { assert ( VecWidth == VecTy . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; if ( IdxN ) { if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , IdxV ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal


<s> switch ( Opc ) { default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op ,


<s> virtual EVT getSetCCResultType ( LLVMContext


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT ) const { return


<s> } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; SDValue M0 = DAG . getConstant ( <NUM_LIT> / VecWidth , dl , <STR_LIT> ) ; SDValue I0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , M0 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , I0 ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * Scale , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ; if ( IdxN ) { unsigned Off = IdxN -> getZExtValue ( ) * ElemWidth ; if ( VecWidth == <NUM_LIT> && ValWidth == <NUM_LIT> ) { assert ( Off == <NUM_LIT> || Off


<s> SDValue getNode ( unsigned MachineOpc , const SDLoc & dl , MVT Ty , ArrayRef < SDValue > Ops ,


<s> if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , InFlag ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> , TPR . getValue ( <NUM_LIT> ) ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) ; } InVals . push_back ( RetVal . getValue ( <NUM_LIT> ) ) ; Chain = RetVal . getValue ( <NUM_LIT> ) ; InFlag = RetVal . getValue ( <NUM_LIT> )


<s> auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , InFlag ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> , TPR . getValue ( <NUM_LIT> ) ) ; }


<s> auto & HLOF = * HTM . getObjFileLowering ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; if ( HLOF . IsGlobalInSmallSection ( GV , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } bool UsePCRel = GV -> hasInternalLinkage ( ) || GV -> hasHiddenVisibility ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ; if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl ,


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; auto * GV = GAN -> getGlobal ( ) ; int64_t Offset = GAN -> getOffset ( ) ; auto & HLOF = * HTM . getObjFileLowering ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; if ( HLOF . IsGlobalInSmallSection ( GV , HTM ) ) return DAG

. getNode ( <STR_LIT> , dl , PtrVT , GA ) ;


<s> virtual EVT getSetCCResultType ( EVT VT ) const { return <STR_LIT>


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT ==


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , DebugLoc dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , MachinePointerInfo (


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , DebugLoc dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false

, MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain .


<s> SDValue Size = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue StackPointer = DAG . getCopyFromReg ( Chain , dl , SPReg , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> ,

dl , <STR_LIT> , StackPointer , Size ) ;


<s> unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue StackPointer = DAG . getCopyFromReg ( Chain , dl , SPReg , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , TM . getRegisterInfo ( ) -> getStackRegister ( ) ,


<s> unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; } StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; FI = MFI -> CreateFixedObject ( ObjSize , StackLocation , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ) ; } } } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; if ( isVarArg


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) )


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr


<s> SDValue <ISA_LIT>TargetLowering :: LowerGLOBALADDRESS ( SDValue Op , SelectionDAG & DAG ) const { SDValue Result ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & )


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand (


<s> SDValue <ISA_LIT>TargetLowering :: LowerMEMBARRIER ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl

, VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl


<s> SDNode * OpNode = Op . getNode ( ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , OpNode -> getValueType ( <NUM_LIT> ) , Cond


<s> SDValue Cond = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op .


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , Op . getDebugLoc ( ) , Addr , Op . getOperand (

<NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex ( ) , <STR_LIT>


<s> } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue A = DAG . getTargetBlockAddress ( BA , PtrVT


<s> case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op