<s> } if ( MO . isDef ( ) && IsSameOrSubReg ) DefIdx = OpNum ; } } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; SDep T = I ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; Latency = std :: max ( Latency , <NUM_LIT> ) ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } } T . setSUnit ( Src ) ; auto F = find ( Dst -> Preds , T ) ; assert ( F != Dst -> Preds . end ( ) ) ; F -> setLatency ( I . getLatency (


<s> static MVT Types [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static MVT TypesV68 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( useHVXV68Ops ( ) && useHVXFloatingPoint ( )


<s> void <ISA_LIT>Subtarget :: getPostRAMutations ( std :: vector < std :: unique_ptr <

ScheduleDAGMutation >> & Mutations ) const {


<s> Mutations . push_back ( llvm :: make_unique < HVXMemLatencyMutation > ( ) ) ; Mutations . push_back ( llvm :: make_unique < BankConflictMutation > ( )


<s> void <ISA_LIT>Subtarget :: getSMSMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation >> & Mutations


<s> void <ISA_LIT>Subtarget :: getSMSMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation >> & Mutations ) const { Mutations . push_back ( llvm :: make_unique < UsrOverflowMutation >


<s> if ( isHVXVectorType ( Ty , true ) ) return Align ( getVectorLength (


<s> bool hasV67Ops ( ) const { return get<ISA_LIT>ArchVersion ( )


<s> bool hasV67OpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) == <STR_LIT>


<s> bool hasV68Ops ( ) const { return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT> ::


<s> return get<ISA_LIT>ArchVersion ( ) ==


<s> bool hasV69Ops ( ) const { return get<ISA_LIT>ArchVersion ( )


<s> return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT>


<s> bool hasV69OpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) == <STR_LIT>


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( <ISA_LIT>_MC :: select<ISA_LIT>CPU ( TT , CPU ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) )

, RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) , InstrItins ( getInstrItineraryForCPU ( CPUString ) ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( <ISA_LIT>_MC :: select<ISA_LIT>CPU ( TT , CPU ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) , InstrItins ( getInstrItineraryForCPU ( CPUString ) ) { assert ( InstrItins . Itineraries != nullptr && <STR_LIT>


<s> static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , { <STR_LIT> , V62 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT>


<s> bool isEnvironmentMusl ( ) const { return TargetTriple . getEnvironment (


<s> bool useAudioOps ( ) const { return UseAudioOps


<s> bool useCabac ( ) const { return UseCabac


<s> bool useHVXIEEEFPOps ( ) const { return UseHVXIEEEFPOps && useHVXOps


<s> return UseHVXQFloatOps && <ISA_LIT>HVXVersion >=


<s> bool useHVXV60Ops ( ) const { return <ISA_LIT>HVXVersion >= <STR_LIT>


<s> return <ISA_LIT>HVXVersion >= <STR_LIT> ::


<s> bool useHVXV67Ops ( ) const { return <ISA_LIT>HVXVersion >=


<s> bool useHVXV69Ops ( ) const { return <ISA_LIT>HVXVersion >= <STR_LIT> ::


<s> return get<ISA_LIT>ArchVersion ( ) >=


<s> return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT> ::


<s> return get<ISA_LIT>ArchVersion ( ) ==


<s> return get<ISA_LIT>ArchVersion ( ) == <STR_LIT> ::


<s> bool hasV62TOps ( ) const { return get<ISA_LIT>ArchVersion ( ) >=


<s> return get<ISA_LIT>ArchVersion ( ) == <STR_LIT>


<s> bool hasV65TOps ( ) const { return get<ISA_LIT>ArchVersion ( ) >=


<s> bool hasV65TOpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) == <STR_LIT> ::


<s> void <ISA_LIT>Subtarget :: getSMSMutations ( std :: vector < std

:: unique_ptr < ScheduleDAGMutation >> & Mutations ) const {


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { CPUString = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( getTargetTriple ( ) , CPU ) ; static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , } ; auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVXOps = false ; UseHVXDblOps = false ; UseLongCalls = false ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( Enable<ISA_LIT>HVX . getPosition ( ) ) UseHVXOps = Enable<ISA_LIT>HVX ; if ( Enable<ISA_LIT>HVXDouble . getPosition ( ) ) UseHVXDblOps = Enable<ISA_LIT>HVXDouble ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; return * this


<s> auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVXOps = false ; UseHVXDblOps = false ; UseLongCalls = false ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( Enable<ISA_LIT>HVX . getPosition ( ) ) UseHVXOps = Enable<ISA_LIT>HVX ; if ( Enable<ISA_LIT>HVXDouble . getPosition ( ) ) UseHVXDblOps


<s> MachineInstr & SrcInst = * Src -> getInstr ( ) ; MachineInstr & DstInst = * Dst -> getInstr ( ) ; if ( Dst -> isBoundaryNode ( ) ) return false ; if ( SrcInst . isPHI ( ) || DstInst . isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ; if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst , <NUM_LIT> ) ; if ( DstBest != nullptr ) changeLatency ( Src ,


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( V2 ) , CPUString ( CPU . str ( ) ) { ParseSubtargetFeatures ( CPU , FS ) ; switch ( <ISA_LIT>ArchVersion ) { case <ISA_LIT>Subtarget :: V2 : break ; case <ISA_LIT>Subtarget :: V3 : EnableV3 = true ; break ; case <ISA_LIT>Subtarget :: V4 : break ; case <ISA_LIT>Subtarget :: V5 : break ; default : llvm_unreachable ( <STR_LIT> ) ; } InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ; else ModeIEEERndNear =


<s> UseHVX64BOps = false ; UseAudioOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; if ( isTinyCore ( ) ) { if ( ! EnableBSBSched . getPosition ( ) ) UseBSBScheduling = false ; } FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . reset ( <STR_LIT>


<s> T . setSUnit ( Src ) ; auto F = std :: find ( Dst -> Preds . begin ( ) , Dst -> Preds . end ( ) , T ) ; assert ( F != Dst -> Preds


<s> const <ISA_LIT>ArchEnum & get<ISA_LIT>ArchVersion ( ) const { return <ISA_LIT>ArchVersion


<s> bool hasV3TOps ( ) const { return <ISA_LIT>ArchVersion >=


<s> bool hasV4TOpsOnly ( ) const { return <ISA_LIT>ArchVersion == V4


<s> bool hasV5TOpsOnly ( ) const { return <ISA_LIT>ArchVersion ==


<s> bool isSubtargetV2 ( ) const { return <ISA_LIT>ArchVersion ==


<s> if ( ! VecTy -> isVectorTy ( ) || isa < ScalableVectorType > ( VecTy ) ) return false ; if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT Ty = EVT :: getEVT ( VecTy , false ) ; if ( ! Ty . isSimple ( ) || Ty . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( isHVXVectorType ( Ty . getSimpleVT ( ) , IncludeBool ) ) return true ; auto Action = getTargetLowering ( ) -> getPreferredVectorAction ( Ty . getSimpleVT ( ) ) ; return Action == TargetLoweringBase ::


<s> SmallSet < SUnit * , <NUM_LIT> > ExclSrc ; SmallSet < SUnit * , <NUM_LIT> > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( <NUM_LIT> ) ; return ; } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { unsigned DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , <NUM_LIT> ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear (


<s> { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , { <STR_LIT> , <STR_LIT> :: V66 } , } ; auto FoundIt = CpuTable . find (


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V4 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseMemOps = DisableMemOps ? false : EnableMemOps ; ModeIEEERndNear = EnableIEEERndNear ; UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . set ( <STR_LIT> , false ) ) ; setFeatureBits ( <ISA_LIT>_MC :: completeHVXFeatures ( Features )


<s> UseMemOps = DisableMemOps ? false : EnableMemOps ; ModeIEEERndNear = EnableIEEERndNear ; UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . set ( <STR_LIT> , false ) ) ; setFeatureBits ( <ISA_LIT>_MC :: completeHVXFeatures ( Features ) ) ; return * this


<s> if ( MO . isReg ( ) ) { Register MOReg = MO . getReg ( ) ; if ( DepR . isVirtual ( ) ) { IsSameOrSubReg = ( MOReg == DepR ) ; } else { IsSameOrSubReg = getRegisterInfo ( ) -> isSubRegisterEq ( DepR , MOReg ) ; } if ( MO . isDef ( ) && IsSameOrSubReg ) DefIdx = OpNum ; } } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; SDep T = I ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ;


<s> IsSameOrSubReg = getRegisterInfo ( ) -> isSubRegisterEq ( DepR , MOReg ) ; } if ( MO . isDef ( ) && IsSameOrSubReg ) DefIdx = OpNum ; } } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; SDep T = I ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; Latency = std :: max ( Latency , <NUM_LIT> ) ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } } T . setSUnit (


<s> if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max (


<s> } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx =


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V4 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseMemOps = DisableMemOps ? false : EnableMemOps ; ModeIEEERndNear = EnableIEEERndNear ; UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; return * this


<s> case <ISA_LIT>Subtarget :: V3 : EnableV3 = true ; break ; case <ISA_LIT>Subtarget :: V4 : break ; default : llvm_unreachable ( <STR_LIT> ) ; } InstrItins = getInstrItineraryForCPU ( CPUString


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( ) { InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; if ( CPUString == <STR_LIT> ) { <ISA_LIT>ArchVersion = V4 ; } else if ( CPUString == <STR_LIT>


<s> if ( ! VecTy . isVector ( ) || ! useHVXOps ( ) || VecTy . isScalableVector ( ) ) return false ; MVT ElemTy = VecTy . getVectorElementType ( ) ; if ( ! IncludeBool && ElemTy == <STR_LIT> ) return false ; unsigned HwLen = getVectorLength ( ) ; unsigned NumElems = VecTy . getVectorNumElements ( ) ; ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; if ( IncludeBool && ElemTy == <STR_LIT> ) { if ( <NUM_LIT> * HwLen == NumElems ) return true ; for ( MVT T : ElemTypes ) if ( NumElems * T .

getSizeInBits ( ) == <NUM_LIT> * HwLen ) return true ;


<s> llvm_unreachable ( <STR_LIT> ) ; } ParseSubtargetFeatures ( CPUString , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear )


<s> { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V4 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition (


<s> if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , <NUM_LIT> ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( <NUM_LIT>


<s> MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , <NUM_LIT> , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , <NUM_LIT> ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( <NUM_LIT> ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep


<s> static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , { <STR_LIT> , <STR_LIT> :: V66 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . reset ( <STR_LIT> ) ) ; setFeatureBits ( <ISA_LIT>_MC :: completeHVXFeatures


<s> static std :: map < StringRef , <STR_LIT> > CpuTable { { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V5 } , { <STR_LIT> , <STR_LIT> :: V55 } , { <STR_LIT> , <STR_LIT> :: V60 } , { <STR_LIT> , <STR_LIT> :: V62 } , { <STR_LIT> , <STR_LIT> :: V65 } , } ; auto FoundIt = CpuTable . find ( CPUString ) ; if ( FoundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = FoundIt -> second ; else llvm_unreachable ( <STR_LIT> ) ; UseHVX128BOps = false ; UseHVX64BOps = false ; UseLongCalls = false ; UseBSBScheduling = hasV60Ops ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits


<s> if ( Op . isReg ( ) && Dep . getReg ( ) != Op . getReg ( ) ) return ; } if ( useBSBScheduling ( ) && SrcInst -> isPHI ( ) ) { changePhiLatency ( SrcInst , Dst , Dep ) ; return ; } if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == <NUM_LIT> ) DstInst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( SrcInst , DstInst ) && isBestZeroLatency ( Src , Dst , QII ) ) { Dep . setLatency ( <NUM_LIT> ) ; return ; } updateLatency ( SrcInst , DstInst ,


<s> for ( auto & I : Deps ) { if ( I . getSUnit ( ) != Dst ) continue ; I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , UpdateDst -> getInstr ( ) , I ) ; for ( auto & PI : UpdateDst


<s> I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , UpdateDst -> getInstr ( ) , I ) ; for ( auto & PI : UpdateDst -> Preds ) { if ( PI . getSUnit ( ) != Src || ! PI . isAssignedRegDep ( ) ) continue ; PI . setLatency ( Lat ) ; updateLatency ( SrcI , UpdateDst -> getInstr ( )


<s> for ( const SDep & PI : Dst -> Preds ) { if ( PI . getLatency ( )


<s> MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( SrcInst -> isPHI ( ) || DstInst -> isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ; if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst , <NUM_LIT> ) ; if ( DstBest != nullptr ) changeLatency ( Src , Src -> Succs , DstBest


<s> } else if ( EnableTCLatencySched ) { if ( QII . isTC1 ( SrcInst ) || QII . isTC2 ( SrcInst ) ) if ( ! QII . isTC1 ( DstInst ) && ! QII . isTC2 ( DstInst ) ) Dep . setLatency ( Dep .


<s> ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ; return llvm :: find ( ElemTypes , Ty ) != ElemTypes . end


<s> bool isHVXElementType ( MVT Ty , bool IncludeBool = false ) const { if ( ! useHVXOps ( ) ) return false ; if ( Ty . isVector ( ) ) Ty = Ty . getVectorElementType ( ) ; if ( IncludeBool && Ty == <STR_LIT> ) return true ; ArrayRef < MVT > ElemTypes = getHVXElementTypes


<s> if ( Dep . getReg ( ) != SrcInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && Dep . getKind ( ) == SDep :: Anti ) { if ( DstInst -> mayStore ( ) ) return ; if ( Dep . getReg ( ) != DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } else if ( QII -> isPostIncrement ( * DstInst ) && DstInst -> mayStore ( ) && Dep . isAssignedRegDep ( ) ) { MachineOperand & Op = DstInst -> getOperand ( DstInst -> getNumOperands ( ) - <NUM_LIT> ) ; if ( Op . isReg ( ) && Dep . getReg ( ) != Op . getReg ( ) ) return ; } if ( useBSBScheduling ( ) && SrcInst -> isPHI ( ) ) { changePhiLatency ( * SrcInst , Dst , Dep ) ; return ; } if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == <NUM_LIT> ) DstInst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst

) && isBestZeroLatency ( Src , Dst , QII ) ) {


<s> for ( const SDep & PI : Dst -> Preds ) { if ( PI . getLatency ( ) != <NUM_LIT> ) continue ; Dep . setLatency ( <NUM_LIT> )


<s> void <ISA_LIT>Subtarget :: getPostRAMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation


<s> unsigned getSmallDataThreshold ( ) const { return


<s> static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , } ; auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end ( ) ) <ISA_LIT>ArchVersion = foundIt -> second ; else llvm_unreachable (


<s> CPUString = <STR_LIT> ( getTargetTriple ( ) , CPU ) ; static std :: map < StringRef , <ISA_LIT>ArchEnum > CpuTable { { <STR_LIT> , V4 } , { <STR_LIT> , V5 } , { <STR_LIT> , V55 } , { <STR_LIT> , V60 } , } ; auto foundIt = CpuTable . find ( CPUString ) ; if ( foundIt != CpuTable . end (

) ) <ISA_LIT>ArchVersion = foundIt -> second ;


<s> if ( SrcInst . isPHI ( ) || DstInst . isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ; if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst ,


<s> bool useHVXDblOps ( ) const { return UseHVXOps && UseHVXDblOps


<s> bool useMemOps ( ) const { return UseMemOps


<s> static Target The<ISA_LIT>Target ; return


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target (

) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTarget < Triple :: hexagon , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> ,


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: hexagon , true > X ( getThe<ISA_LIT>Target ( )


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target


<s> RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT>


<s> RegisterTarget < Triple :: hexagon , true > X ( getThe<ISA_LIT>Target (


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: hexagon , true > X (


<s> RegisterTarget < Triple :: hexagon , false > X (


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! Disable<ISA_LIT>CFGOpt ) addPass (

create<ISA_LIT>CFGOptimizer ( ) , false ) ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( ) ,


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt ::

Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {


<s> if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false ) ; } return false


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) , false ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false ) ; } return false


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; addPass ( createAtomicExpandPass ( TM ) ) ; if ( ! NoOpt


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) , false ) ; if ( ! DisableAModeOpt ) addPass ( create<ISA_LIT>OptAddrMode ( ) ,


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer (


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ,


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) { Pass * Exp = create<ISA_LIT>ExpandCondsets ( ) ; insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ; } if ( ! DisableStoreWidening ) addPass (

create<ISA_LIT>StoreWidening ( ) , false ) ;


<s> addPass ( create<ISA_LIT>CopyToCombine ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>CopyToCombine ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C )


<s> return new <ISA_LIT>PassConfig ( this


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc ::


<s> return getTM < <ISA_LIT>TargetMachine > (


<s> auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> ,

TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target


<s> virtual const <ISA_LIT>FrameLowering * getFrameLowering ( ) const { return & FrameLowering


<s> virtual const InstrItineraryData * getInstrItineraryData


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return


<s> virtual const ScalarTargetTransformInfo * getScalarTargetTransformInfo ( ) const { return & STTI


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return &


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo (


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return &


<s> virtual const VectorTargetTransformInfo * getVectorTargetTransformInfo ( ) const


<s> addPass ( create<ISA_LIT>Packetizer ( NoOpt ) , false ) ; if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ; addPass ( create<ISA_LIT>CallFrameInformation ( ) ,


<s> addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>Packetizer ( NoOpt ) , false ) ; if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ; addPass ( create<ISA_LIT>CallFrameInformation ( ) ,


<s> addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) .

needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ;


<s> TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableVectorCombine ) addPass ( create<ISA_LIT>VectorCombineLegacyPass ( )


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>Packetizer ( NoOpt


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new VLIWMachineScheduler ( C , std :: make_unique < <ISA_LIT>ConvergingVLIWScheduler > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; return DAG


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new VLIWMachineScheduler ( C , std :: make_unique < <ISA_LIT>ConvergingVLIWScheduler > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique <

<ISA_LIT>Subtarget :: CallMutation > ( ) ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model >


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT>

, TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {


<s> PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; } )


<s> addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass


<s> void <ISA_LIT>TargetMachine :: adjustPassManager ( PassManagerBuilder & PMB ) { PMB . addExtension ( PassManagerBuilder :: EP_LateLoopOptimizations , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>LoopIdiomPass ( ) ) ; }


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initialize<ISA_LIT>ExpandCondsetsPass ( * PassRegistry :: getPassRegistry ( ) ) ; initAsmInfo (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT )

: LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) {


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass (

create<ISA_LIT>NewValueJump ( ) , false ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass ( ) ) ; PM . add (


<s> PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopUnrollPass ( )


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! Disable<ISA_LIT>CFGOpt )

addPass ( create<ISA_LIT>CFGOptimizer ( TM ) ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; if ( ! TLOF . IsSmallDataEnabled


<s> virtual ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false ) ; initAsmInfo ( )


<s> PM . add ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( )


<s> PM . add ( create<ISA_LIT>CFGOptimizer ( get<ISA_LIT>TargetMachine ( ) ) ) ; return


<s> PM . add ( create<ISA_LIT>CFGOptimizer ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true


<s> PM . add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM . add ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) )


<s> PM . add ( create<ISA_LIT>FixupHwLoops ( ) ) ; } PM . add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM . add ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine


<s> PM . add ( create<ISA_LIT>HardwareLoops ( ) ) ; } return


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( IfConverterID ) ; return


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return &


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return &


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false )


<s> if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) ,


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false


<s> if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( )


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( )


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! DisableHardwareLoops ) addPass (

create<ISA_LIT>HardwareLoops ( ) , false ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return &


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget


<s> if ( ! NoOpt ) { addPass ( createConstantPropagationPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( create<ISA_LIT>GenExtract


<s> if ( ! NoOpt ) { addPass ( createConstantPropagationPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP (


<s> addPass ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>Peephole ( )


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc (


<s> } addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>Packetizer (


<s> if ( ! DisableHardwareLoops ) { addPass ( create<ISA_LIT>HardwareLoops (


<s> if ( ! DisableHardwareLoops ) { addPass ( create<ISA_LIT>HardwareLoops ( )


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( & IfConverterID ) ; return true


<s> virtual const TargetData * getTargetData


<s> virtual const TargetData * getTargetData (


<s> PM . add ( createConstantPropagationPass ( ) ) ; PM . add ( createLoopSimplifyPass ( ) ) ; PM . add ( createDeadCodeEliminationPass ( ) ) ; PM . add ( createConstantPropagationPass (


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig (


<s> if ( ! Disable<ISA_LIT>MISched ) { enablePass ( &


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false )


<s> TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableVectorCombine ) addPass ( create<ISA_LIT>VectorCombineLegacyPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP (


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F )


<s> static ScheduleDAGInstrs * createVLIWMachineSched ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new VLIWMachineScheduler ( C , std :: make_unique < ConvergingVLIWScheduler > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation >


<s> DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI )


<s> Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( !


<s> PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; } )


<s> addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) , false ) ; if ( ! DisableHSDR ) addPass (


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) , false ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify (


<s> if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> if ( ! DisableStoreWidening ) addPass ( create<ISA_LIT>StoreWidening ( ) , false ) ; if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target (


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X


<s> AttributeList FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( FnAttrs . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions (


<s> } ) ; PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) { LoopPassManager LPM ( DebugPassManager ) ; FunctionPassManager FPM ( DebugPassManager ) ; LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; }


<s> PB . registerLateLoopOptimizationsEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>LoopIdiomRecognitionPass ( ) ) ; } ) ; PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) { LoopPassManager LPM ( DebugPassManager ) ; FunctionPassManager FPM ( DebugPassManager ) ; LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std ::


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo

( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true


<s> Attribute CPUAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeList :: FunctionIndex , <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; if ( FnAttrs . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) FS = FS . empty ( ) ? <STR_LIT> : <STR_LIT> + FS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F


<s> if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( ! DisableHCP


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>OptimizeSZextends ( ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( )


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry (


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>GenMuxPass ( PR )


<s> bool <ISA_LIT>TargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) { PM . add ( create<ISA_LIT>CFGOptimizer ( * this


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { if ( ! DisableHardwareLoops ) { PM . add ( create<ISA_LIT>FixupHwLoops ( ) ) ; } PM . add ( create<ISA_LIT>ExpandPredSpillCode ( * this ) ) ; PM . add ( create<ISA_LIT>SplitTFRCondSets ( * this ) ) ; return false


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI (


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM -> add ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>Peephole ( )


<s> bool <ISA_LIT>PassConfig :: addPostRegAlloc (


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( ! DisableHardwareLoops ) { PM -> add ( create<ISA_LIT>FixupHwLoops ( ) ) ; } PM -> add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ; PM -> add ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) )


<s> PM -> add ( create<ISA_LIT>HardwareLoops


<s> std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple


<s> } ) ; PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass (

<ISA_LIT>VectorLoopCarriedReusePass ( ) ) ;


<s> } ) ; PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; }


<s> addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass (

create<ISA_LIT>GenPredicate ( ) , false ) ;


<s> if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( )


<s> if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( )


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT ,

CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( )


<s> return TargetIRAnalysis ( [ this ] (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo (


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ; addPass ( create<ISA_LIT>Packetizer ( ) , false


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initAsmInfo (


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ,


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { const <ISA_LIT>TargetMachine & TM =


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) { Pass * Exp = create<ISA_LIT>ExpandCondsets ( ) ; insertPass ( & RegisterCoalescerID , IdentifyingPassPtr


<s> insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ; } if ( ! DisableStoreWidening ) addPass ( create<ISA_LIT>StoreWidening ( ) , false ) ; if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI (


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { setMCUseCFI ( false )


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>RemoveExtendArgs ( TM ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; } return false


<s> LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move


<s> void <ISA_LIT>TargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB , bool DebugPassManager ) { PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager

& MPM , PassBuilder :: OptimizationLevel Level ) {


<s> if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; if ( ! DisableHCP ) { addPass ( create<ISA_LIT>ConstPropagationPass ( ) ) ; addPass ( & UnreachableMachineBlockElimID ) ; } if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) ) ; } return


<s> } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , true , true , false , true ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ; if ( EnableGenExtract ) addPass


<s> if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) ) ; if ( ! DisableAModeOpt ) addPass ( create<ISA_LIT>OptAddrMode ( )


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>GatherPacketize ( ) , false ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>Packetizer ( ) , false ) ; if ( EnableVectorPrint ) addPass ( create<ISA_LIT>VectorPrint ( ) , false ) ; addPass ( create<ISA_LIT>CallFrameInformation (


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>GatherPacketize ( ) , false ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>Packetizer ( ) ,


<s> addPass ( create<ISA_LIT>CopyToCombine ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; addPass ( create<ISA_LIT>SplitConst32AndConst64 ( )


<s> void <ISA_LIT>TargetMachine :: adjustPassManager ( PassManagerBuilder & PMB ) { PMB . addExtension ( PassManagerBuilder :: EP_LateLoopOptimizations , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>LoopIdiomPass ( ) ) ; } )


<s> PMB . addExtension ( PassManagerBuilder :: EP_LateLoopOptimizations , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>LoopIdiomPass ( )


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this ,


<s> DAG -> addMutation ( make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG ->


<s> DAG -> addMutation ( make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG ->


<s> if ( CM ) return * CM ; return CodeModel


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const


<s> const <ISA_LIT>FrameLowering * getFrameLowering


<s> const <ISA_LIT>InstrInfo * getInstrInfo (


<s> const InstrItineraryData * getInstrItineraryData (


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo (


<s> return getSubtargetImpl ( ) -> getSelectionDAGInfo ( )


<s> const <ISA_LIT>Subtarget * getSubtargetImpl (


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <STR_LIT> <STR_LIT> <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM ) , ( <ISA_LIT>NoOpt ? CodeGenOpt :: None : OL ) ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { initialize<ISA_LIT>ExpandCondsetsPass ( * PassRegistry :: getPassRegistry (


<s> if ( GO -> hasSection ( ) ) { StringRef Section = GO -> getSection ( ) ; if ( Section . contains ( <STR_LIT> ) ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; if ( Section . contains ( <STR_LIT> ) ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE |


<s> switch ( Size ) { default : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS


<s> bool <ISA_LIT>TargetObjectFile :: isSmallDataEnabled ( const TargetMachine & TM


<s> return Sec . contains ( <STR_LIT> ) || Sec . contains ( <STR_LIT> )


<s> TRACE ( ( GO -> hasPrivateLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasLocalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasInternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasExternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isCommon ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSS ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSSLocal ( ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( EmitLutInText && GO -> getName ( ) .


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { TRACE ( <STR_LIT> << GO -> getName ( ) << <STR_LIT> ) ; TRACE ( <STR_LIT> << GO -> getSection ( ) << <STR_LIT> ) ; TRACE ( ( GO -> hasPrivateLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasLocalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasInternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasExternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isCommon ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSS ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSSLocal ( ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( EmitLutInText && GO -> getName ( ) . startswith ( <STR_LIT> ) ) { if ( const Function * Fn = getLutUsedFunction ( GO ) ) return selectSectionForLookupTable ( GO , TM , Fn ) ; } if ( isGlobalInSmallSection ( GO , TM ) ) return selectSmallSectionForGlobal ( GO , Kind , TM ) ; if ( Kind . isCommon ( ) ) { return BSSSection ; } TRACE ( <STR_LIT> ) ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM


<s> MCSection * <ISA_LIT>TargetObjectFile :: selectSectionForLookupTable ( const GlobalObject * GO , const TargetMachine & TM , const Function * Fn ) const { SectionKind Kind = SectionKind :: getText ( ) ; if ( Fn -> hasSection ( ) ) return getExplicitSectionGlobal ( Fn


<s> bool <ISA_LIT>TargetObjectFile :: shouldPutJumpTableInFunctionSection ( bool UsesLabelDifference , const Function & F


<s> if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GO -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } if ( isGlobalInSmallSection ( GO , TM ) ) return

selectSmallSectionForGlobal ( GO , Kind , TM ) ;


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF


<s> TRACE ( <STR_LIT> << GO -> getName ( ) << <STR_LIT> ) ; TRACE ( <STR_LIT> << GO -> getSection ( ) << <STR_LIT> ) ; TRACE ( ( GO -> hasPrivateLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasLocalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasInternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasExternalLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( GO -> hasCommonLinkage ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isCommon ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSS ( ) ? <STR_LIT> : <STR_LIT> ) << ( Kind . isBSSLocal ( ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( isGlobalInSmallSection ( GO , TM ) ) return selectSmallSectionForGlobal ( GO , Kind , TM ) ; if ( Kind . isCommon ( )


<s> } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type *


<s> unsigned SmallestElement = <NUM_LIT> ; if ( ! Ty ) return <NUM_LIT> ; switch ( Ty -> getTypeID ( ) ) { case Type :: StructTyID : { const StructType * STy = cast < const StructType > ( Ty ) ; for ( auto & E : STy -> elements ( ) ) { unsigned AtomicSize = getSmallestAddressableSize ( E , GV , TM ) ; if ( AtomicSize < SmallestElement ) SmallestElement = AtomicSize ; } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: BFloatTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID : case Type :: MetadataTyID : case Type :: X86_MMXTyID : case Type :: TokenTyID : return <NUM_LIT>


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS


<s> if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind .

isDataNoRel ( ) || Kind . isCommon ( ) ) {


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang ,


<s> const StructType * STy = cast < const StructType > ( Ty ) ; for ( auto & E : STy -> elements ( ) ) { unsigned AtomicSize = getSmallestAddressableSize ( E , GV , TM ) ; if ( AtomicSize < SmallestElement ) SmallestElement = AtomicSize ; } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: BFloatTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID : case Type :: MetadataTyID : case Type :: X86_MMXTyID : case Type ::


<s> const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ; } case Type :: FunctionTyID : case Type :: VoidTyID : case Type :: BFloatTyID : case Type :: X86_FP80TyID : case Type :: FP128TyID : case Type :: PPC_FP128TyID : case Type :: LabelTyID : case Type


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; } return false


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( Kind . isBSS ( ) || Kind . isDataNoRel ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ; } return false


<s> if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM ,


<s> if ( PointerType * PT = dyn_cast < PointerType > ( GType ) ) GType = PT -> getElementType ( ) ; if ( isa < ArrayType > ( GType ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StructType * ST = dyn_cast < StructType > ( GType ) ) { if ( ST -> isOpaque ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned Size = GVar -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( GType ) ; if ( Size ==


<s> } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SmallDataThreshold << <STR_LIT> << GO -> getName ( ) << <STR_LIT> ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVar ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( GVar -> hasSection ( ) ) { bool IsSmall = isSmallDataSection ( GVar -> getSection ( ) ) ; LLVM_DEBUG ( dbgs ( ) << ( IsSmall ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << GVar -> getSection ( ) << '\n' ) ; return IsSmall ; } if ( GVar -> isConstant ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool IsLocal = GVar -> hasLocalLinkage ( ) ; if ( ! StaticsInSData && IsLocal ) { LLVM_DEBUG ( dbgs (


<s> const MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ; if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV

, TM , Kind ) ) return SmallDataSection ;


<s> if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GV -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GV -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } if ( isGlobalInSmallSection ( GV , TM ) ) return selectSmallSectionForGlobal (


<s> StringRef Section = GV -> getSection ( ) ; if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GV -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; if ( Section . find ( <STR_LIT> ) != StringRef :: npos ) return getContext ( ) . getELFSection ( GV -> getSection ( ) , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } if ( isGlobalInSmallSection ( GV , TM ) ) return selectSmallSectionForGlobal ( GV , Kind , Mang , TM ) ; TRACE ( <STR_LIT> ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GV ,


<s> Type * GType = GVar -> getType ( ) ; if ( PointerType * PT = dyn_cast < PointerType > ( GType ) ) GType = PT -> getElementType ( ) ; if ( isa < ArrayType > ( GType ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StructType * ST = dyn_cast < StructType > ( GType ) ) { if ( ST -> isOpaque ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned Size = GVar -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( GType ) ; if ( Size == <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> )


<s> if ( Kind . isCommon ( ) ) { if ( NoSmallDataSorting ) return BSSSection ; Twine Name = Twine ( <STR_LIT> ) + getSectionSuffixForSize ( Size ) ; TRACE ( <STR_LIT> << Name << <STR_LIT> ) ; return getContext ( ) . getELFSection ( Name . str ( ) , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; } if ( Kind . isMergeableConst ( ) ) { TRACE ( <STR_LIT> ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; if ( GVar -> hasSection ( ) && isSmallDataSection ( GVar -> getSection ( ) ) ) Kind = SectionKind :: getData ( ) ; } if ( Kind . isData ( ) ) { if (


<s> if ( Kind . isBSS ( ) || Kind . isData ( ) || Kind . isCommon ( ) ) { Type * Ty = GV -> getType ( ) -> getElementType


<s> const <ISA_LIT>TargetLowering * getTLI ( )


<s> bool shouldMaximizeVectorBandwidth ( ) const { return


<s> if ( Ty -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT

. first + FloatFactor * getTypeNumElements ( Ty ) ;


<s> std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT . first + FloatFactor * getTypeNumElements ( Ty ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo


<s> unsigned <ISA_LIT>TTIImpl :: getCallInstrCost ( Function * F , Type * RetTy , ArrayRef


<s> std :: pair < int , MVT > DstLT = TLI . getTypeLegalizationCost ( DL , DstTy ) ; return std :: max ( SrcLT . first , DstLT . first ) + FloatFactor * (


<s> if ( ValTy -> isVectorTy ( ) ) { std :: pair < int , MVT > LT =

TLI . getTypeLegalizationCost ( DL , ValTy ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , Value * Ptr , bool VariableMask , unsigned Alignment ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr


<s> unsigned <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , Value * Ptr , bool VariableMask , unsigned Alignment ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask


<s> unsigned <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace ) { return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor ,


<s> return BaseT :: getMaskedMemoryOpCost ( Opcode , Src ,


<s> unsigned <ISA_LIT>TTIImpl :: getMaskedMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment ,


<s> unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; Alignment = std :: min ( Alignment , <NUM_LIT> ) ; unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; if ( Alignment == <NUM_LIT> || Alignment == <NUM_LIT> ) return Cost * NumLoads ; unsigned LogA = Log2_32 ( Alignment )


<s> Alignment = std :: min ( Alignment , RegWidth / <NUM_LIT> ) ; if ( VecWidth % RegWidth == <NUM_LIT> ) return VecWidth / RegWidth ; unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; Alignment = std :: min ( Alignment , <NUM_LIT> ) ; unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; if ( Alignment == <NUM_LIT> || Alignment ==


<s> auto isCastFoldedIntoLoad = [ this ] ( const CastInst * CI ) -> bool { if ( ! CI -> isIntegerCast ( ) ) return false ; const DataLayout & DL = getDataLayout ( ) ; unsigned SBW = DL . getTypeSizeInBits ( CI -> getSrcTy ( ) ) ; unsigned DBW = DL . getTypeSizeInBits ( CI -> getDestTy ( ) ) ; if ( DBW != <NUM_LIT> || SBW >= DBW ) return false ; const LoadInst * LI = dyn_cast < const LoadInst > ( CI -> getOperand ( <NUM_LIT> ) ) ; return LI && LI -> hasOneUse ( ) ; } ; if ( const CastInst * CI = dyn_cast < const CastInst > ( U ) ) if ( isCastFoldedIntoLoad ( CI ) ) return TargetTransformInfo :: TCC_Free ; return BaseT :: getUserCost ( U ,


<s> if ( ! CI -> isIntegerCast ( ) ) return false ; const DataLayout & DL = getDataLayout ( ) ; unsigned SBW = DL . getTypeSizeInBits ( CI -> getSrcTy ( ) ) ; unsigned DBW = DL . getTypeSizeInBits ( CI -> getDestTy ( ) ) ; if ( DBW != <NUM_LIT> || SBW >= DBW ) return false ; const LoadInst * LI = dyn_cast < const LoadInst > ( CI -> getOperand ( <NUM_LIT> ) ) ; return LI && LI ->


<s> EVT VecVT = EVT :: getEVT ( VecTy ) ; if ( ! VecVT . isSimple ( ) || VecVT . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ST . isHVXVectorType ( VecVT . getSimpleVT ( ) ) ) return true ; auto Action = TLI . getPreferredVectorAction


<s> unsigned <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info ,


<s> return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info ,


<s> assert ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) ; if ( Opcode == Instruction :: Store ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , I ) ; if ( Src -> isVectorTy ( ) ) { VectorType * VecTy = cast < VectorType > ( Src ) ; unsigned VecWidth = VecTy -> getBitWidth ( ) ; if ( useHVX ( ) && isTypeForHVX ( VecTy ) ) { unsigned RegWidth = getRegisterBitWidth ( true ) ; Alignment = std :: min ( Alignment


<s> bool shouldMaximizeVectorBandwidth ( TargetTransformInfo :: RegisterKind K ) const { return true


<s> unsigned getCFInstrCost ( unsigned Opcode , TTI :: TargetCostKind CostKind ) { return <NUM_LIT>


<s> unsigned <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace , bool UseMaskForCond , bool UseMaskForGaps ) { if ( Indices . size ( ) != Factor || UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ; return getMemoryOpCost ( Opcode , VecTy , Alignment , AddressSpace , nullptr


<s> if ( Indices . size ( ) != Factor || UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost (

Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ;


<s> if ( ST . isHVXVectorType ( VecVT . getSimpleVT ( ) ) ) return true ; auto Action = TLI . getPreferredVectorAction ( VecVT . getSimpleVT ( ) ) ; return Action == TargetLoweringBase :: TypeWidenVector


<s> EVT VecVT = EVT :: getEVT ( VecTy ) ; if ( ! VecVT . isSimple ( ) || VecVT . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ST . isHVXVectorType ( VecVT . getSimpleVT ( ) ) ) return true ; auto Action = TLI . getPreferredVectorAction ( VecVT . getSimpleVT ( ) ) ; return Action == TargetLoweringBase ::


<s> unsigned <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( ValTy -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost


<s> unsigned VecWidth = VecTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) ; if ( useHVX ( ) && isTypeForHVX ( VecTy ) ) { unsigned RegWidth = getRegisterBitWidth ( true ) ; assert ( RegWidth && <STR_LIT> ) ; if ( VecWidth % RegWidth == <NUM_LIT> ) return VecWidth / RegWidth ; const Align RegAlign ( RegWidth / <NUM_LIT> ) ; if ( ! Alignment || * Alignment > RegAlign ) Alignment = RegAlign ; assert ( Alignment ) ; unsigned AlignWidth = <NUM_LIT> * Alignment -> value ( ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; const Align BoundAlignment = std :: min ( Alignment . valueOrOne ( ) , Align ( <NUM_LIT> ) ) ; unsigned AlignWidth = <NUM_LIT> * BoundAlignment . value ( ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth


<s> unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; Alignment = std :: min ( Alignment , <NUM_LIT> ) ; unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; if ( Alignment == <NUM_LIT> || Alignment == <NUM_LIT> )


<s> if ( cast < VectorType > ( VecTy ) -> isScalable ( ) ) return false ; if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT VecVT = EVT :: getEVT ( VecTy ) ; if ( ! VecVT . isSimple ( ) || VecVT . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ST . isHVXVectorType ( VecVT . getSimpleVT ( ) ) ) return true ; auto Action = TLI . getPreferredVectorAction ( VecVT . getSimpleVT ( ) ) ; return Action ==


<s> InstructionCost <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Tp , ScalarEvolution * SE , const


<s> if ( SrcTy -> isFPOrFPVectorTy ( ) || DstTy -> isFPOrFPVectorTy ( ) ) { unsigned SrcN = SrcTy -> isFPOrFPVectorTy ( ) ? getTypeNumElements ( SrcTy ) : <NUM_LIT> ; unsigned DstN = DstTy -> isFPOrFPVectorTy ( ) ? getTypeNumElements ( DstTy ) : <NUM_LIT> ; std :: pair < InstructionCost , MVT > SrcLT = TLI . getTypeLegalizationCost ( DL , SrcTy ) ; std :: pair < InstructionCost , MVT > DstLT = TLI . getTypeLegalizationCost (


<s> unsigned SrcN = SrcTy -> isFPOrFPVectorTy ( ) ? getTypeNumElements ( SrcTy ) : <NUM_LIT> ; unsigned DstN = DstTy -> isFPOrFPVectorTy ( ) ? getTypeNumElements ( DstTy ) : <NUM_LIT> ; std :: pair < InstructionCost , MVT > SrcLT = TLI . getTypeLegalizationCost ( DL , SrcTy ) ; std :: pair < InstructionCost , MVT > DstLT = TLI . getTypeLegalizationCost ( DL , DstTy ) ; InstructionCost Cost = std :: max ( SrcLT . first , DstLT . first )


<s> std :: pair < InstructionCost , MVT > LT = TLI . getTypeLegalizationCost ( DL , ValTy ) ; if ( Opcode == Instruction :: FCmp ) return LT . first + FloatFactor * getTypeNumElements (


<s> std :: pair < InstructionCost , MVT > LT = TLI . getTypeLegalizationCost ( DL , ValTy ) ; if ( Opcode == Instruction :: FCmp ) return LT . first + FloatFactor


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr ,

bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) {


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind


<s> if ( Indices . size ( ) != Factor || UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace

, CostKind , UseMaskForCond , UseMaskForGaps ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ICA . getID ( ) == <STR_LIT> ) { std :: pair < InstructionCost , MVT > LT = TLI . getTypeLegalizationCost ( DL , ICA . getReturnType ( ) ) ; return LT . first + <NUM_LIT> ; } return BaseT :: getIntrinsicInstrCost ( ICA


<s> InstructionCost <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { if ( ICA . getID ( ) == <STR_LIT> ) { std :: pair < InstructionCost , MVT > LT = TLI . getTypeLegalizationCost ( DL , ICA . getReturnType


<s> return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment ,


<s> unsigned <ISA_LIT>TTIImpl :: getMaxInterleaveFactor (


<s> if ( VecWidth % RegWidth == <NUM_LIT> ) return VecWidth / RegWidth ; const Align RegAlign ( RegWidth / <NUM_LIT> ) ; if ( ! Alignment || * Alignment > RegAlign ) Alignment = RegAlign ; assert ( Alignment ) ; unsigned AlignWidth = <NUM_LIT> * Alignment -> value ( ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; const Align BoundAlignment = std :: min ( Alignment . valueOrOne ( ) , Align ( <NUM_LIT> ) ) ; unsigned AlignWidth = <NUM_LIT> * BoundAlignment . value ( ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth )


<s> ElementCount <ISA_LIT>TTIImpl :: getMinimumVF ( unsigned ElemWidth , bool IsScalable


<s> assert ( ! IsScalable && <STR_LIT> ) ; return ElementCount :: getFixed ( ( <NUM_LIT> * ST .


<s> BaseT :: getPeelingPreferences ( L , SE , PP ) ; if ( L && L -> isInnermost ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) >

<NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) <= <NUM_LIT> ) {


<s> return TypeSize :: getFixed ( <NUM_LIT> ) ; case TargetTransformInfo :: RGK_FixedWidthVector : return TypeSize :: getFixed ( getMinVectorRegisterBitWidth ( ) ) ; case TargetTransformInfo :: RGK_ScalableVector : return TypeSize :: getScalable ( <NUM_LIT>


<s> return BaseT :: getScalarizationOverhead ( Ty , DemandedElts ,


<s> return BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert ,


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { UP . Runtime = UP . Partial


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI ::

UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) {


<s> unsigned SBW = DL . getTypeSizeInBits ( CI -> getSrcTy ( ) ) ; unsigned DBW = DL . getTypeSizeInBits ( CI -> getDestTy ( ) ) ; if ( DBW != <NUM_LIT> || SBW >= DBW ) return false ; const LoadInst * LI = dyn_cast < const LoadInst >


<s> Type * ElemTy = Val -> isVectorTy ( ) ? cast < VectorType > ( Val ) -> getElementType ( ) : Val ; if ( Opcode == Instruction :: InsertElement ) { unsigned Cost = ( Index != <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( ElemTy -> isIntegerTy ( <NUM_LIT> ) ) return Cost ; return Cost + getVectorInstrCost ( Instruction :: ExtractElement , Val , Index ) ; } if ( Opcode == Instruction ::


<s> std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , ValTy ) ; if ( Opcode == Instruction :: FCmp ) return LT . first + FloatFactor * getTypeNumElements ( ValTy ) ; } return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind


<s> unsigned <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , CmpInst :: Predicate VecPred , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( ValTy -> isVectorTy ( ) && CostKind == TTI :: TCK_RecipThroughput ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL


<s> unsigned <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind ,


<s> if ( Indices . size ( ) != Factor || UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; return getMemoryOpCost ( Opcode , VecTy , MaybeAlign

( Alignment ) , AddressSpace , CostKind ) ;


<s> VectorType * VecTy = cast < VectorType > ( Src ) ; unsigned VecWidth = VecTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) ; if ( useHVX ( ) && ST . isTypeForHVX ( VecTy ) ) { unsigned RegWidth = getRegisterBitWidth ( true ) ; assert ( RegWidth && <STR_LIT> ) ; if ( VecWidth % RegWidth == <NUM_LIT> ) return VecWidth / RegWidth ; const Align RegAlign ( RegWidth / <NUM_LIT> ) ; if ( ! Alignment || * Alignment > RegAlign ) Alignment = RegAlign ; assert ( Alignment ) ; unsigned AlignWidth = <NUM_LIT> * Alignment -> value ( ) ; unsigned NumLoads = alignTo ( VecWidth ,


<s> bool enableAggressiveInterleaving ( bool LoopHasReductions ) { return false


<s> bool enableInterleavedAccessVectorization (


<s> unsigned <ISA_LIT>TTIImpl :: getCacheLineSize ( ) const { return getST ( ) -> getL1CacheLineSize


<s> return getST ( ) -> getL1CacheLineSize (


<s> unsigned getCFInstrCost ( unsigned Opcode


<s> unsigned <ISA_LIT>TTIImpl :: getNumberOfRegisters ( bool vector ) const { return vector ? <NUM_LIT> : <NUM_LIT>


<s> return getST ( ) -> getL1PrefetchDistance (


<s> return getST ( ) -> getL1PrefetchDistance


<s> const <ISA_LIT>TargetLowering * getTLI ( ) const { return & TLI


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , TTI ::


<s> bool shouldMaximizeVectorBandwidth ( bool


<s> unsigned getAddressComputationCost ( Type * Tp , ScalarEvolution * , const SCEV * ) { return


<s> unsigned getCallInstrCost ( Function * F , Type * RetTy , ArrayRef <


<s> unsigned getCallInstrCost ( Function * F , Type * RetTy , ArrayRef < Type * > Tys ) { return <NUM_LIT>


<s> unsigned getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src , const Instruction * I = nullptr ) { return <NUM_LIT>


<s> return BaseT :: getCmpSelInstrCost ( Opcode , ValTy ,


<s> unsigned getCmpSelInstrCost ( unsigned Opcode , Type * ValTy ,

Type * CondTy , const Instruction * I ) {


<s> unsigned getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , Value * Ptr ,

bool VariableMask , unsigned Alignment ) {


<s> unsigned getMaskedMemoryOpCost ( unsigned Opcode , Type * Src ,

unsigned Alignment , unsigned AddressSpace ) {


<s> unsigned getMaskedMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) { return <NUM_LIT>


<s> unsigned getScalarizationOverhead ( Type * Ty , bool Insert , bool Extract ) { return


<s> unsigned getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { return <NUM_LIT>


<s> unsigned getVectorInstrCost ( unsigned Opcode , Type * Val , unsigned Index ) { return


<s> if ( L && L -> empty ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) > <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) <= <NUM_LIT> ) { PP . PeelCount =


<s> if ( Indices . size ( ) != Factor || UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment ,

AddressSpace , UseMaskForCond , UseMaskForGaps ) ;