<s> unsigned push ( unsigned Opc , MVT Ty , std :: vector < OpRef > && Ops ) { NodeTemplate Res ; Res . Opc = Opc ; Res . Ty = Ty ; Res . Ops


<s> unsigned reset ( unsigned NewTop ) { List . resize ( NewTop


<s> List . resize ( NewTop + <NUM_LIT> ) ; return NewTop


<s> const Coloring :: MapType & M = G . colors ( ) ; if ( M . empty ( ) ) return false ; ElemType Num = Size ; unsigned Pets = <NUM_LIT> * Log - <NUM_LIT> - Step ; bool UseUp = false , UseDown = false ; ColorKind ColorUp = ColorKind :: None ; for ( ElemType J = <NUM_LIT> ; J != Num ; ++ J ) { ElemType I = P [ J ] ; if ( I == Ignore ) continue ; ColorKind C = M . at ( I ) ; if ( C == ColorKind :: None ) continue ; if ( ColorUp == ColorKind :: None ) { ColorUp = ( I < Num / <NUM_LIT> ) ? ColorKind :: Red : ColorKind :: Black ; } unsigned CI = ( I < Num / <NUM_LIT> ) ? I + Num / <NUM_LIT> : I - Num / <NUM_LIT> ; if ( C ==


<s> bool BenesNetwork :: route ( ElemType * P , RowType * T , unsigned Size , unsigned Step ) { Coloring G ( { P , Size } ) ; const Coloring :: MapType & M = G . colors ( ) ; if ( M . empty ( ) ) return false ; ElemType Num = Size ; unsigned Pets = <NUM_LIT> * Log - <NUM_LIT> - Step ; bool UseUp = false , UseDown = false ; ColorKind ColorUp = ColorKind :: None ; for ( ElemType J = <NUM_LIT> ; J != Num ; ++ J ) { ElemType I = P [ J ] ; if ( I == Ignore ) continue ; ColorKind C = M . at ( I ) ; if ( C == ColorKind :: None ) continue ; if ( ColorUp == ColorKind :: None ) { ColorUp = ( I < Num / <NUM_LIT> ) ? ColorKind :: Red : ColorKind :: Black ; } unsigned CI = ( I < Num / <NUM_LIT> ) ? I + Num / <NUM_LIT> : I - Num / <NUM_LIT> ; if ( C == ColorUp ) { if ( I < Num / <NUM_LIT> ) T [ I ] [ Step ] = Pass ; else T [ CI ] [ Step ] = Switch ; T [ J ] [ Pets ] = ( J < Num / <NUM_LIT> ) ? Pass : Switch ; UseUp = true ; } else { if ( I < Num / <NUM_LIT> ) T [ CI ]


<s> bool run ( Controls & F , Controls & R ) { if ( ! route ( Order . data ( ) , Table . data ( ) , size ( ) , <NUM_LIT> ) ) return false ; getControls ( F , <NUM_LIT> , Forward ) ; getControls ( R , Log , Reverse )


<s> if ( HavePairs ) { if ( M < HwLen ) { Vec = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , SingleTy , Vec ) ; } else { Vec = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , SingleTy , Vec ) ; M -= HwLen ; } } SDValue Idx = DAG . getConstant ( M , dl , <STR_LIT> ) ; SDValue Ex = DAG . getNode ( <STR_LIT> , dl , ElemTy , { Vec , Idx } ) ; SDValue L = Lower . LowerOperation ( Ex , DAG ) ; assert ( L . getNode ( ) ) ; Ops . push_back ( L ) ; } SDValue LV ; if ( <NUM_LIT> * HwLen == VecLen ) { SDValue B0 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) , HwLen } ) ; SDValue L0 = Lower . LowerOperation ( B0 , DAG ) ; SDValue B1 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) + HwLen , HwLen } ) ; SDValue L1 = Lower . LowerOperation ( B1 , DAG ) ; LV = DAG . getNode ( <STR_LIT> , dl , ResTy , { L0 , L1 } ) ; } else { SDValue BV = DAG . getBuildVector ( ResTy , dl , Ops ) ; LV = Lower . LowerOperation ( BV , DAG ) ; } assert ( ! N -> use_empty ( ) ) ; ISel . ReplaceNode ( N , LV . getNode ( ) ) ; DAG . RemoveDeadNodes ( ) ; std :: deque < SDNode *


<s> unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDNode * Result ; switch ( IID ) { case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT>


<s> SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } ReplaceUses ( N , Result ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Result ,


<s> HvxSelector ( * this , * CurDAG ) . selectRor (


<s> HvxSelector ( * this , * CurDAG ) . selectShuffle (


<s> void <ISA_LIT>DAGToDAGISel :: SelectHvxVAlign (


<s> void <ISA_LIT>DAGToDAGISel :: SelectHvxVAlign ( SDNode * N ) { HvxSelector ( * this , * CurDAG ) . selectVAlign ( N


<s> SDValue VecV = N -> getOperand ( <NUM_LIT> ) ; SDValue RotV = N -> getOperand ( <NUM_LIT> ) ; SDNode * NewN = nullptr ; if ( auto * CN = dyn_cast < ConstantSDNode > ( RotV . getNode ( ) ) ) { unsigned S = CN -> getZExtValue ( ) % HST . getVectorLength ( ) ; if ( S


<s> } DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << <STR_LIT> << VecLen << <STR_LIT> << HwLen << <STR_LIT> << UseLeft << <STR_LIT> << UseRight << <STR_LIT> << HavePairs << '\n' ; } ) ; if ( ! UseLeft && ! UseRight ) { ISel . ReplaceNode ( N , ISel . selectUndef ( SDLoc ( SN ) , ResTy ) . getNode ( ) ) ; return ; } SDValue Vec0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Vec1 = N -> getOperand ( <NUM_LIT> ) ; ResultStack Results ( SN ) ; Results . push ( TargetOpcode :: COPY , ResTy , { Vec0 } ) ; Results . push ( TargetOpcode :: COPY , ResTy , { Vec1 } ) ; OpRef Va = OpRef :: res ( Results . top ( ) - <NUM_LIT> ) ; OpRef Vb = OpRef :: res ( Results . top ( ) ) ; OpRef Res = ! HavePairs ? shuffs2 ( ShuffleMask ( Mask ) , Va , Vb , Results ) : shuffp2 ( ShuffleMask ( Mask ) , Va , Vb , Results ) ; bool Done = Res .


<s> unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceNode ( N , Result


<s> const SDLoc & dl ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Address = N -> getOperand ( <NUM_LIT> ) ; SDValue Predicate = N -> getOperand ( <NUM_LIT> ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Modifier = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode ; unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , Predicate , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs (


<s> void HvxSelector :: selectVAlign ( SDNode * N ) { SDValue Vv = N -> getOperand ( <NUM_LIT> ) ; SDValue Vu = N -> getOperand


<s> SDValue Rt = N -> getOperand ( <NUM_LIT> ) ; SDNode * NewN = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType


<s> OpRef L = shuffp1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffp1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++


<s> OpRef HvxSelector :: shuffp2 ( ShuffleMask SM , OpRef Va , OpRef Vb , ResultStack & Results ) { DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << __func__ << '\n' ; } ) ; if ( isUndef ( SM . Mask ) ) return OpRef :: undef ( getPairVT ( <STR_LIT> ) ) ; int VecLen = SM . Mask . size ( ) ; SmallVector < int , <NUM_LIT> > PackedMask ( VecLen ) ; OpRef P = packp ( SM , Va , Vb , Results , PackedMask ) ; if ( P . isValid ( ) ) return shuffp1 ( ShuffleMask ( PackedMask ) , P , Results ) ; SmallVector < int , <NUM_LIT> > MaskL ( VecLen ) , MaskR ( VecLen ) ; splitMask ( SM . Mask , MaskL , MaskR ) ; OpRef L = shuffp1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffp1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen


<s> DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << __func__ << '\n' ; } ) ; unsigned VecLen = SM . Mask . size ( ) ; assert ( HwLen == VecLen ) ; ( void ) VecLen ; assert ( all_of ( SM . Mask , [ this ] ( int M ) { return M == - <NUM_LIT> || M < int ( HwLen ) ; } ) ) ; if ( isIdentity ( SM . Mask ) ) return Va ; if ( isUndef ( SM . Mask ) ) return OpRef :: undef ( getSingleVT ( <STR_LIT> ) ) ; OpRef P = perfect ( SM , Va , Results ) ; if ( P . isValid ( )


<s> OpRef C = contracting ( SM , Va , Vb , Results ) ; if ( C . isValid ( ) ) return C ; int VecLen = SM . Mask . size ( ) ; SmallVector < int , <NUM_LIT> > NewMask ( VecLen ) ; OpRef P = packs ( SM , Va , Vb , Results , NewMask ) ; if ( P . isValid ( ) ) return shuffs1 ( ShuffleMask ( NewMask ) , P , Results ) ; SmallVector < int , <NUM_LIT> > MaskL ( VecLen ) , MaskR ( VecLen ) ; splitMask ( SM . Mask , MaskL , MaskR ) ; OpRef L = shuffs1 ( ShuffleMask ( MaskL ) , Va , Results ) ; OpRef R = shuffs1 ( ShuffleMask ( MaskR ) , Vb , Results ) ; if ( ! L . isValid ( ) || ! R . isValid ( ) ) return OpRef :: fail ( ) ; SmallVector < uint8_t , <NUM_LIT> > Bytes ( VecLen ) ; for ( int I = <NUM_LIT> ; I != VecLen ; ++ I ) { if ( MaskL [ I ] != - <NUM_LIT> ) Bytes [ I ] = <NUM_LIT> ; } return vmuxs ( Bytes , L , R


<s> unsigned top ( ) const { return size ( )


<s> return OpRef ( Undef | Ty . SimpleTy


<s> bool ComplexPatternFuncMutatesDAG ( ) const override { return true


<s> FunctionPass * create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ! HFI . needsAligna ( * MF ) ) return ; MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; MachineBasicBlock * EntryBB = MF -> begin ( ) ; unsigned AR = FuncInfo -> CreateReg ( <STR_LIT> ) ; unsigned MaxA = MFI -> getMaxAlignment ( ) ; auto & HII = * HST . getInstrInfo ( ) ; BuildMI ( EntryBB , DebugLoc ( ) , HII . get ( <STR_LIT> ) , AR ) . addImm ( MaxA ) ; MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setStackAlignBaseVReg ( AR


<s> static void initializePassOnce ( PassRegistry & Registry ) { const char * Name =


<s> HRI = HST -> getRegisterInfo ( ) ; SelectionDAGISel :: runOnMachineFunction


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { HST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST -> getInstrInfo (


<s> case <STR_LIT> : return SelectConstantFP ( N ) ; case <STR_LIT> : return SelectFrameIndex ( N ) ; case <STR_LIT> : return SelectAdd ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectMul ( N ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SelectBitOp ( N ) ; case <STR_LIT> : return SelectZeroExtend ( N ) ; case <STR_LIT>


<s> if ( Src1 -> getOpcode ( ) != <STR_LIT> || ! Src1 -> hasOneUse ( ) || Src1 -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) ) ; ReplaceUses ( N , Result ) ; return


<s> SDNode * Src1 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( Src1 -> getOpcode ( ) != <STR_LIT> || ! Src1 -> hasOneUse ( ) || Src1 -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Src1

-> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) ) ;


<s> auto & HFI = * HST -> getFrameLowering ( ) ; MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; int FX = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; if ( ! MFI -> isFixedObjectIndex ( FX ) && HFI . needsAligna


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAddrGP ( SDValue & N , SDValue & R ) { return SelectGlobalAddress ( N , R


<s> unsigned MaxA = MFI -> getMaxAlignment ( ) ; SDValue FI = CurDAG -> getTargetFrameIndex ( FX , <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * R = <NUM_LIT> ; if ( FX < <NUM_LIT> || MaxA <= StkA || ! MFI -> hasVarSizedObjects ( ) ) { R = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , FI , Zero ) ; } else { auto & HMFI = * MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned AR = HMFI . getStackAlignBaseVReg ( ) ; SDValue CH = CurDAG -> getEntryNode ( ) ; SDValue Ops [ ] = { CurDAG -> getCopyFromReg ( CH , DL , AR , <STR_LIT> ) , FI , Zero } ; R = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT>


<s> SDValue N0 = N . getOperand ( <NUM_LIT> ) ; SDValue N1 = N . getOperand ( <NUM_LIT> ) ; unsigned GAOpc = N0 . getOpcode ( ) ; if ( UseGP && GAOpc != <STR_LIT> ) return false ; if ( ! UseGP && GAOpc != <STR_LIT> ) return false ; if ( ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( N1 ) ) { SDValue Addr = N0 . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Addr ) ) { if ( GA -> getOpcode ( ) == <STR_LIT> ) { uint64_t NewOff = GA -> getOffset ( ) + ( uint64_t ) Const -> getSExtValue ( ) ; R = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Const ) , N . getValueType ( ) , NewOff ) ; return true ; } } } break ; } case <STR_LIT> : if ( ! UseGP ) R = N . getOperand ( <NUM_LIT> ) ; return ! UseGP ; case <STR_LIT> : if ( UseGP ) R = N . getOperand ( <NUM_LIT> ) ; return UseGP ; default : return false


<s> if ( ! UseGP && GAOpc != <STR_LIT> ) return false ; if ( ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( N1 ) ) { SDValue Addr = N0 . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Addr ) ) { if ( GA -> getOpcode ( ) == <STR_LIT> ) { uint64_t NewOff = GA -> getOffset ( ) + ( uint64_t ) Const -> getSExtValue ( ) ; R = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Const ) , N . getValueType ( ) , NewOff ) ; return true ; } } } break ; } case <STR_LIT> : if ( ! UseGP ) R = N . getOperand ( <NUM_LIT>


<s> cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3


<s> SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2


<s> cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( ST , Result ) ; ReplaceUses ( SDValue ( ST , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; return Result ; } SDValue Ops [ ] = { Base , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Value , Chain } ; unsigned Opcode = <NUM_LIT> ; if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( SDValue ( ST , <NUM_LIT> ) , SDValue ( Result_2 , <NUM_LIT>


<s> Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; default : return SelectCode ( N ) ; } SDValue const & V = N -> getOperand ( <NUM_LIT> ) ; SDValue U ; if ( isValueExtension ( V , Bits , U ) ) { SDValue R = CurDAG -> getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , U ) ; return SelectCode ( R . getNode ( )


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectLoad ( SDNode * N ) { SDNode * result ; SDLoc dl ( N ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectLoad ( SDNode * N ) { SDNode * result ; SDLoc dl ( N ) ; LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM != <STR_LIT>


<s> SDLoc dl ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue MulOp0 = N -> getOperand ( <NUM_LIT> ) ; SDValue MulOp1 = N -> getOperand ( <NUM_LIT> ) ; SDValue OP0 ; SDValue OP1 ; if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext0 = MulOp0 . getOperand ( <NUM_LIT> ) ; if ( Sext0 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP0 = Sext0 ; } else if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp0 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; OP0 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand ( <NUM_LIT> ) ; if ( Sext1 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP1 = Sext1 ; } else if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp1 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectStore ( SDNode * N ) { SDLoc dl ( N ) ; StoreSDNode * ST = cast < StoreSDNode > ( N


<s> SDNode * U = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF ,


<s> SDValue Ones = CurDAG -> getTargetConstant ( MV , dl , <STR_LIT> ) ; SDNode * OnesReg = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ones ) ; if ( ExVT . getSizeInBits ( ) == <NUM_LIT> ) { SDNode * And = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ; SDValue SubR = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( And , <NUM_LIT> ) , SubR ) ; } return CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ; } SDNode * IsIntrinsic = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( IsIntrinsic -> getOpcode ( ) == <STR_LIT> ) ) { unsigned ID = cast < ConstantSDNode > ( IsIntrinsic -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( doesIntrinsicReturnPredicate ( ID ) ) { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceUses ( N , Result_3 ) ; return Result_3 ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDNode * RsPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic


<s> inline SDValue XformM5ToU5Imm ( signed Imm , SDLoc DL ) { assert ( ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT>


<s> return XformMskToBitPosU5Imm ( Imm ,


<s> SDValue XformMskToBitPosU5Imm ( uint32_t Imm , SDLoc DL ) { int32_t bitPos ; bitPos = Log2_32 ( Imm ) ; assert ( bitPos >= <NUM_LIT> && bitPos < <NUM_LIT>


<s> return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL ,


<s> return CurDAG -> getTargetConstant ( Imm - <NUM_LIT>


<s> assert ( ( Imm >= <NUM_LIT> ) && <STR_LIT> ) ; return CurDAG -> getTargetConstant ( Imm - <NUM_LIT>


<s> if ( Fast ) * Fast = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT>


<s> for ( unsigned i = <NUM_LIT> ; i < NumVectorElements / <NUM_LIT> ; ++ i ) { uint8_t x = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { uint8_t y = CV -> getOperand ( i * <NUM_LIT> + j ) -> getUniqueInteger ( ) . getZExtValue ( ) ; x |= y << ( <NUM_LIT>


<s> MVT VecTy = ty ( VecV ) ; assert ( ! ValTy . isVector ( ) || VecTy . getVectorElementType ( ) == ValTy . getVectorElementType ( ) ) ; unsigned VecWidth = VecTy . getSizeInBits ( ) ; unsigned ValWidth = ValTy . getSizeInBits ( ) ; unsigned ElemWidth = VecTy . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; assert ( ( VecWidth % ElemWidth ) == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode


<s> Consts [ i ] = ConstantInt :: get ( IntTy , <NUM_LIT> ) ; continue ; } if ( auto * CN = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) { const ConstantInt * CI = CN -> getConstantIntValue ( ) ; Consts [ i ] = const_cast < ConstantInt * > ( CI ) ; } else if ( auto * CN = dyn_cast < ConstantFPSDNode > ( V . getNode ( ) ) ) { const ConstantFP * CF = CN -> getConstantFPValue (


<s> const uint32_t * Mask = HRI . getCallPreservedMask ( MF , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; SDValue Ops [ ] = { Chain , TGA , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getRegisterMask ( Mask ) , Glue } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ; MFI . setAdjustsStack


<s> auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; bool ValidHVX128BType = HST . useHVX128BOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ; bool ValidHVXType = HST . useHVX64BOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ; if ( ValidHVX128BType || ValidHVXType || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { IsInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; return isa < ConstantSDNode > ( Offset ) ; } return


<s> auto Aligned = [ ] ( unsigned GivenA , unsigned MinA ) -> bool { return ( GivenA % MinA ) == <NUM_LIT> ; } ; if ( Size >= <NUM_LIT> && Aligned ( DstAlign , <NUM_LIT> ) && ( IsMemset || Aligned ( SrcAlign , <NUM_LIT>


<s> bool <ISA_LIT>TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > (


<s> case <STR_LIT> : case <STR_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; } break ; case 'a' : if ( VT != <STR_LIT> ) return { <NUM_LIT> , nullptr } ; return { <NUM_LIT> , & <STR_LIT> } ; case 'q' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; } break ; case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return { <NUM_LIT> , nullptr } ; case <NUM_LIT> : return { <NUM_LIT> , & <STR_LIT> } ; case <NUM_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVX128BOps ( ) ) return { <NUM_LIT> , & <STR_LIT> } ; return { <NUM_LIT> , & <STR_LIT> } ; case <NUM_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = <STR_LIT> ; Type * VecTy = I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; Info . memVT = <STR_LIT> ( VecTy ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; } return false


<s> if ( Ty . isVector ( ) ) { assert ( Ty . isInteger ( ) && <STR_LIT> ) ; unsigned W = Ty . getSizeInBits ( ) ; if ( W <= <NUM_LIT> ) return DAG . getBitcast ( Ty , DAG . getConstant (


<s> unsigned W = Ty . getSizeInBits ( ) ; if ( W <= <NUM_LIT> ) return DAG . getBitcast ( Ty , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ( W ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , Ty ) ; } if ( Ty . isInteger ( ) ) return DAG . getConstant ( <NUM_LIT> , dl , Ty ) ; if ( Ty . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , dl , Ty ) ; llvm_unreachable ( <STR_LIT> )


<s> if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs >> Log2_32 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ; default : return false ; } return true


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { return true


<s> const SDLoc & dl ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( BW == <NUM_LIT> ) return buildVector32 ( Ops , dl ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; Chain = TPR . getValue ( <NUM_LIT> ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ; Glue = RetVal . getValue ( <NUM_LIT> ) ; Chain = RetVal . getValue


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; Chain = TPR . getValue (


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VecTy , Op . getOperand ( <NUM_LIT> ) , Op .


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { EVT ValTy = Op . getValueType ( ) ; ConstantPoolSDNode * CPN = cast < ConstantPoolSDNode > ( Op ) ; Constant * CVal = nullptr ; bool isVTi1Type = false ; if ( const Constant * ConstVal = dyn_cast < Constant > ( CPN -> getConstVal ( ) ) ) { Type * CValTy = ConstVal -> getType ( ) ; if ( CValTy -> isVectorTy ( ) && CValTy -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CVal = convert_i1_to_i8 ( ConstVal ) ; isVTi1Type = ( CVal != nullptr ) ; } } unsigned Align = CPN -> getAlignment ( ) ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned char TF = IsPositionIndependent ? <STR_LIT> :


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg ,


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( )


<s> const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && HLOF . isGlobalInSmallSection ( GO , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } bool UsePCRel = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Off = DAG . getConstant ( Offset , dl


<s> if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Mem : i += NumVals ; break ; case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegDefEarlyClobber : { for ( ; NumVals ; -- NumVals , ++ i ) { unsigned Reg = cast < RegisterSDNode > ( Op . getOperand ( i )


<s> MVT VecTy = ty ( Op ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy ) ) return LowerHvxInsertElement (


<s> case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG


<s> case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerREADCYCLECOUNTER ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerREADCYCLECOUNTER ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> ,


<s> return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( HRI . getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( )


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( HRI . getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode (


<s> return SC ; } if ( VT . isVector ( ) ) return Op ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && ( RHSVT == <STR_LIT> || RHSVT == <STR_LIT> ) && ( LHSVT == <STR_LIT> || LHSVT == <STR_LIT> ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( C && C -> getAPIntValue ( ) . isNegative ( ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ; } if ( isSExtFree ( LHS ) || isSExtFree ( RHS ) ) { LHS = DAG . getNode ( <STR_LIT> , dl ,


<s> SDValue Chain = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; SDValue InFlag ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; unsigned Flags = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( )

) . useLongCalls ( ) ? <STR_LIT> | <STR_LIT> : <STR_LIT> ;


<s> SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( Sym , DAG ) ; Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; } SDValue LoadOffset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Sym , MachinePointerInfo ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TP ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex


<s> if ( V2 . isUndef ( ) ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) ) ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! V1 . getOperand ( i ) . isUndef (


<s> auto Attr = CI -> getParent ( ) -> getParent ( ) ->


<s> auto & MF = State . getMachineFunction ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const uint16_t RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo ,


<s> } else if ( LocVT == <STR_LIT> ) { unsigned Req = HST . useHVX128BOps ( ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if ( LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return


<s> } } else if ( LocVT == <STR_LIT> ) { unsigned Req = HST . useHVX128BOps ( ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if (


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } return true


<s> static bool CC_<ISA_LIT>32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false


<s> State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } static const MCPhysReg RegList1 [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false


<s> if ( ( int ) ValNo < HState . getNumNamedVarArgParams ( ) ) { return CC_<ISA_LIT> ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; } unsigned ofst ; if ( ArgFlags . isByVal ( ) ) { assert ( ( ArgFlags . getByValSize ( ) > <NUM_LIT> ) && <STR_LIT> ) ; ofst = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } llvm_unreachable ( nullptr )


<s> } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } llvm_unreachable ( nullptr )


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false ,

false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> case <STR_LIT> : { MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( MI ) ; return BB


<s> isInc = ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; Offset = Ptr -> getOperand ( <NUM_LIT> ) ; return ( isa < ConstantSDNode > (


<s> bool <ISA_LIT>TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , SelectionDAG & DAG ) const { const Function * CallerF = DAG .

getMachineFunction ( ) . getFunction ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return Subtarget -> hasV5TOps (


<s> if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) { return false


<s> } return ( ( VT1 . getSimpleVT ( ) == <STR_LIT> ) && ( VT2 . getSimpleVT ( )


<s> ConstantSDNode * N = cast < ConstantSDNode > ( S ) ; int64_t v = ( int64_t ) N -> getSExtValue ( ) ; int64_t m = <NUM_LIT> ; if ( ShiftAmount > <NUM_LIT> ) { m = v % ShiftAmount ; v = v >> ShiftAmount ; } return ( v <= <NUM_LIT> ) && ( v >= -


<s> int64_t v = ( int64_t ) N -> getSExtValue ( ) ; int64_t m = <NUM_LIT> ; if ( ShiftAmount > <NUM_LIT> ) { m = v % ShiftAmount ; v = v


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue BA_SD = DAG . getTargetBlockAddress ( BA


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const BlockAddress * BA = cast < BlockAddressSDNode > (


<s> SDLoc dl ( Op ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; unsigned JTI = JT -> getIndex ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , <STR_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JTE = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JTE [ JTI ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; MBB -> setHasAddressTaken ( ) ; BlockAddress :: get ( const_cast < BasicBlock * > ( MBB -> getBasicBlock ( ) ) ) ; } SDValue JumpTableBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , TargetJT ) ; SDValue ShiftIndex = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue JTAddress = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JumpTableBase , ShiftIndex ) ; SDValue LoadTarget = DAG . getLoad ( <STR_LIT> , dl , Chain , JTAddress , MachinePointerInfo ( ) , false ,


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ;


<s> ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , ValTy , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , ValTy ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue StackPointer = DAG . getCopyFromReg ( Chain , dl , SPReg , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; const <ISA_LIT>RegisterInfo * QRI = Subtarget -> getRegisterInfo ( ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , QRI -> getStackRegister (


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; const <ISA_LIT>RegisterInfo * QRI = Subtarget -> getRegisterInfo ( ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , QRI -> getStackRegister ( ) , Sub ) ; SDValue Ops [ <NUM_LIT> ] = { ArgAdjust , CopyChain


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( ) ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg ,


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; unsigned ObjSize ; unsigned StackLocation ; int FI ; if ( ( VA . isRegLoc ( ) && ! Flags . isByVal ( ) ) || ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) > <NUM_LIT> ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg ,


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI ->


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op ,


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG


<s> if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } return


<s> SDNode * N = DAG . getMachineNode ( MachineOpc ,


<s> SDNode * N = DAG . getMachineNode ( MachineOpc , dl , Ty , Ops ) ; return SDValue ( N ,


<s> bool isCheapToSpeculateCttz ( ) const


<s> bool isUndef ( SDValue Op ) const { if ( Op . isMachineOpcode ( ) ) return Op . getMachineOpcode


<s> if ( ! Ty . isVector ( ) ) return Ty ; return <STR_LIT> ( Ty . getSizeInBits


<s> unsigned TyWidth = Ty . getSizeInBits ( ) ; unsigned ElemWidth = ElemTy . getSizeInBits ( ) ; assert ( ( TyWidth % ElemWidth )


<s> bool <ISA_LIT>TargetLowering :: allowTruncateForTailCall ( Type * Ty1 , Type * Ty2 ) const { if ( ! Ty1 -> isIntegerTy ( ) || ! Ty2 -> isIntegerTy ( ) ) return false ; return Ty1 -> getPrimitiveSizeInBits (


<s> bool <ISA_LIT>TargetLowering :: allowTruncateForTailCall ( Type * Ty1 , Type *


<s> if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return


<s> if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } static const MCPhysReg RegList1 [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false


<s> unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( ( UseHVX && UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstD ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( ( UseHVX && UseHVXDbl ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstS ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } return true


<s> <ISA_LIT>CCState & HState = static_cast < <ISA_LIT>CCState & > ( State ) ; if ( ValNo < HState . getNumNamedVarArgParams ( ) ) { return CC_<ISA_LIT> ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; } unsigned ofst ; if ( ArgFlags . isByVal ( ) ) { ofst = State . AllocateStack ( ArgFlags . getByValSize ( ) , ArgFlags . getByValAlign ( ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT>


<s> if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) return DAG . getNode


<s> MachineFunction * MF = BB -> getParent ( ) ; auto * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( &


<s> assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Value * Fn = <STR_LIT> ( M , IntID ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * Ext = Builder . CreateZExt ( Cmp , Type :: getInt32Ty ( M -> getContext ( ) ) ) ; return Ext


<s> Type * Ty = Val -> getType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Value * Fn = <STR_LIT> ( M , IntID ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVXDblOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> : case


<s> TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT>


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const


<s> static bool getIndexedAddressParts ( SDNode * Ptr , EVT VT , bool isSEXTLoad , SDValue & Base , SDValue & Offset , bool & isInc , SelectionDAG & DAG ) { if ( Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ; bool UseHVX = HST


<s> SDValue <ISA_LIT>TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { int Idx = cast < JumpTableSDNode > ( Table ) -> getIndex ( ) ; EVT VT = Table . getValueType ( ) ; SDValue T = DAG . getTargetJumpTable ( Idx , VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc (


<s> } bool isInc = false ; bool isLegal = getIndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( isLegal ) { auto & HII = * Subtarget . getInstrInfo ( ) ; int32_t OffsetVal = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; if ( HII . isValidAutoIncImm ( VT , OffsetVal ) ) { AM = isInc ? <STR_LIT>


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'q' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && UseHVX && UseHVXDbl ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i ) != V0


<s> for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i )


<s> bool CCMatch = CallerCC == CalleeCC ; if ( ! ( isa < GlobalAddressSDNode > ( Callee ) ) && ! ( isa < ExternalSymbolSDNode > ( Callee ) ) ) { return false ; } if ( ! CCMatch ) return false ; if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA


<s> bool llvm :: isPositiveHalfWord ( SDNode * N ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode >


<s> static bool isSExtFree ( SDValue N ) { if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand

( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ;


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isSimple ( ) || ! VT2 . isSimple ( ) ) return false ; return ( VT1 . getSimpleVT ( ) == <STR_LIT> ) && ( VT2


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl (


<s> Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue A = DAG . getTargetBlockAddress ( BA , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , A ) ; } SDValue A = DAG . getTargetBlockAddress ( BA , PtrVT


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , InFlag ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> , TPR . getValue ( <NUM_LIT> ) ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) ; } InVals . push_back ( RetVal . getValue ( <NUM_LIT> ) ) ; Chain = RetVal . getValue (


<s> assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXSglOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXDblOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V = C0 ; for ( unsigned i = <NUM_LIT> , e = NElts ;


<s> SDValue InpVal = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( InpVal ) ) { uint64_t V = cast < ConstantSDNode > ( InpVal ) -> getZExtValue ( ) ; return DAG . getTargetConstant ( countPopulation ( V ) , dl , <STR_LIT> ) ; } SDValue PopOut = DAG . getNode ( <STR_LIT> , dl


<s> SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> setHasEHReturn ( ) ; unsigned OffsetReg = <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset


<s> FuncInfo -> setHasEHReturn ( ) ; unsigned OffsetReg = <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg


<s> if ( W == <NUM_LIT> ) { unsigned Subreg = ( X == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; if ( X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; N = DAG . getTargetExtractSubreg ( Subreg , dl , <STR_LIT> , Vec ) ; } else if ( VecVT . getSizeInBits ( ) == <NUM_LIT> ) { N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else { N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , N ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , N ) ; } SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , DAG . getConstant ( EltSize , dl , <STR_LIT> ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted , Offset ) ; const SDValue Ops [ ] = { Vec , Combined } ; SDValue


<s> InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( UseHVX && UseHVXDbl && ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( UseHVX && UseHVXDbl && ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; } StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset (


<s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI .


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr


<s> if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Off = DAG . getConstant ( Offset , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT


<s> case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : return LowerToTLSInitialExecModel ( GA , DAG ) ; case TLSModel :: LocalExec : return LowerToTLSLocalExecModel ( GA , DAG ) ; } llvm_unreachable (


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG )


<s> if ( isPositionIndependent ( ) ) { SDValue T = DAG . getTargetJumpTable ( Idx , VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , T ) ; } SDValue T = DAG . getTargetJumpTable ( Idx ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( Op ) ; SDValue Chain = LoadNode -> getChain ( ) ; SDValue Ptr = Op . getOperand ( <NUM_LIT> ) ; SDValue LoweredLoad ; SDValue Result ; SDValue Base = LoadNode -> getBasePtr ( ) ; <STR_LIT> Ext = LoadNode -> getExtensionType ( ) ; unsigned Alignment = LoadNode -> getAlignment ( ) ; SDValue LoadChain ; if ( Ext == <STR_LIT> ) Ext = <STR_LIT> ; if ( VT == <STR_LIT> ) { if ( Alignment == <NUM_LIT> ) { SDValue Loads [ <NUM_LIT> ] ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Base , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Base . getValueType ( ) , Base , Increment ) ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; SDValue ShiftAmount = DAG . getConstant ( <NUM_LIT> , DL ,


<s> unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT (


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , <STR_LIT> ) ; SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( TGA , DAG ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSInitialExecModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) const { SDLoc dl ( GA ) ; int64_t Offset = GA -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TP = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned char TF = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , TF ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; if ( IsPositionIndependent ) { SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( Sym , DAG ) ; Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT ,


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TP = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , <STR_LIT> ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TP ,


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Addr , Op . getOperand ( <NUM_LIT> ) ,

MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> BuildVectorSDNode * BVN = <NUM_LIT> ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDValue V3 ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V1 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V2 ; else if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V2 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V1 ; else return SDValue ( ) ; SDValue CommonSplat = BVN -> getOperand ( <NUM_LIT> ) ; SDValue Result ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; default : return SDValue ( )


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( V2 . isUndef ( ) ) V2 = V1 ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return createSplat ( DAG , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( )


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ; return true


<s> LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || ( LocVT == <STR_LIT> && UseHVX && UseHVXDbl ) ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>Vector ( ValNo , ValVT , LocVT , LocInfo ,


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT


<s> auto & MF = State . getMachineFunction ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseHVX = HST . useHVXOps ( ) ; bool UseHVXDbl = HST . useHVXDblOps ( ) ; unsigned OffSiz = <NUM_LIT> ; if ( LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if ( LocVT ==


<s> const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned Size = DL . getTypeStoreSize ( AI -> getCompareOperand ( ) -> getType ( ) ) ; return Size >= <NUM_LIT> &&


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLOnly


<s> AtomicExpansionKind shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const override { return AtomicExpansionKind ::


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) >


<s> EVT EltVT = VT . getVectorElementType ( ) ; int EltBits = EltVT . getSizeInBits (


<s> if ( ( EltBits != <NUM_LIT> ) && ( EltBits != <NUM_LIT> ) ) return false ; return TargetLowering :: shouldExpandBuildVectorWithShuffles ( VT


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Flags , Fast ) ; if ( Fast ) * Fast = false ; return


<s> unsigned ValLen = ValTy . getVectorNumElements ( ) ; unsigned ResLen = ResTy . getVectorNumElements ( ) ; if ( ValLen == ResLen ) return Val ; const SDLoc & dl ( Val ) ; assert ( ValLen < ResLen ) ; assert ( ResLen % ValLen == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Concats = {


<s> assert ( Elem . size ( ) == <NUM_LIT> ) ; if ( AllConst ) { uint32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } SDValue N = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Elem [ <NUM_LIT> ] , Elem [ <NUM_LIT> ] } , DAG ) ; return DAG . getBitcast ( <STR_LIT> , N ) ; } if ( ElemTy == <STR_LIT> ) { if ( AllConst ) { int32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } bool IsSplat = true ; for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } assert ( Elem . size ( ) == <NUM_LIT> ) ; SDValue Vs [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Vs [ i ] = DAG . getZExtOrTrunc ( Elem [ i ] , dl , <STR_LIT> ) ; Vs [ i ] = DAG . getZeroExtendInReg ( Vs [ i ] , dl , <STR_LIT> ) ; } SDValue S8 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Vs [ <NUM_LIT> ] , S8 } ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Vs [ <NUM_LIT> ]


<s> MVT ElemTy = VecTy . getVectorElementType ( ) ; assert ( VecTy . getVectorNumElements ( ) == Elem . size ( ) ) ; SmallVector < ConstantInt * , <NUM_LIT> > Consts ( Elem . size ( ) ) ; bool AllConst = getBuildVectorConstInts ( Elem , VecTy , DAG , Consts ) ; unsigned First , Num = Elem . size ( ) ; for ( First = <NUM_LIT> ; First != Num ; ++ First ) { if ( ! isUndef ( Elem [ First ] ) ) break ; } if ( First == Num ) return DAG . getUNDEF ( VecTy ) ; if ( AllConst && llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; if ( ElemTy == <STR_LIT> ) { bool IsSplat = true ; for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts [ Num - <NUM_LIT> - i ] -> getZExtValue ( ) & Mask ) ; SDValue V0 = DAG . getConstant ( Val , dl , <STR_LIT>


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , false , false , MachinePointerInfo (


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc & dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , false , false , MachinePointerInfo ( )


<s> assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; PointerType * NewPtrTy = Builder . getIntNTy ( SZ ) ->

getPointerTo ( PT -> getAddressSpace ( ) ) ;


<s> Type * CastTy = Builder . getIntNTy ( SZ ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; unsigned AS = Addr -> getType ( ) -> getPointerAddressSpace ( ) ; Addr = Builder . CreateBitCast ( Addr , CastTy -> getPointerTo ( AS ) ) ; Val = Builder . CreateBitCast ( Val , CastTy ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * Ext = Builder . CreateZExt ( Cmp , Type :: getInt32Ty ( M -> getContext ( ) ) ) ; return


<s> Module * M = BB -> getParent ( ) -> getParent ( ) ; Type * Ty = Val -> getType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; Type * CastTy = Builder . getIntNTy ( SZ ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Function * Fn = <STR_LIT> ( M , IntID ) ; unsigned AS = Addr -> getType ( ) -> getPointerAddressSpace ( ) ; Addr = Builder . CreateBitCast ( Addr , CastTy -> getPointerTo


<s> if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; return <STR_LIT>


<s> if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; return


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & ) const { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & ) const { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT>


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : break ; } return nullptr


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = <STR_LIT> ; Type * VecTy = I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ; Info . memVT = <STR_LIT> ( VecTy ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true


<s> return DAG . getNode ( <STR_LIT> , dl , Ty , getZero ( dl , <STR_LIT> , DAG ) ) ; } if ( Ty . isInteger ( ) ) return DAG . getConstant ( <NUM_LIT> , dl , Ty ) ; if ( Ty . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , dl , Ty ) ; llvm_unreachable ( <STR_LIT>


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF ,


<s> return isOperationLegalOrCustom ( <STR_LIT> ,


<s> SDValue Sc = DAG . getBitcast ( tyScalar ( InpTy ) , InpV ) ; SDValue Ext = DAG . getZExtOrTrunc ( Sc , dl , <STR_LIT> ) ; return getInstr ( <STR_LIT> , dl , ResTy , Ext , DAG ) ; } return SDValue ( ) ; } return Op


<s> MVT ResTy = ty ( Op ) ; SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT InpTy = ty ( InpV ) ; assert ( ResTy . getSizeInBits ( ) == InpTy . getSizeInBits ( ) ) ; const SDLoc & dl ( Op ) ; if ( InpTy == <STR_LIT> ) { if ( ResTy == <STR_LIT> ) { SDValue Sc = DAG . getBitcast ( tyScalar ( InpTy ) , InpV ) ; SDValue Ext = DAG . getZExtOrTrunc ( Sc , dl , <STR_LIT> ) ; return getInstr ( <STR_LIT> , dl , ResTy , Ext , DAG ) ; } return SDValue ( ) ; } return Op