<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> Dependence = true ; return false ; } if ( ( QII -> isMemOp ( J ) && MCIDI . mayStore ( ) ) || ( MCIDJ . mayStore ( ) && QII -> isMemOp ( I ) ) || ( QII -> isMemOp ( J ) && QII -> isMemOp ( I ) ) ) { Dependence = true ; return false ; } if ( MCIDJ . mayStore ( ) && QII -> isDeallocRet ( I ) ) { Dependence = true ; return false ; } MachineBasicBlock :: iterator NextMII = I ; ++ NextMII ; MachineInstr * NextMI = NextMII ; if ( QII -> isNewValueJump ( NextMI ) ) { bool secondRegMatch = false ; bool maintainNewValueJump = false ; if ( NextMI -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { secondRegMatch = true ; maintainNewValueJump = true ; } if ( ! secondRegMatch && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { maintainNewValueJump = true ; } for ( std :: vector < MachineInstr * > :: iterator VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE && maintainNewValueJump ) ; ++ VI ) { SUnit * PacketSU = MIToSUnit [ * VI ] ; if ( PacketSU -> getInstr ( ) -> getDesc ( ) . isCall ( ) ) { Dependence = true ; break ; } if ( PacketSU -> getInstr ( ) -> getDesc ( ) . mayStore ( ) || PacketSU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> || ( ! secondRegMatch && NextMI -> getOperand ( <NUM_LIT> ) . isReg ( ) && PacketSU -> getInstr ( ) -> modifiesRegister ( NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , QRI ) ) || ( secondRegMatch && PacketSU -> getInstr ( ) -> modifiesRegister ( NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , QRI ) ) ) { Dependence = true ; break ; } } if ( ! Dependence ) GlueToNewValueJump = true ; else return false ; } } if ( SUJ -> isSucc ( SUI ) ) { for ( unsigned i = <NUM_LIT> ; ( i < SUJ -> Succs . size ( ) ) && ! FoundSequentialDependence ; ++ i )


<s> bool <ISA_LIT>PacketizerList :: isNewifiable ( MachineInstr * MI ) { if ( isCondInst ( MI ) || IsNewifyStore ( MI ) )


<s> if ( QII -> isNewValueJump ( MI ) ) return true ; if ( QII -> isNewValueStore ( MI ) )


<s> if ( RC == & <STR_LIT> ) NewOpcode = GetDotNewPredOp ( MI -> getOpcode ( ) ) ; else NewOpcode = GetDotNewOp ( MI -> getOpcode ( ) ) ; MI -> setDesc ( QII -> get


<s> if ( ResourceTracker -> canReserveResources ( PseudoMI ) ) { ResourceTracker -> reserveResources ( PseudoMI ) ; MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( PseudoMI ) ; }


<s> while ( MI != End ) { if ( MI -> isKill ( ) ) { MachineBasicBlock :: iterator DeleteMI = MI ; ++ MI ; MBB -> erase ( DeleteMI ) ; End = MBB -> end ( ) ; continue ; } ++ MI ; } } for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { unsigned RemainingCount = MBB -> size ( ) ; for ( MachineBasicBlock :: iterator RegionEnd = MBB -> end ( ) ; RegionEnd != MBB -> begin ( ) ; ) { MachineBasicBlock :: iterator I = RegionEnd ; for ( ; I != MBB -> begin ( ) ; -- I , -- RemainingCount ) { if ( TII -> isSchedulingBoundary ( llvm :: prior ( I ) , MBB , Fn ) ) break ; } I = MBB -> begin ( ) ; if ( I == RegionEnd


<s> if ( ResourceTracker -> canReserveResources ( PseudoMI ) ) { ResourceTracker -> reserveResources ( PseudoMI ) ; MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( PseudoMI ) ; return true ; } else { MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( PseudoMI ) ; return


<s> } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || QII -> isDotNewInst ( PacketMI ) != QII -> isDotNewInst ( MI ) || getPredicateSense ( MI , QII ) != getPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit . find ( * VI ) -> second ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) && TempSU -> getInstr ( ) -> modifiesRegister ( MI -> getOperand ( opNum ) . getReg ( ) , QRI ) ) return false ; } } if ( ! QII -> isPostIncrement ( MI ) && GetStoreValueOperand ( MI ) . isReg ( ) && GetStoreValueOperand ( MI ) . getReg ( ) == DepReg ) { for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) - <NUM_LIT> ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . getReg ( ) == DepReg ) { return false ; } } for ( unsigned opNum = <NUM_LIT> ; opNum <

PacketMI -> getNumOperands ( ) ; opNum ++ ) {


<s> for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) { if ( PacketMI -> getOperand ( opNum ) . isReg ( ) ) predRegNumSrc = PacketMI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumSrc ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) ) predRegNumDst = MI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || QII -> isDotNewInst ( PacketMI ) != QII -> isDotNewInst ( MI ) || getPredicateSense ( MI , QII ) != getPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit . find ( * VI ) -> second ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum <


<s> for ( auto & Pred : SUI -> Preds ) if ( Pred . getSUnit ( ) == SUJ ) if ( ( Pred . getLatency ( ) == <NUM_LIT> && Pred . isAssignedRegDep ( ) ) || HII -> isNewValueJump ( I ) || HII -> isToBeScheduledASAP ( * J , I ) ) return <NUM_LIT> ; } for ( auto J : OldPacketMIs ) { SUnit * SUJ = MIToSUnit [ J ] ; for ( auto & Pred : SUI -> Preds ) if ( Pred . getSUnit ( ) == SUJ &&

Pred . getLatency ( ) > <NUM_LIT> ) return Pred . getLatency ( ) ;


<s> bool <ISA_LIT>PacketizerList :: canPromoteToDotNew ( const MachineInstr & MI , const SUnit * PacketSU , unsigned DepReg , MachineBasicBlock :: iterator & MII , const TargetRegisterClass * RC ) { if ( HII -> isDotNewInst ( MI ) && ! HII -> mayBeNewStore ( MI ) ) return false ; if ( ! isNewifiable ( MI , RC ) ) return false ; const MachineInstr & PI = * PacketSU -> getInstr ( ) ; if ( PI . isInlineAsm ( ) ) return false ; if ( PI . isImplicitDef ( ) ) return false ; if ( isImplicitDependency ( PI , true , DepReg ) || isImplicitDependency ( MI , false , DepReg ) ) return false ; const MCInstrDesc & MCID = PI . getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = ( RC != & <STR_LIT> ) ? HII -> getDotNewOp ( MI ) : HII -> getDotNewPredOp ( MI , MBPI ) ; const MCInstrDesc & D = HII


<s> if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; if ( isSchedBarrier ( MI ) ) return true ; if ( HII -> isSolo ( MI ) ) return true ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) return true ; if ( MI . getOpcode ( ) == <STR_LIT> ) return true ; return false


<s> if ( Latency == <NUM_LIT> ) return false ; if ( PacketStalls ) return Latency > PacketStallCycles ; return true


<s> if ( Minimal ) return false ; if ( producesStall ( MI ) ) return false ; auto & HST = MI . getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( HST . isTinyCoreWithDuplex ( ) && CurrentPacketMIs . size ( ) > <NUM_LIT> && ! PacketHasDuplex ) { for ( auto & MJ : CurrentPacketMIs ) PacketHasSLOT0OnlyInsn |= HII -> isPureSlot0 ( * MJ ) ; int Opcode = HII -> getDuplexOpcode ( MI , false ) ; if ( Opcode >=


<s> for ( auto & MJ : CurrentPacketMIs ) PacketHasSLOT0OnlyInsn |= HII -> isPureSlot0 ( * MJ ) ; int Opcode = HII -> getDuplexOpcode ( MI , false ) ; if ( Opcode >= <NUM_LIT> ) { for ( auto & MJ : CurrentPacketMIs ) { if ( HII -> isDuplexPair ( MI , * MJ )


<s> bool <ISA_LIT>PacketizerList :: tryAllocateResourcesForConstExt ( bool Reserve ) { auto * ExtMI = MF . CreateMachineInstr ( HII -> get ( <STR_LIT> ) , DebugLoc


<s> } assert ( ( predRegClass == & <STR_LIT> ) && <STR_LIT> ) ; for ( auto & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; predRegNumDst = MO . getReg ( ) ; predRegClass = HRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) break ; } assert ( ( predRegClass == & <STR_LIT> ) && <STR_LIT> ) ; if ( predRegNumDst != predRegNumSrc || HII -> isDotNewInst ( PacketMI ) != HII -> isDotNewInst ( MI ) || getPredicateSense ( MI , HII ) != getPredicateSense ( PacketMI , HII ) ) return false ; } unsigned StartCheck = <NUM_LIT> ; for ( auto I : CurrentPacketMIs ) { SUnit * TempSU = MIToSUnit . find ( I ) -> second ; MachineInstr & TempMI = * TempSU -> getInstr ( ) ; if ( & TempMI != & PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( & TempMI == & PacketMI ) continue ; for ( auto & MO : MI . operands ( ) ) if ( MO . isReg ( ) && TempSU -> getInstr ( ) -> modifiesRegister ( MO . getReg ( ) , HRI ) ) return false ; } if ( ! HII -> isPostIncrement ( MI ) ) { for ( unsigned opNum = <NUM_LIT> ; opNum < MI . getNumOperands ( ) - <NUM_LIT> ; opNum ++ ) { const MachineOperand & MO = MI . getOperand ( opNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) == DepReg ) return false ; } } for ( auto & MO : PacketMI . operands ( ) ) { if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( DepReg ) ) return false ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO . isImplicit ( ) ) continue ; Register R = MO .


<s> LLVM_DEBUG ( { if ( ! CurrentPacketMIs . empty ( ) ) { dbgs ( ) << <STR_LIT> ; unsigned Idx =


<s> unsigned R = ResourceTracker -> getUsedResources ( Idx ++ ) ; dbgs ( ) << <STR_LIT> << utohexstr (


<s> bool <ISA_LIT>PacketizerList :: ignorePseudoInstruction ( const MachineInstr & MI , const MachineBasicBlock * ) { if ( MI . isDebugInstr ( ) ) return true ; if ( MI . isCFIInstruction ( ) ) return false ; if ( MI . isInlineAsm ( ) ) return false ; if ( MI . isImplicitDef ( )


<s> bool <ISA_LIT>PacketizerList :: ignorePseudoInstruction ( const MachineInstr & MI , const MachineBasicBlock * ) { if ( MI . isDebugInstr ( ) ) return true ; if ( MI . isCFIInstruction ( ) ) return false ; if ( MI . isInlineAsm ( ) ) return false ; if ( MI . isImplicitDef ( ) ) return false ; const MCInstrDesc & TID = MI . getDesc ( ) ; auto * IS = ResourceTracker -> getInstrItins ( ) -> beginStage ( TID . getSchedClass ( ) ) ; return ! IS -> getUnits (


<s> if ( HII -> isDeallocRet ( MI ) ) if ( DepReg == HRI -> getFrameRegister ( ) || DepReg == HRI -> getStackRegister ( ) ) return true ; if ( DepType == SDep :: Data ) { for ( const MachineOperand & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == DepReg && ! MO . isImplicit ( ) ) return true ; } return false


<s> if ( MI . mayStore ( ) && isPureSlot0InsnWithNoSlot1Store ( MI ) ) return false ; if ( producesStall ( MI ) ) return false ; auto & HST = MI . getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( HST . isTinyCoreWithDuplex ( ) && CurrentPacketMIs . size ( ) > <NUM_LIT> && ! PacketHasDuplex ) { for ( auto & MJ : CurrentPacketMIs ) PacketHasSLOT0OnlyInsn |= HII -> isPureSlot0 ( * MJ ) ; int Opcode = HII -> getDuplexOpcode ( MI , false ) ; if ( Opcode >= <NUM_LIT> ) { for ( auto & MJ


<s> if ( Reg != MJ . getOperand ( BPJ ) . getReg ( ) ) return false ; for ( const auto & PI : SUI -> Preds ) if ( PI . getKind ( ) != SDep :: Anti && ( PI . getKind ( ) != SDep :: Data || PI . getReg ( ) != Reg ) ) return false ; int Incr ; if ( ! HII -> getIncrementValue ( MJ , Incr


<s> assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) ) predRegNumDst = MI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || QII -> isDotNewInst ( PacketMI ) != QII -> isDotNewInst ( MI ) || getPredicateSense ( MI , QII ) != getPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit [ * VI ] ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) && TempSU -> getInstr ( ) -> modifiesRegister ( MI -> getOperand ( opNum ) . getReg ( ) , QRI ) ) return false ; } } if ( ! QII -> isPostIncrement ( MI ) && GetStoreValueOperand ( MI ) . isReg ( ) && GetStoreValueOperand ( MI ) . getReg ( ) == DepReg ) { for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) - <NUM_LIT> ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . getReg ( ) == DepReg ) { return false ; } } for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) { if ( PacketMI -> getOperand ( opNum ) . isReg ( ) && PacketMI -> getOperand ( opNum ) . getReg ( ) == DepReg && PacketMI -> getOperand ( opNum ) . isDef ( ) && PacketMI -> getOperand ( opNum ) . isImplicit ( ) ) { return


<s> bool MinOnly = Minimal || DisablePacketizer || ! HST . usePackets ( ) || skipFunction ( MF . getFunction ( ) ) ; <ISA_LIT>PacketizerList Packetizer ( MF , MLI , AA , MBPI , MinOnly ) ; assert ( Packetizer . getResourceTracker ( ) && <STR_LIT> ) ; for ( MachineBasicBlock & MB : MF ) { auto End = MB . end ( ) ; auto MI = MB . begin ( ) ; while ( MI != End ) { auto NextI = std :: next ( MI ) ; if ( MI -> isKill ( ) ) { MB . erase ( MI ) ; End = MB . end ( ) ; } MI = NextI ; } } if ( HST . isTinyCoreWithDuplex ( ) ) HII -> translateInstrsForDup ( MF , true ) ; for ( auto & MB : MF ) { auto Begin = MB . begin ( ) , End = MB . end ( ) ; while ( Begin != End ) { MachineBasicBlock :: iterator RB = Begin ; while ( RB != End && HII -> isSchedulingBoundary ( * RB , &


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; if ( MI . isImplicitDef ( ) ) { unsigned R = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( R ) ) { MCSuperRegIterator S ( R , HRI , false ) ; MI . addOperand ( MachineOperand :: CreateReg ( * S , true , true ) ) ; } return MII ; } assert ( ResourceTracker -> canReserveResources ( MI ) ) ; bool ExtMI = HII -> isExtended ( MI ) || HII -> isConstExtended ( MI ) ; bool Good = true ; if ( GlueToNewValueJump ) { MachineInstr & NvjMI = * ++ MII ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) Good = tryAllocateResourcesForConstExt ( true ) ; bool ExtNvjMI = HII -> isExtended ( NvjMI ) || HII -> isConstExtended ( NvjMI ) ; if ( Good ) { if ( ResourceTracker -> canReserveResources ( NvjMI ) ) ResourceTracker -> reserveResources ( NvjMI ) ; else Good = false ; } if ( Good && ExtNvjMI ) Good = tryAllocateResourcesForConstExt ( true ) ; if ( ! Good ) { endPacket ( MBB , MI ) ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; tryAllocateResourcesForConstExt ( true ) ; } assert ( ResourceTracker -> canReserveResources ( NvjMI ) ) ; ResourceTracker -> reserveResources ( NvjMI ) ; if ( ExtNvjMI


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasV60TOpsOnly ( ) && HII . isHVXMemWithAIndirect ( MI , MJ ) ) return true ; if ( MI . isInlineAsm ( ) ) return MJ . isInlineAsm ( ) || MJ . isBranch ( ) || MJ . isBarrier ( ) || MJ . isCall ( ) || MJ . isTerminator ( ) ; return


<s> if ( HII -> isDotNewInst ( MI ) && ! HII -> mayBeNewStore ( MI ) ) return false ; if ( ! isNewifiable ( MI , RC ) ) return false ; const MachineInstr & PI = * PacketSU -> getInstr ( ) ; if ( PI . isInlineAsm ( ) ) return false ; if ( PI . isImplicitDef ( ) ) return false ; if ( isImplicitDependency ( PI , DepReg ) ) return false ; const MCInstrDesc & MCID = PI . getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) if ( HII -> isCondInst ( MI ) || MI . isReturn ( ) ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = HII -> getDotNewOp ( MI ) ; const MCInstrDesc & D = HII -> get ( NewOpcode ) ; MachineInstr * NewMI = MF . CreateMachineInstr ( D , DebugLoc ( ) ) ; bool ResourcesAvailable = ResourceTracker -> canReserveResources (


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; BI -> dump ( ) ; ) ; if ( BI -> getOpcode ( ) == <STR_LIT> ) { MI = BI ; continue ; } if ( MI ) { for ( auto & MO : BI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } } if ( ! MI ) return ; MI -> setDesc ( HII -> get ( <STR_LIT>


<s> bool <ISA_LIT>PacketizerList :: demoteToDotOld ( MachineInstr & MI ) { int NewOpcode = HII -> getDotOldOp ( MI . getOpcode ( ) ) ; MI . setDesc ( HII -> get ( NewOpcode ) ) ; return true


<s> if ( HII -> isDeallocRet ( MI ) ) if ( DepReg == HRI -> getFrameRegister ( ) || DepReg == HRI -> getStackRegister ( ) ) return true ; const TargetRegisterClass * RC = HRI -> getMinimalPhysRegClass ( DepReg ) ; if ( RC == & <STR_LIT> ) return true ; if ( HII -> isIndirectCall ( MI ) && ( DepType == SDep :: Data ) ) { MachineOperand MO = MI . getOperand (


<s> static bool isDependent ( const MachineInstr & ProdMI , const MachineInstr & ConsMI ) { if ( ! ProdMI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; unsigned DstReg = ProdMI . getOperand ( <NUM_LIT> )


<s> for ( auto & Op : ConsMI . operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) && Op . getReg ( ) == DstReg ) return true ; return false


<s> static bool isImplicitDependency ( const MachineInstr & I , unsigned DepReg ) { for ( auto & MO : I . operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) && ( MO . getReg ( ) == DepReg ) && MO . isImplicit ( ) ) return true ; return


<s> if ( ! isCallDependent ( I , DepType , SUJ -> Succs [ i ] . getReg ( ) ) ) continue ; } if ( DepType == SDep :: Data ) { if ( canPromoteToDotCur ( J , SUJ , DepReg , II , RC ) ) if ( promoteToDotCur ( J , DepType , II , RC ) ) continue ; } if ( DepType == SDep :: Data && HII -> isDotCurInst ( J ) ) { if ( HII -> isV60VectorInstruction ( I ) ) continue ; } if ( DepType == SDep :: Data ) { if ( canPromoteToDotNew ( I , SUJ , DepReg , II , RC ) ) { if ( promoteToDotNew ( I , DepType , II , RC ) ) { PromotedToDotNew = true ; continue ; } } if ( HII -> isNewValueJump ( I ) ) continue ; } if ( HII -> isPredicated ( I ) && HII -> isPredicated ( J ) && arePredicatesComplements ( I , J ) ) { auto Itr = std :: find ( IgnoreDepMIs . begin ( ) , IgnoreDepMIs . end ( ) , & J ) ; if ( Itr != IgnoreDepMIs . end ( ) ) { Dependence = true ; return false ; } IgnoreDepMIs . push_back ( & I ) ; continue ; } if ( isDirectJump ( I ) && ! J . isBranch ( ) && ! J . isCall ( ) && DepType == SDep :: Order ) continue ; if ( I . isConditionalBranch ( ) && DepType != SDep :: Data && DepType != SDep :: Output ) continue ; if ( DepType == SDep :: Output ) { unsigned DepReg = SUJ -> Succs [ i ] . getReg ( ) ; if ( ! I . definesRegister ( DepReg ) && ! J . definesRegister ( DepReg ) ) continue ; FoundSequentialDependence = true ; break ; } if ( DepType == SDep :: Order ) { if ( ! PacketizeVolatiles ) { bool OrdRefs = I . hasOrderedMemoryRef ( ) || J . hasOrderedMemoryRef ( ) ; if ( OrdRefs ) { FoundSequentialDependence = true ; break ; } } bool LoadJ = J . mayLoad ( ) , StoreJ = J .


<s> MachineInstr & I = * SUI -> getInstr ( ) ; MachineInstr & J = * SUJ -> getInstr ( ) ; if ( cannotCoexist ( I , J ) ) return false ; if ( ! Dependence ) return true ; if ( PromotedToDotNew ) demoteToDotOld ( I ) ; cleanUpDotCur ( )


<s> if ( NewRC == & <STR_LIT> ) if ( HII -> isV60VectorInstruction ( MI ) && MI . mayStore ( ) ) return false ; return HII -> isCondInst ( MI ) || MI . isReturn ( ) || HII -> mayBeNewStore


<s> return HII -> isCondInst ( MI ) || MI . isReturn ( )


<s> if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) if ( HII -> isCondInst ( MI ) || HII -> isJumpR ( MI ) || MI . isReturn ( ) ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = HII -> getDotNewOp ( MI ) ; const MCInstrDesc & D = HII -> get


<s> if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = HII -> getDotNewOp ( MI ) ; const MCInstrDesc & D = HII -> get ( NewOpcode ) ; MachineInstr * NewMI = MF . CreateMachineInstr ( D , DebugLoc ( ) ) ; bool ResourcesAvailable = ResourceTracker -> canReserveResources ( * NewMI ) ; MF . DeleteMachineInstr ( NewMI ) ; if ( ! ResourcesAvailable ) return false ; if ( ! canPromoteToNewValue ( MI , PacketSU , DepReg


<s> if ( HII -> isIndirectCall ( MI ) && ( DepType == SDep :: Data ) ) { const MachineOperand MO = MI . getOperand ( <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . isUse ( ) && ( MO . getReg ( ) == DepReg ) ) return true ; } if ( HII -> isJumpR ( MI ) ) { const MachineOperand & MO = HII -> isPredicated ( MI ) ? MI . getOperand ( <NUM_LIT> ) : MI . getOperand


<s> if ( RC == & <STR_LIT> ) return true ; if ( HII -> isIndirectCall ( MI ) && ( DepType == SDep :: Data ) ) { const MachineOperand MO = MI . getOperand ( <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . isUse ( ) && ( MO . getReg ( ) == DepReg ) ) return true ; } if ( HII -> isJumpR ( MI ) ) { const MachineOperand & MO = HII -> isPredicated ( MI ) ? MI . getOperand ( <NUM_LIT> ) : MI . getOperand ( <NUM_LIT> ) ; assert ( MO . isReg ( ) && MO . isUse ( ) ) ; if ( MO . getReg ( ) ==


<s> static bool isImplicitDependency ( const MachineInstr & I , unsigned DepReg ) { for ( auto & MO : I . operands ( ) ) { if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( DepReg


<s> for ( auto & MO : I . operands ( ) ) { if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( DepReg ) ) return true ; if ( MO . isReg ( ) && MO . isDef ( ) && ( MO . getReg ( ) == DepReg ) && MO . isImplicit ( )


<s> MachineInstr * PseudoMI = MF -> CreateMachineInstr ( QII -> get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; bool CanReserve = ResourceTracker -> canReserveResources


<s> bool <ISA_LIT>PacketizerList :: canReserveResourcesForConstExt ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; assert ( QII -> isExtended ( MI ) && <STR_LIT> ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineInstr * PseudoMI = MF -> CreateMachineInstr ( QII -> get ( <STR_LIT> ) ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return QRI -> Subtarget .


<s> if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasV60OpsOnly ( ) && HII . isHVXMemWithAIndirect ( MI , MJ ) ) return true ; if ( MI . isInlineAsm ( ) ) return MJ . isInlineAsm ( ) || MJ . isBranch ( ) || MJ . isBarrier ( ) || MJ . isCall ( ) || MJ . isTerminator ( ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> assert ( SUI -> getInstr ( ) && SUJ -> getInstr ( ) ) ; MachineInstr & MI = * SUI -> getInstr ( ) ; MachineInstr & MJ = * SUJ -> getInstr ( ) ; unsigned BPI , OPI ; if ( ! HII -> getBaseAndOffsetPosition ( MI , BPI , OPI ) ) return false ; unsigned BPJ , OPJ ; if ( ! HII -> getBaseAndOffsetPosition ( MJ , BPJ , OPJ ) ) return false ; unsigned Reg = MI . getOperand ( BPI ) . getReg ( ) ; if ( Reg != MJ . getOperand ( BPJ ) . getReg ( ) ) return false ; for ( const auto & PI : SUI -> Preds ) if ( PI . getKind ( ) != SDep :: Anti && ( PI . getKind ( ) != SDep :: Data || PI . getReg ( ) != Reg ) ) return false ; int Incr ; if ( ! HII -> getIncrementValue ( MJ , Incr ) ) return false ; int64_t Offset = MI . getOperand ( OPI ) . getImm ( ) ; MI . getOperand ( OPI ) . setImm ( Offset + Incr ) ; ChangedOffset =


<s> if ( Dep . getSUnit ( ) == SU && Dep . getKind ( ) == SDep :: Data && <STR_LIT> . contains ( Dep . getReg ( ) ) ) { if ( restrictingDepExistInPacket ( I , Dep . getReg ( ) ) ) return false ; } } } } unsigned PReg1 = getPredicatedRegister ( MI1 , HII ) ; unsigned PReg2 = getPredicatedRegister ( MI2 , HII ) ; return PReg1 == PReg2 && <STR_LIT> . contains ( PReg1 ) && <STR_LIT> . contains ( PReg2 ) && getPredicateSense ( MI1 , HII ) != getPredicateSense ( MI2 , HII ) && HII -> isDotNewInst ( & MI1 ) == HII


<s> bool <ISA_LIT>PacketizerList :: cannotCoexist ( const MachineInstr * MI , const MachineInstr * MJ ) { return cannotCoexistAsymm ( MI , MJ , * HII ) || cannotCoexistAsymm ( MJ , MI


<s> return cannotCoexistAsymm ( MI , MJ , * HII ) ||

cannotCoexistAsymm ( MJ , MI , * HII ) ;


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasV60TOpsOnly ( ) && HII . isHVXMemWithAIndirect ( MI , MJ ) ) return true ; if ( MI -> isInlineAsm ( ) ) return MJ -> isInlineAsm ( ) || MJ -> isBranch ( ) || MJ -> isBarrier ( ) || MJ -> isCall ( ) || MJ -> isTerminator ( ) ; return false


<s> if ( PacketSU -> getInstr ( ) -> isInlineAsm ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ; dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * MJ = MII ; DEBUG ( dbgs ( ) << <STR_LIT> ; MJ -> dump ( ) ; ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool FoundMatch = false ; for ( auto & MO : MJ -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == DestReg ) FoundMatch = true ; if ( ! FoundMatch ) return false ; for ( auto BI : CurrentPacketMIs ) { DEBUG ( dbgs ( ) << <STR_LIT> ; BI -> dump ( )


<s> if ( ! HII -> mayBeNewStore ( MI ) ) return false ; MachineInstr * PacketMI = PacketSU -> getInstr ( ) ; if ( canPromoteToNewValueStore ( MI , PacketMI , DepReg ) ) return true ; return false


<s> void <ISA_LIT>PacketizerList :: cleanUpDotCur ( ) { MachineInstr * MI = NULL ; for ( auto BI : CurrentPacketMIs ) { DEBUG ( dbgs ( ) << <STR_LIT> ; BI -> dump ( ) ; ) ; if ( BI -> getOpcode ( ) == <STR_LIT> ) { MI = BI ; continue ; } if ( MI ) { for ( auto & MO : BI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } } if ( ! MI ) return ; MI -> setDesc ( HII -> get ( <STR_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump


<s> MI -> setDesc ( HII -> get ( NewOpcode ) ) ; return true


<s> const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; for ( auto * CSR = TRI -> getCalleeSavedRegs ( & MF ) ; CSR && * CSR ; ++ CSR ) if ( MI -> modifiesRegister ( * CSR , TRI ) ) return true ; return false


<s> static const MachineOperand & getAbsSetOperand ( const


<s> static const MachineOperand & getAbsSetOperand ( const MachineInstr * MI ) { assert ( isLoadAbsSet ( MI )


<s> static const MachineOperand & getStoreValueOperand ( const MachineInstr


<s> static const MachineOperand & getStoreValueOperand ( const MachineInstr * MI ) { return MI -> getOperand ( MI -> getNumOperands ( ) -


<s> if ( HII -> isLoopN ( I ) && isBadForLoopN ( J ) ) return true ; if ( HII -> isLoopN ( J ) && isBadForLoopN ( I ) ) return true ; return HII -> isDeallocRet ( I ) && ( J -> isBranch ( ) || J -> isCall ( ) || J


<s> if ( ( HII -> isSaveCalleeSavedRegsCall ( I ) && doesModifyCalleeSavedReg ( J , HRI ) ) || ( HII -> isSaveCalleeSavedRegsCall ( J ) && doesModifyCalleeSavedReg ( I , HRI ) ) ) return true ; if ( isControlFlow ( I ) && isControlFlow ( J ) ) return true ; auto isBadForLoopN = [ this ] ( const MachineInstr * MI ) -> bool { if ( MI -> isCall ( ) || HII -> isDeallocRet ( MI ) || HII

-> isNewValueJump ( MI ) ) return true ;


<s> BitVector DeadDefs ( <STR_LIT> ) ; for ( auto & MO : I -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO . isDead ( ) ) continue ; DeadDefs [ MO . getReg ( ) ] = true ; } for ( auto & MO : J -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ||


<s> bool <ISA_LIT>PacketizerList :: hasV4SpecificDependence ( const MachineInstr * I , const MachineInstr * J ) { bool SysI = isSystemInstr ( I ) , SysJ = isSystemInstr ( J ) ; bool StoreI = I -> mayStore ( ) , StoreJ = J -> mayStore ( ) ; if ( ( SysI && StoreJ ) || ( SysJ && StoreI ) ) return true ; if ( StoreI && StoreJ ) { if ( HII -> isNewValueInst ( J ) || HII -> isMemOp ( J ) || HII -> isMemOp ( I ) ) return true ; } else { bool MopStI = HII -> isMemOp ( I )


<s> bool <ISA_LIT>PacketizerList :: hasV4SpecificDependence ( const MachineInstr * I , const MachineInstr * J ) { bool SysI = isSystemInstr ( I ) , SysJ = isSystemInstr ( J ) ; bool StoreI = I -> mayStore ( ) , StoreJ = J -> mayStore ( ) ; if ( ( SysI && StoreJ ) || ( SysJ && StoreI ) ) return true ; if ( StoreI && StoreJ ) { if ( HII -> isNewValueInst ( J ) || HII -> isMemOp ( J ) || HII -> isMemOp ( I ) ) return true ; } else { bool MopStI = HII -> isMemOp ( I ) || StoreI ; bool MopStJ = HII -> isMemOp (


<s> const TargetRegisterClass * RC = HRI -> getMinimalPhysRegClass ( DepReg ) ; if ( RC == & <STR_LIT> ) return true ; if ( HII -> isIndirectCall ( MI ) && ( DepType == SDep :: Data ) ) { MachineOperand MO = MI -> getOperand ( <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . isUse ( ) && ( MO . getReg ( ) == DepReg ) ) return true ; } return


<s> if ( DepReg == HRI -> getRARegister ( ) ) return true ; if ( HII -> isDeallocRet ( MI ) ) if ( DepReg == HRI -> getFrameRegister ( ) || DepReg == HRI -> getStackRegister ( ) ) return true ; const TargetRegisterClass * RC = HRI -> getMinimalPhysRegClass ( DepReg ) ; if ( RC == & <STR_LIT>


<s> if ( ! ProdMI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; unsigned DstReg = ProdMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto & Op : ConsMI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) && Op


<s> static bool isDirectJump ( const MachineInstr * MI ) { return MI -> getOpcode


<s> static bool isDirectJump ( const MachineInstr * MI ) { return MI -> getOpcode ( )


<s> static bool isImplicitDependency ( const MachineInstr * I , unsigned DepReg ) { for ( auto & MO : I -> operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) && ( MO . getReg ( ) == DepReg ) && MO . isImplicit


<s> unsigned DepReg = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; if ( DepType == SDep :: Data ) { DepReg = SUJ -> Succs [ i ] . getReg ( ) ; RC = HRI -> getMinimalPhysRegClass ( DepReg ) ; } if ( I -> isCall ( ) || I -> isReturn ( ) ) { if ( ! isRegDependence ( DepType ) ) continue ; if ( ! isCallDependent ( I , DepType , SUJ -> Succs [ i ] . getReg ( ) ) ) continue ; } if ( DepType == SDep :: Data ) { if ( canPromoteToDotCur ( J , SUJ , DepReg , II , RC ) ) if ( promoteToDotCur ( J , DepType , II , RC ) ) continue ; } if ( DepType == SDep :: Data && HII -> isDotCurInst ( J ) ) { if ( HII -> isV60VectorInstruction ( I ) ) continue ; } if ( DepType == SDep :: Data ) { if ( canPromoteToDotNew ( I , SUJ , DepReg , II , RC ) ) { if ( promoteToDotNew ( I , DepType , II , RC ) ) { PromotedToDotNew = true ; continue ; } } if ( HII -> isNewValueJump ( I ) ) continue ; } if ( HII -> isPredicated ( * I ) && HII -> isPredicated ( * J ) && arePredicatesComplements ( * I , * J ) ) { auto Itr = std :: find ( IgnoreDepMIs . begin ( ) , IgnoreDepMIs . end ( ) , J ) ; if ( Itr != IgnoreDepMIs . end ( ) ) { Dependence = true ; return false ; } IgnoreDepMIs . push_back ( I ) ; continue ; } if ( isDirectJump ( I ) && ! J -> isBranch ( ) && ! J -> isCall ( ) && DepType == SDep :: Order ) continue ; if ( I -> isConditionalBranch ( ) && DepType != SDep :: Data && DepType != SDep :: Output ) continue ; if ( DepType == SDep :: Output ) { unsigned DepReg = SUJ -> Succs [ i ] . getReg ( ) ; if ( ! I -> definesRegister ( DepReg ) && ! J -> definesRegister ( DepReg ) ) continue ; FoundSequentialDependence = true ; break ; } if ( DepType == SDep :: Order ) { if ( ! PacketizeVolatiles ) { bool OrdRefs = I -> hasOrderedMemoryRef ( ) || J -> hasOrderedMemoryRef ( ) ; if ( OrdRefs ) { FoundSequentialDependence = true ; break ; } } bool LoadJ = J -> mayLoad ( ) , StoreJ = J -> mayStore ( ) ; bool LoadI = I -> mayLoad ( ) , StoreI = I -> mayStore (


<s> return HII -> isCondInst ( MI ) || MI -> isReturn ( ) || HII -> mayBeNewStore


<s> return HII -> isCondInst ( MI ) || MI -> isReturn ( ) ||


<s> if ( MI . isEHLabel ( ) || MI . isCFIInstruction ( ) ) return true ; if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; if ( isSchedBarrier ( & MI


<s> bool <ISA_LIT>PacketizerList :: isSoloInstruction ( const MachineInstr & MI ) { if ( MI . isEHLabel ( ) || MI . isCFIInstruction ( ) ) return true ; if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; if ( isSchedBarrier ( & MI ) ) return true ; if ( HII -> isSolo ( & MI ) ) return true ; if ( MI . getOpcode ( ) == <STR_LIT> ) return true ; return false


<s> if ( HII -> isV60VectorInstruction ( I ) ) { for ( auto J : OldPacketMIs ) { if ( ! HII -> isV60VectorInstruction ( J ) ) continue ; if ( isDependent ( J , I ) && ! HII -> isVecUsableNextPacket ( J , I ) ) return true ; } return false ; } for ( auto J : CurrentPacketMIs ) if ( ! HII -> isV60VectorInstruction ( J ) && isDependent ( J , I ) ) return false ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useBSBScheduling ( ) ) { for ( auto J : OldPacketMIs ) { if ( HII -> isV60VectorInstruction (


<s> bool <ISA_LIT>PacketizerList :: promoteToDotNew ( MachineInstr * MI , SDep :: Kind DepType , MachineBasicBlock :: iterator & MII , const TargetRegisterClass * RC ) { assert ( DepType == SDep :: Data ) ; int NewOpcode ; if ( RC == & <STR_LIT> ) NewOpcode = HII -> getDotNewPredOp ( MI , MBPI


<s> if ( RC == & <STR_LIT> ) NewOpcode = HII -> getDotNewPredOp ( MI , MBPI ) ; else NewOpcode = HII -> getDotNewOp ( MI ) ; MI -> setDesc ( HII -> get


<s> if ( PacketSU -> isSucc ( PacketSUDep ) ) { for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { auto & Dep = PacketSU -> Succs [ i ] ; if ( Dep . getSUnit ( ) == PacketSUDep && Dep . getKind ( ) == SDep :: Anti && Dep


<s> bool <ISA_LIT>PacketizerList :: shouldAddToPacket ( const MachineInstr


<s> for ( auto & B : MF ) { MachineBasicBlock :: iterator BundleIt ; MachineBasicBlock :: instr_iterator NextI ; for ( auto I = B . instr_begin ( ) , E = B . instr_end ( ) ; I != E ; I = NextI ) { NextI = std :: next ( I


<s> bool Good = true ; if ( GlueToNewValueJump ) { MachineInstr * NvjMI = ++ MII ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) Good = tryAllocateResourcesForConstExt ( true ) ; bool ExtNvjMI = HII -> isExtended ( NvjMI ) || HII -> isConstExtended ( NvjMI ) ; if ( Good ) { if ( ResourceTracker -> canReserveResources ( NvjMI ) ) ResourceTracker -> reserveResources ( NvjMI ) ; else Good = false ; } if ( Good && ExtNvjMI ) Good = tryAllocateResourcesForConstExt ( true ) ; if ( ! Good ) { endPacket ( MBB , MI ) ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; tryAllocateResourcesForConstExt ( true ) ; } assert ( ResourceTracker -> canReserveResources ( NvjMI ) ) ; ResourceTracker -> reserveResources ( NvjMI ) ; if ( ExtNvjMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; reserveResourcesForConstExt ( )


<s> if ( isImplicitDependency ( PI , DepReg ) ) return false ; const MCInstrDesc & MCID = PI -> getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) if ( HII -> isCondInst ( MI ) || MI -> isReturn ( ) ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = HII -> getDotNewOp ( MI ) ; const MCInstrDesc & D = HII -> get ( NewOpcode ) ; MachineInstr * NewMI = MF . CreateMachineInstr ( D , DebugLoc ( ) ) ; bool ResourcesAvailable = ResourceTracker -> canReserveResources ( NewMI ) ; MF . DeleteMachineInstr (


<s> if ( predRegClass == & <STR_LIT> ) break ; } assert ( ( predRegClass == & <STR_LIT> ) && <STR_LIT> ) ; for ( auto & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; predRegNumDst = MO . getReg ( ) ; predRegClass = HRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) break ; } assert ( ( predRegClass == & <STR_LIT> ) && <STR_LIT> ) ; if ( predRegNumDst != predRegNumSrc || HII -> isDotNewInst ( PacketMI ) != HII -> isDotNewInst ( MI ) || getPredicateSense ( MI , HII ) != getPredicateSense ( PacketMI , HII ) ) return false ; } unsigned StartCheck = <NUM_LIT> ; for ( auto I : CurrentPacketMIs ) { SUnit * TempSU = MIToSUnit . find ( I ) -> second ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( auto & MO : MI -> operands ( ) ) if ( MO . isReg ( ) && TempSU -> getInstr ( ) -> modifiesRegister ( MO . getReg ( ) , HRI ) ) return false ; } if ( ! HII -> isPostIncrement ( MI ) ) { for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) - <NUM_LIT> ; opNum ++ ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) == DepReg ) return false ; } } for ( auto & MO : PacketMI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO . isImplicit ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( R == DepReg || HRI -> isSuperRegister ( DepReg , R ) ) return false ; } for ( auto & MO : MI -> operands ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) && MO . isImplicit ( ) &&


<s> OldPacketMIs = CurrentPacketMIs ; VLIWPacketizerList :: endPacket ( MBB , MI


<s> for ( auto & Op : MI -> operands ( ) ) { if ( Op . isReg ( ) && Op . getReg ( ) && Op . isUse ( ) && <STR_LIT> . contains ( Op . getReg ( ) ) ) return Op . getReg ( ) ; } llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT>


<s> static PredicateKind getPredicateSense ( const MachineInstr * MI , const <ISA_LIT>InstrInfo * HII ) { if ( ! HII -> isPredicated ( MI ) ) return PK_Unknown ; if ( HII -> isPredicatedTrue ( MI ) ) return PK_True ; return


<s> if ( ! HII -> isPredicated ( MI ) ) return PK_Unknown ; if ( HII -> isPredicatedTrue ( MI ) ) return PK_True ; return


<s> if ( HII -> isLoopN ( I ) && isBadForLoopN ( J ) ) return true ; if ( HII -> isLoopN ( J ) && isBadForLoopN ( I ) ) return true ; return HII -> isDeallocRet ( I ) && ( J -> isBranch ( ) || J ->


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO . isDead ( ) ) continue ; DeadDefs [ MO . getReg ( ) ] = true ; } for ( auto & MO : J -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO .


<s> if ( MI -> isCFIInstruction ( ) ) return false ; if ( MI -> isInlineAsm ( ) ) return false ; if ( MI -> isImplicitDef ( ) ) return false ; const MCInstrDesc & TID = MI -> getDesc ( ) ; auto * IS = ResourceTracker -> getInstrItins ( ) -> beginStage ( TID . getSchedClass ( ) ) ; unsigned FuncUnits = IS -> getUnits (


<s> if ( canPromoteToDotCur ( J , SUJ , DepReg , II , RC ) ) if ( promoteToDotCur ( J , DepType , II , RC ) ) continue ; } if ( DepType == SDep :: Data && HII -> isDotCurInst ( J ) ) { if ( HII -> isV60VectorInstruction ( I ) ) continue ; } if ( DepType == SDep :: Data ) { if ( canPromoteToDotNew ( I , SUJ , DepReg , II , RC ) ) { if ( promoteToDotNew ( I , DepType , II , RC ) ) { PromotedToDotNew = true ; continue ; } } if ( HII -> isNewValueJump ( I ) ) continue ; } if ( HII -> isPredicated ( I ) && HII -> isPredicated ( J ) && arePredicatesComplements ( I , J ) ) { auto Itr = std :: find ( IgnoreDepMIs . begin ( ) , IgnoreDepMIs . end ( ) , J ) ; if ( Itr != IgnoreDepMIs . end ( ) ) { Dependence = true ; return false ; } IgnoreDepMIs . push_back ( I ) ; continue ; } if ( isDirectJump ( I ) && ! J -> isBranch ( ) && ! J -> isCall ( ) && DepType == SDep :: Order ) continue ; if ( I -> isConditionalBranch ( ) && DepType != SDep :: Data && DepType != SDep :: Output ) continue ; if ( DepType == SDep :: Output ) { unsigned DepReg = SUJ -> Succs [ i ] . getReg ( ) ; if ( ! I -> definesRegister ( DepReg ) && ! J -> definesRegister ( DepReg ) ) continue ; FoundSequentialDependence = true ; break ; } if ( DepType == SDep :: Order ) { if ( ! PacketizeVolatiles ) { bool OrdRefs = I -> hasOrderedMemoryRef ( ) || J -> hasOrderedMemoryRef ( ) ; if ( OrdRefs ) { FoundSequentialDependence = true ; break ; } } bool LoadJ = J -> mayLoad ( ) , StoreJ = J -> mayStore ( ) ; bool LoadI = I -> mayLoad ( ) , StoreI = I ->


<s> if ( MI -> isEHLabel ( ) || MI -> isCFIInstruction ( ) ) return true ; if ( MI -> isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; if ( isSchedBarrier ( MI ) ) return true ; if ( HII -> isSolo (


<s> if ( MI -> isEHLabel ( ) || MI -> isCFIInstruction ( ) ) return true ; if ( MI -> isInlineAsm ( )


<s> for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { auto & Dep = PacketSU -> Succs [ i ] ; if ( Dep . getSUnit ( ) == PacketSUDep && Dep . getKind ( ) == SDep

:: Anti && Dep . getReg ( ) == DepReg ) return true ;


<s> auto End = MB . end ( ) ; auto MI = MB . begin ( ) ; while ( MI != End ) { auto NextI = std :: next ( MI ) ; if ( MI -> isKill ( ) ) { MB . erase ( MI ) ; End = MB . end ( ) ; } MI = NextI ; } } for ( auto & MB : MF ) { auto Begin = MB . begin ( ) , End = MB . end ( ) ; while ( Begin != End ) { MachineBasicBlock :: iterator RB = Begin ; while ( RB != End && HII -> isSchedulingBoundary ( RB , & MB , MF ) ) ++ RB ; MachineBasicBlock :: iterator RE = RB ; while ( RE != End && ! HII -> isSchedulingBoundary ( RE , & MB , MF ) ) ++ RE ; if ( RE != End ) ++ RE ; if ( RB != End ) Packetizer . PacketizeMIs ( & MB , RB , RE ) ; Begin = RE


<s> auto * ExtMI = MF . CreateMachineInstr ( HII -> get ( <STR_LIT> ) , DebugLoc ( ) ) ; bool Avail = ResourceTracker -> canReserveResources ( ExtMI


<s> <ISA_LIT>PacketizerList :: <ISA_LIT>PacketizerList ( MachineFunction & MF , MachineLoopInfo & MLI , const MachineBranchProbabilityInfo * MBPI ) : VLIWPacketizerList ( MF


<s> ++ MI ; } } for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { unsigned RemainingCount = MBB -> size ( ) ; for ( MachineBasicBlock :: iterator RegionEnd = MBB -> end ( ) ; RegionEnd != MBB -> begin ( ) ; ) { MachineBasicBlock :: iterator I = RegionEnd ; for ( ; I != MBB -> begin ( ) ; -- I , -- RemainingCount ) { if ( TII -> isSchedulingBoundary ( std :: prev ( I ) , & * MBB , Fn ) ) break ; } I = MBB -> begin ( ) ; if ( I == RegionEnd ) { RegionEnd = std :: prev ( RegionEnd ) ; -- RemainingCount ; continue ; } if ( I == std :: prev ( RegionEnd ) ) { RegionEnd = std :: prev ( RegionEnd ) ; continue ; } Packetizer . PacketizeMIs ( & * MBB ,


<s> if ( HII -> isDotCurInst ( MI ) && ! HII -> mayBeCurLoad ( MI ) ) return false ; if ( ! HII -> mayBeCurLoad ( MI ) ) return false ; if ( PacketSU -> getInstr ( ) -> isInlineAsm ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ; dbgs ( ) << <STR_LIT> ; ) ; MachineInstr & MJ = * MII ; DEBUG ( { dbgs ( ) << <STR_LIT> ; MJ . dump (


<s> B . splice ( InsertPt , & B , MI ) ; MachineBasicBlock :: const_instr_iterator I = BundleIt . getInstrIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = B . instr_end ( ) ; unsigned Size = <NUM_LIT> ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) ++ Size ; if ( Size > <NUM_LIT> ) return BundleIt ; MachineBasicBlock :: iterator NextIt = std :: next ( BundleIt ) ; MachineInstr * SingleI = BundleIt -> getNextNode ( ) ; SingleI -> unbundleFromPred


<s> if ( ! MI -> isInsideBundle ( ) ) continue ; bool InsertBeforeBundle ; if ( MI -> isInlineAsm ( ) ) InsertBeforeBundle = ! hasWriteToReadDep ( * MI , * BundleIt , HRI ) ; else if ( MI -> isDebugValue ( ) ) InsertBeforeBundle = true ; else continue


<s> NextI = std :: next ( I ) ; MachineInstr * MI = & * I ; if ( MI -> isBundle ( ) ) BundleIt = I ; if ( ! MI -> isInsideBundle ( ) ) continue ; bool InsertBeforeBundle ; if ( MI -> isInlineAsm ( ) ) InsertBeforeBundle = ! hasWriteToReadDep ( * MI , * BundleIt , HRI ) ; else if ( MI -> isDebugValue ( )


<s> if ( MI . isInlineAsm ( ) ) return MJ . isInlineAsm ( ) || MJ . isBranch ( ) || MJ . isBarrier ( ) || MJ . isCall ( ) || MJ . isTerminator ( ) ; switch ( MI . getOpcode ( ) ) { case ( <STR_LIT> ) : case ( <STR_LIT> ) : case ( <STR_LIT> ) : case ( <STR_LIT>


<s> if ( canPromoteToDotCur ( J , SUJ , DepReg , II , RC ) ) if ( promoteToDotCur ( J , DepType , II , RC ) ) continue ; } if ( DepType == SDep :: Data && HII -> isDotCurInst ( J ) ) { if ( HII -> isV60VectorInstruction ( I ) ) continue ; } if ( DepType == SDep :: Data ) { if ( canPromoteToDotNew ( I , SUJ , DepReg , II , RC ) ) { if ( promoteToDotNew ( I , DepType , II , RC ) ) { PromotedToDotNew = true ; continue ; } } if ( HII -> isNewValueJump ( I ) ) continue ; } if ( HII -> isPredicated ( I ) && HII -> isPredicated ( J ) && arePredicatesComplements ( I , J ) ) { auto Itr = find ( IgnoreDepMIs , & J ) ; if ( Itr != IgnoreDepMIs . end ( ) ) { Dependence = true ; return false ; } IgnoreDepMIs . push_back ( & I ) ; continue ; } if ( isDirectJump ( I ) && ! J . isBranch ( ) && ! J . isCall ( ) && DepType == SDep :: Order ) continue ; if ( I . isConditionalBranch ( ) && DepType != SDep :: Data && DepType != SDep :: Output ) continue ; if ( DepType == SDep :: Output ) { unsigned DepReg = SUJ -> Succs [ i ] . getReg ( ) ; if ( ! I . definesRegister ( DepReg ) && ! J . definesRegister ( DepReg ) ) continue ; FoundSequentialDependence = true ; break ; } if ( DepType == SDep :: Order ) { if ( ! PacketizeVolatiles ) { bool OrdRefs = I . hasOrderedMemoryRef ( ) || J . hasOrderedMemoryRef ( ) ; if ( OrdRefs ) { FoundSequentialDependence = true ; break ; } } bool LoadJ = J . mayLoad ( ) , StoreJ = J . mayStore ( ) ; bool LoadI = I . mayLoad ( ) , StoreI = I . mayStore ( ) ; if ( StoreJ ) { if ( LoadI ) { FoundSequentialDependence = true ; break ; } } else if ( ! LoadJ || ( ! LoadI && ! StoreI ) ) { FoundSequentialDependence = true ; break ; } continue ; } if ( DepType == SDep :: Data && J . getOpcode ( ) == <STR_LIT> ) { unsigned Opc = I . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I . getOperand ( <NUM_LIT> ) . getReg ( ) == HRI -> getStackRegister ( ) ) { GlueAllocframeStore = useCallersSP ( I ) ; if ( GlueAllocframeStore


<s> <ISA_LIT>PacketizerList Packetizer ( MF , MLI , AA , MBPI ) ; assert ( Packetizer . getResourceTracker ( ) && <STR_LIT> ) ; for ( auto & MB : MF ) { auto End = MB . end ( ) ; auto MI = MB . begin ( ) ; while ( MI != End ) { auto NextI = std :: next ( MI ) ; if ( MI -> isKill ( ) ) { MB . erase ( MI ) ; End = MB . end ( ) ; } MI = NextI ; } } for ( auto & MB : MF ) { auto Begin = MB . begin ( ) , End = MB . end ( ) ; while ( Begin != End ) { MachineBasicBlock :: iterator RB = Begin ; while ( RB != End && HII -> isSchedulingBoundary ( * RB , & MB , MF ) ) ++ RB ; MachineBasicBlock :: iterator RE = RB ; while ( RE != End && ! HII -> isSchedulingBoundary ( * RE


<s> const MachineInstr & PI = * PacketSU -> getInstr ( ) ; if ( PI . isInlineAsm ( ) ) return false ; if ( PI . isImplicitDef ( ) ) return false ; if ( isImplicitDependency ( PI , DepReg ) ) return false ; const MCInstrDesc & MCID = PI . getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) if ( HII -> isCondInst ( MI ) || HII -> isJumpR ( MI ) ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII

-> mayBeNewStore ( MI ) ) return false ;


<s> if ( DepType == SDep :: Data ) { if ( canPromoteToDotNew ( I , SUJ , DepReg , II , RC ) ) { if ( promoteToDotNew ( I , DepType , II , RC ) ) { PromotedToDotNew = true ; continue ; } } if ( HII -> isNewValueJump ( I ) ) continue ; } if ( HII -> isPredicated ( I ) && HII -> isPredicated ( J ) && arePredicatesComplements ( I , J ) ) { auto Itr = find ( IgnoreDepMIs , & J ) ; if ( Itr != IgnoreDepMIs . end ( ) ) { Dependence = true ; return false ; } IgnoreDepMIs . push_back ( & I ) ; continue ; } if ( isDirectJump ( I ) && ! J . isBranch ( ) && ! J . isCall ( ) && DepType == SDep :: Order ) continue ; if ( I . isConditionalBranch ( ) && DepType != SDep :: Data && DepType != SDep :: Output ) continue ; if ( DepType == SDep :: Output ) { unsigned DepReg = SUJ -> Succs [ i ] . getReg ( ) ; if ( ! I . definesRegister ( DepReg ) && ! J . definesRegister ( DepReg ) ) continue ; FoundSequentialDependence = true ; break ; } if ( DepType == SDep :: Order ) { if ( ! PacketizeVolatiles ) { bool OrdRefs = I . hasOrderedMemoryRef ( ) || J . hasOrderedMemoryRef ( ) ; if ( OrdRefs ) { FoundSequentialDependence = true ; break ; } } bool LoadJ = J . mayLoad ( ) , StoreJ = J . mayStore ( ) ; bool LoadI = I . mayLoad ( ) , StoreI = I . mayStore ( ) ; if ( StoreJ ) { if ( LoadI ) { FoundSequentialDependence = true ; break ; } } else if ( ! LoadJ || ( ! LoadI && ! StoreI ) ) { FoundSequentialDependence = true ; break ; } continue ; } if ( DepType == SDep :: Data && J . getOpcode ( ) == <STR_LIT> ) { unsigned Opc = I . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I . getOperand ( <NUM_LIT> ) . getReg ( ) == HRI -> getStackRegister ( ) ) { GlueAllocframeStore = useCallersSP ( I ) ; if ( GlueAllocframeStore ) continue ; } default : break ; } } if ( DepType == SDep :: Anti && J . isCall ( ) ) { for ( const MCPhysReg * P = J . getDesc ( ) . ImplicitDefs ; P && * P ; ++ P ) { if ( ! I . modifiesRegister ( * P , HRI ) ) continue ; FoundSequentialDependence = true ; break ; } } if ( DepType != SDep :: Anti ) { FoundSequentialDependence =


<s> bool <ISA_LIT>PacketizerList :: isNewifiable ( const MachineInstr & MI , const TargetRegisterClass * NewRC ) { if ( NewRC == & <STR_LIT> ) if ( HII -> isV60VectorInstruction ( MI ) && MI . mayStore ( ) ) return false ; return HII -> isCondInst ( MI ) || HII -> isJumpR ( MI ) || HII ->


<s> const <ISA_LIT>RegisterInfo * QRI = ( const <ISA_LIT>RegisterInfo * ) TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; if ( ! QRI -> Subtarget . hasV4TOps ( ) || ! QII -> mayBeNewStore ( MI ) ) return false ; MachineInstr * PacketMI = PacketSU -> getInstr (


<s> } if ( QII -> isPredicated ( PacketMI ) ) { if ( ! QII -> isPredicated ( MI ) ) return false ; unsigned predRegNumSrc = <NUM_LIT> ; unsigned predRegNumDst = <NUM_LIT> ; const TargetRegisterClass * predRegClass = nullptr ; for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) { if ( PacketMI -> getOperand ( opNum ) . isReg ( ) ) predRegNumSrc = PacketMI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumSrc ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) ) predRegNumDst = MI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || QII -> isDotNewInst ( PacketMI ) != QII -> isDotNewInst ( MI ) || getPredicateSense ( MI , QII ) != getPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit [ * VI ] ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( )


<s> bool <ISA_LIT>PacketizerList :: IsCallDependent ( MachineInstr * MI , SDep :: Kind DepType , unsigned DepReg ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; const <ISA_LIT>RegisterInfo * QRI = ( const <ISA_LIT>RegisterInfo * ) TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; if ( DepReg == QRI -> getRARegister


<s> return ( ( MI -> getOpcode ( ) == <STR_LIT> ) || ( MI ->


<s> bool <ISA_LIT>PacketizerList :: canPromoteToDotNew ( const MachineInstr & MI , const SUnit * PacketSU , unsigned DepReg , MachineBasicBlock :: iterator & MII , const TargetRegisterClass * RC ) { if ( HII -> isDotNewInst ( MI ) && ! HII -> mayBeNewStore ( MI ) ) return false ; if ( ! isNewifiable ( MI , RC ) ) return false ; const MachineInstr & PI = * PacketSU -> getInstr ( ) ; if ( PI . isInlineAsm ( ) ) return false ; if ( PI . isImplicitDef ( ) ) return false ; if ( isImplicitDependency ( PI , true , DepReg ) || isImplicitDependency ( MI , false , DepReg ) ) return false ; const MCInstrDesc & MCID = PI . getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = HII -> getDotNewOp ( MI ) ; const MCInstrDesc & D = HII -> get ( NewOpcode ) ; MachineInstr * NewMI = MF . CreateMachineInstr ( D , DebugLoc ( ) ) ; bool ResourcesAvailable = ResourceTracker -> canReserveResources ( * NewMI ) ; MF . deleteMachineInstr (


<s> MachineBasicBlock :: iterator <ISA_LIT>PacketizerList :: addToPacket ( MachineInstr * MI ) { MachineBasicBlock :: iterator MII = MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; if ( GlueToNewValueJump ) { ++ MII ; MachineInstr * nvjMI = MII ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources ( MI ) ; if ( ( QII -> isExtended ( MI ) || QII -> isConstExtended ( MI ) ) && ! tryAllocateResourcesForConstExt ( MI ) ) { endPacket ( MBB , MI ) ; ResourceTracker -> reserveResources ( MI ) ; assert ( canReserveResourcesForConstExt ( MI ) && <STR_LIT> ) ; reserveResourcesForConstExt ( MI ) ; assert ( canReserveResourcesForConstExt ( MI ) && <STR_LIT> ) ; reserveResourcesForConstExt ( nvjMI ) ; assert ( ResourceTracker -> canReserveResources (


<s> for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { if ( PacketSU -> Succs [ i ] . getSUnit ( ) == SU && PacketSU -> Succs [ i ] . getKind ( ) == SDep :: Data && <STR_LIT> . contains ( PacketSU -> Succs [ i ] . getReg ( ) ) && RestrictingDepExistInPacket ( * VIN , PacketSU -> Succs [ i ] . getReg ( ) , MIToSUnit ) ) { return false ; } } } } unsigned PReg1 = getPredicatedRegister ( MI1 , QII ) ; unsigned PReg2 = getPredicatedRegister ( MI2 , QII ) ; return ( ( PReg1 == PReg2 ) && <STR_LIT> . contains ( PReg1 ) && <STR_LIT> . contains ( PReg2 ) && ( getPredicateSense ( MI1 , QII ) != getPredicateSense ( MI2 , QII ) ) && ( QII -> isDotNewInst ( MI1 ) == QII ->


<s> if ( RC == & <STR_LIT> && isCondInst ( MI ) ) return true ; else if ( RC != & <STR_LIT> && ! QII -> mayBeNewStore ( MI ) ) return false ; else { int NewOpcode = QII -> GetDotNewOp ( MI ) ; const MCInstrDesc & desc = QII -> get ( NewOpcode ) ; DebugLoc dl ; MachineInstr * NewMI = MI -> getParent ( ) -> getParent ( ) -> CreateMachineInstr ( desc , dl ) ; bool ResourcesAvailable = ResourceTracker ->


<s> bool <ISA_LIT>PacketizerList :: canReserveResourcesForConstExt ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; assert ( ( QII -> isExtended ( MI ) || QII ->

isConstExtended ( MI ) ) && <STR_LIT> ) ;


<s> for ( const MCPhysReg * CSR = TRI -> getCalleeSavedRegs ( MI ->


<s> for ( const MCPhysReg * CSR = TRI -> getCalleeSavedRegs ( MI -> getParent ( ) -> getParent ( ) ) ; * CSR ; ++ CSR ) { unsigned CalleeSavedReg = * CSR ; if ( MI -> modifiesRegister ( CalleeSavedReg , TRI ) ) return true ; } return false


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU )


<s> const char * getPassName ( ) const override { return


<s> assert ( QII -> isPostIncrement ( MI ) && <STR_LIT> ) ; DenseMap < unsigned , unsigned > DefRegsSet ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isDef ( ) ) { DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] = <NUM_LIT> ; } for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isUse ( ) ) { if ( DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] ) { return MI -> getOperand ( opNum ) ; } } if ( MI -> getDesc ( ) . mayLoad (


<s> assert ( QII -> isPostIncrement ( MI ) && <STR_LIT> ) ; DenseMap < unsigned , unsigned > DefRegsSet ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isDef ( ) ) { DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] = <NUM_LIT> ; } for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isUse ( ) ) { if ( DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] ) { return MI -> getOperand ( opNum ) ; } } if ( MI -> getDesc ( ) . mayLoad ( ) ) { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return ( MI -> getOperand ( <NUM_LIT> ) ) ; } if ( MI -> getDesc ( ) . mayStore ( ) ) { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) &&


<s> for ( MachineInstr :: mop_iterator OI = MI -> operands_begin ( ) , OE = MI -> operands_end ( ) ; OI != OE ; ++ OI ) { MachineOperand & Op = * OI ; if ( Op . isReg ( ) && Op . getReg ( ) && Op . isUse ( ) && <STR_LIT> . contains ( Op . getReg ( ) ) ) return Op


<s> static PredicateKind getPredicateSense ( MachineInstr * MI , const


<s> return ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT>


<s> static MachineOperand & GetStoreValueOperand ( MachineInstr *


<s> initialize<ISA_LIT>PacketizerPass ( * PassRegistry :: getPassRegistry ( )


<s> <ISA_LIT>PacketizerList :: <ISA_LIT>PacketizerList ( MachineFunction & MF , MachineLoopInfo & MLI , const MachineBranchProbabilityInfo * MBPI ) : VLIWPacketizerList ( MF , MLI , true ) { this -> MBPI


<s> bool <ISA_LIT>PacketizerList :: ignorePseudoInstruction ( MachineInstr * MI , MachineBasicBlock * MBB ) { if ( MI -> isDebugValue ( ) ) return true ; if ( MI -> isCFIInstruction ( ) ) return false ; if ( MI -> isInlineAsm ( ) ) return false ; const MCInstrDesc & TID = MI -> getDesc ( ) ; unsigned SchedClass = TID . getSchedClass ( ) ; const InstrStage * IS = ResourceTracker -> getInstrItins ( )


<s> PromotedToDotNew = false ; GlueToNewValueJump = false ; GlueAllocframeStore = false ; FoundSequentialDependence =


<s> } if ( QII -> isDeallocRet ( MI ) ) { if ( DepReg == QRI -> getFrameRegister ( ) || DepReg == QRI -> getStackRegister ( ) ) return true ; } const TargetRegisterClass * RC = QRI -> getMinimalPhysRegClass ( DepReg ) ; if ( RC == & <STR_LIT> ) { return true ; } if ( IsIndirectCall ( MI ) && ( DepType == SDep :: Data


<s> if ( TID . isConditionalBranch ( ) || QII -> isConditionalTransfer ( MI ) || QII -> isConditionalALU32 ( MI

) || QII -> isConditionalLoad ( MI ) || QII -> isConditionalStore ( MI ) ) {


<s> const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; const MCInstrDesc & TID = MI -> getDesc ( ) ; if ( TID . isConditionalBranch ( ) || QII -> isConditionalTransfer ( MI ) || QII -> isConditionalALU32 ( MI ) || QII -> isConditionalLoad ( MI ) || QII -> isConditionalStore


<s> return ( MI -> getDesc ( ) . isTerminator ( ) || MI ->


<s> static bool IsDirectJump ( MachineInstr * MI ) { return ( MI -> getOpcode ( )


<s> bool <ISA_LIT>PacketizerList :: isLegalToPruneDependencies ( SUnit * SUI , SUnit * SUJ ) { MachineInstr * I = SUI -> getInstr ( ) ; assert ( I && SUJ -> getInstr ( ) && <STR_LIT> ) ; const unsigned FrameSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; if ( Dependence ) { if ( PromotedToDotNew ) { DemoteToDotOld ( I ) ; } if ( GlueAllocframeStore


<s> bool <ISA_LIT>PacketizerList :: isNewifiable ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const


<s> bool <ISA_LIT>PacketizerList :: isNewifiable ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = (


<s> bool isPromotedToDotNew ( ) const { return


<s> return ( DepType == SDep :: Data || DepType ==

SDep :: Anti || DepType == SDep :: Output ) ;


<s> static bool IsRegDependence ( const SDep :: Kind DepType ) { return ( DepType == SDep :: Data || DepType == SDep :: Anti || DepType ==


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT>


<s> if ( MI -> isInlineAsm ( ) ) return true ; if ( IsSchedBarrier ( MI ) )


<s> bool <ISA_LIT>PacketizerList :: PromoteToDotNew ( MachineInstr * MI , SDep :: Kind DepType , MachineBasicBlock :: iterator & MII , const TargetRegisterClass * RC ) { assert ( DepType == SDep :: Data ) ; const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; int


<s> int NewOpcode ; if ( RC == & <STR_LIT> ) NewOpcode = QII -> GetDotNewPredOp ( MI , MBPI ) ; else NewOpcode = QII -> GetDotNewOp ( MI ) ; MI -> setDesc ( QII ->


<s> MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( PseudoMI ) ; } else { MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( PseudoMI


<s> const TargetInstrInfo * TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; const MachineBranchProbabilityInfo * MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; <ISA_LIT>PacketizerList Packetizer ( Fn , MLI , MBPI ) ; assert ( Packetizer . getResourceTracker ( ) && <STR_LIT> ) ; for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { MachineBasicBlock :: iterator End = MBB -> end ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; while ( MI != End


<s> for ( auto I : EM ) { auto FS = DefM . find ( I . second . Reg ) ; if ( FS == DefM . end ( ) || FS -> second . empty ( ) ) continue ; RDefMap [ I . second ] [ SA . Id ] = FS -> second . top ( ) -> Id ; RDefMap [ I . first ]


<s> NodeId RDefSR_SA = RDefSR [ SA . Id ] ; for ( NodeId N = DA . Addr -> getReachedUse ( ) , NextN ; N ; N = NextN ) { auto UA = DFG . addr < UseNode * > ( N ) ; NextN = UA . Addr -> getSibling ( ) ; uint16_t F = UA . Addr -> getFlags ( ) ; if ( ( F & NodeAttrs :: PhiRef ) || ( F & NodeAttrs :: Fixed ) ) continue ; if ( UA . Addr -> getRegRef ( DFG ) != DR ) continue ; NodeAddr < InstrNode * > IA = UA . Addr -> getOwner ( DFG ) ; assert ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) ; if ( RDefSR [ IA . Id ] != RDefSR_SA ) continue ; MachineOperand & Op = UA . Addr -> getOp ( ) ; if ( Op . isTied ( ) ) continue ; if ( trace ( ) ) { dbgs ( ) << <STR_LIT> << Print < RegisterRef > ( DR , DFG ) << <STR_LIT> << Print < RegisterRef > ( SR , DFG ) << <STR_LIT> << * NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; } unsigned NewReg = MinPhysReg ( SR ) ; Op . setReg ( NewReg ) ; Op . setSubReg ( <NUM_LIT> ) ; DFG . unlinkUse ( UA , false ) ; if ( RDefSR_SA != <NUM_LIT> ) { UA . Addr -> linkToDef ( UA . Id , DFG . addr < DefNode * > ( RDefSR_SA ) ) ; } else { UA . Addr -> setReachingDef ( <NUM_LIT> ) ; UA . Addr -> setSibling ( <NUM_LIT> ) ; } Changed = true ; if ( HasLimit && CpCount >= CpLimit ) break ; CpCount ++ ; auto FC = CopyMap . find ( IA . Id ) ; if ( FC != CopyMap


<s> auto MinPhysReg = [ this ] ( RegisterRef RR ) -> unsigned { const TargetRegisterInfo & TRI = DFG . getTRI ( ) ; const TargetRegisterClass & RC = * TRI . getMinimalPhysRegClass ( RR . Reg ) ; if ( ( RC . LaneMask & RR . Mask ) == RC . LaneMask ) return RR . Reg ; for ( MCSubRegIndexIterator S ( RR . Reg , & TRI ) ; S . isValid ( ) ; ++ S ) if ( RR . Mask == TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ) return S . getSubReg ( ) ; llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ; } ; for ( auto C : Copies ) { if ( HasLimit && CpCount >= CpLimit ) break ; auto SA = DFG . addr < InstrNode * > ( C ) ; auto FS = CopyMap . find ( SA . Id ) ; if ( FS == CopyMap . end ( ) ) continue ; EqualityMap & EM = FS -> second ; for ( NodeAddr < DefNode * > DA : SA . Addr -> members_if ( DFG . IsDef , DFG ) ) { RegisterRef DR = DA . Addr -> getRegRef ( DFG ) ; auto FR = EM . find ( DR ) ; if ( FR == EM . end ( ) ) continue ; RegisterRef SR = FR -> second ; if ( DR == SR ) continue ; auto & RDefSR = RDefMap [ SR ] ; NodeId RDefSR_SA = RDefSR [ SA . Id ] ; for ( NodeId N = DA . Addr -> getReachedUse ( ) , NextN ; N ; N = NextN ) { auto UA = DFG . addr < UseNode * > ( N ) ; NextN = UA . Addr -> getSibling ( ) ; uint16_t F = UA . Addr -> getFlags ( ) ; if ( ( F & NodeAttrs :: PhiRef ) || ( F & NodeAttrs :: Fixed ) ) continue ; if ( UA . Addr -> getRegRef ( DFG ) != DR ) continue ; NodeAddr < InstrNode * > IA = UA .


<s> EqualityMap EM ; if ( interpretAsCopy ( SA . Addr -> getCode ( ) , EM ) ) recordCopy ( SA , EM ) ; } updateMap ( IA ) ; DFG . pushDefs ( IA , DefM ) ; } MachineDomTreeNode * N = MDT . getNode ( B ) ; for ( auto I : * N ) Changed |= scanBlock ( I ->


<s> for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) { NodeAddr < StmtNode * > SA = IA ; EqualityMap EM ; if ( interpretAsCopy ( SA . Addr -> getCode ( ) , EM ) ) recordCopy ( SA , EM ) ; } updateMap ( IA ) ; DFG . pushDefs ( IA , DefM ) ; } MachineDomTreeNode * N = MDT . getNode ( B


<s> Common = true ; break ; } if ( ! Common ) return ; for ( auto & R : RDefMap ) { if ( ! RRs . count ( R . first ) ) continue ; auto F = DefM . find ( R . first . Reg ) ; if ( F == DefM . end ( ) || F -> second . empty


<s> CopyMap . insert ( std :: make_pair ( SA . Id , EM ) ) ; Copies . push_back ( SA . Id )


<s> void CopyPropagation :: recordCopy ( NodeAddr < StmtNode * >


<s> for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) { NodeAddr < StmtNode * > SA = IA ; EqualityMap EM ; if ( interpretAsCopy ( SA . Addr -> getCode ( ) , EM ) ) recordCopy ( SA , EM ) ; } } MachineDomTreeNode * N = MDT . getNode ( B ) ; for ( auto I : * N ) Changed |= scanBlock ( I ->


<s>
bool
CopyPropagation
::
run
(
)
{
scanBlock
(
&
DFG
.
getMF
(
)
.
front
(
)
)
;
if
(
trace
(
)
)
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
I
:
Copies
)
{
dbgs
(
)
<<
<STR_LIT>
<<
*
DFG
.
addr
<
StmtNode
*
>
(
I
)
.
Addr
->
getCode
(
)
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
J
:
CopyMap
[
I
]
)
dbgs
(
)
<<
' '
<<
Print
<
RegisterRef
>
(
J
.
first
,
DFG
)
<<
'='
<<
Print
<
RegisterRef
>
(
J
.
second
,
DFG
)
;
dbgs
(
)
<<
<STR_LIT>
;
}
}
bool
Changed
=
false
;
bool
HasLimit
=
CpLimit
.
getNumOccurrences
(
)
>
<NUM_LIT>
;
auto
MinPhysReg
=
[
this
]
(
RegisterRef
RR
)
->
unsigned
{
const
TargetRegisterInfo
&
TRI
=
DFG
.
getTRI
(
)
;
const
TargetRegisterClass
&
RC
=
*
TRI
.
getMinimalPhysRegClass
(
RR
.
Reg
)
;
if
(
(
RC
.
LaneMask
&
RR
.
Mask
)
==
RC
.
LaneMask
)
return
RR
.
Reg
;
for
(
MCSubRegIndexIterator
S
(
RR
.
Reg
,
&
TRI
)
;
S
.
isValid
(
)
;
++
S
)
if
(
RR
.
Mask
==
TRI
.
getSubRegIndexLaneMask
(
S
.
getSubRegIndex
(
)
)
)
return
S
.
getSubReg
(
)
;
llvm_unreachable
(
<STR_LIT>
)
;
return
<NUM_LIT>
;
}
;
for
(
auto
C
:
Copies
)
{
if
(
HasLimit
&&
CpCount
>=
CpLimit
)
break
;
auto
SA
=
DFG
.
addr
<
InstrNode
*
>
(
C
)
;
auto
FS
=
CopyMap
.
find
(
SA
.
Id
)
;
if
(
FS
==
CopyMap
.
end
(
)
)
continue
;
EqualityMap
&
EM
=
FS
->
second
;
for
(
NodeAddr
<
DefNode
*
>
DA
:
SA
.
Addr
->
members_if
(
DFG
.
IsDef
,
DFG
)
)
{
RegisterRef
DR
=
DA
.
Addr
->
getRegRef
(
DFG
)
;
auto
FR
=
EM
.
find
(
DR
)
;
if
(
FR
==
EM
.
end
(
)
)
continue
;
RegisterRef
SR
=
FR
->
second
;
if
(
DR
==
SR
)
continue
;
NodeId
AtCopy
=
getLocalReachingDef
(
SR
,
SA
)
;
for
(
NodeId
N
=
DA
.
Addr
->
getReachedUse
(
)
,
NextN
;
N
;
N
=
NextN
)
{
auto
UA
=
DFG
.
addr
<
UseNode
*
>
(
N
)
;
NextN
=
UA
.
Addr
->
getSibling
(
)
;
uint16_t
F
=
UA
.
Addr
->
getFlags
(
)
;
if
(
(
F
&
NodeAttrs
::
PhiRef
)
||
(
F
&
NodeAttrs
::
Fixed
)
)
continue
;
if
(
UA
.
Addr
->
getRegRef
(
DFG
)
!=
DR
)
continue
;
NodeAddr
<
InstrNode
*
>
IA
=
UA
.
Addr
->
getOwner
(
DFG


<s> const MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; RegisterRef DstR = DFG . makeRegRef ( Dst . getReg ( ) , Dst . getSubReg ( ) ) ; RegisterRef SrcR = DFG . makeRegRef ( Src . getReg ( ) , Src . getSubReg ( ) ) ; assert ( Register :: isPhysicalRegister ( DstR . Reg ) ) ; assert ( Register :: isPhysicalRegister ( SrcR . Reg ) ) ; const TargetRegisterInfo & TRI = DFG . getTRI ( ) ; if ( TRI . getMinimalPhysRegClass ( DstR . Reg ) != TRI . getMinimalPhysRegClass ( SrcR . Reg ) ) return false ; EM . insert ( std :: make_pair ( DstR , SrcR ) ) ; return true ; } case TargetOpcode :: REG_SEQUENCE : llvm_unreachable ( <STR_LIT> )


<s> if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) { NodeAddr < StmtNode * > SA = IA ; EqualityMap EM ; if ( interpretAsCopy ( SA . Addr -> getCode ( ) , EM ) ) recordCopy ( SA , EM ) ; } updateMap ( IA ) ; DFG . pushAllDefs ( IA , DefM ) ; } MachineDomTreeNode * N = MDT . getNode ( B ) ; for ( auto I : * N ) Changed |=


<s> switch ( Opc ) { case TargetOpcode :: COPY : { const MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; RegisterRef DstR = { Dst . getReg ( ) , Dst . getSubReg ( ) } ; RegisterRef SrcR = { Src . getReg ( ) , Src . getSubReg ( ) } ; if ( TargetRegisterInfo :: isVirtualRegister ( DstR . Reg ) ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcR . Reg ) ) return false ; MachineRegisterInfo & MRI = DFG . getMF ( ) . getRegInfo ( ) ; if ( MRI . getRegClass ( DstR . Reg ) != MRI . getRegClass ( SrcR . Reg ) ) return false ; } else if ( TargetRegisterInfo :: isPhysicalRegister ( DstR . Reg ) ) { if ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcR . Reg ) ) return false ; const TargetRegisterInfo & TRI = DFG . getTRI ( ) ; if ( TRI . getMinimalPhysRegClass ( DstR . Reg ) != TRI . getMinimalPhysRegClass ( SrcR . Reg ) ) return false ; } else { return false ; } EM . insert ( std :: make_pair ( DstR , SrcR ) ) ; return true ; } case TargetOpcode :: REG_SEQUENCE : { const MachineOperand & Dst = MI -> getOperand


<s> Copies . push_back ( SA . Id ) ; for ( auto I : EM ) { auto FS = DefM . find ( I . second ) ; if ( FS == DefM . end ( ) || FS -> second . empty ( ) ) continue ; RDefMap [ I . second ] [ SA . Id ]


<s> void CopyPropagation :: recordCopy ( NodeAddr < StmtNode * > SA , EqualityMap & EM ) { CopyMap . insert ( std :: make_pair ( SA . Id , EM ) ) ; Copies . push_back ( SA . Id ) ; for ( auto I : EM ) { auto FS = DefM . find ( I . second ) ; if ( FS == DefM . end ( ) || FS -> second . empty ( ) ) continue ; RDefMap [ I . second ] [ SA . Id ] = FS ->


<s> auto FS = CopyMap . find ( SA . Id ) ; if ( FS == CopyMap . end ( ) ) continue ; EqualityMap & EM = FS -> second ; for ( NodeAddr < DefNode * > DA : SA . Addr -> members_if ( DFG . IsDef , DFG ) ) { RegisterRef DR = DA . Addr -> getRegRef ( ) ; auto FR = EM . find ( DR ) ; if ( FR == EM . end ( ) ) continue ; RegisterRef SR = FR -> second ; if ( DR == SR ) continue ; auto & RDefSR = RDefMap [ SR ] ; NodeId RDefSR_SA = RDefSR [ SA . Id ] ; for ( NodeId N = DA . Addr -> getReachedUse ( ) , NextN ; N ; N = NextN ) { auto UA = DFG . addr < UseNode * > ( N ) ; NextN = UA . Addr -> getSibling ( ) ; uint16_t F = UA . Addr -> getFlags ( ) ; if ( ( F & NodeAttrs :: PhiRef ) || ( F & NodeAttrs :: Fixed ) ) continue ; if ( UA . Addr -> getRegRef ( ) != DR ) continue ; NodeAddr < InstrNode * > IA = UA . Addr -> getOwner ( DFG ) ; assert ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) ; if ( RDefSR [ IA . Id ] != RDefSR_SA ) continue ; MachineOperand & Op = UA . Addr -> getOp ( ) ; if ( Op . isTied ( ) ) continue ; if ( trace ( ) ) { dbgs ( ) << <STR_LIT> << Print < RegisterRef > ( DR , DFG ) << <STR_LIT> << Print < RegisterRef > ( SR , DFG ) << <STR_LIT> << * NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; } Op . setReg ( SR . Reg ) ; Op . setSubReg ( SR . Sub ) ; DFG . unlinkUse ( UA , false ) ; UA . Addr -> linkToDef ( UA . Id , DFG . addr < DefNode * > ( RDefSR_SA ) ) ; Changed = true ; if ( HasLimit && CpCount >= CpLimit ) break ; CpCount ++ ; auto FC = CopyMap . find ( IA . Id ) ; if ( FC != CopyMap . end ( ) ) { auto & M = FC -> second ; for ( auto & J : M ) { if ( J . second != DR ) continue ; J . second =


<s> RegisterRef SrcR = { Op1 . getReg ( ) , Op1 . getSubReg ( ) } ; auto FS = DefM . find ( SrcR ) ; if ( FS == DefM . end ( ) || FS -> second . empty ( ) ) return ; Copies . push_back ( SA . Id ) ; RDefMap [ SrcR ] [ SA . Id ] = FS -> second


<s> if ( UA . Addr -> getRegRef ( ) != DR0 ) continue ; NodeAddr < InstrNode * > IA = UA . Addr -> getOwner ( DFG ) ; assert ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) ; MachineInstr * MI = NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; if ( RDefMap [ UR0 ] [ IA . Id ] != RD0 ) continue ; MachineOperand & Op = UA . Addr -> getOp ( ) ; if ( Op . isTied ( ) ) continue ; if ( trace ( ) ) { dbgs ( ) << <STR_LIT> << Print < RegisterRef > ( DR0 , DFG ) << <STR_LIT> << Print < RegisterRef > ( UR0 , DFG ) << <STR_LIT> << * NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; } Op . setReg ( UR0 . Reg ) ; Op . setSubReg ( UR0 . Sub ) ; Changed = true ; if ( HasLimit && CpCount >= CpLimit ) break ; CpCount ++ ; if ( MI ->


<s> bool CopyPropagation :: scanBlock ( MachineBasicBlock * B ) { bool Changed = false ; auto BA = DFG . getFunc ( ) . Addr -> findBlock ( B , DFG ) ; DFG . markBlock ( BA . Id , DefM ) ; for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) { NodeAddr < StmtNode * > SA = IA ; MachineInstr * MI = SA . Addr -> getCode ( ) ; if ( MI -> isCopy ( ) ) recordCopy ( SA , MI ) ; } updateMap ( IA ) ; DFG . pushDefs ( IA , DefM ) ; } MachineDomTreeNode * N = MDT . getNode ( B ) ; for ( auto I : * N ) Changed |=


<s> bool CopyPropagation :: scanBlock ( MachineBasicBlock * B ) { bool Changed = false ; auto BA = DFG . getFunc ( ) . Addr -> findBlock ( B , DFG ) ; DFG . markBlock ( BA . Id , DefM ) ; for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) { NodeAddr < StmtNode * >


<s> if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > ( RA , DFG ) << '\n' ; if ( DFG . IsUse ( RA ) ) DFG . unlinkUse ( RA , true ) ; else if ( DFG . IsDef ( RA ) ) DFG . unlinkDef ( RA , true ) ; } for ( NodeAddr < InstrNode * > IA : DINs ) { NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; BA . Addr -> removeMember ( IA , DFG ) ; if ( ! DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) continue ; MachineInstr * MI = NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << *


<s> if ( MI -> mayStore ( ) || MI -> isBranch ( ) || MI -> isCall ( ) || MI -> isReturn ( ) ) return true ; if ( MI -> hasOrderedMemoryRef ( ) || MI -> hasUnmodeledSideEffects ( ) ) return true ; if ( MI -> isPHI ( ) ) return false ; for ( auto & Op : MI -> operands


<s> } else { llvm_unreachable ( <STR_LIT> ) ; return false ; } } auto UsesFirst = [ ] ( NodeAddr < RefNode * > A , NodeAddr < RefNode * > B ) -> bool { uint16_t KindA = A . Addr -> getKind ( ) , KindB = B . Addr -> getKind ( ) ; if ( KindA == NodeAttrs :: Use && KindB == NodeAttrs :: Def ) return true ; if ( KindA == NodeAttrs :: Def && KindB == NodeAttrs :: Use ) return false ; return A . Id < B . Id ; } ; llvm :: sort ( DRNs , UsesFirst ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> ; for ( NodeAddr < RefNode * > RA : DRNs ) { if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > (


<s> if ( MI -> mayStore ( ) || MI -> isBranch ( ) || MI -> isCall ( ) || MI -> isReturn ( ) ) return true ; if ( MI -> hasOrderedMemoryRef ( ) || MI -> hasUnmodeledSideEffects ( ) ) return true ; if ( MI -> isPHI ( ) ) return false ; for ( auto & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && MRI . isReserved ( Op . getReg ( ) ) ) return true ; return


<s> if ( MI -> mayStore ( ) || MI -> isBranch ( ) || MI -> isCall ( ) || MI -> isReturn ( ) ) return true ; if ( MI -> hasOrderedMemoryRef ( ) || MI -> hasUnmodeledSideEffects ( ) ) return true ; if ( MI -> isPHI ( ) )


<s> if ( KindA == NodeAttrs :: Use && KindB == NodeAttrs :: Def ) return true ; if ( KindA == NodeAttrs :: Def && KindB == NodeAttrs :: Use ) return false ; return A . Id < B . Id ; } ; llvm :: sort ( DRNs , UsesFirst ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> ; for ( NodeAddr < RefNode * > RA : DRNs ) { if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > ( RA , DFG ) << '\n' ; if ( DFG . IsUse ( RA ) ) DFG . unlinkUse ( RA , true ) ; else if ( DFG . IsDef ( RA ) ) DFG . unlinkDef ( RA , true ) ; } for ( NodeAddr < InstrNode * > IA : DINs ) { NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; BA . Addr -> removeMember ( IA , DFG ) ; if ( ! DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) continue ; MachineInstr * MI = NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * MI ; MI -> eraseFromParent ( )


<s> if ( trace ( ) ) { dbgs ( ) << <STR_LIT> ; for ( NodeId N : LiveNodes ) { auto RA = DFG . addr < RefNode * > ( N ) ; dbgs ( ) << PrintNode < RefNode * > ( RA , DFG ) << <STR_LIT> ; } } auto IsDead = [ this ] ( NodeAddr < InstrNode * > IA ) -> bool { for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) if ( LiveNodes . count ( DA . Id ) ) return false ; return true ; } ; for ( NodeAddr < BlockNode * > BA : DFG . getFunc ( ) . Addr -> members ( DFG ) ) { for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { for ( NodeAddr < RefNode * > RA : IA . Addr -> members ( DFG ) ) if ( ! LiveNodes . count ( RA . Id ) ) DeadNodes .


<s> uint16_t KindA = A . Addr -> getKind ( ) , KindB = B . Addr -> getKind ( ) ; if ( KindA == NodeAttrs :: Use && KindB == NodeAttrs :: Def ) return true ; if ( KindA == NodeAttrs :: Def && KindB == NodeAttrs :: Use ) return false ; return A . Id < B . Id ; } ; std :: sort ( DRNs . begin ( ) , DRNs . end ( ) , UsesFirst ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> ; for ( NodeAddr < RefNode * > RA : DRNs ) { if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > ( RA , DFG ) << '\n' ; if ( DFG . IsUse ( RA ) ) DFG . unlinkUse ( RA ) ; else if ( DFG . IsDef ( RA ) ) DFG . unlinkDef ( RA ) ; } for ( NodeAddr < InstrNode * > IA : DINs ) { NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; BA . Addr -> removeMember ( IA , DFG ) ; if ( ! DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) continue ; MachineInstr * MI = NodeAddr < StmtNode * > ( IA ) . Addr ->


<s> void DeadCodeElimination :: processDef ( NodeAddr < DefNode * > DA , SetVector < NodeId > & WorkQ ) { NodeAddr < InstrNode * > IA = DA . Addr -> getOwner ( DFG ) ; for ( NodeAddr < UseNode * > UA : IA . Addr -> members_if ( DFG . IsUse , DFG ) ) { if ( ! LiveNodes . count ( UA . Id ) ) WorkQ . insert (


<s> void DeadCodeElimination :: processUse ( NodeAddr < UseNode * > UA , SetVector < NodeId > &


<s> if ( ! LiveNodes . count ( DA . Id ) ) WorkQ . insert ( DA


<s> for ( NodeAddr < RefNode * > RA : IA . Addr -> members ( DFG ) ) { if ( ! LiveNodes . count ( RA . Id ) ) WorkQ . insert ( RA .


<s> LiveNodes . insert ( N ) ; auto RA = DFG . addr < RefNode * > ( N ) ; if ( DFG . IsDef ( RA ) ) processDef ( RA , WorkQ ) ; else processUse ( RA , WorkQ ) ; } if ( trace ( ) ) { dbgs ( ) << <STR_LIT> ; for ( NodeId N : LiveNodes ) { auto RA = DFG . addr < RefNode * > ( N ) ; dbgs ( ) << PrintNode < RefNode * > ( RA , DFG ) << <STR_LIT> ; } } auto IsDead = [ this ] ( NodeAddr < InstrNode * > IA ) -> bool { for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) if ( LiveNodes . count ( DA . Id ) ) return false ; return true ; } ; for ( NodeAddr < BlockNode * > BA : DFG . getFunc ( ) . Addr -> members ( DFG ) ) { for ( NodeAddr < InstrNode * > IA : BA . Addr -> members


<s> LiveNodes . insert ( N ) ; auto RA = DFG . addr < RefNode * > ( N ) ; if ( DFG . IsDef ( RA ) ) processDef ( RA , WorkQ ) ; else processUse ( RA , WorkQ ) ; } if ( trace ( ) ) { dbgs ( ) << <STR_LIT> ; for ( NodeId N : LiveNodes ) { auto RA = DFG . addr < RefNode * > ( N ) ; dbgs ( ) << PrintNode < RefNode * > ( RA , DFG ) << <STR_LIT> ; } } auto IsDead = [ this ] ( NodeAddr < InstrNode * > IA ) -> bool { for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) if ( LiveNodes . count ( DA . Id ) ) return false ; return true ; } ; for ( NodeAddr < BlockNode * > BA : DFG . getFunc ( ) . Addr -> members ( DFG ) ) { for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( DFG ) ) { for ( NodeAddr < RefNode * > RA : IA . Addr -> members ( DFG ) ) if ( ! LiveNodes . count ( RA . Id ) ) DeadNodes . insert ( RA . Id ) ; if ( DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) if ( isLiveInstr ( NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ) ) continue ; if ( IsDead ( IA ) ) { DeadInstrs . insert ( IA . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < InstrNode * > ( IA , DFG ) << <STR_LIT> ; } } } return ! DeadNodes . empty ( )


<s> bool empty ( ) const { return Queue . empty


<s> DRNs . push_back ( DFG . addr < RefNode * > ( I ) ) ; continue ; } uint16_t Kind = BA . Addr -> getKind ( ) ; if ( Kind == NodeAttrs :: Stmt || Kind == NodeAttrs :: Phi ) { for ( auto N : NodeAddr < CodeNode * > ( BA ) . Addr -> members ( DFG ) ) DRNs . push_back ( N ) ; DINs . push_back ( DFG . addr < InstrNode * > ( I ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; return false ; } } auto UsesFirst = [ ] ( NodeAddr < RefNode * > A , NodeAddr < RefNode * > B ) -> bool { uint16_t KindA = A . Addr -> getKind ( ) , KindB = B . Addr -> getKind ( ) ; if ( KindA == NodeAttrs :: Use && KindB == NodeAttrs :: Def ) return true ; if ( KindA == NodeAttrs :: Def && KindB == NodeAttrs :: Use ) return false ; return A . Id < B . Id ; } ; llvm :: sort ( DRNs . begin ( ) , DRNs . end ( ) , UsesFirst ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> ; for ( NodeAddr < RefNode * > RA : DRNs ) { if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > ( RA , DFG ) << '\n' ; if ( DFG . IsUse ( RA ) ) DFG . unlinkUse ( RA , true ) ; else if ( DFG . IsDef ( RA ) ) DFG . unlinkDef ( RA , true ) ; } for ( NodeAddr < InstrNode * > IA : DINs ) { NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; BA . Addr -> removeMember ( IA , DFG ) ; if ( ! DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) continue ; MachineInstr * MI = NodeAddr < StmtNode * > (


<s> T V = Queue . front ( ) ; Queue . pop ( ) ; Set . erase ( V


<s> if ( ! LiveNodes . count ( UA . Id ) ) WorkQ . push_back ( UA . Id ) ; } for ( NodeAddr < DefNode * > TA : DFG . getRelatedRefs ( IA , DA ) ) LiveNodes


<s> void DeadCodeElimination :: processUse ( NodeAddr < UseNode * > UA , SetQueue < NodeId > & WorkQ ) { for ( NodeAddr < DefNode * > DA : LV . getAllReachingDefs ( UA ) ) { if ( ! LiveNodes . count ( DA . Id ) )


<s> if ( ! isLiveInstr ( NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ) ) return ; for ( NodeAddr < RefNode * > RA : IA


<s> NodeAddr < BlockNode * > findBlock ( MachineBasicBlock * BB ) const { return BlockNodes . at


<s> assert ( LM . any ( ) ) ; return LM . all ( ) ? <NUM_LIT>


<s> return K == <NUM_LIT> ? LaneBitmask :: getAll ( ) : get


<s> if ( NA . Addr -> getType ( ) == NodeAttrs :: Ref ) { NodeAddr < RefNode * > RA = NA ; if ( RA . Addr -> getRegRef ( G ) == RR && P ( NA ) ) return NA ; if ( NextOnly ) break ; NA = G . addr < NodeBase * >


<s> static bool IsPreservingDef ( const NodeAddr < DefNode


<s> NodeAllocator ( uint32_t NPB = <NUM_LIT> ) : NodesPerBlock ( NPB ) , BitsPerIndex ( Log2_32 ( NPB ) ) , IndexMask ( ( <NUM_LIT> << BitsPerIndex ) - <NUM_LIT> ) { assert ( isPowerOf2_32 (


<s> PackedRegisterRef pack ( RegisterRef


<s> return { RR . Reg , LMI . getIndexForLaneMask ( RR .


<s> return RegisterRef ( PR . Reg , LMI . getLaneMaskForIndex ( PR . MaskId


<s> ML . Addr -> append ( NA ) ; } else { Code . FirstM = NA . Id ; NodeId Self = G . id ( this ) ; NA . Addr ->


<s> addMember ( PA , G ) ; return ; } assert ( M . Addr -> getType ( ) == NodeAttrs :: Code ) ; if ( M . Addr -> getKind ( ) == NodeAttrs :: Stmt ) { Code . FirstM = PA . Id ; PA . Addr -> setNext ( M . Id ) ; } else { assert ( M . Addr -> getKind ( ) == NodeAttrs :: Phi ) ; NodeAddr < NodeBase * > MN = M ; do { M = MN ; MN = G . addr < NodeBase * > ( M . Addr -> getNext ( ) ) ; assert ( MN . Addr -> getType ( ) == NodeAttrs :: Code ) ; } while ( MN . Addr -> getKind ( ) == NodeAttrs :: Phi ) ; addMemberAfter ( M ,


<s> for ( NodeAddr < BlockNode * > BA : Blocks ) for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( * this ) ) for ( NodeAddr < RefNode * > RA : IA . Addr -> members ( * this ) ) AllRefs . insert ( RA . Addr -> getRegRef ( * this ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineBasicBlock & EntryB = * EA . Addr -> getCode ( ) ; assert ( EntryB . pred_empty ( ) && <STR_LIT> ) ; for ( std :: pair < unsigned , unsigned > P : MRI . liveins ( ) ) LiveIns . insert ( RegisterRef ( P . first ) ) ; if ( MRI . tracksLiveness ( ) ) { for ( auto I : EntryB . liveins ( ) ) LiveIns . insert ( RegisterRef ( I . PhysReg , I . LaneMask ) ) ; } for ( auto I = LiveIns . rr_begin ( ) , E = LiveIns . rr_end ( ) ; I != E ; ++ I ) { RegisterRef RR = * I ; NodeAddr < PhiNode * > PA = newPhi ( EA ) ; uint16_t PhiFlags = NodeAttrs :: PhiRef | NodeAttrs :: Preserving ; NodeAddr < DefNode * > DA = newDef ( PA , RR , PhiFlags ) ; PA . Addr -> addMember ( DA , * this ) ; } RegisterSet EHRegs = getLandingPadLiveIns ( ) ; if ( ! EHRegs . empty ( ) ) { for ( NodeAddr < BlockNode * > BA : Blocks ) { const MachineBasicBlock & B = * BA . Addr -> getCode ( ) ; if ( ! B . isEHPad ( ) ) continue ; NodeList Preds ; for ( MachineBasicBlock * PB : B . predecessors ( ) ) Preds . push_back ( findBlock (


<s> iterator end ( ) const { return Masks . end


<s> NodeAddr < BlockNode * > findBlock ( MachineBasicBlock * BB ) { return BlockNodes [ BB


<s> assert ( Idx != <NUM_LIT> && ! Map . empty ( ) && Idx - <NUM_LIT> < Map


<s> } ; auto RelatedStmt = [ & Related , RA ] ( NodeAddr < RefNode * > TA ) -> bool { return Related ( TA ) && & RA . Addr -> getOp ( ) == & TA . Addr -> getOp ( ) ; } ; auto RelatedPhi = [ & Related , RA ] ( NodeAddr < RefNode * > TA ) -> bool { if ( ! Related ( TA ) ) return false ; if ( TA . Addr -> getKind ( ) != NodeAttrs :: Use ) return true ; const NodeAddr < const PhiUseNode * > TUA = TA ; const NodeAddr < const PhiUseNode * > RUA = RA ; return TUA . Addr -> getPredecessor ( ) == RUA . Addr -> getPredecessor ( ) ; } ; RegisterRef RR = RA . Addr -> getRegRef ( * this ) ; if ( IA . Addr -> getKind ( ) == NodeAttrs :: Stmt ) return RA . Addr -> getNextRef ( RR , RelatedStmt , true , * this ) ; return RA . Addr -> getNextRef ( RR , RelatedPhi


<s> auto RelatedStmt = [ & Related , RA ] ( NodeAddr < RefNode * > TA ) -> bool { return Related ( TA ) && & RA . Addr -> getOp ( ) == & TA . Addr -> getOp ( ) ; } ; auto RelatedPhi = [ & Related , RA ] ( NodeAddr < RefNode * > TA ) -> bool { if ( ! Related ( TA ) ) return false ; if ( TA . Addr -> getKind ( ) != NodeAttrs :: Use ) return true ; const NodeAddr < const PhiUseNode * > TUA = TA ; const NodeAddr < const PhiUseNode * > RUA = RA ; return TUA . Addr -> getPredecessor ( ) == RUA . Addr -> getPredecessor ( ) ; } ; RegisterRef RR = RA . Addr -> getRegRef ( * this ) ; if ( IA . Addr -> getKind ( ) == NodeAttrs :: Stmt ) return RA . Addr -> getNextRef (


<s> if ( NodeAttrs :: flags ( Attrs ) & NodeAttrs :: PhiRef ) return G . unpack ( Ref . PR ) ; assert ( Ref . Op != nullptr ) ; return G . makeRegRef ( * Ref


<s> assert ( NodeAttrs :: type ( Attrs ) == NodeAttrs :: Ref ) ; if ( NodeAttrs :: flags ( Attrs ) & NodeAttrs :: PhiRef ) return G . unpack ( Ref . PR ) ; assert ( Ref . Op


<s> uint32_t insert ( T Val ) { auto F = llvm :: find


<s> assert ( Op . isReg ( ) ) ; if ( In . isCall ( ) ) if ( Op . isDef ( ) && Op . isDead ( ) ) return true ; return


<s> static bool isCoverOf ( RegisterRef RA , RegisterRef RB , const TargetRegisterInfo & TRI ) { return RegisterAggr ( TRI ) . insert (


<s> if ( In . isBranch ( ) ) for ( const MachineOperand & O : In . operands ( ) ) if ( O . isGlobal ( ) || O . isSymbol ( ) ) return true ; const MCInstrDesc & D = In . getDesc ( ) ; if ( ! D . getImplicitDefs ( ) && ! D . getImplicitUses ( ) ) return false ; const MachineOperand & Op = In


<s> RegisterSet EHLiveIns = getLandingPadLiveIns ( ) ; MachineBasicBlock * MBB = BA . Addr -> getCode ( ) ; for ( MachineBasicBlock * SB : MBB -> successors ( ) ) { bool IsEHPad = SB -> isEHPad ( ) ; NodeAddr < BlockNode * > SBA = findBlock ( SB ) ; for ( NodeAddr < InstrNode * > IA : SBA . Addr -> members_if ( IsPhi , * this ) ) { if ( IsEHPad ) { NodeAddr < RefNode * > RA = IA . Addr -> getFirstMember ( * this ) ; assert ( RA . Id != <NUM_LIT> ) ; if ( EHLiveIns . count ( RA . Addr -> getRegRef ( * this ) ) ) continue ; } for ( auto U : IA . Addr -> members_if ( IsUseForBA , * this ) ) { NodeAddr < PhiUseNode * > PUA = U ; RegisterRef RR = PUA . Addr -> getRegRef ( * this ) ; linkRefUp < UseNode * > ( IA , PUA , DefM [ RR . Reg ] ) ; } } } releaseBlock ( BA . Id


<s> if ( F == DefM . end ( ) ) continue ; DefStack & DS = F -> second ; if ( Kind == NodeAttrs :: Use ) linkRefUp < UseNode * > ( SA , RA , DS ) ; else if ( Kind == NodeAttrs :: Def ) linkRefUp < DefNode * > ( SA , RA , DS ) ; else llvm_unreachable (


<s> if ( Op . isReg ( ) ) return makeRegRef ( Op . getReg ( ) , Op . getSubReg ( ) ) ; return RegisterRef ( PRI . getRegMaskId ( Op . getRegMask (


<s> if ( Op . isReg ( ) ) return makeRegRef ( Op . getReg ( ) , Op . getSubReg ( ) ) ; return RegisterRef ( PRI . getRegMaskId ( Op . getRegMask ( ) ) , LaneBitmask :: getAll (


<s> NodeAddr < UseNode * > UA = newNode ( NodeAttrs :: Ref | NodeAttrs :: Use |


<s> PackedRegisterRef pack ( RegisterRef RR )


<s> PackedRegisterRef pack ( RegisterRef RR ) const { return LMI . pack


<s> OS << Print < NodeId > ( RA . Id , G ) << '<' << Print < RegisterRef > ( RA . Addr -> getRegRef ( G )


<s> if ( Visited . count ( DA . Id ) ) continue ; if ( ! ( DA . Addr -> getFlags ( ) & NodeAttrs :: Clobbering ) ) continue ; NodeList Rel = getRelatedRefs ( IA , DA ) ; NodeAddr < DefNode * > PDA = Rel . front ( ) ; RegisterRef RR = PDA . Addr -> getRegRef ( * this ) ; DefM [ RR . Reg ] . push ( DA ) ; Defined . insert ( RR . Reg ) ; for ( RegisterId A : PRI . getAliasSet ( RR . Reg ) ) { assert ( A != RR . Reg ) ; if ( ! Defined . count ( A ) ) DefM [ A ] . push ( DA ) ; } for ( NodeAddr < NodeBase * > T : Rel


<s> auto DFLoc = MDF . find ( BB ) ; if ( DFLoc == MDF . end ( ) || DFLoc -> second . empty ( ) ) return ; RegisterSet Defs ; for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( * this ) ) for ( NodeAddr < RefNode * > RA : IA . Addr ->

members_if ( IsDef , * this ) ) Defs . insert ( RA . Addr -> getRegRef ( * this ) ) ;


<s> RegisterSet Defs ; for ( NodeAddr < InstrNode * > IA : BA . Addr -> members ( * this ) ) for ( NodeAddr < RefNode * > RA : IA . Addr -> members_if ( IsDef , * this ) ) Defs . insert ( RA . Addr -> getRegRef ( * this ) ) ; const MachineDominanceFrontier :: DomSetType & DF = DFLoc -> second ; SetVector < MachineBasicBlock * > IDF ( DF . begin ( ) , DF . end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < IDF . size ( ) ; ++ i ) { auto F = MDF . find ( IDF [ i ] ) ; if ( F != MDF . end ( ) ) IDF . insert ( F -> second . begin ( ) , F -> second . end ( ) ) ; } for ( auto DB : IDF ) { NodeAddr < BlockNode * > DBA = findBlock


<s> auto PA = addr < PhiNode * > ( PhiQ [ <NUM_LIT> ] ) ; PhiQ . remove ( PA . Id ) ; NodeList Refs = PA . Addr -> members ( * this ) ; if ( HasUsedDef ( Refs ) ) continue ; for ( NodeAddr < RefNode * > RA : Refs ) { if ( NodeId RD = RA . Addr -> getReachingDef ( ) ) { auto RDA = addr < DefNode * > ( RD ) ; NodeAddr < InstrNode * > OA = RDA .


<s> Memory . clear ( ) ; BlockNodes . clear ( ) ; Func = NodeAddr < FuncNode * > (


<s> void DataFlowGraph :: reset ( ) { Memory . clear (


<s> LaneBitmask M = AR . Mask & BR . Mask ; return M . any ( ) ? RegisterRef ( AR .