<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return QRI . Subtarget . hasV4TOps ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case


<s> if ( SrcReg == RI . getSubReg ( DestReg , <STR_LIT> ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( KillSrc ) ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) .

addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI -> getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC ==


<s> bool <ISA_LIT>InstrInfo :: getBaseAndOffsetPosition ( const MachineInstr * MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( isMemOp ( MI ) ) { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI -> mayStore ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI -> mayLoad ( ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else return false ; if ( isPredicated ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI -> getOperand ( BasePos ) . isReg ( ) || ! MI -> getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true


<s> SmallVector < MachineInstr * , <NUM_LIT> > <ISA_LIT>InstrInfo :: getBranchingInstrs ( MachineBasicBlock & MBB ) const { SmallVector < MachineInstr * , <NUM_LIT> > Jumpers ; MachineBasicBlock :: instr_iterator I = MBB . instr_end ( ) ; if ( I == MBB . instr_begin ( ) ) return Jumpers ; do { -- I ; if ( I -> isEHLabel ( ) ) return Jumpers ; } while ( I != MBB . instr_begin


<s> return ( MI -> isBranch ( ) && isPredicated ( MI ) ) || isConditionalTransfer ( MI ) || isConditionalALU32 ( MI ) || isConditionalLoad ( MI ) || ( MI ->

mayStore ( ) && isPredicated ( MI ) && ! isNewValueStore ( MI ) && ! isPredicatedNew ( MI ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isConditionalLoad ( const MachineInstr * MI ) const { if ( ! MI -> getDesc ( ) . mayLoad ( ) || ! isPredicated ( MI


<s> if ( isNewValueInst ( MI ) || ( isPredicated ( MI ) && isPredicatedNew ( MI ) ) ) return true ; return


<s> if ( isNewValueInst ( MI ) || ( isPredicated ( MI ) && isPredicatedNew ( MI )


<s> case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( OpCExtended [ <NUM_LIT> ] || isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) && ( OpCExtended [ <NUM_LIT> ] || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT>


<s> return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( OpCExtended [ <NUM_LIT> ] || isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) && ( OpCExtended [ <NUM_LIT> ] || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm


<s> const uint64_t F = MI -> getDesc ( )


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ; assert ( isPredicated ( MI )


<s> assert ( isPredicated ( MI ) ) ; return ( F >> <STR_LIT> )


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ! ( ( F >>


<s> unsigned <ISA_LIT>InstrInfo :: nonDbgBundleSize ( MachineBasicBlock :: const_iterator BundleHead ) const { assert ( BundleHead -> isBundle ( ) && <STR_LIT> ) ; auto MII = BundleHead . getInstrIterator ( ) ; return nonDbgMICount ( ++ MII , getBundleEnd (


<s> unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq (


<s> TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) || ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } return true


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains (


<s> return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; int regPos = <NUM_LIT> ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ) { BccOpc = <STR_LIT> ; regPos = <NUM_LIT> ; } if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , <NUM_LIT> , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ regPos ] . getReg ( ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ regPos ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( BOpc


<s> } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMH_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMH_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMB_AUTOINC_MIN &&

Offset <= <ISA_LIT>_MEMB_AUTOINC_MAX ) ;


<s> case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm (


<s> MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else { assert ( false && <STR_LIT> ) ; } } int regPos = invertJump ? <NUM_LIT>


<s> if ( <STR_LIT> -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> )


<s> bool LastOpcodeHasNVJump = isNewValueJump ( LastInst ) ; if ( LastOpcodeHasJMP_c && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isEndLoopN ( LastOpcode ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcodeHasNVJump && ( SecondLastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst -> getIterator ( ) ; if ( AllowModify ) I -> eraseFromParent


<s> int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned SizeA = <NUM_LIT> , SizeB = <NUM_LIT> ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIa -> hasOrderedMemoryRef ( ) ) return false ; if ( MIa -> mayLoad ( ) && ! isMemOp ( MIa ) && MIb -> mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ; if ( ! BaseRegA || ! SizeA ) return false ; unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t )


<s> int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned SizeA = <NUM_LIT> , SizeB = <NUM_LIT> ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIa -> hasOrderedMemoryRef ( ) ) return false ; if ( MIa -> mayLoad ( ) && ! isMemOp ( MIa ) && MIb -> mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ; if ( ! BaseRegA ||


<s> return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , KillFlag ) ; return ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { unsigned DstHi = HRI . getSubReg ( DestReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; unsigned DstLo = HRI . getSubReg ( DestReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( HRI . getSubReg ( SrcReg , <STR_LIT> ) , KillFlag ) ; return ; } dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << PrintReg ( DestReg , & HRI ) << <STR_LIT> << PrintReg ( SrcReg , & HRI ) << '\n' ; llvm_unreachable ( <STR_LIT>


<s> unsigned Latency = ItinData -> getStageLatency ( MI -> getDesc ( ) . getSchedClass ( ) ) ; if ( ! EnableTimingClassLatency || MI -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . useBSBScheduling ( ) ) if ( Latency > <NUM_LIT> ) Latency = <NUM_LIT> ; return


<s> unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> )


<s> return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( OpCExtended [ <NUM_LIT> ] || isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) && ( OpCExtended [ <NUM_LIT> ] || isInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode (


<s> bool <ISA_LIT>InstrInfo :: isSaveCalleeSavedRegsCall ( const MachineInstr * MI ) const { return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode


<s> if ( MI -> isCall ( ) ) { for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) return true ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isPosition ( ) ) return true ; if ( MI -> isInlineAsm ( ) &&


<s> for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) return true ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI ->


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT>


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC


<s> } if ( mayBeNewStore ( MI2 ) ) if ( MI2 -> getOpcode ( ) == <STR_LIT> ) if ( MI1 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI2

-> getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ;


<s> unsigned DstReg = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int N = MI2 -> getNumOperands ( ) ; for ( int I = <NUM_LIT> ; I < N ; I ++ ) if ( MI2 -> getOperand ( I ) . isReg ( ) && DstReg == MI2 -> getOperand ( I ) . getReg ( ) ) return true ; } if ( mayBeNewStore ( MI2 ) ) if ( MI2 -> getOpcode ( ) == <STR_LIT> ) if ( MI1 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI1 -> getOperand ( <NUM_LIT> ) . getReg

( ) == MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ;


<s> } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1SubHi = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src1SubLo = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src2SubHi = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; unsigned Src2SubLo = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubHi ) . addReg ( Src2SubHi ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubLo ) . addReg ( Src2SubLo ) ; MBB . erase ( MI ) ; MRI . clearKillFlags ( Src1SubHi ) ; MRI . clearKillFlags ( Src1SubLo ) ; MRI . clearKillFlags ( Src2SubHi ) ; MRI . clearKillFlags ( Src2SubLo ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src3Reg = MI -> getOperand ( <NUM_LIT> )


<s> Opcode_t BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) ) BccOpc = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( Term != MBB . end ( ) && isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT>


<s> case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset &&


<s> return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT>


<s> bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = & * T ; B . erase (


<s> MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = & * T ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ; MRI . clearKillFlags ( PredReg


<s> if ( Cond . empty ( ) || ! isPredicated ( Cond [ <NUM_LIT> ] . getImm ( ) )


<s> if ( Cond . empty ( ) || ! isPredicated ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) return false ; return ! isPredicatedTrue ( Cond [ <NUM_LIT> ] . getImm


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( Offset


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return & * MIB


<s> <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT>


<s> BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ]


<s> const InstrItineraryData * II = TM -> getSubtargetImpl


<s> unsigned BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = ( <NUM_LIT> << ( getMemAccessSize ( MIa ) - <NUM_LIT> ) ) ; unsigned SizeB = ( <NUM_LIT> << ( getMemAccessSize ( MIb ) - <NUM_LIT> ) ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) .


<s> if ( getAddrMode ( MI ) != <STR_LIT> && getAddrMode ( MI ) != <STR_LIT> && ! isMemOp ( MI ) && ! isPostIncrement ( MI ) ) return <NUM_LIT> ; assert ( getMemAccessSize ( MI ) && <STR_LIT> ) ; AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned BasePos = <NUM_LIT> , OffsetPos = <NUM_LIT> ; if ( ! getBaseAndOffsetPosition ( MI , BasePos , OffsetPos ) ) return <NUM_LIT> ; if ( isPostIncrement ( MI ) ) { Offset =


<s> AccessSize = ( <NUM_LIT> << ( getMemAccessSize ( MI ) - <NUM_LIT> ) ) ; unsigned BasePos = <NUM_LIT> , OffsetPos = <NUM_LIT> ; if ( ! getBaseAndOffsetPosition ( MI , BasePos , OffsetPos ) ) return <NUM_LIT> ; if ( isPostIncrement ( MI ) ) { Offset = <NUM_LIT> ; } else { const MachineOperand & OffsetOp = MI . getOperand


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == &


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) .

addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) .


<s> if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t


<s> if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) ) BccOpc = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( Term != MBB . end ( ) && isPredicated ( * Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = & * ++ MBB . getIterator ( ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT>


<s> return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT>


<s> if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true


<s> const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ; if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg


<s> return static_cast < const <ISA_LIT>Subtarget & > ( STI


<s> DFAPacketizer * <ISA_LIT>InstrInfo :: CreateTargetScheduleState (

const TargetSubtargetInfo & STI ) const {


<s> TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned NewReg = RegInfo . createVirtualRegister ( TRC


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI -> getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = RI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true


<s> const <ISA_LIT>RegisterInfo & HRI = getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( HRI . getFrameRegister ( ) ) . addImm ( - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MBB . erase ( MI ) ; return true ; case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MBB . erase ( MI ) ; return true ; } case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MBB . erase ( MI ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1SubHi = HRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src1SubLo = HRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src2SubHi = HRI . getSubReg ( Src2Reg , <STR_LIT> ) ; unsigned Src2SubLo = HRI . getSubReg ( Src2Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , HRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubHi ) . addReg ( Src2SubHi ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , HRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubLo ) . addReg ( Src2SubLo ) ; MBB . erase ( MI ) ; MRI . clearKillFlags ( Src1SubHi ) ; MRI . clearKillFlags ( Src1SubLo ) ; MRI . clearKillFlags ( Src2SubHi ) ; MRI . clearKillFlags ( Src2SubLo ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> )


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const override { return


<s> unsigned short <ISA_LIT>InstrInfo :: getCExtOpNum ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc (


<s> unsigned short <ISA_LIT>InstrInfo :: getCExtOpNum (


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return <NUM_LIT>


<s> MachineBasicBlock * Dst = BrTarget -> getMBB ( ) ; const BranchProbability Prediction = MBPI -> getEdgeProbability ( Src , Dst ) ; if ( Prediction >= BranchProbability ( <NUM_LIT> , <NUM_LIT> ) ) taken = true ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : return taken ? <STR_LIT> : <STR_LIT>


<s> if ( NewOpcode >= <NUM_LIT> ) return NewOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return getDotNewPredJumpOp ( MI , MBPI ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> } if ( isNewValueStore ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; assert ( NewOp >=


<s> } if ( isNewValueStore ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; assert ( NewOp >= <NUM_LIT> && <STR_LIT> ) ; } return


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> InvPredOpcode = isPredicatedTrue ( Opc ) ? <STR_LIT> ( Opc ) : <STR_LIT> ( Opc ) ; if ( InvPredOpcode >= <NUM_LIT> ) return InvPredOpcode ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> if ( MI -> isDebugValue ( ) || MI -> isPosition ( ) ) return <NUM_LIT> ; unsigned Size = MI -> getDesc ( ) . getSize ( ) ; if ( ! Size ) Size =


<s> isConditionalLoad ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isConditionalStore ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isConditionalTransfer ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return


<s> unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) ) return true ; assert ( MO . isImm ( ) &&


<s> bool <ISA_LIT>InstrInfo :: isDotNewInst ( const MachineInstr


<s> return ( isNewValueInst ( MI ) || ( isPredicated (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ( MI

-> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) {


<s> bool <ISA_LIT>InstrInfo :: isNewValue ( Opcode_t Opcode ) const { const uint64_t F = get


<s> bool <ISA_LIT>InstrInfo :: isNewValueInst ( const MachineInstr * MI ) const { if ( isNewValueJump ( MI ) ) return true ; if ( isNewValueStore ( MI ) ) return true ; return false


<s> if ( isNewValueStore ( MI ) ) return true ; return false


<s> return isNewValue ( Opcode ) && get ( Opcode ) . isBranch ( )


<s> const uint64_t F = get ( Opcode ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isOperandExtended ( const MachineInstr * MI , unsigned short OperandNum ) const { const uint64_t F = MI -> getDesc ( )


<s> bool <ISA_LIT>InstrInfo :: isPostIncrement ( const MachineInstr * MI ) const { return ( getAddrMode ( MI ) ==


<s> case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return true


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isPosition ( ) || MI -> isInlineAsm ( ) ) return true ; return false


<s> void <ISA_LIT>InstrInfo :: loadRegFromAddr ( MachineFunction & MF , unsigned DestReg , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { llvm_unreachable ( <STR_LIT>


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm (


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr * MI ) const { const uint64_t F = MI ->


<s> if ( MI -> getDesc ( ) . mayLoad ( ) || MI -> getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : NonExtOpcode = <STR_LIT> ( MI -> getOpcode (


<s> MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . empty ( ) ) return true ; assert ( Cond [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ; Opcode_t opcode = Cond [ <NUM_LIT> ] . getImm


<s> void <ISA_LIT>InstrInfo :: storeRegToAddr ( MachineFunction & MF , unsigned SrcReg , bool isKill , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { llvm_unreachable ( <STR_LIT>


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill )


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2


<s> SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return false


<s> unsigned UseOpc = U -> getMachineOpcode ( ) ; Ops [ I1N ] = C0 ; If0 = SDValue ( DAG . getMachineNode ( UseOpc , dl , UVT , Ops ) , <NUM_LIT> ) ; Ops [ I1N ] = C1 ; If1 = SDValue ( DAG . getMachineNode ( UseOpc , dl , UVT , Ops ) , <NUM_LIT> ) ; } else { unsigned UseOpc = U -> getOpcode ( ) ; Ops [ I1N ] = C0 ; If0 = DAG . getNode ( UseOpc , dl , UVT , Ops ) ; Ops [ I1N ] = C1 ; If1 = DAG . getNode ( UseOpc , dl , UVT , Ops ) ; } SDValue Sel = DAG . getNode ( <STR_LIT> , dl , UVT , OpI1 , If1 , If0 ) ; DAG . ReplaceAllUsesWith ( U , Sel . getNode ( )


<s> EVT OpVT = OpI1 . getValueType ( ) ; if ( ! OpVT . isSimple ( ) || OpVT . getSimpleVT ( ) != <STR_LIT> ) continue ; for ( auto I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) { SDNode * U = * I ; if ( U -> getNumValues ( ) != <NUM_LIT> ) continue ; EVT UVT = U -> getValueType ( <NUM_LIT> ) ; if ( ! UVT . isSimple ( ) || ! UVT . isInteger ( ) || UVT . getSimpleVT ( ) == <STR_LIT> ) continue ; if ( isMemOPCandidate ( N , U ) ) continue ; unsigned I1N = I . getOperandNo ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( U -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> , n = U -> getNumOperands ( ) ; i != n ; ++ i ) Ops [ i ] = U -> getOperand ( i ) ; EVT BVT = Ops [ I1N ] . getValueType ( ) ; SDLoc dl ( U ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , BVT ) ; SDValue C1 = DAG . getConstant ( <NUM_LIT> , dl , BVT ) ; SDValue If0 , If1 ; if ( isa < MachineSDNode > ( U ) ) { unsigned UseOpc = U -> getMachineOpcode ( ) ; Ops [ I1N ] = C0 ; If0 = SDValue ( DAG . getMachineNode ( UseOpc , dl , UVT , Ops ) , <NUM_LIT> ) ; Ops [ I1N ] = C1 ; If1 = SDValue ( DAG . getMachineNode ( UseOpc , dl , UVT , Ops ) , <NUM_LIT> ) ; } else { unsigned UseOpc = U -> getOpcode ( ) ; Ops [ I1N ] = C0 ; If0 = DAG . getNode ( UseOpc , dl , UVT , Ops ) ; Ops [ I1N


<s> HST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; HRI = HST -> getRegisterInfo ( ) ; SelectionDAGISel :: runOnMachineFunction (


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { HST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; HRI = HST -> getRegisterInfo ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; updateAligna ( )


<s> return SelectGlobalAddress ( N , R , false , <NUM_LIT>


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAddrGP ( SDValue & N , SDValue & R ) { return SelectGlobalAddress ( N , R , true , <NUM_LIT>


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm0 ( SDValue & N , SDValue & R ) { return SelectAnyImmediate ( N , R , <NUM_LIT>


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm0 ( SDValue


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm1 ( SDValue & N , SDValue & R ) { return SelectAnyImmediate ( N , R , <NUM_LIT>


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm2 ( SDValue & N , SDValue & R ) { return SelectAnyImmediate ( N ,


<s> return SelectAnyImmediate ( N , R , <NUM_LIT>


<s> const <ISA_LIT>FrameLowering * HFI = HST -> getFrameLowering ( ) ; int FX = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; unsigned StkA = HFI -> getStackAlignment ( ) ; unsigned MaxA = MFI . getMaxAlignment ( ) ; SDValue FI = CurDAG -> getTargetFrameIndex ( FX , <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Zero = CurDAG -> getTargetConstant (


<s> if ( GA -> getOpcode ( ) == <STR_LIT> ) { uint64_t NewOff = GA -> getOffset ( ) + ( uint64_t ) Const -> getSExtValue ( ) ; R = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Const ) , N . getValueType ( ) , NewOff ) ; return true ; } } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! UseGP ) R = N . getOperand ( <NUM_LIT> ) ; return ! UseGP ; case <STR_LIT> : if ( UseGP ) R = N . getOperand ( <NUM_LIT> ) ; return UseGP ; default : return false ; } return false


<s> SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDNode * R = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) ; SDValue M0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue M1 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * C = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , M0 , N ->


<s> MVT ResTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; if ( HST -> isHVXVectorType ( ResTy , true ) ) return SelectHvxVAlign ( N ) ; const SDLoc & dl ( N ) ; unsigned VecLen = ResTy . getSizeInBits ( ) ; if ( VecLen == <NUM_LIT> ) { SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDNode * R = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) ; SDValue M0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue M1 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * C = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , M0 , N -> getOperand ( <NUM_LIT> ) , M1 ) ; SDNode * S = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( R , <NUM_LIT> ) , SDValue ( C , <NUM_LIT> ) ) ; SDValue E = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , SDValue ( S , <NUM_LIT> ) ) ; ReplaceNode ( N , E . getNode ( ) ) ; } else { assert ( VecLen == <NUM_LIT> ) ; SDNode * Pu = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT>


<s> unsigned <ISA_LIT>DAGToDAGISel :: getUsesInFunction ( const Value * V ) { if ( GAUsesInFunction . count ( V ) ) return GAUsesInFunction [ V ] ; unsigned Result = <NUM_LIT> ; const Function * CurF = CurDAG -> getMachineFunction ( ) . getFunction ( ) ; for ( const User * U : V -> users ( ) ) { if ( isa < Instruction > ( U ) && cast < Instruction > ( U )

-> getParent ( ) -> getParent ( ) == CurF ) ++ Result ;


<s> assert ( C ) ; if ( auto * FN = dyn_cast < FrameIndexSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; unsigned A = MFI . getObjectAlignment ( FN -> getIndex ( ) ) ; assert ( isPowerOf2_32 ( A )


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == Mask ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == Mask ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } break ; } case <STR_LIT> : case <STR_LIT> : { uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( ( C -> getZExtValue ( ) & Mask ) == <NUM_LIT> ) { Src = Val . getOperand (


<s> } } break ; case <STR_LIT> : { uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == Mask ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == Mask ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } break ; } case <STR_LIT> : case <STR_LIT> : { uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( ( C -> getZExtValue ( ) & Mask ) == <NUM_LIT> ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val . getOperand ( <NUM_LIT> ) ) ) { if ( ( C -> getZExtValue ( ) & Mask ) == <NUM_LIT> ) { Src = Val . getOperand ( <NUM_LIT> ) ; return true ; } } } default : break ; } return false


<s> SDValue I = CurDAG -> getTargetConstant ( Inc -> getSExtValue ( ) , dl , <STR_LIT> ) ; MachineSDNode * Res = CurDAG -> getMachineNode ( FLC -> second , dl , RTys , { IntN -> getOperand ( <NUM_LIT> ) , I , SDValue ( Mod , <NUM_LIT> ) , IntN -> getOperand ( <NUM_LIT> ) } ) ; return Res ; } static std :: map < unsigned , unsigned > LoadPbrMap = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; auto FLB = LoadPbrMap . find ( IntNo ) ; if ( FLB != LoadPbrMap . end ( ) ) { SDNode * Mod = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , IntN -> getOperand ( <NUM_LIT> ) ) ; EVT ValTy = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT RTys [ ] = { ValTy , <STR_LIT> , <STR_LIT> } ; MachineSDNode * Res = CurDAG -> getMachineNode ( FLB -> second , dl , RTys , { IntN -> getOperand ( <NUM_LIT> ) , SDValue ( Mod , <NUM_LIT> ) , IntN -> getOperand ( <NUM_LIT> ) } ) ; return Res


<s> } SDValue IncV = CurDAG -> getTargetConstant ( Inc , dl , <STR_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand ( ) ; SDValue From [ <NUM_LIT> ] = { SDValue ( ST , <NUM_LIT> ) , SDValue ( ST , <NUM_LIT> ) } ; SDValue To [ <NUM_LIT> ] ; if ( IsValidInc ) { SDValue Ops [ ] = { Base , IncV , Value , Chain } ; MachineSDNode * S = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Ops ) ; S -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( S , <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( S , <NUM_LIT> ) ; } else { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Zero , Value , Chain } ; MachineSDNode * S = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; S -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; To [ <NUM_LIT> ] = SDValue ( S , <NUM_LIT> ) ; MachineSDNode * A = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , IncV ) ; To [ <NUM_LIT> ] = SDValue ( A , <NUM_LIT> ) ; } ReplaceUses ( From , To , <NUM_LIT>


<s> StoreInstrForLoadIntrinsic ( L , N ) ; CurDAG -> RemoveDeadNode ( N ) ; return ; } SelectCode (


<s> if ( keepsLowBits ( V , Bits , U ) ) { SDValue R = CurDAG -> getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , U ) ; ReplaceNode ( N , R . getNode (


<s> } default : return false ; } EVT RT = R . getValueType ( ) ; if ( RT == <STR_LIT> ) return true ; assert ( RT == <STR_LIT> ) ; const SDLoc & dl ( N ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , R , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , R , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDNode * T = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE ,


<s> case <STR_LIT> : return SelectIntrinsicWOChain ( N ) ; case <STR_LIT> : return SelectTypecast ( N ) ; case <STR_LIT> : return SelectP2D ( N ) ; case <STR_LIT> : return SelectD2P ( N ) ; case <STR_LIT> : return SelectQ2V ( N ) ; case <STR_LIT> : return SelectV2Q ( N ) ; } if ( HST -> useHVXOps ( ) ) { switch ( N -> getOpcode ( ) ) { case <STR_LIT> : return SelectHvxShuffle ( N ) ; case <STR_LIT> : return SelectHvxRor ( N ) ; } } SelectCode ( N


<s> Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isAlignedMemNode ( LD ) ) { if ( LD -> isNonTemporal ( ) ) Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; else Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; } break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue IncV = CurDAG -> getTargetConstant ( Inc , dl , <STR_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; auto getExt64 = [ this , ExtType ] ( MachineSDNode * N , const SDLoc & dl ) -> MachineSDNode * { if ( ExtType == <STR_LIT> || ExtType == <STR_LIT> ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Zero , SDValue ( N , <NUM_LIT> ) ) ; } if ( ExtType == <STR_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( N , <NUM_LIT> ) ) ; return N ; } ; SDValue From [ <NUM_LIT> ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; SDValue To [ <NUM_LIT> ] ; EVT ValueVT = LD -> getValueType ( <NUM_LIT> ) ; if ( ValueVT == <STR_LIT> && ExtType != <STR_LIT> ) { assert ( LoadedVT . getSizeInBits ( ) <= <NUM_LIT> ) ; ValueVT = <STR_LIT>


<s> SDValue Base = ST -> getBasePtr ( ) ; SDValue Offset = ST -> getOffset ( ) ; SDValue Value = ST -> getValue ( ) ; int32_t Inc = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; EVT StoredVT = ST -> getMemoryVT ( ) ; EVT ValueVT = Value . getValueType ( ) ; bool IsValidInc = HII -> isValidAutoIncImm ( StoredVT , Inc ) ; unsigned Opcode = <NUM_LIT> ; assert ( StoredVT . isSimple ( ) ) ; switch ( StoredVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isAlignedMemNode ( ST ) ) { if ( ST -> isNonTemporal ( ) ) Opcode


<s> StoreInstrForLoadIntrinsic ( L , N ) ; CurDAG -> RemoveDeadNode ( N ) ; return ; } unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo == <STR_LIT> || IntNo ==


<s> void <ISA_LIT>DAGToDAGISel :: SelectQ2V ( SDNode * N ) { const SDLoc & dl ( N ) ; MVT ResTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue C = CurDAG -> getTargetConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * R = CurDAG -> getMachineNode ( <STR_LIT> ,


<s> MVT OpTy = Op . getValueType ( ) . getSimpleVT ( ) ; SDNode * T = CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , CurDAG -> getVTList ( OpTy ) , { Op } ) ; ReplaceNode ( T , Op


<s> void <ISA_LIT>DAGToDAGISel :: SelectTypecast ( SDNode * N ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; MVT OpTy = Op . getValueType ( ) . getSimpleVT ( ) ; SDNode * T = CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , CurDAG -> getVTList ( OpTy ) , { Op } ) ; ReplaceNode ( T , Op . getNode ( ) ) ; CurDAG -> RemoveDeadNode ( T )


<s> const SDLoc & dl ( N ) ; MVT ResTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue C = CurDAG -> getTargetConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * R = CurDAG -> getMachineNode ( <STR_LIT> ,


<s> void <ISA_LIT>DAGToDAGISel :: SelectV2Q ( SDNode * N ) { const SDLoc & dl ( N ) ; MVT ResTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue C = CurDAG -> getTargetConstant ( - <NUM_LIT> , dl ,


<s> return new <ISA_LIT>DAGToDAGISel ( TM )


<s> return new <ISA_LIT>DAGToDAGISel ( TM


<s> return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> virtual const char * getPassName ( ) const { return


<s> ConstantSDNode * N = cast < ConstantSDNode > ( S ) ; int64_t v = ( int64_t )


<s> static bool IsS11_1_Offset ( SDNode * S ) { ConstantSDNode * N = cast <


<s> ConstantSDNode * N = cast < ConstantSDNode > ( S ) ; int64_t v = ( int64_t ) N -> getSExtValue


<s> int64_t v = ( int64_t ) N -> getSExtValue ( ) ; return isShiftedInt < <NUM_LIT> , <NUM_LIT>


<s> int64_t v = ( int64_t ) N -> getSExtValue ( ) ; return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( v


<s> ConstantSDNode * N = cast < ConstantSDNode > ( S ) ; int64_t v = ( int64_t ) N -> getSExtValue ( ) ; return isShiftedUInt < <NUM_LIT> , <NUM_LIT> >


<s> case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectSelect ( N ) ; case <STR_LIT> : return SelectTruncate ( N ) ; case <STR_LIT> : return SelectMul ( N ) ; case <STR_LIT>


<s> return SelectAdd ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectSelect ( N ) ; case <STR_LIT> : return SelectTruncate ( N ) ; case <STR_LIT> : return SelectMul ( N ) ; case <STR_LIT> : return SelectZeroExtend (


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectAdd ( SDNode * N ) { DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDNode * Src1 = N -> getOperand ( <NUM_LIT> )


<s> } SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) , Src1 -> getOperand ( <NUM_LIT> ) ) ; ReplaceUses ( N , Result ) ; return


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return ( IsS11_0_Offset ( Offset . getNode ( ) ) ) ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return ( IsS11_0_Offset ( Offset . getNode


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRriS11_2 ( SDValue & Addr , SDValue & Base , SDValue & Offset ) { if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return ( IsS11_2_Offset ( Offset . getNode ( ) ) ) ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT>


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return ( IsS11_3_Offset ( Offset . getNode ( ) ) ) ; } Base = Addr ; Offset = CurDAG -> getTargetConstant (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRriU6_1 ( SDValue & Addr , SDValue & Base , SDValue & Offset ) { if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN ->


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRrr ( SDValue & Addr , SDValue & R1 , SDValue & R2 ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true


<s> EVT StoredVT = ST -> getMemoryVT ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Base ) -> getOffset ( ) ; if ( Offset != <NUM_LIT> && OffsetFitsS11 ( StoredVT , Offset ) ) { MVT PointerTy = TLI . getPointerTy ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Base ) -> getGlobal ( ) ; SDValue TargAddr = CurDAG -> getTargetGlobalAddress ( GV , dl , PointerTy , <NUM_LIT> ) ; SDNode * NewBase = CurDAG -> getMachineNode ( <STR_LIT> , dl , PointerTy , TargAddr ) ; if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Ops [ ] = { SDValue ( NewBase , <NUM_LIT> ) , CurDAG -> getTargetConstant ( Offset , PointerTy ) , Value , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand


<s> SDNode * IntRegTFR = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDNode * Pd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IntRegTFR , <NUM_LIT> ) ) ; SDNode * NotPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Pd , <NUM_LIT> ) ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Pd , <NUM_LIT> ) , SDValue ( NotPd , <NUM_LIT> ) ) ; ReplaceUses ( N , Result ) ; return Result


<s> ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; APFloat APF = CN -> getValueAPF ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstantFP ( APF . convertToFloat ( ) , <STR_LIT> ) ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstantFP ( APF . convertToDouble ( ) , <STR_LIT> ) ) ; } return SelectCode ( N


<s> return SelectIndexedLoadSignExtend64 ( LD , Opcode , dl ) ; } if ( TII -> isValidAutoIncImm ( LoadedVT , Val ) ) { SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result ; } else { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result ; } else { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_1


<s> SDNode * OffsetNode = Offset . getNode ( ) ; int32_t Val = cast < ConstantSDNode > ( OffsetNode ) -> getSExtValue ( ) ; SDValue N1 = LD -> getOperand ( <NUM_LIT> ) ; SDValue CPTmpN1_0 ; SDValue CPTmpN1_1 ; if ( SelectADDRriS11_2 ( N1 , CPTmpN1_0 , CPTmpN1_1 ) && N1 . getNode ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { if ( TII -> isValidAutoIncImm ( LoadedVT , Val ) ) { SDValue TargetConst = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConst , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2


<s> SDValue TargetConst = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConst , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) ,