<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) && Subtarget . hasV60TOps (


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> )


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) return Count ; if ( Count && ( I -> getOpcode ( ) == <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MBB . erase ( & MBB . back ( ) ) ; I = MBB .


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else { llvm_unreachable ( <STR_LIT>


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BasePosA , OffsetPosA ; if ( ! getBaseAndOffsetPosition ( MIa , BasePosA , OffsetPosA ) ) return false ; const MachineOperand & BaseA = MIa . getOperand ( BasePosA ) ; unsigned BaseRegA = BaseA . getReg ( ) ; unsigned BaseSubA = BaseA . getSubReg ( ) ; unsigned BasePosB , OffsetPosB ; if ( ! getBaseAndOffsetPosition ( MIb , BasePosB , OffsetPosB ) ) return false ; const MachineOperand & BaseB = MIb . getOperand ( BasePosB ) ; unsigned BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = getMemAccessSize ( MIa ) ; unsigned SizeB = getMemAccessSize ( MIb ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? <NUM_LIT> : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? <NUM_LIT> : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return SizeB


<s> if ( atInsnStart && ! std :: isspace ( static_cast < unsigned char > ( * Str ) ) ) { Length += MaxInstLength ; atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) . data ( ) , MAI . getCommentString ( ) . size ( ) ) == <NUM_LIT> ) atInsnStart = false ; } StringRef Occ ( <STR_LIT> ) ; Length += AStr . count ( Occ ) * <NUM_LIT> ; return Length


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( const MachineInstr & LdSt , const MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned AccessSize


<s> bool isAliased ( const MachineFrameInfo * ) const override { return false


<s> const uint64_t F = get ( Opcode ) . TSFlags ; return ( F >> <STR_LIT>


<s> bool mayAlias ( const MachineFrameInfo


<s> if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ; Cond . push_back ( MachineOperand :: CreateImm


<s> MachineFunction * MF = MBB . getParent ( ) ; DebugLoc DL = Cmp . getDebugLoc ( ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( & MBB , Cmp . getOpcode ( ) , Cmp . getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( ! Loop ) return <NUM_LIT> ; if ( Loop -> getOpcode ( ) == <STR_LIT> || Loop -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount )


<s> BuildMI ( * Loop -> getParent ( ) , Loop , Loop -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( TripCountAdjust ) ; Loop -> getOperand ( <NUM_LIT> ) . setReg (


<s> return ; } Register LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewLoopCount = TII -> createVR ( MF , <STR_LIT> ) ; BuildMI ( * Loop -> getParent ( ) , Loop , Loop -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( TripCountAdjust ) ; Loop -> getOperand ( <NUM_LIT> )


<s> unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg


<s> if ( I != LoopBB -> end ( ) && isEndLoopN ( I -> getOpcode ( ) ) ) { SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * LoopInst = findLoopInstr ( LoopBB , I -> getOpcode ( ) , I -> getOperand ( <NUM_LIT> ) . getMBB ( ) , VisitedBBs ) ; if ( LoopInst ) return std :: make_unique < <ISA_LIT>PipelinerLoopInfo > ( LoopInst , & * I ) ; } return


<s> void <ISA_LIT>InstrInfo :: changeDuplexOpcode ( MachineBasicBlock :: instr_iterator MII , bool ToBigInstrs ) const { int Opcode = - <NUM_LIT> ; if ( ToBigInstrs ) { if ( getDuplexCandidateGroup ( * MII ) ) Opcode =

getDuplexOpcode ( * MII , ToBigInstrs ) ;


<s> int Opcode = - <NUM_LIT> ; if ( ToBigInstrs ) { if ( getDuplexCandidateGroup ( * MII ) ) Opcode = getDuplexOpcode ( * MII , ToBigInstrs ) ; } else Opcode = getDuplexOpcode ( *


<s> if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR


<s> Optional < bool > createTripCountGreaterCondition ( int TC , MachineBasicBlock & MBB , SmallVectorImpl < MachineOperand > & Cond ) override { if ( TripCount == - <NUM_LIT> ) { unsigned Done = TII -> createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) , Done ) . addReg ( LoopCount ) . addImm ( TC ) ; Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ; Cond . push_back ( NewCmp -> getOperand (


<s> const TargetRegisterClass * TRC ; if ( VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else


<s> if ( ( GA . getOpcode ( ) != <STR_LIT> ) || ( GB . getOpcode ( ) != <STR_LIT> ) ) return - <NUM_LIT> ; Register DestReg = GA . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! GB . readsRegister ( DestReg ) ) return - <NUM_LIT> ; if ( DestReg != <STR_LIT> && DestReg != <STR_LIT> ) return - <NUM_LIT> ; const MachineOperand & CmpOp = GA . getOperand ( <NUM_LIT> ) ; if ( ! CmpOp . isImm ( ) ) return - <NUM_LIT> ; int V = CmpOp . getImm ( ) ; if ( V == - <NUM_LIT> ) return DestReg == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! isUInt < <NUM_LIT> > ( V ) ) return - <NUM_LIT> ; return DestReg == <STR_LIT> ?


<s> int NVOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : report_fatal_error ( Twine ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case


<s> int <ISA_LIT>InstrInfo :: getDuplexOpcode ( const MachineInstr & MI , bool ForBigCore ) const { static const std :: map < unsigned , unsigned > DupMap = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; unsigned OpNum = MI . getOpcode ( ) ; if ( ForBigCore


<s> SmallVector < std :: pair < MCPhysReg , const MachineOperand * > , <NUM_LIT> > Clobbers ; const MachineBasicBlock & B = * MI . getParent ( ) ; Regs . addLiveIns ( B ) ; auto E = MachineBasicBlock :: const_iterator ( MI . getIterator ( ) ) ; for ( auto I = B . begin ( ) ; I != E ; ++


<s> bool <ISA_LIT>InstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable ,

unsigned & Width , const TargetRegisterInfo * TRI ) const {


<s> const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , Width ) ; if ( ! BaseOp || ! BaseOp -> isReg (


<s> <ISA_LIT>PipelinerLoopInfo ( MachineInstr * Loop , MachineInstr * EndLoop ) : Loop ( Loop ) , EndLoop ( EndLoop ) , MF ( Loop -> getParent ( ) -> getParent ( ) ) , TII ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , DL ( Loop -> getDebugLoc ( ) ) { TripCount = Loop -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : Loop -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( TripCount == - <NUM_LIT> ) LoopCount = Loop -> getOperand ( <NUM_LIT>


<s> <ISA_LIT>PipelinerLoopInfo ( MachineInstr * Loop , MachineInstr * EndLoop ) : Loop ( Loop ) , EndLoop ( EndLoop ) , MF ( Loop -> getParent ( ) -> getParent ( ) ) , TII ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , DL ( Loop -> getDebugLoc ( ) ) { TripCount = Loop -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : Loop -> getOperand ( <NUM_LIT>


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( Register :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( Register :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid (

) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ;


<s> unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; return is_TC4x ( SchedClass ) ||


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> )


<s> for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ; } if ( MI . getDesc ( ) . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM_BR ) return


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex (


<s> Uses . clear ( ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( !


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Value = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return <NUM_LIT>


<s> MCInst <ISA_LIT>InstrInfo :: getNop ( ) const { static const MCInst Nop = MCInstBuilder ( <STR_LIT> ) ; return MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addInst


<s> return MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) .


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { auto Op = MI . getOperand ( <NUM_LIT> ) ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress ) return false ; if ( Op . isImm ( )


<s> case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case


<s> if ( isFloat ( MI ) && MI . hasRegisterImplicitUseOperand ( <STR_LIT> ) ) return false ; return true


<s> bool <ISA_LIT>InstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isFloat ( MI ) && MI . hasRegisterImplicitUseOperand ( <STR_LIT> ) ) return false ; return true


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI . getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI . getOperand ( oper ) ; if ( MO . isReg ( ) ) { if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : <STR_LIT> ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ; return


<s> if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; default : return - <NUM_LIT> ; } } return -


<s> int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { DefIdx = Idx ; break ; } } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & HRI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & HRI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx =


<s> DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI ) ; unsigned RegAlign = TRI -> getSpillAlignment ( * RC ) ; unsigned KillFlag = getKillRegState ( isKill ) ; bool HasAlloca = MFI . hasVarSizedObjects ( ) ; const auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering & HFI = * HST . getFrameLowering ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ,


<s> bool <ISA_LIT>InstrInfo :: addLatencyToSchedule ( const MachineInstr & MI1 , const MachineInstr & MI2


<s> for ( unsigned i = <NUM_LIT> , e = First . getNumOperands ( ) ; i < e ; ++ i ) { const MachineOperand & Op = First . getOperand ( i ) ; if ( Op . isReg ( ) && Op . isDef ( ) && Op . getReg ( ) == Stored . getReg ( ) ) return true ; } } return false


<s> Taken = MBPI -> getEdgeProbability ( Src , Dst ) >= OneHalf ; } else { assert ( MI . isConditionalBranch ( ) ) ; const MachineBasicBlock & B = * MI . getParent ( ) ; bool SawCond = false , Bad = false ; for ( const MachineInstr & I : B ) { if ( ! I . isBranch ( ) ) continue ; if ( I . isConditionalBranch ( ) ) { SawCond = true ; if ( & I != & MI ) { Bad = true ; break ; } } if ( I . isUnconditionalBranch ( ) && ! SawCond ) { Bad = true ; break ; } } if ( ! Bad ) { MachineBasicBlock :: const_instr_iterator It ( MI ) ; MachineBasicBlock :: const_instr_iterator NextIt = std :: next ( It ) ; if ( NextIt == B . instr_end ( ) ) { for ( const MachineBasicBlock * SB : B . successors (


<s> int NewOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NewOpcode >= <NUM_LIT> ) return NewOpcode ; dbgs ( ) << <STR_LIT> << getName ( MI . getOpcode ( )


<s> int NewOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NewOpcode >= <NUM_LIT> ) return NewOpcode ; dbgs ( ) << <STR_LIT> << getName ( MI . getOpcode ( ) ) << '\n' ; llvm_unreachable (


<s> int NewOp = MI . getOpcode ( ) ; if ( isPredicated ( NewOp ) && isPredicatedNew ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! HST . getFeatureBits ( ) [ <STR_LIT> ] ) { switch ( NewOp ) { case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> : NewOp =


<s> return ( MI . isBranch ( ) && isPredicated ( MI ) ) || isConditionalTransfer ( MI ) || isConditionalALU32 ( MI ) || isConditionalLoad ( MI ) || ( MI . mayStore ( ) && isPredicated ( MI ) && ! isNewValueStore ( MI


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> auto & HRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( <STR_LIT> . contains ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( <STR_LIT> . contains ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs

) if ( RegA == * SubRegs ) return true ;


<s> SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( <STR_LIT> . contains ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( <STR_LIT> . contains ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ; } return


<s> if ( MI . mayLoad ( ) || MI . mayStore ( ) || MI . isCompare ( ) ) return true ; unsigned SchedClass = MI . getDesc (


<s> if ( ! isV60VectorInstruction ( I ) ) return false ; if ( ! I . mayLoad ( ) && ! I . mayStore ( ) ) return false ; return J . isIndirectBranch ( ) || isIndirectCall (


<s> case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : case TargetOpcode :: PHI : return false ; default : break ; } unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; switch ( SchedClass ) { case <STR_LIT> :: ALU32_2op_tc_1_SLOT0123 : case <STR_LIT> :: ALU32_3op_tc_1_SLOT0123 : case <STR_LIT> :: ALU32_ADDI_tc_1_SLOT0123 : case <STR_LIT> :: ALU64_tc_1_SLOT23 : case <STR_LIT> :: EXTENDER_tc_1_SLOT0123 : case <STR_LIT> :: S_2op_tc_1_SLOT23 : case <STR_LIT> :: S_3op_tc_1_SLOT23 : case <STR_LIT> :: V2LDST_tc_ld_SLOT01 : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isLateSourceInstr ( const MachineInstr & MI ) const { return MI . getDesc ( ) . getSchedClass ( ) == <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( const MachineInstr & MI )


<s> bool <ISA_LIT>InstrInfo :: isTC1 ( const MachineInstr & MI ) const { unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; switch ( SchedClass ) { case <STR_LIT> :: ALU32_2op_tc_1_SLOT0123 : case <STR_LIT> :: ALU32_3op_tc_1_SLOT0123 : case <STR_LIT> :: ALU32_ADDI_tc_1_SLOT0123 : case <STR_LIT> :: ALU64_tc_1_SLOT23 : case <STR_LIT> :: EXTENDER_tc_1_SLOT0123 : case <STR_LIT> ::


<s> unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; return SchedClass == <STR_LIT> :: M_tc_3or4x_SLOT23


<s> unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ; return SchedClass == <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT>


<s> return isV60VectorInstruction ( MI )


<s> bool <ISA_LIT>InstrInfo :: isVecAcc ( const MachineInstr & MI ) const { return isV60VectorInstruction ( MI ) && isAccumulator (


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; }


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT>


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align <


<s> if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> )


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl <


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const

SmallVectorImpl < unsigned > & Ops , int FI ) const {


<s> getMatchingCondBranchOpcode ( int Opc , bool invertPredicate ) const { enum <STR_LIT> inPredSense ; inPredSense = invertPredicate ? <STR_LIT> : <STR_LIT> ; int CondOpcode = <STR_LIT> ( Opc , inPredSense ) ; if ( CondOpcode >= <NUM_LIT> ) return CondOpcode ; switch ( Opc )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return QRI . Subtarget . hasV4TOps ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) && isInt < <NUM_LIT> > ( MI ->

getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm


<s> } if ( needShift ) { for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand & MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else if ( MO . isGlobal ( ) ) { assert ( hasGAOpnd == false && <STR_LIT> ) ; tmpOpnds . push_back ( MO ) ; hasGAOpnd = true ; GAIdx = oper ; continue ; } else { llvm_unreachable ( <STR_LIT> ) ; } } } int regPos = invertJump ? <NUM_LIT> : <NUM_LIT> ; MachineOperand PredMO = Cond [ regPos ] ; if ( oper < - <NUM_LIT> ) oper = - <NUM_LIT> ; MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( PredMO . getReg ( ) , PredMO . isDef ( ) , PredMO . isImplicit ( ) ,

false , PredMO . isDead ( ) , PredMO . isUndef ( ) , PredMO . isDebug ( ) ) ;


<s> return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) !=


<s> I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; return


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; int regPos = <NUM_LIT> ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ) { BccOpc = <STR_LIT> ; regPos = <NUM_LIT> ; } if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; int regPos = <NUM_LIT> ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ) { BccOpc = <STR_LIT> ; regPos = <NUM_LIT> ; } if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond )


<s> TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) || ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) && LastInst -> getOpcode ( )


<s> if ( <STR_LIT> . contains ( SrcReg , DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( SrcReg == RI . getSubReg ( DestReg , <STR_LIT> ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , ( RI . getSubReg ( DestReg , <STR_LIT> ) ) ) . addImm ( <NUM_LIT> ) ; } return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } llvm_unreachable ( <STR_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: createVR ( MachineFunction * MF , MVT VT ) const { MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * TRC ; if ( VT == <STR_LIT>


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI -> getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = RI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == <STR_LIT> ) { Pred . push_back ( MO


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; int regPos = <NUM_LIT> ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ) { BccOpc = <STR_LIT> ; regPos = <NUM_LIT> ; } if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB )


<s> bool <ISA_LIT>InstrInfo :: isConditionalALU32 ( const MachineInstr * MI ) const { const <ISA_LIT>RegisterInfo & QRI = getRegisterInfo ( ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return QRI . Subtarget . get<ISA_LIT>ArchVersion ( ) == <ISA_LIT>Subtarget :: V4 ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , unsigned ExtraPredCycles , const

BranchProbability & Probability ) const {


<s> isSpillPredRegOp ( const MachineInstr * MI ) const { switch ( MI -> getOpcode


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return true ; } llvm_unreachable ( <STR_LIT> <STR_LIT> )


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; }


<s> int oper ; for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; int BccOpcNot = <STR_LIT> ; MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BOpc && I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BccOpc && I ->


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> -> hasSubClassEq (


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm (


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned VectorSize = TRI -> getSpillSize ( <STR_LIT> ) ; assert ( isPowerOf2_32 ( VectorSize ) ) ; if ( Offset & ( VectorSize - <NUM_LIT> ) ) return false ; return isInt < <NUM_LIT> > ( Offset >> Log2_32 ( VectorSize ) ) ; } case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT>


<s> FBB = nullptr ; MachineBasicBlock :: instr_iterator I = MBB . instr_end ( ) ; if ( I == MBB . instr_begin ( ) ) return false ; do { -- I ; if ( I -> isEHLabel ( ) ) return true ; } while ( I != MBB . instr_begin ( ) ) ; I = MBB . instr_end ( ) ; -- I ; while ( I -> isDebugValue ( ) ) { if ( I == MBB . instr_begin ( ) ) return false ; -- I ; } bool JumpToBlock = I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . isMBB ( ) ; if ( AllowModify && JumpToBlock && MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; I -> eraseFromParent ( ) ; I = MBB . instr_end ( ) ; if ( I == MBB . instr_begin ( ) ) return false ; -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; MachineInstr * SecondLastInst = nullptr ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( I ) ) { if ( ! SecondLastInst ) SecondLastInst = I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } while ( I ) ; int LastOpcode = LastInst -> getOpcode ( ) ; int SecLastOpcode = SecondLastInst ? SecondLastInst -> getOpcode ( ) : <NUM_LIT> ; if ( LastOpcode == <STR_LIT> && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( SecLastOpcode == <STR_LIT> && ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return


<s> case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MBB . erase ( MI ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1SubHi = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src1SubLo = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src2SubHi = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; unsigned Src2SubLo = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubHi ) . addReg ( Src2SubHi ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , int


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , int FI ) const { return nullptr


<s> if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( )


<s> for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand & MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else if ( MO . isGlobal ( ) ) { assert ( hasGAOpnd == false && <STR_LIT> ) ; tmpOpnds . push_back ( MO ) ; hasGAOpnd = true ; GAIdx = oper ; continue ; } else { llvm_unreachable ( <STR_LIT> ) ; } } } int regPos = invertJump ? <NUM_LIT>


<s> default : return <NUM_LIT> ; } I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; unsigned Opc2 = I -> getOpcode ( ) ; switch ( Opc2 ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : I -> eraseFromParent ( ) ; return <NUM_LIT> ; default : return <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isMBB ( ) ) return true ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm


<s> for ( MachineBasicBlock :: pred_iterator PB = BB -> pred_begin ( ) , PE = BB -> pred_end ( ) ; PB != PE ; ++ PB ) { if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( *

PB ) -> instr_rend ( ) ; I != E ; ++ I ) {


<s> Register BaseRegB = BaseB . getReg ( ) ; unsigned BaseSubB = BaseB . getSubReg ( ) ; if ( BaseRegA != BaseRegB || BaseSubA != BaseSubB ) return false ; unsigned SizeA = getMemAccessSize ( MIa ) ; unsigned SizeB = getMemAccessSize ( MIb ) ; const MachineOperand & OffA = MIa . getOperand ( OffsetPosA ) ; const MachineOperand & OffB = MIb . getOperand ( OffsetPosB ) ; if ( ! MIa . getOperand ( OffsetPosA ) . isImm ( ) || ! MIb . getOperand ( OffsetPosB ) . isImm ( ) ) return false ; int OffsetA = isPostIncrement ( MIa ) ? <NUM_LIT> : OffA . getImm ( ) ; int OffsetB = isPostIncrement ( MIb ) ? <NUM_LIT> : OffB . getImm ( ) ; if ( OffsetA > OffsetB ) { uint64_t OffDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return SizeB <= OffDiff ; } if ( OffsetA < OffsetB


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb , AliasAnalysis * AA ) const { if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BasePosA , OffsetPosA ; if ( ! getBaseAndOffsetPosition ( MIa , BasePosA , OffsetPosA ) ) return false ; const MachineOperand & BaseA = MIa . getOperand ( BasePosA ) ; Register BaseRegA = BaseA . getReg ( ) ; unsigned BaseSubA = BaseA


<s> else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; Register LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ;

++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ;


<s> -- I ; } if ( AllowModify && I -> getOpcode ( ) == <STR_LIT> && MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; I -> eraseFromParent ( ) ; I = MBB . instr_end ( ) ; if ( I == MBB . instr_begin ( ) ) return false ; -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; MachineInstr * SecondLastInst = nullptr ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( I ) ) { if ( ! SecondLastInst ) SecondLastInst = I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } while ( I ) ; int LastOpcode = LastInst -> getOpcode ( ) ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ; unsigned S = ( F >> MemAccessSizePos ) & MemAccesSizeMask ; unsigned Size = getMemAccessSizeInBytes ( MemAccessSize ( S ) ) ; if ( Size != <NUM_LIT> ) return Size ; if ( MI . getOpcode ( ) == <STR_LIT> ) return <STR_LIT> ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; switch ( S ) { case <STR_LIT> : return HRI . getSpillSize (


<s> MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI . getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI . getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . add ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ; ( void ) GotPredReg ; assert ( GotPredReg ) ; T . addReg ( PredReg , PredRegFlags ) ; while ( NOp < NumOps ) T . add ( MI . getOperand ( NOp ++ ) ) ; MI . setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI . getNumOperands ( ) ) MI . removeOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI . addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ; MRI . clearKillFlags ( PredReg


<s> if ( Offset % Size != <NUM_LIT> ) return false ; int Count = Offset / Size ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > (


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const override { return nullptr


<s> <STR_LIT> <ISA_LIT>InstrInfo :: getCompoundCandidateGroup ( const MachineInstr & MI ) const { unsigned DstReg , SrcReg , Src1Reg , Src2Reg ; switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( Src1Reg ) && isIntRegForSubInst ( Src2Reg ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( SrcReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ( ( isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) || ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && isIntRegForSubInst ( Src1Reg ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Src1Reg ) && ( <STR_LIT> == Src1Reg ||


<s> int <ISA_LIT>InstrInfo :: getDotNewOp ( const MachineInstr & MI ) const { int NVOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> const MachineBasicBlock * Dst = BrTarget . getMBB ( ) ; const BranchProbability Prediction = MBPI -> getEdgeProbability ( Src , Dst ) ; if ( Prediction >= BranchProbability ( <NUM_LIT> , <NUM_LIT> ) ) taken = true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return taken ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return taken ? <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isCompoundBranchInstr ( const MachineInstr & MI ) const { return ( getType ( MI ) == <STR_LIT> && MI . isBranch (


<s> bool <ISA_LIT>InstrInfo :: isCompoundBranchInstr ( const MachineInstr & MI ) const { return ( getType ( MI ) == <STR_LIT> &&


<s> const uint64_t F = MID . TSFlags ; if ( ( F >> <STR_LIT> ) & <STR_LIT> ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return true ; default : return


<s> bool <ISA_LIT>InstrInfo :: isIndirectCall ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( offset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> >


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN_128B ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX_128B ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) .


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> .


<s> bool <ISA_LIT>InstrInfo :: predCanBeUsedAsDotNew ( const MachineInstr & MI , unsigned PredReg ) const { for ( unsigned opNum = <NUM_LIT> ; opNum < MI . getNumOperands ( ) ; opNum ++ ) { const MachineOperand & MO = MI . getOperand (


<s> MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , getRegisterInfo ( ) ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ; Cond . push_back ( MachineOperand ::


<s> DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; unsigned KillFlag = getKillRegState ( isKill ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( )


<s> int NVOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr * MI ) const { bool isPred = MI -> getDesc ( ) . isPredicable ( ) ; if ( ! isPred ) return false ; const int Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : return isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> )


<s> case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT>


<s> return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) || ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) .


<s> TBB = NULL ; FBB = NULL ; MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return false ; do { -- I ; if ( I -> isEHLabel ( ) ) return true ; } while ( I != MBB . begin ( ) ) ; I = MBB . end ( ) ; -- I ; while ( I -> isDebugValue ( ) ) { if ( I == MBB . begin ( ) ) return false ; -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( ( ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) || ( SecondLastInst -> getOpcode ( ) == <STR_LIT> ) ) && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = ~ <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Mask = <NUM_LIT> ; break ; } switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg2 = <NUM_LIT> ; Value = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; } return false


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT>


<s> bool hasGAOpnd = false ; std :: vector < MachineOperand > tmpOpnds ; bool needShift = true ; if ( MI -> getNumOperands ( ) == <NUM_LIT> ) { needShift = false ; oper = - <NUM_LIT> ; } else if ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isDef ( ) && ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isImplicit ( ) ) { MI -> addOperand ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) ) ; needShift = false ; oper = MI -> getNumOperands ( ) - <NUM_LIT> ; } else { MI -> addOperand ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) ) ; } if ( needShift ) { for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand & MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else if ( MO . isGlobal (


<s> bool <ISA_LIT>InstrInfo :: getMemOperandsWithOffset ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , const


<s> unsigned AccessSize = <NUM_LIT> ; OffsetIsScalable = false ; const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ; if ( ! BaseOp || ! BaseOp


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT>


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) .


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlignment ( FI ) ; unsigned KillFlag = getKillRegState ( isKill ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> .