<s> Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || ( LocVT == <STR_LIT> && UseHVX && UseHVXDbl ) ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>Vector ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } return true


<s> EVT ValTy = Op . getValueType ( ) ; ConstantPoolSDNode * CPN = cast < ConstantPoolSDNode > ( Op ) ; Constant * CVal = nullptr ; bool isVTi1Type = false ; if ( auto * CV = dyn_cast < ConstantVector > ( CPN -> getConstVal ( ) ) ) { if ( cast < VectorType > ( CV -> getType ( ) ) -> getElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { IRBuilder < > IRB ( CV -> getContext ( ) ) ; SmallVector < Constant * , <NUM_LIT> > NewConst ; unsigned VecLen = CV -> getNumOperands ( ) ; assert ( isPowerOf2_32 ( VecLen ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < VecLen ; ++ i ) NewConst . push_back ( IRB . getInt8 ( CV -> getOperand ( i ) -> isZeroValue ( ) ) ) ; CVal = ConstantVector :: get ( NewConst ) ; isVTi1Type = true ; } } unsigned Align = CPN -> getAlignment ( ) ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned char TF = IsPositionIndependent ? <STR_LIT>


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return


<s> case 'r' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'q' : switch ( VT . getSizeInBits ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . getSizeInBits ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op


<s> return false ; } } else if ( LocVT == <STR_LIT> ) { unsigned Req = ( UseHVX && UseHVXDbl ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if ( LocVT


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , unsigned Align , bool * Fast ) const { if ( Fast ) * Fast = false ; return Subtarget . isHVXVectorType ( VT . getSimpleVT


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AS , unsigned Align , bool * Fast ) const { if ( Fast ) * Fast = false ; return Subtarget . isHVXVectorType ( VT


<s> SDValue <ISA_LIT>TargetLowering :: buildVector32 ( ArrayRef < SDValue > Elem , const SDLoc & dl , MVT VecTy , SelectionDAG & DAG ) const { MVT ElemTy = VecTy . getVectorElementType ( ) ; assert ( VecTy . getVectorNumElements ( ) == Elem . size ( ) ) ; SmallVector < ConstantInt * , <NUM_LIT> > Consts ( Elem . size ( ) ) ; bool AllConst = getBuildVectorConstInts ( Elem , VecTy , DAG , Consts ) ; unsigned First , Num = Elem . size ( ) ; for ( First = <NUM_LIT> ; First != Num ; ++ First ) if ( ! isUndef ( Elem [ First ] ) ) break ; if ( First == Num ) return DAG . getUNDEF ( VecTy ) ; if ( AllConst && llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; if ( ElemTy == <STR_LIT> ) { assert ( Elem . size ( ) == <NUM_LIT> ) ; if ( AllConst ) { uint32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } SDValue N = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Elem [ <NUM_LIT> ] , Elem [


<s> SmallVector < ConstantInt * , <NUM_LIT> > Consts ( Elem . size ( ) ) ; bool AllConst = getBuildVectorConstInts ( Elem , VecTy , DAG , Consts ) ; unsigned First , Num = Elem . size ( ) ; for ( First = <NUM_LIT> ; First != Num ; ++ First ) if ( ! isUndef ( Elem [ First ] ) ) break ; if ( First == Num ) return DAG . getUNDEF ( VecTy ) ; if ( AllConst && llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; if ( ElemTy == <STR_LIT> ) { bool IsSplat = true ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) { if ( i == First ) continue ; if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts

[ Num - <NUM_LIT> - i ] -> getZExtValue ( ) & Mask ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useHVXOps ( ) )

return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>_HVX ) ;


<s> static bool CC_SkipOdd ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs ) ; if ( RegNum != NumArgRegs && RegNum % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgRegs [ RegNum ] ) ; return false


<s> unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; PointerType * NewPtrTy = Builder . getIntNTy ( SZ ) -> getPointerTo (


<s> Module * M = BB -> getParent ( ) -> getParent ( ) ; Type * Ty = Val -> getType ( ) ; unsigned SZ = Ty -> getPrimitiveSizeInBits ( ) ; Type * CastTy = Builder . getIntNTy ( SZ ) ; assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Value * Fn = <STR_LIT> ( M , IntID ) ; unsigned AS = Addr -> getType ( ) -> getPointerAddressSpace ( ) ; Addr = Builder . CreateBitCast ( Addr , CastTy -> getPointerTo ( AS ) ) ; Val = Builder . CreateBitCast ( Val , CastTy ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * Ext = Builder . CreateZExt ( Cmp , Type :: getInt32Ty ( M


<s> if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; SDValue M0 = DAG . getConstant ( <NUM_LIT> / VecWidth , dl , <STR_LIT> ) ; SDValue I0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , M0 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , I0 ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; unsigned VecRep = <NUM_LIT> / VecWidth ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * VecRep , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ; if ( IdxN ) { unsigned Off = IdxN -> getZExtValue ( ) * ElemWidth ; if ( VecWidth == <NUM_LIT> && ValWidth == <NUM_LIT> ) { assert ( Off == <NUM_LIT> || Off == <NUM_LIT> ) ; unsigned SubIdx = Off == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; ExtV = DAG . getTargetExtractSubreg ( SubIdx , dl , <STR_LIT> , VecV ) ; } else if ( Off == <NUM_LIT> && ( ValWidth % <NUM_LIT> ) == <NUM_LIT> ) { ExtV = DAG . getZeroExtendInReg ( VecV , dl , tyScalar ( ValTy ) ) ; } else { SDValue OffV = DAG . getConstant ( Off , dl , <STR_LIT> ) ; ExtV = DAG . getNode ( <STR_LIT> , dl , ScalarTy , { VecV , WidthV , OffV } ) ; } } else { if ( ty ( IdxV ) != <STR_LIT> ) IdxV = DAG . getZExtOrTrunc ( IdxV , dl , <STR_LIT> ) ; SDValue OffV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV ,

DAG . getConstant ( ElemWidth , dl , <STR_LIT> ) ) ;


<s> static Value * getBrevLdObject ( Value * V ) { if ( Operator :: getOpcode ( V ) == Instruction :: ExtractValue || Operator :: getOpcode ( V ) == Instruction :: BitCast ) V =

cast < Operator > ( V ) -> getOperand ( <NUM_LIT> ) ;


<s> else if ( isa < IntrinsicInst > ( V ) && isBrevLdIntrinsic ( V ) ) V = cast < Instruction > ( V ) -> getOperand ( <NUM_LIT> ) ; return V


<s> for ( unsigned i = <NUM_LIT> , e = Values . size ( ) ; i != e ; ++ i ) { SDValue V = Values [ i ] ; if ( V . isUndef ( ) ) { Consts [ i ] = ConstantInt :: get ( IntTy , <NUM_LIT> ) ; continue ; } if ( auto * CN = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) { const ConstantInt * CI = CN -> getConstantIntValue ( ) ; Consts [ i ] = ConstantInt :: get ( IntTy , CI -> getValue ( ) . getSExtValue ( ) ) ; } else if ( auto * CN = dyn_cast < ConstantFPSDNode > ( V . getNode (


<s> EVT VT = LSN -> getMemoryVT ( ) ; if ( ! VT . isSimple ( ) ) return false ; bool IsLegalType = VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ||

Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ;


<s> if ( Subtarget . useHVXOps ( ) ) { ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * Subtarget . getVectorLength ( ) ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth <

HwWidth ) return TargetLoweringBase :: TypeWidenVector ;


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> )


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> BaseVal = V ; V = getBrevLdObject ( V ) ; } while ( BaseVal != V ) ; if ( const PHINode * PN = dyn_cast < PHINode > ( V ) )

return returnEdge ( PN , IntrBaseVal ) ;


<s> if ( auto * BVN = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { if ( SDValue S = BVN -> getSplatValue ( ) ) { unsigned NewOpc ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT>


<s> SDValue Width = DAG . getConstant ( ValBytes * <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Idx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VecR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue Ins = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { VecR , ValR , Width , Idx } ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ins ) ; } unsigned VecWidth = VecTy . getSizeInBits ( ) ; unsigned ValWidth = ValTy . getSizeInBits ( ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; assert ( ( VecWidth % ValWidth ) == <NUM_LIT> ) ; MVT ScalarTy = <STR_LIT> ( VecWidth ) ; unsigned VW = ty ( ValV ) . getSizeInBits ( ) ; ValV = DAG . getBitcast ( <STR_LIT> ( VW ) , ValV ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; if ( VW != VecWidth ) ValV = DAG . getAnyExtOrTrunc ( ValV , dl , ScalarTy ) ; SDValue WidthV = DAG . getConstant ( ValWidth ,


<s> static bool isBrevLdIntrinsic ( const Value * Inst ) { unsigned ID = cast < IntrinsicInst >


<s> } if ( ! CCMatch ) { bool R = ( CallerCC == CallingConv :: C || CallerCC == CallingConv :: Fast ) ; bool E = ( CalleeCC == CallingConv :: C || CalleeCC == CallingConv :: Fast ) ; if ( ! R || ! E ) return false ; } if ( IsVarArg ) return false ; if ( IsCalleeStructRet || IsCallerStructRet ) return false ; return true


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return


<s> SDValue X = Op . getOperand ( <NUM_LIT> ) , Y = Op . getOperand ( <NUM_LIT> ) , C = Op . getOperand ( <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , Op . getNode ( ) -> getVTList ( ) , { X , Y , C } ) ; EVT CarryTy = C . getValueType ( ) ; SDValue SubC = DAG . getNode ( <STR_LIT> , dl , Op . getNode ( ) -> getVTList ( ) , { X , Y , DAG . getLogicalNOT ( dl , C , CarryTy ) } ) ; SDValue Out [ ] = { SubC . getValue ( <NUM_LIT> ) , DAG . getLogicalNOT ( dl , SubC . getValue


<s> assert ( ResTy . getSizeInBits ( ) == InpTy . getSizeInBits ( ) ) ; const SDLoc & dl ( Op ) ; if ( ResTy == <STR_LIT> ) { SDValue Sc = DAG . getBitcast ( tyScalar ( InpTy


<s> SDValue <ISA_LIT>TargetLowering :: LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) const { MVT ResTy = ty ( Op ) ; SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT InpTy = ty ( InpV ) ; assert ( ResTy . getSizeInBits ( ) == InpTy . getSizeInBits ( ) ) ; const SDLoc & dl ( Op ) ; if ( ResTy == <STR_LIT> ) { SDValue Sc = DAG . getBitcast ( tyScalar ( InpTy )


<s> if ( VecTy == <STR_LIT> || VecTy == <STR_LIT> || VecTy == <STR_LIT> ) { SDValue Rs [ <NUM_LIT> ] ; SDValue Z = getZero ( dl , <STR_LIT> , DAG ) ; unsigned Rep = <NUM_LIT> / VecTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SDValue S = DAG . getConstant ( <NUM_LIT> << i , dl , <STR_LIT> ) ; Rs [ i ] = DAG . getSelect ( dl , <STR_LIT> , Ops [ i / Rep ] , S , Z ) ; } for ( ArrayRef < SDValue > A ( Rs ) ; A . size ( ) != <NUM_LIT> ; A = A . drop_back ( A . size ( ) / <NUM_LIT> ) ) { for ( unsigned i = <NUM_LIT> , e = A . size ( ) / <NUM_LIT> ; i != e ; ++ i ) Rs [ i ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Rs [ <NUM_LIT> * i ] ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; Chain = TPR . getValue ( <NUM_LIT> ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Align = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; ConstantSDNode * AlignConst = dyn_cast < ConstantSDNode > ( Align ) ; assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ; LLVM_DEBUG ( { dbgs ( ) << __func__ << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( )


<s> dbgs ( ) << __func__ << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( ) << <STR_LIT> ; } ) ; SDValue AC = DAG . getConstant ( A , dl , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue AA = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Size , AC ) ; DAG . ReplaceAllUsesOfValueWith ( Op ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { return extractVector ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ty


<s> return extractVector ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ty ( Op ) , ty ( Op )


<s> MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty


<s> <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) , MF . getFunction ( ) . getFunctionType ( ) -> getNumParams ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool ByVal = Flags . isByVal ( ) ; if ( VA . isRegLoc ( ) && ByVal && Flags . getByValSize ( ) <= <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool InReg = VA . isRegLoc ( ) && ( ! ByVal || ( ByVal && Flags . getByValSize ( ) > <NUM_LIT> ) ) ; if ( InReg ) { MVT RegVT = VA . getLocVT ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) RegVT = VA . getValVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned VReg = MRI . createVirtualRegister ( RC ) ; SDValue Copy = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getValVT ( ) == <STR_LIT> ) { assert ( RegVT . getSizeInBits ( ) <= <NUM_LIT> ) ; SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI


<s> auto & HLOF = * HTM . getObjFileLowering ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && Subtarget . useSmallData ( ) && HLOF . isGlobalInSmallSection ( GO , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } bool UsePCRel = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; if ( UsePCRel ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; } SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SDValue ValV = Op . getOperand (


<s> return insertVector ( Op . getOperand ( <NUM_LIT> ) , ValV , Op . getOperand ( <NUM_LIT> )


<s> void <ISA_LIT>TargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG


<s> if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerROTL ( SDValue Op , SelectionDAG & DAG ) const { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return Op ; return SDValue (


<s> SDValue <ISA_LIT>TargetLowering :: LowerStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * SN = cast < StoreSDNode > ( Op . getNode ( ) ) ; unsigned ClaimAlign = SN -> getAlignment ( ) ; SDValue Ptr = SN -> getBasePtr ( ) ; const SDLoc & dl ( Op ) ; validateConstPtrAlignment ( Ptr , dl , ClaimAlign ) ; MVT StoreTy = SN -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned NeedAlign = Subtarget . getTypeAlignment ( StoreTy ) ; if ( ClaimAlign < NeedAlign ) return


<s> const SDLoc & dl ( Op ) ; const DataLayout & DL = DAG . getDataLayout ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; unsigned AS = LN -> getAddressSpace ( ) ; bool DoDefault = false ; if ( ! LN -> isUnindexed ( ) ) DoDefault = true ; if ( ! AlignLoads ) { if ( allowsMemoryAccess ( Ctx , DL , LN -> getMemoryVT ( ) , AS , HaveAlign ) ) return Op ; DoDefault = true ; } if ( ! DoDefault && <NUM_LIT> * HaveAlign == NeedAlign ) { MVT PartTy = HaveAlign <= <NUM_LIT> ? <STR_LIT> ( <NUM_LIT> * HaveAlign ) : <STR_LIT> ( <STR_LIT> , HaveAlign ) ; DoDefault = allowsMemoryAccess ( Ctx , DL , PartTy , AS , HaveAlign ) ; } if ( DoDefault ) { std :: pair < SDValue , SDValue > P = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( { P . first , P . second } , dl ) ; } assert ( LoadTy . getSizeInBits ( ) == <NUM_LIT> * NeedAlign ) ; unsigned LoadLen = NeedAlign ; SDValue Base = LN -> getBasePtr ( ) ; SDValue Chain = LN -> getChain ( ) ; auto BO = getBaseAndOffset ( Base ) ; unsigned BaseOpc = BO . first . getOpcode ( ) ; if ( BaseOpc == <STR_LIT> && BO . second % LoadLen == <NUM_LIT> ) return Op ; if ( BO . second % LoadLen != <NUM_LIT> ) { BO . first = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( BO . second % LoadLen , dl , <STR_LIT> ) ) ; BO . second -= BO . second % LoadLen ; } SDValue BaseNoOff = ( BaseOpc != <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( NeedAlign , dl , <STR_LIT> ) ) : BO . first ; SDValue Base0 = DAG . getMemBasePlusOffset ( BaseNoOff , BO . second , dl ) ; SDValue Base1 = DAG . getMemBasePlusOffset ( BaseNoOff , BO . second + LoadLen , dl ) ; MachineMemOperand * WideMMO =


<s> DoDefault = true ; } if ( ! DoDefault && <NUM_LIT> * HaveAlign == NeedAlign ) { MVT PartTy = HaveAlign <= <NUM_LIT> ? <STR_LIT> ( <NUM_LIT> * HaveAlign ) : <STR_LIT> ( <STR_LIT> , HaveAlign ) ; DoDefault = allowsMemoryAccess ( Ctx , DL , PartTy , AS , HaveAlign ) ; } if ( DoDefault ) { std :: pair < SDValue , SDValue > P = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( { P . first , P . second } , dl ) ; } assert ( LoadTy . getSizeInBits ( ) == <NUM_LIT> * NeedAlign ) ; unsigned LoadLen = NeedAlign ; SDValue Base = LN -> getBasePtr ( ) ; SDValue Chain = LN -> getChain ( ) ; auto BO = getBaseAndOffset ( Base ) ; unsigned BaseOpc = BO . first . getOpcode ( ) ; if ( BaseOpc == <STR_LIT> && BO . second % LoadLen == <NUM_LIT> ) return Op ; if ( BO . second % LoadLen != <NUM_LIT> ) { BO . first = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( BO . second % LoadLen , dl , <STR_LIT> ) ) ; BO . second -= BO . second % LoadLen ; } SDValue BaseNoOff = ( BaseOpc != <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BO . first , DAG . getConstant ( NeedAlign , dl , <STR_LIT> ) ) : BO . first ; SDValue Base0 = DAG . getMemBasePlusOffset ( BaseNoOff , BO . second , dl ) ; SDValue Base1 = DAG . getMemBasePlusOffset ( BaseNoOff , BO


<s> if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat10 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat10 } , DAG ) ; SDValue Concat01 = DAG . getNode ( <STR_LIT> , dl , typeJoin ( { ty ( Op0 ) , ty ( Op1 ) } ) , { Op0 , Op1 } ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat01 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat01 } , DAG ) ; } if ( ByteMask . size ( ) == <NUM_LIT> ) { if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return Op0 ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) { SDValue T0 = DAG . getBitcast ( <STR_LIT> , Op0 ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 ) ; return DAG . getBitcast ( VecTy , T1 ) ; } if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) { VectorPair P = opSplit ( Op0 , dl , DAG ) ; return getInstr ( <STR_LIT> , dl , VecTy , { P . second , P . first } , DAG ) ; } if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 ,


<s> unsigned S = <NUM_LIT> * i ; uint64_t M = ByteMask [ i ] & <NUM_LIT> ; if ( M == <NUM_LIT> ) MaskUnd |= M << S ; MaskIdx |= M << S ; } if ( ByteMask . size ( ) == <NUM_LIT> ) { if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return Op0 ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) { SDValue T0 = DAG . getBitcast ( <STR_LIT> , Op0 ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 ) ; return DAG . getBitcast ( VecTy , T1 ) ; } SDValue Concat10 = DAG . getNode ( <STR_LIT> , dl , typeJoin ( { ty ( Op1 ) , ty ( Op0 ) } ) , { Op1 , Op0 } ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat10 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat10 } , DAG ) ; SDValue Concat01 = DAG . getNode ( <STR_LIT> , dl , typeJoin ( { ty ( Op0 ) , ty ( Op1 ) } ) , { Op0 , Op1 } ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat01 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Concat01 } , DAG ) ; } if ( ByteMask . size ( ) == <NUM_LIT> ) { if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return Op0 ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) { SDValue T0 = DAG . getBitcast ( <STR_LIT> , Op0 ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 ) ; return DAG . getBitcast ( VecTy , T1 ) ; } if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) return getInstr ( <STR_LIT> , dl , VecTy , { Op1 , Op0 } , DAG ) ; if ( MaskIdx == ( <NUM_LIT> | MaskUnd ) ) { VectorPair P = opSplit ( Op0 , dl , DAG ) ; return getInstr ( <STR_LIT> , dl , VecTy , { P . second ,


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { const SDLoc & dl ( N ) ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ; case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT>


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { const DataLayout & DL = AI -> getModule ( )


<s> const DataLayout & DL = AI -> getModule ( ) -> getDataLayout ( ) ; unsigned Size = DL . getTypeStoreSize ( AI -> getCompareOperand (


<s> std :: pair < SDValue , int > BO = getBaseAndOffset ( L -> getBasePtr ( ) ) ; if ( BO . first . getOpcode ( ) == <STR_LIT> ) return false ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( BO . first ) ) { auto & HTM = static_cast < const <ISA_LIT>TargetMachine &


<s> auto * CA = dyn_cast < ConstantSDNode > ( Ptr ) ; if ( ! CA ) return ; unsigned Addr = CA -> getZExtValue ( ) ; unsigned HaveAlign = Addr != <NUM_LIT> ? <NUM_LIT> << countTrailingZeros ( Addr ) : NeedAlign ; if ( HaveAlign < NeedAlign ) { std :: string ErrMsg ; raw_string_ostream O ( ErrMsg ) ; O << <STR_LIT> << format_hex ( Addr , <NUM_LIT> ) << <STR_LIT> << HaveAlign


<s> SDValue <ISA_LIT>TargetLowering :: contractPredicate ( SDValue Vec64 , const SDLoc & dl , SelectionDAG & DAG ) const { assert ( ty ( Vec64 ) . getSizeInBits ( ) == <NUM_LIT> ) ; if ( isUndef ( Vec64 ) ) return DAG . getUNDEF (


<s> if ( isUndef ( Vec32 ) ) return DAG . getUNDEF ( <STR_LIT> ) ; return getNode ( <STR_LIT> , dl , <STR_LIT> , { Vec32 } ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT InpTy = ty ( InpV ) ; assert ( ResTy . getSizeInBits ( ) == InpTy . getSizeInBits ( ) ) ; const SDLoc & dl ( Op ) ; if ( ResTy == <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) const { MVT ResTy = ty ( Op ) ; SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT InpTy = ty ( InpV ) ; assert ( ResTy . getSizeInBits ( ) == InpTy . getSizeInBits ( ) ) ; const SDLoc & dl ( Op ) ; if ( ResTy == <STR_LIT> ) { SDValue Sc = DAG . getBitcast ( tyScalar ( InpTy


<s> SDValue <ISA_LIT>TargetLowering :: LowerBUILD_VECTOR ( SDValue Op , SelectionDAG & DAG ) const { MVT VecTy = ty ( Op ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxBuildVector ( Op , DAG ) ; unsigned BW = VecTy . getSizeInBits ( ) ; const SDLoc & dl ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( BW == <NUM_LIT> ) return buildVector32 ( Ops , dl , VecTy , DAG ) ; if ( BW == <NUM_LIT> ) return buildVector64 ( Ops , dl , VecTy , DAG ) ; if ( VecTy == <STR_LIT> || VecTy == <STR_LIT> || VecTy == <STR_LIT> ) { SDValue Rs [ <NUM_LIT> ] ; SDValue Z = getZero ( dl , <STR_LIT> , DAG ) ; unsigned Rep = <NUM_LIT> / VecTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { SDValue S = DAG . getConstant ( <NUM_LIT> << i , dl


<s> } while ( Scale > <NUM_LIT> ) { SDValue WidthV = DAG . getConstant ( <NUM_LIT> / Scale , dl , <STR_LIT> ) ; Words [ IdxW ^ <NUM_LIT> ] . clear ( ) ; for ( unsigned i = <NUM_LIT> , e = Words [ IdxW ] . size ( ) ; i != e ; i += <NUM_LIT> ) { SDValue W0 = Words [ IdxW ] [ i ] , W1 = Words [ IdxW ] [ i + <NUM_LIT> ] ; SDValue T = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { W0 , W1 , WidthV , WidthV } ) ; Words [ IdxW ^ <NUM_LIT> ] . push_back ( T ) ; } IdxW ^= <NUM_LIT> ; Scale /= <NUM_LIT> ; } assert ( Scale == <NUM_LIT> && Words [ IdxW ] . size ( ) == <NUM_LIT> ) ; SDValue WW = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Words [ IdxW ] [ <NUM_LIT> ] , Words [ IdxW ] [ <NUM_LIT> ] ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , WW


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxConcatVectors ( Op , DAG ) ; assert ( VecTy == <STR_LIT> || VecTy == <STR_LIT> || VecTy == <STR_LIT> ) ; MVT OpTy = ty ( Op . getOperand ( <NUM_LIT> ) ) ; unsigned Scale = VecTy . getVectorNumElements ( ) / OpTy . getVectorNumElements ( ) ; assert ( Scale == Op . getNumOperands ( ) && Scale > <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Words [ <NUM_LIT> ] ; unsigned IdxW = <NUM_LIT> ; for ( SDValue P : Op . getNode ( ) -> op_values ( ) ) { SDValue W = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , P ) ; for ( unsigned R = Scale ; R > <NUM_LIT> ; R /= <NUM_LIT> ) { W = contractPredicate ( W , dl , DAG ) ; W = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , W ) ; } W = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , W ) ; Words [ IdxW ] . push_back ( W ) ; } while ( Scale > <NUM_LIT> ) { SDValue WidthV = DAG . getConstant ( <NUM_LIT> / Scale , dl , <STR_LIT> ) ; Words [ IdxW ^ <NUM_LIT> ] . clear ( ) ; for ( unsigned i = <NUM_LIT> , e = Words [ IdxW ] . size ( ) ; i != e ; i += <NUM_LIT> ) { SDValue W0 = Words [ IdxW ] [ i ] , W1 = Words [ IdxW ] [ i + <NUM_LIT> ] ; SDValue T = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { W0 , W1 , WidthV , WidthV } ) ; Words [ IdxW ^ <NUM_LIT> ] . push_back ( T ) ; } IdxW ^= <NUM_LIT> ; Scale /= <NUM_LIT> ; } assert ( Scale == <NUM_LIT> && Words [ IdxW ] . size ( ) == <NUM_LIT>


<s> MVT VecTy = ty ( Vec ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxExtractSubvector ( Op , DAG ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ty ( Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; MVT VecTy = ty ( Vec ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty


<s> MVT VecTy = ty ( Vec ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty (


<s> SDValue ValV = Op . getOperand ( <NUM_LIT> ) ; return insertVector ( Op . getOperand ( <NUM_LIT> ) , ValV , Op . getOperand ( <NUM_LIT> ) , SDLoc


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { MVT VecTy = ty ( Op ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxInsertElement ( Op , DAG ) ; return insertVector ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op )

, VecTy . getVectorElementType ( ) , DAG ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op ,


<s> SDValue <ISA_LIT>TargetLowering :: LowerZERO_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { MVT ResTy = ty ( Op ) ; SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( InpV ) . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> && Subtarget . isHVXVectorType ( ResTy ) ) return extendHvxVectorPred ( InpV , SDLoc ( Op ) , ty ( Op ) , true , DAG ) ; return Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerZERO_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { MVT ResTy = ty ( Op ) ; SDValue InpV = Op . getOperand (


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> int32_t SV = SplatBitSize < <NUM_LIT> ? int32_t ( ZV << ( <NUM_LIT> - SplatBitSize ) ) >> ( <NUM_LIT> - SplatBitSize ) : int32_t ( ZV ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( SV , dl , <STR_LIT> ) ) ; } } } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { SDValue V0 = BVN -> getOperand ( <NUM_LIT> ) ; SDValue V1 = BVN -> getOperand ( <NUM_LIT> ) ; if ( V0 . isUndef ( ) ) V0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( V1 . isUndef ( ) ) V1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( V0 ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( V1 ) ; if ( ! C0 || ! C1 ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; if ( isInt < <NUM_LIT> > ( C0 -> getSExtValue ( ) ) || isInt < <NUM_LIT> > ( C1 -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i ) . isUndef ( ) ) continue ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( i ) ) ; if ( ! Cst ) { SDValue pack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BVN -> getOperand ( <NUM_LIT> ) , BVN -> getOperand ( <NUM_LIT> ) ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , pack ) ; } } } uint64_t Res =


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG


<s> if ( UseHVX ) { ArrayRef < int > Mask = SVN -> getMask ( ) ; size_t MaskLen = Mask . size ( ) ; unsigned SizeInBits = VT . getScalarSizeInBits ( ) * MaskLen ; if ( ( Subtarget . useHVXSglOps ( ) && SizeInBits == <NUM_LIT> * <NUM_LIT> ) || ( Subtarget . useHVXDblOps ( ) && SizeInBits == <NUM_LIT> * <NUM_LIT> ) ) { StridedLoadKind Pattern = isStridedLoad ( Mask ) ; if ( Pattern == StridedLoadKind :: NoPattern ) return SDValue ( ) ; unsigned Opc = Pattern == StridedLoadKind :: Even ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , VT , { Op . getOperand (

<NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , const MachineFunction


<s> if ( ElemTy == <STR_LIT> ) { if ( AllConst ) { int32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } bool IsSplat = true ; for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } assert ( Elem . size ( ) == <NUM_LIT> ) ; SDValue Vs [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Vs [ i ] = DAG . getZExtOrTrunc ( Elem [ i ] , dl , <STR_LIT> ) ; Vs [ i ] = DAG . getZeroExtendInReg ( Vs [ i ] , dl


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT>


<s> unsigned LR = HRI . getRARegister ( ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || HMFI . hasClobberLR ( ) ) return Op ; unsigned NumOps = Op . getNumOperands ( ) ; if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Mem : i += NumVals


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; unsigned LR = HRI . getRARegister ( ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || HMFI . hasClobberLR ( ) ) return Op ; unsigned NumOps = Op . getNumOperands ( ) ; if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm ::


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR (


<s> return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVXDblOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT>


<s> return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVXDblOps ( ) )


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; int EltSize = EltVT . getSizeInBits ( ) ; SDValue Width = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? EltSize : VTN * EltSize , dl , <STR_LIT> ) ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Idx ) ) { uint64_t X = CI -> getZExtValue ( ) ; SDValue Offset = DAG . getConstant ( X * EltSize , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { Vec , Width , Offset } ; ConstantSDNode * CW = dyn_cast < ConstantSDNode > ( Width ) ; assert ( CW && <STR_LIT> ) ; SDValue N ; MVT SVT = VecVT . getSimpleVT ( ) ; uint64_t W = CW -> getZExtValue ( ) ; if ( W == <NUM_LIT> ) { MVT LocVT = <STR_LIT> ( SVT . getSizeInBits ( ) ) ; SDValue VecCast = DAG . getNode ( <STR_LIT> , dl , LocVT , Vec ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , LocVT , VecCast , Offset ) ; return DAG . getNode ( <STR_LIT> , dl , LocVT , Shifted , DAG . getConstant ( <NUM_LIT> , dl , LocVT ) ) ; } else if ( W == <NUM_LIT> ) { unsigned Subreg = ( X == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; if ( X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else llvm_unreachable (


<s> EVT EltVT = VecVT . getVectorElementType ( ) ; int EltSize = EltVT . getSizeInBits ( ) ; SDValue Width = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? EltSize : VTN * EltSize , dl , <STR_LIT> ) ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Idx ) ) { uint64_t X = CI -> getZExtValue ( ) ; SDValue Offset = DAG . getConstant ( X * EltSize , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { Vec , Width , Offset } ; ConstantSDNode * CW = dyn_cast < ConstantSDNode > ( Width ) ; assert ( CW && <STR_LIT> ) ; SDValue N ; MVT SVT = VecVT . getSimpleVT ( ) ; uint64_t W = CW -> getZExtValue ( ) ; if ( W == <NUM_LIT> ) { MVT LocVT = <STR_LIT> ( SVT . getSizeInBits ( ) ) ; SDValue VecCast = DAG . getNode ( <STR_LIT> , dl , LocVT , Vec ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , LocVT , VecCast , Offset ) ; return DAG . getNode ( <STR_LIT> , dl , LocVT , Shifted , DAG . getConstant ( <NUM_LIT> , dl , LocVT ) ) ; } else if ( W == <NUM_LIT> ) { unsigned Subreg = ( X == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; if ( X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else if ( SVT == <STR_LIT> && X == <NUM_LIT> ) Subreg = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; N = DAG . getTargetExtractSubreg ( Subreg , dl , <STR_LIT> , Vec ) ; } else if ( SVT . getSizeInBits ( ) == <NUM_LIT> ) { N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( SVT . getSizeInBits ( ) == <NUM_LIT> ) { N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , N ) ; } else return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N ) ; } SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , DAG . getConstant ( EltSize , dl , <STR_LIT> ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted ,


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; CallingConv :: ID CallConv = CLI . CallConv ; bool IsVarArg = CLI . IsVarArg ; bool DoesNotReturn = CLI . DoesNotReturn ; bool IsStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; unsigned NumParams = CLI . CS . getInstruction ( ) ? CLI . CS . getFunctionType ( ) -> getNumParams ( ) : <NUM_LIT> ; if ( GlobalAddressSDNode * GAN = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( GAN -> getGlobal ( ) , dl , <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) , NumParams ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; auto Attr = MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) ; if ( Attr . getValueAsString ( ) == <STR_LIT> ) CLI . IsTailCall = false ; if ( CLI . IsTailCall ) { bool StructAttrFlag = MF . getFunction ( ) . hasStructRetAttr ( ) ; CLI . IsTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , IsVarArg , IsStructRet , StructAttrFlag , Outs , OutVals , Ins , DAG ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isMemLoc ( ) ) { CLI . IsTailCall = false ; break ; } } LLVM_DEBUG ( dbgs ( ) << ( CLI . IsTailCall ? <STR_LIT> : <STR_LIT> <STR_LIT> ) ) ; } unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , HRI . getStackRegister ( ) , PtrVT ) ; bool NeedsArgAlign = false ; unsigned LargestAlignSeen


<s> else return EVT :: getVectorVT ( C , <STR_LIT> , VT . getVectorNumElements ( )


<s> } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } llvm_unreachable (


<s> case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN (


<s> bool IsLegalType = VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || Subtarget . isHVXVectorType ( VT . getSimpleVT ( ) ) ; if ( ! IsLegalType ) return false ; if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = Op -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Offset . getNode ( ) ) ) return false ; AM = <STR_LIT> ; int32_t V = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; return Subtarget . getInstrInfo ( ) -> isValidAutoIncImm


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> if ( CP -> isMachineConstantPoolEntry ( ) ) Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , ValTy , CP -> getAlignment ( ) ) ; else Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) ,


<s> <STR_LIT> Flags = Ins [ i ] . Flags ; unsigned ObjSize ; unsigned StackLocation ; int FI ; if ( ( VA . isRegLoc ( ) && ! Flags . isByVal ( ) ) || ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) > <NUM_LIT> ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert (


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ]


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDNode * OpNode = Op . getNode ( ) ; EVT SVT = OpNode -> getValueType ( <NUM_LIT> ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS


<s> SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDNode * OpNode = Op . getNode ( ) ; EVT SVT = OpNode -> getValueType (


<s> assert ( VecTy . getVectorNumElements ( ) == Elem . size ( ) ) ; SmallVector < ConstantInt * , <NUM_LIT> > Consts ( Elem . size ( ) ) ; bool AllConst = getBuildVectorConstInts ( Elem , VecTy , DAG , Consts ) ; unsigned First , Num = Elem . size ( ) ; for ( First = <NUM_LIT> ; First != Num ; ++ First ) { if ( ! isUndef ( Elem [ First ] ) ) break ; } if ( First == Num ) return DAG . getUNDEF ( VecTy ) ; if ( AllConst && llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) { assert ( Elem . size ( ) == <NUM_LIT> ) ; if ( AllConst ) { uint32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( VecTy , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } SDValue E0 , E1 ; if ( ElemTy == <STR_LIT> ) { E0 = DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Elem [ <NUM_LIT> ] ) , dl , <STR_LIT> ) ; E1 = DAG . getZExtOrTrunc ( DAG . getBitcast ( <STR_LIT> , Elem [ <NUM_LIT> ] ) , dl , <STR_LIT> ) ; } else { E0 = Elem [ <NUM_LIT> ] ; E1 = Elem [ <NUM_LIT> ] ; } SDValue N = getInstr ( <STR_LIT> , dl , <STR_LIT> , { E1 , E0 } , DAG ) ; return DAG . getBitcast ( VecTy , N ) ; } if ( ElemTy == <STR_LIT> ) { if ( AllConst ) { int32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } bool IsSplat = true ; for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } assert ( Elem . size ( ) == <NUM_LIT> ) ; SDValue Vs [ <NUM_LIT>


<s> bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue NL = DAG . getLoad ( LN -> getAddressingMode ( ) , LN -> getExtensionType ( ) , <STR_LIT> , dl , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getOffset ( ) , LN -> getPointerInfo ( ) , <STR_LIT> , LN -> getAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) , LN -> getAAInfo ( ) , LN -> getRanges ( ) ) ; LN = cast < LoadSDNode > ( NL . getNode ( ) ) ; } unsigned ClaimAlign = LN -> getAlignment ( ) ; validateConstPtrAlignment ( LN -> getBasePtr ( ) , dl , ClaimAlign ) ; SDValue LU = LowerUnalignedLoad ( SDValue ( LN , <NUM_LIT> ) , DAG ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , Ty , LU ) ; SDValue Ch = cast < LoadSDNode > ( LU . getNode ( ) ) -> getChain ( ) ; return DAG . getMergeValues ( { TC


<s> MVT Ty = ty ( Val ) ; bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; SDValue NS = DAG . getStore ( SN -> getChain ( ) , dl , TC , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ; if ( SN -> isIndexed ( ) ) { NS = DAG . getIndexedStore ( NS , dl , SN -> getBasePtr ( ) , SN -> getOffset ( ) , SN -> getAddressingMode ( ) ) ; } SN = cast < StoreSDNode > ( NS . getNode ( ) ) ; } unsigned ClaimAlign = SN -> getAlignment ( ) ; SDValue Ptr = SN -> getBasePtr ( ) ; validateConstPtrAlignment ( Ptr , dl , ClaimAlign ) ; MVT StoreTy = SN -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned NeedAlign = Subtarget .


<s> const SDLoc & dl ( Op ) ; StoreSDNode * SN = cast < StoreSDNode > ( Op . getNode ( ) ) ; SDValue Val = SN -> getValue ( ) ; MVT Ty = ty ( Val ) ; bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; SDValue NS = DAG . getStore ( SN -> getChain ( ) , dl , TC , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ; if ( SN -> isIndexed ( ) ) { NS = DAG . getIndexedStore ( NS , dl , SN -> getBasePtr ( ) , SN -> getOffset ( ) , SN -> getAddressingMode ( ) ) ; } SN = cast < StoreSDNode > ( NS . getNode ( ) ) ; } unsigned ClaimAlign = SN -> getAlignment ( ) ; SDValue Ptr = SN -> getBasePtr ( ) ; validateConstPtrAlignment ( Ptr , dl ,


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ?

AtomicExpansionKind :: Expand : AtomicExpansionKind :: None ;


<s> } } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) , NumNamedVarArgParams ) ; if ( NumNamedVarArgParams > <NUM_LIT> ) CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>_VarArg ) ; else CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; if ( isTailCall ) { bool StructAttrFlag = DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ; isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , IsStructRet , StructAttrFlag , Outs , OutVals , Ins , DAG ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isMemLoc ( ) ) { isTailCall = false ; break ; } } if ( isTailCall ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; const <ISA_LIT>RegisterInfo * QRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , QRI -> getStackRegister ( ) , getPointerTy ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getConstant ( LocMemOffset , StackPtr . getValueType ( ) ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) { MemOpChains . push_back ( CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , TM . getRegisterInfo ( ) -> getStackRegister ( ) , Sub ) ; SDValue Ops [ <NUM_LIT> ] = { ArgAdjust


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals


<s> bool hasLoadLinkedStoreConditional ( ) const override { return


<s> unsigned VecLen = VT . getVectorMinNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == <NUM_LIT> || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ <NUM_LIT> ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == <STR_LIT> ) return TargetLoweringBase :: TypeWidenVector ; if ( ! isPowerOf2_32 ( VecLen ) )


<s> SDValue Chain = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; SDValue InFlag ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; unsigned Flags = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) .

useLongCalls ( ) ? <STR_LIT> | <STR_LIT> : <STR_LIT> ;


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc & dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , false , false , false

, MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( UseHVX && UseHVXDbl && ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( UseHVX && UseHVXDbl && ( ( RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> || RegVT == <STR_LIT> ) ) ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT>


<s> unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; } StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; FI = MFI -> CreateFixedObject ( ObjSize , StackLocation , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) ) ) ; } } } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOps ) ; if ( isVarArg ) { int FrameIndex = MFI -> CreateFixedObject ( <ISA_LIT>_PointerSize , HEXAGON_LRFP_SIZE + CCInfo


<s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG

. getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl (


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const uint16_t RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false


<s> SDValue T ; if ( CPN -> isMachineConstantPoolEntry ( ) ) T = DAG . getTargetConstantPool ( CPN -> getMachineCPVal ( ) , ValTy , Align , Offset , TF ) ; else if ( isVTi1Type ) T = DAG . getTargetConstantPool ( CVal , ValTy , Align , Offset , TF ) ; else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ; if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy ,


<s> MVT tyVector ( MVT Ty , MVT ElemTy ) const { if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) == ElemTy ) return Ty ; unsigned TyWidth = Ty . getSizeInBits ( ) , ElemWidth


<s> static bool CC_<ISA_LIT> ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { if ( ArgFlags . isByVal ( ) ) { assert ( ( ArgFlags . getByValSize ( ) > <NUM_LIT> ) && <STR_LIT> ) ; unsigned Offset = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT =


<s> case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } default : llvm_unreachable ( <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTPOP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue InpVal = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( InpVal


<s> const SDValue Ops [ ] = { Vec , Width , Offset } ; ConstantSDNode * W = dyn_cast < ConstantSDNode > ( Width ) ; assert ( W && <STR_LIT> ) ; SDValue N ; if ( VecVT . getSimpleVT ( ) == <STR_LIT> ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Vec ) ; else if ( C -> getZExtValue ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Vec ) ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( ( VecVT . getSimpleVT ( ) == <STR_LIT> ) && ( W -> getZExtValue ( ) == <NUM_LIT> ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Vec ) ; else if ( C -> getZExtValue ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Vec ) ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( ( VecVT . getSimpleVT ( ) == <STR_LIT> ) && ( W -> getZExtValue ( ) == <NUM_LIT> ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Vec ) ; else if ( C -> getZExtValue ( ) == <NUM_LIT> ) N = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Vec ) ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( VecVT . getSizeInBits ( ) == <NUM_LIT> ) { N = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; }


<s> Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; Tmp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ <NUM_LIT> ] , ShiftAmount ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Tmp1 , Loads [ <NUM_LIT> ] ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Tmp4 , Tmp2 ) ; LoadChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , Loads [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) ) ; } else { Result = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , LoadNode -> getPointerInfo ( ) , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , LoadNode -> getAlignment ( ) ) ; LoadChain = Result . getValue ( <NUM_LIT> ) ; } } else llvm_unreachable ( <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , Result ) ; SDValue Ops [ ] = { Result , LoadChain } ; return DAG . getMergeValues ( Ops


<s> if ( Alignment == <NUM_LIT> ) { SDValue Loads [ <NUM_LIT> ] ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Base , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Base . getValueType ( ) , Base , Increment ) ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; SDValue ShiftAmount = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ <NUM_LIT> ] , ShiftAmount ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Tmp1 , Loads [ <NUM_LIT> ] ) ; Increment = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Base . getValueType


<s> case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op


<s> if ( i == First ) continue ; if ( Elem [ i ] == Elem [ First ] || Elem [ i ] . getOpcode ( ) == <STR_LIT> ) continue ; IsSplat = false ; break ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VecTy , Elem [ First ] ) ; } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts [ i ] -> getZExtValue ( ) & Mask ) ; SDValue V0 = DAG . getConstant ( Val , dl , <STR_LIT> ) ; return DAG . getBitcast ( VecTy , V0 ) ; } MVT HalfTy = <STR_LIT> ( ElemTy , Num / <NUM_LIT> ) ; SDValue L = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( { Elem . data ( ) , Num / <NUM_LIT> } , dl , HalfTy , DAG ) ; SDValue H = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( { Elem . data ( ) + Num / <NUM_LIT> , Num / <NUM_LIT> } , dl , HalfTy , DAG ) ; unsigned Id = <STR_LIT> ; SDNode * N = DAG . getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VecTy , { DAG . getTargetConstant ( Id , dl , <STR_LIT> ) , L , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , H

, DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ) ;


<s> State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( HST . useHVX64BOps ( ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstD ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( HST . useHVX128BOps ( ) && ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) ) { if ( unsigned Reg = State . AllocateReg ( VecLstD ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset ,


<s> case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVX128BOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = &


<s> case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVX128BOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( BW == <NUM_LIT> ) return buildVector32 ( Ops , SDLoc ( Op ) , VT , DAG ) ; return buildVector64 ( Ops , SDLoc ( Op )


<s> MVT ST = VecVT . getSimpleVT ( ) ; if ( ST == <STR_LIT> || ST == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Vec0 ) ; if ( UseHVX ) { assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVX64BOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVX128BOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVX64BOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVX64BOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V =


<s> EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; bool UseHVX64B = Subtarget . useHVX64BOps ( ) ; if ( ! VT . isVector ( ) || ! UseHVX ) return SDValue ( ) ; EVT ResVT = Op . getValueType ( ) ; unsigned ResSize = ResVT . getSizeInBits ( ) ; unsigned VectorSizeInBits = UseHVX64B ? ( <NUM_LIT> * <NUM_LIT> ) : ( <NUM_LIT> * <NUM_LIT> ) ; unsigned OpSize = VT . getSizeInBits ( ) ; if ( ! ( ResVT . isByteSized ( ) && ResSize == VectorSizeInBits ) || ! ( VT . isByteSized ( ) && OpSize == <NUM_LIT> * VectorSizeInBits ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst ) return SDValue ( ) ; unsigned Val = Cst -> getZExtValue ( ) ; if ( Val == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , ResVT


<s> LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || ( LocVT == <STR_LIT> && HST . useHVX128BOps ( ) ) ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>Vector ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } return true


<s> static bool CC_<ISA_LIT>32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { static const unsigned RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false


<s> static bool CC_<ISA_LIT>32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { static const unsigned RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT


<s> MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( MI ) ; return BB ; } default : assert ( false &&


<s> case 'r' : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT>


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : switch ( VT . getSimpleVT (


<s> SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; const <ISA_LIT>RegisterInfo * QRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , QRI -> getStackRegister ( ) , Sub ) ; SDValue Ops [ <NUM_LIT> ] = { ArgAdjust , CopyChain } ; return DAG . getMergeValues ( Ops , dl


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( ) ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain ,


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) || HTM . Options . DisableTailCalls ) return false ; return


<s> SDValue <ISA_LIT>TargetLowering :: GetDynamicTLSAddr ( SelectionDAG & DAG , SDValue Chain , GlobalAddressSDNode * GA , SDValue * InFlag , EVT PtrVT , unsigned ReturnReg , unsigned char OperandFlags ) const { MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , DAG . getRegister ( <STR_LIT> , PtrVT ) , * InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ; } else { SDValue Ops [ ] = { Chain , TGA , DAG . getRegister ( <STR_LIT> , PtrVT ) } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ; } MFI . setAdjustsStack ( true


<s> if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) return false ; if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true


<s> if ( ST == <STR_LIT> || ST == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Vec0 ) ; if ( UseHVX ) { assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXSglOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXDblOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V = C0 ; for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { unsigned N = NElts - i - <NUM_LIT> ; SDValue OpN = Op . getOperand ( N ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && OpN . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; OpN = DAG . getNode ( <STR_LIT> , dl , VT , C , OpN ) ; } SDValue Idx = DAG . getConstant ( N , dl , <STR_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , W ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , S , Offset ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { V , OpN , Or } ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) V = DAG . getNode (


<s> SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; bool UseHVXSgl = Subtarget . useHVXSglOps ( ) ; if ( ! VT . isVector ( ) || ! UseHVX ) return SDValue ( ) ; EVT ResVT = Op . getValueType ( ) ; unsigned ResSize = ResVT . getSizeInBits ( ) ; unsigned VectorSizeInBits = UseHVXSgl ? ( <NUM_LIT> * <NUM_LIT> ) : ( <NUM_LIT> * <NUM_LIT> ) ; unsigned OpSize = VT . getSizeInBits ( ) ; if ( ! ( ResVT . isByteSized ( ) && ResSize == VectorSizeInBits ) || ! ( VT . isByteSized ( ) && OpSize == <NUM_LIT> * VectorSizeInBits ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst )


<s> return DAG . getNode ( <STR_LIT> , dl , VT , N ) ; } SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , DAG . getConstant ( EltSize , dl , <STR_LIT> ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted , Offset ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Val . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , VT , C , Val ) ; } const SDValue Ops [ ] = { Vec


<s> SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , DAG . getConstant ( EltSize , dl , <STR_LIT> ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Width , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Combined = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Shifted , Offset ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Val . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , VT , C , Val ) ; } const SDValue Ops [ ] = { Vec , Val , Combined } ; SDValue N ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) N = DAG .

getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVECTOR_SHIFT ( SDValue Op , SelectionDAG & DAG ) const { BuildVectorSDNode * BVN = <NUM_LIT> ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDValue V3 ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V1 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V2 ; else if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V2 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V1 ; else return SDValue ( ) ; SDValue CommonSplat = BVN -> getOperand ( <NUM_LIT> ) ; SDValue Result ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; default : return SDValue ( ) ; } } else if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl