<s> static DecodeStatus DecodeRegisterClass ( MCInst & Inst , unsigned RegNo , const uint16_t


VecRegDecoderTable , sizeof ( VecRegDecoderTable ) ) ) ;


<s> Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return


<s> Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = <ISA_LIT>_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; remapInstruction ( MI


<s> MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; const auto ArchSTI = <ISA_LIT>_MC :: getArchSubtarget ( & STI ) ; const auto STI_ = ( ArchSTI != nullptr ) ? * ArchSTI : STI ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI_ , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; remapInstruction (


<s> MCContext & contextFromDecoder ( void const * Decoder


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { DecodeStatus Result = DecodeStatus :: Success ; bool Complete = false ; Size = <NUM_LIT> ; * CurrentBundle = & MI ; MI = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; <ISA_LIT>MCChecker Checker ( * MCII , STI , MI , MI , * getContext ( ) . getRegisterInfo ( ) ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; return MCDisassembler ::


<s> static DecodeStatus s12ImmDecoder ( MCInst & MI , unsigned tmp


<s> static DecodeStatus s16ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler ::


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler ::


<s> static const uint16_t CtrlReg64DecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlReg64DecoderTable ) / sizeof ( CtrlReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlReg64DecoderTable [ RegNo ] == <STR_LIT>


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return


<s> static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t CtrlRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RegNo >= sizeof ( CtrlRegDecoderTable ) / sizeof ( CtrlRegDecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( CtrlRegDecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo


<s> while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address ,


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { Size = <NUM_LIT> ; if ( Bytes . size ( ) <

<NUM_LIT> ) return MCDisassembler :: Fail ;


<s> static DecodeStatus s10ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm (


<s> static DecodeStatus s10ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT>


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler


<s> static DecodeStatus s11_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t ,


<s> static DecodeStatus s11_1ImmDecoder ( MCInst & MI , unsigned tmp ,


<s> static DecodeStatus s11_2ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t ,


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler ::


<s> static DecodeStatus s11_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm )


<s> static DecodeStatus s16ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> >


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm )


<s> static DecodeStatus s6_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm


<s> static DecodeStatus s8ImmDecoder ( MCInst & MI , unsigned tmp


<s> static DecodeStatus s8ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler ::


<s> MI . clear ( ) ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os


<s> while ( Result == Success && Complete == false ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE


<s> uint32_t insn = llvm :: <STR_LIT> :: read < uint32_t , llvm :: <STR_LIT> , llvm :: <STR_LIT> > ( Bytes . data ( ) ) ; insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ; return decodeInstruction ( DecoderTable32 , MI , insn , Address


<s> Size = <NUM_LIT> ; if ( Region . readBytes ( Address , Bytes . size ( ) , Bytes . data ( ) ) == - <NUM_LIT> ) { return MCDisassembler :: Fail ; } uint32_t insn = llvm :: <STR_LIT> :: read < uint32_t , llvm :: <STR_LIT> , llvm :: <STR_LIT> > ( Bytes . data ( ) ) ; insn &= ~ static_cast < uint32_t > ( <STR_LIT>


<s> using namespace <ISA_LIT> ; static const MCPhysReg CtrlReg64DecoderTable [ ] = { C1_0 , <NUM_LIT> , C3_2 , <NUM_LIT> , C5_4 , <NUM_LIT> , C7_6 , <NUM_LIT> , C9_8 , <NUM_LIT> , C11_10 , <NUM_LIT> , CS , <NUM_LIT> , UPC , <NUM_LIT> , C17_16 , <NUM_LIT> , PKTCOUNT , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMER , <NUM_LIT> } ; if ( RegNo >= array_lengthof ( CtrlReg64DecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlReg64DecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler


<s> SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , C6 , C7 , USR , PC , UGP , GP , CS0 , CS1 , UPCL , UPCH , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo


<s> using namespace <ISA_LIT> ; static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , C6 , C7 , USR , PC , UGP , GP , CS0 , CS1 , UPCL , UPCH , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register )


<s> static DecodeStatus s3_6ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler


<s> static DecodeStatus s4_6ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand ::


<s> RegNo = RegNo >> <NUM_LIT> ; if ( RegNo >= sizeof ( SysReg64DecoderTable ) / sizeof ( SysReg64DecoderTable [ <NUM_LIT> ] ) ) return MCDisassembler :: Fail ; if ( SysReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SysReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg


<s> RegNo = RegNo >> <NUM_LIT> ; if ( RegNo >= sizeof ( SysReg64DecoderTable ) / sizeof ( SysReg64DecoderTable [ <NUM_LIT> ] ) )


<s> uint32_t Extended = FullValue + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant (

MI , Extended , Disassembler . getContext ( ) ) ;


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; unsigned Bits = <ISA_LIT>MCInstrInfo :: getExtentBits ( * Disassembler . MCII , MI ) ; if ( Bits == <NUM_LIT> ) Bits = <NUM_LIT> ; uint64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 ( tmp ,


<s> if ( RegNo >= array_lengthof ( CtrlReg64DecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlReg64DecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register


<s> static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] ==

NoRegister ) return MCDisassembler :: Fail ;


<s> using namespace <ISA_LIT> ; static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT>


RegNo , GeneralDoubleLow8RegDecoderTable ) ;


<s> static const MCPhysReg GeneralSubRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; return DecodeRegisterClass ( Inst ,


<s> static DecodeStatus DecodeGuestRegs64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { using namespace <ISA_LIT> ; static const MCPhysReg GuestReg64DecoderTable [ ] = { G1_0 , <NUM_LIT> , G3_2 , <NUM_LIT> , G5_4 , <NUM_LIT> , G7_6 , <NUM_LIT> , G9_8 , <NUM_LIT> , G11_10 , <NUM_LIT> , G13_12 , <NUM_LIT> , G15_14 , <NUM_LIT> , G17_16 , <NUM_LIT> , G19_18 , <NUM_LIT> , G21_20 , <NUM_LIT> , G23_22 , <NUM_LIT> , G25_24 , <NUM_LIT> , G27_26 , <NUM_LIT> , G29_28 , <NUM_LIT> , G31_30 , <NUM_LIT> } ; if ( RegNo >= array_lengthof ( GuestReg64DecoderTable ) ) return MCDisassembler :: Fail ; if ( GuestReg64DecoderTable [ RegNo ] == <STR_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GuestReg64DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg (


<s> static DecodeStatus DecodeHvxQRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst ,


<s> static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return DecodeRegisterClass ( Inst , RegNo ,


<s> static const MCPhysReg HvxVQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ,


<s> switch ( RegNo ) { case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createReg (


<s> unsigned Register = <NUM_LIT> ; switch ( RegNo ) { case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default : return MCDisassembler


<s> static <ISA_LIT>Disassembler const & disassembler ( void const * Decoder ) { return * static_cast < <ISA_LIT>Disassembler const * >


<s> return * static_cast < <ISA_LIT>Disassembler const *


<s> uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Disassembler . CurrentExtender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success ) ; ( void )


<s> if ( ! Disassembler . CurrentExtender || MI . size ( ) != <ISA_LIT>MCInstrInfo :: getExtendableOp ( MCII , MI ) ) return Value ; unsigned Alignment = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MI ) ; uint32_t Lower6 = static_cast < uint32_t > ( Value >> Alignment ) & <NUM_LIT> ; int64_t Bits ; bool Success = Disassembler . CurrentExtender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success


<s> * CurrentBundle = & MI ; MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; while ( Result == Success && ! Complete ) { if ( Bytes . size ( ) < HEXAGON_INSTR_SIZE ) return MCDisassembler :: Fail ; MCInst * Inst = new ( getContext ( ) ) MCInst ; Result = getSingleInstruction ( * Inst , MI , Bytes , Address , os , cs , Complete ) ; MI . addOperand ( MCOperand :: createInst ( Inst ) ) ; Size += HEXAGON_INSTR_SIZE ; Bytes = Bytes . slice ( HEXAGON_INSTR_SIZE ) ; } if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return


<s> } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_t ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_f ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_tnew_pt ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . setOpcode ( L4_return_map_to_raw_fnew_pt ) ; MI . erase ( MI . begin ( ) + <NUM_LIT> ) ; MI . erase ( MI . begin ( ) ) ; } break ; case <STR_LIT>


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 < T > ( tmp ) ) ; int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext


<s> static void signedDecoder ( MCInst & MI , unsigned tmp , const void * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( Disassembler , MI , SignExtend64


<s> <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; int64_t FullValue = fullValue ( Disassembler , MI , tmp ) ; assert ( FullValue >= <NUM_LIT> && <STR_LIT> ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , FullValue , Disassembler . getContext ( ) ) ; return MCDisassembler ::


<s> assert ( ! SSB ) ; SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; } if ( SSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( SSB ) ; FP . SplitB -> addSuccessor ( SSB ) ; } } if ( FP . JoinB ) { updatePhiNodes ( FP .


<s> return new <ISA_LIT>EarlyIfConversion


<s> DebugLoc DL = PN -> getDebugLoc ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; NewR = MRI -> createVirtualRegister ( RC ) ; NonPHI = BuildMI ( * B , NonPHI , DL , TII -> get ( TargetOpcode :: COPY ) , NewR ) . addReg ( UseR , <NUM_LIT> , UseSR ) ; } MRI -> replaceRegWith ( DefR , NewR ) ; B -> erase ( I


<s> void <ISA_LIT>EarlyIfConversion :: eliminatePhis ( MachineBasicBlock * B ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( B ) << <STR_LIT> ) ; MachineBasicBlock :: iterator I , NextI , NonPHI = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != NonPHI ; I = NextI ) { NextI = std :: next ( I ) ; MachineInstr * PN = & *


<s> AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU


<s> case S2_storerhabs : case S2_storerhgp : return IfTrue ? S4_pstorerht_abs : S4_pstorerhf_abs ; case S2_storerf_io : return IfTrue ? S2_pstorerft_io : S2_pstorerff_io ; case S4_storerf_rr : return IfTrue ? S4_pstorerft_rr : S4_pstorerff_rr ; case S2_storerfabs : case S2_storerfgp : return IfTrue ? S4_pstorerft_abs : S4_pstorerff_abs ; case S4_storeirh_io : return IfTrue ? S4_storeirht_io : S4_storeirhf_io ; case S2_storeri_io : return IfTrue ? S2_pstorerit_io : S2_pstorerif_io ; case S4_storeri_rr : return IfTrue ? S4_pstorerit_rr : S4_pstorerif_rr ; case S2_storeriabs : case S2_storerigp : return IfTrue ? S4_pstorerit_abs


<s> for ( auto & I : * B ) if ( I . isEHLabel (


<s> <ISA_LIT>EarlyIfConversion ( ) : MachineFunctionPass ( ID ) , TII ( <NUM_LIT> ) , TRI ( <NUM_LIT> ) , MFN ( <NUM_LIT>

) , MRI ( <NUM_LIT> ) , MDT ( <NUM_LIT> ) , MLI ( <NUM_LIT> ) {


<s> case S2_storerhabs : case S4_storeirh_io : case S2_storerhgp : case S2_storerf_io : case S4_storerf_rr : case S2_storerfabs : case S2_storerfgp : case S2_storeri_io : case S4_storeri_rr : case S2_storeriabs : case S4_storeiri_io : case S2_storerigp : case S2_storerd_io : case S4_storerd_rr : case S2_storerdabs : case S2_storerdgp : return true ; } return


<s> bool <ISA_LIT>EarlyIfConversion :: isPreheader ( const MachineBasicBlock * B ) const { if ( B -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ; return L && SB == L ->


<s> if ( B -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ; return L && SB == L -> getHeader


<s> MachineBasicBlock * TSB = * FP . TrueB -> succ_begin ( ) ; MachineBasicBlock * FSB = * FP . FalseB -> succ_begin ( ) ; if ( TSB != FSB ) return false ; if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } unsigned TS = <NUM_LIT> , FS = <NUM_LIT> , Spare = <NUM_LIT> ; if ( FP . TrueB ) { TS = std :: distance ( FP . TrueB -> begin ( ) , FP . TrueB -> getFirstTerminator ( ) ) ; if ( TS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } if ( FP . FalseB ) { FS = std :: distance ( FP . FalseB -> begin ( ) , FP . FalseB -> getFirstTerminator ( ) ) ; if ( FS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } unsigned TotalIn = TS + FS ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB ) ; PredDefs += countPredicateDefs ( FP . JoinB


<s> } MachineBasicBlock * TSB = * FP . TrueB -> succ_begin ( ) ; MachineBasicBlock * FSB = * FP . FalseB -> succ_begin ( ) ; if ( TSB != FSB ) return false ; if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } unsigned TS = <NUM_LIT> , FS = <NUM_LIT> , Spare = <NUM_LIT> ; if ( FP . TrueB ) { TS = std :: distance ( FP . TrueB -> begin ( ) , FP . TrueB -> getFirstTerminator ( ) ) ; if ( TS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } if ( FP . FalseB ) { FS = std :: distance ( FP . FalseB -> begin ( ) , FP . FalseB -> getFirstTerminator ( ) ) ; if ( FS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } unsigned TotalIn = TS + FS ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB


<s> if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) return false ; if ( MI -> isCall ( ) || MI -> isBarrier ( ) || MI


<s> const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; unsigned DefR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; if ( RC == & <STR_LIT> ) return false ; } } return true


<s> if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( ConstMIOperands MO ( & MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) !=


<s> if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( ConstMIOperands MO ( & MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) != & <STR_LIT> ) continue ; for ( auto U = MRI -> use_begin ( R ) ; U != MRI -> use_end ( ) ; ++ U ) if ( U -> getParent ( ) -> isPHI ( ) ) return false ; } } return


<s> PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ; MachineBasicBlock :: succ_iterator I , E = SuccB -> succ_end ( ) ; for ( I = SuccB -> succ_begin ( ) ; I != E ; ++ I ) PredB -> addSuccessor ( * I ) ; PredB -> normalizeSuccProbs ( ) ; replacePhiEdges ( SuccB , PredB ) ; removeBlock (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( FromB ) << <STR_LIT> ) ; MachineBasicBlock :: iterator End = FromB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator I , NextI ; for ( I = FromB -> begin ( ) ; I != End ; I = NextI ) { assert ( ! I -> isPHI ( ) ) ; NextI = std :: next ( I ) ; if ( isSafeToSpeculate ( & * I ) ) ToB -> splice ( At , FromB


<s> } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode (


<s> if ( IDN ) { MachineBasicBlock * IDB = IDN -> getBlock ( ) ; typedef GraphTraits < MachineDomTreeNode * > GTN ; typedef SmallVector < MachineDomTreeNode * , <NUM_LIT> > DTNodeVectType ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I )


<s> for ( auto I = OldB -> succ_begin ( ) , E = OldB -> succ_end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = * I ; MachineBasicBlock :: iterator P , N =


<s> MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop (


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed =


<s> bool <ISA_LIT>EarlyIfConversion :: usesUndefVReg ( const MachineInstr * MI ) const { for ( ConstMIOperands MO ( MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isUse ( ) ) continue ; unsigned R = MO ->


<s> if ( ! MO -> isReg ( ) || ! MO -> isUse ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ; assert ( DefI && <STR_LIT> ) ; if ( DefI -> isImplicitDef


<s> typedef SmallVector < MachineDomTreeNode * , <NUM_LIT> > DTNodeVectType ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L ,


<s> DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ; if ( ! isValid ( FP )


<s> for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; } MachineBasicBlock * EntryB = GraphTraits < MachineFunction * > :: getEntryNode ( MFN ) ; Changed |= visitBlock ( L ?


<s> bool <ISA_LIT>EarlyIfConversion :: isValidCandidate ( const MachineBasicBlock * B ) const { if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_empty ( ) ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO


<s> bool <ISA_LIT>EarlyIfConversion :: isValidCandidate ( const MachineBasicBlock * B ) const { if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_empty ( ) ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode (


<s> using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( auto & I : Cn ) { MachineBasicBlock * SB = I -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( ! B -> succ_empty ( ) ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( MachineBasicBlock * Pred : B -> predecessors ( ) ) Pred -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ; MFN -> erase ( B -> getIterator ( )


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoop * L : * MLI ) Changed |= visitLoop ( L ) ; Changed |= visitLoop ( nullptr ) ; return Changed


<s> auto & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false


<s> MachineBasicBlock * SB = I -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ; if ( ! isValid ( FP ) ) { LLVM_DEBUG ( dbgs (


<s> llvm_unreachable ( <STR_LIT> ) ; } const MCInstrDesc & D = HII -> get ( Opc ) ; DebugLoc DL = B -> findBranchDebugLoc ( ) ; unsigned MuxR = MRI -> createVirtualRegister ( DRC ) ; BuildMI ( * B , At , DL , D , MuxR ) . addReg ( PredR ) .

addReg ( TR , <NUM_LIT> , TSR ) . addReg ( FR , <NUM_LIT> , FSR ) ;


<s> if ( T != FP . TrueB && T != FP . FalseB ) { assert ( ! SSB ) ; SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; } if (


<s> MachineOperand & UO = PN -> getOperand ( <NUM_LIT> ) ; unsigned UseR = UO . getReg ( ) , UseSR = UO . getSubReg ( ) ; unsigned DefR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewR = UseR ; if ( UseSR ) { const DebugLoc & DL = PN -> getDebugLoc ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; NewR = MRI -> createVirtualRegister ( RC ) ; NonPHI = BuildMI ( * B , NonPHI , DL , HII -> get ( TargetOpcode :: COPY ) , NewR ) . addReg ( UseR , <NUM_LIT> , UseSR ) ; } MRI -> replaceRegWith ( DefR ,


<s> <ISA_LIT>EarlyIfConversion ( ) : MachineFunctionPass ( ID ) , HII ( nullptr ) , TRI ( nullptr ) , MFN

( nullptr ) , MRI ( nullptr ) , MDT ( nullptr ) , MLI ( nullptr ) {


<s> PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << PredDefs


<s> unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << PredDefs << <STR_LIT> ) ; if ( PredDefs > <NUM_LIT> ) return false ; return true


<s> if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R


<s> if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; unsigned PredR = T1I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction :: iterator NextBI = std :: next ( MachineFunction :: iterator ( B ) ) ; MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB = nullptr ; } } else


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ; PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ; MachineBasicBlock :: succ_iterator I , E = SuccB -> succ_end ( ) ; for ( I = SuccB -> succ_begin ( ) ; I != E ; ++ I ) PredB -> addSuccessor ( * I ) ; PredB -> normalizeSuccProbs ( ) ; replacePhiEdges ( SuccB , PredB ) ; removeBlock ( SuccB ) ; if ( ! TermOk ) PredB


<s> if ( HII -> isPostIncrement ( * MI ) ) { MIB . add ( * MOI ) ; ++ MOI ; } MIB . addReg ( PredR ) ; for ( const MachineOperand & MO : make_range ( MOI , MI -> operands_end ( ) ) ) MIB . add ( MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCInstrDesc & D = HII -> get ( IfTrue ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( * ToB , At , DL , D ) . addReg ( PredR ) . addMBB ( TB ) ; MI -> eraseFromParent ( )


<s> MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed =


<s> else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR || FR ) ; unsigned MuxR = <NUM_LIT> , MuxSR = <NUM_LIT> ; if ( TR && FR ) { unsigned DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; MuxR = buildMux ( FP . SplitB , FP . SplitB -> getFirstTerminator ( )

, RC , FP . PredR , TR , TSR , FR , FSR ) ;


<s> bool <ISA_LIT>EarlyIfConversion :: usesUndefVReg ( const MachineInstr * MI ) const { for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ; assert ( DefI && <STR_LIT> )


<s> if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } auto TotalCount = [ ] ( const MachineBasicBlock * B , unsigned & Spare ) { if ( ! B ) return <NUM_LIT> ; unsigned T = std :: count_if ( B -> begin ( ) , B -> getFirstTerminator ( ) , [ ] ( const MachineInstr & MI ) { return ! MI . isMetaInstruction ( ) ; } ) ; if ( T < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - T ; return T ; } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << PredDefs << <STR_LIT> ) ; if ( PredDefs > <NUM_LIT> ) return false ; return


<s> } auto TotalCount = [ ] ( const MachineBasicBlock * B , unsigned & Spare ) { if ( ! B ) return <NUM_LIT> ; unsigned T = std :: count_if ( B -> begin ( ) , B -> getFirstTerminator ( ) , [ ] ( const MachineInstr & MI ) { return ! MI . isMetaInstruction ( ) ; } ) ; if ( T < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - T ; return T ; } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB


<s> if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; switch ( MRI -> getRegClass ( R ) -> getID ( ) ) { case <STR_LIT> : case


<s> if ( IDN ) { MachineBasicBlock * IDB = IDN -> getBlock ( ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ; MFN -> erase ( B -> getIterator ( )


<s> unsigned <ISA_LIT>EarlyIfConversion :: computePhiCost ( MachineBasicBlock * B ) const { assert ( B -> pred_size ( ) <= <NUM_LIT> ) ; if ( B -> pred_size ( ) < <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; MachineBasicBlock :: const_iterator I , E = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != E ; ++ I ) { const MachineOperand & RO1 = I -> getOperand ( <NUM_LIT>


<s> } MIB . addReg ( PredR ) ; for ( const MachineOperand & MO : make_range ( MOI , MI -> operands_end ( ) ) ) MIB . addOperand ( MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCInstrDesc & D = HII -> get ( IfTrue ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( * ToB , At , DL , D ) . addReg


<s> unsigned TR = <NUM_LIT> , TSR = <NUM_LIT> , FR = <NUM_LIT> , FSR = <NUM_LIT> , SR = <NUM_LIT> , SSR = <NUM_LIT> ; for ( int i = PN -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; i -= <NUM_LIT> ) { const MachineOperand & RO = PN -> getOperand ( i ) , & BO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( BO . getMBB ( ) == FP . SplitB ) SR = RO . getReg ( ) , SSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . TrueB ) TR = RO . getReg ( ) , TSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR && FR ) ; using namespace <ISA_LIT> ; unsigned DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; unsigned Opc = <NUM_LIT> ; if ( RC == & IntRegsRegClass


<s> else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR && FR ) ; using namespace <ISA_LIT> ; unsigned DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; unsigned Opc = <NUM_LIT> ; if ( RC == & IntRegsRegClass ) Opc = C2_mux ; else if ( RC == & DoubleRegsRegClass ) Opc = PS_pselect ; else if ( RC == & VectorRegsRegClass ) Opc = PS_vselect ; else if ( RC == & VecDblRegsRegClass ) Opc = PS_wselect ; else if ( RC == & VectorRegs128BRegClass ) Opc = PS_vselect_128B ; else if ( RC == & VecDblRegs128BRegClass ) Opc = PS_wselect_128B ; else llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & D = HII -> get


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) ) continue ; if ( isPredicate ( R ) )


<s> } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB


<s> if ( MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( MI -> getOpcode ( ) == TargetOpcode :: LIFETIME_END


<s> bool <ISA_LIT>EarlyIfConversion :: isSafeToSpeculate ( const MachineInstr * MI ) const { if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) return false ; if ( MI -> isCall ( ) || MI -> isBarrier (

) || MI -> isBranch ( ) ) return false ;


<s> if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && !

isSafeToSpeculate ( & MI ) ) return false ;


<s> MachineBasicBlock * TB = nullptr , * FB = nullptr ; MachineBasicBlock :: const_iterator T1I = B -> getFirstTerminator ( ) ; if ( T1I == B -> end ( ) ) return false ; unsigned Opc = T1I -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; Register PredR = T1I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction :: iterator NextBI = std :: next ( MachineFunction :: iterator ( B ) ) ; MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ; PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( )


<s> MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B , true ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ; MFN -> erase ( B -> getIterator (


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ; assert ( DefI && <STR_LIT> ) ; if ( DefI -> isImplicitDef ( ) ) return true ; } return false


<s> MachineBasicBlock * TB = nullptr , * FB = nullptr ; MachineBasicBlock :: const_iterator T1I = B -> getFirstTerminator ( ) ; if ( T1I == B -> end ( ) ) return false ; unsigned Opc = T1I -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; unsigned PredR = T1I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineFunction :: iterator NextBI = std :: next ( MachineFunction :: iterator ( B ) ) ; MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB =


<s> MachineInstr * PN = & * I ; unsigned TR = <NUM_LIT> , TSR = <NUM_LIT> , FR = <NUM_LIT> , FSR = <NUM_LIT> , SR = <NUM_LIT> , SSR = <NUM_LIT> ; for ( int i = PN -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; i -= <NUM_LIT> ) { const MachineOperand & RO = PN -> getOperand ( i ) , & BO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( BO . getMBB ( ) == FP . SplitB ) SR = RO . getReg ( ) , SSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . TrueB ) TR = RO . getReg ( ) , TSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> removeOperand ( i + <NUM_LIT> ) ; PN -> removeOperand (


<s> if ( Inc . size ( ) < <NUM_LIT> ) continue ; const MachineOperand & RA = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & RB = MI . getOperand ( <NUM_LIT> ) ; assert ( RA . isReg ( ) && RB . isReg ( ) ) ; if ( RA . getSubReg ( ) != <NUM_LIT> || RB . getSubReg ( ) != <NUM_LIT> ) { Cost ++ ; continue ; } const MachineInstr * Def1 = MRI -> getVRegDef ( RA . getReg ( ) ) ; const MachineInstr * Def3 = MRI -> getVRegDef ( RB . getReg ( ) ) ; if ( ! HII -> isPredicable ( * Def1 ) || ! HII -> isPredicable ( * Def3 ) ) Cost ++ ; } return Cost


<s> unsigned PredDefs = <NUM_LIT> ; for ( auto & MI : * B ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO .


<s> void <ISA_LIT>EarlyIfConversion :: eliminatePhis ( MachineBasicBlock * B ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( B ) << <STR_LIT> ) ; MachineBasicBlock :: iterator I , NextI , NonPHI = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != NonPHI ; I = NextI ) { NextI = std :: next ( I ) ; MachineInstr * PN = & * I ; assert ( PN -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & UO = PN -> getOperand ( <NUM_LIT> ) ; Register UseR = UO . getReg ( ) , UseSR = UO . getSubReg ( ) ; Register DefR = PN -> getOperand (


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> bool <ISA_LIT>EarlyIfConversion :: isPreheader ( const MachineBasicBlock * B ) const { if ( B -> succ_size ( ) != <NUM_LIT> ) return false ; MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor


<s> MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ; return L && SB == L -> getHeader ( )


<s> if ( MBPI && FP . TrueB && ! FP . FalseB && ( MBPI -> getEdgeProbability ( FP . SplitB , FP . TrueB ) < JumpProb || MBPI -> getEdgeProbability ( FP . SplitB , FP . TrueB ) > Prob ) ) return false ; if ( MBPI && ! FP . TrueB && FP . FalseB && ( MBPI -> getEdgeProbability ( FP . SplitB , FP . FalseB ) < JumpProb || MBPI -> getEdgeProbability ( FP . SplitB , FP . FalseB ) > Prob ) ) return false ; if ( FP . TrueB && FP . FalseB ) { if ( MBPI ) { if ( MBPI -> getEdgeProbability ( FP . SplitB , FP . TrueB ) > Prob ) return false ; if ( MBPI -> getEdgeProbability ( FP . SplitB , FP . FalseB ) > Prob ) return false ; } MachineBasicBlock * TSB = * FP . TrueB -> succ_begin ( ) ; MachineBasicBlock * FSB = * FP . FalseB -> succ_begin ( ) ; if ( TSB != FSB ) return false ; if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } auto TotalCount = [ ] ( const MachineBasicBlock * B , unsigned & Spare ) { if ( ! B ) return <NUM_LIT> ; unsigned T = std :: count_if ( B -> begin ( ) , B -> getFirstTerminator ( ) , [ ] ( const MachineInstr & MI ) { return ! MI . isMetaInstruction ( ) ; } ) ; if ( T < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - T ; return T ; } ; unsigned Spare = <NUM_LIT> ; unsigned TotalIn = TotalCount ( FP . TrueB , Spare ) + TotalCount ( FP . FalseB , Spare ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && ! FP . TrueB -> succ_empty ( ) ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && ! FP . FalseB -> succ_empty ( ) ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT>


<s> if ( MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( MI -> getOpcode ( ) ==

TargetOpcode :: LIFETIME_END ) return false ;


<s> bool <ISA_LIT>EarlyIfConversion :: isSafeToSpeculate ( const MachineInstr * MI ) const { if ( MI -> mayLoadOrStore ( ) ) return false ; if ( MI -> isCall ( ) || MI -> isBarrier ( ) || MI -> isBranch ( ) ) return false ; if ( MI -> hasUnmodeledSideEffects ( ) ) return false ; if ( MI -> getOpcode ( ) == TargetOpcode :: LIFETIME_END ) return false ; return true


<s> if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; Register DefR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isPredicate ( DefR ) ) return false ; } } return true


<s> bool <ISA_LIT>EarlyIfConversion :: isValid ( const FlowPattern & FP ) const { if ( hasEHLabel ( FP . SplitB ) ) return false ; if ( FP . TrueB && ! isValidCandidate ( FP . TrueB ) ) return false ; if ( FP . FalseB && ! isValidCandidate ( FP . FalseB ) ) return false ; if ( FP . JoinB ) { const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; Register DefR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isPredicate ( DefR


<s> unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual (


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ; PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ; PredB -> transferSuccessorsAndUpdatePHIs ( SuccB )


<s> void <ISA_LIT>EarlyIfConversion :: predicateBlockNB ( MachineBasicBlock * ToB , MachineBasicBlock :: iterator At , MachineBasicBlock * FromB , unsigned PredR , bool IfTrue ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( FromB ) << <STR_LIT> ) ; MachineBasicBlock :: iterator End = FromB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator I , NextI ; for ( I = FromB -> begin ( ) ; I != End ; I = NextI ) { assert ( ! I -> isPHI


<s> if ( HII -> isPostIncrement ( * MI ) ) { MIB . add ( * MOI ) ; ++ MOI ; } MIB . addReg ( PredR ) ; for ( const MachineOperand & MO : make_range ( MOI , MI -> operands_end ( ) ) ) MIB . add ( MO ) ; MIB . cloneMemRefs ( * MI ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> )


<s> TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo >


<s> if ( FP . SplitB -> succ_size ( ) != <NUM_LIT> ) return ; MachineBasicBlock * SB = * FP . SplitB -> succ_begin ( ) ; if ( SB -> pred_size ( ) != <NUM_LIT> ) return ; if ( ! hasEHLabel ( SB ) || hasUncondBranch ( SB ) ) mergeBlocks ( FP . SplitB


<s> const MachineOperand & RO = PN -> getOperand ( i ) , & BO = PN -> getOperand ( i + <NUM_LIT> ) ; if ( BO . getMBB ( ) == FP . SplitB ) SR = RO . getReg ( ) , SSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . TrueB ) TR = RO . getReg ( ) , TSR = RO . getSubReg ( ) ; else if ( BO . getMBB ( ) == FP . FalseB ) FR = RO . getReg ( ) , FSR = RO . getSubReg ( ) ; else continue ; PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } if ( TR == <NUM_LIT> ) TR = SR ,


<s> } if ( TR == <NUM_LIT> ) TR = SR , TSR = SSR ; else if ( FR == <NUM_LIT> ) FR = SR , FSR = SSR ; assert ( TR || FR ) ; unsigned MuxR = <NUM_LIT> , MuxSR = <NUM_LIT> ; if ( TR && FR ) { Register DR = PN -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; MuxR = buildMux ( FP . SplitB , FP . SplitB -> getFirstTerminator ( ) , RC , FP . PredR , TR , TSR , FR , FSR ) ; } else if ( TR ) { MuxR = TR ; MuxSR = TSR ; } else { MuxR = FR ; MuxSR = FSR ; } PN -> addOperand ( MachineOperand :: CreateReg ( MuxR , false , false , false , false , false


<s> Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ; assert ( DefI


<s> bool Changed = false ; MachineDomTreeNode * N = MDT -> getNode ( B ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ; if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ; if ( ! isValid ( FP ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> )


<s> bool <ISA_LIT>EarlyIfConversion :: visitBlock ( MachineBasicBlock * B , MachineLoop * L ) { bool Changed = false ; MachineDomTreeNode * N = MDT -> getNode ( B ) ; using GTN = GraphTraits < MachineDomTreeNode * > ; using DTNodeVectType = SmallVector < MachineDomTreeNode * , <NUM_LIT> > ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B )


<s> LLVM_DEBUG ( ( L ? dbgs ( ) << <STR_LIT> << PrintMB ( HB ) : dbgs ( ) << <STR_LIT> ) << <STR_LIT> ) ; bool Changed = false ; if ( L ) { for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end (

) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ;


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister


<s> for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( ! isPredicate (


<s> if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( ! isPredicate ( R )


<s> unsigned <ISA_LIT>EarlyIfConversion :: computePhiCost ( MachineBasicBlock * B ) const { assert ( B -> pred_size ( ) <= <NUM_LIT> ) ; if ( B -> pred_size ( ) < <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; MachineBasicBlock :: const_iterator I , E = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != E ; ++ I ) { const MachineOperand & RO1 = I -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RO3 = I -> getOperand ( <NUM_LIT> ) ; assert ( RO1 . isReg ( ) && RO3 . isReg ( ) ) ; if ( RO1 . getSubReg ( ) != <NUM_LIT> || RO3 .


<s> MachineInstrBuilder MIB = BuildMI ( * ToB , At , DL , TII -> get ( COpc ) ) . addReg ( PredR ) ; for ( MIOperands MO ( * MI ) ; MO . isValid ( ) ; ++ MO ) MIB . addOperand ( * MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( )


<s> TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed =


<s> TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( B ) << <STR_LIT> ) ; MachineDomTreeNode * N = MDT -> getNode ( B ) ; MachineDomTreeNode * IDN = N -> getIDom ( ) ; if ( IDN ) { MachineBasicBlock * IDB = IDN -> getBlock ( ) ; typedef GraphTraits < MachineDomTreeNode * > GTN ; typedef SmallVector < MachineDomTreeNode * , <NUM_LIT> > DTNodeVectType ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B


<s> } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B ) ; Deleted . insert ( B ) ; MDT -> eraseNode (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( B ) << <STR_LIT> ) ; MachineBasicBlock :: iterator I , NextI , NonPHI = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != NonPHI ; I = NextI ) { NextI = std :: next ( I ) ; MachineInstr * PN = & * I ; assert ( PN -> getNumOperands ( ) ==


<s> MachineBasicBlock :: iterator At = FP . SplitB -> getFirstTerminator ( ) ; predicateBlockNB ( FP . SplitB , At , FP . FalseB , FP . PredR , false ) ; } MachineBasicBlock * SSB = <NUM_LIT> ; FP . SplitB -> erase ( OldTI , FP . SplitB -> end ( ) ) ; while ( FP . SplitB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * T = * FP . SplitB -> succ_begin ( ) ; if ( T != FP . TrueB && T != FP . FalseB ) { assert ( ! SSB ) ; SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; } if ( SSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( SSB ) ; FP . SplitB -> addSuccessor ( SSB ) ; } } if ( FP . JoinB ) { updatePhiNodes ( FP . JoinB , FP ) ; } else { if ( TSB ) updatePhiNodes ( TSB


<s> SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP


<s> if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( ConstMIOperands MO ( MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) ) continue ; unsigned R = MO -> getReg (


<s> for ( ; MO . isValid ( ) ; ++ MO ) MIB . addOperand ( * MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCInstrDesc & D = HII -> get ( IfTrue ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( * ToB , At , DL , D )


<s> ++ MO ; } MIB . addReg ( PredR ) ; for ( ; MO . isValid ( ) ; ++ MO ) MIB . addOperand ( * MO ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MI -> eraseFromParent ( ) ; return ; } if ( Opc == <STR_LIT> ) { MachineBasicBlock * TB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCInstrDesc & D = HII -> get ( IfTrue ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( * ToB , At , DL , D ) . addReg ( PredR ) . addMBB ( TB ) ; MI -> eraseFromParent


<s> bool <ISA_LIT>EarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop (


<s> bool <ISA_LIT>EarlyIfConversion :: usesUndefVReg ( const MachineInstr * MI ) const { for ( ConstMIOperands MO ( * MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isUse ( ) ) continue ; unsigned R = MO -> getReg (


<s> DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ; DEBUG ( dbgs ( ) << <STR_LIT>


<s> if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef (


<s> bool TermOk = hasUncondBranch ( SuccB ) ; eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ; PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ; PredB -> transferSuccessorsAndUpdatePHIs ( SuccB ) ; removeBlock ( SuccB ) ; if ( ! TermOk )


<s> void <ISA_LIT>EarlyIfConversion :: mergeBlocks ( MachineBasicBlock * PredB , MachineBasicBlock * SuccB ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( PredB ) << <STR_LIT> << PrintMB ( SuccB ) << <STR_LIT> ) ; bool TermOk = hasUncondBranch ( SuccB ) ; eliminatePhis ( SuccB ) ; TII -> RemoveBranch ( *


<s> for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( )

; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B ) ;


<s> typedef SmallVector < MachineDomTreeNode * , <NUM_LIT> > DTNodeVectType ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; MDT -> changeImmediateDominator ( SB , IDB ) ; } } while ( B -> succ_size ( ) > <NUM_LIT> ) B -> removeSuccessor ( B -> succ_begin ( ) ) ; for ( auto I = B -> pred_begin ( ) , E = B -> pred_end ( ) ; I != E ; ++ I ) ( * I ) -> removeSuccessor ( B ) ; Deleted . insert ( B ) ; MDT -> eraseNode ( B ) ; MachineFunction :: iterator BI = B ; MFN -> erase (


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI , StringRef CPU ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ,


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ,


<s> case fixup_<ISA_LIT>_LD_GOT_HI16 : return ELF :: R_HEX_LD_GOT_HI16 ; case fixup_<ISA_LIT>_LD_GOT_32 : return ELF :: R_HEX_LD_GOT_32 ; case fixup_<ISA_LIT>_LD_GOT_16 : return ELF :: R_HEX_LD_GOT_16 ; case fixup_<ISA_LIT>_IE_LO16 : return ELF :: R_HEX_IE_LO16 ; case fixup_<ISA_LIT>_IE_HI16 : return ELF :: R_HEX_IE_HI16 ; case fixup_<ISA_LIT>_IE_32 : return ELF :: R_HEX_IE_32 ; case fixup_<ISA_LIT>_IE_GOT_LO16 : return ELF :: R_HEX_IE_GOT_LO16 ; case fixup_<ISA_LIT>_IE_GOT_HI16 : return ELF :: R_HEX_IE_GOT_HI16 ; case fixup_<ISA_LIT>_IE_GOT_32 : return ELF :: R_HEX_IE_GOT_32 ; case fixup_<ISA_LIT>_IE_GOT_16 : return ELF :: R_HEX_IE_GOT_16 ; case fixup_<ISA_LIT>_TPREL_LO16 : return ELF :: R_HEX_TPREL_LO16 ; case fixup_<ISA_LIT>_TPREL_HI16 : return ELF :: R_HEX_TPREL_HI16 ; case fixup_<ISA_LIT>_TPREL_32 : return ELF :: R_HEX_TPREL_32 ; case fixup_<ISA_LIT>_TPREL_16 : return ELF :: R_HEX_TPREL_16 ; case fixup_<ISA_LIT>_6_PCREL_X : return ELF :: R_HEX_6_PCREL_X ; case fixup_<ISA_LIT>_GOTREL_32_6_X : return ELF :: R_HEX_GOTREL_32_6_X ; case fixup_<ISA_LIT>_GOTREL_16_X : return ELF :: R_HEX_GOTREL_16_X ; case fixup_<ISA_LIT>_GOTREL_11_X : return ELF :: R_HEX_GOTREL_11_X ; case fixup_<ISA_LIT>_GOT_32_6_X : return ELF :: R_HEX_GOT_32_6_X ; case fixup_<ISA_LIT>_GOT_16_X : return ELF :: R_HEX_GOT_16_X ; case fixup_<ISA_LIT>_GOT_11_X : return ELF :: R_HEX_GOT_11_X ; case fixup_<ISA_LIT>_DTPREL_32_6_X : return ELF :: R_HEX_DTPREL_32_6_X ; case fixup_<ISA_LIT>_DTPREL_16_X : return ELF :: R_HEX_DTPREL_16_X ; case fixup_<ISA_LIT>_DTPREL_11_X : return ELF :: R_HEX_DTPREL_11_X ; case fixup_<ISA_LIT>_GD_GOT_32_6_X : return ELF :: R_HEX_GD_GOT_32_6_X ; case fixup_<ISA_LIT>_GD_GOT_16_X : return ELF :: R_HEX_GD_GOT_16_X ; case fixup_<ISA_LIT>_GD_GOT_11_X : return ELF :: R_HEX_GD_GOT_11_X ; case fixup_<ISA_LIT>_LD_GOT_32_6_X : return ELF :: R_HEX_LD_GOT_32_6_X ; case fixup_<ISA_LIT>_LD_GOT_16_X : return ELF :: R_HEX_LD_GOT_16_X ; case fixup_<ISA_LIT>_LD_GOT_11_X : return ELF :: R_HEX_LD_GOT_11_X ; case fixup_<ISA_LIT>_IE_32_6_X : return ELF :: R_HEX_IE_32_6_X ; case fixup_<ISA_LIT>_IE_16_X : return ELF :: R_HEX_IE_16_X ; case fixup_<ISA_LIT>_IE_GOT_32_6_X : return ELF :: R_HEX_IE_GOT_32_6_X ; case fixup_<ISA_LIT>_IE_GOT_16_X : return ELF :: R_HEX_IE_GOT_16_X ; case fixup_<ISA_LIT>_IE_GOT_11_X : return ELF :: R_HEX_IE_GOT_11_X ; case fixup_<ISA_LIT>_TPREL_32_6_X : return ELF :: R_HEX_TPREL_32_6_X ; case fixup_<ISA_LIT>_TPREL_16_X : return ELF :: R_HEX_TPREL_16_X ; case fixup_<ISA_LIT>_TPREL_11_X : return ELF :: R_HEX_TPREL_11_X ; case fixup_<ISA_LIT>_23_REG : return ELF :: R_HEX_23_REG ; case fixup_<ISA_LIT>_27_REG : return ELF :: R_HEX_27_REG ; case fixup_<ISA_LIT>_GD_PLT_B22_PCREL_X : return ELF :: R_HEX_GD_PLT_B22_PCREL_X ; case fixup_<ISA_LIT>_GD_PLT_B32_PCREL_X : return ELF :: R_HEX_GD_PLT_B32_PCREL_X ; case fixup_<ISA_LIT>_LD_PLT_B22_PCREL_X : return ELF :: R_HEX_LD_PLT_B22_PCREL_X ; case fixup_<ISA_LIT>_LD_PLT_B32_PCREL_X


<s> case fixup_<ISA_LIT>_DTPREL_LO16 : return ELF :: R_HEX_DTPREL_LO16 ; case fixup_<ISA_LIT>_DTPREL_HI16 : return ELF :: R_HEX_DTPREL_HI16 ; case fixup_<ISA_LIT>_DTPREL_32 : return ELF :: R_HEX_DTPREL_32 ; case fixup_<ISA_LIT>_DTPREL_16 : return ELF :: R_HEX_DTPREL_16 ; case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : return ELF :: R_HEX_GD_PLT_B22_PCREL ; case fixup_<ISA_LIT>_LD_PLT_B22_PCREL : return ELF :: R_HEX_LD_PLT_B22_PCREL ; case fixup_<ISA_LIT>_GD_GOT_LO16 : return ELF :: R_HEX_GD_GOT_LO16 ; case fixup_<ISA_LIT>_GD_GOT_HI16 : return ELF :: R_HEX_GD_GOT_HI16 ; case fixup_<ISA_LIT>_GD_GOT_32 : return ELF :: R_HEX_GD_GOT_32 ; case fixup_<ISA_LIT>_GD_GOT_16 : return ELF :: R_HEX_GD_GOT_16 ; case fixup_<ISA_LIT>_LD_GOT_LO16 : return ELF :: R_HEX_LD_GOT_LO16 ; case fixup_<ISA_LIT>_LD_GOT_HI16 : return ELF :: R_HEX_LD_GOT_HI16 ; case fixup_<ISA_LIT>_LD_GOT_32 : return ELF :: R_HEX_LD_GOT_32 ; case fixup_<ISA_LIT>_LD_GOT_16 : return ELF :: R_HEX_LD_GOT_16 ; case fixup_<ISA_LIT>_IE_LO16 : return ELF :: R_HEX_IE_LO16 ; case fixup_<ISA_LIT>_IE_HI16 : return ELF :: R_HEX_IE_HI16 ; case fixup_<ISA_LIT>_IE_32 : return ELF :: R_HEX_IE_32 ; case fixup_<ISA_LIT>_IE_GOT_LO16 : return ELF :: R_HEX_IE_GOT_LO16 ; case fixup_<ISA_LIT>_IE_GOT_HI16 : return ELF :: R_HEX_IE_GOT_HI16 ; case fixup_<ISA_LIT>_IE_GOT_32 : return ELF :: R_HEX_IE_GOT_32 ; case fixup_<ISA_LIT>_IE_GOT_16 : return ELF :: R_HEX_IE_GOT_16 ; case fixup_<ISA_LIT>_TPREL_LO16 : return ELF :: R_HEX_TPREL_LO16 ; case fixup_<ISA_LIT>_TPREL_HI16 : return ELF :: R_HEX_TPREL_HI16 ; case fixup_<ISA_LIT>_TPREL_32 : return ELF :: R_HEX_TPREL_32 ; case fixup_<ISA_LIT>_TPREL_16 : return ELF :: R_HEX_TPREL_16 ; case fixup_<ISA_LIT>_6_PCREL_X : return ELF :: R_HEX_6_PCREL_X ; case fixup_<ISA_LIT>_GOTREL_32_6_X : return ELF :: R_HEX_GOTREL_32_6_X ; case fixup_<ISA_LIT>_GOTREL_16_X : return ELF :: R_HEX_GOTREL_16_X ; case fixup_<ISA_LIT>_GOTREL_11_X : return ELF :: R_HEX_GOTREL_11_X ; case fixup_<ISA_LIT>_GOT_32_6_X : return ELF :: R_HEX_GOT_32_6_X ; case fixup_<ISA_LIT>_GOT_16_X : return ELF :: R_HEX_GOT_16_X ; case fixup_<ISA_LIT>_GOT_11_X : return ELF :: R_HEX_GOT_11_X ; case fixup_<ISA_LIT>_DTPREL_32_6_X : return ELF :: R_HEX_DTPREL_32_6_X ; case fixup_<ISA_LIT>_DTPREL_16_X : return ELF :: R_HEX_DTPREL_16_X ; case fixup_<ISA_LIT>_DTPREL_11_X : return ELF :: R_HEX_DTPREL_11_X ; case fixup_<ISA_LIT>_GD_GOT_32_6_X : return ELF :: R_HEX_GD_GOT_32_6_X ; case fixup_<ISA_LIT>_GD_GOT_16_X : return ELF :: R_HEX_GD_GOT_16_X ; case fixup_<ISA_LIT>_GD_GOT_11_X : return ELF :: R_HEX_GD_GOT_11_X ; case fixup_<ISA_LIT>_LD_GOT_32_6_X : return ELF :: R_HEX_LD_GOT_32_6_X ; case fixup_<ISA_LIT>_LD_GOT_16_X : return ELF :: R_HEX_LD_GOT_16_X ; case fixup_<ISA_LIT>_LD_GOT_11_X : return ELF :: R_HEX_LD_GOT_11_X ; case fixup_<ISA_LIT>_IE_32_6_X : return ELF :: R_HEX_IE_32_6_X ; case fixup_<ISA_LIT>_IE_16_X : return ELF :: R_HEX_IE_16_X ; case fixup_<ISA_LIT>_IE_GOT_32_6_X : return ELF :: R_HEX_IE_GOT_32_6_X ; case fixup_<ISA_LIT>_IE_GOT_16_X : return ELF :: R_HEX_IE_GOT_16_X ; case fixup_<ISA_LIT>_IE_GOT_11_X : return ELF :: R_HEX_IE_GOT_11_X ; case fixup_<ISA_LIT>_TPREL_32_6_X : return ELF


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI , StringRef CPU ) { return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI


<s> return false ; } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return false


<s> } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT>


<s> static bool MCLDEmulate<ISA_LIT>ELF ( LinkerScript & pScript , LinkerConfig & pConfig ) { if ( ! MCLDEmulateELF ( pScript , pConfig ) ) return false ; pConfig . targets ( ) . setEndian ( TargetOptions :: Little ) ; pConfig . targets ( ) . setBitClass ( <NUM_LIT> ) ; pConfig . attribute ( ) . constraint ( ) . enableWholeArchive ( ) ; pConfig . attribute ( ) . constraint ( ) . enableAsNeeded ( ) ; pConfig . attribute ( ) . constraint ( ) . setSharedSystem ( ) ; pConfig . attribute ( ) . predefined ( ) . unsetWholeArchive ( ) ; pConfig . attribute ( ) . predefined ( ) . unsetAsNeeded ( ) ; pConfig . attribute ( ) . predefined ( ) . setDynamic (


<s> bool <ISA_LIT>ExpandCondsets :: coalesceRegisters ( RegisterRef R1 , RegisterRef R2 ) { if ( CoaLimitActive ) { if ( CoaCounter >= CoaLimit ) return false ; CoaCounter ++ ; } unsigned BW1 , BW2 ; if ( ! isIntReg ( R1 , BW1 ) || ! isIntReg ( R2 , BW2 ) || BW1 != BW2 ) return false ; if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return


<s> <ISA_LIT>ExpandCondsets ( ) : MachineFunctionPass ( ID ) , HII ( nullptr ) , TRI ( nullptr ) , MRI ( nullptr ) , LIS ( nullptr ) , CoaLimitActive ( false ) , TfrLimitActive ( false ) , CoaCounter ( <NUM_LIT> ) , TfrCounter ( <NUM_LIT> ) { if ( OptCoaLimit . getPosition ( ) ) CoaLimitActive = true , CoaLimit = OptCoaLimit ; if ( OptTfrLimit . getPosition ( ) ) TfrLimitActive = true , TfrLimit = OptTfrLimit ; initialize<ISA_LIT>ExpandCondsetsPass ( * PassRegistry :: getPassRegistry ( )


<s> MRI = & MF . getRegInfo ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent ( ) ) ) ; bool Changed = false ; std :: set < unsigned > CoalUpd , PredUpd ; SmallVector < MachineInstr * , <NUM_LIT> > Condsets ; for ( auto & B : MF ) for ( auto & I : B ) if ( isCondset ( I ) ) Condsets . push_back ( & I ) ; Changed |= coalesceSegments ( Condsets , CoalUpd ) ; std :: set < unsigned > KillUpd ; for ( MachineInstr * MI : Condsets ) for ( MachineOperand & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) ) if ( ! CoalUpd . count ( Op . getReg ( ) ) ) KillUpd . insert ( Op . getReg ( ) ) ; updateLiveness ( KillUpd , false , true , false ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent ( ) ) ) ; for ( MachineInstr * MI : Condsets ) Changed |= split ( * MI , PredUpd ) ; Condsets . clear ( ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent ( ) ) ) ; for ( auto & B : MF ) Changed |= predicateInBlock ( B , PredUpd ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent (


<s> std :: set < unsigned > CoalUpd , PredUpd ; SmallVector < MachineInstr * , <NUM_LIT> > Condsets ; for ( auto & B : MF ) for ( auto & I : B ) if ( isCondset ( I ) ) Condsets . push_back ( & I ) ; Changed |= coalesceSegments ( Condsets , CoalUpd ) ; std :: set < unsigned > KillUpd ; for ( MachineInstr * MI : Condsets ) for ( MachineOperand & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && Op . isUse ( ) ) if ( ! CoalUpd . count ( Op . getReg ( ) ) ) KillUpd . insert ( Op . getReg ( ) ) ; updateLiveness ( KillUpd , false , true , false ) ; DEBUG ( LIS -> print ( dbgs ( ) << <STR_LIT> , MF . getFunction ( ) -> getParent (


<s> ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I -> start , I -> end , NewVN ) ) ; } while ( L2 . begin ( ) != L2 . end ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; LIS -> removeInterval ( R2 . Reg ) ; updateKillFlags ( R1 . Reg )


<s> unsigned PredState = getRegState ( PredOp ) & ~ RegState :: Kill ; MachineInstrBuilder MIB ; if ( SrcOp . isReg ( ) ) { unsigned SrcState = getRegState ( SrcOp ) ; if ( RegisterRef ( SrcOp ) == RegisterRef ( DstR , DstSR ) ) SrcState &= ~ RegState :: Kill ; MIB = BuildMI ( B , At , DL , HII -> get ( Opc ) ) . addReg ( DstR , DstState , DstSR ) . addReg ( PredOp . getReg ( ) , PredState , PredOp . getSubReg ( ) ) . addReg ( SrcOp . getReg ( ) , SrcState , SrcOp . getSubReg ( ) ) ; } else { MIB = BuildMI ( B , At , DL , HII -> get ( Opc ) ) . addReg ( DstR , DstState , DstSR ) . addReg ( PredOp . getReg ( ) , PredState , PredOp . getSubReg ( ) ) . add ( SrcOp ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB


<s> ( void ) Opc ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( Cond ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << TfrI ) ; MachineOperand & MD = TfrI . getOperand ( <NUM_LIT> ) ; MachineOperand & MP = TfrI . getOperand ( <NUM_LIT> ) ; MachineOperand & MS = TfrI . getOperand ( <NUM_LIT> ) ; if ( ! MS . isKill ( ) ) return false ; if ( MD . getSubReg ( ) && ! MRI -> shouldTrackSubRegLiveness ( MD . getReg ( ) ) ) return false ; RegisterRef RT ( MS ) ; unsigned PredR = MP . getReg ( ) ; MachineInstr * DefI = getReachingDefForPred ( RT , TfrI , PredR , Cond ) ; if ( ! DefI || ! isPredicable ( DefI ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , nullptr ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR =


<s> if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; if ( Op . isDef ( ) && Op . isUndef ( ) ) { assert ( RR . Sub && <STR_LIT> ) ; RR . Sub = <NUM_LIT> ; } addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD = MD ; bool CanUp = canMoveOver ( TfrI , Defs , Uses ) ; bool CanDown = canMoveOver ( * DefI , Defs , Uses ) ; if ( DefI -> mayLoad ( ) || DefI -> mayStore ( ) ) if ( ! canMoveMemTo ( * DefI , TfrI , true ) ) CanDown = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( CanUp ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( CanDown ? <STR_LIT> : <STR_LIT> ) ) ; MachineBasicBlock :: iterator PastDefIt = std :: next


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MI . getParent ( ) ) << <STR_LIT> << MI ) ; MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & MP = MI . getOperand ( <NUM_LIT> ) ; assert ( MD . isDef ( ) ) ; unsigned DR = MD . getReg ( ) , DSR = MD . getSubReg ( ) ; bool ReadUndef = MD . isUndef ( ) ; MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState ( ST ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineInstrBuilder ( MF , MI ) . addReg ( RT .


<s> if ( TfrLimitActive ) { if ( TfrCounter >= TfrLimit ) return false ; TfrCounter ++ ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MI . getParent ( ) ) << <STR_LIT> << MI ) ; MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & MP = MI . getOperand ( <NUM_LIT> ) ; assert ( MD . isDef ( ) ) ; unsigned DR = MD . getReg ( ) , DSR = MD . getSubReg ( ) ; bool ReadUndef = MD . isUndef ( ) ; MachineBasicBlock :: iterator At = MI ; auto updateRegs = [ & UpdRegs ] ( const MachineInstr & MI ) -> void { for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; } ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { updateRegs ( MI ) ; MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState ( ST ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineInstrBuilder ( MF , MI ) . addReg ( RT . Reg , S , RT . Sub ) ; return true


<s> auto KillAt = [ this , Reg ] ( SlotIndex K , LaneBitmask LM ) -> void { MachineInstr * MI = LIS -> getInstructionFromIndex ( K ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . getReg ( ) != Reg || MI -> isRegTiedToDefOperand ( i ) ) continue ; LaneBitmask SLM = getLaneMask ( Reg , Op . getSubReg ( ) ) ; if ( ( SLM & LM ) == SLM ) { Op . setIsKill ( true ) ; break ; } } } ; LiveInterval & LI = LIS -> getInterval (


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( R ) ) ; assert ( MRI -> isReserved ( R ) ) ; continue ; } if ( Recalc ) recalculateLiveInterval ( R ) ; if ( UpdateKills ) MRI -> clearKillFlags (


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( RS . Reg ) ) ; PhysR = RS . Reg ; } unsigned PhysS = ( RS . Sub == <NUM_LIT> ) ? PhysR : TRI -> getSubReg ( PhysR , RS . Sub ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( PhysS ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : return IfTrue ? A2_tfrt : A2_tfrf ; case <NUM_LIT> : return IfTrue ? A2_tfrpt : A2_tfrpf ; } llvm_unreachable (


<s> unsigned PhysR ; RegisterRef RS = SO ; if ( TargetRegisterInfo :: isVirtualRegister ( RS . Reg ) ) { const TargetRegisterClass * VC = MRI -> getRegClass ( RS . Reg ) ; assert ( VC -> begin ( ) != VC -> end ( ) && <STR_LIT> ) ; PhysR = * VC -> begin ( ) ; } else { assert ( TargetRegisterInfo :: isPhysicalRegister ( RS . Reg ) ) ; PhysR = RS . Reg ; } unsigned PhysS = ( RS . Sub == <NUM_LIT> ) ? PhysR : TRI -> getSubReg ( PhysR , RS


<s> unsigned Opc = MI . getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI . getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState

:: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ;


<s> void <ISA_LIT>ExpandCondsets :: predicateAt ( const MachineOperand & DefOp , MachineInstr & MI , MachineBasicBlock :: iterator Where , const MachineOperand & PredOp , bool Cond , std :: set < unsigned > & UpdRegs ) { MachineBasicBlock & B = * MI . getParent ( ) ; DebugLoc DL = Where -> getDebugLoc ( ) ; unsigned Opc = MI . getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI . getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . addOperand ( MO ) ; Ox


<s> MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF ) ) { MI . setDesc ( HII -> get ( TargetOpcode :: COPY ) ) ; unsigned S = getRegState ( ST ) ; while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineInstrBuilder ( MF , MI ) . addReg ( RT . Reg , S , RT . Sub ) ; return true ; } } MachineInstr * TfrT = genCondTfrFor ( ST , At , DR , DSR , MP , true , ReadUndef , false ) ; MachineInstr * TfrF = genCondTfrFor ( SF , At , DR , DSR , MP , false , ReadUndef , true ) ; LIS -> InsertMachineInstrInMaps ( * TfrT ) ; LIS -> InsertMachineInstrInMaps ( * TfrF ) ; for ( auto & Op : MI . operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; removeInstr ( MI ) ; return true


<s> TfrCounter ++ ; } DEBUG ( dbgs ( ) << <STR_LIT> << MI . getParent ( ) -> getNumber ( ) << <STR_LIT> << MI ) ; MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & MP = MI . getOperand ( <NUM_LIT> ) ; assert ( MD . isDef ( ) ) ; unsigned DR = MD . getReg ( ) , DSR = MD . getSubReg ( ) ; bool ReadUndef = MD . isUndef ( ) ; MachineBasicBlock :: iterator At = MI ; MachineOperand & ST = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SF = MI . getOperand ( <NUM_LIT> ) ; if ( ST . isReg ( ) && SF . isReg ( ) ) { RegisterRef RT ( ST ) ; if ( RT == RegisterRef ( SF


<s> LaneBitmask SLM = getLaneMask ( DR , DSR ) ; return ( SLM & LM ) . any ( ) ; } ; auto Dominate = [ this ] ( SetVector < MachineBasicBlock * > & Defs , MachineBasicBlock * Dest ) -> bool { for ( MachineBasicBlock * D : Defs ) if ( D != Dest && MDT -> dominates ( D , Dest ) ) return true ; MachineBasicBlock * Entry = & Dest -> getParent ( ) -> front ( ) ; SetVector < MachineBasicBlock * > Work ( Dest -> pred_begin ( ) , Dest -> pred_end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < Work . size ( ) ; ++ i ) { MachineBasicBlock * B = Work [ i ] ; if ( Defs . count ( B ) ) continue ; if ( B == Entry ) return false ; for ( auto * P : B -> predecessors ( ) ) Work . insert ( P ) ; } return true ; } ; SetVector < MachineBasicBlock * > Defs ; SmallVector < SlotIndex , <NUM_LIT> > PredDefs ; for ( auto & Seg : Range ) { if ( ! Seg . start . isRegister ( ) ) continue ; MachineInstr * DefI = LIS -> getInstructionFromIndex ( Seg . start ) ; Defs . insert ( DefI -> getParent ( ) ) ; if ( HII -> isPredicated ( * DefI ) ) PredDefs . push_back ( Seg . start ) ; } SmallVector < SlotIndex , <NUM_LIT> > Undefs ; LiveInterval & LI = LIS -> getInterval ( Reg ) ; LI . computeSubRangeUndefs ( Undefs , LM , * MRI , * LIS -> getSlotIndexes ( ) ) ; for ( auto & SI : PredDefs ) { MachineBasicBlock * BB = LIS -> getMBBFromIndex ( SI ) ; auto P = Range . extendInBlock ( Undefs , LIS -> getMBBStartIdx ( BB ) , SI ) ; if ( P . first != nullptr || P . second ) SI = SlotIndex ( ) ; } SmallVector < SlotIndex , <NUM_LIT> > ExtTo ; for ( auto & SI : PredDefs ) { if ( ! SI . isValid ( ) ) continue ; MachineBasicBlock * BB = LIS -> getMBBFromIndex ( SI ) ; if ( BB -> pred_empty ( ) ) continue ; if ( Dominate ( Defs , BB )


<s> unsigned Opc = MI . getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI . getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++