<s> if ( ! DisableOptSZExt && MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; MI -> setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI -> getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ; unsigned PR = <NUM_LIT> , S1 = <NUM_LIT> , S2 = <NUM_LIT> ; switch ( Op ) { case <STR_LIT>


<s> PeepholeDoubleRegsMap [ DstReg ] = std :: make_pair ( * & SrcReg , <STR_LIT> ) ; } if ( ! DisablePNotP && MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI . isCopy ( ) ) { assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } else { DenseMap < unsigned , std :: pair < unsigned , unsigned > > :: iterator DI = PeepholeDoubleRegsMap . find ( SrcReg ) ; if ( DI != PeepholeDoubleRegsMap . end ( ) ) { std :: pair < unsigned , unsigned > PeepholeSrc = DI -> second ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MachineOperand :: CreateReg ( PeepholeSrc . first , false , false , false , false , false , false , PeepholeSrc . second ) ) ; } } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI . getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; MRI -> clearKillFlags ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI . getOpcode ( ) ) ; MI . setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI . getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ; unsigned PR = <NUM_LIT> , S1 = <NUM_LIT> , S2 = <NUM_LIT> ; switch ( Op


<s> <ISA_LIT>PLT1 * <ISA_LIT>PLT :: create ( ) { return new <ISA_LIT>PLT1 ( *


<s> unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < <ISA_LIT>PLT0 > ( ( * it ) ) . getValue ( ) , <ISA_LIT>PLT0 :: EntrySize ) ; result += <ISA_LIT>PLT0 :: EntrySize ; ++ it ; <ISA_LIT>PLT1 * plt1 = <NUM_LIT> ; <ISA_LIT>PLT :: iterator ie = end ( ) ; while ( it != ie ) { plt1 = & ( llvm :: cast < <ISA_LIT>PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , <ISA_LIT>PLT1 :: EntrySize ) ; result += <ISA_LIT>PLT1


<s> while ( it != ie ) { plt1 = & ( llvm :: cast < <ISA_LIT>PLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , <ISA_LIT>PLT1 :: EntrySize ) ; result += <ISA_LIT>PLT1 :: EntrySize ; ++ it


<s> ++ it ; if ( end ( ) != it ) { PLTEntryBase * plt1 = & ( llvm :: cast < PLTEntryBase > ( * it ) ) ; size += ( m_pSectionData -> size ( ) - <NUM_LIT> ) * plt1 -> size ( ) ; } m_Section . setSize ( size ) ; uint32_t offset = <NUM_LIT> ; SectionData :: iterator frag , fragEnd = m_pSectionData -> end ( ) ; for ( frag = m_pSectionData -> begin ( ) ; frag != fragEnd ; ++


<s> PLTEntryBase * <ISA_LIT>PLT :: getPLT0 ( ) const { iterator first = m_pSectionData -> getFragmentList ( ) . begin ( ) ; assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ; PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( * first ) ) ; return


<s> iterator first = m_pSectionData -> getFragmentList ( ) . begin ( ) ; assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ; PLTEntryBase * plt0 = & ( llvm :: cast <


<s> return ( m_pSectionData -> size ( ) >


<s> <ISA_LIT>PLT :: <ISA_LIT>PLT ( LDSection & pSection , <ISA_LIT>GOTPLT & pGOTPLT , const LinkerConfig & pConfig ) : PLT ( pSection ) , m_GOTPLT ( pGOTPLT ) { assert ( LinkerConfig :: DynObj == pConfig . codeGenType ( ) || LinkerConfig :: Exec == pConfig . codeGenType ( ) || LinkerConfig :: Binary == pConfig . codeGenType ( ) ) ; m_PLT0 = hexagon_plt0 ; m_PLT0Size = sizeof ( hexagon_plt0 ) ; new <ISA_LIT>PLT0 ( * m_pSectionData ) ; pSection . setAlign (


<s> EM . insert ( std :: make_pair ( DstR , SrcR ) ) ; } ; DataFlowGraph & DFG = getDFG ( ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & HiOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & LoOp = MI -> getOperand ( <NUM_LIT> ) ; assert ( DstOp . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; mapRegs ( DFG . makeRegRef ( DstOp . getReg ( ) , <STR_LIT> ) , DFG . makeRegRef ( HiOp . getReg ( ) , HiOp . getSubReg ( ) ) ) ; mapRegs ( DFG . makeRegRef ( DstOp . getReg ( ) , <STR_LIT> ) , DFG . makeRegRef ( LoOp . getReg ( ) , LoOp . getSubReg ( ) ) ) ; return true ; } case <STR_LIT> : { const MachineOperand & A = MI -> getOperand ( <NUM_LIT> ) ; if ( ! A . isImm ( ) || A . getImm ( ) != <NUM_LIT> ) return false ; LLVM_FALLTHROUGH ; } case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & SrcOp = MI -> getOperand (


<s> OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! llvm :: all_of ( Defs , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; MI . setDesc ( HII . get ( NewOpc )


<s> OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! llvm :: all_of ( Defs , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; MI . setDesc ( HII . get ( NewOpc ) ) ; MI . getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; return true


<s> bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , TOI ) ; G . build ( BuildOptions :: KeepDeadPhis ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if ( Changed ) { if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ; Liveness LV ( * MRI , G ) ; LV . trace ( RDFDump ) ; LV . computeLiveIns ( ) ; LV . resetLiveIns ( ) ; LV . resetKills


<s> EM . insert ( std :: make_pair ( DstR , SrcR ) ) ; } ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & HiOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & LoOp = MI -> getOperand ( <NUM_LIT> ) ; assert ( DstOp . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { HiOp . getReg ( ) , HiOp . getSubReg ( ) } ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { LoOp . getReg ( ) , LoOp . getSubReg ( ) } ) ; return


<s> break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI -> getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! std :: all_of ( Defs . begin ( ) , Defs . end ( ) , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * MI ; MI -> setDesc ( HII . get ( NewOpc ) ) ; MI -> getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * MI ; return true


<s> if ( RDFLimit . getPosition ( ) ) { if ( RDFCount >= RDFLimit ) return false ; RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump )


<s> DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G ,


<s> CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if ( Changed ) { if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ; Liveness LV ( * MRI , G ) ; LV . trace ( RDFDump ) ; LV . computeLiveIns ( ) ; LV . resetLiveIns ( ) ; LV . resetKills


<s> if ( RDFLimit . getPosition ( ) ) { if ( RDFCount >= RDFLimit ) return false ; RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( ) ; if ( RDFDump ) { dbgs ( ) << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; dbgs ( ) << MF . getName


<s> AU . addRequired < MachineDominanceFrontier > ( ) ; AU . setPreservesAll (


<s> AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage


<s> <ISA_LIT>RDFOpt ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>RDFOptPass ( * PassRegistry :: getPassRegistry


<s> return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! std :: all_of ( Defs . begin ( ) , Defs . end ( ) , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; MI . setDesc ( HII . get ( NewOpc ) ) ; MI . getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; return true


<s> R2I . insert ( std :: make_pair ( RA . Id , SA . Id ) ) ; if ( DFG . IsDef ( RA ) && DeadNodes . count ( RA . Id ) ) if ( ! DeadInstrs . count ( SA . Id ) ) PartlyDead . insert ( SA . Id ) ; } } } SetVector < NodeId > Remove = DeadInstrs ; bool Changed = false ; for ( NodeId N : PartlyDead ) { auto SA = DFG . addr < StmtNode * > ( N ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * SA .


<s> <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if ( Changed ) { if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ; Liveness LV ( * MRI , G ) ; LV . trace ( RDFDump ) ; LV . computeLiveIns ( ) ; LV . resetLiveIns ( ) ; LV . resetKills ( ) ; } if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT>


<s> RDFCount ++ ; } MDT = & getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed ; if ( RDFDump ) MF . print ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> , nullptr ) ; <ISA_LIT>RegisterAliasInfo HAI ( HRI ) ; TargetOperandInfo TOI ( HII ) ; DataFlowGraph G ( MF , HII , HRI , * MDT , MDF , HAI , TOI ) ; G . build ( BuildOptions :: KeepDeadPhis ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>CP CP ( G ) ; CP . trace ( RDFDump ) ; Changed = CP . run ( ) ; if ( RDFDump ) dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' << PrintNode < FuncNode * > ( G . getFunc ( ) , G ) << '\n' ; <ISA_LIT>DCE DCE ( G , * MRI ) ; DCE . trace ( RDFDump ) ; Changed |= DCE . run ( ) ; if (


<s> auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( HII . isValidOffset ( Opc , RealOffset ) ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; } const Function * F = MF . getFunction ( ) ; dbgs ( ) << <STR_LIT> ; if ( F ) dbgs ( ) << F -> getName ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MB . getNumber ( ) << <STR_LIT> << MI ; llvm_unreachable (


<s> switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( HII . isValidOffset ( Opc , RealOffset ) ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; } const Function * F = MF .


<s> unsigned <ISA_LIT>RegisterInfo :: getFirstCallerSavedNonParamReg ( ) const { return <STR_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( ) const { return <STR_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { return <STR_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { return


<s> Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set (


<s> unsigned <ISA_LIT>RegisterInfo :: getStackRegister ( ) const { return


<s> bool <ISA_LIT>RegisterInfo :: isCalleeSaveReg ( unsigned


<s> bool <ISA_LIT>RegisterInfo :: isEHReturnCalleeSaveReg ( unsigned R ) const { return R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT>


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getFrameLowering ( )


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getFrameLowering (


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT>


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable (


<s> unsigned FPReg = getFrameRegister ( ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( FPReg , <NUM_LIT> ) ; Moves . push_back ( MachineMove ( <NUM_LIT> ,


<s> auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset ) ) { auto & MRI = MF . getRegInfo ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm (


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegsV3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsV3EHReturn [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; bool HasEHReturn = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget ::


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return <ISA_LIT>CSR_RegMask


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv


<s> case <STR_LIT> : case <STR_LIT> : return ISub [ GenIdx ] ; case <STR_LIT> : case <STR_LIT> : return VSub [ GenIdx ] ; } if ( const TargetRegisterClass * SuperRC = * RC -> getSuperClasses ( ) ) return get<ISA_LIT>SubRegIndex ( SuperRC


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode (


<s> MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT>


<s> assert ( GenIdx == <STR_LIT> || GenIdx == <STR_LIT> ) ; static const unsigned ISub [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned VSub [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( RC . getID ( )


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF


<s> } else { llvm_unreachable ( <STR_LIT> ) ; } } else { unsigned ResReg = HEXAGON_RESERVED_REG_1 ; if ( ! MFI . hasVarSizedObjects ( ) && TII . isValidOffset ( MI . getOpcode ( ) , ( FrameSize + Offset ) ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( getStackRegister ( ) , false , false , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( FrameSize + Offset ) ; } else if ( ! TII . isValidOffset ( <STR_LIT> , Offset ) ) { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addReg ( ResReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addImm ( Offset ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } } else { unsigned dstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addReg ( FrameReg ) . addReg ( dstReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( dstReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } else


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return


<s> static const unsigned VSub [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned WSub [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : return ISub [ GenIdx ] ; case <STR_LIT> : return VSub [ GenIdx ] ; case <STR_LIT>


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> bool <ISA_LIT>RegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! HST . useHVXOps ( ) || NewRC -> getID ( ) != <STR_LIT> . getID ( ) ) return true ; bool SmallSrc = SrcRC -> getID ( ) == <STR_LIT> . getID ( ) ; bool SmallDst = DstRC -> getID ( ) == <STR_LIT> . getID ( ) ; if ( ! SmallSrc && ! SmallDst ) return true ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const SlotIndexes & Indexes = * LIS . getSlotIndexes (


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { return <STR_LIT>


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( int x = Reserved . find_first ( ) ; x >= <NUM_LIT> ; x = Reserved .

find_next ( x ) ) markSuperRegs ( Reserved , x ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( int x = Reserved . find_first ( ) ; x >= <NUM_LIT> ; x = Reserved .


<s> unsigned <ISA_LIT>RegisterInfo :: getNumRegPressureSets ( ) const { return <NUM_LIT>


<s> <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; static const unsigned RCSetStartTable [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned SetListStart = RCSetStartTable [ RC -> getID ( ) ] ; return & RCSetsTable [


<s> static const RegClassWeight RCWeightTable [ ] = { { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; return RCWeightTable [ RC -> getID (


<s> static const int RegPressureLimit [ ] = { <NUM_LIT> , <NUM_LIT>


<s> static const int RegPressureLimit [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; assert ( ( Idx < <NUM_LIT>


<s> V0 , V1 , V2 , V3 , V4 , V5 , V6 , V7 , V8 , V9 , V10 , V11 , V12 , V13 , V14 , V15 , V16 , V17 , V18 , V19 , V20 , V21 , V22 , V23 , V24 , V25 , V26 , V27 , V28 , V29 , V30 , V31 , <NUM_LIT> } ; static const MCPhysReg VecDbl [ ] = { W0 , W1 , W2 , W3 , W4 , W5 , W6 , W7 , W8 , W9 , W10 , W11 , W12 , W13 , W14 , W15 , <NUM_LIT> } ; static const MCPhysReg VecPred [ ] = { Q0 , Q1 , Q2 , Q3 , <NUM_LIT> } ; switch ( RC -> getID ( ) ) { case IntRegsRegClassID : return Int32 ; case DoubleRegsRegClassID : return Int64 ; case PredRegsRegClassID : return Pred ; case HvxVRRegClassID : return VecSgl ; case HvxWRRegClassID : return VecDbl ; case HvxQRRegClassID : return VecPred ; default : break ; } static const MCPhysReg Empty [ ] = { <NUM_LIT> } ; dbgs ( ) << <STR_LIT> << getRegClassName ( RC


<s> P0 , P1 , P2 , P3 , <NUM_LIT> } ; static const MCPhysReg VecSgl [ ] = { V0 , V1 , V2 , V3 , V4 , V5 , V6 , V7 , V8 , V9 , V10 , V11 , V12 , V13 , V14 , V15 , V16 , V17 , V18 , V19 , V20 , V21 , V22 , V23 , V24 , V25 , V26 , V27 , V28 , V29 , V30 , V31 , <NUM_LIT> } ; static const MCPhysReg VecDbl [ ] = { W0 , W1 , W2 , W3 , W4 , W5 , W6 , W7 , W8 , W9 , W10 , W11 , W12 , W13 , W14 , W15 , <NUM_LIT> } ; static const MCPhysReg VecPred [ ] = { Q0 , Q1 , Q2 , Q3 , <NUM_LIT> } ; switch ( RC -> getID ( ) ) { case IntRegsRegClassID : return Int32 ; case DoubleRegsRegClassID : return Int64 ; case PredRegsRegClassID : return Pred ; case HvxVRRegClassID : return VecSgl ; case HvxWRRegClassID : return VecDbl ; case HvxQRRegClassID : return VecPred ; default : break ; } static const MCPhysReg Empty [ ] = { <NUM_LIT> } ; dbgs ( ) << <STR_LIT> << getRegClassName ( RC ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; return Empty


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; Register BP ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) . getFixed ( ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = <NUM_LIT>


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return getFrameRegister ( ) ; return getStackRegister


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI =


<s> unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR

) . addReg ( BP ) . addImm ( RealOffset ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = <NUM_LIT> ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false ,


<s> MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; Register BP ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister (


<s> static const MCPhysReg CalleeSavedRegsV3EHReturn [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; bool HasEHReturn = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <STR_LIT> :: V4 : case <STR_LIT> :: V5 : case <STR_LIT> :: V55 : case <STR_LIT> :: V60 : case <STR_LIT> :: V62 : return HasEHReturn ? CalleeSavedRegsV3EHReturn :


<s> MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> } else if ( MI . getOpcode ( ) == <STR_LIT> ) { } else { assert ( <NUM_LIT>


<s> static const TargetRegisterClass * const CalleeSavedRegClassesV3 [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; switch ( Subtarget . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V1 : break ; case <ISA_LIT>Subtarget ::


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegsV2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const uint16_t CalleeSavedRegsV3 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( Subtarget . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget ::


<s> bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset ) ) { auto & MRI = MF . getRegInfo ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR


<s> if ( ! UseFP && ! UseAP ) RealOffset = FrameSize + Offset ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } unsigned BP = <NUM_LIT> ; bool Valid = false ; if ( UseFP ) { BP = FP ; Valid = ValidFP ; } else if ( UseAP ) { BP = AP ; Valid = ValidFP ; } else { BP = SP ; Valid = ValidSP ; } if ( Valid ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; } const Function * F = MF . getFunction ( ) ; dbgs ( ) << <STR_LIT> ; if ( F ) dbgs ( ) << F -> getName ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MB . getNumber ( )


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCallerSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CallerSavedRegsV4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; auto & HST = static_cast < const <ISA_LIT>Subtarget &


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) .


<s> return MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP (


<s> return MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF


<s> if ( TFI -> hasFP ( MF ) ) return <STR_LIT> ; return


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP (


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( int x = Reserved . find_first ( ) ; x >= <NUM_LIT> ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( int x = Reserved . find_first ( ) ; x >= <NUM_LIT> ; x = Reserved .


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : return CalleeSavedRegClassesV3 ; } llvm_unreachable ( <STR_LIT> <STR_LIT>


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCallerSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CallerSavedRegsV4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget :: V60 : return CallerSavedRegsV4 ; } llvm_unreachable ( <STR_LIT>


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCallerSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CallerSavedRegsV4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget ::


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT>


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( HEXAGON_RESERVED_REG_1 ) ; Reserved . set ( HEXAGON_RESERVED_REG_2 ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> )


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF )


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction


<s> size_t off = <NUM_LIT> ; for ( size_t bit = <NUM_LIT> ; bit != sizeof ( T1 ) * <NUM_LIT> ; ++ bit ) { const bool valBit = ( pData >> off ) & <NUM_LIT> ; const bool maskBit = ( pMask >> bit ) & <NUM_LIT> ; if ( maskBit


<s> Relocation & rel_entry = * pTarget . getRelaDyn ( ) . create ( ) ; rel_entry . setType ( pTarget . getCopyRelType ( ) ) ; assert ( pSym . outSymbol ( )


<s> switch ( pReloc . type ( ) ) { case llvm :: ELF :: R_HEX_LO16 : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_HI16 : shift = <NUM_LIT> ; bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_32 : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_16 : bitMask = <NUM_LIT> ; alignment = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_8 : bitMask = <NUM_LIT> ; alignment = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_12_X : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_32_6_X : bitMask = <NUM_LIT> ; shift = <NUM_LIT> ; effectiveBits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_16_X : case llvm :: ELF :: R_HEX_11_X : case llvm :: ELF :: R_HEX_10_X : case llvm :: ELF :: R_HEX_9_X : case llvm :: ELF :: R_HEX_8_X : case llvm :: ELF :: R_HEX_7_X : case llvm :: ELF :: R_HEX_6_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; break ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) { uint32_t range = <NUM_LIT>


<s> break ; case llvm :: ELF :: R_HEX_12_X : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_32_6_X : bitMask = <NUM_LIT> ; shift = <NUM_LIT> ; effectiveBits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_16_X : case llvm :: ELF :: R_HEX_11_X : case llvm :: ELF :: R_HEX_10_X : case llvm :: ELF :: R_HEX_9_X : case llvm :: ELF :: R_HEX_8_X : case llvm :: ELF :: R_HEX_7_X : case llvm :: ELF :: R_HEX_6_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; break ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) { uint32_t range = <NUM_LIT> << effectiveBits ; if ( result > ( range - <NUM_LIT> ) ) return Relocator :: Overflow ; } pReloc . target ( ) |= ApplyMask <


<s> Relocator :: Result <ISA_LIT>Relocator :: applyRelocation ( Relocation & pRelocation ) { Relocation :: Type type = pRelocation . type ( ) ; if ( type > <NUM_LIT> ) { return Relocator


<s> if ( type > <NUM_LIT> ) { return Relocator :: Unknown ; } return ApplyFunctions [ type ] . func ( pRelocation , *


<s> assert ( bss_sect_hdr != NULL ) ; SectionData * bss_section = NULL ; if ( bss_sect_hdr -> hasSectionData ( ) ) bss_section = bss_sect_hdr -> getSectionData ( ) ; else bss_section = IRBuilder :: CreateSectionData ( * bss_sect_hdr ) ; uint32_t addralign = config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , pSym . size ( ) ) ; uint64_t size = ObjectBuilder :: AppendFragment ( * frag , * bss_section , addralign ) ; bss_sect_hdr -> setSize ( bss_sect_hdr -> size ( ) + size ) ; ResolveInfo :: Binding binding = ( ResolveInfo :: Binding ) pSym . binding ( ) ; if ( binding == ResolveInfo :: Weak ) binding = ResolveInfo :: Global ; LDSymbol * cpy_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( pSym . name ( ) , ( ResolveInfo :: Type ) pSym . type ( ) , ResolveInfo :: Define , binding , pSym . size ( ) , <NUM_LIT> , FragmentRef :: Create ( * frag , <NUM_LIT>

) , ( ResolveInfo :: Visibility ) pSym . other ( ) ) ;


<s> const char * <ISA_LIT>Relocator :: getName ( Relocation :: Type pType ) const { return ApplyFunctions [ pType ]


<s> RelRelMap & getRelRelMap ( ) { return m_RelRelMap


<s> Relocator :: Size <ISA_LIT>Relocator :: getSize ( Relocation :: Type pType ) const { return


<s> SymGOTMap & getSymGOTMap ( ) { return m_SymGOTMap


<s> <ISA_LIT>LDBackend & ld_backend = pParent . getTarget ( ) ; Relocation & rela_entry = * ld_backend . getRelaDyn ( ) . create ( ) ; rela_entry . setType ( pType ) ; rela_entry . targetRef ( ) . assign ( pFrag , pOffset ) ; if ( pType == llvm :: ELF :: R_HEX_RELATIVE || pSym

== NULL ) rela_entry . setSymInfo ( <NUM_LIT> ) ;


<s> static Relocator :: Address helper_get_GOT_address ( ResolveInfo & pSym , <ISA_LIT>Relocator & pParent ) { <ISA_LIT>GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( pSym ) ; assert ( got_entry !=


<s> static Relocator :: Address helper_get_PLT_address ( ResolveInfo & pSym , <ISA_LIT>Relocator & pParent ) { PLTEntryBase * plt_entry = pParent . getSymPLTMap ( ) . lookUp ( pSym ) ; assert ( plt_entry != NULL ) ; return pParent . getTarget ( ) . getPLT ( ) . addr (


<s> static <ISA_LIT>GOTEntry & helper_GOT_init ( Relocation & pReloc , bool pHasRel , <ISA_LIT>Relocator & pParent ) { ResolveInfo * rsym = pReloc . symInfo ( ) ; <ISA_LIT>LDBackend & ld_backend = pParent . getTarget ( ) ; assert ( pParent . getSymGOTMap ( ) . lookUp ( * rsym ) == NULL ) ; <ISA_LIT>GOTEntry * got_entry = ld_backend . getGOT ( ) . create ( ) ; pParent . getSymGOTMap ( ) . record ( * rsym , * got_entry ) ; if ( ! pHasRel ) { got_entry -> setValue ( <ISA_LIT>Relocator :: SymVal ) ; } else { if ( helper_use_relative_reloc ( * rsym , pParent ) ) { helper_DynRel_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_HEX_RELATIVE , pParent ) ; got_entry -> setValue ( <ISA_LIT>Relocator :: SymVal ) ; } else { helper_DynRel_init ( rsym , * got_entry , <NUM_LIT> , llvm :: ELF :: R_HEX_GLOB_DAT


<s> <ISA_LIT>LDBackend & ld_backend = pParent . getTarget ( ) ; assert ( pParent . getSymGOTMap ( ) . lookUp ( * rsym ) == NULL ) ; <ISA_LIT>GOTEntry * got_entry = ld_backend . getGOT ( ) . create ( ) ; pParent . getSymGOTMap ( ) . record ( * rsym , * got_entry ) ; if ( ! pHasRel


<s> static bool helper_use_relative_reloc ( const ResolveInfo & pSym , const <ISA_LIT>Relocator & pFactory ) { if ( pSym . isDyn ( ) || pSym . isUndef ( ) || pFactory . getTarget ( ) . isSymbolPreemptible


<s> Relocator :: Result none ( Relocation & pReloc , <ISA_LIT>Relocator &


<s> break ; case llvm :: ELF :: R_HEX_GOT_11_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; result_u = GOT_S - GOT ; pReloc . target ( ) |= ApplyMask < uint32_t > ( bitMask , result_u ) ; return Relocator :: OK ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) { int32_t range = <NUM_LIT> << ( effectiveBits - <NUM_LIT> ) ; if ( ( result > range - <NUM_LIT> ) || ( result < - range ) ) return Relocator :: Overflow ; } pReloc . target ( ) |= ApplyMask < int32_t


<s> Relocator :: Result relocGOT ( Relocation & pReloc , <ISA_LIT>Relocator & pParent ) { if ( ! ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReserveGOT ) ) { return Relocator :: BadReloc ; } <ISA_LIT>GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * pReloc . symInfo ( ) ) ; assert ( got_entry != NULL ) ; if ( <ISA_LIT>Relocator :: SymVal == got_entry -> getValue ( ) ) got_entry -> setValue ( pReloc . symValue ( ) ) ; Relocator :: Address GOT_S = helper_get_GOT_address ( * pReloc . symInfo ( ) , pParent ) ; Relocator :: Address GOT = pParent . getTarget ( ) . getGOTSymbolAddr ( ) ; int32_t result = ( int32_t ) ( GOT_S - GOT ) ; uint32_t effectiveBits = <NUM_LIT> ; uint32_t alignment = <NUM_LIT> ; uint32_t bitMask = <NUM_LIT> ; uint32_t result_u ; uint32_t shift = <NUM_LIT> ; switch ( pReloc . type ( ) ) { case llvm :: ELF :: R_HEX_GOT_LO16 : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_GOT_HI16 : bitMask =


<s> Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; FragmentRef & target_fragref = pReloc . targetRef ( ) ; Fragment * target_frag = target_fragref . frag ( ) ; LDSection & target_sect = target_frag -> getParent ( ) -> getSection ( ) ; result = ( int64_t ) ( S + A - P ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == <NUM_LIT> ) { return applyRel ( pReloc ,


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; int64_t result ; Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; FragmentRef & target_fragref = pReloc . targetRef ( ) ; Fragment * target_frag = target_fragref . frag ( ) ; LDSection & target_sect = target_frag -> getParent ( ) -> getSection ( ) ; result = ( int64_t ) ( S + A - P ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == <NUM_LIT> ) { return applyRel ( pReloc , result ) ; } if ( ! rsym -> isLocal ( ) ) { if ( rsym -> reserved ( ) & <ISA_LIT>Relocator


<s> else PLT_S = pReloc . symValue ( ) ; Relocator :: Address P = pReloc . place ( ) ; uint32_t bitMask = FINDBITMASK ( pReloc . target ( ) ) ; uint32_t result = ( PLT_S + pReloc . addend ( ) - P ) >> <NUM_LIT> ; pReloc . target ( ) = pReloc . target ( ) | ApplyMask < uint32_t > ( bitMask , result ) ; return Relocator


<s> Relocator :: Address P = pReloc . place ( ) ; uint32_t bitMask = FINDBITMASK ( pReloc . target ( ) ) ; uint32_t result = ( PLT_S + pReloc . addend ( ) - P ) >> <NUM_LIT> ; pReloc . target ( ) = pReloc . target ( ) | ApplyMask < uint32_t > ( bitMask , result ) ; return Relocator


<s> case llvm :: ELF :: R_HEX_6_X : assert ( ! ( rsym -> reserved ( ) & ReserveRel ) && <STR_LIT> ) ; return ; case llvm :: ELF :: R_HEX_32 : if ( ld_backend . symbolNeedsPLT ( * rsym ) ) { if ( ! ( rsym -> reserved ( ) & ReservePLT ) ) { helper_PLT_init ( pReloc , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReservePLT ) ; } } if ( ld_backend . symbolNeedsDynRel ( * rsym , ( rsym -> reserved ( ) & ReservePLT ) , true ) ) { if ( ld_backend . symbolNeedsCopyReloc ( pReloc , * rsym ) ) { LDSymbol & cpy_sym = defineSymbolforCopyReloc ( pBuilder , * rsym , ld_backend ) ; addCopyReloc ( * cpy_sym . resolveInfo ( ) , ld_backend ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_HEX_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; ld_backend . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_HEX_GOTREL_LO16 : case llvm :: ELF :: R_HEX_GOTREL_HI16 : case llvm :: ELF :: R_HEX_GOTREL_32 : case llvm :: ELF :: R_HEX_GOTREL_32_6_X : case llvm :: ELF :: R_HEX_GOTREL_16_X : case llvm :: ELF ::


<s> } } if ( ld_backend . symbolNeedsDynRel ( * rsym , ( rsym -> reserved ( ) & ReservePLT ) , true ) ) { if ( ld_backend . symbolNeedsCopyReloc ( pReloc , * rsym ) ) { LDSymbol & cpy_sym = defineSymbolforCopyReloc ( pBuilder , * rsym , ld_backend ) ; addCopyReloc ( * cpy_sym . resolveInfo ( ) , ld_backend ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_HEX_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; ld_backend . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_HEX_GOTREL_LO16 : case llvm :: ELF :: R_HEX_GOTREL_HI16 : case llvm :: ELF :: R_HEX_GOTREL_32 : case llvm :: ELF :: R_HEX_GOTREL_32_6_X : case llvm :: ELF :: R_HEX_GOTREL_16_X : case llvm :: ELF :: R_HEX_GOTREL_11_X : return ; case llvm :: ELF :: R_HEX_GOT_LO16 : case llvm :: ELF :: R_HEX_GOT_HI16 : case llvm :: ELF :: R_HEX_GOT_32 : case llvm :: ELF :: R_HEX_GOT_16 : case llvm :: ELF :: R_HEX_GOT_32_6_X : case llvm :: ELF :: R_HEX_GOT_16_X : case llvm :: ELF :: R_HEX_GOT_11_X : if ( rsym -> reserved ( ) & ReserveGOT ) return ; if ( config ( ) . isCodeStatic ( ) ) helper_GOT_init ( pReloc , false , * this ) ; else helper_GOT_init ( pReloc , true , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveGOT ) ; return ; case llvm :: ELF :: R_HEX_B22_PCREL : case llvm :: ELF :: R_HEX_B15_PCREL : case llvm :: ELF :: R_HEX_B7_PCREL : case llvm :: ELF :: R_HEX_B13_PCREL : case llvm :: ELF :: R_HEX_B9_PCREL : case llvm :: ELF :: R_HEX_B32_PCREL_X : case llvm :: ELF ::


<s> assert ( rsym != NULL && <STR_LIT> ) ; if ( config ( ) . isCodeStatic ( ) ) return ; assert ( pSection . getLink ( ) != NULL ) ; if ( ( pSection . getLink ( ) -> flag ( ) & llvm :: ELF :: SHF_ALLOC ) == <NUM_LIT> ) return ; if ( rsym -> isLocal ( ) ) scanLocalReloc ( pReloc , pLinker , pModule , pSection ) ; else scanGlobalReloc ( pReloc , pLinker , pModule , pSection ) ; if ( rsym -> isUndef ( ) && ! rsym -> isDyn ( ) && ! rsym -> isWeak ( ) && ! rsym ->

isNull ( ) ) issueUndefRef ( pReloc , pSection , pInput ) ;


<s> Relocator :: Result unsupported ( Relocation & pReloc


<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendOps ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>RemoveExtendArgs


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ; FunctionPass :: getAnalysisUsage


<s> AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; FunctionPass :: getAnalysisUsage ( AU


<s> if ( ! isa < PointerType > ( Arg -> getType ( ) ) ) { for ( Instruction :: use_iterator UI = Arg -> use_begin ( ) ; UI != Arg -> use_end ( ) ; ) { if ( isa < SExtInst > ( * UI ) ) { Instruction * Use = cast < Instruction > ( * UI ) ; SExtInst * SI = new SExtInst ( Arg , Use -> getType ( ) ) ; assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( Use -> getType ( ) ) ) ) ; ++ UI ; Use -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore (


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved ( <STR_LIT> ) ; FunctionPass :: getAnalysisUsage (


<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendArgs ( const <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>RemoveExtendArgs


<s> return new <ISA_LIT>RemoveExtendArgs


<s> AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved


<s> AU . addPreserved ( <STR_LIT> ) ; FunctionPass :: getAnalysisUsage ( AU


<s> initialize<ISA_LIT>RemoveExtendArgsPass ( * PassRegistry :: getPassRegistry (


<s> <ISA_LIT>RemoveExtendArgs ( ) : FunctionPass ( ID ) { initialize<ISA_LIT>RemoveExtendArgsPass ( * PassRegistry ::


<s> assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( I -> getType ( ) ) ) ) ; ++ UI ; I -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; I -> eraseFromParent ( ) ; } else { ++ UI


<s> Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; bool LongCalls = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLongCalls ( ) ; unsigned Flags = LongCalls ? <STR_LIT> :


<s> if ( AlwaysInline || ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; const MachineFunction & MF = DAG .


<s> uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back (


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( AlwaysInline || ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( )

) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ;


<s> Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI .


<s> const char * SpecialMemcpyName = <STR_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; bool LongCalls = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLongCalls ( ) ; unsigned Flags = LongCalls ? <STR_LIT> : <NUM_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) , Flags ) , std

:: move ( Args ) ) . setDiscardResult ( ) ;


<s> void <ISA_LIT>Shuffler :: append ( MCInst const & ID , MCInst const * Extender , unsigned S ) { <ISA_LIT>Instr PI ( & TUL , MCII , & ID , Extender , S ) ; Packet . push_back ( PI


<s> <ISA_LIT>Instr PI ( & TUL , MCII , & ID , Extender , S ) ; Packet . push_back ( PI


<s> void <ISA_LIT>Shuffler :: applySlotRestrictions


<s> bool bid ( unsigned B ) { unsigned b = B & ~ isSold ; if ( b ) { for ( unsigned i = <NUM_LIT> ; i < HEXAGON_PACKET_SIZE ; ++ i ) if ( b & ( <NUM_LIT>


<s> <ISA_LIT>CVIResource :: <ISA_LIT>CVIResource ( TypeUnitsAndLanes * TUL , MCInstrInfo const & MCII , unsigned s , MCInst const * id ) : <ISA_LIT>Resource ( s ) { unsigned T = <ISA_LIT>MCInstrInfo :: getType ( MCII , * id ) ; if ( TUL -> count


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCContext & Context , bool ReportErrors , MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : Context

( Context ) , MCII ( MCII ) , STI ( STI ) , ReportErrors ( ReportErrors ) {


<s> void <ISA_LIT>Shuffler :: reportError ( Twine const & Msg ) { if ( ReportErrors ) { for ( auto const & I : AppliedRestrictions ) { auto SM = Context . getSourceManager


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_MPY0


<s> ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE


<s> if ( Key == <NUM_LIT> || Units == <NUM_LIT> || ( SlotWeight * s >= <NUM_LIT> ) ) return Weight = <NUM_LIT> ; unsigned Ctpop = countPopulation ( Units ) ; unsigned Cttz = countTrailingZeros ( Units ) ; Weight = ( <NUM_LIT> << ( SlotWeight * s ) ) * ( ( MaskWeight - Ctpop ) <<


<s> unsigned Ctpop = countPopulation ( Units ) ; unsigned Cttz = countTrailingZeros ( Units ) ; Weight = ( <NUM_LIT> << ( SlotWeight * s ) ) * ( ( MaskWeight - Ctpop )


<s> iterator begin ( ) { return ( Packet


<s> iterator begin ( ) { return ( Packet .


<s> iterator end ( ) { return ( Packet . end (


<s> MCInst const * getDesc ( ) const { return


<s> unsigned getError ( ) const { return


<s> unsigned getError ( ) const { return ( Error


<s> MCInst const * getExtender ( ) const { return Extender


<s> unsigned getLanes ( ) const { return ( Lanes


<s> unsigned getUnits ( ) const { return


<s> unsigned getUnits ( ) const { return (


<s> unsigned getWeight ( ) const { return


<s> <ISA_LIT>Bid ( unsigned B ) { Bid = B ? MAX / countPopulation ( B )


<s> <ISA_LIT>Bid ( unsigned B ) { Bid = B ? MAX / countPopulation ( B ) :


<s> <ISA_LIT>Instr ( MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id ) , Extender ( Extender ) , Core (

s ) , CVI ( MCII , s , id ) , SoloException ( x ) { }


<s> <ISA_LIT>Instr ( MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id ) , Extender ( Extender ) , Core ( s

) , CVI ( MCII , s , id ) , SoloException ( x ) { }


<s> <ISA_LIT>Resource ( unsigned s ) { setUnits


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : MCII


<s> <ISA_LIT>UnitAuction ( ) : isSold ( <NUM_LIT> )


<s> unsigned isSoloException ( ) const { return ( SoloException


<s> unsigned isSoloException ( ) const {


<s> bool isValid ( ) const { return ( Valid


<s> static bool lessCore ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) { return ( <STR_LIT> ( A . Core , B . Core )


<s> static bool lessCVI ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) { return ( <STR_LIT> ( A . CVI


<s> bool mayLoad ( ) const { return ( Load )


<s> bool mayStore ( ) const { return ( Store


<s> Packet . clear ( ) ; BundleFlags = <NUM_LIT>


<s> void setError ( unsigned Err ) { Error =


<s> void setStore ( bool f = true ) { Store


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; return


<s> const unsigned MaskWeight = SlotWeight - <NUM_LIT> ; bool Key = ( <NUM_LIT> << s ) & getUnits ( ) ; assert ( SlotWeight * s < <NUM_LIT> && <STR_LIT> ) ; Weight = ( Key << ( SlotWeight * s ) ) * ( ( MaskWeight - countPopulation ( getUnits ( ) ) ) << countTrailingZeros ( getUnits ( ) ) ) ; return ( Weight


<s> if ( size ( ) > <NUM_LIT> && check ( ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' )


<s> unsigned size ( ) const { return ( Packet . size


<s> <ISA_LIT>Instr PI ( MCII , STI , & ID , Extender ,


<s> permitNonSlot ( ) ; if ( ! CheckFailure ) restrictStoreLoadOrder ( Summary ) ; if ( ! CheckFailure ) restrictBranchOrder ( Summary ) ; if ( ! CheckFailure ) restrictPreferSlot3 ( Summary ) ; return !


<s> const <ISA_LIT>PacketSummary Summary = GetPacketSummary ( ) ; if ( ! applySlotRestrictions ( Summary ) )


<s> dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ . CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ . CVI . getLanes (


<s> <ISA_LIT>Instr ( <ISA_LIT>CVIResource :: TypeUnitsAndLanes * T , MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id ) , Extender ( Extender

) , Core ( s ) , CVI ( T , MCII , s , id ) , SoloException ( x ) { }


<s> <ISA_LIT>Instr ( <ISA_LIT>CVIResource :: TypeUnitsAndLanes * T , MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id ) , Extender ( Extender ) , Core ( s ) , CVI ( T , MCII ,


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCContext & Context , bool ReportErrors , MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : Context ( Context ) , MCII ( MCII ) , STI ( STI ) , ReportErrors ( ReportErrors ) { reset (


<s> void <ISA_LIT>Shuffler :: permitNonSlot ( ) { for ( <ISA_LIT>Instr & ISJ : insts (


<s> { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; for ( std :: pair < unsigned , unsigned > jumpSlot : jumpSlots ) { if ( ! ( jumpSlot . first & Summary . branchInsts [ <NUM_LIT> ] ->


<s> void <ISA_LIT>Shuffler :: restrictPreferSlot3 ( <ISA_LIT>PacketSummary const & Summary ) { const bool HasOnlySlot3 = llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { return ( I . Core . getUnits ( ) == Slot3Mask ) ; } ) ; const bool NeedsPrefSlot3Shuffle = ( Summary . branchInsts . size ( ) <= <NUM_LIT> && ! HasOnlySlot3 && Summary . pSlot3Cnt == <NUM_LIT> && Summary . PrefSlot3Inst ) ; if ( ! NeedsPrefSlot3Shuffle ) return ; <ISA_LIT>Instr * PrefSlot3Inst = * Summary . PrefSlot3Inst ; const unsigned saveUnits = PrefSlot3Inst -> Core . getUnits ( ) ; PrefSlot3Inst -> Core . setUnits ( saveUnits & Slot3Mask ) ; const bool HasShuffledPacket = tryAuction ( Summary ) .


<s> void <ISA_LIT>Shuffler :: restrictPreferSlot3 ( <ISA_LIT>PacketSummary const & Summary ) { const bool HasOnlySlot3 = llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { return ( I . Core . getUnits ( ) == Slot3Mask ) ; } ) ; const bool NeedsPrefSlot3Shuffle = ( Summary . branchInsts . size ( ) <= <NUM_LIT> && ! HasOnlySlot3 && Summary . pSlot3Cnt == <NUM_LIT> && Summary . PrefSlot3Inst ) ; if ( ! NeedsPrefSlot3Shuffle ) return ; <ISA_LIT>Instr * PrefSlot3Inst = * Summary . PrefSlot3Inst ; const unsigned saveUnits = PrefSlot3Inst -> Core . getUnits ( ) ; PrefSlot3Inst -> Core . setUnits ( saveUnits & Slot3Mask ) ; const bool HasShuffledPacket = tryAuction ( Summary ) . hasValue ( ) ; if ( HasShuffledPacket )


<s> const unsigned Type = <ISA_LIT>MCInstrInfo :: getType ( MCII , Inst ) ; if ( Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> ) { const unsigned Units = ISJ . Core . getUnits ( ) ; if ( Units & Slot1Mask ) { AppliedRestrictions . push_back ( std :: make_pair ( Inst . getLoc ( ) , <STR_LIT> ) ) ; AppliedRestrictions . push_back ( std :: make_pair ( * Summary . Slot1AOKLoc , <STR_LIT> <STR_LIT> )


<s> bool <ISA_LIT>Shuffler :: restrictStoreLoadOrder ( <ISA_LIT>PacketSummary const & Summary ) { static const unsigned slotFirstLoadStore = Slot1Mask ; static const unsigned slotLastLoadStore = Slot0Mask ; unsigned slotLoadStore = slotFirstLoadStore ; for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) { MCInst const & ID = ISJ -> getDesc ( ) ; if ( ! ISJ -> Core . getUnits ( ) ) return false ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ID ) . mayLoad ( ) ) { if ( Summary . loads == <NUM_LIT> && Summary . loads == Summary . memory && Summary . memops == <NUM_LIT> ) switch ( ID . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleLoad ) ; break ; } else if ( Summary . loads >= <NUM_LIT> && isMemReorderDisabled ( ) ) { if ( slotLoadStore < slotLastLoadStore ) { reportError ( <STR_LIT>


<s> return false ; } bool Ok = true ; if ( size ( ) > <NUM_LIT> && ( Ok = check ( ) ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: stable_sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } LLVM_DEBUG ( for ( <ISA_LIT>Instr const & ISJ : insts ( ) ) { dbgs ( ) . write_hex ( ISJ . Core . getUnits ( ) ) ; if ( ISJ . CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ . CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ . CVI


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; for ( <ISA_LIT>Instr const & ISJ : insts ( PacketResult ) ) dbgs ( ) << <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , * ISJ . ID ) << <STR_LIT> << llvm ::

format_hex ( ISJ . Core . getUnits ( ) , <NUM_LIT> , true ) << <STR_LIT> ;


<s> const bool InvalidPacket = ( ( Summary . load0 > <NUM_LIT> || Summary . store0 > <NUM_LIT> || ! ValidHVXMem ) || ( Summary . duplex > <NUM_LIT> || ( Summary . duplex && Summary . memory ) ) ) ; return !


<s> bool <ISA_LIT>Shuffler :: ValidPacketMemoryOps ( <ISA_LIT>PacketSummary const & Summary ) const { const unsigned ZCVIloads = Summary . AllCVIloads - Summary . NonZCVIloads ; const bool ValidHVXMem = Summary . NonZCVIloads <= <NUM_LIT> && ZCVIloads <= <NUM_LIT> && Summary . CVIstores <= <NUM_LIT> ; const bool InvalidPacket = ( ( Summary . load0 > <NUM_LIT> || Summary . store0 > <NUM_LIT> || ! ValidHVXMem ) || ( Summary . duplex > <NUM_LIT> || ( Summary . duplex && Summary . memory ) ) ) ; return ! InvalidPacket


<s> Packet = * ShuffledPacket ; } llvm :: stable_sort ( * this , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI


<s> bool <ISA_LIT>Shuffler :: ValidResourceUsage ( <ISA_LIT>PacketSummary const & Summary ) { Optional < <ISA_LIT>Packet > ShuffledPacket = tryAuction ( Summary ) ; if ( ! ShuffledPacket ) { reportError ( <STR_LIT> ) ; return false ; } else { Packet = * ShuffledPacket ; } llvm :: stable_sort ( * this , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ; hvxInsts . push_back ( inst ) ; } if ( hvxInsts . size ( ) > <NUM_LIT> ) { unsigned startIdx , usedUnits ; startIdx = usedUnits = <NUM_LIT> ; if ( ! checkHVXPipes ( hvxInsts , startIdx , usedUnits ) ) { reportError ( Twine ( <STR_LIT> ) ) ; return


<s> if ( startIdx < hvxInsts . size ( ) ) { if ( ! hvxInsts [ startIdx ] . Units ) return checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits ) ; for ( unsigned b = <NUM_LIT> ; b <= <NUM_LIT> ; b <<= <NUM_LIT> ) { if ( ( hvxInsts [ startIdx ] . Units & b ) == <NUM_LIT> ) continue ; unsigned allBits = makeAllBits ( b , hvxInsts [ startIdx ] . Lanes ) ; if ( ( allBits & usedUnits ) == <NUM_LIT> ) { if ( checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits | allBits ) ) return true ; } } return


<s> unsigned subInst0Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; unsigned subInst1Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; Result += ! isDuplexAGroup ( subInst0Opcode ) ; Result += ! isDuplexAGroup (


<s> if ( Type == <STR_LIT> ) { unsigned subInst0Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; unsigned subInst1Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; Result += ! isDuplexAGroup


<s> <ISA_LIT>UnitAuction ( unsigned cs = <NUM_LIT> )


<s> <ISA_LIT>UnitAuction ( unsigned cs = <NUM_LIT> ) : isSold (


<s> const unsigned MaskWeight = SlotWeight - <NUM_LIT> ; unsigned Units = getUnits ( ) ; unsigned Key = ( ( <NUM_LIT> << s ) & Units ) != <NUM_LIT> ; if ( Key == <NUM_LIT> || Units == <NUM_LIT> || ( SlotWeight * s >= <NUM_LIT> ) ) return Weight = <NUM_LIT> ; unsigned Ctpop = countPopulation ( Units ) ; unsigned Cttz = countTrailingZeros ( Units ) ; Weight = ( <NUM_LIT> << ( SlotWeight * s ) ) * ( ( MaskWeight - Ctpop ) << Cttz ) ; return


<s> else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ -> CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ; DEBUG ( dbgs ( ) << '\n'


<s> <ISA_LIT>Instr ( MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID ( id

) , Extender ( Extender ) , Core ( s ) , SoloException ( x ) { }


<s> <ISA_LIT>Instr ( MCInst const * id , MCInst const * Extender , unsigned s , bool x = false ) : ID

( id ) , Extender ( Extender ) , Core ( s ) , SoloException ( x ) { }


<s> void setUnits ( unsigned s ) { Slots = s & ~ ( - <NUM_LIT> << HEXAGON_PACKET_SIZE ) ; setWeight ( s )


<s> <ISA_LIT>UnitAuction AuctionCore ( Summary . ReservedSlotMask ) ; std :: stable_sort ( PacketResult . begin ( ) , PacketResult . end ( ) , <STR_LIT> ) ; const bool ValidSlots = llvm :: all_of ( insts ( PacketResult ) , [ & AuctionCore ] ( <ISA_LIT>Instr const & I ) { return AuctionCore . bid ( I . Core . getUnits ( ) ) ; } ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; for ( <ISA_LIT>Instr const & ISJ : insts ( PacketResult ) ) dbgs ( ) << <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , * ISJ . ID ) << <STR_LIT> << llvm :: format_hex ( ISJ . Core . getUnits ( ) ,


<s> llvm :: Optional < <ISA_LIT>Shuffler :: <ISA_LIT>Packet > <ISA_LIT>Shuffler :: tryAuction ( <ISA_LIT>PacketSummary const & Summary ) const { <ISA_LIT>Packet PacketResult = Packet ; <ISA_LIT>UnitAuction AuctionCore ( Summary . ReservedSlotMask ) ; std :: stable_sort ( PacketResult . begin ( ) , PacketResult . end ( ) , <STR_LIT> ) ; const bool ValidSlots = llvm :: all_of ( insts ( PacketResult ) , [ & AuctionCore ] ( <ISA_LIT>Instr const & I ) { return AuctionCore . bid ( I . Core . getUnits ( ) ) ; } ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT> :


<s> for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ; hvxInsts . push_back ( inst


<s> reportError ( <STR_LIT> ) ; return false ; } else { Packet = * ShuffledPacket ; } std :: stable_sort ( begin ( ) , end ( ) , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const_iterator I = cbegin ( ) ; I != cend ( ) ; ++ I ) { struct CVIUnits inst ; inst . Units = I -> CVI . getUnits ( ) ; inst . Lanes = I -> CVI . getLanes ( ) ; if ( inst . Units == <NUM_LIT> ) continue ; hvxInsts . push_back ( inst ) ; } if ( hvxInsts . size ( ) > <NUM_LIT> ) { unsigned startIdx , usedUnits ; startIdx = usedUnits = <NUM_LIT> ; if ( ! checkHVXPipes ( hvxInsts , startIdx


<s> void <ISA_LIT>Shuffler :: reportError ( Twine const & Msg ) { if ( ReportErrors ) Context . reportError


<s> bool Ok = true ; if ( size ( ) > <NUM_LIT> && ( Ok = check ( ) ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip <


<s> MCInst const & getDesc ( ) const { return


<s> unsigned getLanes ( ) const { return Lanes


<s> bool mayStore ( ) const { return Store


<s> <ISA_LIT>Instr ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst const * id , MCInst const * Extender , unsigned s ) : ID ( id ) , Extender ( Extender ) , Core (


<s> <ISA_LIT>Instr ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCInst const * id , MCInst const * Extender , unsigned s ) : ID ( id ) , Extender ( Extender ) , Core ( s


<s> const_packet_range insts ( ) const { return make_range ( cbegin ( ) ,


<s> return make_range ( cbegin ( ) , cend


<s> void <ISA_LIT>Shuffler :: reportError ( llvm :: Twine const & Msg ) { if ( ReportErrors ) Context . reportError (


<s> setUnits ( ( ( <NUM_LIT> << HEXAGON_PACKET_SIZE ) - <NUM_LIT>


<s> if ( size ( ) > <NUM_LIT> && ( Ok = check ( ) ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI


<s> if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ -> CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ; DEBUG ( dbgs ( )


<s> bool Key = ( <NUM_LIT> << s ) & getUnits ( ) ; Weight = ( Key << ( SlotWeight * s ) ) * ( ( MaskWeight - countPopulation ( getUnits ( ) ) ) << countTrailingZeros ( getUnits


<s> bool Key = ( <NUM_LIT> << s ) & getUnits ( ) ; Weight = ( Key << ( SlotWeight * s ) ) * ( ( MaskWeight - countPopulation ( getUnits

( ) ) ) << countTrailingZeros ( getUnits ( ) ) ) ;


<s> void <ISA_LIT>Shuffler :: append ( MCInst const * ID , MCInst const * Extender , unsigned S , bool X ) { <ISA_LIT>Instr PI ( & TUL , MCII , ID , Extender , S , X ) ; Packet . push_back ( PI


<s> <ISA_LIT>CVIResource :: SetupTUL ( & TUL , STI . getCPU


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes (


<s> if ( ( load0 > <NUM_LIT> || store0 > <NUM_LIT> || CVIloads > <NUM_LIT> || CVIstores > <NUM_LIT> ) || ( duplex > <NUM_LIT> || ( duplex && memory ) ) || ( solo && size ( ) > <NUM_LIT> ) || ( onlyAX && neitherAnorX > <NUM_LIT> ) || ( onlyAX && xtypeFloat ) ) { Error = SHUFFLE_ERROR_INVALID ; return false ; } if ( jump1 && jumps > <NUM_LIT> ) { Error = SHUFFLE_ERROR_BRANCHES ; return false ; } bool bOnlySlot3 = false ; for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) { MCInst const * ID = ISJ -> getDesc ( ) ; if ( ! ISJ -> Core . getUnits ( ) ) { Error = SHUFFLE_ERROR_UNKNOWN ; return false ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . getOpcode ( ) != <STR_LIT> ) if ( onlyNo1 ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & ~ slotOne ) ; if ( <ISA_LIT>MCInstrInfo :: getType ( MCII , * ID ) != <STR_LIT> ) if ( onlyAin1 ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & ~ slotOne ) ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . isCall ( ) ) if ( jumps > <NUM_LIT> ) { if ( slotJump < slotLastJump ) { Error = SHUFFLE_ERROR_BRANCHES ; return false ; } ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotJump ) ; slotJump >>= <NUM_LIT> ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . mayLoad ( ) ) { if ( loads == <NUM_LIT> && loads == memory ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleLoad ) ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . mayStore ( ) ) { if ( ! store0 ) { if ( stores == <NUM_LIT> ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleStore ) ; else if ( stores > <NUM_LIT> ) { if ( slotLoadStore < slotLastLoadStore ) { Error = SHUFFLE_ERROR_STORES ; return false ; } ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotLoadStore ) ; slotLoadStore >>= <NUM_LIT> ; } } if ( store1 && stores > <NUM_LIT> ) { Error = SHUFFLE_ERROR_STORES ; return false ; } } if ( ISJ -> Core . getUnits ( ) == slotThree ) bOnlySlot3 = true ; if ( ! ISJ -> Core . getUnits ( ) ) { Error = SHUFFLE_ERROR_NOSLOTS


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes (


<s> <ISA_LIT>Instr ( <ISA_LIT>CVIResource :: TypeUnitsAndLanes * T , MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s ) : ID ( id ) , Extender ( Extender

) , Core ( s ) , CVI ( T , MCII , s , id ) { }


<s> <ISA_LIT>Instr ( <ISA_LIT>CVIResource :: TypeUnitsAndLanes * T , MCInstrInfo const & MCII , MCInst const * id , MCInst const * Extender , unsigned s ) : ID ( id ) , Extender ( Extender ) , Core ( s )


<s> bool <ISA_LIT>Shuffler :: applySlotRestrictions ( <ISA_LIT>PacketSummary const & Summary , const bool DoShuffle ) { restrictSlot1AOK ( Summary ) ; restrictNoSlot1Store ( Summary ) ; permitNonSlot ( ) ; if ( ! CheckFailure ) restrictStoreLoadOrder ( Summary ) ; if ( ! CheckFailure ) restrictBranchOrder ( Summary


<s> if ( ! ValidPacketMemoryOps ( Summary ) ) { reportError ( <STR_LIT> ) ; return false ; } if ( RequireShuffle ) ValidResourceUsage (


<s> if ( ! applySlotRestrictions ( Summary , RequireShuffle ) ) return false ; if ( ! ValidPacketMemoryOps ( Summary


<s> <ISA_LIT>Shuffler :: <ISA_LIT>Shuffler ( MCContext & Context , bool ReportErrors , MCInstrInfo const & MCII , MCSubtargetInfo const & STI ) : Context ( Context ) ,

BundleFlags ( ) , MCII ( MCII ) , STI ( STI ) , ReportErrors ( ReportErrors ) , CheckFailure ( ) {


<s> if ( ReportErrors ) reportResourceUsage ( Summary ) ; reportError ( Twine ( <STR_LIT> )


<s> if ( ReportErrors ) reportResourceUsage ( Summary ) ; reportError ( Twine ( <STR_LIT>


<s> bool <ISA_LIT>Shuffler :: shuffle ( ) { if ( size ( ) > HEXAGON_PACKET_SIZE ) { reportError ( <STR_LIT> ) ; return false ; } bool Ok = check ( ) ; if ( size ( ) > <NUM_LIT> && Ok ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: stable_sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } LLVM_DEBUG ( for ( <ISA_LIT>Instr const & ISJ : insts ( ) ) { dbgs ( ) . write_hex ( ISJ . Core . getUnits ( ) ) ; if ( ISJ . CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ . CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ . CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ .


<s> llvm :: stable_sort ( PacketResult , <STR_LIT> ) ; const bool ValidSlots = llvm :: all_of ( insts ( PacketResult ) , [ & AuctionCore ] ( <ISA_LIT>Instr const & I ) { return AuctionCore . bid ( I . Core . getUnits ( ) ) ; } ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( ValidSlots ? <STR_LIT>


<s> Optional < <ISA_LIT>Packet > ShuffledPacket = tryAuction ( Summary ) ; if ( ! ShuffledPacket ) { reportResourceError ( Summary , <STR_LIT> ) ; return false ; } llvm :: stable_sort ( * ShuffledPacket , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const auto & I : * ShuffledPacket ) { struct CVIUnits inst ; inst . Units = I . CVI .


<s> unsigned getUnits ( ) const { return (


<s> bool isValid ( ) const { return Valid


<s> bool mayStore ( ) const { return Store


<s> void setStore ( bool f = true ) { Store =


<s> Slots = s & ( ( <NUM_LIT> << HEXAGON_PACKET_SIZE ) - <NUM_LIT> ) ; setWeight ( s


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE


<s> else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ -> CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ; DEBUG ( dbgs ( ) << '\n' ) ; return Ok


<s> FunctionPass * llvm :: create<ISA_LIT>SplitConst32AndConst64 ( ) { return new <ISA_LIT>SplitConst32AndConst64 (


<s> <ISA_LIT>SplitConst32AndConst64 ( ) : MachineFunctionPass


<s> <ISA_LIT>SplitConst32AndConst64 ( ) : MachineFunctionPass (