<s> Lex ( ) ; AccessAlignmentLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( AccessAlignment ) ) return true ; if ( ! isPowerOf2_64 ( AccessAlignment ) ) return Error ( AccessAlignmentLoc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( Size < <NUM_LIT> ) return Error ( SizeLoc , <STR_LIT> <STR_LIT> ) ; if ( ByteAlignment < <NUM_LIT> ) return Error ( ByteAlignmentLoc , <STR_LIT> <STR_LIT> ) ; if ( ! Sym -> isUndefined ( ) ) return Error ( Loc , <STR_LIT> + Sym -> getName ( ) ) ; <ISA_LIT>MCELFStreamer & <ISA_LIT>ELFStreamer = static_cast < <ISA_LIT>MCELFStreamer & > ( getStreamer ( ) ) ; if ( IsLocal ) { <ISA_LIT>ELFStreamer . <ISA_LIT>MCEmitLocalCommonSymbol ( Sym , Size , ByteAlignment , AccessAlignment ) ; return false ; } <ISA_LIT>ELFStreamer . <ISA_LIT>MCEmitCommonSymbol ( Sym , Size ,


<s> DEBUG ( MCB . dump_pretty ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCB . setLoc ( IDLoc ) ; const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; <ISA_LIT>MCChecker Check ( getContext ( ) , MII , getSTI ( ) , MCB , * RI ) ; bool CheckOk = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MII , getSTI ( ) , getContext ( ) , MCB , & Check ) ; if ( CheckOk


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , _STI , MII ) , Parser ( _Parser ) , MCB ( <ISA_LIT>MCInstrInfo :: createBundle ( ) ) , InBrackets ( false ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; MCAsmParserExtension :: Initialize ( _Parser )


<s> <ISA_LIT>Operand & FirstOperand = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( FirstOperand . isToken ( ) && FirstOperand . getToken ( ) == <STR_LIT> ) { assert ( Operands . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( InBrackets ) { getParser ( ) . Error ( IDLoc , <STR_LIT> ) ; return true ; } InBrackets = true ; return false ; } if ( FirstOperand . isToken ( ) && FirstOperand . getToken ( ) == <STR_LIT> ) { assert ( Operands . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! InBrackets ) { getParser ( ) . Error ( IDLoc , <STR_LIT> ) ; return true ; } InBrackets = false ; if ( matchBundleOptions ( ) ) return true ; return finishBundle ( IDLoc , Out


<s> if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( std :: remove_if ( Collapsed . begin ( ) , Collapsed . end ( ) , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split


<s> if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( std :: remove_if ( Collapsed . begin ( ) , Collapsed . end ( ) , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed


<s> Lexer . Lex ( ) ; bool Contigious = Lexer . getTok ( ) . getString ( ) . data ( ) == Lookahead . back ( ) . getString ( ) . data ( ) + Lookahead . back ( ) . getString ( ) . size ( ) ; bool Type = Lexer . is ( AsmToken :: Identifier ) || Lexer . is ( AsmToken :: Dot ) || Lexer . is ( AsmToken :: Integer ) || Lexer . is ( AsmToken :: Real ) || Lexer . is ( AsmToken :: Colon ) ; bool Workaround = Lexer . is ( AsmToken :: Colon ) || Lookahead . back ( ) . is ( AsmToken :: Colon ) ; Again = ( Contigious && Type ) || ( Workaround && Type ) ; NeededWorkaround = NeededWorkaround || ( Again && ! ( Contigious && Type ) ) ; } std :: string Collapsed = RawString ; Collapsed . erase ( std :: remove_if ( Collapsed . begin ( ) , Collapsed . end ( ) , isspace ) , Collapsed . end ( ) ) ; StringRef FullString = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = FullString . split ( '.' ) ; unsigned DotReg = matchRegister ( DotSplit . first . lower ( ) ) ; if ( DotReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { if ( DotSplit . second . empty ( ) ) { RegNo = DotReg ; EndLoc = Lexer . getLoc


<s> void adds3_6ImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT>


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( & <ISA_LIT>MCInstrInfo :: getExpr ( * getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue


<s> <ISA_LIT>MCExpr * Expr = const_cast < <ISA_LIT>MCExpr * > ( cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ) ; int64_t Value ; if ( ! Expr ->


<s> MCInst NewInst ; NewInst . setOpcode ( MCI . getOpcode ( ) ) ; for ( MCOperand & I : MCI ) if ( I . isImm ( ) ) { int64_t Value ( I . getImm ( ) ) ; NewInst . addOperand ( MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( Value , getContext ( ) ) , getContext ( ) ) ) ) ; } else { if ( I . isExpr ( ) && cast < <ISA_LIT>MCExpr > ( I . getExpr ( ) ) -> signMismatch ( ) && WarnSignedMismatch ) Warning ( MCI . getLoc ( ) , <STR_LIT> ) ; NewInst . addOperand ( I ) ; } MCI =


<s> if ( isSigned ) { if ( Res < ( <NUM_LIT> << ( bits - <NUM_LIT> ) ) && Res >= - ( <NUM_LIT> << ( bits - <NUM_LIT> ) ) ) return true ; } else { if ( bits == <NUM_LIT> ) return true ; if ( Res >= <NUM_LIT> ) return ( ( uint64_t ) Res < ( uint64_t ) ( <NUM_LIT> << bits ) ) ? true : false ; else { const int64_t high_bit_set = <NUM_LIT> <<


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> ,


<s> if ( FirstOperand . isToken ( ) && FirstOperand . getToken ( ) == <STR_LIT> ) { assert ( Operands . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! InBrackets ) { getParser ( ) . Error ( IDLoc , <STR_LIT> ) ; return true ; } InBrackets = false ; if ( matchBundleOptions ( ) ) return true ; return finishBundle ( IDLoc , Out ) ; } MCInst * SubInst = new ( getParser ( ) . getContext ( ) ) MCInst ; if ( matchOneInstruction ( * SubInst , IDLoc , Operands , ErrorInfo , MatchingInlineAsm ) ) return true ; <ISA_LIT>MCInstrInfo :: extendIfNeeded ( getParser ( ) . getContext ( ) , MCII , MCB , * SubInst ) ; MCB . addOperand ( MCOperand :: createInst ( SubInst )


<s> bool <ISA_LIT>AsmParser :: mustExtend ( OperandVector & Operands ) { unsigned Count = <NUM_LIT> ; for ( std :: unique_ptr < MCParsedAsmOperand > & i : Operands ) if ( i -> isImm ( ) ) if ( <ISA_LIT>MCInstrInfo :: mustExtend ( * static_cast < <ISA_LIT>Operand * > ( i . get ( ) ) -> Imm . Val ) ) ++ Count ; assert ( Count < <NUM_LIT> && <STR_LIT> ) ; return Count ==


<s> if ( ! Subsection -> evaluateAsAbsolute ( Res ) ) return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; if ( ( Res < <NUM_LIT> ) && ( Res > - <NUM_LIT> ) ) Subsection = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( <NUM_LIT> + Res , getContext ( ) ) , getContext ( ) ) ; getStreamer ( ) .


<s> getParser ( ) . parseExpression ( Subsection ) ; if ( ! Subsection -> evaluateAsAbsolute ( Res ) ) return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; if ( ( Res < <NUM_LIT> ) && ( Res > - <NUM_LIT> ) ) Subsection = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( <NUM_LIT>

+ Res , getContext ( ) ) , getContext ( ) ) ;


<s> bool <ISA_LIT>AsmParser :: parseExpressionOrOperand ( OperandVector & Operands ) { if ( implicitExpressionLocation ( Operands ) ) { MCAsmParser & Parser = getParser ( ) ; SMLoc Loc = Parser . getLexer ( ) . getLoc ( ) ; MCExpr const * Expr = nullptr ; bool Error = parseExpression ( Expr )


<s> continue ; } case AsmToken :: Hash : { bool MustNotExtend = false ; bool ImplicitExpression = implicitExpressionLocation ( Operands ) ; SMLoc ExprLoc = Lexer . getLoc ( ) ; if ( ! ImplicitExpression ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Token . getString ( ) , Token . getLoc ( ) ) ) ; Lexer . Lex ( ) ; bool MustExtend = false ; bool HiOnly = false ; bool LoOnly = false ; if ( Lexer . is ( AsmToken :: Hash ) ) { Lexer . Lex ( ) ; MustExtend = true ; } else if ( ImplicitExpression ) MustNotExtend = true ; AsmToken const & Token = Parser . getTok ( ) ; if ( Token . is ( AsmToken :: Identifier ) ) { StringRef String = Token . getString ( ) ; AsmToken IDToken = Token ; if ( String . lower ( ) == <STR_LIT> ) { HiOnly = true ; } else if ( String . lower ( ) == <STR_LIT> ) { LoOnly = true ; } if ( HiOnly || LoOnly ) { AsmToken LParen = Lexer . peekTok ( ) ; if ( ! LParen . is ( AsmToken :: LParen ) ) { HiOnly = false ; LoOnly = false ; } else { Lexer . Lex ( ) ; } } } MCExpr const * Expr = nullptr ; if ( parseExpression ( Expr ) ) return true ; int64_t Value ; MCContext & Context = Parser . getContext ( ) ; assert ( Expr != nullptr ) ; if ( Expr -> evaluateAsAbsolute ( Value ) ) { if ( HiOnly ) Expr = MCBinaryExpr :: createLShr ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Context ) , Context ) ; if ( HiOnly || LoOnly ) Expr = MCBinaryExpr :: createAnd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Context ) , Context ) ; } else { MCValue Value ; if ( Expr -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) { if ( ! Value . isAbsolute ( ) ) { switch ( Value . getAccessVariant ( ) ) { case MCSymbolRefExpr :: VariantKind :: VK_TPREL : case MCSymbolRefExpr :: VariantKind :: VK_DTPREL : MustNotExtend = ! MustExtend ; break ; default : break ; } } } } Expr = <ISA_LIT>MCExpr :: create ( Expr , Context ) ; <ISA_LIT>MCInstrInfo :: setMustNotExtend ( * Expr ,


<s> Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) <<


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue


<s> void addn8_0ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> void adds12_0ExtOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst


<s> void adds32_0ImmOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst ,


<s> void adds8_0Imm64Operands ( MCInst & Inst , unsigned


<s> void adds8_0ImmOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N


<s> void adds9_0ExtOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst ,


<s> void addu10_0ExtOperands ( MCInst & Inst , unsigned


<s> void addu2_0ImmOperands ( MCInst & Inst


<s> void addu32_0ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> void addu32_0ImmOperands ( MCInst & Inst , unsigned


<s> void addu32_0MustExtOperands ( MCInst & Inst , unsigned N )


<s> void addu5_0ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N


<s> void addu5_0ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N )


<s> void addu64_0ImmOperands ( MCInst & Inst , unsigned N )


<s> void addu8_0ExtOperands ( MCInst & Inst , unsigned N )


<s> void addu9_0ImmOperands ( MCInst & Inst , unsigned


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false ,


<s> bool isn8_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false ,


<s> bool iss10_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true ,


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> ,


<s> bool iss16_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> ,


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true ,


<s> bool iss9_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> ,


<s> bool iss9_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true ,


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , true , false


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false


<s> bool isu8_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true ,


<s> bool isu8_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true


<s> while ( true ) { if ( ! Parser . getTok ( ) . is ( AsmToken :: Colon ) ) return false ; Lex ( ) ; StringRef Option = Parser . getTok ( ) . getString ( ) ; if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setOuterLoop (


<s> bool <ISA_LIT>AsmParser :: matchBundleOptions ( ) { MCAsmParser & Parser = getParser ( ) ; while ( true ) { if ( ! Parser . getTok ( ) . is ( AsmToken :: Colon ) ) return false ; Lex ( ) ; StringRef Option = Parser . getTok ( ) . getString ( ) ; if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled


<s> if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef Whole =


<s> StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; ( void ) Second ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = Raw ; Collapsed . erase ( remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef Whole =


<s> Tokens . emplace_back ( Lexer . getTok ( ) ) ; Lex ( ) ; switch ( Tokens . back ( ) . getKind ( ) ) { case AsmToken :: TokenKind :: Hash : if ( Tokens . size ( ) > <NUM_LIT> ) if ( ( Tokens . end ( ) - <NUM_LIT> ) -> getKind ( ) == AsmToken :: TokenKind :: Plus ) { Tokens . insert ( Tokens . end ( ) - <NUM_LIT> , AsmToken ( AsmToken :: TokenKind :: Comma , Comma ) ) ; Done = true ; } break ; case AsmToken ::


<s> NeededWorkaround = NeededWorkaround || ( Again && ! ( Contigious && Type ) ) ; } std :: string Collapsed = RawString ; Collapsed . erase ( remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef FullString = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = FullString . split ( '.' ) ; unsigned DotReg = matchRegister ( DotSplit . first . lower ( ) ) ; if ( DotReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { if ( DotSplit . second . empty ( ) ) { RegNo = DotReg ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return true ; return false ; } else { RegNo = DotReg ; size_t First = RawString . find ( '.' ) ; StringRef DotString ( RawString . data ( ) + First , RawString . size ( ) - First ) ; Lexer . UnLex ( AsmToken ( AsmToken :: Identifier , DotString ) ) ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return true ; return false ; } } std :: pair < StringRef , StringRef > ColonSplit = StringRef ( FullString ) . split ( ':' ) ; unsigned ColonReg = matchRegister ( ColonSplit . first . lower ( ) ) ; if ( ColonReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { Lexer . UnLex ( Lookahead . back ( ) ) ; Lookahead . pop_back ( ) ; Lexer . UnLex ( Lookahead . back ( ) ) ; Lookahead . pop_back ( ) ; RegNo =


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCB . setLoc ( IDLoc ) ; const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; <ISA_LIT>MCChecker Check ( getContext ( ) , MCII , getSTI ( ) , MCB , * RI ) ; bool CheckOk = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , getSTI ( ) , getContext ( ) , MCB , & Check ) ; if ( CheckOk ) { if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) == <NUM_LIT> ) { assert ( ! <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) ; assert ( ! <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) ; return false


<s> MCSubtargetInfo const & STI = getSTI ( ) ; MCInst OrigBundle = MCB ; <ISA_LIT>MCChecker Check ( getContext ( ) , MII , STI , MCB , * RI , true ) ; bool CheckOk = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MII , STI , getContext ( ) , MCB , & Check , true ) ; if ( CheckOk ) { if ( <ISA_LIT>MCInstrInfo :: bundleSize (


<s> if ( ! Parser . getTok ( ) . is ( AsmToken :: Colon ) ) return false ; Lex ( ) ; char const * MemNoShuffMsg = <STR_LIT> <STR_LIT> ; StringRef Option = Parser . getTok ( ) . getString ( ) ; auto IDLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setOuterLoop


<s> StringRef Option = Parser . getTok ( ) . getString ( ) ; auto IDLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> )

<ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; <ISA_LIT>MCExpr * Expr = const_cast < <ISA_LIT>MCExpr * > ( cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ) ; int64_t Value ; if ( ! Expr -> evaluateAsAbsolute ( Value ) ) { Inst . addOperand ( MCOperand :: createExpr ( Expr )


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; <ISA_LIT>MCExpr * Expr = const_cast < <ISA_LIT>MCExpr * > ( cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ) ; int64_t Value ; if ( ! Expr -> evaluateAsAbsolute ( Value ) ) { Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; return ; } int64_t Extended = SignExtend64 ( Value


<s> NewInst . setOpcode ( MCI . getOpcode ( ) ) ; for ( MCOperand & I : MCI ) if ( I . isImm ( ) ) { int64_t Value ( I . getImm ( ) ) ; NewInst . addOperand ( MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( Value , getContext ( ) ) , getContext ( ) ) ) ) ; } else { if ( I . isExpr ( ) && cast < <ISA_LIT>MCExpr > ( I . getExpr ( ) ) -> signMismatch (

) && WarnSignedMismatch ) Warning ( MCI . getLoc ( ) , <STR_LIT> ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate , Context ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return std :: unique_ptr < <ISA_LIT>Operand >


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Register , Context ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc =


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return std :: unique_ptr < <ISA_LIT>Operand


<s> while ( ! Lexer . is ( AsmToken :: RCurly ) ) Lexer


<s> while ( ! Lexer . is ( AsmToken :: RCurly ) ) Lexer . Lex ( ) ; Lexer . Lex ( )


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCB . setLoc ( IDLoc ) ; const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; <ISA_LIT>MCChecker Check ( getContext ( ) , MII , getSTI ( ) , MCB , * RI ) ; bool CheckOk = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MII , getSTI ( ) , getContext ( ) , MCB , & Check ) ; if ( CheckOk )


<s> if ( ! Parser . getStreamer ( ) . hasRawTextSupport ( ) ) { MCELFStreamer * MES = static_cast < MCELFStreamer * > ( & Parser . getStreamer ( ) ) ; Assembler = & MES -> getAssembler ( )


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , _STI , MII ) , Parser ( _Parser ) , InBrackets ( false ) { MCB . setOpcode ( <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; MCAsmParserExtension :: Initialize ( _Parser


<s> bool isa30_2Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> ,


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , true ,


<s> bool isf32Imm ( ) const { return false


<s> bool ism32_0Imm ( ) const { return true


<s> bool isn1Const ( ) const { if ( ! isImm ( ) ) return


<s> bool isReg ( ) const override { return Kind


<s> bool iss10_6Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT>


<s> bool iss11_2Imm ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true ,


<s> bool iss11_3Imm ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , true


<s> bool iss29_3Imm ( ) const { return true


<s> bool iss30_2Imm ( ) const { return true


<s> bool iss32_0Imm ( ) const { return true


<s> bool iss3_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false


<s> bool iss3_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false ,


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false


<s> bool iss7_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true ,


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false


<s> bool isu1_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false ,


<s> bool isu31_1Imm ( ) const { return true


<s> bool isu32_0MustExt ( ) const { return isImm ( )


<s> bool isu3_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false ,


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , true , true


<s> bool isu64_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , true ,


<s> bool isu7_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false


<s> bool isu8_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false


<s> bool isu8_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false


<s> bool isu9_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false


<s> TmpInst . setOpcode ( opCode ) ; TmpInst . addOperand ( Rdd ) ; TmpInst . addOperand ( MO1 ) ; TmpInst . addOperand


<s> if ( ! Parser . getTok ( ) . is ( AsmToken :: Colon ) ) return false ; Lex ( ) ; char const * MemNoShuffMsg = <STR_LIT> <STR_LIT> ; StringRef Option = Parser . getTok ( ) . getString ( ) ; auto IDLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; } else if ( Option . compare_lower (


<s> switch ( result ) { default : break ; case Match_Success : return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : case Match_InvalidTiedOperand : SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= InstOperands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( static_cast < <ISA_LIT>Operand * > ( InstOperands [ ErrorInfo ] . get ( ) ) ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc


<s> unsigned <ISA_LIT>AsmParser :: matchRegister (


<s> std :: string errStr ; raw_string_ostream ES ( errStr ) ; ES << <STR_LIT> << Val << <STR_LIT> << format_hex ( Val , <NUM_LIT> ) << <STR_LIT> ; if ( Max >= <NUM_LIT> ) ES << <STR_LIT> << Max ; else ES << Max << <STR_LIT> <<


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . lower ( ) == <STR_LIT> ) return ParseDirectiveFalign ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( ( IDVal . lower ( ) == <STR_LIT> ) || ( IDVal . lower ( ) == <STR_LIT>

) ) return ParseDirectiveComm ( true , DirectiveID . getLoc ( ) ) ;


<s> if ( ! getParser ( ) . parseExpression ( Value ) ) { const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( Value ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( Size , IntValue ) && ! isIntN ( Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; MaxBytesToFill = IntValue ; Lex ( ) ; } else { return Error ( ExprLoc , <STR_LIT> ) ; } } getTargetStreamer ( ) . emitFAlign ( <NUM_LIT> , MaxBytesToFill ) ; Lex ( ) ; return false


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveSubsection ( SMLoc L ) { const MCExpr * Subsection = nullptr ; int64_t Res ; assert ( ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) && <STR_LIT> ) ; getParser ( ) . parseExpression ( Subsection ) ; if ( ! Subsection -> evaluateAsAbsolute ( Res ) ) return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; if ( ( Res < <NUM_LIT> ) && ( Res > - <NUM_LIT> ) ) Subsection = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( <NUM_LIT> + Res , getContext ( ) ) , getContext ( ) ) ; getStreamer ( ) . SubSection (


<s> Tokens . emplace_back ( Lexer . getTok ( ) ) ; Lex ( ) ; switch ( Tokens . back ( ) . getKind ( ) ) { case AsmToken :: TokenKind :: Hash : if ( Tokens . size ( ) > <NUM_LIT> ) if ( ( Tokens . end ( ) - <NUM_LIT> ) -> getKind ( ) == AsmToken :: TokenKind :: Plus ) { Tokens . insert ( Tokens . end ( ) - <NUM_LIT> , AsmToken ( AsmToken ::


<s> MCExpr const * Expr = nullptr ; bool Error = parseExpression ( Expr ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , getContext ( ) ) ; if ( ! Error ) Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( getContext ( )


<s> AsmToken const & Token = Lexer . getTok ( ) ; RawString = StringRef ( RawString . data ( ) , Token . getString ( ) . data ( ) - RawString . data ( ) + Token . getString ( ) . size ( ) ) ; Lookahead . push_back ( Token ) ; Lexer . Lex ( ) ; bool Contigious = Lexer . getTok ( ) . getString ( ) . data ( ) == Lookahead . back ( ) . getString ( ) . data ( ) + Lookahead . back ( ) . getString ( ) . size ( ) ; bool Type = Lexer . is ( AsmToken :: Identifier ) || Lexer . is ( AsmToken :: Dot ) || Lexer . is ( AsmToken :: Integer ) || Lexer . is ( AsmToken :: Real ) || Lexer . is ( AsmToken :: Colon ) ; bool Workaround = Lexer . is ( AsmToken :: Colon ) || Lookahead . back ( ) . is ( AsmToken :: Colon ) ; Again = ( Contigious && Type ) || ( Workaround && Type ) ; NeededWorkaround = NeededWorkaround || ( Again && ! ( Contigious && Type ) ) ; } std :: string Collapsed = RawString ; Collapsed . erase ( llvm :: remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef FullString = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = FullString . split ( '.' ) ; unsigned DotReg = matchRegister ( DotSplit . first . lower ( ) ) ; if ( DotReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { if ( DotSplit . second . empty ( ) ) { RegNo = DotReg ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return true ; return false ; } else { RegNo = DotReg ; size_t First = RawString . find ( '.' ) ; StringRef DotString ( RawString . data ( ) + First , RawString . size ( ) - First ) ; Lexer . UnLex ( AsmToken ( AsmToken :: Identifier , DotString ) ) ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return true ; return false ; } } std :: pair < StringRef , StringRef > ColonSplit = StringRef ( FullString ) . split ( ':' ) ; unsigned ColonReg = matchRegister ( ColonSplit . first . lower ( ) ) ; if ( ColonReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { do { Lexer . UnLex ( Lookahead . back ( ) ) ; Lookahead . pop_back ( ) ; } while ( ! Lookahead . empty ( ) && ! Lexer . is ( AsmToken :: Colon ) ) ; RegNo = ColonReg ; EndLoc = Lexer .


<s> static bool previousIsLoop ( OperandVector & Operands , size_t Index ) { return previousEqual ( Operands , Index , <STR_LIT> ) || previousEqual ( Operands , Index , <STR_LIT> ) || previousEqual ( Operands ,

Index , <STR_LIT> ) || previousEqual ( Operands , Index , <STR_LIT> ) || previousEqual ( Operands , Index , <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: RegisterMatchesArch ( unsigned MatchNum ) const { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( MatchNum ) ) if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return false ; return


<s> std :: pair < StringRef , StringRef > HeadTail = String . split ( '.' ) ; if ( ! HeadTail . first . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( getContext ( ) , HeadTail . first , Loc ) ) ; if ( ! HeadTail . second . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( getContext ( ) , String . substr ( HeadTail . first . size ( ) , <NUM_LIT> ) , Loc ) ) ; String = HeadTail . second ; } while ( ! String . empty ( ) ) ; return


<s> case MCK_1 : { int64_t Value ; return Op -> isImm ( ) && Op -> Imm . Val -> evaluateAsAbsolute ( Value ) && Value == <NUM_LIT> ? Match_Success : Match_InvalidOperand ; } } if ( Op -> Kind == <ISA_LIT>Operand :: Token && Kind != InvalidMatchClass ) { StringRef myStringRef = StringRef ( Op -> Tok . Data , Op -> Tok . Length ) ; if ( matchTokenString ( myStringRef . lower ( ) ) == ( MatchClassKind ) Kind ) return Match_Success ; if ( matchTokenString ( myStringRef . upper ( ) ) == ( MatchClassKind ) Kind ) return Match_Success ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Op -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Match_InvalidOperand


<s> Subtarget = & Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const bool Modified = AsmPrinter :: runOnMachineFunction ( Fn ) ; emitXRayTable (


<s> inline static unsigned get<ISA_LIT>RegisterPair ( unsigned Reg , const MCRegisterInfo * RI ) { assert ( <STR_LIT> . contains ( Reg ) ) ; MCSuperRegIterator SR ( Reg , RI , false ) ; unsigned Pair = * SR ; assert ( <STR_LIT> . contains ( Pair )


<s> if ( MBB -> hasAddressTaken ( ) ) return false ; return AsmPrinter :: isBlockOnlyReachableByFallthrough (


<s> if ( MBB -> hasAddressTaken ( ) ) return


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target )


<s> const MachineOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else llvm_unreachable ( <STR_LIT> ) ; if ( Offset . isImm ( ) ) { if ( Offset . getImm ( ) ) O << <STR_LIT> << Offset . getImm ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; return


<s> } else { assert ( Imm . isExpr ( ) && <STR_LIT> ) ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; assert ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) ; MCSymbol * MOSymbol = nullptr ; if ( MO . isGlobal ( ) ) MOSymbol = AP . getSymbol ( MO . getGlobal ( ) ) ; else if ( MO . isCPI ( ) ) MOSymbol = AP . GetCPISymbol ( MO . getIndex ( ) ) ; else if ( MO . isJTI ( ) ) MOSymbol = AP . GetJTISymbol ( MO . getIndex ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; StringRef SymbolName = MOSymbol -> getName ( ) ; std :: string LitaName = <STR_LIT> + SymbolName . str ( ) ; MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; Sym = AP . OutContext . getOrCreateSymbol ( Twine ( LitaName ) ) ; if ( Sym -> isUndefined ( ) ) { OutStreamer . EmitLabel ( Sym ) ; OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Local ) ; OutStreamer . EmitValue ( Imm . getExpr ( ) , AlignSize ) ; OutStreamer . EmitCodeAlignment


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB = <ISA_LIT>MCInstrInfo :: createBundle ( ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB ,


<s> Subtarget = & Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return AsmPrinter :: runOnMachineFunction ( Fn


<s> Subtarget = & Fn . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return AsmPrinter :: runOnMachineFunction


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ; else return


<s> isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> hasAddressTaken ( ) ) { return


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << MO2 .


<s> void <ISA_LIT>AsmPrinter :: printAddrModeBasePlusOffset ( const MachineInstr * MI , int OpNo , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( OpNo ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNo +


<s> assert ( ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) && <STR_LIT> ) ; O << * GetCPISymbol ( MO


<s> assert ( ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) && <STR_LIT> ) ; O << * GetCPISymbol ( MO . getIndex (


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; assert ( ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) && <STR_LIT> ) ; O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; if ( MO . getOffset ( ) != <NUM_LIT> ) { O << <STR_LIT> ; O << MO . getOffset


<s> assert ( ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) && <STR_LIT> ) ; O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; if ( MO . getOffset ( ) != <NUM_LIT> ) { O << <STR_LIT> ; O << MO . getOffset


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; assert ( ( MO . getType ( ) == MachineOperand ::


<s> void <ISA_LIT>AsmPrinter :: printPredicateOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) { Subtarget = & TM . getSubtarget


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf (

* MI ) ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ;


<s> auto PostSled = OutContext . createTempSymbol ( ) ; SledJump -> addOperand ( MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( PostSled , OutContext ) , OutContext ) ) ) ; MCInst SledJumpPacket ; SledJumpPacket . setOpcode ( <STR_LIT> ) ; SledJumpPacket . addOperand ( MCOperand ::


<s> SledJumpPacket . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; SledJumpPacket . addOperand ( MCOperand :: createInst ( SledJump ) ) ; EmitToStreamer ( * OutStreamer , SledJumpPacket ) ; emitNops ( NoopsInSledCount ) ; OutStreamer -> emitLabel ( PostSled ) ; recordSled ( CurSled , MI , Kind


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target (


<s> case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; Register RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return


<s> case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; Register RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo , OS ) ; return false


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand ::


<s> int64_t Value ; if ( Imm . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) { StringRef sectionPrefix ; std :: string ImmString ; StringRef Name ; if ( AlignSize == <NUM_LIT> ) { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( Value ) ; } else { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( static_cast < uint32_t > ( Value ) ) ; } std :: string symbolName = Name . drop_back ( ImmString . size ( ) ) . str ( ) + ImmString ; std :: string sectionName = sectionPrefix . str ( ) + symbolName ; MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( sectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; Sym = AP . OutContext . getOrCreateSymbol ( Twine ( symbolName ) ) ; if ( Sym -> isUndefined ( ) ) { OutStreamer . emitLabel ( Sym ) ; OutStreamer . emitSymbolAttribute ( Sym , MCSA_Global ) ; OutStreamer . emitIntValue ( Value , AlignSize ) ; OutStreamer . emitCodeAlignment ( AlignSize , & STI ) ; } } else { assert ( Imm . isExpr ( ) && <STR_LIT> ) ; const MachineOperand & MO = MI


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { assert ( Subtarget -> usePackets ( ) && <STR_LIT> ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert ( Ok ) ; ( void ) Ok ; if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) ==


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { assert ( Subtarget -> usePackets ( ) && <STR_LIT> ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert ( Ok


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { assert ( Subtarget -> usePackets ( ) && <STR_LIT> ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; }


<s> virtual const char * getPassName ( ) const { return <STR_LIT>


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ; else return


<s> if ( Imm . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) { StringRef sectionPrefix ; std :: string ImmString ; StringRef Name ; if ( AlignSize == <NUM_LIT> ) { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( Value ) ; } else { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( static_cast < uint32_t > ( Value ) ) ; } std :: string symbolName = Name . drop_back ( ImmString . size ( ) ) . str ( ) + ImmString ; std :: string sectionName = sectionPrefix . str ( ) + symbolName ; MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( sectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; Sym = AP . OutContext . getOrCreateSymbol ( Twine ( symbolName ) ) ; if ( Sym -> isUndefined ( ) ) { OutStreamer . emitLabel ( Sym ) ; OutStreamer . emitSymbolAttribute ( Sym , MCSA_Global ) ; OutStreamer . emitIntValue ( Value , AlignSize ) ; OutStreamer . emitCodeAlignment ( AlignSize ) ; } } else { assert ( Imm . isExpr (


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNo ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT>


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & Base = MI -> getOperand ( OpNo ) ; const MachineOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ; if ( Offset . isImm ( ) ) { if ( Offset . getImm ( ) ) O << <STR_LIT>


<s> return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo ,


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo , OS ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; } else { printOp ( MI -> getOperand ( OpNo )


<s> void printBranchOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; } else { printOp ( MI -> getOperand ( OpNo


<s> O << getRegisterName ( MO1 . getReg ( ) ) <<


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << ( int


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << (


<s> int value = MI -> getOperand ( OpNo ) . getImm ( ) ; O << -


<s> void print<ISA_LIT>NegImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { int value = MI -> getOperand ( OpNo )


<s> if ( MO . isReg ( ) ) { printRegister ( MO , false , OS ) ; } else if ( MO . isImm ( )


<s> printRegister ( MO , false , OS ) ; } else if ( MO . isImm ( ) ) { OS << MO . getImm


<s> O << <STR_LIT> ; if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { print<ISA_LIT>ImmOperand ( MI , OpNo , O ) ; } else { printOp ( MI -> getOperand ( OpNo ) , O ) ; } O << <STR_LIT>


<s> void printSymbolLo ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { print<ISA_LIT>ImmOperand ( MI , OpNo , O ) ; } else { printOp ( MI -> getOperand ( OpNo ) , O ) ; } O <<


<s> <ISA_LIT>LowerToMC ( MI , MCI , * this ) ; OutStreamer . EmitInstruction ( MCI


<s> unsigned IgnoreCount = <NUM_LIT> ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { <ISA_LIT>LowerToMC ( & * MII , MCB , * this ) ; } } } else { <ISA_LIT>LowerToMC ( MI , MCB , * this ) ; <ISA_LIT>MCInstrInfo :: padEndloop ( OutStreamer -> getContext (


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) )


<s> case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return


<s> <ISA_LIT>LowerToMC ( MI , MCB , * this ) ; <ISA_LIT>MCInstrInfo :: padEndloop ( MCB ) ; } <ISA_LIT>MCInstrInfo :: tryCompound ( * Subtarget -> getInstrInfo ( ) , OutStreamer -> getContext ( ) , MCB ) ; SmallVector < DuplexCandidate , <NUM_LIT> > possibleDuplexes ; possibleDuplexes = <ISA_LIT>MCInstrInfo :: getDuplexPossibilties ( * Subtarget -> getInstrInfo ( ) , MCB ) ; <ISA_LIT>MCShuffle ( * Subtarget -> getInstrInfo ( ) , * Subtarget , OutStreamer ->

getContext ( ) , MCB , possibleDuplexes ) ;


<s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; MCContext & Ctx = OutStreamer -> getContext ( ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , Ctx , MCB , nullptr ) ; assert ( Ok ) ; ( void


<s> unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo ,


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugValue ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , OutStreamer -> getContext ( ) , MCB , nullptr ) ; assert (


<s> else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; printRegister ( MI -> getOperand ( <NUM_LIT> ) , false , O ) ; O << <STR_LIT> ; printRegister ( MI -> getOperand ( <NUM_LIT> ) , false , O


<s> void print<ISA_LIT>NOneImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) const { O << -


<s> for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; MCContext & Ctx = OutStreamer -> getContext ( ) ; bool Ok = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , Ctx , MCB , nullptr ) ; assert ( Ok ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter (


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & Base = MI -> getOperand ( OpNo ) ; const MachineOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else llvm_unreachable ( <STR_LIT> ) ; if ( Offset . isImm ( ) ) { if ( Offset . getImm ( ) ) O << <STR_LIT> << Offset . getImm ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } return false


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : O << MO . getImm (


<s> int32_t V = cast < MCConstantExpr > ( HE -> getExpr ( ) ) -> getValue ( ) ; auto * NewCE = MCConstantExpr :: create ( V / int32_t ( VectorSize ) , Ctx ) ; auto * NewHE = <ISA_LIT>MCExpr :: create ( NewCE , Ctx ) ; T . addOperand ( MCOperand :: createExpr ( NewHE ) ) ; } return T


<s> if ( Imm . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) { StringRef sectionPrefix ; std :: string ImmString ; StringRef Name ; if ( AlignSize == <NUM_LIT> ) { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( Value ) ; } else { Name = <STR_LIT> ; sectionPrefix = <STR_LIT> ; ImmString = utohexstr ( static_cast < uint32_t > ( Value ) ) ; } std :: string symbolName = Name . drop_back ( ImmString . size ( ) ) . str ( ) + ImmString ; std :: string sectionName = sectionPrefix . str ( ) + symbolName ; MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( sectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; Sym = AP . OutContext . getOrCreateSymbol ( Twine ( symbolName ) ) ; if ( Sym -> isUndefined ( ) ) { OutStreamer . EmitLabel ( Sym ) ; OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; OutStreamer . EmitIntValue ( Value , AlignSize ) ; OutStreamer . EmitCodeAlignment ( AlignSize ) ; } } else


<s> unsigned Opc = MI . getOpcode ( ) ; BitVector T ( Bits . size ( ) ) ; bool GotBits = HBS :: getUsedBits ( Opc , OpN , T , Begin , HII ) ; unsigned LB , LE ; if ( isLossyShiftLeft ( MI , OpN , LB , LE ) || isLossyShiftRight ( MI , OpN , LB , LE ) ) { assert ( MI . getOperand ( OpN ) . isReg ( ) ) ; BitTracker :: RegisterRef RR = MI . getOperand ( OpN ) ; const TargetRegisterClass * RC = HBS :: getFinalVRegClass ( RR , MRI ) ; uint16_t Width = HRI . getRegSizeInBits ( * RC ) ; if ( ! GotBits ) T . set (


<s> bool CopyGeneration :: findMatch ( const BitTracker :: RegisterRef & Inp , BitTracker :: RegisterRef & Out , const RegisterSet & AVs ) { if ( ! BT . has ( Inp . Reg ) ) return false ; const BitTracker :: RegisterCell & InpRC = BT . lookup ( Inp . Reg ) ; auto * FRC = HBS :: getFinalVRegClass ( Inp , MRI ) ; unsigned B , W ; if ( ! HBS :: getSubregMask ( Inp , B , W , MRI ) ) return false ; for ( unsigned R = AVs . find_first ( ) ; R ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) || Forbidden [ R ] ) continue ; const BitTracker :: RegisterCell & RC = BT . lookup ( R ) ; unsigned RW = RC . width ( ) ; if ( W == RW ) { if ( FRC != MRI . getRegClass ( R ) ) continue ; if ( ! HBS :: isTransparentCopy ( R , Inp , MRI ) ) continue ; if ( ! HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) continue ; Out . Reg


<s> if ( V . Type != BitTracker :: BitValue :: Ref ) break ; if ( V . RefI . Reg != SrcR || V . RefI . Pos != P + I ) break ; } if ( I != Z ) continue ; if ( MaxBitSplit . getNumOccurrences ( ) ) CountBitSplit ++ ; MachineInstr * DefS = MRI . getVRegDef ( S ) ; assert ( DefS != nullptr ) ; DebugLoc DL = DefS -> getDebugLoc ( ) ; MachineBasicBlock & B = * DefS -> getParent ( ) ; auto At = DefS -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( DefS ) ; if ( MRI . getRegClass ( SrcR ) -> getID ( ) == <STR_LIT> ) SrcSR = ( std :: min ( Pos , P ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ! validateReg ( { SrcR , SrcSR } , <STR_LIT> , <NUM_LIT> ) ) continue ; unsigned ImmOp = Pos <= P ? W - Z : Z ; unsigned NewR = <NUM_LIT> ; for ( MachineInstr * In : NewMIs ) { if ( In -> getOpcode ( ) != <STR_LIT> ) continue ; MachineOperand & Op1 = In -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getReg ( ) != SrcR || Op1 . getSubReg ( ) != SrcSR ) continue ; if ( In -> getOperand ( <NUM_LIT> ) . getImm ( ) != ImmOp ) continue ; MachineOperand & Op0 = In -> getOperand ( <NUM_LIT> ) ; MachineInstr * DefI = MRI . getVRegDef ( Op0 . getReg ( ) ) ; assert ( DefI != nullptr ) ; if ( ! MDT . dominates ( DefI , & * At ) ) continue ; assert ( Op0 . getSubReg ( ) == <NUM_LIT> ) ; NewR = Op0 . getReg ( ) ; break ; } if ( ! NewR ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto NewBS = BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( SrcR , <NUM_LIT> , SrcSR ) . addImm ( ImmOp ) ; NewMIs . push_back ( NewBS ) ; } if ( Pos <= P


<s> unsigned Opc = MI -> getOpcode ( ) ; unsigned COpc = getCombineOpcode ( H . Low , L . Low ) ; if ( COpc == Opc ) return false ; if ( ! validateReg ( H , COpc , <NUM_LIT> ) || ! validateReg ( L , COpc , <NUM_LIT> ) ) return false ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; BuildMI ( B , At , DL , HII . get ( COpc ) , NewR ) . addReg ( H . Reg , <NUM_LIT> , H . Sub ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ; return


<s> RegHalf L , H ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! matchHalf ( RD . Reg , RC , <NUM_LIT> , H ) ) return false ; if ( L . Reg == H . Reg && L . Sub == H . Sub && ! H . Low && L . Low ) return false ; unsigned Opc = MI -> getOpcode ( ) ; unsigned COpc = getCombineOpcode ( H . Low , L . Low ) ; if ( COpc == Opc ) return false ; if ( ! validateReg ( H , COpc , <NUM_LIT> ) || ! validateReg ( L , COpc , <NUM_LIT> ) ) return false ; MachineBasicBlock & B = * MI


<s> RegHalf L ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! HBS :: isZero ( RC , <NUM_LIT> , <NUM_LIT> ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = <NUM_LIT> ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; if ( L . Low && Opc != <STR_LIT> ) { if ( validateReg ( L , <STR_LIT> , <NUM_LIT> ) ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; } } else if ( ! L . Low && Opc != <STR_LIT> ) { if ( validateReg ( L , <STR_LIT> , <NUM_LIT> ) ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) . addImm ( <NUM_LIT> ) ; } } if ( NewR == <NUM_LIT> ) return false ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT>


<s> unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { int32_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return false ; } if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) return false ; unsigned W = RC . width ( ) ; while ( W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( <NUM_LIT> ) ) W -- ; if ( W == <NUM_LIT> || W == RC . width ( ) ) return false ; unsigned NewOpc = ( W == <NUM_LIT> ) ? <STR_LIT> : ( W == <NUM_LIT> ) ? <STR_LIT> : ( W < <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; if ( ! validateReg ( RS , NewOpc , <NUM_LIT> ) ) continue ; unsigned NewR = MRI . createVirtualRegister


<s> bool BitSimplification :: genExtractLow ( MachineInstr * MI , BitTracker :: RegisterRef RD , const BitTracker :: RegisterCell & RC ) { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { int32_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return false ; } if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) return false ; unsigned W = RC . width ( ) ; while ( W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( <NUM_LIT> ) ) W -- ; if ( W == <NUM_LIT> || W == RC . width ( ) ) return false ; unsigned NewOpc = ( W == <NUM_LIT> ) ? <STR_LIT> : ( W == <NUM_LIT> ) ? <STR_LIT> : ( W < <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; if ( ! validateReg ( RS , NewOpc , <NUM_LIT> ) ) continue ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; auto MIB = BuildMI ( B , At , DL , HII . get ( NewOpc ) , NewR ) . addReg ( RS . Reg , <NUM_LIT> , RS . Sub ) ; if ( NewOpc == <STR_LIT> ) MIB . addImm ( ( <NUM_LIT> << W ) - <NUM_LIT> ) ; else if ( NewOpc == <STR_LIT> ) MIB . addImm ( W ) . addImm ( <NUM_LIT> ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ; return true


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( Rs . Reg

, <NUM_LIT> , Rs . Sub ) . addReg ( Rt . Reg , <NUM_LIT> , Rt . Sub ) ;


<s> break ; default : return false ; } if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; MachineOperand & OffOp = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OffOp . isImm ( ) ) return false ; int64_t Off = OffOp . getImm ( ) ; if ( ! isUIntN ( <NUM_LIT> + Align , Off ) || ( Off & ( ( <NUM_LIT> << Align ) - <NUM_LIT> ) ) ) return false ; BitTracker :: RegisterRef RS = MI -> getOperand ( <NUM_LIT> ) ; if ( ! BT . has ( RS . Reg ) ) return false ; const BitTracker :: RegisterCell & RC = BT . lookup ( RS . Reg ) ; uint64_t U ; if ( ! HBS :: getConst ( RC , <NUM_LIT> , RC . width ( ) , U ) ) return false ; int V ; switch ( Opc ) { case <STR_LIT> : V = int8_t ( U ) ; break ; case <STR_LIT> : V = int16_t ( U ) ; break ; case <STR_LIT> : V = int32_t ( U ) ; break ; } if ( ! isInt < <NUM_LIT> > ( V ) ) return false ; MI -> RemoveOperand ( <NUM_LIT> ) ; switch ( Opc ) { case


<s> StringRef getPassName ( ) const override { return <STR_LIT>


<s> Begin = <NUM_LIT> ; Width = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( * RC ) ; return true ; } Begin = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( * RC ) / <NUM_LIT> ; if ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) Begin = Width ; break ; default : return


<s> bool <ISA_LIT>BitSimplify :: hasTiedUse ( unsigned Reg , MachineRegisterInfo & MRI , unsigned NewSub ) { if ( ! PreserveTiedOps ) return false ; return llvm :: any_of ( MRI . use_operands ( Reg ) , [

NewSub ] ( const MachineOperand & Op ) -> bool {


<s> <ISA_LIT>BitSimplify ( ) : MachineFunctionPass ( ID ) , MDT ( nullptr ) { initialize<ISA_LIT>BitSimplifyPass ( * PassRegistry :: getPassRegistry


<s> <ISA_LIT>LoopRescheduling ( ) : MachineFunctionPass ( ID ) , HII ( nullptr ) , HRI ( nullptr ) , MRI ( nullptr ) , BTP ( nullptr ) { initialize<ISA_LIT>LoopReschedulingPass ( * PassRegistry :: getPassRegistry


<s> unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case


<s> if ( Pos + <NUM_LIT> > SC . width ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { const BitTracker :: BitValue & RV = RC [ i + B ] ; if ( RV . Type == BitTracker :: BitValue :: Ref ) { if ( RV . RefI . Reg != Reg ) return false ; if ( RV . RefI . Pos != i + Pos ) return false ; continue ; } if ( RC [ i + B ] != SC [ i + Pos ] ) return false ; } unsigned Sub = <NUM_LIT> ; switch ( Pos ) { case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = false ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = false ; break ; default : return false ; } RH . Reg = Reg ; RH . Sub = Sub ; RH . Low = Low ; if ( ! HBS :: getFinalVRegClass ( RH , MRI ) ) RH . Sub


<s> RegMap . insert ( std :: make_pair ( G . Inp . Reg , PhiR ) ) ; for ( unsigned i = G . Ins . size ( ) ; i > <NUM_LIT> ; -- i ) { const MachineInstr * SI = G . Ins [ i - <NUM_LIT> ] ; unsigned DR = getDefReg ( SI ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; unsigned NewDR = MRI -> createVirtualRegister ( RC ) ; DebugLoc DL = SI -> getDebugLoc ( ) ; auto MIB = BuildMI ( LB , At , DL , HII -> get ( SI -> getOpcode ( ) ) , NewDR ) ; for ( unsigned j = <NUM_LIT> , m = SI -> getNumOperands ( ) ; j < m ; ++ j ) { const MachineOperand & Op = SI -> getOperand ( j ) ; if ( ! Op . isReg ( ) ) { MIB . add ( Op ) ; continue ; } if ( ! Op . isUse ( ) ) continue ; unsigned UseR = RegMap [ Op . getReg ( ) ] ; MIB . addReg ( UseR , <NUM_LIT> , Op . getSubReg


<s> auto & HRI = static_cast < const <ISA_LIT>RegisterInfo & > ( * MRI . getTargetRegisterInfo ( ) ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; assert ( ( Sub1 == SubLo && Sub2 == SubHi ) || ( Sub1 == SubHi && Sub2 == SubLo ) ) ; if ( Sub1 == SubLo && Sub2


<s> case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : { BitTracker :: RegisterRef RS = MI . getOperand ( <NUM_LIT> ) ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) break ; if ( RS . Sub != <NUM_LIT> ) Changed = HBS :: replaceRegWithSub ( RD . Reg , RS . Reg , RS . Sub , MRI ) ; else Changed = HBS :: replaceReg ( RD . Reg , RS . Reg , MRI ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { BitTracker :: RegisterRef SL , SH ; if ( HBS :: parseRegSequence ( MI , SL , SH , MRI ) ) { const TargetRegisterClass * RC = MRI . getRegClass ( RD . Reg ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; Changed = HBS :: replaceSubWithSub ( RD . Reg , SubLo , SL . Reg , SL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , SubHi , SH . Reg , SH . Sub , MRI ) ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * RC = MRI . getRegClass ( RD . Reg ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ; BitTracker :: RegisterRef RH = MI . getOperand ( <NUM_LIT> ) , RL = MI . getOperand ( <NUM_LIT> ) ; Changed = HBS :: replaceSubWithSub ( RD . Reg , SubLo , RL . Reg , RL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , SubHi , RH . Reg , RH . Sub , MRI ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned SrcX = ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Sub = ( Opc == <STR_LIT>


<s> if ( hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I !=


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( OldR ) || ! TargetRegisterInfo :: isVirtualRegister ( NewR ) ) return false ; if ( OldSR != NewSR && hasTiedUse ( OldR , MRI , NewSR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I =


<s> for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) ) continue ; if ( ! MI -> isPHI ( ) && ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! isDead ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead )


<s> SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! isDead ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned i = <NUM_LIT> , n = Regs . size ( ) ; i != n ; ++ i ) MRI . markUsesInDebugValueAsUndef ( Regs [ i ] ) ; Changed = true ; } return Changed


<s> for ( unsigned R = AVs . find_first ( ) ; R != <NUM_LIT> ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( R ) ; unsigned SW = SC . width ( ) ; if ( SW < RW || ( SW % RW ) != <NUM_LIT> ) continue ; unsigned Off = <NUM_LIT> ; while ( Off <= SW - Len ) { unsigned OE = ( Off + Len ) / RW ; if ( OE != Off / RW ) { Off = OE * RW ; continue ; } if ( HBS :: isEqual ( RC , <NUM_LIT> , SC , Off , Len ) ) break ; ++ Off ; } if ( Off > SW - Len ) continue ; unsigned ExtOpc = <NUM_LIT> ; if ( Off == <NUM_LIT> ) { if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ; else if ( Len == <NUM_LIT> ) ExtOpc = Signed ? <STR_LIT> : <STR_LIT> ; else if ( Len < <NUM_LIT> && ! Signed ) ExtOpc = <STR_LIT> ; } if ( ExtOpc == <NUM_LIT> ) { ExtOpc = Signed ? ( RW == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : ( RW == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } unsigned SR = <NUM_LIT> ; if ( RW != SW && RW * <NUM_LIT> != SW ) continue ; if ( RW != SW ) SR = ( Off / RW == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Off = Off % RW ; if ( ! validateReg ( { R , SR } , ExtOpc , <NUM_LIT> ) ) continue ; if ( MI -> getOpcode ( ) == ExtOpc ) { const MachineOperand & SrcOp = MI -> getOperand ( <NUM_LIT> ) ; if ( SrcOp . getReg ( ) == R ) continue ; } DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; auto MIB = BuildMI ( B , At , DL , HII . get ( ExtOpc ) , NewR ) . addReg ( R , <NUM_LIT> , SR ) ; switch ( ExtOpc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : MIB . addImm ( ( <NUM_LIT> <<


<s> auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; const BitTracker :: BitValue & V = SC [ F + BN ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg != RS . Reg ) { const TargetRegisterClass * TC = MRI . getRegClass ( V . RefI . Reg ) ; unsigned P = std :: numeric_limits < unsigned > :: max ( ) ; BitTracker :: RegisterRef RR ( V . RefI . Reg , <NUM_LIT> ) ; if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; RR . Sub = <STR_LIT> ; if ( P >= <NUM_LIT> ) { P -= <NUM_LIT> ; RR . Sub = <STR_LIT> ; } } else if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; } if ( P != std :: numeric_limits < unsigned > :: max ( ) ) { unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( RR . Reg , <NUM_LIT> , RR . Sub ) . addImm ( P ) ; HBS :: replaceReg ( RD . Reg , NewR , MRI ) ; BT . put ( NewR , RC ) ; return true ; } } else if ( V . is ( <NUM_LIT> ) || V . is


<s> auto * OpRC = HII . getRegClass ( HII . get ( Opc ) , OpNum , & HRI , MF ) ; auto * RRC = HBS :: getFinalVRegClass ( R , MRI ) ; return OpRC -> hasSubClassEq (


<s> bool Changed = false ; if ( T . TopDown ) Changed = T . processBlock ( B , AVs ) ; RegisterSet Defs ; for ( auto & I : B ) getInstrDefs ( I , Defs ) ; RegisterSet NewAVs


<s> bool RedundantInstrElimination :: computeUsedBits ( const MachineInstr & MI , unsigned OpN , BitVector & Bits , uint16_t Begin ) { unsigned Opc = MI . getOpcode ( ) ; BitVector T ( Bits . size ( ) ) ; bool GotBits = HBS :: getUsedBits ( Opc , OpN , T , Begin , HII ) ; unsigned LB , LE ; if ( isLossyShiftLeft ( MI , OpN , LB , LE ) || isLossyShiftRight ( MI , OpN , LB , LE ) ) { assert ( MI . getOperand ( OpN ) . isReg ( ) ) ; BitTracker :: RegisterRef RR = MI . getOperand ( OpN ) ; const TargetRegisterClass * RC = HBS :: getFinalVRegClass ( RR , MRI ) ; uint16_t Width = RC -> getSize ( ) * <NUM_LIT> ; if ( ! GotBits ) T . set


<s> bool empty ( ) const { return ! BitVector :: any


<s> void ensure ( unsigned Idx ) { if ( size ( ) <= Idx ) resize ( std :: max ( Idx + <NUM_LIT>


<s> bool CopyGeneration :: findMatch ( const BitTracker :: RegisterRef & Inp , BitTracker :: RegisterRef & Out , const RegisterSet & AVs ) { if ( ! BT . has ( Inp . Reg ) ) return false ; const BitTracker :: RegisterCell & InpRC = BT . lookup ( Inp . Reg ) ; unsigned B , W ; if ( ! HBS :: getSubregMask ( Inp , B , W , MRI ) ) return false ; for ( unsigned R = AVs . find_first ( ) ; R ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) || ! HBS :: isTransparentCopy ( R , Inp , MRI ) ) continue ; const BitTracker :: RegisterCell & RC = BT . lookup ( R ) ; unsigned RW = RC . width ( ) ; if ( W == RW ) { if ( MRI . getRegClass ( Inp . Reg ) != MRI . getRegClass ( R ) ) continue ; if ( ! HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) continue ; Out . Reg = R ; Out . Sub = <NUM_LIT> ; return true ; } if ( W * <NUM_LIT> != RW ) continue ; if ( MRI . getRegClass ( R ) != & <STR_LIT> ) continue ; if ( HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) Out . Sub = <STR_LIT> ; else if ( HBS :: isEqual ( InpRC , B , RC , W ,


<s> unsigned find_first ( ) const { int First = BitVector :: find_first ( ) ; if ( First <


<s> int Next = BitVector :: find_next ( v2x ( Prev ) ) ; if ( Next < <NUM_LIT> ) return <NUM_LIT> ; return x2v (


<s> if ( COpc == Opc ) return false ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( COpc ) , NewR ) . addReg ( H . Reg , <NUM_LIT> , H . Sub ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ; return


<s> bool BitSimplification :: genExtractHalf ( MachineInstr * MI , BitTracker :: RegisterRef RD , const BitTracker :: RegisterCell & RC ) { RegHalf L ; if ( ! matchHalf ( RD . Reg , RC , <NUM_LIT> , L ) || ! HBS :: isZero ( RC , <NUM_LIT> , <NUM_LIT> ) ) return false ; unsigned Opc = MI -> getOpcode ( ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = <NUM_LIT> ; if ( L . Low && Opc != <STR_LIT> ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) ; } else if ( ! L . Low && Opc != <STR_LIT> ) { NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( L . Reg , <NUM_LIT> , L . Sub ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } if ( NewR == <NUM_LIT> ) return false ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT>


<s> BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( Rs . Reg , <NUM_LIT> , Rs . Sub ) . addReg ( Rt . Reg , <NUM_LIT> , Rt . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ; return true


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( B , MI , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( Rs . Reg , <NUM_LIT> , Rs . Sub ) . addReg ( Rt . Reg , <NUM_LIT> , Rt . Sub ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , RC


<s> if ( Opc != <STR_LIT> ) return false ; MachineOperand & ValOp = MI -> getOperand ( <NUM_LIT> ) ; BitTracker :: RegisterRef RS = ValOp ; if ( ! BT . has ( RS . Reg ) ) return false ; const BitTracker :: RegisterCell & RC = BT . lookup ( RS . Reg ) ; RegHalf H ; if ( ! matchHalf ( <NUM_LIT> , RC , <NUM_LIT> , H ) ) return false ; if ( H . Low ) return false ; MI -> setDesc ( HII .


<s> BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , Reg ) . addImm ( C ) ; return Reg ; } unsigned Lo = Lo_32 ( C ) , Hi = Hi_32 ( C ) ; if ( isInt < <NUM_LIT> > ( Lo ) || isInt < <NUM_LIT> > ( Hi ) ) { unsigned Opc = isInt < <NUM_LIT> > ( Lo ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , At , DL , HII . get ( Opc ) , Reg ) . addImm ( int32_t ( Hi ) ) . addImm ( int32_t ( Lo ) ) ; return Reg ; } BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , Reg ) . addImm ( C ) ; return Reg ; } if ( RC == & <STR_LIT> ) { unsigned Opc ; if ( C == <NUM_LIT> ) Opc = <STR_LIT> ; else if ( ( C & <NUM_LIT> ) == <NUM_LIT> ) Opc = <STR_LIT> ; else return <NUM_LIT> ; BuildMI ( B , At , DL , HII . get ( Opc ) , Reg ) ; return Reg


<s> unsigned BitSimplification :: getCombineOpcode ( bool HLow ,


<s> assert ( B < RC . width ( ) && B + W <= RC . width ( ) ) ; int64_t T = <NUM_LIT> ; for ( uint16_t i = B + W ; i > B ; -- i ) { const BitTracker :: BitValue & BV = RC [ i - <NUM_LIT> ] ; T <<= <NUM_LIT> ; if ( BV . is ( <NUM_LIT> ) ) T |= <NUM_LIT> ; else if ( ! BV . is ( <NUM_LIT> ) ) return false ; } U = T


<s> int64_t T = <NUM_LIT> ; for ( uint16_t i = B + W ; i > B ; -- i ) { const BitTracker :: BitValue & BV = RC [ i - <NUM_LIT> ] ; T <<= <NUM_LIT> ; if ( BV . is ( <NUM_LIT> ) ) T |= <NUM_LIT> ; else if ( ! BV . is ( <NUM_LIT> ) ) return false ; } U = T


<s> unsigned <ISA_LIT>LoopRescheduling :: getDefReg ( const MachineInstr * MI ) { RegisterSet Defs ; HBS :: getInstrDefs ( * MI , Defs ) ; if ( Defs . count ( ) != <NUM_LIT> ) return <NUM_LIT> ; return Defs .


<s> for ( auto & Op : MI . operands ( ) ) { if ( ! Op . isReg ( ) || !


<s> unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; Uses . insert ( R


<s> bool <ISA_LIT>BitSimplify :: getSubregMask ( const BitTracker :: RegisterRef & RR , unsigned & Begin , unsigned & Width , MachineRegisterInfo & MRI ) { const TargetRegisterClass * RC = MRI . getRegClass ( RR . Reg ) ; if ( RC == & <STR_LIT> ) { assert ( RR . Sub == <NUM_LIT> ) ; Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } if ( RC == & <STR_LIT> ) { if ( RR . Sub == <NUM_LIT> ) { Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } assert ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) ; Width = <NUM_LIT> ; Begin = ( RR . Sub == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return true ; } return


<s> case A4_cmphgti : case A4_cmphgtui : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_asrh : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } break ; case A4_cmpbeq : case A4_cmpbgt : case A4_cmpbgtu : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A4_cmpheq : case A4_cmphgt : case A4_cmphgtu : case A2_addh_h16_ll : case A2_addh_h16_sat_ll : case A2_addh_l16_ll : case A2_addh_l16_sat_ll : case A2_combine_ll : case A2_subh_h16_ll : case A2_subh_h16_sat_ll : case A2_subh_l16_ll : case A2_subh_l16_sat_ll : case M2_mpy_acc_ll_s0 : case M2_mpy_acc_ll_s1 : case M2_mpy_acc_sat_ll_s0 : case M2_mpy_acc_sat_ll_s1 : case M2_mpy_ll_s0 : case M2_mpy_ll_s1 : case M2_mpy_nac_ll_s0 : case M2_mpy_nac_ll_s1 : case M2_mpy_nac_sat_ll_s0 : case M2_mpy_nac_sat_ll_s1 : case M2_mpy_rnd_ll_s0 : case M2_mpy_rnd_ll_s1 : case M2_mpy_sat_ll_s0 : case M2_mpy_sat_ll_s1 : case M2_mpy_sat_rnd_ll_s0 : case M2_mpy_sat_rnd_ll_s1 : case M2_mpyd_acc_ll_s0 : case M2_mpyd_acc_ll_s1 : case M2_mpyd_ll_s0 : case M2_mpyd_ll_s1 : case M2_mpyd_nac_ll_s0 : case M2_mpyd_nac_ll_s1 : case M2_mpyd_rnd_ll_s0 : case M2_mpyd_rnd_ll_s1 : case M2_mpyu_acc_ll_s0 : case M2_mpyu_acc_ll_s1 : case M2_mpyu_ll_s0 : case M2_mpyu_ll_s1 : case M2_mpyu_nac_ll_s0 : case M2_mpyu_nac_ll_s1 : case M2_mpyud_acc_ll_s0 : case M2_mpyud_acc_ll_s1 : case M2_mpyud_ll_s0 : case M2_mpyud_ll_s1 : case M2_mpyud_nac_ll_s0 : case M2_mpyud_nac_ll_s1 : if ( OpN == <NUM_LIT> || OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_lh : case A2_addh_h16_sat_lh : case A2_combine_lh : case A2_subh_h16_lh : case A2_subh_h16_sat_lh : case M2_mpy_acc_lh_s0 : case M2_mpy_acc_lh_s1 : case M2_mpy_acc_sat_lh_s0 : case M2_mpy_acc_sat_lh_s1 : case M2_mpy_lh_s0 : case M2_mpy_lh_s1 : case M2_mpy_nac_lh_s0 : case M2_mpy_nac_lh_s1 : case M2_mpy_nac_sat_lh_s0 : case M2_mpy_nac_sat_lh_s1 : case M2_mpy_rnd_lh_s0 : case M2_mpy_rnd_lh_s1 : case M2_mpy_sat_lh_s0 : case M2_mpy_sat_lh_s1 : case M2_mpy_sat_rnd_lh_s0 : case M2_mpy_sat_rnd_lh_s1 : case M2_mpyd_acc_lh_s0 : case M2_mpyd_acc_lh_s1 : case M2_mpyd_lh_s0 : case M2_mpyd_lh_s1 : case M2_mpyd_nac_lh_s0 : case M2_mpyd_nac_lh_s1 : case M2_mpyd_rnd_lh_s0 : case M2_mpyd_rnd_lh_s1 : case M2_mpyu_acc_lh_s0 : case M2_mpyu_acc_lh_s1 : case M2_mpyu_lh_s0 : case M2_mpyu_lh_s1 : case M2_mpyu_nac_lh_s0 : case M2_mpyu_nac_lh_s1 : case M2_mpyud_acc_lh_s0 : case M2_mpyud_acc_lh_s1 : case M2_mpyud_lh_s0 : case M2_mpyud_lh_s1 : case M2_mpyud_nac_lh_s0 : case M2_mpyud_nac_lh_s1 : case A2_addh_l16_hl : case A2_addh_l16_sat_hl : case A2_subh_l16_hl : case A2_subh_l16_sat_hl : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hl : case A2_addh_h16_sat_hl : case A2_combine_hl : case A2_subh_h16_hl : case A2_subh_h16_sat_hl : case M2_mpy_acc_hl_s0 : case M2_mpy_acc_hl_s1 : case M2_mpy_acc_sat_hl_s0 : case M2_mpy_acc_sat_hl_s1 : case M2_mpy_hl_s0 : case M2_mpy_hl_s1


<s> case A2_addh_l16_hl : case A2_addh_l16_sat_hl : case A2_subh_l16_hl : case A2_subh_l16_sat_hl : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hl : case A2_addh_h16_sat_hl : case A2_combine_hl : case A2_subh_h16_hl : case A2_subh_h16_sat_hl : case M2_mpy_acc_hl_s0 : case M2_mpy_acc_hl_s1 : case M2_mpy_acc_sat_hl_s0 : case M2_mpy_acc_sat_hl_s1 : case M2_mpy_hl_s0 : case M2_mpy_hl_s1 : case M2_mpy_nac_hl_s0 : case M2_mpy_nac_hl_s1 : case M2_mpy_nac_sat_hl_s0 : case M2_mpy_nac_sat_hl_s1 : case M2_mpy_rnd_hl_s0 : case M2_mpy_rnd_hl_s1 : case M2_mpy_sat_hl_s0 : case M2_mpy_sat_hl_s1 : case M2_mpy_sat_rnd_hl_s0 : case M2_mpy_sat_rnd_hl_s1 : case M2_mpyd_acc_hl_s0 : case M2_mpyd_acc_hl_s1 : case M2_mpyd_hl_s0 : case M2_mpyd_hl_s1 : case M2_mpyd_nac_hl_s0 : case M2_mpyd_nac_hl_s1 : case M2_mpyd_rnd_hl_s0 : case M2_mpyd_rnd_hl_s1 : case M2_mpyu_acc_hl_s0 : case M2_mpyu_acc_hl_s1 : case M2_mpyu_hl_s0 : case M2_mpyu_hl_s1 : case M2_mpyu_nac_hl_s0 : case M2_mpyu_nac_hl_s1 : case M2_mpyud_acc_hl_s0 : case M2_mpyud_acc_hl_s1 : case M2_mpyud_hl_s0 : case M2_mpyud_hl_s1 : case M2_mpyud_nac_hl_s0 : case M2_mpyud_nac_hl_s1 : if ( OpN == <NUM_LIT> ) { Bits . set ( Begin + <NUM_LIT> , Begin + <NUM_LIT> ) ; return true ; } if ( OpN == <NUM_LIT> ) { Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; } break ; case A2_addh_h16_hh : case A2_addh_h16_sat_hh : case A2_combine_hh : case A2_subh_h16_hh : case A2_subh_h16_sat_hh : case M2_mpy_acc_hh_s0 : case M2_mpy_acc_hh_s1 : case M2_mpy_acc_sat_hh_s0 : case M2_mpy_acc_sat_hh_s1 : case M2_mpy_hh_s0 : case M2_mpy_hh_s1 : case M2_mpy_nac_hh_s0 : case M2_mpy_nac_hh_s1 : case M2_mpy_nac_sat_hh_s0 : case M2_mpy_nac_sat_hh_s1 : case M2_mpy_rnd_hh_s0 : case M2_mpy_rnd_hh_s1 : case M2_mpy_sat_hh_s0 : case M2_mpy_sat_hh_s1 : case M2_mpy_sat_rnd_hh_s0 : case M2_mpy_sat_rnd_hh_s1 : case M2_mpyd_acc_hh_s0 : case M2_mpyd_acc_hh_s1 : case M2_mpyd_hh_s0 : case M2_mpyd_hh_s1 : case M2_mpyd_nac_hh_s0 : case M2_mpyd_nac_hh_s1 : case M2_mpyd_rnd_hh_s0 : case M2_mpyd_rnd_hh_s1 : case M2_mpyu_acc_hh_s0 : case M2_mpyu_acc_hh_s1 : case M2_mpyu_hh_s0 : case M2_mpyu_hh_s1 : case M2_mpyu_nac_hh_s0 : case M2_mpyu_nac_hh_s1 : case M2_mpyud_acc_hh_s0 : case M2_mpyud_acc_hh_s1 : case M2_mpyud_hh_s0 : case M2_mpyud_hh_s1 : case M2_mpyud_nac_hh_s0 : case M2_mpyud_nac_hh_s1 : if ( OpN == <NUM_LIT> || OpN ==


<s> using namespace <ISA_LIT> ; switch ( Opc ) { case S2_storerb_io : case S2_storerbnew_io : case S2_pstorerbt_io : case S2_pstorerbf_io : case S4_pstorerbtnew_io : case S4_pstorerbfnew_io : case S2_pstorerbnewt_io : case S2_pstorerbnewf_io : case S4_pstorerbnewtnew_io : case S4_pstorerbnewfnew_io : case S2_storerb_pi : case S2_storerbnew_pi : case S2_pstorerbt_pi : case S2_pstorerbf_pi : case S2_pstorerbtnew_pi : case S2_pstorerbfnew_pi : case S2_pstorerbnewt_pi : case S2_pstorerbnewf_pi : case S2_pstorerbnewtnew_pi : case S2_pstorerbnewfnew_pi : case S4_storerb_ap : case S4_storerbnew_ap : case S2_storerb_pr : case S2_storerbnew_pr : case S4_storerb_ur : case S4_storerbnew_ur : case S2_storerb_pbr : case S2_storerbnew_pbr : case S2_storerb_pci : case S2_storerbnew_pci : case S2_storerb_pcr : case S2_storerbnew_pcr : case S4_storerb_rr : case S4_storerbnew_rr : case S4_pstorerbt_rr : case S4_pstorerbf_rr : case S4_pstorerbtnew_rr : case S4_pstorerbfnew_rr : case S4_pstorerbnewt_rr : case S4_pstorerbnewf_rr : case S4_pstorerbnewtnew_rr : case S4_pstorerbnewfnew_rr : case S2_storerbgp : case S2_storerbnewgp : case S4_pstorerbt_abs : case S4_pstorerbf_abs : case S4_pstorerbtnew_abs : case S4_pstorerbfnew_abs : case S4_pstorerbnewt_abs : case S4_pstorerbnewf_abs : case S4_pstorerbnewtnew_abs : case S4_pstorerbnewfnew_abs : Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; case S2_storerh_io : case S2_storerhnew_io : case S2_pstorerht_io : case S2_pstorerhf_io : case S4_pstorerhtnew_io : case S4_pstorerhfnew_io : case S2_pstorerhnewt_io : case S2_pstorerhnewf_io : case S4_pstorerhnewtnew_io : case S4_pstorerhnewfnew_io : case S2_storerh_pi : case S2_storerhnew_pi : case S2_pstorerht_pi : case S2_pstorerhf_pi : case S2_pstorerhtnew_pi : case S2_pstorerhfnew_pi : case S2_pstorerhnewt_pi : case S2_pstorerhnewf_pi : case S2_pstorerhnewtnew_pi : case S2_pstorerhnewfnew_pi : case S4_storerh_ap : case S4_storerhnew_ap : case S2_storerh_pr : case S2_storerhnew_pr : case S4_storerh_ur : case S4_storerhnew_ur : case S2_storerh_pbr : case S2_storerhnew_pbr : case S2_storerh_pci : case S2_storerhnew_pci : case S2_storerh_pcr : case S2_storerhnew_pcr : case S4_storerh_rr : case S4_pstorerht_rr : case S4_pstorerhf_rr : case S4_pstorerhtnew_rr : case S4_pstorerhfnew_rr : case S4_storerhnew_rr : case S4_pstorerhnewt_rr : case S4_pstorerhnewf_rr : case S4_pstorerhnewtnew_rr : case S4_pstorerhnewfnew_rr : case S2_storerhgp : case S2_storerhnewgp : case S4_pstorerht_abs : case S4_pstorerhf_abs : case S4_pstorerhtnew_abs : case S4_pstorerhfnew_abs : case S4_pstorerhnewt_abs : case S4_pstorerhnewf_abs : case S4_pstorerhnewtnew_abs : case S4_pstorerhnewfnew_abs : Bits . set ( Begin , Begin + <NUM_LIT> ) ; return true ; case S2_storerf_io : case S2_pstorerft_io : case S2_pstorerff_io : case S4_pstorerftnew_io : case S4_pstorerffnew_io : case S2_storerf_pi : case S2_pstorerft_pi : case S2_pstorerff_pi : case S2_pstorerftnew_pi : case S2_pstorerffnew_pi : case S4_storerf_ap : case S2_storerf_pr : case S4_storerf_ur : case S2_storerf_pbr : case S2_storerf_pci : case S2_storerf_pcr : case S4_storerf_rr : case S4_pstorerft_rr : case S4_pstorerff_rr : case S4_pstorerftnew_rr : case S4_pstorerffnew_rr


<s> bool has ( unsigned R ) const { unsigned Idx = v2x (


<s> initialize<ISA_LIT>BitSimplifyPass ( * PassRegistry :: getPassRegistry (


<s> bool includes ( const RegisterSet & Rs ) const { return ! Rs . BitVector :: test ( * this


<s> RegisterSet & insert ( const RegisterSet & Rs ) { return static_cast < RegisterSet & > ( BitVector :: operator


<s> bool intersects ( const RegisterSet & Rs )


<s> case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( unsigned i = <NUM_LIT> , w = RC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = RC [ i ] ; if ( ! V . is ( <NUM_LIT> ) && ! V . is (


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( auto I = MRI . use_begin ( R ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> isDebugValue ( ) ) continue ; if ( UseI -> isPHI ( ) ) { assert ( ! UseI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; unsigned DR = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DR == R ) continue ; } return false ; } return


<s> bool DeadCodeElimination :: isDead ( unsigned R ) const { for ( auto I = MRI . use_begin ( R ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> isDebugValue ( ) ) continue ; if ( UseI -> isPHI ( ) ) { assert ( ! UseI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; unsigned DR = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DR == R ) continue ; } return false


<s> if ( RC1 [ B1 + i ] . Type == BitTracker :: BitValue :: Ref && RC1 [ B1 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC2 [ B2 + i ] . Type == BitTracker :: BitValue :: Ref && RC2 [ B2 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC1 [ B1 + i ] != RC2 [ B2 + i ] ) return false ; } return


<s> if ( RC1 [ B1 + i ] . Type == BitTracker :: BitValue :: Ref && RC1 [ B1 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC2 [ B2 + i ] . Type == BitTracker :: BitValue :: Ref && RC2 [ B2 + i ] . RefI . Reg == <NUM_LIT> ) return false ; if ( RC1 [ B1 + i ] != RC2 [ B2 + i ] ) return false ; } return true


<s> for ( unsigned i = <NUM_LIT> ; i < W ; ++ i ) { const BitTracker :: BitValue & V1 = OutC1 [ i ] , & V2 = OutC2 [ i ] ; if ( V1 . Type != V2 . Type || V1 . Type == BitTracker :: BitValue :: One ) return false ; if ( V1 . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V1 . RefI . Pos != V2 . RefI . Pos ) return false ; if ( V1 . RefI . Reg != InpR1 ) return false ; if ( V2 . RefI . Reg == <NUM_LIT> || V2 . RefI . Reg ==


<s> for ( unsigned i = <NUM_LIT> , w = OutC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = OutC [ i ] ; if ( V . Type != BitTracker ::


<s> if ( ! BTP -> has ( OutR ) || ! BTP -> has ( InpR ) ) return false ; const BitTracker :: RegisterCell & OutC = BTP -> lookup ( OutR ) ; for ( unsigned i = <NUM_LIT> , w = OutC . width ( ) ; i < w ; ++ i ) { const BitTracker :: BitValue & V = OutC [ i ] ; if ( V . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V . RefI . Reg != InpR ) return false ; } return true


<s> if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == InpR ) return i == n


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) || ! TargetRegisterInfo :: isVirtualRegister ( RS . Reg ) ) return false ; auto * DRC = getFinalVRegClass ( RD , MRI ) ; if ( ! DRC )


<s> bool <ISA_LIT>BitSimplify :: isTransparentCopy ( const BitTracker :: RegisterRef & RD , const BitTracker :: RegisterRef &


<s> bool <ISA_LIT>BitSimplify :: isZero ( const BitTracker :: RegisterCell & RC , uint16_t B , uint16_t W ) { assert ( B < RC . width ( ) && B + W <= RC . width ( ) ) ; for ( uint16_t i = B ; i < B + W ; ++ i ) if ( ! RC [ i ]


<s> for ( uint16_t i = B ; i < B + W ; ++ i ) if ( ! RC [ i ] . is ( <NUM_LIT> ) ) return false ; return


<s> const BitTracker :: RegisterCell & SC = BT . lookup ( Reg ) ; if ( Pos + <NUM_LIT> > SC . width ( ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { const BitTracker :: BitValue & RV = RC [ i + B ] ; if ( RV . Type == BitTracker :: BitValue :: Ref ) { if ( RV . RefI . Reg != Reg ) return false ; if ( RV . RefI . Pos != i + Pos ) return false ; continue ; } if ( RC [ i + B ] != SC [ i + Pos ] ) return false ; } unsigned Sub = <NUM_LIT> ; switch ( Pos ) { case <NUM_LIT> : Sub = <STR_LIT> ; Low = true ; break ; case <NUM_LIT> : Sub = <STR_LIT> ; Low = false ; break ; case <NUM_LIT> : Sub = <STR_LIT>


<s> if ( ! matchHalf ( SelfR , RC , <NUM_LIT> , H2 ) || ! matchHalf ( SelfR , RC , <NUM_LIT> , H1 ) ) return false ; if ( H1 . Reg != L1 . Reg || H1 . Sub != L1 . Sub || H1


<s> if ( Sub1 == <STR_LIT> && Sub2 == <STR_LIT> ) { SL = I . getOperand ( <NUM_LIT> ) ; SH = I . getOperand ( <NUM_LIT> ) ; return true ; } if ( Sub1 == <STR_LIT> && Sub2 == <STR_LIT> ) { SH = I . getOperand ( <NUM_LIT> ) ; SL = I . getOperand ( <NUM_LIT> ) ; return true ; } return false


<s> if ( ! BT . has ( RD . Reg ) ) continue ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; const BitTracker :: RegisterCell & RC = BT . lookup ( RD . Reg ) ; if ( FRC -> getID ( ) == <STR_LIT> ) { bool T = genPackhl ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == <STR_LIT> ) { bool T = genExtractHalf ( MI , RD , RC ) ; T = T || genCombineHalf ( MI , RD , RC


<s> case <STR_LIT> : case <STR_LIT> : { BitTracker :: RegisterRef RS = MI . getOperand ( <NUM_LIT> ) ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) break ; if ( RS . Sub != <NUM_LIT> ) Changed = HBS :: replaceRegWithSub ( RD . Reg , RS . Reg , RS . Sub , MRI ) ; else Changed = HBS :: replaceReg ( RD . Reg , RS . Reg , MRI ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { BitTracker :: RegisterRef SL , SH ; if ( HBS :: parseRegSequence ( MI , SL , SH ) ) { Changed = HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , SL . Reg , SL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , SH . Reg , SH . Sub , MRI ) ; } break ; } case <STR_LIT> : { BitTracker :: RegisterRef RH = MI . getOperand ( <NUM_LIT> ) , RL = MI . getOperand ( <NUM_LIT> ) ; Changed = HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , RL . Reg , RL . Sub , MRI ) ; Changed |= HBS :: replaceSubWithSub ( RD . Reg , <STR_LIT> , RH . Reg , RH . Sub , MRI ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned SrcX = ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Sub = ( Opc == <STR_LIT> ) ?


<s> bool CopyPropagation :: propagateRegCopy ( MachineInstr & MI ) { bool Changed = false ; unsigned Opc = MI . getOpcode ( ) ; BitTracker :: RegisterRef RD = MI . getOperand ( <NUM_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) ; switch ( Opc ) { case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : { BitTracker :: RegisterRef RS = MI . getOperand ( <NUM_LIT> ) ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) break ; if ( RS . Sub != <NUM_LIT> ) Changed = HBS :: replaceRegWithSub ( RD . Reg , RS . Reg , RS . Sub , MRI ) ; else Changed = HBS :: replaceReg ( RD . Reg , RS . Reg , MRI ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { BitTracker :: RegisterRef SL , SH ; if ( HBS :: parseRegSequence ( MI , SL , SH


<s> RegisterSet & remove ( const RegisterSet & Rs


<s> auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I =


<s> decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; if ( I -> getSubReg ( ) != OldSR ) continue ; I -> setReg (


<s> bool <ISA_LIT>BitSimplify :: replaceSubWithSub ( unsigned OldR , unsigned OldSR , unsigned NewR , unsigned NewSR , MachineRegisterInfo & MRI ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( OldR ) || ! TargetRegisterInfo :: isVirtualRegister ( NewR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End


<s> for ( auto I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) Changed |= runOnNode ( * I ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc

== TargetOpcode :: LIFETIME_END ) continue ;