<s> int <ISA_LIT>InstrInfo :: getIndirectIndexBegin ( const MachineFunction & MF ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int Offset = - <NUM_LIT> ; if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } if ( MRI . livein_empty ( ) ) { return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( std :: pair < unsigned , unsigned > LI : MRI . liveins ( ) ) { unsigned Reg = LI . first ; if ( Register :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ; } return Offset


<s> } case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo ::


<s> if ( I -> isReg ( ) && ! Register :: isVirtualRegister ( I -> getReg ( ) ) && I

-> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { return isPredicateSetter ( MI . getOpcode (


<s> bool <ISA_LIT>InstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const { return isPredicateSetter ( MI . getOpcode ( )


<s> unsigned VectorComponents = <NUM_LIT> ; if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI


<s> unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , <STR_LIT> :: src0 ) ) . setIsKill


<s> unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == ( unsigned ) Reg ) break ; } Offset = std :: max ( Offset , ( int ) RegIndex ) ; } return Offset +


<s> if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST


<s> SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > Result ; if ( MI . getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( const auto & Op : OpTable ) { MachineOperand & MO = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( const auto & Op : OpTable ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , Op [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } if ( Reg == <STR_LIT> ) { MachineOperand & Operand = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , <STR_LIT> :: literal ) ) ; if ( Operand . isImm ( ) ) { Result . push_back ( std :: make_pair ( & MO , Operand . getImm ( ) ) ) ; continue ; } assert ( Operand . isGlobal ( ) ) ; } Result . push_back ( std :: make_pair ( & MO , <NUM_LIT> ) ) ; } return


<s> int getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const override { return


<s> bool <ISA_LIT>InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , const BranchProbability & Probability ) const { return true


<s> bool <ISA_LIT>InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles ,

const BranchProbability & Probability ) const {


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB

, unsigned NumFCycles , unsigned ExtraFCycles , const BranchProbability & Probability ) const {


<s> } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand (


<s> if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents =


<s> if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; } for ( ; i < <NUM_LIT> ; ++


<s> unsigned Reg = Src . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back


<s> SmallSet < int64_t , <NUM_LIT> > Literals ; for ( unsigned i = <NUM_LIT> , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; for ( const auto & Src : getSrcs ( MI ) ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) ||

<STR_LIT> . contains ( Src . first -> getReg ( ) ) ) {


<s> unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned >> TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TransBS = TransSwz


<s> if ( ! FBB ) { if ( Cond . empty ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT> ; } } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( * PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [


<s> const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < <NUM_LIT> || Src . first == <NUM_LIT> ) continue ; if ( Src . first == GET_REG_INDEX ( RI . getEncodingValue ( <STR_LIT> ) ) ) { if ( Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_012_SCL_210 && Swz [ i ] != <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 ) { return false ; } continue ; } if ( Vector [ Src . second ] [ j ] < <NUM_LIT> ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT>


<s> return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } else if ( isVector ( MI ) ) { return false


<s> const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { for ( unsigned Chan = <NUM_LIT> ; Chan <


<s> break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; default : return true ; } MachineOperand & MO2 = Cond [


<s> return MI . findRegisterDefOperandIdx ( <STR_LIT>


<s> return MI . findRegisterDefOperandIdx ( <STR_LIT> )


<s> return MI . findRegisterUseOperandIdx ( <STR_LIT> ) != -


<s> bool <ISA_LIT>InstrInfo :: usesAddressRegister ( MachineInstr &


<s> return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( MachineRegisterInfo :: livein_iterator LI = MRI . livein_begin ( ) , LE = MRI . livein_end ( ) ; LI != LE ; ++ LI ) { unsigned Reg = LI -> first ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg )


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; int End = getIndirectIndexEnd ( MF ) ; if ( End == - <NUM_LIT> ) return ; for ( int Index = getIndirectIndexBegin ( MF ) ; Index <= End ; ++ Index ) { unsigned SuperReg = <STR_LIT> . getRegister


<s> unsigned Reg = Src . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; } for ( ; i < <NUM_LIT> ; ++ i ) Result


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; Register IgnoredFrameReg ; Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT>


<s> if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST .


<s> buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: val ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == <STR_LIT> ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } }


<s> const std :: pair < int , unsigned > DummyPair ( - <NUM_LIT> , <NUM_LIT> ) ; std :: vector < std :: pair < int , unsigned > > Result ; unsigned i = <NUM_LIT> ; for ( unsigned n = Srcs . size ( ) ; i < n ; ++ i ) { unsigned Reg = Srcs [ i ] . first -> getReg ( ) ; int Index = RI . getEncodingValue ( Reg ) & <NUM_LIT> ; if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; } for ( ; i < <NUM_LIT> ; ++ i ) Result . push_back ( DummyPair ) ; return


<s> SmallSet < int64_t , <NUM_LIT> > Literals ; for ( unsigned i = <NUM_LIT> , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr * MI = MIs [ i ] ; if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) continue ; ArrayRef < std :: pair < MachineOperand * , int64_t >> Srcs = getSrcs ( MI ) ; for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first


<s> for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg (


<s> SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > <ISA_LIT>InstrInfo :: getSrcs ( MachineInstr * MI ) const { SmallVector < std :: pair < MachineOperand * , int64_t > , <NUM_LIT> > Result ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { MachineOperand & MO = MI -> getOperand ( getOperandIdx ( MI -> getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg


<s> return ( <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && usesVertexCache ( MI -> getOpcode ( )

) ) || usesTextureCache ( MI -> getOpcode ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: usesVertexCache ( const MachineInstr * MI ) const { const MachineFunction * MF = MI -> getParent


<s> assert ( PredSet && <STR_LIT> ) ; addFlag ( PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT> ; } } else { MachineInstr * PredSet = findFirstPredicateSetterFrom ( MBB , MBB . end ( ) ) ; assert ( PredSet && <STR_LIT> ) ; addFlag ( PredSet , <NUM_LIT> , MO_FLAG_PUSH ) ; PredSet -> getOperand ( <NUM_LIT> ) . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) return <NUM_LIT> ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; return <NUM_LIT>


<s> MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr & SecondLastInst = * I ; unsigned SecondLastOpc = SecondLastInst . getOpcode ( ) ; if ( SecondLastOpc == <STR_LIT> && LastOpc == <STR_LIT> ) { auto predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; FBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode >


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; } return false


<s> BaseReg = Addr ; Offset = CurDAG -> getIntPtrConstant ( <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; } return


<s> if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast )


<s> if ( ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( )


<s> static int ConstantAddressBlock ( unsigned AddressSpace , <ISA_LIT>AS AMDGPUA<ISA_LIT> ) { switch ( AddressSpace ) { case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 : return <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_1 : return <NUM_LIT> + <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_2 : return <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_3 : return <NUM_LIT> + <NUM_LIT> * <NUM_LIT> ; case AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_4 : return <NUM_LIT> +


<s> if ( ! Neg . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Neg = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( ! Abs . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Abs = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : { unsigned Opcode = ParentNode -> getMachineOpcode ( ) ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; if ( ! Sel . getNode ( ) ) return false ; SDValue CstOffset = Src . getOperand ( <NUM_LIT> ) ; if ( ParentNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return false ; int SrcIndices [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; std :: vector < unsigned > Consts ; for ( int OtherSrcIdx : SrcIndices ) { int OtherSelIdx = TII -> getSelIdx ( Opcode , OtherSrcIdx ) ; if ( OtherSrcIdx < <NUM_LIT> || OtherSelIdx < <NUM_LIT> ) continue ; if ( HasDst ) { OtherSrcIdx -- ; OtherSelIdx -- ; } if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( ParentNode -> getOperand ( OtherSrcIdx ) ) ) { if ( Reg -> getReg ( ) == <STR_LIT> ) { ConstantSDNode * Cst = cast < ConstantSDNode > ( ParentNode -> getOperand ( OtherSelIdx ) ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; } } } ConstantSDNode * Cst = cast < ConstantSDNode > ( CstOffset ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; if ( ! TII -> fitsConstReadLimitations ( Consts ) ) { return false ; } Sel = CstOffset ; Src = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return true ; } case <STR_LIT> : if ( cast < ConstantSDNode > ( Imm


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetLowering :: getSubtarget ( ) const { return static_cast < const <ISA_LIT>Subtarget * >


<s> if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ; return std :: next ( I ) ->


<s> static inline bool isEOP ( MachineBasicBlock :: iterator I ) { if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ; return std :: next ( I ) -> getOpcode ( )


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; } return isNullConstant (


<s> if ( ConstantFPSDNode * CFP = dyn_cast <


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstantFP ( - <NUM_LIT> , DL

, <STR_LIT> ) , DAG . getCondCode ( <STR_LIT> ) ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ,


<s> SDValue <ISA_LIT>TargetLowering :: lowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering


<s> SDValue <ISA_LIT>TargetLowering :: lowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ; unsigned IgnoredFrameReg ; unsigned Offset = TFL -> getFrameIndexReference ( MF , FrameIndex


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; MVT ConstPtrVT = getPointerTy ( DL , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , SDLoc ( GSD ) , ConstPtrVT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( GSD ) , ConstPtrVT


<s> GlobalAddressSDNode * GSD = cast < GlobalAddressSDNode > ( Op ) ; if ( GSD -> getAddressSpace ( ) != AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; const DataLayout & DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = GSD ->


<s> return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset ,

DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType


<s> <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT . isInteger ( ) ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; Temp = True ; True = False ; False = Temp ; break ; default : break ; } SDValue SelectNode = DAG . getNode ( <STR_LIT> , DL , CompareVT , Cond , Zero , True , False , DAG . getCondCode ( CCOpcode ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectNode ) ; } SDValue HWTrue , HWFalse ; if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; } else if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstant ( - <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstant ( <NUM_LIT> , DL , CompareVT ) ; } else { llvm_unreachable (


<s> } SDValue DWordAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; if ( AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS ) { if ( StoreNode -> isTruncatingStore ( ) ) { assert ( VT . bitsLE ( <STR_LIT> ) ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode ->


<s> SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case


<s> SDLoc DL ( Op ) ; SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case <STR_LIT> : TrigNode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue TrigVal = DAG . getNode ( TrigNode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , FractPart , DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( Gen >= <ISA_LIT>Subtarget :: R700 )


<s> BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [


<s> SDValue & Abs = Ops [ AbsIdx [ i ] - <NUM_LIT> ] ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; int SelIdx = TII -> getSelIdx ( Opcode , OperandIdx [ i ] ) ; if ( HasDst ) SelIdx -- ; SDValue & Sel = ( SelIdx > - <NUM_LIT> ) ? Ops [ SelIdx ] : FakeOp ; if ( FoldOperand ( Node , i , Src , Neg , Abs , Sel , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else if ( Opcode == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = Node -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { SDValue & Src = Ops [ i ] ; if ( FoldOperand ( Node , i , Src , FakeOp , FakeOp , FakeOp , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } } else if ( Opcode == <STR_LIT> ) { SDValue Src = Node -> getOperand ( <NUM_LIT> ) ; if ( ! Src . isMachineOpcode ( ) || ! TII -> hasInstrModifiers ( Src . getMachineOpcode ( ) ) ) return Node ; int ClampIdx = TII -> getOperandIdx ( Src . getMachineOpcode ( ) , <STR_LIT> :: clamp ) ; if ( ClampIdx < <NUM_LIT> ) return Node ; SDLoc DL ( Node ) ; std :: vector < SDValue > Ops ( Src -> op_begin ( ) , Src -> op_end ( ) ) ; Ops [ ClampIdx - <NUM_LIT> ] = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getMachineNode ( Src . getMachineOpcode ( ) , DL , Node -> getVTList ( ) , Ops ) ; } else { if ( ! TII -> hasInstrModifiers ( Opcode ) ) return Node ; int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) } ; int NegIdx [ ]


<s> SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( )


<s> assert ( RemapSwizzle . empty ( ) ) ; SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) { RemapSwizzle [ i ] = <NUM_LIT>


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT .


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT )


<s> static inline bool isEOP ( MachineBasicBlock


<s> if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { return Cst -> isNullValue ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Jump = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op

. getValueType ( ) , Chain , Jump , Cond ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Vector = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Index ) || Vector . getOpcode ( )


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerFPTOUINT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getCondCode (


<s> unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; assert ( isInt < <NUM_LIT> > (


<s> SDValue Vector = Op . getOperand ( <NUM_LIT> ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Index ) || Vector . getOpcode ( ) == <STR_LIT> ) return Op ; Vector = vectorToVerticalVector ( DAG , Vector ) ; SDValue Insert = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Vector , Value , Index ) ; return vectorToVerticalVector ( DAG , Insert


<s> if ( SDValue Ret = <ISA_LIT>TargetLowering :: LowerLOAD ( Op , DAG ) ) return Ret ; if ( LoadNode -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS && isa < GlobalVariable > ( GetUnderlyingObject ( LoadNode -> getMemOperand ( ) -> getValue ( ) , DAG . getDataLayout ( ) ) ) ) { SDValue Ptr = DAG . getZExtOrTrunc ( LoadNode -> getBasePtr ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op -> getVTList ( ) , LoadNode -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } if ( LoadNode -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS && VT . isVector ( ) ) { SDValue MergedValues [ <NUM_LIT> ] = { ScalarizeVectorLoad ( Op , DAG ) , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } int ConstantBlock = ConstantAddressBlock ( LoadNode -> getAddressSpace ( ) ) ; if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < ConstantExpr > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , DL , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getNode ( <STR_LIT> , DL , NewVT , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG


<s> SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Lo , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shift ) ; HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , HiSmall , Overflow ) ; SDValue LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shift ) ; SDValue HiBig = DAG . getNode ( <STR_LIT> , DL , VT , Lo , BigShift ) ; SDValue LoBig = Zero ; Hi = DAG . getSelectCC ( DL , Shift , Width , HiSmall ,


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shift = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Width = DAG . getConstant ( VT . getSizeInBits ( ) , DL , VT ) ; SDValue Width1 = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , DL , VT ) ; SDValue BigShift = DAG . getNode ( <STR_LIT> , DL , VT , Shift , Width ) ; SDValue CompShift = DAG . getNode ( <STR_LIT> , DL , VT , Width1 , Shift ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Lo , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shift ) ; HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , HiSmall , Overflow


<s> SDValue Shift = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; const bool SRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue Width = DAG . getConstant ( VT . getSizeInBits ( ) , DL , VT ) ; SDValue Width1 = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , DL , VT ) ; SDValue BigShift = DAG . getNode ( <STR_LIT> , DL , VT , Shift , Width ) ; SDValue CompShift = DAG . getNode ( <STR_LIT> , DL , VT , Width1 , Shift ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Hi , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( SRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , Shift ) ; SDValue LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shift ) ; LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , LoSmall , Overflow ) ; SDValue LoBig = DAG . getNode ( SRA ? <STR_LIT> : <STR_LIT> , DL , VT , Hi , BigShift ) ; SDValue HiBig = SRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , Width1


<s> SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , Shift ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , Shift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && Value . getValueType ( ) . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return Chain ; } } EVT ValueVT = Value . getValueType ( ) ; if ( StoreNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } SDValue Ret = <ISA_LIT>TargetLowering :: LowerSTORE ( Op , DAG ) ; if ( Ret . getNode ( ) ) { return Ret ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = static_cast < const <ISA_LIT>FrameLowering * > ( Subtarget -> getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( ValueVT . isVector ( ) ) { unsigned NumElemVT = ValueVT . getVectorNumElements ( ) ; EVT ElemVT = ValueVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Stores (


<s> } SDValue TrigVal = DAG . getNode ( TrigNode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , FractPart , DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( Gen >= <ISA_LIT>Subtarget :: R700 ) return TrigVal ; return DAG . getNode ( <STR_LIT> , DL , VT , TrigVal ,

DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; SDValue FractPart = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Arg , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; unsigned TrigNode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case <STR_LIT> : TrigNode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT>


<s> BuildVector = CompactSwizzlableVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ; } SwizzleRemap . clear (


<s> static SDValue ReorganizeVector ( SelectionDAG & DAG , SDValue VectorEntry , DenseMap < unsigned , unsigned > & RemapSwizzle ) { assert ( VectorEntry . getOpcode ( ) == <STR_LIT> ) ; assert ( RemapSwizzle . empty ( ) ) ; SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; bool isUnmovable [ <NUM_LIT> ] = { false , false , false , false } ; for ( unsigned i = <NUM_LIT> ; i


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDLoc DL ( Ptr ) ; return DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr ,

DAG . getConstant ( SRLPad , DL , <STR_LIT> ) ) ;


<s> EVT EltVT = VecVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = VecVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getConstant ( i , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL


<s> EVT VecVT = Vector . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = VecVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getConstant (

i , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ) ;


<s> if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( <STR_LIT> ) &&


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( <STR_LIT> )


<s> case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: SPIR_KERNEL : case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS : case CallingConv


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . isUndef ( ) ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C ->


<s> } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } SDValue Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result ,


<s> if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ; return std :: next ( I ) ->


<s> } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( <STR_LIT> , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , PtrInfo , MemVT , Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg


<s> GlobalAddressSDNode * GSD = cast < GlobalAddressSDNode > ( Op ) ; if ( GSD -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; const DataLayout & DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; MVT ConstPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , SDLoc ( GSD ) , ConstPtrVT ) ; return DAG . getNode ( <STR_LIT> , SDLoc


<s> const GlobalValue * GV = GSD -> getGlobal ( ) ; MVT ConstPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , SDLoc ( GSD ) , ConstPtrVT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( GSD ) ,


<s> PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL ,

<STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) ) ;


<s> unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( )


<s> Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } if ( Ptr . getOpcode ( ) != <STR_LIT> ) { assert ( VT == <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , LoadNode -> getMemOperand ( ) ) ; } return SDValue (


<s> assert ( VT . bitsLE ( <STR_LIT> ) ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return Chain


<s> DenseMap < unsigned , unsigned > SwizzleRemap ; BuildVector = CompactSwizzlableVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ; } SwizzleRemap . clear ( ) ; BuildVector = ReorganizeVector ( DAG ,


<s> assert ( RemapSwizzle . empty ( ) ) ; SDLoc DL ( VectorEntry ) ; EVT EltTy = VectorEntry . getValueType ( ) . getVectorElementType ( ) ; SDValue NewBldVec [ <NUM_LIT> ] ; bool isUnmovable [ <NUM_LIT> ] = { false , false , false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { RemapSwizzle [ i ] = i ; if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = dyn_cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( i == Idx ) isUnmovable [ Idx ] = true ; } } for ( unsigned i = <NUM_LIT> ;


<s> EVT EltTy = VectorEntry . getValueType ( ) . getVectorElementType ( ) ; SDValue NewBldVec [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . isUndef ( ) ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode


<s> LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; assert ( Load -> getAlignment ( ) >= MemVT . getStoreSize ( ) ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue Offset = Load -> getOffset ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG .


<s> SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue (


<s> } } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) && ( CompareVT == VT || VT == <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } if ( isZero ( LHS ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> CCSwapped = <STR_LIT> ( CCOpcode ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } else { <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case


<s> } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { return SDValue ( ) ; } if ( Ptr . getOpcode ( ) != <STR_LIT> ) { assert ( VT == <STR_LIT>


<s> SDLoc DL ( Op ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; assert ( Load -> getAlignment ( ) >= MemVT . getStoreSize ( ) ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue Offset = Load -> getOffset ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( Type :: getInt32PtrTy ( * DAG . getContext ( ) , AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Read , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType == <STR_LIT> ) { SDValue MemEltVTNode = DAG . getValueType ( MemEltVT ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , MemEltVTNode ) ; } else { Ret = DAG . getZeroExtendInReg ( Ret , DL , MemEltVT ) ; } SDValue Ops [ ] = { Ret , Read . getValue ( <NUM_LIT> )


<s> assert ( Store -> isTruncatingStore ( ) || Store -> getValue ( ) . getValueType ( ) == <STR_LIT> ) ; assert ( Store -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ; SDValue Mask ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( Type :: getInt32PtrTy ( * DAG . getContext ( ) , AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr


<s> if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( <STR_LIT> ) &&


<s> const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! Src . isMachineOpcode ( ) ) return false ; switch ( Src . getMachineOpcode ( ) ) { case <STR_LIT> : if ( ! Neg . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Neg = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( ! Abs . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Abs = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( ParentNode ) , <STR_LIT> ) ; return true ; case <STR_LIT> : { unsigned Opcode = ParentNode -> getMachineOpcode ( ) ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; if ( ! Sel . getNode ( ) ) return false ; SDValue CstOffset = Src . getOperand ( <NUM_LIT> ) ; if ( ParentNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return false ; int SrcIndices [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; std :: vector < unsigned > Consts ; for ( int OtherSrcIdx : SrcIndices ) { int OtherSelIdx = TII -> getSelIdx ( Opcode , OtherSrcIdx ) ; if ( OtherSrcIdx < <NUM_LIT> || OtherSelIdx < <NUM_LIT> ) continue ; if ( HasDst ) { OtherSrcIdx -- ; OtherSelIdx -- ; } if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode >

( ParentNode -> getOperand ( OtherSrcIdx ) ) ) {


<s> return true ; case <STR_LIT> : { unsigned Opcode = ParentNode -> getMachineOpcode ( ) ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; if ( ! Sel . getNode ( ) ) return false ; SDValue CstOffset = Src . getOperand ( <NUM_LIT> ) ; if ( ParentNode -> getValueType ( <NUM_LIT> ) . isVector ( ) ) return false ; int SrcIndices [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src2 ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; std :: vector < unsigned > Consts ; for ( int OtherSrcIdx : SrcIndices ) { int OtherSelIdx = TII -> getSelIdx ( Opcode , OtherSrcIdx ) ; if ( OtherSrcIdx < <NUM_LIT> || OtherSelIdx < <NUM_LIT> ) continue ; if ( HasDst ) { OtherSrcIdx -- ; OtherSelIdx -- ; } if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( ParentNode -> getOperand ( OtherSrcIdx ) ) ) { if ( Reg -> getReg ( ) == <STR_LIT> ) { ConstantSDNode * Cst = cast < ConstantSDNode > ( ParentNode -> getOperand ( OtherSelIdx ) ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; } } } ConstantSDNode * Cst = cast < ConstantSDNode > ( CstOffset ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; if ( ! TII -> fitsConstReadLimitations ( Consts ) ) { return false ; } Sel = CstOffset ; Src = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return


<s> if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { return Cst -> isZero ( ) ; } else if ( ConstantFPSDNode * CstFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CstFP -> isZero ( ) ; } else


<s> analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { Register Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) !=


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; if ( <STR_LIT> ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { Register Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Alignment = MinAlign ( VT . getStoreSize ( ) , PartOffset ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PARAM_I_ADDRESS ) ; SDValue Arg = DAG . getLoad ( <STR_LIT> , Ext , VT , DL , Chain , DAG . getConstant ( PartOffset , DL , <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , PtrInfo , MemVT ,

Alignment , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> const <ISA_LIT>FrameLowering * TFL = Subtarget -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN ->


<s> const <ISA_LIT>FrameLowering * TFL = Subtarget -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex


<s> static SDValue ReorganizeVector ( SelectionDAG & DAG , SDValue VectorEntry , DenseMap < unsigned , unsigned > & RemapSwizzle ) { assert ( RemapSwizzle . empty ( ) ) ; SDLoc DL ( VectorEntry ) ; EVT EltTy = VectorEntry . getValueType ( ) . getVectorElementType ( ) ; SDValue NewBldVec [ <NUM_LIT> ] ; bool isUnmovable [ <NUM_LIT> ] = { false , false , false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) NewBldVec [ i ] = DAG . getNode ( <STR_LIT> , DL , EltTy , VectorEntry , DAG . getIntPtrConstant ( i , DL ) ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { RemapSwizzle [ i ] = i ; if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( i == Idx ) isUnmovable [ Idx ] = true ; } } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode (


<s> SDValue Mask ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL


<s> assert ( Store -> getAlignment ( ) >= <NUM_LIT> ) ; Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , ShiftAmt ) ; DstMask = DAG . getNOT ( DL , DstMask , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; SDValue NewStore = DAG . getStore ( Chain , DL , Value , Ptr , MachinePointerInfo ( ) ) ; if ( VectorTrunc ) { Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewStore ) ; DAG . ReplaceAllUsesOfValueWith ( OldChain , Chain


<s> assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; }


<s> SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; if ( <STR_LIT> ( CallConv ) ) { AnalyzeFormalArguments ( CCInfo , Ins ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext = <STR_LIT>


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; assert ( isInt < <NUM_LIT> > (


<s> if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < ConstantExpr > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , DL , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType


<s> Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , ShiftAmt ) ; DstMask = DAG . getNOT ( DL , DstMask , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; SDValue NewStore = DAG . getStore ( Chain , DL , Value , Ptr , MachinePointerInfo ( ) ) ; if (


<s> llvm_unreachable ( <STR_LIT> ) ; } SDValue OldChain = Store -> getChain ( ) ; bool VectorTrunc = ( OldChain . getOpcode ( ) == <STR_LIT> ) ; SDValue Chain = VectorTrunc ? OldChain -> getOperand ( <NUM_LIT> ) : OldChain ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Offset = Store -> getOffset ( ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , ShiftAmt ) ; DstMask = DAG . getNOT ( DL , DstMask , <STR_LIT> ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; SDValue NewStore = DAG . getStore ( Chain , DL , Value , Ptr , MachinePointerInfo ( ) ) ; if ( VectorTrunc ) { Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewStore ) ; DAG . ReplaceAllUsesOfValueWith ( OldChain


<s> BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( MI . getOpcode ( ) ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( isEOP ( I ) ) ; break ; case <STR_LIT> : BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ; } case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ; } case <STR_LIT> : case <STR_LIT> : { bool isLastInstructionOfItsType = true ; unsigned InstExportType = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; for ( MachineBasicBlock :: iterator NextExportInst = std :: next ( I ) , EndBlock = BB -> end ( ) ; NextExportInst != EndBlock ; NextExportInst = std :: next ( NextExportInst ) ) { if ( NextExportInst -> getOpcode ( ) == <STR_LIT> || NextExportInst -> getOpcode ( ) == <STR_LIT> ) { unsigned CurrentInstExportType = NextExportInst -> getOperand ( <NUM_LIT> )


<s> CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext =


<s> if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } SDValue LoweredLoad ; if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( VT . isVector ( ) ) { unsigned NumElemVT = VT . getVectorNumElements ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Loads [ <NUM_LIT> ] ; assert ( NumElemVT <= <NUM_LIT> ) ; assert ( NumElemVT >= StackWidth && <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElemVT ; ++ i ) { unsigned Channel , PtrIncr


<s> <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType ==


<s> EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , DL , <STR_LIT> ) , ShiftAmt ) ; DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DstMask , DAG . getConstant ( <NUM_LIT> , DL


<s> EVT VT = Value . getValueType ( ) ; assert ( VT . bitsLE ( <STR_LIT> ) ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue DWordAddr = DAG . getNode ( <STR_LIT> , DL , VT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , Shift ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , Shift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( Subtarget -> hasCARRY ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Subtarget -> hasBORROW ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! Subtarget -> hasBFE ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> hasBFE ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> hasBFE ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; const MVT ScalarIntVTs [ ] = { <STR_LIT> , <STR_LIT> } ; for ( MVT VT : ScalarIntVTs ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } setSchedulingPreference ( Sched ::


<s> SDValue <ISA_LIT>TargetLowering :: lowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget ->


<s> unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = <NUM_LIT> + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ,


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; if ( <STR_LIT> ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector (


<s> if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = <NUM_LIT> + VA . getLocMemOffset


<s> unsigned Offset = TFL -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; return DAG . getConstant ( Offset * <NUM_LIT> * TFL -> getStackWidth ( MF )

, SDLoc ( Op ) , Op . getValueType ( ) ) ;


<s> scalarizeVectorLoad ( LoadNode , DAG ) , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } int ConstantBlock = ConstantAddressBlock ( LoadNode -> getAddressSpace ( ) ) ; if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < ConstantExpr > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { SDValue Slots [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> * i + ConstantBlock * <NUM_LIT> , DL , <STR_LIT> ) ) ; Slots [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewPtr ) ; } EVT NewVT = <STR_LIT> ; unsigned NumElements = <NUM_LIT> ; if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } SDValue LoweredLoad


<s> if ( StoreNode -> isTruncatingStore ( ) ) { EVT VT = Value . getValueType ( ) ; assert ( VT . bitsLE ( <STR_LIT> ) ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue DWordAddr = DAG . getNode ( <STR_LIT> , DL , VT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , Shift ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , Shift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && ValueVT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; if ( StoreNode -> isTruncatingStore ( ) ||


<s> return expandUnalignedStore ( StoreNode , DAG ) ; } SDValue DWordAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) { if ( TruncatingStore ) { assert ( VT . bitsLE ( <STR_LIT> ) ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return


<s> MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return Chain ; } } if ( AS != <ISA_LIT>AS :: PRIVATE_ADDRESS ) return