<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; return MI . getOperand ( <NUM_LIT> ) . isReg ( ) || RI . isAGPR ( MRI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( )


<s> if ( MI . isReturn ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ||


<s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ; CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ <NUM_LIT> ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT>


<s> } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_BACKWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( PCReg ) ; RS -> enterBasicBlockEnd ( MBB ) ; Register Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false ,


<s> auto I = MBB . end ( ) ; MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , PCReg ) ; if ( BrOffset >= <NUM_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_FORWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> )

. addMBB ( & DestBB , MO_LONG_BRANCH_BACKWARD ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> bool <ISA_LIT>InstrInfo :: isInlineConstant ( const MachineOperand & MO , uint8_t OperandType ) const { if ( ! MO . isImm ( ) || OperandType < <STR_LIT> || OperandType > <STR_LIT> ) return false ; int64_t Imm = MO . getImm ( ) ; switch ( OperandType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int32_t Trunc = static_cast < int32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( Imm ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( Imm ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) return Signed ? isInt < <NUM_LIT> > ( Offset ) : isUInt < <NUM_LIT> > ( Offset ) ; return Signed ? isInt < <NUM_LIT> > ( Offset ) : isUInt


<s> bool <ISA_LIT>InstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = Reg . isVirtual ( ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const TargetRegisterClass * DRC = RI . getRegClass ( OpInfo . RegClass ) ; if ( MO . getSubReg ( ) ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ; if ( ! SuperRC


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - <NUM_LIT> ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI . getOperand ( OpIdx ) ; int ConstantBusLimit = ST . getConstantBusLimit ( MI . getOpcode ( ) ) ; int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ]


<s> int VOP3LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( isVALU ( MI ) && usesConstantBus ( MRI , * MO , OpInfo ) ) { if ( isVOP3 ( MI ) && isLiteralConstantLike ( * MO , OpInfo ) && ! VOP3LiteralLimit -- ) return false ; SmallDenseSet < RegSubRegPair > SGPRsUsed ; if ( MO -> isReg ( ) ) SGPRsUsed . insert ( RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { RegSubRegPair SGPR ( Op . getReg ( ) , Op . getSubReg ( ) ) ; if ( ! SGPRsUsed . count ( SGPR ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; SGPRsUsed . insert ( SGPR ) ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == <STR_LIT> ) { if ( -- ConstantBusLimit <= <NUM_LIT> ) return false ; } else if ( isVOP3 ( MI ) && <STR_LIT> ( InstDesc , i ) && isLiteralConstantLike ( Op , InstDesc . OpInfo [ i ] ) ) { if ( ! VOP3LiteralLimit -- ) return false ; if ( -- ConstantBusLimit <= <NUM_LIT> ) return


<s> Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ; if ( Def -> isMoveImmediate ( ) && DstRC != & <STR_LIT> ) FoldImmediate ( * Copy , * Def , OpReg , & MRI ) ; bool ImpDef = Def -> isImplicitDef ( ) ; while ( ! ImpDef && Def && Def -> isCopy ( ) ) { if ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) . isPhysical ( ) ) break ; Def = MRI . getUniqueVRegDef ( Def -> getOperand ( <NUM_LIT> )


<s> MachineOperand * SAddr = getNamedOperand ( MI , <STR_LIT> :: saddr ) ; if ( ! SAddr || RI . isSGPRClass ( MRI .

getRegClass ( SAddr -> getReg ( ) ) ) ) return ;


<s> if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & <STR_LIT> , VRC ) ) VRC = & <STR_LIT> ; else VRC = & <STR_LIT> ; Register Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode


<s> MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; for ( auto & MO : MI . uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; MachineBasicBlock :: iterator J = I ++ ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ; LoopBB -> splice ( LoopBB -> begin (


<s> for ( MachineInstr & CandI : make_range ( std :: next ( MachineBasicBlock :: reverse_iterator ( Inst ) ) , Inst . getParent ( ) -> rend ( ) ) ) { if ( CandI . findRegisterDefOperandIdx ( <STR_LIT> , false , false , & RI ) != - <NUM_LIT> ) { if ( CandI . isCopy ( ) && CandI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { SCCSource = CandI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } } } if ( ( SCCSource != <STR_LIT> ) && Src0 . isImm ( ) && ( Src0 . getImm ( ) == - <NUM_LIT> ) && Src1 . isImm ( ) && ( Src1 . getImm ( ) == <NUM_LIT> ) ) { MRI . replaceRegWith ( Dest . getReg ( ) , SCCSource ) ; return ; } const TargetRegisterClass * TC = ST . getWavefrontSize ( ) == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; Register CopySCC = MRI . createVirtualRegister ( TC ) ; if ( SCCSource == <STR_LIT> ) { unsigned Opcode = ( ST . getWavefrontSize ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; auto NewSelect = BuildMI ( MBB , MII , DL , get ( Opcode ) , CopySCC ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; NewSelect -> getOperand ( <NUM_LIT> ) . setIsUndef ( Cond . isUndef ( ) ) ; } else


<s> if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RegClass ) ) { if ( RI . getRegSizeInBits ( * RegClass ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } } ArrayRef < int16_t > SubIndices = RI . getRegSplitParts ( RegClass , EltSize ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < SubIndices . size ( ) ; ++ Idx ) { int64_t IdxValue = Idx == <NUM_LIT> ? Value : <NUM_LIT> ; MachineInstrBuilder Builder = BuildMI ( MBB , MI , DL , get ( Opcode ) , RI . getSubReg ( DestReg , SubIndices [ Idx ] ) ) ; Builder . addImm ( IdxValue


<s> const DebugLoc & DL = Inst . getDebugLoc ( ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : { Register ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , TmpReg ) . addReg ( ImmReg , RegState :: Kill ) . add ( Src0 ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . add ( Src1 ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg , RegState :: Kill ) ; break ; } case <STR_LIT> : { Register ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ImmReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( ImmReg , RegState :: Kill ) . add ( Src0 ) . add ( Src1 ) ; break ; } case <STR_LIT> : { Register ImmReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Inst , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) .


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; Register OldDstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = Inst . getOpcode ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; unsigned NewOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addOperand ( MachineOperand :: CreateImm


<s> Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MRI . replaceRegWith ( OldDstReg , ResultReg ) ; legalizeOperands ( Inst , MDT ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return true


<s> Gen = <STR_LIT> ; break ; case <ISA_LIT>Subtarget :: GFX10 : Gen = <STR_LIT> ; break ; } } int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ; if ( isAsmOnlyOpcode ( MCOp


<s> const MachineInstr & SecondLdSt = * BaseOps2 . front ( ) -> getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; const unsigned LoadSize = NumBytes / NumLoads ; const unsigned NumDWORDs = ( ( LoadSize + <NUM_LIT> ) / <NUM_LIT> ) * NumLoads ; return NumDWORDs <=


<s> return false ; } return true ; } if ( MI . isPreISelOpcode ( ) || <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ; return true


<s> } if ( MI . isPreISelOpcode ( ) || <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ; return


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( SrcReg != <STR_LIT> && <STR_LIT>


<s> if ( I == MBB . end ( ) ) return false ; if ( I -> getOpcode ( ) == <STR_LIT> ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } BranchPredicate Pred = getBranchPredicate ( I -> getOpcode ( ) ) ; if ( Pred == INVALID_BR )


<s> assert ( ! SrcOp . isFPImm ( ) ) ; if ( SrcOp . isImm ( ) ) { APInt Imm ( <NUM_LIT> , SrcOp . getImm ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addImm ( Imm . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } else { assert ( SrcOp . isReg ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & SrcCond = MI . getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addReg ( SrcCond .

getReg ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ;


<s> if ( DescSize == <NUM_LIT> || DescSize == <NUM_LIT> ) return DescSize ; assert ( DescSize == <NUM_LIT> ) ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , getOpSize ( MI , Src0Idx ) ) ) return <NUM_LIT> ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , getOpSize ( MI , Src1Idx ) ) ) return <NUM_LIT> ; return <NUM_LIT> ; } switch ( Opc ) { case TargetOpcode


<s> bool isFLATGlobal ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags


<s> bool isFLATGlobal ( uint16_t Opcode )


<s> bool isFLATScratch ( uint16_t Opcode


<s> return false ; case MachineOperand :: MO_Immediate : return ! isInlineConstant ( MO , OpSize ) ; case MachineOperand :: MO_FrameIndex : case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_GlobalAddress : case MachineOperand ::


<s> bool isSegmentSpecificFLAT ( uint16_t Opcode ) const { auto Flags = get ( Opcode ) . TSFlags ; return Flags & (


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { unsigned Opcode = getSGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && RC -> getSize ( ) == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ; return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction


<s> unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && RC -> getSize ( ) == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } unsigned Opcode = getSGPRSpillSaveOpcode ( RC -> getSize ( ) ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex

( FrameIndex ) . addMemOperand ( MMO ) ;


<s> switch ( Desc . OpInfo [ i ] . OperandType ) { case MCOI :: OPERAND_REGISTER : if ( MI . getOperand ( i ) . isImm ( ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case <STR_LIT> : break ; case <STR_LIT> : if ( isLiteralConstant ( MI . getOperand ( i ) , RI . getRegClass ( RegClass ) -> getSize ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case MCOI :: OPERAND_IMMEDIATE : case <STR_LIT> : if ( ! MI . getOperand ( i ) . isImm ( ) && ! MI . getOperand ( i ) . isFI ( ) ) { ErrInfo = <STR_LIT> ; return false ; } LLVM_FALLTHROUGH ; default : continue ; } if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; if ( RegClass != - <NUM_LIT> ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( Reg == <STR_LIT> || TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isVOPC ( MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) ++ ConstantBusCount ; unsigned SGPRUsed = findImplicitSGPRRead ( MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) { if ( OpIdx ==


<s> return false ; } } } if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isVOPC ( MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) ++ ConstantBusCount ; unsigned SGPRUsed = findImplicitSGPRRead ( MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } else { ++ ConstantBusCount ; } } } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; const MachineOperand & Src1 = MI . getOperand ( Src1Idx ) ; const MachineOperand & Src2 = MI . getOperand ( Src2Idx ) ; if ( Src0 . isReg ( ) && Src1 . isReg ( ) && Src2 . isReg ( ) ) { if ( ! compareMachineOp ( Src0 , Src1 ) && ! compareMachineOp ( Src0 , Src2 ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ) { const bool IsDst = Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { if ( unsigned SubReg = MO . getSubReg ( ) ) { assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ; return RI . getNumChannelsFromSubReg ( SubReg ) * <NUM_LIT> ; } } return RI . getRegSizeInBits ( * getOpRegClass (


<s> assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ; return RI . getNumChannelsFromSubReg ( SubReg ) * <NUM_LIT> ; } } return RI . getRegSizeInBits ( * getOpRegClass ( MI ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : llvm_unreachable ( <STR_LIT> ) ; } ++ I ; } if ( I == E ) return false ; if ( I -> getOpcode ( ) != <STR_LIT> ) return analyzeBranchImpl ( MBB , I , TBB , FBB , Cond , AllowModify ) ; ++ I ; if ( I == MBB . end ( ) ) return


<s> } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( *


<s> assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = <STR_LIT> ( RC -> getID ( ) ) / <NUM_LIT> ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . hasVGPRs ( RC ) && NumInsts <= <NUM_LIT> ; } case SCC_TRUE : case SCC_FALSE : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = <STR_LIT> ( RC -> getID ( ) ) / <NUM_LIT> ; if ( NumInsts % <NUM_LIT> == <NUM_LIT> ) NumInsts /= <NUM_LIT> ; CondCycles = TrueCycles =


<s> Register SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub0 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub1 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub2 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub3 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) . addReg ( SRsrcSub0 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub1 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub2 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub3 ) . addImm ( <STR_LIT> ) ; Rsrc . setReg ( SRsrc ) ; Rsrc . setIsKill ( true ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg0 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT> ) . addReg ( VRsrc , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg1 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT> ) . addReg ( VRsrc , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( AndOpc ) , AndCond ) . addReg ( CondReg0 ) . addReg ( CondReg1 ) ; MRI . setSimpleHint ( SaveExec , AndCond ) ; BuildMI ( LoopBB , I , DL , TII . get ( SaveExecOpc ) , SaveExec ) . addReg ( AndCond , RegState :: Kill ) ; I = LoopBB . end ( ) ; BuildMI ( LoopBB , I , DL , TII . get ( XorTermOpc ) , Exec ) . addReg ( Exec ) . addReg ( SaveExec ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) ) . addMBB


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * EltRC = getOpRegClass ( MI , <NUM_LIT> ) ; unsigned Opc ; if ( RI . hasVGPRs ( EltRC ) ) { Opc = ST . useVGPRIndexMode ( ) ? <STR_LIT> : <STR_LIT> ; } else { Opc = RI . getRegSizeInBits ( * EltRC ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } const MCInstrDesc & OpDesc = get ( Opc ) ; Register VecReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsUndef = MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ; unsigned SubReg = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( VecReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( RI . getSubReg ( VecReg , SubReg ) , RegState :: Undef ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( VecReg , RegState :: ImplicitDefine ) . addReg ( VecReg , RegState :: Implicit | ( IsUndef ? RegState :: Undef : <NUM_LIT> ) ) ; const int ImpDefIdx = OpDesc . getNumOperands ( ) + OpDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MIB -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RegLo = RI . getSubReg ( Reg , <STR_LIT> ) ; Register RegHi = RI . getSubReg ( Reg , <STR_LIT> ) ; MIBundleBuilder Bundler ( MBB , MI ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , Reg ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegLo ) . addReg ( RegLo ) . add ( MI . getOperand ( <NUM_LIT> ) ) ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) , RegHi ) . addReg ( RegHi ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) ; Bundler . append ( MIB


<s> const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; if ( ! ST . isWave32 ( ) ) return ; for ( auto & Op : MI . implicit_operands ( ) ) { if ( Op . isReg ( ) && Op . getReg

( ) == <STR_LIT> ) Op . setReg ( <STR_LIT> ) ;


<s> MachineInstrBuilder <ISA_LIT>InstrInfo :: getAddNoCarry ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , Register DestReg , RegScavenger & RS ) const { if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = ! RS . isRegUsed ( <STR_LIT> ) ? Register ( RI . getVCC ( ) ) : RS . scavengeRegister ( RI . getBoolRC ( ) , I , <NUM_LIT> , false ) ; if ( ! UnusedCarry . isValid ( ) ) return MachineInstrBuilder ( ) ; return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define |


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> static unsigned getAGPRSpillSaveOpcode ( unsigned Size ) { switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: getNumFlatOffsetBits ( unsigned AddrSpace , bool Signed ) const { if ( ! ST . hasFlatInstOffsets ( ) ) return


<s> if ( Register :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; return RI . getRegClass


<s> const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass


<s> if ( Op1 . isReg ( ) && Register :: isVirtualRegister ( Op1 . getReg ( ) ) ) { if ( Op1 . isUndef ( ) ) return nullptr ; RSR = getRegSubRegPair ( Op1 ) ; DefInst = MRI . getVRegDef ( RSR . Reg ) ; } break ; } default : if ( followSubRegDef ( * MI , RSR )


<s> } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_BACKWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( PCReg ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false , <NUM_LIT> ) ; MRI . replaceRegWith ( PCReg , Scav ) ; MRI . clearVirtRegs ( ) ; RS -> setRegUsed ( Scav ) ; return <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT>


<s> bool isD16 ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags &


<s> bool <ISA_LIT>InstrInfo :: isLegalFLATOffset ( int64_t Offset , unsigned AddrSpace , bool Signed ) const { if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { return ( Signed && isInt < <NUM_LIT> > ( Offset ) ) || ( ! Signed && isUInt < <NUM_LIT> > ( Offset ) ) ; } return ( Signed && isInt < <NUM_LIT> > ( Offset ) ) || ( !


<s> if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { return ( Signed && isInt < <NUM_LIT> > ( Offset ) ) || ( ! Signed && isUInt <


<s> const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ; if ( ! SuperRC ) return false ; DRC = RI . getMatchingSuperRegClass ( SuperRC , DRC , MO . getSubReg


<s> if ( Register :: isPhysicalRegister ( SubReg . getReg ( ) ) ) return TRI . isSubRegister ( SuperVec . getReg ( ) , SubReg . getReg ( ) ) ; return SubReg . getSubReg ( ) != <STR_LIT> && SubReg .


<s> unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & <STR_LIT> , VRC ) ) VRC = & <STR_LIT> ; else VRC = & <STR_LIT> ; Register Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . add ( MO ) ; MO . ChangeToRegister ( Reg , false


<s> const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI .


<s> unsigned SubOp = ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MII , DL , get ( SubOp ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( Src . getReg ( ) ) . addReg ( TmpReg ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI ,


<s> MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; Register TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SubOp = ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MII , DL , get ( SubOp ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg

( Src . getReg ( ) ) . addReg ( TmpReg ) ;


<s> const TargetRegisterClass * Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) .

addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;


<s> MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( SrcReg != <STR_LIT> && <STR_LIT> ) ; assert ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( Register :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillSaveOpcode ( SpillSize ) : getVGPRSpillSaveOpcode ( SpillSize ) ; MFI -> setHasSpilledVGPRs ( ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; if ( RI . hasAGPRs ( RC ) ) { MachineRegisterInfo & MRI = MF -> getRegInfo


<s> for ( MachineInstr & MI : make_range ( std :: next ( MachineBasicBlock :: reverse_iterator ( SCCUseInst ) ) , SCCUseInst -> getParent ( ) -> rend ( ) ) ) { if ( MI . modifiesRegister ( <STR_LIT> , & RI ) ) break ; if ( MI . definesRegister ( <STR_LIT>


<s> for ( MachineInstr & MI : make_range ( std :: next ( MachineBasicBlock :: iterator ( SCCDefInst ) ) , SCCDefInst . getParent ( ) -> end ( ) ) ) { int SCCIdx = MI . findRegisterUseOperandIdx ( <STR_LIT> , false , & RI ) ; if ( SCCIdx != - <NUM_LIT> ) { if ( MI . isCopy ( ) ) { MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MRI . replaceRegWith ( DestReg , NewCond ) ; CopyToDelete . push_back ( & MI ) ; } else { if ( NewCond . isValid ( ) ) MI . getOperand ( SCCIdx


<s> OpNo = I . getOperandNo ( ) ; break ; } if ( ! RI . hasVectorRegisters ( getOpRegClass ( UseMI , OpNo ) ) ) { Worklist . insert ( & UseMI ) ; do { ++ I ; } while ( I != E && I -> getParent ( ) == & UseMI ) ; } else


<s> if ( I == E ) return false ; while ( I != E && ! I -> isBranch ( ) && ! I -> isReturn ( ) ) { switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true


<s> switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : llvm_unreachable ( <STR_LIT> ) ; } ++


<s> case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = <NUM_LIT> ; } else if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { SrcReg2 = Register ( ) ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else { return


<s> Offset0 = Load0Offset -> getZExtValue ( ) ; Offset1 = Load1Offset -> getZExtValue ( ) ; return true ; } if ( ( isMUBUF ( Opc0 ) || isMTBUF ( Opc0 ) ) && ( isMUBUF ( Opc1 ) || isMTBUF ( Opc1 ) ) ) { if ( ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: soffset ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: vaddr ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: srsrc ) ) return false ; int OffIdx0 = <STR_LIT> ( Opc0 , <STR_LIT> :: offset ) ; int OffIdx1 = <STR_LIT> ( Opc1 , <STR_LIT> :: offset ) ; if ( OffIdx0 == - <NUM_LIT> || OffIdx1 == - <NUM_LIT> ) return false ; OffIdx0 -= get ( Opc0 ) . NumDefs ; OffIdx1 -= get ( Opc1 ) . NumDefs ; SDValue Off0 = Load0 -> getOperand ( OffIdx0 ) ; SDValue Off1 = Load1 -> getOperand ( OffIdx1 ) ; if ( ! isa < ConstantSDNode > ( Off0 ) || ! isa < ConstantSDNode > ( Off1 ) ) return false ; Offset0 = cast < ConstantSDNode > ( Off0 ) -> getZExtValue ( ) ; Offset1 = cast < ConstantSDNode > ( Off1 ) -> getZExtValue ( ) ; return true ; } return false


<s> return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIb ) && ! isMTBUF ( MIb ) ; } if ( isFLAT ( MIa ) ) { if ( isFLAT ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return false ; } return false


<s> } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIb ) && ! isMTBUF ( MIb ) ; } if ( isFLAT ( MIa ) ) { if ( isFLAT ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return false ; } return false


<s> BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , NewSuperReg ) . addReg ( SuperReg . getReg ( ) , <NUM_LIT> , SuperReg . getSubReg ( ) ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , SubReg ) . addReg ( NewSuperReg , <NUM_LIT> , SubIdx ) ; return


<s> Inst32 . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else if ( <STR_LIT> ( Op32 , <STR_LIT> :: sdst ) != - <NUM_LIT> ) { assert ( ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( * Src2 ) ; } else { fixImplicitOperands ( *


<s> assert ( ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( * Src2 ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Src2 -> isReg ( ) || ! RI . isVGPR ( MRI , Src2 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src2_modifiers ) ) return false ; break ; case <STR_LIT> : break ; } } const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 && ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) ) ) return false ; if ( hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) ) return false ; if ( ! hasVALU32BitEncoding ( MI . getOpcode ( ) ) ) return false ; return ! hasModifiersSet ( MI , <STR_LIT> :: omod ) && ! hasModifiersSet ( MI , <STR_LIT>


<s> if ( ! getMemOperandsWithOffsetWidth ( MIa , BaseOps0 , Offset0 , Offset0IsScalable , Dummy0 , & RI ) || ! getMemOperandsWithOffsetWidth ( MIb , BaseOps1 , Offset1 , Offset1IsScalable , Dummy1 , & RI ) ) return false ; if ( ! memOpsHaveSameBaseOperands ( BaseOps0


<s> Register DstReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MachineInstr * <ISA_LIT>IF = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>END = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg ) ; IfEntry -> erase ( TI ) ; IfEntry -> insert ( IfEntry -> end ( ) , <ISA_LIT>IF ) ; IfEnd -> insert ( IfEnd -> getFirstNonPHI ( ) , <ISA_LIT>END


<s> Register ZeroReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; materializeImmediate ( * PMBB , PMBB -> getFirstTerminator ( ) , DebugLoc ( ) , ZeroReg , <NUM_LIT> ) ; HeaderPHIBuilder . addReg ( ZeroReg ) ; } HeaderPHIBuilder . addMBB ( PMBB ) ; } MachineInstr * HeaderPhi = HeaderPHIBuilder ; MachineInstr * <ISA_LIT>IFBREAK = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , BackEdgeReg ) . addReg ( DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>LOOP = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( BackEdgeReg ) . addMBB ( LoopEntry ) ; LoopEntry -> insert ( LoopEntry -> begin ( ) , HeaderPhi ) ; LoopEnd -> erase ( TI ) ; LoopEnd -> insert ( LoopEnd -> end ( ) , <ISA_LIT>IFBREAK ) ; LoopEnd -> insert ( LoopEnd -> end ( ) , <ISA_LIT>LOOP


<s> for ( MachineOperand & Use : MI . implicit_operands ( ) ) { if ( Use . isUse ( ) && ( Use . getReg ( ) ==

<STR_LIT> || Use . getReg ( ) == <STR_LIT> ) ) {


<s> if ( Cur != MBB . end ( ) ) do { if ( ! Cur -> isPHI ( ) && Cur -> readsRegister ( Dst ) ) return BuildMI ( MBB , Cur , DL , get ( TargetOpcode :: COPY ) , Dst ) . addReg ( Src ) ; ++


<s> return BuildMI ( MBB , InsPt , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , Dst ) . addReg ( Src , <NUM_LIT> , SrcSubReg ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; } return TargetInstrInfo :: createPHISourceCopy ( MBB , InsPt , DL , Src ,


<s> unsigned XorTermOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AndOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; MachineBasicBlock :: iterator I = LoopBB . begin ( ) ; SmallVector < Register , <NUM_LIT> > ReadlanePieces ; Register CondReg = <STR_LIT> ; Register VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; unsigned RegSize = TRI -> getRegSizeInBits ( Rsrc . getReg ( ) , MRI ) ; unsigned NumSubRegs = RegSize / <NUM_LIT> ; assert ( NumSubRegs % <NUM_LIT> == <NUM_LIT> && NumSubRegs <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumSubRegs ; Idx += <NUM_LIT> ) { Register CurRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegLo ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx ) ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegHi ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx + <NUM_LIT> ) ) ; ReadlanePieces . push_back ( CurRegLo ) ; ReadlanePieces . push_back ( CurRegHi ) ; Register CurReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg ( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ; Register NewCondReg = MRI . createVirtualRegister ( BoolXExecRC ) ; auto Cmp = BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , NewCondReg ) . addReg ( CurReg ) ; if ( NumSubRegs <= <NUM_LIT> ) Cmp . addReg ( VRsrc ) ; else Cmp . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx , <NUM_LIT> ) ) ; if ( CondReg == <STR_LIT> ) CondReg = NewCondReg ; else { Register AndReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( AndOpc ) , AndReg ) . addReg ( CondReg ) . addReg ( NewCondReg ) ; CondReg =


<s> for ( auto I = std :: next ( DefMI . getIterator ( ) ) ; ; ++ I ) { assert ( I != DefBB -> end ( ) ) ; if ( I -> isDebugInstr ( ) ) continue ; if ( ++ NumInst > MaxInstScan ) return true ; for ( const MachineOperand & Op : I -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; if ( Op . isUse ( ) ) { if ( Reg == VReg && -- NumUse == <NUM_LIT> ) return false ; } else if ( TRI -> regsOverlap ( Reg , <STR_LIT>


<s> for ( auto I = std :: next ( DefMI . getIterator ( ) ) ; I != E ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; if ( ++ NumInst > MaxInstScan ) return true ; if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) return true ; } return false


<s> Register Reg = RI . getSubReg ( DestReg , SubIdx ) ; unsigned Opcode = <STR_LIT> ; Register Src = RI . getSubReg ( SrcReg , SubIdx ) ; bool AlignedDest = ( ( Reg - <STR_LIT> ) % <NUM_LIT> ) == <NUM_LIT> ; bool AlignedSrc = ( ( Src - <STR_LIT> ) % <NUM_LIT> ) == <NUM_LIT> ; if ( AlignedDest && AlignedSrc && ( Idx + <NUM_LIT> < BaseIndices . size ( ) ) ) { unsigned Channel = RI . getChannelFromSubReg ( SubIdx ) ; SubIdx = RI . getSubRegFromChannel ( Channel , <NUM_LIT> ) ; Opcode = <STR_LIT> ; Idx ++


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( const MachineInstr & MI , unsigned & SrcOpIdx0


<s> static Register findImplicitSGPRRead ( const MachineInstr & MI ) { for ( const MachineOperand & MO : MI . implicit_operands ( ) ) { if ( MO . isDef ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> for ( const MachineOperand & MO : MI . implicit_operands ( ) ) { if ( MO . isDef ( ) ) continue ; switch ( MO . getReg ( ) ) { case


<s> int Idx = OpIndices [ i ] ; if ( Idx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; const TargetRegisterClass * OpRC = RI . getRegClass ( Desc . OpInfo [ Idx ] . RegClass ) ; bool IsRequiredSGPR = RI . isSGPRClass ( OpRC ) ; if ( IsRequiredSGPR ) return MO . getReg ( ) ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RegRC = MRI . getRegClass ( Reg ) ; if ( RI . isSGPRClass ( RegRC )


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( DstReg . isVirtual ( ) || SrcReg . isVirtual ( ) ) && ( DstReg . isVirtual ( ) != SrcReg . isVirtual ( ) ) ) { MachineRegisterInfo & MRI = MF


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = ! RS . isRegUsed ( <STR_LIT> ) ? Register ( RI . getVCC ( ) ) : RS . scavengeRegister ( RI . getBoolRC ( ) , I , <NUM_LIT> , false ) ; if ( ! UnusedCarry . isValid (


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = ! RS . isRegUsed ( <STR_LIT> ) ? Register ( RI . getVCC ( ) ) : RS . scavengeRegister ( RI

. getBoolRC ( ) , I , <NUM_LIT> , false ) ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . isAGPRClass ( SrcRC ) ) { if ( RI . isAGPRClass ( NewDstRC ) ) return nullptr ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; break ; default : NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; } if ( ! NewDstRC ) return nullptr ; } else { if ( RI . isVGPRClass ( NewDstRC ) || NewDstRC == & <STR_LIT>


<s> return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_VS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_GS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_HS : case CallingConv ::


<s> switch ( MF . getFunction ( ) . getCallingConv ( ) ) { case CallingConv :: <ISA_LIT>_PS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_VS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_GS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_ES : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: C


<s> const MachineFunction * MF = MO -> getParent ( ) -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF


<s> static bool getFoldableImm ( const MachineOperand * MO , int64_t & Imm , MachineInstr * * DefMI = nullptr ) { if ( ! MO -> isReg ( ) ) return false ; const MachineFunction * MF = MO -> getParent ( ) -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; return getFoldableImm ( MO -> getReg ( ) , MRI , Imm ,


<s> default : llvm_unreachable ( <STR_LIT> ) ; } } assert ( EltSize == <NUM_LIT> && <STR_LIT> ) ; return get ( getIndirectVGPRWriteMovRelPseudoOpc ( VecSize


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT>


<s> } if ( isMIMG ( MI ) ) { int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; return DescSize


<s> unsigned Offset1 = Offset1Op -> getImm ( ) ; if ( Offset0 + <NUM_LIT> != Offset1 ) return false ; unsigned EltSize ; if ( LdSt . mayLoad ( ) ) EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , <NUM_LIT> ) ) / <NUM_LIT> ; else { assert ( LdSt . mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , Data0Idx ) ) / <NUM_LIT> ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; BaseOps . push_back ( BaseOp ) ; Offset = EltSize * Offset0 ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) { DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data1 ) ; Width += getOpSize ( LdSt , DataOpIdx ) ; } else { Width = getOpSize ( LdSt , DataOpIdx ) ; } } return true ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * RSrc = getNamedOperand ( LdSt , <STR_LIT> :: srsrc ) ; if ( ! RSrc ) return false ; BaseOps . push_back ( RSrc ) ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( BaseOp && ! BaseOp -> isFI ( ) ) BaseOps . push_back ( BaseOp ) ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; Offset = OffsetImm -> getImm ( ) ; const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset ) { if ( SOffset -> isReg ( ) ) BaseOps . push_back ( SOffset ) ; else Offset += SOffset -> getImm ( ) ; } DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdata ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; return true ; } if ( isMIMG ( LdSt ) ) { int SRsrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; BaseOps . push_back ( & LdSt . getOperand ( SRsrcIdx )


<s> if ( RI . getRegSizeInBits ( * DstRC ) == <NUM_LIT> ) { return RI . isSGPRClass ( DstRC ) ? <STR_LIT> : <STR_LIT> ; } else if ( RI . getRegSizeInBits ( * DstRC ) == <NUM_LIT> && RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ; } else if ( RI . getRegSizeInBits ( * DstRC ) == <NUM_LIT> && ! RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ; } return <STR_LIT>


<s> if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; auto RegClass = TID . OpInfo [ OpNum ] . RegClass ; bool IsAllocatable = false ; if ( TID . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) { const int VDstIdx = <STR_LIT> ( TID . Opcode , <STR_LIT>


<s> { MO_GOTPCREL , <STR_LIT> } , { MO_GOTPCREL32_LO , <STR_LIT> } , { MO_GOTPCREL32_HI , <STR_LIT> } , { MO_REL32_LO , <STR_LIT> } , { MO_REL32_HI , <STR_LIT> } , { MO_ABS32_LO , <STR_LIT> } ,


<s> ArrayRef < std :: pair < MachineMemOperand :: Flags , const


<s> switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; return MI . getOperand ( <NUM_LIT> ) . isReg ( ) || RI . isAGPR ( MRI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> static unsigned getVGPRSpillRestoreOpcode ( unsigned Size ) { switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> DefInst = nullptr ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { auto & Op1 = MI -> getOperand ( <NUM_LIT> ) ; if ( Op1 . isReg ( ) && Op1 . getReg ( ) . isVirtual ( ) ) { if ( Op1 . isUndef ( ) ) return nullptr ; RSR = getRegSubRegPair ( Op1 ) ; DefInst = MRI . getVRegDef ( RSR . Reg ) ; } break ; } default : if ( followSubRegDef ( * MI , RSR ) ) { if ( ! RSR . Reg ) return nullptr ; DefInst = MRI . getVRegDef (


<s> bool <ISA_LIT>InstrInfo :: hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || isEXP ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) )


<s> int Op32 = <STR_LIT> ( Opcode ) ; if ( Op32 == - <NUM_LIT> ) return false ; return pseudoToMCOpcode ( Op32 )


<s> if ( Opcode == <STR_LIT> && ST . hasGFX90AInsts ( ) ) return false ; int Op32 = <STR_LIT> ( Opcode ) ; if ( Op32 == - <NUM_LIT>


<s> if ( ! Def -> definesRegister ( SrcReg , & RI ) ) continue ; if ( Def -> getOpcode ( ) != <STR_LIT> ) break ; MachineOperand & DefOp = Def -> getOperand ( <NUM_LIT> ) ; assert ( DefOp . isReg ( ) || DefOp . isImm ( ) ) ; if ( DefOp . isReg ( ) ) { bool SafeToPropagate = true ; for ( auto I = Def ; I != MI && SafeToPropagate ; ++ I ) if ( I -> modifiesRegister ( DefOp . getReg ( ) , & RI ) ) SafeToPropagate = false ; if ( ! SafeToPropagate ) break ; DefOp . setIsKill ( false ) ; } MachineInstrBuilder Builder = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , DestReg ) . add ( DefOp ) ; if ( ImpDefSuperReg ) Builder . addReg ( ImpDefSuperReg , RegState :: Define | RegState :: Implicit ) ; if ( ImpUseSuperReg ) { Builder . addReg ( ImpUseSuperReg , getKillRegState ( KillSrc ) | RegState :: Implicit ) ; } return ; } RS . enterBasicBlock ( MBB ) ; RS . forward ( MI ) ; unsigned MaxVGPRs = RI . getRegPressureLimit ( & <STR_LIT> , * MBB . getParent ( ) ) ; unsigned RegNo = DestReg % <NUM_LIT> ; Register Tmp = <STR_LIT> ; assert ( MBB . getParent ( ) -> getRegInfo ( ) . isReserved ( Tmp ) && <STR_LIT> ) ; while ( RegNo -- && RS . FindUnusedReg ( & <STR_LIT> ) ) { Register Tmp2 = RS . scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; if ( ! Tmp2 || RI . getHWRegIndex ( Tmp2 ) >= MaxVGPRs ) break ; Tmp = Tmp2 ; RS . setRegUsed ( Tmp ) ; } unsigned TmpCopyOp = <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) { TmpCopyOp = <STR_LIT> ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; } MachineInstrBuilder UseBuilder = BuildMI ( MBB , MI , DL , TII . get ( TmpCopyOp ) , Tmp ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( ImpUseSuperReg ) { UseBuilder . addReg ( ImpUseSuperReg , getKillRegState ( KillSrc ) | RegState :: Implicit ) ; } MachineInstrBuilder DefBuilder = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> )

, DestReg ) . addReg ( Tmp , RegState :: Kill ) ;


<s> BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . addReg ( SrcReg ) ; return Reg


<s> BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . addReg


<s> MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , PCReg ) ; auto & MCCtx = MF -> getContext ( ) ; MCSymbol * PostGetPCLabel = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; GetPC -> setPostInstrSymbol ( * MF , PostGetPCLabel ) ; MCSymbol * OffsetLo = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; MCSymbol * OffsetHi = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addSym ( OffsetLo , MO_FAR_BRANCH_OFFSET ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addSym ( OffsetHi , MO_FAR_BRANCH_OFFSET ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( PCReg ) ; RS -> enterBasicBlockEnd ( MBB ) ; Register Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false , <NUM_LIT> , false ) ; if ( Scav ) { RS -> setRegUsed ( Scav ) ; MRI . replaceRegWith ( PCReg , Scav ) ; MRI . clearVirtRegs ( ) ; } else { const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; TRI -> spillEmergencySGPR ( GetPC , RestoreBB , <STR_LIT> , RS ) ; MRI . replaceRegWith ( PCReg , <STR_LIT> ) ; MRI . clearVirtRegs


<s> BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . addReg ( SrcReg ) ; return


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . addReg ( SrcReg ) ; return Reg


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { insertNoops ( MBB , MI , <NUM_LIT>


<s> void <ISA_LIT>InstrInfo :: insertNoops ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Quantity ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; while ( Quantity > <NUM_LIT> ) { unsigned Arg = std :: min ( Quantity , <NUM_LIT> ) ; Quantity -=


<s> void <ISA_LIT>InstrInfo :: insertNoops ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Quantity ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; while ( Quantity > <NUM_LIT> ) { unsigned Arg = std :: min ( Quantity ,


<s> std :: swap ( TrueReg , FalseReg ) ; } MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( DstReg ) ; unsigned DstSize = RI . getRegSizeInBits ( * DstRC ) ; if ( DstSize == <NUM_LIT> ) { MachineInstr * Select ; if ( Pred == SCC_TRUE ) { Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( TrueReg ) . addReg ( FalseReg ) ; } else { Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; } preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } if ( DstSize == <NUM_LIT> && Pred == SCC_TRUE ) { MachineInstr * Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( TrueReg ) . addReg ( FalseReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { if ( NElts % <NUM_LIT> ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; } else { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; NElts /= <NUM_LIT> ; } } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) ; I = MIB -> getIterator ( ) ; SmallVector < Register , <NUM_LIT> > Regs ; for ( int Idx = <NUM_LIT> ; Idx != NElts


<s> if ( Idx == - <NUM_LIT> ) return false ; const auto RCID = MI . getDesc ( ) . OpInfo [ Idx


<s> bool <ISA_LIT>InstrInfo :: isHighLatencyDef ( int Opc ) const { return get ( Opc ) . mayLoad ( ) && ( isMUBUF ( Opc ) || isMTBUF ( Opc ) || isMIMG ( Opc ) || isFLAT


<s> bool <ISA_LIT>InstrInfo :: isIgnorableUse ( const MachineOperand & MO ) const { return MO . getReg ( ) == <STR_LIT> && MO . isImplicit ( ) && isVALU ( * MO

. getParent ( ) ) && ! resultDependsOnExec ( * MO . getParent ( ) ) ;


<s> return MO . getReg ( ) == <STR_LIT> && MO . isImplicit ( ) && isVALU ( * MO . getParent ( ) ) && ! resultDependsOnExec (


<s> if ( isMAI ( MI ) && ST . hasMFMAInlineLiteralBug ( ) && OpNo == ( unsigned ) <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src2 ) ) return false ; return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ; } if ( ! RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ) return false ; if ( ! isVOP3 ( MI ) || ! <STR_LIT> ( InstDesc , OpNo ) ) return true ; return ST . hasVOP3Literal (


<s> if ( ST . hasFlatSegmentOffsetBug ( ) && FlatVariant == <STR_LIT> && ( AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS || AddrSpace == <ISA_LIT>AS :: GLOBAL_ADDRESS ) ) return false ; bool Signed = FlatVariant != <STR_LIT> ; if ( ST . hasNegativeScratchOffsetBug ( ) && FlatVariant == <STR_LIT> ) Signed = false ; if ( ST . hasNegativeUnalignedScratchOffsetBug ( ) && FlatVariant == <STR_LIT> && Offset < <NUM_LIT> && ( Offset % <NUM_LIT> ) != <NUM_LIT> ) { return


<s> if ( ST . hasNegativeScratchOffsetBug ( ) && FlatVariant == <STR_LIT> ) Signed = false ; if ( ST . hasNegativeUnalignedScratchOffsetBug ( ) && FlatVariant == <STR_LIT> && Offset < <NUM_LIT> && ( Offset % <NUM_LIT> ) != <NUM_LIT> ) { return false ; } unsigned N = <STR_LIT> ( ST , Signed ) ; return Signed ? isIntN ( N , Offset ) : isUIntN ( N , Offset


<s> if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * DRC = RI . getRegClass ( OpInfo . RegClass ) ; if ( Reg . isPhysical ( ) ) return DRC -> contains ( Reg ) ; const TargetRegisterClass * RC = MRI . getRegClass ( Reg ) ; if ( MO .


<s> bool <ISA_LIT>InstrInfo :: isLegalVSrcOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO


<s> return ! MI . hasImplicitDef ( ) && MI . getNumImplicitOperands ( ) == MI . getDesc ( ) . getNumImplicitUses ( ) && ! MI . mayRaiseFPException ( ) ; } return


<s> unsigned OpSubReg = Op . getSubReg ( ) ; const TargetRegisterClass * OpRC = RI . getSubClassWithSubReg ( RI . getRegClassForReg ( MRI , OpReg ) , OpSubReg ) ; if ( DstRC == OpRC ) return ; Register DstReg = MRI . createVirtualRegister ( DstRC ) ; auto Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . add ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ; if ( Def -> isMoveImmediate ( ) && DstRC != & <STR_LIT> ) FoldImmediate ( * Copy , * Def , OpReg , & MRI ) ; bool ImpDef = Def -> isImplicitDef ( ) ; while ( ! ImpDef && Def && Def


<s> if ( ! SAddr || RI . isSGPRClass ( MRI . getRegClass ( SAddr -> getReg ( ) ) ) ) return ; if ( moveFlatAddrToVGPR ( MI


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Src0 . isReg ( ) && RI . isVGPR ( MRI , Src0 . getReg ( ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src0 ) ; Src0 . ChangeToRegister ( Reg , false ) ; } if ( Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } return ; } if ( Src0 . isReg ( ) && RI . isAGPR ( MRI , Src0 . getReg ( ) ) ) legalizeOpWithMove ( MI , Src0Idx ) ; if ( Src1 . isReg ( ) && RI . isAGPR ( MRI , Src1 . getReg ( ) ) ) legalizeOpWithMove ( MI , Src1Idx ) ; if ( isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src1 ) ) return ; if ( Opc == <STR_LIT> && Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; return ; } if ( HasImplicitSGPR || ! MI . isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } MI . setDesc ( get ( CommutedOpc ) ) ; Register Src0Reg = Src0 . getReg ( ) ; unsigned Src0SubReg = Src0 . getSubReg ( ) ; bool Src0Kill = Src0 . isKill ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 .


<s> unsigned Size = RI . getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; const TargetRegisterClass * VRC64 = RI . getVGPR64Class ( ) ; if ( RI . getCommonSubClass ( VRC64 , VRC ) ) VRC = VRC64 ; else VRC = & <STR_LIT> ; Register Reg = MRI . createVirtualRegister (


<s> MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = RI . getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; const TargetRegisterClass * VRC64 = RI . getVGPR64Class ( ) ; if ( RI . getCommonSubClass ( VRC64 , VRC ) ) VRC = VRC64 ; else VRC = & <STR_LIT> ; Register Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I


<s> } const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , Begin , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; MachineBasicBlock :: iterator AfterMI = MI ; ++ AfterMI ; for ( auto I = Begin ; I != AfterMI ; I ++ ) { for ( auto & MO : I -> uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * BodyBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , BodyBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( BodyBB ) ; BodyBB -> addSuccessor ( LoopBB ) ; BodyBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , End , MBB . end


<s> ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , BodyBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( BodyBB ) ; BodyBB -> addSuccessor ( LoopBB ) ; BodyBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , End , MBB . end ( ) ) ; BodyBB -> splice ( BodyBB -> begin ( ) , & MBB , Begin , MBB . end ( ) ) ; MBB . addSuccessor ( LoopBB ) ; if ( MDT ) { MDT -> addNewBlock ( LoopBB , & MBB ) ; MDT -> addNewBlock ( BodyBB , LoopBB ) ; MDT -> addNewBlock ( RemainderBB , BodyBB ) ; for ( auto & Succ : RemainderBB -> successors ( ) ) { if ( MDT -> properlyDominates ( & MBB , Succ ) ) { MDT -> changeImmediateDominator ( Succ , RemainderBB ) ; } } } emitLoadSRsrcFromVGPRLoop ( TII , MRI , MBB , * LoopBB , * BodyBB , DL , Rsrc ) ; MachineBasicBlock :: iterator First = RemainderBB -> begin ( ) ; BuildMI ( * RemainderBB , First , DL , TII . get ( MovExecOpc ) , Exec ) . addReg ( SaveExec ) ; return


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; if ( ST . hasDLInsts ( ) ) { Register NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src0 , MRI , DL ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src1 , MRI , DL ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . add ( Src0 ) . add ( Src1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; addUsersToMoveToVALUWorklist ( NewDest , MRI , Worklist ) ; } else { bool Src0IsSGPR = Src0 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src0 . getReg ( ) ) ) ; bool Src1IsSGPR = Src1 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src1 . getReg ( ) ) ) ; MachineInstr * Xor ; Register Temp = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( Src0IsSGPR ) { BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Temp ) . add ( Src0 ) ; Xor = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Temp ) . add ( Src1 ) ; } else if ( Src1IsSGPR ) { BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Temp ) . add ( Src1 ) ; Xor = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) .


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RegClass = MRI . getRegClass ( DestReg ) ; if ( RegClass == & <STR_LIT> || RegClass == & <STR_LIT> || RegClass == & <STR_LIT> || RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass == & <STR_LIT> || RegClass == & <STR_LIT> || RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass -> hasSuperClassEq ( & <STR_LIT> ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RegClass ) ) { if ( RI . getRegSizeInBits ( * RegClass ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize =


<s> if ( MI . isCall ( ) ) return true ; if ( ! isTargetSpecificOpcode ( MI . getOpcode ( ) ) ) return true ; return ! isSALU ( MI ) || MI . readsRegister (


<s> return MI . readsRegister ( <STR_LIT> , & RI ) ; } if ( MI . isCall ( ) ) return true ; if ( ! isTargetSpecificOpcode ( MI . getOpcode ( )


<s> if ( BaseOps1 . front ( ) -> isIdenticalTo ( * BaseOps2 . front ( ) ) ) return true ; if ( ! MI1 . hasOneMemOperand ( ) || ! MI2 . hasOneMemOperand ( ) ) return false ; auto MO1 = * MI1 . memoperands_begin ( ) ; auto MO2 = * MI2 . memoperands_begin (


<s> if ( const MCPhysReg * ImpDef = MI . getDesc ( ) . getImplicitDefs ( ) ) { for ( ; ImpDef && * ImpDef ; ++ ImpDef ) { if ( * ImpDef == <STR_LIT> ) return true ; } } return false


<s> if ( OldVAddrIdx == NewVAddrIdx ) { MachineOperand & NewVAddr = Inst . getOperand ( NewVAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . moveOperands ( & NewVAddr , & SAddr , <NUM_LIT> ) ; Inst . removeOperand ( OldSAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . addRegOperandToUseList ( & NewVAddr ) ; } else { assert ( OldSAddrIdx == NewVAddrIdx ) ; if ( OldVAddrIdx >= <NUM_LIT> ) { int NewVDstIn = <STR_LIT> ( NewOpc , <STR_LIT> :: vdst_in ) ; if ( NewVDstIn != - <NUM_LIT> ) { int OldVDstIn = <STR_LIT> ( Opc , <STR_LIT> :: vdst_in ) ; Inst . untieRegOperand ( OldVDstIn ) ; } Inst . removeOperand ( OldVAddrIdx ) ; if ( NewVDstIn != - <NUM_LIT> ) { int NewVDst = <STR_LIT> ( NewOpc , <STR_LIT> :: vdst


<s> unsigned Opc = Inst . getOpcode ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; unsigned NewOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; Inst . removeOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MRI . replaceRegWith ( OldDstReg


<s> } } if ( isMAI ( Opcode ) ) { int MFMAOp = <STR_LIT> ( Opcode ) ; if ( MFMAOp != - <NUM_LIT> ) Opcode = MFMAOp ; } int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - <NUM_LIT> ; if ( ST . hasGFX940Insts ( ) ) NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp == ( uint16_t ) - <NUM_LIT> ) NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp == ( uint16_t ) - <NUM_LIT> ) NMCOp = <STR_LIT>


<s> if ( MI . isBranch ( ) || MI . isReturn ( ) ) { RemovedSize += getInstSizeInBytes ( MI ) ; MI . eraseFromParent ( ) ; ++


<s> MachineFunction * MF = MBB . getParent ( ) ; DiagnosticInfoUnsupported IllegalCopy ( MF -> getFunction ( ) , Msg , DL , DS_Error ) ; LLVMContext & C = MF -> getFunction ( )


<s> const MachineInstr & FirstLdSt = * BaseOps1 . front ( ) -> getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOps2 . front ( ) -> getParent ( ) ; if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; } else if ( ! BaseOps1 . empty ( ) || ! BaseOps2 . empty ( ) ) { return false ; } const unsigned LoadSize = NumBytes / NumLoads ; const unsigned NumDWORDs = ( ( LoadSize + <NUM_LIT> ) / <NUM_LIT> ) * NumLoads ; return NumDWORDs <=


<s> bool <ISA_LIT>InstrInfo :: shouldClusterMemOps ( ArrayRef < const MachineOperand * > BaseOps1 , ArrayRef < const MachineOperand * > BaseOps2 , unsigned NumLoads , unsigned NumBytes ) const { if ( ! BaseOps1 . empty ( ) && ! BaseOps2 . empty ( ) ) { const MachineInstr & FirstLdSt = * BaseOps1 . front ( ) -> getParent ( ) ; const MachineInstr & SecondLdSt = * BaseOps2 .


<s> } if ( MI . isPreISelOpcode ( ) || <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo ::

isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const GCNSubtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) , ST ( ST ) { SchedModel . init ( &


<s> int64_t ImmField = <NUM_LIT> ; bool Signed = FlatVariant != <STR_LIT> ; if ( ST . hasNegativeScratchOffsetBug ( ) && FlatVariant == <STR_LIT> ) Signed = false ; const unsigned NumBits = <STR_LIT> ( ST , Signed ) ; if ( Signed ) { int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; if ( ST . hasNegativeUnalignedScratchOffsetBug ( ) && FlatVariant == <STR_LIT> && ImmField < <NUM_LIT> && ( ImmField % <NUM_LIT> ) != <NUM_LIT> ) { RemainderOffset += ImmField % <NUM_LIT> ; ImmField -= ImmField % <NUM_LIT> ; } } else if ( COffsetVal >=


<s> Register CarryReg = MRI . createVirtualRegister ( CarryRC ) ; Register DeadCarryReg = MRI . createVirtualRegister ( CarryRC ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const TargetRegisterClass * Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 )

. addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;


<s> const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; legalizeOperands ( * LoHalf , MDT


<s> MachineBasicBlock :: iterator MII = Inst ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; Register MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> ,


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; Register DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; Register DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; Register FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . insert ( & LoHalf ) ; Worklist . insert ( & HiHalf ) ; addUsersToMoveToVALUWorklist ( FullDestReg ,


<s> const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; Register DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; Register DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) ; if ( Swap ) std :: swap ( DestSub0 , DestSub1 ) ; Register FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg


<s> const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; Register DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; Register DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 )


<s> Register Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Interm ) . add ( Src1 ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , NewDest ) . add ( Src0 ) . addReg ( Interm ) ; Worklist . insert ( & Not ) ; Worklist . insert ( & Op ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; addUsersToMoveToVALUWorklist ( NewDest , MRI ,


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; Register NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , Interm ) . add ( Src0 ) . add ( Src1 ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) ; Worklist . insert ( & Op ) ; Worklist . insert ( & Not ) ; MRI . replaceRegWith ( Dest . getReg ( ) ,


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( SrcReg != <STR_LIT> && <STR_LIT> ) ; assert ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( SrcReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID


<s> void <ISA_LIT>InstrInfo :: swapOperands ( MachineInstr & Inst ) const { assert ( Inst . getNumExplicitOperands ( ) == <NUM_LIT> ) ; MachineOperand Op1 = Inst . getOperand


<s> assert ( Inst . getNumExplicitOperands ( ) == <NUM_LIT> ) ; MachineOperand Op1 = Inst . getOperand ( <NUM_LIT> ) ; Inst . removeOperand ( <NUM_LIT> ) ; Inst . addOperand ( Op1 )


<s> bool IsDebug = RegOp . isDebug ( ) ; if ( NonRegOp . isImm ( ) ) RegOp . ChangeToImmediate ( NonRegOp . getImm ( ) ) ; else if ( NonRegOp . isFI ( ) ) RegOp . ChangeToFrameIndex ( NonRegOp . getIndex ( ) ) ; else if ( NonRegOp . isGlobal ( ) ) { RegOp . ChangeToGA ( NonRegOp . getGlobal ( ) , NonRegOp . getOffset ( ) , NonRegOp


<s> static void updateLiveVariables ( LiveVariables * LV , MachineInstr & MI , MachineInstr & NewMI ) { if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI


<s> bool <ISA_LIT>InstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , const MCOperandInfo & OpInfo ) const { if ( MO . isImm ( ) ) return ! isInlineConstant ( MO , OpInfo ) ; if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( MO . getReg ( ) . isVirtual ( ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; if ( MO . isImplicit ( ) ) { return MO . getReg ( ) == <STR_LIT> || MO . getReg (

) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ;


<s> if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( MO . getReg ( ) . isVirtual ( ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( MO . getReg ( ) == <STR_LIT> )


<s> if ( Src2 ) { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) ) return false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Src2 -> isReg ( ) || ! RI . isVGPR ( MRI , Src2 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src2_modifiers ) ) return false ; break ; case <STR_LIT> : break ; } } const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 && ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) ) ) return false ; if ( hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers


<s> static bool getFoldableImm ( const MachineOperand * MO , int64_t & Imm ) { if ( ! MO -> isReg ( ) ) return false ; const MachineFunction * MF = MO -> getParent ( ) -> getParent (


<s> if ( ! MO -> isReg ( ) ) return false ; const MachineFunction * MF = MO -> getParent ( ) -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; return getFoldableImm ( MO -> getReg ( ) ,


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg ) ; } unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; RCID = adjustAllocatableRegClass ( ST , MRI


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getRegClass ( const MCInstrDesc & TID , unsigned OpNum , const TargetRegisterInfo * TRI , const MachineFunction & MF ) const { if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; auto RegClass = TID . OpInfo [ OpNum ] . RegClass ; bool IsAllocatable = false ; if ( TID . TSFlags & ( <STR_LIT> | <STR_LIT>