<s> unsigned NumElts = Store -> getMemoryVT ( ) . getVectorNumElements ( ) ; SDLoc SL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned EltSize = MemEltVT . getStoreSize ( ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( <STR_LIT> , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , SL , <STR_LIT> ) ) ; SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL ,

PtrVT , Store -> getBasePtr ( ) , Offset ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRIN<ISA_LIT>C_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT>


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) return <NUM_LIT> ; unsigned SignBits = <NUM_LIT> - Width -> getZExtValue ( ) + <NUM_LIT> ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Offset || ! Offset -> isNullValue ( ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; return Width ? <NUM_LIT> - ( Width -> getZExtValue ( ) & <NUM_LIT> ) : <NUM_LIT> ; } case <STR_LIT> : case


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; } if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op


<s> bool <ISA_LIT>TargetLowering :: isHWTrueValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> isExactlyValue


<s> EVT MemVT = Store -> getMemoryVT ( ) ; if ( Store -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS && MemVT . bitsLT ( <STR_LIT> ) ) { unsigned Mask = <NUM_LIT> ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask


<s> DP << <STR_LIT> << getDescription ( ) << <STR_LIT>


<s> SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( )


<s> return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc (


<s> return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG


<s> unsigned <ISA_LIT>TargetLowering :: numBitsSigned ( SDValue Op , SelectionDAG


<s> case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f /


<s> if ( Opc == <STR_LIT> ) Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> - Width ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; Known . Zero = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , LHSKnown , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , RHSKnown , Depth + <NUM_LIT> ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , <NUM_LIT> ) ) ; unsigned LHSValBits = <NUM_LIT> - std :: max ( LHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned RHSValBits = <NUM_LIT> - std :: max ( RHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned MaxValBits = std :: min ( LHSValBits


<s> if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , Reason + FuncName , CLI . DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ; if ( ! CLI . IsTailCall ) { for ( unsigned I = <NUM_LIT> , E = CLI . Ins . size ( ) ; I != E ; ++ I ) InVals . push_back ( DAG . getUNDEF ( CLI . Ins [ I ] . VT ) ) ; } return DAG . getEntryNode


<s> case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isTypeLegal ( <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } if ( VT != <STR_LIT> ) break ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> : if ( ! isOrEquivalentToAdd ( DAG , LHS ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( ConstantSDNode * C2 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ) { SDValue Shl = DAG . getNode ( <STR_LIT> , SL , VT , LHS -> getOperand ( <NUM_LIT> ) , SDValue ( RHS , <NUM_LIT> ) ) ; SDValue C2V = DAG . getConstant ( C2 -> getAPIntValue ( ) <<


<s> SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; switch ( LHS -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isTypeLegal ( <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } if ( VT != <STR_LIT> ) break ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> : if ( ! isOrEquivalentToAdd ( DAG


<s> case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( BitsFrom , Demanded , TLO ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; } case <STR_LIT> : return performLoadCombine ( N , DCI ) ; case <STR_LIT> : return performStoreCombine ( N , DCI ) ; case


<s> if ( getTargetMachine ( ) . Options . UnsafeFPMath ) return true ; if ( const auto * BO = dyn_cast < BinaryWithFlagsSDNode > ( Op

) ) return BO -> Flags . hasNoSignedZeros ( ) ;


<s> Op . getNode ( ) -> dump ( ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC


<s> SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand (


<s> return performMulLoHi24Combine ( N , DCI ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( )


<s> SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; else LHS = LHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOpcode ( ) != <STR_LIT> ) RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; else RHS = RHS . getOperand ( <NUM_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , SL , VT , LHS , RHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) LHS = LHS . getOperand ( <NUM_LIT> ) ; else if ( RHS . getOpcode ( ) == <STR_LIT> ) RHS = RHS . getOperand ( <NUM_LIT> ) ; else RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; SDValue Res = DAG . getNode ( Opc , SL , VT , LHS , RHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : { if ( ! mayIgnoreSignedZero ( N0 ) ) return SDValue (


<s> if ( SDValue Folded = foldFreeOpFromSelect ( DCI , SDValue ( N , <NUM_LIT> ) ) ) return Folded ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; if ( ( DAG . isConstantValueOfAnyType ( True ) || DAG . isConstantValueOfAnyType ( True ) ) && ( ! DAG . isConstantValueOfAnyType ( False ) && ! DAG . isConstantValueOfAnyType ( False ) ) ) { SDLoc SL ( N ) ; <STR_LIT> NewCC = getSetCCInverse ( cast < CondCodeSDNode > ( CC ) -> get ( ) , LHS . getValueType ( ) . isInteger ( ) ) ; SDValue NewCond = DAG . getSetCC ( SL , Cond . getValueType ( ) , LHS , RHS , NewCC ) ; return DAG . getNode ( <STR_LIT> , SL , VT , NewCond , False , True ) ; } } if ( VT == <STR_LIT> && Cond


<s> else std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad ) ; DCI . CombineTo ( N , BC , NewLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT>


<s> if ( ! SN -> isSimple ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; unsigned Align = SN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) )


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { R = dyn_cast < RegisterSDNode > ( N ) ; } else { R = dyn_cast < RegisterSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; } if ( R ) { const MachineFunction * MF = FLI -> MF ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const <ISA_LIT>RegisterInfo & TRI = ST . getInstrInfo ( ) -> getRegisterInfo ( ) ; unsigned Reg = R -> getReg ( ) ; if ( TRI . isPhysicalRegister ( Reg ) ) return TRI . isVGPR ( MRI , Reg ) ; if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == Subtarget -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ) return true ; } break ; case <STR_LIT>


<s> if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode


<s> if ( DestVT == <STR_LIT> && ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) ) { SDLoc DL ( Op ) ; SDValue FpToInt32 = DAG . getNode ( OpOpcode , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToInt32 ) ; } if ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> ) ) { SDLoc DL (


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRIN<ISA_LIT>C_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand (


<s> default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT>


<s> SDValue NEG_RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RCP_LO ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; const EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue CmpRcpHiZero = DAG . getSetCC ( DL , CCVT , RCP_HI , Zero , <STR_LIT> ) ; SDValue ABS_RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , CmpRcpHiZero , NEG_RCP_LO , RCP_LO ) ; SDValue E = DAG . getNode ( <STR_LIT> , DL , VT , ABS_RCP_LO , RCP ) ; SDValue RCP_A_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ; SDValue RCP_S_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , DL , VT , CmpRcpHiZero , RCP_A_E , RCP_S_E ) ; SDValue Quotient = DAG . getNode ( <STR_LIT> , DL , VT , Tmp0 , Num ) ; SDValue Num_S_Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , Den ) ; SDValue Remainder = DAG . getNode ( <STR_LIT> , DL , VT , Num , Num_S_Remainder ) ; SDValue Remainder_GE_Den = DAG . getSetCC ( DL , CCVT , Remainder , Den , <STR_LIT> ) ; SDValue Remainder_GE_Zero = DAG . getSetCC ( DL , CCVT , Num , Num_S_Remainder , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , CCVT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT ,


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( isConstantFPZero ( RHS ) ) return SDValue ( ) ; SDValue NegLHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; unsigned Opposite = inverseMinMax ( Opc ) ; SDValue Res = DAG . getNode ( Opposite , SL , VT , NegLHS , NegRHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( Opc , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( Opc , SL , VT , Neg , N0 -> getFlags ( ) ) ; } case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Neg , N0 . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : { SDLoc SL ( N ) ; SDValue Src = N0 . getOperand (


<s> MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; Type * EltType = GV -> getValueType ( ) ; unsigned Size = DL . getTypeAllocSize ( EltType ) ; unsigned Alignment = DL . getPrefTypeAlignment ( EltType ) ; MVT PrivPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; MVT ConstPtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; int FI = FrameInfo -> CreateStackObject ( Size , Alignment , false ) ; SDValue InitPtr = DAG . getFrameIndex ( FI , PrivPtrVT ) ; const GlobalVariable * Var = cast < GlobalVariable > ( GV ) ; if ( ! Var -> hasInitializer ( ) ) { return DAG . getZExtOrTrunc ( InitPtr , SDLoc ( Op ) , ConstPtrVT ) ; } const Constant * Init = Var -> getInitializer ( ) ; SmallVector < SDNode * , <NUM_LIT> > WorkList ; for ( SDNode :: use_iterator I = DAG . getEntryNode ( ) -> use_begin ( ) , E = DAG . getEntryNode ( ) -> use_end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) continue ; WorkList . push_back ( * I ) ; } SDValue Chain = LowerConstantInitializer ( Init , GV , InitPtr , DAG . getEntryNode ( ) , DAG ) ; for ( SmallVector < SDNode * , <NUM_LIT> > :: iterator I = WorkList . begin ( ) , E = WorkList . end ( ) ; I != E ; ++ I ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> ; i < ( * I ) -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( ( * I ) -> getOperand ( i ) ) ; } DAG . UpdateNodeOperands ( * I , Ops ) ; } return DAG . getZExtOrTrunc ( InitPtr , SDLoc ( Op ) ,


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand (


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case


<s> case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = ( LHS == True ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , LHS , RHS ) ; } default : return SDValue (


<s> SDValue <ISA_LIT>TargetLowering :: LowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget -> getFrameLowering ( ) ; FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FIN -> getIndex ( ) ; unsigned Offset = TFL -> getFrameIndexOffset ( MF


<s> if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT . isVector ( ) ) { assert ( ! RegisterVT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = RegisterVT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ; MemVT = EVT :: getVectorVT ( State . getContext ( ) , ScalarVT , NumElements ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) MemVT = MemVT . getScalarType ( ) ; if ( MemVT . isExtended ( ) ) { assert ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) ; MemVT = MemVT . getPow2VectorType ( State . getContext ( ) ) ; } unsigned PartOffset = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumRegs ; ++ i ) { State . addLoc ( CCValAssign :: getCustomMem ( InIndex ++ , RegisterVT , BasePartOffset + PartOffset , MemVT . getSimpleVT


<s> ExplicitArgOffset = alignTo ( ExplicitArgOffset , Align ) + AllocSize ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , ArgVT ) ; if ( ! Subtarget -> isAmdHsaOS ( ) && ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) ) { MemVT = ArgVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; } else if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ; } else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) { MemVT = ArgVT . getScalarType ( ) ; } else if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { unsigned MemoryBits = ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT . isVector ( ) ) { assert ( ! RegisterVT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = RegisterVT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) ,


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned ExplicitArgOffset = ST . getExplicitKernelArgOffset ( MF . getFunction ( ) ) ; unsigned Alignment = ST . getAlignmentForImplicitArgPtr ( ) ; uint64_t ArgOffset = alignTo ( MFI -> getExplicitKernArgSize ( ) , Alignment ) +


<s> uint32_t <ISA_LIT>TargetLowering :: getImplicitParameterOffset ( const MachineFunction & MF , const ImplicitParameter Param ) const { const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned ExplicitArgOffset = ST . getExplicitKernelArgOffset (


<s> if ( In . VT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( In . VT . isVector ( ) ) { assert ( ! In . VT . getScalarType ( ) . isFloatingPoint ( ) ) ; unsigned NumElements = In . VT . getVectorNumElements ( ) ; assert ( MemoryBits % NumElements == <NUM_LIT> ) ; EVT ScalarVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits / NumElements ) ; MemVT = EVT :: getVectorVT ( State . getContext ( ) , ScalarVT , NumElements ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } if ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) MemVT = MemVT . getScalarType ( ) ; if ( MemVT . isExtended ( ) ) { assert ( MemVT . isVector ( ) && MemVT . getVectorNumElements ( ) == <NUM_LIT> ) ; MemVT = MemVT . getPow2VectorType ( State


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return


<s> case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op ,


<s> Op -> dump ( & DAG ) ; llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG


<s> static bool allocateCCRegs ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State , const TargetRegisterClass * RC , unsigned NumRegs ) { ArrayRef < MCPhysReg > RegList = makeArrayRef ( RC -> begin ( ) , NumRegs ) ; unsigned RegResult = State . AllocateReg ( RegList ) ; if ( RegResult == <STR_LIT> ) return false ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , RegResult , LocVT , LocInfo ) ) ; return true


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT> , <NUM_LIT> ) ; } default : return false


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT>


<s> for ( const Argument & Arg : Fn . args ( ) ) { Type * BaseArgTy = Arg . getType ( ) ; unsigned Align = DL . getABITypeAlignment ( BaseArgTy ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; unsigned AllocSize = DL . getTypeAllocSize ( BaseArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , Align ) + ExplicitOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , Align ) + AllocSize ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( * this , DL , BaseArgTy , ValueVTs , & Offsets , ArgOffset ) ; for ( unsigned Value = <NUM_LIT> , NumValues = ValueVTs . size ( ) ; Value != NumValues ; ++ Value ) { uint64_t BasePartOffset = Offsets [ Value ] ; EVT ArgVT = ValueVTs [ Value ] ; EVT MemVT = ArgVT ; MVT RegisterVT = getRegisterTypeForCallingConv ( Ctx , CC , ArgVT ) ; unsigned NumRegs = getNumRegistersForCallingConv ( Ctx , CC , ArgVT ) ; if ( NumRegs == <NUM_LIT> ) { if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { MemVT = ArgVT ; } } else if ( ArgVT . isVector ( ) && RegisterVT . isVector ( ) && ArgVT . getScalarType ( ) == RegisterVT . getScalarType ( ) ) { assert ( ArgVT . getVectorNumElements ( ) > RegisterVT . getVectorNumElements ( ) ) ; MemVT = RegisterVT ; } else if ( ArgVT . isVector ( ) && ArgVT . getVectorNumElements ( ) == NumRegs ) { MemVT = ArgVT . getScalarType ( ) ; } else if ( ArgVT . isExtended ( ) ) { MemVT = RegisterVT ; } else { unsigned MemoryBits = ArgVT . getStoreSizeInBits ( ) / NumRegs ; assert ( ArgVT . getStoreSizeInBits ( ) % NumRegs == <NUM_LIT> ) ; if ( RegisterVT . isInteger ( ) ) { MemVT = EVT :: getIntegerVT ( State . getContext ( ) , MemoryBits ) ; } else if ( RegisterVT .


<s> case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_LS : return CC_<ISA_LIT> ; case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return CC_<ISA_LIT>_Func ; default : report_fatal_error ( <STR_LIT>


<s> bool LHSPositive = ! ! ( LHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ; } if ( Negative ) Known . One . setHighBits ( <NUM_LIT> - MaxValBits ) ; else Known . Zero . setHighBits ( <NUM_LIT> - MaxValBits ) ; break ; } case <STR_LIT> : { ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CMask ) return ; KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , LHSKnown , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , RHSKnown , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) { SelBits *= <NUM_LIT> ; Known . One |= ( ( RHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( RHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits < <NUM_LIT> ) { SelBits = ( SelBits & <NUM_LIT> ) * <NUM_LIT> ; Known . One |= ( ( LHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( LHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits == <NUM_LIT> ) { Known . Zero |= <NUM_LIT> << I ; } else if (


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) return <NUM_LIT> ; unsigned SignBits = <NUM_LIT> - Width -> getZExtValue ( ) + <NUM_LIT> ; if ( ! isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand (


<s> SDValue CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc (


<s> SDValue CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG .


<s> return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG . getEntryNode ( ) )


<s> LLVM_READNONE static bool fnegFoldsIntoOp ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> <ISA_LIT>AS get<ISA_LIT>AS ( ) const


<s> MVT getFenceOperandTy ( const DataLayout & DL ) const override { return <STR_LIT>


<s> if ( ! GVar || ! GVar -> hasInitializer ( ) ) return false ; return ! isa < UndefValue > ( GVar


<s> switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> static bool isConstantFPZero ( SDValue N ) { if ( const ConstantFPSDNode * C = isConstOrConstSplatFP ( N ) ) return C -> isZero


<s> return ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> || ( ScalarVT == <STR_LIT> && Subtarget -> has16BitInsts (


<s> bool isFsqrtCheap ( SDValue Operand , SelectionDAG &


<s> case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) && DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return false ; } case <STR_LIT> : case <STR_LIT> : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SNaN ; case <STR_LIT> : case <STR_LIT> : { return SNaN ; } case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : return true


<s> assert ( LoadTy . getSizeInBits ( ) == CastTy . getSizeInBits ( ) ) ; if ( LoadTy . getScalarType ( ) == <STR_LIT> ) return false ; unsigned LScalarSize = LoadTy . getScalarSizeInBits ( ) ; unsigned CastScalarSize = CastTy . getScalarSizeInBits ( ) ; return ( LScalarSize < CastScalarSize ) ||


<s> return true ; case <STR_LIT> : { unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrID ) { default : return false ; case <STR_LIT> : case <STR_LIT> : return true ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT


<s> if ( Arg . isRegister ( ) ) return CreateLiveInRegister ( DAG ,

RC , Arg . getRegister ( ) , VT , SL ) ;


<s> auto SrcPtrInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue Ptr = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( VT , SL , DAG . getEntryNode ( ) , Ptr , SrcPtrInfo , <NUM_LIT> , MachineMemOperand :: MODereferenceable |


<s> SDValue <ISA_LIT>TargetLowering :: loadStackInputValue ( SelectionDAG & DAG , EVT VT , const SDLoc & SL , int64_t Offset ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( VT . getStoreSize ( ) , Offset , true ) ; auto SrcPtrInfo = MachinePointerInfo :: getStack ( MF , Offset


<s> DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadLDSDecl ) ; } assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * GV ) ; return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadInit ) ; return SDValue (


<s> if ( Flags . isDefined ( ) ) return Flags . hasNoSignedZeros ( ) ; return false


<s> case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performTruncateCombine ( N , DCI ) ; case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { simplifyI24 ( N , <NUM_LIT> , DCI ) || simplifyI24 ( N , <NUM_LIT> , DCI ) ; return SDValue ( ) ; } case <STR_LIT> : case <STR_LIT> : return performMulLoHi24Combine ( N , DCI ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : return performFAbsCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return


<s> } case <STR_LIT> : case <STR_LIT> : { if ( ! mayIgnoreSignedZero ( N0 ) ) return SDValue ( ) ; SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue MHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) LHS = LHS . getOperand ( <NUM_LIT> ) ; else if ( MHS . getOpcode ( ) == <STR_LIT> ) MHS = MHS . getOperand ( <NUM_LIT> ) ; else MHS = DAG . getNode ( <STR_LIT> , SL , VT , MHS ) ; if ( RHS . getOpcode ( ) != <STR_LIT> ) RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; else RHS = RHS . getOperand ( <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Opc , SL , VT , LHS , MHS , RHS ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( isConstantFPZero ( RHS ) ) return SDValue ( ) ; SDValue NegLHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; unsigned Opposite = inverseMinMax ( Opc ) ; SDValue Res = DAG . getNode ( Opposite , SL , VT , NegLHS , NegRHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( Opc , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( Opc , SL , VT , Neg , N0 -> getFlags ( ) ) ; } case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( )


<s> std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL ,


<s> SDLoc SL ( N ) ; SDValue MulLo = DAG . getNode ( MulLoOpc , SL , <STR_LIT> , N0 , N1 ) ; SDValue MulHi = DAG . getNode ( MulHiOpc , SL , <STR_LIT> , N0 , N1 ) ; return DAG . getMergeValues ( { MulLo , MulHi } , SL


<s> SDValue <ISA_LIT>TargetLowering :: performMulLoHi24Combine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; if ( simplifyI24 ( N , <NUM_LIT> , DCI ) || simplifyI24 ( N , <NUM_LIT> , DCI ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; bool Signed = ( N -> getOpcode ( ) == <STR_LIT> ) ; unsigned MulLoOpc = Signed ? <STR_LIT> : <STR_LIT> ; unsigned MulHiOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDLoc SL ( N


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( ! RHSVal ) return LHS ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; switch ( LHS -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } if ( VT != <STR_LIT> ) break ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } } if ( VT != <STR_LIT> )


<s> ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( ! RHSVal ) return LHS ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; switch ( LHS -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL ,

<STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performSrlCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; unsigned ShiftAmt = RHS -> getZExtValue ( ) ; if ( ShiftAmt < <NUM_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue VecOp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , VecOp , One ) ; SDValue NewConst = DAG . getConstant ( ShiftAmt - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , NewConst ) ; SDValue BuildPair = DAG . getBuildVector ( <STR_LIT> , SL , { NewShift , Zero } ) ; return DAG . getNode ( <STR_LIT> ,


<s> SDValue One = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue VecOp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , VecOp , One ) ; SDValue NewConst = DAG . getConstant ( ShiftAmt - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , NewConst ) ; SDValue BuildPair = DAG . getBuildVector ( <STR_LIT> , SL , { NewShift , Zero } ) ; return DAG . getNode ( <STR_LIT> , SL


<s> if ( SN -> isVolatile ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; unsigned Align = SN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN


<s> unsigned AS = SN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorStore ( SN , DAG ) ; return expandUnalignedStore ( SN , DAG ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue (


<s> SDValue Vec = Src . getOperand ( <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue Elt0 = Vec . getOperand ( <NUM_LIT> ) ; EVT EltVT = Elt0 . getValueType ( ) ; if ( VT . getSizeInBits ( ) <= EltVT . getSizeInBits ( ) ) { if ( EltVT . isFloatingPoint ( ) ) { Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Elt0 ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , Elt0 ) ; } } } if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { if ( auto K = isConstOrConstSplat ( Src . getOperand ( <NUM_LIT> ) ) ) { if ( <NUM_LIT> * K -> getZExtValue ( ) == Src . getValueType ( ) . getScalarSizeInBits ( ) ) { SDValue BV = stripBitcast ( Src . getOperand ( <NUM_LIT> ) ) ; if ( BV . getOpcode ( ) == <STR_LIT> && BV . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue SrcElt = BV . getOperand (


<s> EVT VT = Op . getValueType ( ) ; APInt Demanded = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , true , true ) ; if ( TLI . SimplifyDemandedBits ( Node24 , OpIdx , Demanded , DCI , TLO ) ) return true ; return false


<s> SDValue <ISA_LIT>TargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) return scalarizeVectorLoad ( Load , DAG ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT ,


<s> unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoLoad . getValue ( <NUM_LIT> ) , HiLoad . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Ops ,


<s> std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , LoMemVT . getStoreSize ( ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , BaseAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , HiAlign , Store -> getMemOperand ( ) -> getFlags


<s> SDValue <ISA_LIT>TargetLowering :: storeStackInputValue ( SelectionDAG & DAG , const SDLoc & SL ,

SDValue Chain , SDValue StackPtr , SDValue ArgVal , int64_t Offset ) const {


<s> static inline SDValue stripBitcast ( SDValue Val ) { return Val . getOpcode ( ) == <STR_LIT> ? Val .


<s> SmallVector < MachineBasicBlock * , <NUM_LIT> > Stack ; Stack . push_back ( A ) ; do { MachineBasicBlock * MBB = Stack . back ( ) ; Stack . pop_back ( ) ; for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) { if ( Succ == A ) return false ; if ( Succ != B && Reachable . insert ( Succ ) . second ) Stack . push_back ( Succ ) ; } } while ( ! Stack . empty


<s> bool <ISA_LIT>LateCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; AC = & getAnalysis < AssumptionCacheTracker > ( )


<s> } IRBuilder < > IRB ( & LI ) ; IRB . SetCurrentDebugLocation ( LI . getDebugLoc ( ) ) ; unsigned AS = LI . getPointerAddressSpace ( ) ; unsigned LdBits = DL -> getTypeStoreSize ( LI . getType ( ) ) * <NUM_LIT> ; auto IntNTy = Type :: getIntNTy ( LI . getContext ( ) , LdBits ) ; PointerType * Int32PtrTy = Type :: getInt32PtrTy ( LI . getContext ( ) , AS ) ; PointerType * Int8PtrTy = Type :: getInt8PtrTy ( LI . getContext ( ) , AS ) ; auto * NewPtr = IRB . CreateBitCast ( IRB . CreateConstGEP1_64 ( IRB . CreatePointerBitCastOrAddrSpaceCast ( Base , Int8PtrTy ) , Offset - Adjust ) , Int32PtrTy ) ; LoadInst * NewLd = IRB . CreateAlignedLoad ( IRB . getInt32Ty ( ) , NewPtr , Align ( <NUM_LIT> ) ) ; NewLd -> copyMetadata ( LI ) ; NewLd -> setMetadata ( LLVMContext :: MD_range


<s> if ( LI . getAlign ( ) >= <NUM_LIT> ) return false ; if ( ! canWidenScalarExtLoad ( LI ) ) return false ; int64_t Offset = <NUM_LIT> ; auto * Base = GetPointerBaseWithConstantOffset ( LI . getPointerOperand ( ) , Offset , * DL ) ; if ( ! isDWORDAligned ( Base ) ) return false ; int64_t Adjust = Offset & <NUM_LIT> ; if ( Adjust == <NUM_LIT> ) { LI . setAlignment ( Align ( <NUM_LIT> ) ) ; return true ; } IRBuilder < > IRB ( & LI ) ; IRB . SetCurrentDebugLocation ( LI . getDebugLoc ( ) ) ; unsigned AS = LI


<s> if ( AS != <ISA_LIT>AS :: CONSTANT_ADDRESS && AS != <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return false ; if ( ! LI . isSimple ( ) ) return false ; auto * Ty = LI . getType ( ) ; if ( Ty -> isAggregateType ( ) ) return false ; unsigned TySize = DL -> getTypeStoreSize ( Ty ) ; if ( TySize >= <NUM_LIT> ) return


<s> Mod = & M ; DL = & Mod -> getDataLayout (


<s> StringRef getPassName ( ) const override { return


<s> if ( skipFunction ( F ) ) return false ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; bool Changed = false ; for ( auto & BB : F ) for ( Instruction & I : llvm :: make_early_inc_range ( BB ) ) Changed |= visit ( I ) ; return


<s> auto * Base = GetPointerBaseWithConstantOffset ( LI . getPointerOperand ( ) , Offset , * DL ) ; if ( ! isDWORDAligned ( Base ) ) return false ; int64_t Adjust = Offset & <NUM_LIT> ; if ( Adjust == <NUM_LIT> ) { LI . setAlignment ( Align ( <NUM_LIT> ) ) ; return true ; } IRBuilder < > IRB ( & LI ) ; IRB . SetCurrentDebugLocation ( LI . getDebugLoc ( ) ) ; unsigned AS = LI . getPointerAddressSpace ( ) ; unsigned LdBits = DL -> getTypeStoreSize ( LI . getType ( ) ) * <NUM_LIT> ; auto IntNTy = Type :: getIntNTy ( LI . getContext ( ) , LdBits ) ; PointerType * Int32PtrTy = Type :: getInt32PtrTy ( LI . getContext ( ) , AS ) ; PointerType * Int8PtrTy = Type :: getInt8PtrTy ( LI . getContext ( ) , AS ) ; auto * NewPtr = IRB . CreateBitCast ( IRB . CreateConstGEP1_64 ( IRB . getInt8Ty ( ) , IRB . CreatePointerBitCastOrAddrSpaceCast ( Base , Int8PtrTy ) , Offset - Adjust ) , Int32PtrTy ) ; LoadInst * NewLd = IRB . CreateAlignedLoad ( IRB . getInt32Ty ( ) , NewPtr , Align ( <NUM_LIT> ) ) ; NewLd -> copyMetadata ( LI ) ; NewLd -> setMetadata ( LLVMContext :: MD_range , nullptr ) ; unsigned ShAmt = Adjust * <NUM_LIT> ; auto * NewVal = IRB . CreateBitCast ( IRB . CreateTrunc ( IRB . CreateLShr ( NewLd , ShAmt ) , IntNTy ) , LI . getType ( ) ) ; LI . replaceAllUsesWith (


<s> } if ( auto * I = dyn_cast < Instruction > ( V ) ) { const Function * UF = I -> getFunction ( ) ; if ( UF == F ) { Ret = true ; } else if ( ! F ) { Ret |= ! isKernelCC ( UF ) ; } continue ; } assert ( isa < Constant > ( V ) && <STR_LIT> ) ; append_range ( Stack , V -> users


<s> if ( ! GV . hasInitializer ( ) ) { continue ; } if ( ! isa < UndefValue > ( GV . getInitializer ( ) ) ) { continue ; } if ( GV . isConstant ( ) ) { continue ; } if ( ! shouldLowerLDSToStruct ( UsedList , GV , F ) ) { continue ; } LocalVars . push_back ( &


<s> if ( ! GV . hasInitializer ( ) ) { continue ; } if ( ! isa < UndefValue > ( GV . getInitializer ( ) ) ) { continue ; } if ( GV . isConstant ( ) ) { continue ; } if ( ! shouldLowerLDSToStruct ( UsedList , GV , F ) ) { continue ; } LocalVars . push_back ( & GV ) ; } return LocalVars


<s> if ( auto * I = dyn_cast < Instruction > ( U ) ) { return I -> getFunction ( ) == F ; } if ( isa < ConstantExpr >


<s> assert ( ! F || isKernelCC ( F ) ) ; while ( ! Stack . empty ( ) ) { const User * V = Stack . pop_back_val ( ) ; Visited . insert ( V ) ; if ( auto * G = dyn_cast < GlobalValue > ( V -> stripPointerCasts ( ) ) ) { if ( UsedList . contains ( G ) ) { continue ; } } if ( auto * I = dyn_cast < Instruction > ( V ) ) { const Function * UF = I -> getFunction ( ) ; if ( UF == F ) { Ret = true ; } else if ( ! F ) { Ret |= ! isKernelCC ( UF ) ; } continue ; } if ( auto * E = dyn_cast < ConstantExpr > ( V ) ) { if ( F ) { if ( ! isUsedOnlyFromFunction ( E , F ) ) return false ; } for ( const User * U : E -> users ( ) ) { if ( Visited . insert ( U ) . second ) { Stack . push_back ( U ) ; } } continue ; } return !


<s> continue ; } if ( std :: none_of ( GV . user_begin ( ) , GV . user_end ( ) , [ & ] ( User * U ) { return userRequiresLowering ( UsedList , U ) ; } ) ) { continue ; } LocalVars . push_back ( & GV ) ; } return LocalVars


<s> bool isKernelCC ( Function * Func ) { return <STR_LIT> ( Func ->


<s> void collectReachableCallees ( Module & M , DenseMap < Function * , SmallPtrSet < Function * , <NUM_LIT> >> & KernelToCallees ) { CollectReachableCallees CRC { M } ; CRC . collectReachableCallees


<s> void collectReachableCallees ( Module & M , DenseMap < Function * , SmallPtrSet < Function * , <NUM_LIT> >> & KernelToCallees ) { CollectReachableCallees CRC { M }


<s> return DL . getValueOrABITypeAlignment ( GV -> getPointerAlignment ( DL ) , GV ->


<s> SmallVector < GlobalValue * , <NUM_LIT> > TmpVec ; collectUsedGlobalVariables ( M , TmpVec , true ) ; UsedList . insert ( TmpVec . begin ( ) , TmpVec . end ( ) ) ; TmpVec . clear ( ) ; collectUsedGlobalVariables ( M , TmpVec , false ) ; UsedList . insert ( TmpVec . begin ( ) , TmpVec . end ( ) ) ; return UsedList


<s> SmallVector < const User * , <NUM_LIT> > Stack ( GV -> users ( ) ) ; while ( ! Stack . empty ( ) ) { const User * U = Stack . pop_back_val (


<s> for ( Instruction * I : InstUsers ) { convertConstantExprsToInstructions ( I , C


<s> void replaceConstantUsesInFunction ( ConstantExpr * C , const Function * F ) { SetVector < Instruction * >


<s> SmallPtrSet < const User * , <NUM_LIT> > Visited ; SmallVector < const User * , <NUM_LIT> > Stack ( GV . users ( ) ) ; SmallPtrSet < const GlobalValue * , <NUM_LIT> > GlobalUsers ; assert ( ! F || isKernelCC ( F ) ) ; while ( ! Stack . empty ( ) ) { const User * V = Stack . pop_back_val ( ) ; Visited . insert ( V ) ; if ( auto * G = dyn_cast < GlobalValue > ( V ) ) { StringRef GName = G -> getName ( ) ; if ( F && GName != <STR_LIT> && GName != <STR_LIT> ) { return


<s> if ( auto * G = dyn_cast < GlobalValue > ( V ) ) { StringRef GName = G -> getName ( ) ; if ( F && GName != <STR_LIT> && GName != <STR_LIT> ) { return false ; } GlobalUsers . insert ( G ) ; continue ; } if ( auto * I = dyn_cast < Instruction > ( V ) ) { const Function * UF = I -> getFunction ( ) ; if ( UF == F ) { Ret = true ; } else if ( ! F ) { Ret |= ! isKernelCC


<s> static Register buildDivRCP ( MachineIRBuilder & B , Register Src ) { const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto Cvt0 = B . buildUITOFP ( S32 , Src ) ; auto RcpIFlag = B . buildInstr ( <STR_LIT> , {


<s> const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto Cvt0 = B . buildUITOFP ( S32 , Src ) ; auto RcpIFlag = B . buildInstr ( <STR_LIT> , { S32 } , { Cvt0 } ) ; auto FPUIntMaxPlus1 = B . buildFConstant ( S32 , BitsToFloat


<s> MachineInstrBuilder MIB = B . buildInstr ( <STR_LIT> ) . addDef ( PCReg ) ; MIB . addGlobalAddress ( GV , Offset + <NUM_LIT> , GAFlags ) ; if ( GAFlags == <ISA_LIT>InstrInfo :: MO_NONE ) MIB . addImm ( <NUM_LIT> ) ; else MIB . addGlobalAddress ( GV , Offset + <NUM_LIT> , GAFlags + <NUM_LIT> ) ; B . getMRI ( ) -> setRegClass ( PCReg , & <STR_LIT> ) ; if ( PtrTy . getSizeInBits ( ) == <NUM_LIT> ) B . buildExtract (


<s> assert ( B . getMRI ( ) -> getType ( SrcOp . getReg ( ) ) == S32 ) ; } } int NumAddrRegs = AddrRegs . size ( ) ; if ( NumAddrRegs != <NUM_LIT> ) { if ( NumAddrRegs > <NUM_LIT> && ! isPowerOf2_32 ( NumAddrRegs ) ) { const int RoundedNumRegs = NextPowerOf2 ( NumAddrRegs ) ; auto Undef = B . buildUndef ( S32 ) ; AddrRegs . append ( RoundedNumRegs - NumAddrRegs , Undef . getReg ( <NUM_LIT> ) ) ; NumAddrRegs = RoundedNumRegs ; } auto VAddr = B . buildBuildVector ( LLT :: vector ( NumAddrRegs , <NUM_LIT> ) , AddrRegs ) ; MI . getOperand ( DimIdx ) . setReg ( VAddr . getReg ( <NUM_LIT> ) ) ; } for ( int I = <NUM_LIT> ; I != NumVAddrs ; ++ I ) { MachineOperand & SrcOp = MI . getOperand ( DimIdx + I ) ; if ( SrcOp . isReg ( ) ) MI . getOperand ( DimIdx + I ) . setReg (


<s> const unsigned ExpBits = <NUM_LIT> ; LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto Const0 = B . buildConstant ( S32 , FractBits - <NUM_LIT> ) ; auto Const1 = B . buildConstant ( S32 , ExpBits ) ; auto ExpPart = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Const0 . getReg ( <NUM_LIT> ) ) . addUse ( Const1 . getReg ( <NUM_LIT> ) ) ; return B . buildSub ( S32 , ExpPart , B


<s> unsigned Size = Ty . getSizeInBits ( ) ; unsigned Pieces = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned NewNumElts = ( Ty . getNumElements ( ) + <NUM_LIT> ) / Pieces ; return std :: make_pair ( TypeIdx , LLT :: scalarOrVector


<s> const ArgDescriptor * <ISA_LIT>LegalizerInfo :: getArgDescriptor ( MachineIRBuilder & B , <STR_LIT> ArgType ) const { const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const ArgDescriptor * Arg ; const TargetRegisterClass * RC ; std :: tie ( Arg , RC )

= MFI -> getPreloadedValue ( ArgType ) ;


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return


<s> Register LiveIn = MRI . getLiveInVirtReg ( PhyReg ) ; if ( ! LiveIn ) { LiveIn = MRI . createGenericVirtualRegister ( Ty ) ; MRI . addLiveIn ( PhyReg , LiveIn ) ; } if ( ! InsertLiveInCopy ) return LiveIn


<s> SmallVector < Register , <NUM_LIT> > WideRegs ; for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) WideRegs . push_back

( B . buildAnyExt ( S32 , Unmerge . getReg ( I ) ) . getReg ( <NUM_LIT> ) ) ;


<s> assert ( StoreVT . isVector ( ) && StoreVT . getElementType ( ) == S16 ) ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; SmallVector < Register , <NUM_LIT> > WideRegs ; for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) WideRegs . push_back ( B . buildAnyExt ( S32 , Unmerge . getReg ( I ) ) . getReg ( <NUM_LIT> ) ) ; int NumElts = StoreVT . getNumElements


<s> if ( ! MRI . getVRegDef ( LiveIn ) ) { MachineBasicBlock & OrigInsBB = B . getMBB ( ) ; auto OrigInsPt = B . getInsertPt ( ) ; MachineBasicBlock & EntryMBB = B . getMF


<s> Register <ISA_LIT>LegalizerInfo :: insertLiveInCopy ( MachineIRBuilder & B , MachineRegisterInfo & MRI , Register LiveIn , Register PhyReg ) const { assert ( PhyReg . isPhysical ( ) && <STR_LIT> ) ; if ( ! MRI . getVRegDef ( LiveIn ) ) { MachineBasicBlock & OrigInsBB = B . getMBB ( ) ; auto OrigInsPt = B . getInsertPt ( ) ; MachineBasicBlock & EntryMBB = B . getMF ( ) . front ( ) ; EntryMBB . addLiveIn ( PhyReg ) ; B . setInsertPt ( EntryMBB , EntryMBB . begin ( ) ) ; B . buildCopy ( LiveIn , PhyReg ) ; B . setInsertPt ( OrigInsBB , OrigInsPt


<s> const LLT EltTy = Ty . getScalarType ( ) ; return Ty . getSizeInBits ( ) <= MaxSize && EltTy .

getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ;


<s> B . setInstr ( MI ) ; Register PackedVal = B . buildBuildVector ( VecTy , { NewVal , CmpVal } ) . getReg ( <NUM_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( DstReg ) . addUse ( PtrReg ) . addUse ( PackedVal ) . setMemRefs ( MI . memoperands ( ) ) ; MI . eraseFromParent (


<s> unsigned Opc = IsInc ? <STR_LIT> : <STR_LIT> ; B . buildInstr ( Opc ) . addDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; return true


<s> <STR_LIT> ; B . buildInstr ( Opc ) . addDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . cloneMemRefs ( MI ) ; MI . eraseFromParent


<s> const unsigned NumVIndexOps = IsCmpSwap ? <NUM_LIT> : <NUM_LIT> ; const bool HasVIndex = MI . getNumOperands ( ) == NumVIndexOps ; Register VIndex ; if ( HasVIndex ) { VIndex = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; ++ OpOffset ; } Register VOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; unsigned AuxiliaryData = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; unsigned ImmOffset ; unsigned TotalOffset ; std :: tie ( VOffset , ImmOffset , TotalOffset ) = splitBufferOffsets ( B , VOffset ) ; if ( TotalOffset != <NUM_LIT> ) MMO = B . getMF ( ) . getMachineMemOperand ( MMO , TotalOffset , MMO -> getSize ( ) ) ; if ( ! VIndex ) VIndex = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; auto MIB = B . buildInstr ( getBufferAtomicPseudo ( IID ) ) . addDef ( Dst ) . addUse ( VData ) ; if ( IsCmpSwap ) MIB . addReg


<s> <STR_LIT> ; } else if ( IsFormat ) { Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else { switch ( MemSize ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : Opc = <STR_LIT> ; break ; } } Register LoadDstReg ; bool IsExtLoad = ( ! IsD16 && MemSize < <NUM_LIT> ) || ( IsD16 && ! Ty . isVector ( ) ) ; LLT UnpackedTy = Ty . changeElementSize ( <NUM_LIT> ) ; if ( IsExtLoad ) LoadDstReg = B . getMRI ( ) -> createGenericVirtualRegister ( S32 ) ; else if ( Unpacked && IsD16 && Ty . isVector ( ) ) LoadDstReg = B . getMRI ( ) -> createGenericVirtualRegister ( UnpackedTy ) ; else LoadDstReg = Dst ; if ( ! VIndex ) VIndex = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; auto MIB = B . buildInstr ( Opc ) . addDef ( LoadDstReg ) . addUse ( RSrc ) . addUse ( VIndex ) . addUse ( VOffset ) . addUse ( SOffset ) . addImm ( ImmOffset ) ; if ( IsTyped ) MIB . addImm ( Format ) ; MIB . addImm ( AuxiliaryData ) . addImm ( HasVIndex ? - <NUM_LIT> : <NUM_LIT> ) . addMemOperand ( MMO ) ; if ( LoadDstReg != Dst ) { B . setInsertPt ( B . getMBB ( ) , ++ B . getInsertPt ( ) ) ; if ( IsExtLoad ) B . buildTrunc ( Dst , LoadDstReg ) ; else { auto Unmerge = B . buildUnmerge ( S32 , LoadDstReg ) ; SmallVector < Register , <NUM_LIT> > Repack ; for ( unsigned I = <NUM_LIT> , N = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != N ; ++ I ) Repack . push_back ( B . buildTrunc ( EltTy , Unmerge . getReg ( I ) ) . getReg ( <NUM_LIT> ) ) ; B . buildMerge ( Dst ,


<s> Register VOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; unsigned Format = <NUM_LIT> ; if ( IsTyped ) { Format = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; ++ OpOffset ; } unsigned AuxiliaryData = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; std :: tie ( VOffset , ImmOffset , TotalOffset ) = splitBufferOffsets ( B , VOffset ) ; if ( TotalOffset != <NUM_LIT> ) MMO = B . getMF ( ) . getMachineMemOperand ( MMO , TotalOffset , MemSize ) ; unsigned Opc ; if ( IsTyped ) { Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else if ( IsFormat ) { Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else { switch ( MemSize ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : Opc =


<s> Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( Src0 ) == LLT :: scalar ( <NUM_LIT> ) ) ; B . setInstr ( MI ) ; auto Merge = B . buildMerge ( S32 , { Src0 , Src1 } ) ; B . buildBitcast ( Dst , Merge ) ; MI . eraseFromParent ( ) ; return true


<s> case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE : case TargetOpcode :: G_FMAXNUM_IEEE : return legalizeMinNumMaxNum ( MI , MRI , B ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT : return legalizeExtractVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_INSERT_VECTOR_ELT : return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : return legalizeLoad ( MI , MRI , B , Observer ) ; case TargetOpcode :: G_FMAD : return legalizeFMad ( MI , MRI , B ) ; case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : return legalizeUDIV_UREM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : return legalizeSDIV_SREM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ; case TargetOpcode :: G_FLOG : return legalizeFlog ( MI , B , <NUM_LIT> / numbers :: log2ef ) ; case TargetOpcode :: G_FLOG10 : return legalizeFlog ( MI , B , numbers :: ln2f / numbers :: ln10f ) ; case TargetOpcode :: G_FEXP : return legalizeFExp ( MI , B ) ; case TargetOpcode ::


<s> return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : return legalizeLoad ( MI , MRI , B , Observer ) ; case TargetOpcode :: G_FMAD : return legalizeFMad ( MI , MRI , B ) ; case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : return legalizeUDIV_UREM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : return legalizeSDIV_SREM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ; case TargetOpcode :: G_FLOG : return legalizeFlog ( MI , B , <NUM_LIT> / numbers :: log2ef ) ; case TargetOpcode :: G_FLOG10 : return legalizeFlog ( MI , B , numbers :: ln2f / numbers :: ln10f ) ; case TargetOpcode :: G_FEXP : return legalizeFExp ( MI , B ) ; case TargetOpcode :: G_FPOW : return legalizeFPow ( MI , B ) ; case TargetOpcode :: G_FFLOOR : return legalizeFFloor ( MI , MRI ,


<s> if ( ST . getTrapHandlerAbi ( ) != GCNSubtarget :: TrapHandlerAbiHsa || ! ST . isTrapHandlerEnabled ( ) ) { DiagnosticInfoUnsupported NoTrap ( B . getMF ( ) . getFunction ( ) , <STR_LIT> , MI . getDebugLoc ( ) , DS_Warning ) ; LLVMContext & Ctx = B . getMF ( ) . getFunction ( ) . getContext ( ) ; Ctx . diagnose ( NoTrap )


<s> LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Dst ) ) ; B . setInstr ( MI ) ; if ( IdxVal -> Value < VecTy . getNumElements ( ) ) B . buildExtract ( Dst , Vec , IdxVal -> Value * EltTy . getSizeInBits ( ) ) ; else B . buildUndef ( Dst ) ; MI . eraseFromParent ( )


<s> LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Dst ) ) ; B . setInstr ( MI ) ; if ( IdxVal -> Value < VecTy . getNumElements ( ) ) B . buildExtract ( Dst , Vec , IdxVal -> Value * EltTy . getSizeInBits ( ) ) ; else B . buildUndef ( Dst ) ; MI . eraseFromParent ( ) ; return


<s> LLT ResTy = MRI . getType ( Res ) ; LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; const MachineFunction & MF = B . getMF ( ) ; bool Unsafe = MF . getTarget ( ) . Options . UnsafeFPMath || MI . getFlag ( MachineInstr :: FmArcp ) ; if ( ! MF . getTarget ( ) . Options . UnsafeFPMath && ResTy == S64 ) return false ; if ( ! Unsafe && ResTy == S32 && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMode ( ) . allFP32Denormals ( ) ) return false ; if ( auto CLHS = getConstantFPVRegVal


<s> B . setInstr ( MI ) ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( Src ) == S64 ) ; auto Trunc = B . buildIntrinsicTrunc ( S64 , Src ) ; const auto Zero = B . buildFConstant ( S64 , <NUM_LIT> ) ; const auto One = B . buildFConstant ( S64 , <NUM_LIT> ) ; auto Lt0 = B . buildFCmp ( CmpInst :: FCMP_OGT , S1 , Src , Zero ) ; auto NeTrunc = B . buildFCmp ( CmpInst :: FCMP_ONE , S1 , Src , Trunc ) ; auto And = B . buildAnd ( S1 , Lt0 ,


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT S16 = LLT :: scalar ( <NUM_LIT> ) ; LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; if ( legalizeFastUnsafeFDIV ( MI , MRI , B ) ) return true ; if ( DstTy == S16 ) return legalizeFDIV16 ( MI , MRI , B ) ; if ( DstTy == S32 ) return legalizeFDIV32 ( MI


<s> LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto LHSExt = B . buildFPExt ( S32 , LHS , Flags ) ; auto RHSExt = B . buildFPExt ( S32 , RHS , Flags ) ; auto RCP = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( RHSExt . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto QUOT = B . buildFMul ( S32 , LHSExt , RCP , Flags ) ; auto RDst = B . buildFPTrunc ( S16 , QUOT , Flags ) ; B . buildIntrinsic ( <STR_LIT> , Res , false ) . addUse ( RDst . getReg ( <NUM_LIT> ) ) . addUse ( RHS ) . addUse ( LHS ) . setMIFlags ( Flags ) ; MI . eraseFromParent


<s> auto NumeratorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto ApproxRcp = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( DenominatorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S32 , DenominatorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( true , B , ST , Mode ) ; auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul , Flags ) ; auto Fma4 = B . buildFMA ( S32 , NegDivScale0 , Fma3 , NumeratorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( false , B , ST , Mode ) ; auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma1 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( NumeratorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; B . buildIntrinsic ( <STR_LIT> , Res , false ) . addUse ( Fmas . getReg ( <NUM_LIT> ) ) . addUse ( RHS ) . addUse ( LHS ) . setMIFlags ( Flags ) ; MI . eraseFromParent (


<s> auto NumeratorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto ApproxRcp = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( DenominatorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S32 , DenominatorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( true , B , ST , Mode ) ; auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 ,


<s> auto NumUnmerge = B . buildUnmerge ( S32 , LHS ) ; auto DenUnmerge = B . buildUnmerge ( S32 , RHS ) ; auto Scale0Unmerge = B . buildUnmerge ( S32 , DivScale0 ) ; auto Scale1Unmerge = B . buildUnmerge ( S32 , DivScale1 ) ; auto CmpNum = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , NumUnmerge . getReg ( <NUM_LIT> ) , Scale1Unmerge . getReg ( <NUM_LIT> ) ) ; auto CmpDen = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , DenUnmerge . getReg ( <NUM_LIT> ) , Scale0Unmerge . getReg ( <NUM_LIT> ) ) ; Scale = B . buildXor ( S1 , CmpNum , CmpDen ) . getReg ( <NUM_LIT> ) ; } else { Scale = DivScale1 . getReg ( <NUM_LIT> ) ; } auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( Mul . getReg (

<NUM_LIT> ) ) . addUse ( Scale ) . setMIFlags ( Flags ) ;


<s> unsigned Flags = MI . getFlags ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; B . setInstr ( MI ) ; auto K = B . buildFConstant ( Ty , numbers :: log2e ) ; auto Mul = B . buildFMul ( Ty , Src , K , Flags ) ; B . buildFExp2 ( Dst , Mul , Flags ) ; MI . eraseFromParent ( )


<s> const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OrigSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Flags = MI . getFlags ( ) ; assert ( ST . hasFractBug ( ) && MRI . getType ( Dst ) == S64 && <STR_LIT> ) ; auto Fract = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( OrigSrc ) . setMIFlags ( Flags ) ; Register ModSrc = stripAnySourceMods ( OrigSrc , MRI ) ; auto Const = B . buildFConstant ( S64 , BitsToDouble ( <NUM_LIT> ) ) ; Register Min = MRI . createGenericVirtualRegister ( S64 ) ; const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getMode ( ) . IEEE ) B . buildFMinNumIEEE ( Min , Fract , Const , Flags ) ; else B . buildFMinNum ( Min , Fract , Const , Flags ) ; Register CorrectedFract = Min ; if ( ! MI . getFlag ( MachineInstr :: FmNoNans ) ) { auto IsNan = B . buildFCmp ( CmpInst :: FCMP_ORD , S1 , ModSrc , ModSrc , Flags ) ; CorrectedFract = B . buildSelect ( S64 , IsNan , ModSrc , Min , Flags ) . getReg ( <NUM_LIT> ) ; } auto NegFract = B . buildFNeg ( S64 , CorrectedFract , Flags ) ; B . buildFAdd ( Dst , OrigSrc , NegFract , Flags ) ; MI . eraseFromParent ( ) ; return true


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; unsigned Flags = MI . getFlags ( ) ; B . setInstr ( MI ) ; auto Log2Operand = B . buildFLog2 ( Ty , Src , Flags ) ; auto Log2BaseInvertedOperand = B . buildFConstant ( Ty , Log2BaseInverted ) ; B . buildFMul ( Dst , Log2Operand


<s> if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . allFP32Denormals ( ) ) return true ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . allFP64FP16Denormals ( ) ) return true ; MachineIRBuilder HelperBuilder ( MI ) ; GISelObserverWrapper


<s> unsigned Flags = MI . getFlags ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; B . setInstr ( MI ) ; const LLT S16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; if ( Ty == S32 ) { auto Log = B . buildFLog2 ( S32 , Src0 , Flags ) ; auto Mul = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Log . getReg ( <NUM_LIT> ) ) . addUse ( Src1 ) . setMIFlags ( Flags ) ; B . buildFExp2 ( Dst , Mul


<s> const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; assert ( MRI . getType ( Src ) == S64 && MRI . getType ( Dst ) == S64 ) ; unsigned Flags = MI . getFlags ( ) ; auto Trunc = B . buildIntrinsicTrunc ( S64 , Src , Flags ) ; auto K0 = B . buildFConstant ( S64 , BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) ) ; auto K1 = B . buildFConstant ( S64 , BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) ) ; auto Mul = B . buildFMul ( S64 , Trunc , K0 , Flags ) ; auto FloorMul = B . buildFFloor ( S64 , Mul , Flags ) ; auto Fma = B . buildFMA ( S64 ,


<s> auto CopySign = B . buildFCopysign ( Ty , C1 , Src ) ; auto Tmp1 = B . buildFAdd ( Ty , Src , CopySign ) ; auto Tmp2 = B . buildFSub ( Ty , Tmp1 , CopySign ) ; auto C2 = B . buildFConstant ( Ty , C2Val ) ; auto Fabs = B . buildFAbs ( Ty , Src ) ; auto Cond = B . buildFCmp ( CmpInst :: FCMP_OGT , LLT :: scalar ( <NUM_LIT> ) , Fabs , C2 ) ; B . buildSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Cond , Src , Tmp2 ) ; return true


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; B . setInstr ( MI ) ; if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! MFI -> isEntryFunction ( ) ) { const Function & Fn = MF . getFunction ( ) ; DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , MI . getDebugLoc ( ) , DS_Warning ) ; Fn . getContext ( ) . diagnose ( BadLDSDecl ) ; B . buildIntrinsic ( <STR_LIT> , ArrayRef < Register > ( ) , true ) ; B . buildUndef ( DstReg ) ; MI . eraseFromParent ( ) ; return true ; } if ( ! <ISA_LIT>TargetLowering :: hasDefinedInitializer ( GV ) ) { const <ISA_LIT>TargetLowering * TLI = ST . getTargetLowering ( ) ; if ( ! TLI -> shouldUseLDSConstAddress ( GV ) ) { MI . getOperand ( <NUM_LIT> ) . setTargetFlags ( <ISA_LIT>InstrInfo :: MO_ABS32_LO ) ; return true ; } B . buildConstant ( DstReg , MFI -> allocateLDSGlobal ( B . getDataLayout ( ) , * GV ) ) ; MI . eraseFromParent ( ) ; return true ; } const Function & Fn = MF . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , MI . getDebugLoc ( ) ) ; Fn . getContext ( ) . diagnose ( BadInit ) ; return true


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( DstReg ) ; LLT IdxTy = LLT :: scalar ( DstTy . getSizeInBits ( ) ) ; const ArgDescriptor * Arg ; const TargetRegisterClass * RC ; std :: tie ( Arg , RC ) = MFI -> getPreloadedValue ( <STR_LIT> ) ; if ( ! Arg ) return false ; Register KernargPtrReg = MRI . createGenericVirtualRegister ( DstTy ) ; if ( ! loadInputValue ( KernargPtrReg , B , Arg ) ) return false ; B . buildPtrAdd ( DstReg , KernargPtrReg , B . buildConstant ( IdxTy , Offset ) .


<s> if ( ! MFI -> isEntryFunction ( ) ) { return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; } B . setInstr ( MI ) ; uint64_t Offset = ST . getTargetLowering ( ) -> getImplicitParameterOffset ( B . getMF ( ) , <ISA_LIT>TargetLowering :: FIRST_IMPLICIT ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( DstReg ) ; LLT IdxTy = LLT :: scalar ( DstTy . getSizeInBits ( ) ) ; const ArgDescriptor * Arg ; const TargetRegisterClass * RC ; std :: tie ( Arg , RC ) = MFI -> getPreloadedValue ( <STR_LIT> ) ; if ( ! Arg ) return false ; Register KernargPtrReg = MRI . createGenericVirtualRegister ( DstTy ) ; if ( ! loadInputValue ( KernargPtrReg , B , Arg ) ) return false ; B . buildPtrAdd ( DstReg , KernargPtrReg , B . buildConstant ( IdxTy , Offset ) . getReg ( <NUM_LIT> ) ) ; MI . eraseFromParent


<s> Optional < ValueAndVReg > IdxVal = getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! IdxVal ) return true ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Vec = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ins = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT VecTy = MRI . getType ( Vec ) ; LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Ins ) ) ; B . setInstr ( MI


<s> auto Shr = B . buildAShr ( S64 , FractMask , Exp ) ; auto Not = B . buildNot ( S64 , Shr ) ; auto Tmp0 = B . buildAnd ( S64 , Src , Not ) ; auto FiftyOne = B . buildConstant ( S32 , FractBits - <NUM_LIT> ) ; auto ExpLt0 = B . buildICmp ( CmpInst :: ICMP_SLT , S1 , Exp , Zero32 ) ; auto ExpGt51 = B . buildICmp ( CmpInst :: ICMP_SGT , S1 , Exp , FiftyOne ) ; auto Tmp1 = B . buildSelect ( S64 , ExpLt0 , SignBit64 , Tmp0 ) ; B . buildSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ExpGt51 , Src , Tmp1 ) ; return true


<s> const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( Src ) == S64 ) ; auto Unmerge = B . buildUnmerge ( { S32 , S32 } , Src ) ; Register Hi = Unmerge . getReg ( <NUM_LIT> ) ; auto Exp = extractF64Exponent ( Hi , B ) ; const unsigned FractBits = <NUM_LIT> ; const auto SignBitMask = B . buildConstant ( S32 , UINT32_C ( <NUM_LIT> ) << <NUM_LIT> ) ; auto SignBit = B . buildAnd ( S32 , Hi , SignBitMask ) ; const auto FractMask = B . buildConstant ( S64 , ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> ) ; const auto Zero32 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto SignBit64 = B . buildMerge ( S64 , { Zero32 , SignBit } ) ; auto Shr = B . buildAShr ( S64 , FractMask , Exp ) ; auto Not = B . buildNot ( S64 , Shr ) ; auto Tmp0 = B . buildAnd ( S64 , Src , Not ) ; auto FiftyOne = B . buildConstant ( S32 , FractBits - <NUM_LIT> ) ; auto ExpLt0 = B . buildICmp ( CmpInst :: ICMP_SLT , S1 , Exp , Zero32 ) ; auto ExpGt51 = B . buildICmp ( CmpInst :: ICMP_SGT , S1 , Exp , FiftyOne ) ; auto Tmp1 = B . buildSelect ( S64 , ExpLt0


<s> const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; assert ( MRI . getType ( Src ) == S64 && MRI . getType ( Dst ) == S64 ) ; auto Unmerge = B . buildUnmerge ( { S32 , S32 } , Src ) ; auto CvtHi = Signed ? B . build<ISA_LIT>TOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) : B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto CvtLo = B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto ThirtyTwo = B . buildConstant ( S32 , <NUM_LIT>


<s> auto Unmerge = B . buildUnmerge ( { S32 , S32 } , Src ) ; auto CvtHi = Signed ? B . build<ISA_LIT>TOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) : B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto CvtLo = B . buildUITOFP ( S64 , Unmerge . getReg ( <NUM_LIT> ) ) ; auto ThirtyTwo = B . buildConstant ( S32 , <NUM_LIT>


<s> LLT ConstPtr = LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ; auto Cast = B . buildAddrSpaceCast ( ConstPtr , MI

. getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> if ( ! loadInputValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , B , Arg ) ) return false ; MI . eraseFromParent


<s> B . setInstr ( MI ) ; const ArgDescriptor * Arg = getArgDescriptor ( B , ArgType ) ; if ( ! Arg


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; unsigned Size = Ty . getSizeInBits ( ) ; MachineFunction & MF = B . getMF ( ) ; Observer . changingInstr ( MI ) ; MI . setDesc ( B . getTII ( ) . get ( <STR_LIT> ) ) ; MI . RemoveOperand (


<s> bool <ISA_LIT>LegalizerInfo :: legalizeSDIV_SREM ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { if ( MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return legalizeSDIV_SREM32 ( MI , MRI , B ) ; return


<s> LHS = B . buildAdd ( S32 , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildAdd ( S32 , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; LHS = B . buildXor ( S32 , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildXor ( S32 , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; Register UDivRem = MRI . createGenericVirtualRegister ( S32 ) ; legalizeUDIV_UREM32Impl ( B , UDivRem , LHS , RHS , IsRem ) ; if ( IsRem ) { auto RSign =


<s> auto LHSign = B . buildAShr ( S32 , LHS , ThirtyOne ) ; auto RHSign = B . buildAShr ( S32 , LHS , ThirtyOne ) ; LHS = B . buildAdd ( S32 , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildAdd ( S32 , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; LHS = B . buildXor ( S32 , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildXor ( S32 , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; Register UDivRem = MRI . createGenericVirtualRegister ( S32 ) ; legalizeUDIV_UREM32Impl ( B , UDivRem , LHS , RHS , IsRem ) ; if ( IsRem ) { auto RSign = LHSign ; UDivRem = B . buildXor ( S32 , UDivRem , RSign ) . getReg ( <NUM_LIT> ) ; B . buildSub ( DstReg , UDivRem , RSign ) ; } else { auto DSign = B . buildXor ( S32 , LHSign , RHSign ) ; UDivRem = B . buildXor ( S32 , UDivRem ,


<s> LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> )

) return legalizeUDIV_UREM32 ( MI , MRI , B ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeUDIV_UREM ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) return legalizeUDIV_UREM32 ( MI , MRI , B ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) return legalizeUDIV_UREM64 ( MI , MRI , B ) ; return false


<s> B . setInstr ( MI ) ; const bool IsRem = MI . getOpcode ( ) == <STR_LIT> ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Num = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Den = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; legalizeUDIV_UREM32Impl ( B , DstReg , Num , Den , IsRem ) ; MI . eraseFromParent (


<s> Register Num = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Den = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; legalizeUDIV_UREM32Impl ( B , DstReg , Num , Den , IsRem ) ; MI . eraseFromParent


<s> auto RCP_S_E = B . buildSub ( S32 , RCP , E ) ; auto Tmp0 = B . buildSelect ( S32 , CmpRcpHiZero , RCP_A_E , RCP_S_E ) ; auto Quotient = B . buildUMulH ( S32 , Tmp0 , Num ) ; auto Num_S_Remainder = B . buildMul ( S32 , Quotient , Den ) ; auto Remainder = B . buildSub ( S32 , Num , Num_S_Remainder ) ; auto Remainder_GE_Den = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , Remainder , Den ) ; auto Remainder_GE_Zero = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , Num , Num_S_Remainder ) ; auto Tmp1 = B . buildAnd ( S1 , Remainder_GE_Den , Remainder_GE_Zero ) ; auto One = B . buildConstant ( S32 , <NUM_LIT> ) ; auto Quotient_A_One = B . buildAdd ( S32 , Quotient , One ) ; auto Quotient_S_One = B . buildSub ( S32 , Quotient , One ) ; auto Div = B . buildSelect ( S32 , Tmp1 , Quotient , Quotient_A_One ) ; if ( IsRem )