<s> const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ; I . setDesc ( TII . get ( IsVGPR ? <STR_LIT> : <STR_LIT> ) ) ; if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; return RBI . constrainGenericRegister ( DstReg , IsVGPR ? <STR_LIT> : <STR_LIT>


<s> LLT Src1Ty = MRI -> getType ( Src1Reg ) ; unsigned DstSize = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; unsigned InsSize = Src1Ty . getSizeInBits ( ) ; int64_t Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || InsSize % <NUM_LIT> != <NUM_LIT> ) return false ; if ( InsSize > <NUM_LIT> ) return false ; unsigned SubReg = TRI . getSubRegFromChannel ( Offset / <NUM_LIT> , InsSize / <NUM_LIT> ) ; if ( SubReg == <STR_LIT> ) return false ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , * MRI ) ; if ( ! DstRC ) return false ; const RegisterBank * Src0Bank = RBI . getRegBank ( Src0Reg , * MRI , TRI ) ; const RegisterBank * Src1Bank = RBI . getRegBank ( Src1Reg , * MRI


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } )

MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ;


<s> initM0 ( I ) ; return selectImpl ( I , *


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand (


<s> ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ; BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , <NUM_LIT> , SubRegs [ I ] ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubRegs [ I ] ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( DstRC && ! RBI . constrainGenericRegister ( Dst . getReg ( ) , * DstRC , * MRI ) ) return false ; } MI . eraseFromParent ( ) ; return true


<s> MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( SrcReg , * MRI , TRI ) ; auto Pred = static_cast < CmpInst :: Predicate > ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; int Opcode = getV_CMPOpcode ( Pred


<s> bool <ISA_LIT>InstructionSelector :: selectIntrinsicIcmp ( MachineInstr & I ) const { Register Dst = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isVCC ( Dst , * MRI ) ) return false ; if ( MRI -> getType ( Dst ) . getSizeInBits ( ) != STI . getWavefrontSize ( ) ) return false ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( SrcReg , * MRI , TRI ) ; auto Pred = static_cast < CmpInst :: Predicate > ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; int Opcode = getV_CMPOpcode (


<s> bool <ISA_LIT>InstructionSelector :: selectMUBUFOffsetImpl ( MachineOperand & Root , Register & RSrcReg , Register & SOffset , int64_t & Offset ) const { if ( STI . useFlatForGlobal ( ) ) return false ; MUBUFAddressData AddrData = parseMUBUFAddress ( Root . getReg ( ) ) ; if ( shouldUseAddr64 ( AddrData ) ) return false ; Register SRDPtr = AddrData . N0 ; Offset = AddrData . Offset ; MachineIRBuilder B ( * Root .


<s> bool <ISA_LIT>InstructionSelector :: selectRelocConstant ( MachineInstr & I ) const { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstBank = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( <NUM_LIT> , * DstBank , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const bool IsVALU = DstBank -> getID ( ) == <STR_LIT> ; Module * M = MF -> getFunction ( ) . getParent ( ) ; const MDNode * Metadata = I . getOperand ( <NUM_LIT> ) . getMetadata ( ) ; auto SymbolName = cast < MDString > ( Metadata -> getOperand (


<s> MachineFunction & MF = * MBB -> getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; MachineOperand & Dst = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; unsigned Depth = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( ! RC -> hasSubClassEq ( & <STR_LIT> ) || ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Depth != <NUM_LIT> || MF . getInfo < <ISA_LIT>MachineFunctionInfo > (


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } } return selectImpl ( MI , *


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } }


<s> std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root ) ; if ( ! isKnownNeverNaN ( Src , * MRI ) ) return None ; return {


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ]


<s> Optional < ValueAndVReg > ConstSelect = getConstantVRegValWithLookThrough ( LaneSelect , * MRI , true , true ) ; if ( ConstSelect ) { MIB . addReg ( Val ) ; MIB . addImm ( ConstSelect -> Value & maskTrailingOnes < uint64_t > ( STI . getWavefrontSizeLog2 ( ) ) ) ; } else { Optional < ValueAndVReg > ConstVal = getConstantVRegValWithLookThrough ( Val , * MRI , true , true ) ; if ( ConstVal && <STR_LIT> ( ConstVal -> Value , STI . hasInv2PiInlineImm ( ) ) ) { MIB . addImm ( ConstVal -> Value ) ; MIB . addReg ( LaneSelect ) ; } else { MIB . addReg ( Val ) ; RBI . constrainGenericRegister ( LaneSelect , <STR_LIT> , * MRI ) ; BuildMI ( * MBB , * MIB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LaneSelect ) ; MIB . addReg ( <STR_LIT> ) ; } } MIB . addReg ( VDstIn ) ; MI . eraseFromParent (


<s> void <ISA_LIT>InstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) { MRI = & MF . getRegInfo ( ) ; Subtarget = & MF . getSubtarget < GCNSubtarget


<s> void <ISA_LIT>InstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * P<ISA_LIT> , BlockFrequencyInfo * BFI , AAResults * AA ) { MRI = & MF .


<s> bool <ISA_LIT>InstructionSelector :: selectDSGW<ISA_LIT>ntrinsic ( MachineInstr & MI , <STR_LIT> IID ) const { if ( IID == <STR_LIT> && ! STI . hasGWSSemaReleaseAll ( ) ) return false ; const bool HasVSrc = MI . getNumOperands ( ) == <NUM_LIT> ; assert ( HasVSrc || MI . getNumOperands ( ) == <NUM_LIT> ) ; Register BaseOffset = MI . getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const RegisterBank * OffsetRB = RBI . getRegBank ( BaseOffset , * MRI , TRI ) ; if ( OffsetRB -> getID ( ) != <STR_LIT> ) return false ; MachineInstr * OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { std :: tie ( BaseOffset , ImmOffset ) = <STR_LIT> ( * MRI , BaseOffset ) ; if ( Readfirstlane ) { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT>


<s> Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; auto ConstSrc1 = getConstantVRegValWithLookThrough ( Src1 , * MRI , true , true ) ; if ( ConstSrc1 ) { auto ConstSrc0 = getConstantVRegValWithLookThrough ( Src0 , * MRI , true , true ) ; if ( ConstSrc0 ) { uint32_t Lo16 = static_cast < uint32_t > ( ConstSrc0 -> Value ) & <NUM_LIT> ; uint32_t Hi16 = static_cast < uint32_t > ( ConstSrc1 -> Value ) & <NUM_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( Lo16 | ( Hi16 << <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ; } } MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( )


<s> const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || DstSize > <NUM_LIT> ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( I . getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) ; I . eraseFromParent ( ) ; return


<s> Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || DstSize > <NUM_LIT> ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( I . getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ; const DebugLoc & DL = I . getDebugLoc (


<s> const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ; unsigned NewOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; unsigned MovOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; LLT Ty = MRI -> getType ( DstReg ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register ImmReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII .

get ( MovOpc ) , ImmReg ) . addImm ( Mask ) ;


<s> unsigned MovOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; LLT Ty = MRI -> getType ( DstReg ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register ImmReg = MRI -> createVirtualRegister ( & RegRC ) ; BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , ImmReg ) . addImm ( Mask ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , DstReg ) . addReg ( SrcReg ) . addReg ( ImmReg ) ; I . eraseFromParent ( ) ; return true


<s> MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( HighBits ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; if ( isStackPtrRelative ( PtrInfo ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset & <NUM_LIT> ) ; } } } ; } assert ( Offset == <NUM_LIT> ) ; Optional < int > FI ; Register VAddr = Root . getReg ( ) ; if ( const MachineInstr * RootDef = MRI -> getVRegDef ( Root . getReg ( ) ) ) { if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( FI . hasValue ( ) ) MIB . addFrameIndex ( FI . getValue ( ) ) ; else MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( ! Info -> isEntryFunction ( ) && FI . hasValue ( ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder


<s> const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DefTy = MRI -> getType ( DefReg ) ; const RegClassOrRegBank & RegClassOrBank = MRI -> getRegClassOrRegBank ( DefReg ) ; const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; DefRC = TRI . getRegClassForTypeOnBank ( DefTy


<s> if ( SrcReg == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( ! RC ) return true ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( ! isVCC ( SrcReg , * MRI ) ) { if ( ! RBI . constrainGenericRegister ( DstReg , * TRI . getBoolRC ( ) , * MRI ) ) return false ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; Register MaskedReg = MRI -> createVirtualRegister ( SrcRC ) ; unsigned AndOpc = TRI . isSGPRClass ( SrcRC ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( AndOpc ) , MaskedReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm (


<s> BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( PtrBase ) ; if ( ! RBI . constrainGenericRegister ( PtrBase , <STR_LIT> , * MRI ) ) return false ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Offset ) . addImm ( IsGDS ? - <NUM_LIT> : <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent


<s> case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent (


<s> Register DstReg0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg0 ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const unsigned SrcFlags = getUndefRegState ( Src . isUndef ( ) ) ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I ) ; BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: COPY ) , Dst . getReg ( ) ) . addReg ( SrcReg , SrcFlags , SubRegs


<s> const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const unsigned SrcFlags = getUndefRegState ( Src . isUndef ( ) ) ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SrcRC , DstSize / <NUM_LIT> ) ; for ( int I = <NUM_LIT> , E = NumDst ; I != E ; ++ I ) { MachineOperand & Dst = MI . getOperand ( I


<s> static unsigned extractDLC ( unsigned AuxiliaryData ) { return ( AuxiliaryData >>


<s> return ( AuxiliaryData >> <NUM_LIT> ) &


<s> } int64_t Offset ; if ( Def -> getOpcode ( ) == <STR_LIT> ) { if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Offset ) ) ) return std :: make_tuple ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset , Def ) ; if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_Copy ( m_ICst ( Offset ) ) ) ) return std :: make_tuple ( Def -> getOperand


<s> static unsigned getBufferStoreFormatOpcode ( LLT Ty , const unsigned MemSize , const bool Offen ) { bool IsD16Packed = Ty . getScalarSizeInBits ( ) == <NUM_LIT> ; bool IsD16Unpacked = <NUM_LIT> * MemSize < Ty . getSizeInBits ( ) ; int NumElts = Ty . isVector ( ) ? Ty . getNumElements ( ) : <NUM_LIT> ; if ( IsD16Packed ) { switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; default : return - <NUM_LIT> ; } } if ( IsD16Unpacked ) { switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case


<s> if ( ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) || ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) ) return false ; if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ; return KnownBits -> signBitIsZero ( Base . getReg (


<s> if ( mi_match ( Reg , MRI , m_ICst ( C ) ) && C == <NUM_LIT> ) return true ; return mi_match ( Reg , MRI , m_Copy ( m_ICst ( C ) ) ) && C


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; assert ( CstVal &&


<s> if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC


<s> if ( isDSOffsetLegal ( * MRI , LHS , PossibleOffset , <NUM_LIT> ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PossibleOffset ) ; } } } ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { } else if ( mi_match ( Root . getReg ( ) , * MRI , m_ICst ( ConstAddr ) ) ) { } return


<s> MachineInstr * Add = BuildMI ( * BB , & I , DL , TII . get ( Opc ) , DstReg ) . addDef ( UnusedCarry , RegState :: Dead ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Add , TII , TRI , RBI ) ; } assert ( ! Sub && <STR_LIT> ) ; const TargetRegisterClass & RC = IsSALU ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & HalfRC = IsSALU ? <STR_LIT> : <STR_LIT> ; MachineOperand Lo1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Lo2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; Register DstLo = MRI -> createVirtualRegister ( & HalfRC ) ; Register DstHi = MRI -> createVirtualRegister ( & HalfRC ) ; if ( IsSALU ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . add ( Lo1 ) . add ( Lo2 ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . add ( Hi1 ) . add ( Hi2 ) ; } else { const TargetRegisterClass * CarryRC = TRI . getWaveMaskRegClass ( ) ; Register CarryReg = MRI -> createVirtualRegister ( CarryRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . addDef ( CarryReg ) . add ( Lo1 ) . add ( Lo2 ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addc = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . addDef ( MRI -> createVirtualRegister ( CarryRC ) , RegState :: Dead ) . add ( Hi1 ) . add ( Hi2 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * Addc , TII , TRI , RBI ) ) return false ; } BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( DstReg , RC , * MRI ) ) return false ; I . eraseFromParent


<s> MachineOperand & Src1 = I . getOperand ( <NUM_LIT> ) ; Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI


<s> Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI ,


<s> } else return false ; if ( ! MRI -> getRegClassOrNull ( CondReg ) ) MRI -> setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ; BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) . addMBB ( I . getOperand


<s> if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; return RBI . constrainGenericRegister ( DstReg , IsVGPR ? <STR_LIT> : <STR_LIT>


<s> unsigned Size = RBI . getSizeInBits ( SrcReg , * MRI , TRI ) ; auto Pred = ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ; Register CCReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isSCC ( CCReg , * MRI ) ) { int Opcode = getS_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , * MRI ) ; I . eraseFromParent ( ) ; return Ret ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg (


<s> const RegisterBank * Src1Bank = RBI . getRegBank ( Src1Reg , * MRI , TRI ) ; const TargetRegisterClass * Src0RC = TRI . getRegClassForSizeOnBank ( DstSize , * Src0Bank , * MRI ) ; const TargetRegisterClass * Src1RC = TRI . getRegClassForSizeOnBank ( InsSize , * Src1Bank , * MRI ) ; Src0RC = TRI . getSubClassWithSubReg ( Src0RC , SubReg ) ; if ( ! Src0RC ) return false ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , * Src0RC , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , * Src1RC , * MRI ) ) return false ; const DebugLoc & DL = I


<s> int64_t Enabled = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Done = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VM = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , VM , false , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Enabled = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Reg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg1 = I . getOperand ( <NUM_LIT> )


<s> const DebugLoc & DL = I . getDebugLoc ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; assert ( Size <= <NUM_LIT> || Size == <NUM_LIT> ) ; const MachineOperand & CCOp = I . getOperand ( <NUM_LIT> ) ; Register CCReg = CCOp . getReg ( ) ; if ( isSCC ( CCReg , * MRI ) ) { unsigned SelectOpcode = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * CopySCC = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CCReg ) ; if ( ! MRI -> getRegClassOrNull ( CCReg ) ) MRI -> setRegClass ( CCReg , TRI . getConstrainedRegClassForOperand ( CCOp , * MRI ) ) ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( SelectOpcode ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) .


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register Dst0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Dst1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool IsAdd = I . getOpcode ( ) == <STR_LIT> ; if ( ! isSCC ( Dst1Reg , MRI ) ) { unsigned NewOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; I . setDesc ( TII . get ( NewOpc ) ) ; I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( NewOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI . getRegClassOrNull ( Dst1Reg ) ) MRI . setRegClass ( Dst1Reg , & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , MRI ) || ! RBI .

constrainGenericRegister ( Src1Reg , <STR_LIT> , MRI ) ) return false ;


<s> const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } Register SOffset = FI . hasValue ( ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; return { { [ = ]


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectMUBUFScratchOffset ( MachineOperand & Root ) const { MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; int64_t Offset = <NUM_LIT> ; if ( ! mi_match ( Root . getReg ( ) , * MRI , m_ICst ( Offset ) ) || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; int64_t Offset = <NUM_LIT> ; if ( ! mi_match ( Root . getReg ( ) , * MRI , m_ICst ( Offset ) ) || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( Offset ) ) return { } ; const MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; Register SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; return


<s> const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; if ( RB . getID ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DefRC = TRI . getRegClassForTypeOnBank ( DefTy , RB , * MRI ) ; if ( ! DefRC


<s> int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! isUInt < <NUM_LIT> > ( EncodedImm ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( EncodedImm


<s> SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , * MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Register OffsetReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( OffsetReg


<s> getBufferStoreOpcode ( Ty , MemSize , Offen ) ; if ( Opc == - <NUM_LIT> ) return false ; MachineInstrBuilder MIB = B . buildInstr ( Opc ) . addUse ( VData ) ; if ( Offen ) MIB . addUse ( VOffset ) ; MIB . addUse ( RSrc ) . addUse ( SOffset ) . addImm ( ImmOffset ) . addImm ( extractGLC ( AuxiliaryData ) ) . addImm ( extractSLC ( AuxiliaryData ) ) . addImm ( <NUM_LIT> ) . addImm ( extractDLC ( AuxiliaryData ) ) . addImm ( extractSWZ ( AuxiliaryData ) ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI ,


<s> getBufferStoreOpcode ( Ty , MemSize , Offen ) ; if ( Opc == - <NUM_LIT> ) return false ; MachineInstrBuilder MIB = B . buildInstr ( Opc ) . addUse ( VData ) ; if ( Offen ) MIB . addUse ( VOffset ) ; MIB . addUse ( RSrc ) . addUse ( SOffset ) . addImm ( ImmOffset ) . addImm ( extractGLC ( AuxiliaryData ) ) . addImm ( extractSLC ( AuxiliaryData ) ) . addImm ( <NUM_LIT> ) . addImm ( extractDLC ( AuxiliaryData ) ) . addImm ( extractSWZ (

AuxiliaryData ) ) . addMemOperand ( MMO ) ;


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ =


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } }


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3Mods0Clamp0OMod ( MachineOperand & Root ) const { Register Src ; unsigned Mods ; std :: tie ( Src , Mods ) = selectVOP3ModsImpl ( Root . getReg ( ) ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } }


<s> Mods |= <STR_LIT> ; MI = MRI -> getVRegDef ( Src ) ; } if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) { Src = MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3OpSelMods0 ( MachineOperand & Root ) const { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Root . getReg ( ) ) ; } , [ = ]

( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI -> getType ( DstReg ) ; const LLT SrcTy = MRI -> getType ( SrcReg ) ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const RegisterBank * DstRB ; if ( DstTy == S1 ) { DstRB = SrcRB ; } else { DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( SrcRB != DstRB ) return false ; } const bool IsVALU = DstRB -> getID ( ) == <STR_LIT> ; unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) && SrcTy == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { MachineBasicBlock * MBB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register LoReg = MRI -> createVirtualRegister ( DstRC ) ; Register HiReg = MRI -> createVirtualRegister ( DstRC ) ; BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; if ( IsVALU && STI . hasSDWA ( ) ) { MachineInstr * MovSDWA = BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( HiReg ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_1 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_0 ) . addReg ( LoReg , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { Register TmpReg0 = MRI -> createVirtualRegister ( DstRC ) ; Register TmpReg1 = MRI -> createVirtualRegister ( DstRC ) ; Register ImmReg = MRI -> createVirtualRegister ( DstRC ) ; if ( IsVALU ) { BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , TmpReg0 ) . addImm ( <NUM_LIT>


<s> Optional < uint64_t > OffsetVal = getConstantZext32Val ( Root . getReg ( ) , * MRI ) ; if ( ! OffsetVal ) return { } ; Optional < int64_t > EncodedImm = <STR_LIT> ( STI , *


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectSMRDBufferImm ( MachineOperand & Root ) const { Optional < uint64_t > OffsetVal = getConstantZext32Val ( Root . getReg ( ) , * MRI ) ; if ( ! OffsetVal ) return {


<s> if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Optional < int64_t > EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! EncodedImm ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( * EncodedImm


<s> if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Optional < int64_t > EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! EncodedImm ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [


<s> case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> : return Signed ? <NUM_LIT> :


<s> if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ; Register BasePtr = OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( BasePtr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset . getValue ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT>


<s> const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ; } default : return selectImpl ( I ,


<s> bool <ISA_LIT>InstructionSelector :: selectG_<ISA_LIT>TOFP_UITOFP ( MachineInstr & I ) const { MachineBasicBlock * MBB = I . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register Src = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isSCC ( Src , MRI ) ) return selectImpl ( I , * CoverageInfo ) ; bool Signed = I . getOpcode ( ) == <STR_LIT> ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType (


<s> bool Signed = I . getOpcode ( ) == <STR_LIT> ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Src ) ; unsigned NewOpc = DstSize > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( * MBB , I , DL , TII . get ( NewOpc ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( getFPTrueImmVal ( DstSize , Signed ) ) ; if ( ! constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ) return false ; I . eraseFromParent ( ) ; return true


<s> getAddrModeInfo ( * MI , * MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; if ( ! GEPInfo . Imm || ! isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) return None ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Register OffsetReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg (


<s> default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C : return selectG_INTRIN<ISA_LIT>C ( I


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS128Bit8ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root , true


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS128Bit8ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root ,


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned


<s> [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Reg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , [


<s> int64_t OffsetValue0 = Offset / ( IsDS128 ? <NUM_LIT> : <NUM_LIT> ) ; int64_t OffsetValue1 = OffsetValue0 + <NUM_LIT> ; if ( isDSOffsetLegal ( PtrBase , OffsetValue1 , ( IsDS128 ? <NUM_LIT> : <NUM_LIT> ) ) ) { return std :: make_pair ( PtrBase , OffsetValue0 ) ; } } else if ( RootDef -> getOpcode ( )


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( isUInt < <NUM_LIT> > ( GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , OffsetReg ) . addImm ( GEPInfo . Imm ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addReg ( OffsetReg


<s> if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; switch ( I . getOpcode ( ) ) { default : break ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_CONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP (


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode ::


<s> Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef && RHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ; return {


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == -


<s> LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % DstSize != <NUM_LIT> ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC )


<s> if ( ! MRI -> getRegClassOrNull ( CCReg ) ) MRI -> setRegClass ( CCReg , TRI . getConstrainedRegClassForOperand ( CCOp , * MRI ) ) ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( SelectOpcode ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select


<s> if ( I . getOpcode ( ) == <STR_LIT> ) return selectCOPY ( I ) ; const RegisterBank * SrcBank = getArtifactRegBank ( SrcReg , * MRI , TRI ) ; if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( Mask ) . addReg ( SrcReg ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } const unsigned BFE = Signed ? <STR_LIT> : <STR_LIT> ; MachineInstr * ExtI = BuildMI ( MBB , I , DL , TII . get ( BFE ) , DstReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( SrcSize ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; } if ( SrcBank -> getID ( ) == <STR_LIT> && DstSize <= <NUM_LIT> ) { if ( ! RBI . constrainGenericRegister ( SrcReg , <STR_LIT> , * MRI ) ) return false ; if ( Signed && DstSize == <NUM_LIT> && ( SrcSize == <NUM_LIT> || SrcSize == <NUM_LIT> ) ) { const unsigned SextOpc = SrcSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII . get ( SextOpc ) , DstReg ) . addReg ( SrcReg ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } const unsigned BFE64 = Signed ? <STR_LIT> : <STR_LIT> ; const unsigned BFE32 = Signed ? <STR_LIT> : <STR_LIT> ; if ( DstSize > <NUM_LIT> && SrcSize <= <NUM_LIT> ) { Register ExtReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , ExtReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) . addReg ( UndefReg ) . addImm ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( BFE64 ) , DstReg ) . addReg ( ExtReg ) . addImm ( SrcSize << <NUM_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , * MRI ) ; } unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) .


<s> } else { DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( SrcRB != DstRB ) return false ; } unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstRB , * MRI ) ; if ( SrcSize > <NUM_LIT> ) { int SubRegIdx = sizeToSubRegIndex ( DstSize ) ; if ( SubRegIdx == - <NUM_LIT> ) return false ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register DstReg = MRI . createVirtualRegister ( & SubRC ) ; if ( MO . isReg ( ) ) { unsigned ComposedSubIdx = TRI . composeSubRegIndices ( MO . getSubReg ( ) , SubIdx ) ; unsigned Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ; } assert ( MO . isImm ( ) ) ; APInt Imm ( <NUM_LIT> , MO . getImm ( ) ) ; switch ( SubIdx ) { default : llvm_unreachable ( <STR_LIT> ) ; case


<s> const LLT Ty = MRI . getType ( Reg ) ; return Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID ( )


<s> auto & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { if ( RC -> getID ( ) != <STR_LIT> ) return false ; const LLT Ty = MRI . getType ( Reg ) ; return Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ; return RB -> getID ( )


<s> auto & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; const TargetRegisterClass * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( RC ) { const LLT Ty = MRI . getType ( Reg ) ; return RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) && Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get


<s> case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : case TargetOpcode :: G_XOR : if ( selectG_AND_OR_XOR ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectG_ADD_SUB ( I ) ) return true ; LLVM_FALLTHROUGH ; default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_BUILD_VECTOR : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode ::


<s> I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI . getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI . setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI . getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI . setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand (


<s> if ( isSCC ( CCReg , MRI ) ) { int Opcode = getS_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) && RBI . constrainGenericRegister ( CCReg , <STR_LIT> , MRI ) ; I . eraseFromParent ( ) ; return Ret


<s> bool <ISA_LIT>InstructionSelector :: selectG_LOAD ( MachineInstr & I ) const { return false


<s> bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) ; I . eraseFromParent


<s> Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> std :: tie ( PtrBase , ConstOffset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( ConstOffset == <NUM_LIT> ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( ConstOffset , AddrSpace , Signed ) ) return Default ; return std :: make_pair ( PtrBase


<s> unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( ConstOffset , AddrSpace , Signed ) ) return Default ; return std :: make_pair (


<s> if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { int FI = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } Register SAddr = AddrDef -> Reg ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef && RHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ; return {


<s> MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( PtrReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI . getRegClassOrNull ( Reg ) ) MRI . setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ; } default : return selectImpl ( I , CoverageInfo


<s> default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode ::


<s> assert ( Size == <NUM_LIT> ) ; unsigned CCReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isSCC ( CCReg , MRI ) ) { unsigned Opcode = getS_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; MachineInstr * Copy = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * Copy , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } assert ( Size == <NUM_LIT> || Size == <NUM_LIT> ) ; unsigned Opcode = getV_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent (


<s> void <ISA_LIT>InstructionSelector :: renderTruncImm32 ( MachineInstrBuilder & MIB , const MachineInstr & MI ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; Optional < int64_t > CstVal = getConstantVRegVal ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; assert ( CstVal && <STR_LIT>


<s> unsigned IntrinsicID = I . getIntrinsicID ( ) ; switch ( IntrinsicID ) { case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) .


<s> case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return selectDivScale ( I


<s> unsigned Mods = <NUM_LIT> ; MachineInstr * MI = getDefIgnoringCopies ( Src , * MRI ) ; if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) { Src = MI -> getOperand ( <NUM_LIT> ) . getReg (


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT>


<s> if ( ! isInstrUniform ( I ) ) return false ; if ( hasVgprParts ( AddrInfo ) ) return false ; MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; } if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI ,


<s> ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SuperRC , EltSize ) ; if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ; return std :: make_pair ( IdxBaseReg , SubRegs [


<s> if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ; return std :: make_pair ( IdxBaseReg


<s> MIB . addImm ( MI . getOperand ( OpIdx ) . getImm


<s> MIB . addImm ( MI . getOperand ( OpIdx ) .


<s> void <ISA_LIT>InstructionSelector :: renderTruncTImm16 ( MachineInstrBuilder & MIB , const MachineInstr & MI


<s> void <ISA_LIT>InstructionSelector :: renderTruncTImm32 ( MachineInstrBuilder & MIB , const MachineInstr &


<s> MIB . addImm ( MI . getOperand ( OpIdx


<s> if ( ! RootDef ) return std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; int64_t ConstAddr = <NUM_LIT> ; if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( isDSOffsetLegal ( LHS . getReg ( ) , PossibleOffset , <NUM_LIT> ) ) { return std :: make_pair ( LHS . getReg ( ) , PossibleOffset ) ; } } } else if ( RootDef -> getOpcode


<s> case <STR_LIT> : { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectStoreIntrinsic ( I , false ) ; case <STR_LIT> : return selectStoreIntrinsic ( I , true ) ; case <STR_LIT> : case <STR_LIT> : return selectDSOrderedIntrinsic ( I , IntrinsicID ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isVCC ( DstReg , MRI ) ) { const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; if ( ! MRI . getRegClassOrNull ( SrcReg ) ) MRI . setRegClass ( SrcReg , TRI . getConstrainedRegClassForOperand ( Src , MRI ) ) ; I . eraseFromParent ( ) ; return true ; } } for ( const MachineOperand & MO : I . operands ( ) ) { if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI .

getConstrainedRegClassForOperand ( MO , MRI ) ;


<s> return Ret ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent


<s> const unsigned DstSize = DstTy . getSizeInBits ( ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForSizeOnBank ( DstSize , * DstBank , MRI ) ; if ( ! DstRC ) return false ; ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( DstRC , SrcSize / <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * BB , & MI , DL , TII . get ( TargetOpcode :: REG_SEQUENCE ) , DstReg ) ; for ( int I = <NUM_LIT> , E = MI . getNumOperands ( ) - <NUM_LIT> ; I !=


<s> static Register buildAddr64RSrc ( MachineIRBuilder & B , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & TII , Register BasePtr ) { uint64_t DefaultFormat = TII


<s> return buildRSRC ( B , MRI , - <NUM_LIT> , Hi_32 ( DefaultFormat )


<s> if ( IdxBaseReg == <STR_LIT> ) { assert ( Offset == <NUM_LIT> ) ; IdxBaseReg = IdxReg ; } ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SuperRC , EltSize ) ; if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ; return std :: make_pair ( IdxBaseReg , SubRegs


<s> MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI


<s> MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , *


<s> GEPInfo GEPInfo ( * PtrMI ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { const MachineOperand & GEPOp = PtrMI -> getOperand ( i ) ; const MachineInstr * OpDef = MRI . getUniqueVRegDef ( GEPOp . getReg ( ) ) ; assert ( OpDef ) ; if ( i == <NUM_LIT> && isConstant ( * OpDef ) ) { assert ( GEPInfo . Imm == <NUM_LIT> ) ; GEPInfo . Imm = OpDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; continue ; } const RegisterBank * OpBank = RBI . getRegBank ( GEPOp . getReg ( ) , MRI , TRI ) ; if ( OpBank -> getID ( ) == <STR_LIT> ) GEPInfo . SgprParts . push_back ( GEPOp . getReg ( ) ) ; else GEPInfo . VgprParts . push_back (


<s> const RegClassOrRegBank & RegClassOrBank = MRI . getRegClassOrRegBank ( Reg ) ; if ( auto * RB = RegClassOrBank . dyn_cast < const RegisterBank * > ( ) ) return RB ; if ( auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( )

) return & RBI . getRegBankFromRegClass ( * RC , LLT ( ) ) ;


<s> if ( auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ) return & RBI . getRegBankFromRegClass ( * RC , LLT ( ) ) ; return nullptr


<s> Optional < int64_t > OffsetVal = getConstantVRegVal ( Reg , MRI ) ; if ( ! OffsetVal || ! isInt < <NUM_LIT> > ( * OffsetVal ) ) return None ; return Lo_32 ( * OffsetVal )


<s> switch ( MF . getFunction ( ) . getCallingConv ( ) ) { case CallingConv :: <ISA_LIT>_PS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_VS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_GS : return <NUM_LIT> ; case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_ES : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: C


<s> case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_ES : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv


<s> static unsigned getLogicalBitOpcode ( unsigned Opc , bool Is64 ) { switch ( Opc ) { case <STR_LIT> : return Is64 ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Is64 ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Is64 ? <STR_LIT>


<s> MachineOperand & RHS = RootI -> getOperand ( <NUM_LIT> ) ; Optional < ValueAndVReg > MaybeOffset = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI , true ) ; if ( ! MaybeOffset ) return { Root , <NUM_LIT> } ; return { RootI -> getOperand ( <NUM_LIT> ) . getReg ( ) ,


<s> Register DstReg = MRI -> createVirtualRegister ( & SubRC ) ; if ( MO . isReg ( ) ) { unsigned ComposedSubIdx = TRI . composeSubRegIndices ( MO . getSubReg ( ) , SubIdx ) ; Register Reg = MO . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( Reg , <NUM_LIT> , ComposedSubIdx ) ; return MachineOperand :: CreateReg ( DstReg , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isEarlyClobber ( ) , <NUM_LIT> , MO . isDebug ( ) , MO . isInternalRead ( ) ) ; } assert ( MO . isImm ( ) ) ; APInt Imm ( <NUM_LIT> , MO . getImm ( ) ) ; switch ( SubIdx


<s> return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_EQ : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SGT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SGE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SLT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_SLE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_UGT : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_UGE : return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; case CmpInst :: ICMP_ULT : return Size == <NUM_LIT> ? <STR_LIT> :


<s> if ( ! GEPInfo . VgprParts . empty ( )


<s> static bool isConstant ( const MachineInstr


<s> if ( ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) || ( OffsetBits == <NUM_LIT> &&

! isUInt < <NUM_LIT> > ( Offset ) ) ) return false ;


<s> bool <ISA_LIT>InstructionSelector :: isInlineImmediate ( const APFloat


<s> auto PSV = PtrInfo . V . dyn_cast < const PseudoSourceValue * > ( ) ; return PSV && PSV -> isStack (


<s> static bool isStackPtrRelative ( const MachinePointerInfo & PtrInfo ) { auto PSV = PtrInfo . V . dyn_cast < const PseudoSourceValue * > ( ) ; return PSV && PSV -> isStack


<s> if ( RC ) { const LLT Ty = MRI . getType ( Reg ) ; return RC -> hasSuperClassEq ( TRI . getBoolRC ( ) ) && Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * >


<s> static bool isZero ( Register Reg , const MachineRegisterInfo & MRI ) { int64_t Val ; return mi_match ( Reg , MRI , m_ICst ( Val ) ) && Val


<s> static bool isZero ( Register Reg , const MachineRegisterInfo & MRI ) { int64_t Val ; return mi_match ( Reg , MRI , m_ICst ( Val )


<s> static bool isZeroOrOneOrUndef ( int X ) { return X == <NUM_LIT> || X == <NUM_LIT> || X ==


<s> NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; if ( isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) && isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) ) return Src0 ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; NewMask [ <NUM_LIT> ] = NewMask [ <NUM_LIT> ] == - <NUM_LIT> ? - <NUM_LIT> : NewMask [ <NUM_LIT> ] - <NUM_LIT> ; NewMask [ <NUM_LIT> ] = NewMask [ <NUM_LIT> ] == - <NUM_LIT> ? - <NUM_LIT>


<s> Data . Offset = Offset ; } if ( MachineInstr * InputAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Data . N0 , * MRI ) ) { Data . N2 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N3 = InputAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Data . N2 = getDefIgnoringCopies ( Data . N2 , * MRI ) -> getOperand (


<s> static bool parseTexFail ( uint64_t TexFailCtrl , bool & TFE , bool & LWE , bool & IsTexFail ) { if ( TexFailCtrl ) IsTexFail = true ; TFE = ( TexFailCtrl & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; TexFailCtrl &= ~ ( uint64_t ) <NUM_LIT> ; LWE = ( TexFailCtrl & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; TexFailCtrl &= ~ ( uint64_t ) <NUM_LIT> ; return TexFailCtrl


<s> assert ( OpIdx == - <NUM_LIT> ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT ) MIB . addImm ( Op . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT>


<s> assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( ( MI . getOperand ( OpIdx ) . getImm


<s> void <ISA_LIT>InstructionSelector :: renderExtractGLC ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( OpIdx >= <NUM_LIT>


<s> void <ISA_LIT>InstructionSelector :: renderExtractSWZ ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( ( MI . getOperand ( OpIdx ) . getImm ( ) >> <NUM_LIT>


<s> void <ISA_LIT>InstructionSelector :: renderNegateImm ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == -


<s> void <ISA_LIT>InstructionSelector :: renderNegateImm ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( - MI . getOperand ( <NUM_LIT> )


<s> MIB . addImm ( MI . getOperand ( <NUM_LIT> )


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( MI . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue (


<s> void <ISA_LIT>InstructionSelector :: renderTruncTImm ( MachineInstrBuilder & MIB , const


<s> Register DstReg = Dst . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( isVCC ( DstReg , * MRI ) ) { if ( SrcReg == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( ! RC ) return true ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( ! isVCC ( SrcReg , * MRI ) ) { if ( ! RBI . constrainGenericRegister ( DstReg , * TRI . getBoolRC ( ) , * MRI ) ) return false ; const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; Register MaskedReg = MRI -> createVirtualRegister ( SrcRC ) ; unsigned AndOpc = TRI . isSGPRClass ( SrcRC ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( AndOpc ) , MaskedReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( MaskedReg ) ; if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , SrcRC ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC ) continue ; RBI . constrainGenericRegister ( MO . getReg ( )


<s> I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ; if ( ! RC


<s> Register Dst1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI -> getType ( Dst0 ) ; unsigned Opc ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; Register Numer = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Denom = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ChooseDenom = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register Src0 = ChooseDenom != <NUM_LIT> ?


<s> int64_t Offset ; std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( Offset ) { if ( isDSOffsetLegal ( PtrBase , Offset , <NUM_LIT> ) ) { return std :: make_pair ( PtrBase , Offset ) ; } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { } else if ( mi_match ( Root . getReg ( ) , *


<s> int64_t ConstAddr = <NUM_LIT> ; Register PtrBase ; int64_t Offset ; std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( Offset ) { if ( isDSOffsetLegal ( PtrBase , Offset , <NUM_LIT> ) ) { return std :: make_pair ( PtrBase , Offset ) ; } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { } else if ( mi_match ( Root . getReg ( ) , * MRI


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned ( MachineOperand & Root ) const { Register Reg ; unsigned Offset ; std :: tie ( Reg , Offset ) = selectDS64Bit4ByteAlignedImpl ( Root ) ; return {


<s> PtrBase = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = <NUM_LIT> ; } MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const unsigned Opc = IsAppend ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( PtrBase ) ; BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) )

. addImm ( Offset ) . addImm ( IsGDS ? - <NUM_LIT> : <NUM_LIT> ) . cloneMemRefs ( MI ) ;


<s> if ( OffsetRB -> getID ( ) != <STR_LIT> ) return false ; MachineInstr * OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { std :: tie ( BaseOffset , ImmOffset , OffsetDef ) = <STR_LIT> ( * MRI


<s> MachineFunction * MF = MBB -> getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned IndexOperand = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool WaveRelease = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; bool WaveDone = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; if ( WaveDone && ! WaveRelease ) report_fatal_error ( <STR_LIT> ) ; unsigned OrderedCountIndex = IndexOperand & <NUM_LIT> ; IndexOperand &= ~ <NUM_LIT> ; unsigned CountDw = <NUM_LIT> ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { CountDw = ( IndexOperand >> <NUM_LIT> ) & <NUM_LIT> ; IndexOperand &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; if ( CountDw < <NUM_LIT> || CountDw > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } } if ( IndexOperand ) report_fatal_error ( <STR_LIT> ) ; unsigned Instruction = IntrID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned ShaderType = getDSShaderTypeValue ( * MF ) ; unsigned Offset0 = OrderedCountIndex << <NUM_LIT> ; unsigned Offset1 = WaveRelease | ( WaveDone << <NUM_LIT> ) | ( ShaderType << <NUM_LIT> ) | ( Instruction << <NUM_LIT> ) ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) Offset1 |= ( CountDw - <NUM_LIT> ) << <NUM_LIT> ; unsigned Offset = Offset0 | ( Offset1 << <NUM_LIT> ) ; Register M0Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Val ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder DS = BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( ValReg ) . addImm ( Offset ) . cloneMemRefs ( MI ) ; if ( ! RBI . constrainGenericRegister ( M0Val , <STR_LIT> , * MRI ) ) return false ; bool Ret = constrainSelectedInstRegOperands ( * DS , TII , TRI


<s> Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MI . eraseFromParent ( ) ; if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI .


<s> BuildMI ( * BB , & MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MI . eraseFromParent ( ) ; if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectFlatOffset ( MachineOperand & Root ) const { return selectFlatOffsetImpl < false


<s> } } ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) ,


<s> return selectFlatOffsetImpl < true > (


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectFlatOffsetSigned ( MachineOperand


<s> Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; int64_t ShiftAmt ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) .


<s> if ( RB ) { IsSgpr = RB -> getID ( ) == <STR_LIT> ; Size = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; } else { const TargetRegisterClass * RC = TRI . getRegClassForReg ( * MRI , DstReg ) ; IsSgpr = TRI . isSGPRClass ( RC ) ; Size = TRI . getRegSizeInBits ( * RC ) ; } if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return false ; unsigned Opcode = IsSgpr ? <STR_LIT> : <STR_LIT> ; if ( Size == <NUM_LIT> ) { I . setDesc ( TII . get ( Opcode ) ) ; I . addImplicitDefUseOperands ( * MF ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } const DebugLoc & DL = I . getDebugLoc ( ) ; APInt Imm ( Size , I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MachineInstr * ResInst ; if ( IsSgpr && TII . isInlineConstant ( Imm ) ) { ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else { const TargetRegisterClass * RC = IsSgpr ? & <STR_LIT> : & <STR_LIT> ; Register LoReg = MRI -> createVirtualRegister ( RC ) ; Register HiReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ; ResInst = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ; } I . eraseFromParent ( ) ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( ResInst -> getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC ) return true ; return RBI . constrainGenericRegister ( DstReg , * DstRC , *


<s> const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( IdxReg

) . addImm ( <STR_LIT> :: SRC0_ENABLE ) ;


<s> Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IdxReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( SrcTy , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( DstTy , * DstRB , * MRI ) ; if ( ! SrcRC || ! DstRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , RegState :: Undef , SubReg )


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register LoReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register HiReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register ConstReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register OpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( Src , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , ConstReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , OpReg ) . addReg ( HiReg ) . addReg ( ConstReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( OpReg ) . addImm ( <STR_LIT> ) ; MI . eraseFromParent (


<s> I . setDesc ( TII . get ( IsVGPR ? <STR_LIT> : <STR_LIT> ) ) ; if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; return RBI . constrainGenericRegister ( DstReg , IsVGPR