<s> default : return nullptr ; case <STR_LIT> : break ; case <STR_LIT> : { const MachineOperand * Src0 = getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( * Src0 , <NUM_LIT> ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( * MI , <STR_LIT> :: dst ) ; const MachineOperand * Src0 = getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( * MI , <STR_LIT> :: src1


<s> if ( Src1Idx == - <NUM_LIT> ) return false ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) ) { if ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) return false ; } else if ( Src1 . isReg ( ) ) { if ( hasModifiersSet ( * MI , <STR_LIT> :: src0_modifiers ) || hasModifiersSet ( * MI , <STR_LIT> :: src1_modifiers ) ) return false ; } else return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx


<s> Src1 -> setIsKill ( Src2 -> isKill ( ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || ( Src1 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) ) return false ; const int64_t Imm = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( RI . hasVGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; return NewDstRC ; default : return NewDstRC


<s> if ( isDS ( * LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; if ( OffsetImm ) { const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } const MachineOperand * Offset0Imm = getNamedOperand ( * LdSt , <STR_LIT> :: offset0 ) ; const MachineOperand * Offset1Imm = getNamedOperand ( * LdSt , <STR_LIT> :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; if ( Offset1 > Offset0 && Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt -> mayLoad ( ) ) EltSize = getOpRegClass ( * LdSt , <NUM_LIT> ) -> getSize ( ) / <NUM_LIT> ; else { assert ( LdSt -> mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = getOpRegClass ( * LdSt , Data0Idx ) -> getSize ( ) ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( * LdSt ) || isMTBUF ( * LdSt ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( * LdSt ,


<s> switch ( MI . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> )


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) ,


<s> bool <ISA_LIT>InstrInfo :: isInlineConstant ( const MachineOperand & MO , unsigned OpSize ) const { if ( MO . isImm (


<s> bool <ISA_LIT>InstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ?


<s> if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg


<s> bool <ISA_LIT>InstrInfo :: isLiteralConstant ( const MachineOperand & MO , unsigned OpSize


<s> bool <ISA_LIT>InstrInfo :: isMov ( unsigned Opcode ) const { switch ( Opcode ) { default : return


<s> <STR_LIT> ( Opc , <STR_LIT> :: src0 ) , <STR_LIT> ( Opc , <STR_LIT> :: src1 ) , <STR_LIT> ( Opc , <STR_LIT> :: src2 ) } ; unsigned SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx ==


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & <STR_LIT> , VRC ) ) VRC = & <STR_LIT> ; else VRC = & <STR_LIT> ; unsigned Reg = MRI . createVirtualRegister ( VRC


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineOperand & MO = MI -> getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI -> getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = <STR_LIT> ; if ( MO . isReg ( )


<s> } if ( ! ST . isVGPRSpillingEnabled ( MFI ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI

-> getScratchRSrcReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) . addMemOperand ( MMO ) ;


<s> MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( Src .


<s> unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( Src . getReg ( ) ) . addReg ( TmpReg ) ; MRI . replaceRegWith ( Dest .


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; int DstIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: dst ) ; assert ( DstIdx != - <NUM_LIT> ) ; unsigned DstRCID = get ( MI -> getOpcode ( ) ) . OpInfo [ DstIdx ] . RegClass ; switch ( RI . getRegClass ( DstRCID ) -> getSize ( ) ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpcode = getVALUOp ( * MI ) ; unsigned RegOffset ; unsigned ImmOffset ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { RegOffset = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ImmOffset = <NUM_LIT> ; } else { assert ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; ImmOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) ImmOffset <<= <NUM_LIT> ; RegOffset = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( ImmOffset ) ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ; const MCInstrDesc & NewInstDesc = get


<s> if ( isDS ( * FirstLdSt ) && isDS ( * SecondLdSt ) ) return true ; if ( isSMRD ( * FirstLdSt ) && isSMRD ( * SecondLdSt ) ) return true ; if ( ( isMUBUF ( * FirstLdSt ) || isMTBUF ( * FirstLdSt ) ) && ( isMUBUF

( * SecondLdSt ) || isMTBUF ( * SecondLdSt ) ) ) return true ;


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; DebugLoc DL = Inst -> getDebugLoc ( ) ; MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . addOperand ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . addOperand ( SrcRegSub1 ) . addReg ( MidReg ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI ,


<s> uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; ( void ) Offset ; assert ( Inst -> getOpcode ( ) == <STR_LIT> && BitWidth <= <NUM_LIT> && Offset == <NUM_LIT> && <STR_LIT> ) ; if ( BitWidth < <NUM_LIT> ) { unsigned MidRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned MidRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return ; } MachineOperand & Src = Inst ->


<s> const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg


<s> const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg


<s> assert ( Inst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; MachineOperand Op1 = Inst -> getOperand ( <NUM_LIT> ) ; Inst -> RemoveOperand ( <NUM_LIT>


<s> if ( MI . findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) return ; if ( MI . findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> )


<s> assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa )


<s> } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF (


<s> unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm


<s> return nullptr ; case <STR_LIT> : break ; case <STR_LIT> : { const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( * Src0 , <NUM_LIT> ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI


<s> const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . addOperand ( * Dst ) . addImm ( <NUM_LIT> ) . addOperand ( * Src0 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src1 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src2 )

. addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_3_64 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_7_64 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_15_64 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_1 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_2 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_3 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_7 ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ; Opcode = <STR_LIT> ; SubIndices = Sub0_15 ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( RI . getHWRegIndex ( DestReg ) <= RI . getHWRegIndex ( SrcReg ) ) Forward = true ; else Forward = false ; for ( unsigned Idx = <NUM_LIT> ; Idx < SubIndices . size ( ) ; ++ Idx ) { unsigned


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } else { assert ( SrcOp . isReg ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & SrcCond = MI . getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addReg ( SrcCond . getReg ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( Src0 , <STR_LIT> ) ) . addReg ( RI . getSubReg ( Src1 , <STR_LIT> ) ) . addReg ( SrcCond . getReg ( ) , getKillRegState ( SrcCond . isKill ( ) ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( ST . getRegisterInfo ( ) ) ; MachineFunction & MF = * MBB .


<s> Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> ) { UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI . eraseFromParent


<s> uint64_t RsrcDataFormat = <STR_LIT> ; if ( ST . isAmdHsaOS ( ) ) { RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; } return


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const { unsigned Opc = LdSt . getOpcode ( ) ; if ( isDS ( LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; if ( OffsetImm ) { const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } const MachineOperand * Offset0Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset0 ) ; const MachineOperand * Offset1Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; if ( Offset1 > Offset0 && Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt . mayLoad ( ) ) EltSize = getOpRegClass ( LdSt , <NUM_LIT> ) -> getSize ( ) / <NUM_LIT> ; else { assert ( LdSt . mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = getOpRegClass ( LdSt , Data0Idx ) -> getSize ( ) ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isSMRD (


<s> } assert ( TBB && Cond [ <NUM_LIT> ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; if ( ! FBB ) { BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT>


<s> unsigned OpSize = RI . getRegClass ( OpInfo . RegClass ) -> getSize ( ) ; if ( isLiteralConstant ( MO , OpSize ) ) return RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ; return RI . opCanUseInlineConstant ( OpInfo . OperandType


<s> return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) || MI

. modifiesRegister ( <STR_LIT> , & RI ) ;


<s> return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) || MI . modifiesRegister ( <STR_LIT> ,


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg

( Src . getReg ( ) ) . addReg ( TmpReg ) ;


<s> const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI .


<s> unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR ) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) ; for ( unsigned i = <NUM_LIT> ; i < SubRegs


<s> MachineBasicBlock :: iterator Next = std :: next ( I ) ; I -> eraseFromParent ( ) ; ++ Count ; I = Next ; } return


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( - Cond [ <NUM_LIT> ] . getImm ( ) ) ; return false


<s> SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = <NUM_LIT> ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass (


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC


<s> BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ; return ; } MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg

( Src . getReg ( ) , <NUM_LIT> , <STR_LIT> ) ;


<s> & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg (


<s> const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( ! MO . isImplicit ( ) && ( MO . getReg ( )


<s> if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == <STR_LIT> ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == <STR_LIT> ) return true ; return ( MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || ( ! MO . isImplicit ( ) && ( <STR_LIT> . contains ( MO .

getReg ( ) ) || <STR_LIT> . contains ( MO . getReg ( ) ) ) ) ) ;


<s> const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isVOPC ( MI ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) ++ ConstantBusCount ; unsigned SGPRUsed = findImplicitSGPRRead ( MI ) ; if ( SGPRUsed != <STR_LIT> ) ++ ConstantBusCount ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } else { ++ ConstantBusCount ; } } } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Desc . getOpcode ( ) == <STR_LIT> || Desc . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; const MachineOperand & Src1 = MI . getOperand (


<s> if ( unsigned SubReg = MO . getSubReg ( ) ) { assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg

( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned Reg = NewDesc . ImplicitUses [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; } } if ( NewDesc . ImplicitDefs ) { for ( unsigned i = <NUM_LIT> ; NewDesc . ImplicitDefs [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitDefs [ i


<s> unsigned <ISA_LIT>InstrInfo :: buildExtractSubReg ( MachineBasicBlock :: iterator MI , MachineRegisterInfo & MRI , MachineOperand & SuperReg , const TargetRegisterClass * SuperRC , unsigned SubIdx , const TargetRegisterClass * SubRC ) const { assert ( SuperReg . isReg ( ) ) ; unsigned NewSuperReg = MRI . createVirtualRegister ( SuperRC ) ; unsigned SubReg = MRI . createVirtualRegister ( SubRC ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , NewSuperReg ) . addReg ( SuperReg . getReg ( ) , <NUM_LIT> , SuperReg . getSubReg ( ) ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , SubReg ) . addReg ( NewSuperReg , <NUM_LIT> , SubIdx ) ; return SubReg


<s> return BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addReg ( IndirectBaseReg ) . addReg (


<s> assert ( Src0Idx != - <NUM_LIT> && <STR_LIT> ) ; MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; if ( ! Src0 . isReg ( ) ) return nullptr ; int Src1Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return nullptr ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( isVOP2 ( MI -> getOpcode ( ) ) && ( ! isOperandLegal ( MI , Src0Idx , & Src1 ) || ! isOperandLegal ( MI , Src1Idx , & Src0 ) ) ) { return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ; int Src0ModsVal = Src0Mods -> getImm ( ) ; if ( ! Src1Mods && Src0ModsVal != <NUM_LIT> ) return nullptr ; int Src1ModsVal = Src1Mods -> getImm ( ) ; assert ( ( Src1ModsVal == <NUM_LIT> ) && <STR_LIT> ) ; Src1Mods -> setImm ( Src0ModsVal ) ; Src0Mods -> setImm ( Src1ModsVal ) ; } unsigned Reg = Src0 . getReg ( ) ; unsigned SubReg = Src0 . getSubReg ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Reg , false ) ; Src1 . setSubReg ( SubReg ) ; } else


<s> if ( isVOP2 ( MI -> getOpcode ( ) ) && ( ! isOperandLegal ( MI , Src0Idx , & Src1 ) || ! isOperandLegal ( MI , Src1Idx , & Src0 ) ) ) { return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ; int Src0ModsVal = Src0Mods -> getImm


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT>


<s> switch ( MI -> getOpcode ( ) ) { default : return <ISA_LIT>InstrInfo :: isTriviallyReMaterializable ( MI , AA ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . isImm


<s> MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; int Opcode = - <NUM_LIT> ; if ( RI . isSGPRClass ( RC ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } } else if ( RI . hasVGPRs ( RC ) && ST . isVGPRSpillingEnabled ( MFI ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT>


<s> } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ; MI -> setDesc ( get ( NewOpcode ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( SRsrc ) ; } else { MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( SRsrc , false ) ; } MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( ImmOffset ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const TargetRegisterClass * NewDstRC = RI . getRegClass ( get ( NewOpcode ) . OpInfo [ <NUM_LIT> ] . RegClass ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> )


<s> legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } addDescImplicitUseDef ( NewDesc , Inst ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( RI . hasVGPRs ( NewDstRC ) ) continue ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) continue ; break ; default : break ; } unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; legalizeOperands ( Inst ) ; for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( NewDstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr & UseMI = * I -> getParent (


<s> MachineInstr * Lo = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , LoDst ) . addImm ( Op . getImm ( ) & <NUM_LIT> ) ; MachineInstr * Hi = BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , HiDst ) . addImm ( Op . getImm ( ) >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: REG_SEQUENCE ) , Dst ) . addReg ( LoDst ) . addImm ( <STR_LIT> ) . addReg ( HiDst ) . addImm ( <STR_LIT> ) ; Worklist . push_back ( Lo ) ; Worklist . push_back ( Hi


<s> unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineInstr * First = BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . addOperand ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; MachineInstr * Second = BuildMI ( MBB , MII , DL , InstDesc , ResultReg

) . addOperand ( SrcRegSub1 ) . addReg ( MidReg ) ;


<s> & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * DestSubRC = RI . getSubRegClass ( DestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( DestRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . push_back


<s> MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . push_back ( LoHalf ) ; Worklist . push_back (


<s> const MachineOperand * SBase = getNamedOperand ( * MI , <STR_LIT> :: sbase ) ; bool IsKill = SBase -> isKill ( ) ; if ( OffOp ) { bool isVI = MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ; unsigned OffScale = isVI ? <NUM_LIT> : <NUM_LIT> ; unsigned LoOffset = OffOp -> getImm ( ) * OffScale ; unsigned HiOffset = LoOffset + HalfSize ; Lo = BuildMI ( * MBB , MI , DL , get ( HalfImmOp ) , RegLo ) . addReg ( SBase -> getReg ( ) , <NUM_LIT> , SBase -> getSubReg ( ) ) . addImm ( LoOffset / OffScale ) ; if ( ! isUInt < <NUM_LIT> > ( HiOffset ) || ( ! isVI && ! isUInt < <NUM_LIT> > ( HiOffset / OffScale ) ) ) { unsigned OffsetSGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , get ( <STR_LIT> ) , OffsetSGPR ) . addImm ( HiOffset ) ; Hi = BuildMI ( * MBB , MI , DL , get ( HalfSGPROp ) , RegHi ) . addReg ( SBase -> getReg ( ) , getKillRegState ( IsKill ) , SBase -> getSubReg ( ) ) . addReg ( OffsetSGPR ) ; } else { Hi = BuildMI ( * MBB , MI , DL , get ( HalfImmOp ) , RegHi ) . addReg ( SBase -> getReg ( ) , getKillRegState ( IsKill ) ,

SBase -> getSubReg ( ) ) . addImm ( HiOffset / OffScale ) ;


<s> switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } } if ( Opcode != - <NUM_LIT> ) { FrameInfo -> setObjectAlignment ( FrameIndex , <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg ) . addFrameIndex ( FrameIndex ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) ; } else


<s> for ( int i = <NUM_LIT> , e = Desc . getNumOperands ( ) ; i != e ; ++ i ) { if ( MI -> getOperand ( i ) . isFPImm ( ) ) { ErrInfo = <STR_LIT> <STR_LIT> ; return false ; } int RegClass = Desc . OpInfo [ i ] . RegClass ; switch ( Desc . OpInfo [ i ] . OperandType ) { case MCOI :: OPERAND_REGISTER : if ( MI -> getOperand ( i ) . isImm ( ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case <STR_LIT> : break ; case <STR_LIT> : if ( isLiteralConstant ( MI -> getOperand ( i ) , RI . getRegClass ( RegClass ) -> getSize ( ) ) ) { ErrInfo = <STR_LIT> ; return false ; } break ; case MCOI :: OPERAND_IMMEDIATE : if ( ! MI -> getOperand ( i ) . isImm ( ) && ! MI -> getOperand ( i ) . isFI ( ) ) { ErrInfo = <STR_LIT> ; return false ; } default : continue ; } if ( ! MI -> getOperand ( i ) . isReg ( ) ) continue ; if ( RegClass != - <NUM_LIT> ) { unsigned Reg = MI -> getOperand ( i ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; const TargetRegisterClass * RC = RI . getRegClass ( RegClass ) ; if ( ! RC -> contains ( Reg ) ) { ErrInfo = <STR_LIT> ; return false ; } } } if ( isVOP1 ( Opcode ) || isVOP2 ( Opcode ) || isVOP3 ( Opcode ) || isVOPC ( Opcode ) ) { const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; unsigned ConstantBusCount = <NUM_LIT> ; unsigned SGPRUsed = <STR_LIT> ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI -> getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO , getOpSize ( Opcode , OpIdx ) ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg (


<s> MachineInstr & UseMI = * I -> getParent ( ) ; if ( ! canReadVGPR ( UseMI , I . getOperandNo ( ) ) ) { Worklist . push_back ( & UseMI ) ; do { ++


<s> if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( AA && MIa . hasOneMemOperand ( ) && MIb . hasOneMemOperand ( ) ) { const MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; const MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; if ( MMOa -> getValue ( ) && MMOb -> getValue ( ) ) { MemoryLocation LocA ( MMOa -> getValue ( ) , MMOa -> getSize ( ) , MMOa -> getAAInfo ( ) ) ; MemoryLocation LocB ( MMOb -> getValue ( ) , MMOb -> getSize ( ) , MMOb -> getAAInfo ( ) ) ; if ( ! AA -> alias ( LocA , LocB ) ) return true ; } } if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap (


<s> assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( AA && MIa . hasOneMemOperand ( ) && MIb . hasOneMemOperand ( ) ) { const MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; const MachineMemOperand * MMOb = * MIb . memoperands_begin (


<s> MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned WorkGroupSize = MFI -> getMaxFlatWorkGroupSize ( ) ; unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT>


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( RC == & <STR_LIT> ) { if ( DestReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RC ) ) { if ( RC -> getSize ( ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ; EltSize = <NUM_LIT>


<s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MCInstrDesc & MovRelDesc = get ( <STR_LIT> ) ; unsigned VecReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsUndef = MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ; unsigned SubReg = <STR_LIT> + MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( VecReg == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * MovRel = BuildMI ( MBB , MI , DL , MovRelDesc ) . addReg ( RI . getSubReg ( VecReg , SubReg ) , RegState :: Undef ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( VecReg , RegState :: ImplicitDefine ) . addReg ( VecReg , RegState :: Implicit | ( IsUndef ? RegState :: Undef : <NUM_LIT> ) ) ; const int ImpDefIdx = MovRelDesc . getNumOperands ( ) + MovRelDesc . getNumImplicitUses ( ) ; const int ImpUseIdx = ImpDefIdx + <NUM_LIT> ; MovRel -> tieOperands ( ImpDefIdx , ImpUseIdx ) ; MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RegLo = RI . getSubReg ( Reg , <STR_LIT> ) ; unsigned RegHi = RI . getSubReg ( Reg , <STR_LIT> ) ; MIBundleBuilder Bundler ( MBB , MI ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , Reg ) ) ; Bundler . append ( BuildMI ( MF , DL , get ( <STR_LIT> ) , RegLo ) . addReg ( RegLo ) . add ( MI . getOperand ( <NUM_LIT> ) ) ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) , RegHi ) . addReg ( RegHi ) ; if ( MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <ISA_LIT>InstrInfo :: MO_NONE ) MIB . addImm ( <NUM_LIT> ) ; else MIB . add ( MI . getOperand ( <NUM_LIT> )


<s> const MachineOperand * ImmOp = getNamedOperand ( DefMI , <STR_LIT> :: src0 ) ; assert ( ImmOp ) ; if ( ! ImmOp -> isImm ( ) ) { return false ; } UseMI . setDesc ( get ( NewOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( ImmOp -> getImm ( ) ) ; UseMI . addImplicitDefUseOperands ( * UseMI . getParent ( ) -> getParent ( ) ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; const MachineOperand & ImmOp = DefMI . getOperand ( <NUM_LIT> ) ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; unsigned Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands (


<s> return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( UnusedCarry

, RegState :: Define | RegState :: Dead ) ;


<s> if ( isVALU ( MI ) || isSALU ( MI ) ) { if ( isFixedSize ( MI ) ) return DescSize ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return <NUM_LIT> ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return <NUM_LIT> ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( DescSize == <NUM_LIT> ) return <NUM_LIT> ; switch ( Opc


<s> default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT>


<s> preserveCondRegFlags ( CondBr -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ; CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef (


<s> preserveCondRegFlags ( CondBr -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ; CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; CondReg . setIsKill ( Cond [ <NUM_LIT> ] . isKill ( ) ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT>


<s> unsigned SelOp = Pred == SCC_TRUE ? <STR_LIT> : <STR_LIT> ; MachineInstr * Select = BuildMI ( MBB , I , DL , get ( SelOp ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } if ( DstSize == <NUM_LIT> && Pred == SCC_TRUE ) { MachineInstr * Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; assert ( NElts % <NUM_LIT> == <NUM_LIT> ) ; NElts /= <NUM_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) ; I = MIB -> getIterator ( ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( int Idx = <NUM_LIT> ; Idx != NElts ; ++ Idx ) { unsigned DstElt = MRI . createVirtualRegister ( EltRC


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT>


<s> static void reportIllegalCopy ( const <ISA_LIT>InstrInfo * TII , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) { MachineFunction * MF = MBB .


<s> const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt


<s> & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . add ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . add ( SrcRegSub1 ) . addReg ( MidReg ) ; MRI . replaceRegWith ( Dest .


<s> const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( )


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const MCInstrDesc & InstDesc = get ( Opcode ) ; const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg


<s> } else { assert ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; ImmOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) ImmOffset <<= <NUM_LIT> ; RegOffset = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( ImmOffset ) ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ; MI -> setDesc ( get ( NewOpcode ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( SRsrc ) ; } else { MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( SRsrc , false ) ; } MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( ImmOffset ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm


<s> return getNamedOperand ( const_cast < MachineInstr & > (


<s> return getNamedOperand ( const_cast < MachineInstr & > ( MI


<s> const MIRFormatter * getMIRFormatter ( ) const override { if ( ! Formatter . get ( ) ) Formatter = std :: make_unique


<s> if ( ! Formatter . get ( ) ) Formatter = std :: make_unique < <ISA_LIT>MIRFormatter > ( ) ; return Formatter . get ( )


<s> unsigned getOpSize ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg (


<s> inline TargetInstrInfo :: RegSubRegPair getRegSubRegPair ( const MachineOperand & O ) { assert ( O . isReg ( ) ) ; return TargetInstrInfo :: RegSubRegPair ( O . getReg ( ) , O . getSubReg


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isInlineAsm


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isInlineAsm (


<s> return llvm :: any_of ( MI . explicit_uses ( ) , [ & MRI , this ] ( const MachineOperand & MO ) { return MO . isReg ( ) && RI . isVGPR ( MRI , MO . getReg


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return llvm :: any_of ( MI . explicit_uses ( ) , [ & MRI , this ] (


<s> bool isAtomic ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags &


<s> bool isDOT ( uint16_t Opcode ) const { return get ( Opcode ) .


<s> bool isFPAtomic ( uint16_t Opcode ) const { return get ( Opcode )


<s> bool isInlineConstant ( const APFloat & Imm ) const { return isInlineConstant ( Imm .


<s> if ( ! P . SubReg ) return RC == & TRC ; auto * TRI = MRI . getTargetRegisterInfo


<s> assert ( MI . isCopy ( ) ) ; Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF


<s> bool usesFPDPRounding ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags


<s> void <ISA_LIT>InstrInfo :: addSCCDefUsersToVALUWorklist ( MachineOperand & Op , MachineInstr & SCCDefInst , SetVectorType & Worklist ) const { assert ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) && ! Op . isDead ( ) && Op . getParent ( ) == & SCCDefInst ) ; for ( MachineInstr & MI : make_range ( std :: next ( MachineBasicBlock :: iterator ( SCCDefInst ) ) , SCCDefInst . getParent ( ) -> end


<s> assert ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) && ! Op . isDead ( ) && Op . getParent ( ) == & SCCDefInst ) ; for ( MachineInstr & MI : make_range ( std :: next ( MachineBasicBlock :: iterator ( SCCDefInst ) ) , SCCDefInst . getParent ( ) -> end ( ) ) ) { if ( MI . findRegisterUseOperandIdx ( <STR_LIT> , false , & RI ) != - <NUM_LIT> )


<s> case <STR_LIT> : break ; default : OpNo = I . getOperandNo ( ) ; break ; } if ( ! RI . hasVGPRs ( getOpRegClass ( UseMI , OpNo ) ) ) { Worklist . insert ( & UseMI ) ; do { ++ I ; } while ( I != E && I -> getParent ( ) == & UseMI ) ; } else { ++


<s> if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIa ) && ! isMTBUF ( MIa ) ; } if ( isFLAT ( MIa )


<s> assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIa ) && ! isMTBUF ( MIa ) ; } if ( isFLAT ( MIa


<s> } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; } BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm


<s> unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; const DebugLoc & DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) . addImm ( <NUM_LIT> ) ; }


<s> bool <ISA_LIT>InstrInfo :: canShrink ( const MachineInstr & MI , const MachineRegisterInfo & MRI ) const { const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) ) return false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Src2 -> isReg ( ) || ! RI . isVGPR ( MRI , Src2 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src2_modifiers ) ) return false ; break ; case <STR_LIT> : break ; } } const MachineOperand * Src1 = getNamedOperand ( MI


<s> if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; } if ( auto Imm = getFoldableImm ( Src0 ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> && isOperandLegal ( MI , <STR_LIT> ( NewOpc , <STR_LIT> :: src0 ) , Src1 ) ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src1 ) . addImm ( Imm ) . add ( * Src2 ) ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return nullptr ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . addImm ( Src0Mods ? Src0Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src0 ) . addImm ( Src1Mods ? Src1Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src1 ) . addImm ( <NUM_LIT>

) . add ( * Src2 ) . addImm ( Clamp ? Clamp -> getImm ( ) : <NUM_LIT> ) . addImm ( Omod ? Omod -> getImm ( ) : <NUM_LIT> ) ;


<s> const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB -> getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { if ( auto Imm = getFoldableImm ( Src2 ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( auto Imm = getFoldableImm ( Src1 ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; } if ( auto Imm = getFoldableImm ( Src0 )


<s> } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , * ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsFMA = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; unsigned NewOpc = IsFMA ? ( IsF32 ? <STR_LIT> : <STR_LIT> ) : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == - <NUM_LIT> ) return false ; const int64_t Imm = ImmOp -> getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; unsigned Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( NewOpc ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse


<s> if ( ST . isAmdHsaOS ( ) ) { if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; } return


<s> uint64_t <ISA_LIT>InstrInfo :: getDefaultRsrcDataFormat ( ) const { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { return ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } uint64_t RsrcDataFormat = <STR_LIT> ; if ( ST . isAmdHsaOS (


<s> uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ; Rsrc23 |= EltSizeValue << <STR_LIT> ; } uint64_t IndexStride = ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: GFX9 ? <NUM_LIT> : <NUM_LIT> ; Rsrc23 |= IndexStride << <STR_LIT> ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS && ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: GFX9 ) Rsrc23 &= ~ <STR_LIT> ; return


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) )


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( MI . mayStore ( ) && isSMRD ( MI ) ) return true ; if ( MI . isReturn ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return false


<s> if ( BrOffset >= <NUM_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_FORWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addMBB ( & DestBB , MO_LONG_BRANCH_BACKWARD ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( PCReg ) ; RS -> enterBasicBlockEnd ( MBB ) ; unsigned Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false , <NUM_LIT> ) ; MRI . replaceRegWith ( PCReg , Scav ) ; MRI . clearVirtRegs ( ) ; RS -> setRegUsed ( Scav ) ; return <NUM_LIT> + <NUM_LIT> + <NUM_LIT> +


<s> static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { if ( NElts % <NUM_LIT> ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; } else { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; NElts /= <NUM_LIT> ; } } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) ; I = MIB -> getIterator ( ) ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( int Idx = <NUM_LIT> ; Idx != NElts ; ++ Idx ) { unsigned DstElt = MRI . createVirtualRegister


<s> if ( MO . isImm ( ) && isInlineConstant ( MO , OpInfo ) ) return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ; if ( ! RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ) return false ; if ( ! isVOP3 ( MI ) || ! <STR_LIT> ( InstDesc , OpNo ) ) return true ; const MachineFunction * MF = MI . getParent ( ) -> getParent


<s> const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & <STR_LIT> , VRC )


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } return true ; } if ( <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ; return


<s> const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) .

add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ;


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineBasicBlock :: iterator MII = Inst ; const TargetRegisterClass * Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg ,

RegState :: Kill ) . addImm ( <NUM_LIT> ) ;


<s> if ( MO . isImm ( ) ) return ! isInlineConstant ( MO , OpInfo ) ; if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; if ( MO . isImplicit ( ) ) { return MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ; } else { return <STR_LIT> . contains ( MO . getReg ( ) ) || <STR_LIT>


<s> void <ISA_LIT>InstrInfo :: addUsersToMoveToVALUWorklist ( Register DstReg , MachineRegisterInfo & MRI , SetVectorType & Worklist ) const { for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( DstReg ) , E = MRI . use_end ( ) ; I != E ; ) { MachineInstr & UseMI = * I -> getParent ( ) ; unsigned OpNo


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : llvm_unreachable ( <STR_LIT> ) ; } ++ I ; } if ( I == E ) return false ; if ( I -> getOpcode ( ) != <STR_LIT> ) return analyzeBranchImpl ( MBB , I , TBB , FBB , Cond , AllowModify ) ; ++ I ; if ( I == MBB . end ( ) )


<s> if ( Op32DstIdx != - <NUM_LIT> ) { Inst32 . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { assert ( ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( * Src2 ) ; } else { fixImplicitOperands ( *


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned WorkGroupSize = MFI -> getMaxFlatWorkGroupSize ( ) ; unsigned WavefrontSize = ST . getWavefrontSize ( ) ; Register TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; const DebugLoc & DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { Register TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) )


<s> Register VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; unsigned RegSize = TRI -> getRegSizeInBits ( Rsrc . getReg ( ) , MRI ) ; unsigned NumSubRegs = RegSize / <NUM_LIT> ; assert ( NumSubRegs % <NUM_LIT> == <NUM_LIT> && NumSubRegs <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumSubRegs ; Idx += <NUM_LIT> ) { Register CurRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegLo ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx ) ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegHi ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx + <NUM_LIT> ) ) ; ReadlanePieces . push_back ( CurRegLo ) ; ReadlanePieces . push_back ( CurRegHi ) ; Register CurReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg

( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ;


<s> BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg ( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ; Register NewCondReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , NewCondReg ) . addReg ( CurReg ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx , <NUM_LIT> ) ) ; if ( CondReg == <STR_LIT> ) CondReg = NewCondReg ; else { Register AndReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( AndOpc ) , AndReg ) . addReg ( CondReg ) . addReg ( NewCondReg ) ; CondReg = AndReg ; } } auto SRsrcRC = TRI -> getEquivalentSGPRClass ( MRI . getRegClass ( VRsrc ) ) ; Register SRsrc = MRI . createVirtualRegister ( SRsrcRC ) ; auto Merge = BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) ; unsigned Channel = <NUM_LIT> ; for ( Register Piece : ReadlanePieces ) { Merge . addReg ( Piece ) . addImm ( TRI -> getSubRegFromChannel ( Channel ++ ) ) ; } Rsrc . setReg ( SRsrc ) ; Rsrc . setIsKill ( true ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; MRI . setSimpleHint ( SaveExec , CondReg ) ; BuildMI ( LoopBB , I , DL , TII . get ( SaveExecOpc ) , SaveExec ) . addReg ( CondReg , RegState :: Kill ) ; I = LoopBB . end ( ) ; BuildMI ( LoopBB , I , DL , TII . get ( XorTermOpc ) , Exec ) . addReg


<s> bool llvm :: execMayBeModifiedBeforeAnyUse ( const MachineRegisterInfo & MRI , Register VReg , const MachineInstr & DefMI ) { assert ( MRI . isSSA ( ) && <STR_LIT> ) ; auto * TRI = MRI . getTargetRegisterInfo ( ) ; auto * DefBB = DefMI . getParent ( ) ; const int MaxUseInstScan = <NUM_LIT> ; int NumUseInst = <NUM_LIT> ; for ( auto & UseInst : MRI . use_nodbg_instructions ( VReg ) ) { if ( UseInst . getParent ( )


<s> for ( auto & UseInst : MRI . use_nodbg_instructions ( VReg ) ) { if ( UseInst . getParent ( ) != DefBB ) return true ; if ( ++ NumUseInst > MaxUseInstScan ) return true ; } const int MaxInstScan = <NUM_LIT> ; int NumInst = <NUM_LIT> ; for ( auto I = std :: next ( DefMI . getIterator


<s> if ( Opc == <STR_LIT> ) { Register DstReg = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Is16Bit = getOpSize ( UseMI , <NUM_LIT> ) == <NUM_LIT> ; bool isVGPRCopy = RI . isVGPR ( * MRI , DstReg ) ; unsigned NewOpc = isVGPRCopy ? <STR_LIT> : <STR_LIT> ; APInt Imm ( <NUM_LIT> , ImmOp -> getImm ( ) ) ; if ( UseMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) Imm = Imm . ashr ( <NUM_LIT> ) ; if ( RI . isAGPR ( * MRI , DstReg ) ) { if ( ! isInlineConstant ( Imm ) ) return false ; NewOpc = <STR_LIT> ; } if ( Is16Bit ) { if ( isVGPRCopy ) return false ; if ( DstReg . isVirtual ( ) && UseMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != <STR_LIT> ) return false ; UseMI . getOperand ( <NUM_LIT> ) . setSubReg ( <NUM_LIT> ) ; if ( DstReg . isPhysical ( ) ) { DstReg = RI . get32BitRegister ( DstReg ) ; UseMI . getOperand ( <NUM_LIT> ) . setReg ( DstReg ) ; } assert ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) ; } UseMI . setDesc ( get ( NewOpc ) ) ; UseMI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm . getSExtValue ( ) ) ; UseMI . addImplicitDefUseOperands ( * UseMI . getParent ( ) -> getParent ( ) ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( hasAnyModifiersSet ( UseMI ) ) return false ; MachineOperand * Src0 = getNamedOperand ( UseMI , <STR_LIT> :: src0 ) ; if ( isInlineConstant ( UseMI , * Src0 , * ImmOp ) ) return false ; bool IsF32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsFMA = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MachineOperand * Src1 = getNamedOperand ( UseMI , <STR_LIT> :: src1 ) ; MachineOperand * Src2 = getNamedOperand ( UseMI , <STR_LIT> :: src2 ) ; if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Reg ) { if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; if ( ! Src2 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src2 -> getReg ( ) ) ) ) return false ; unsigned NewOpc = IsFMA ? ( IsF32 ? <STR_LIT> : <STR_LIT> ) : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) == -


<s> switch ( Size ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> return get ( getIndirectSGPRWritePseudo32 ( VecSize ) ) ; case <NUM_LIT> : return get ( getIndirectSGPRWritePseudo64 ( VecSize ) ) ; default : llvm_unreachable (


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT>


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> )


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return


<s> if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx == - <NUM_LIT> ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return isVOP3 ( MI ) ? <NUM_LIT> : ( DescSize + <NUM_LIT> ) ; return DescSize ; } if ( isMIMG ( MI ) ) { int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ; return RI . getPhysRegClass ( Reg