<s> void LinearizedRegion :: initLiveOut ( RegionMRT * Region , const MachineRegisterInfo * MRI , const TargetRegisterInfo * TRI , PHILinearize & PHIInfo ) { storeLiveOuts ( Region , MRI , TRI ,


<s> return ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MergeBB ) << <STR_LIT> << printReg ( DestRegister , TRI ) << <STR_LIT> << printReg ( IfSourceRegister , TRI ) << <STR_LIT> << printMBBReference ( * IfBB ) << printReg ( CodeSourceRegister , TRI ) << <STR_LIT> << printMBBReference ( * CodeBB ) << <STR_LIT> ) ; const DebugLoc & DL = MergeBB -> findDebugLoc ( MergeBB -> begin ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * MergeBB , MergeBB -> instr_begin ( ) , DL , TII -> get ( TargetOpcode :: PHI ) , DestRegister ) ; if ( IsUndefIfSource && false ) { MIB . addReg ( IfSourceRegister , RegState :: Undef ) ; } else { MIB . addReg ( IfSourceRegister ) ; } MIB . addMBB (


<s> if ( MergeBB -> succ_begin ( ) == MergeBB -> succ_end ( ) ) { return ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MergeBB ) << <STR_LIT> << printReg ( DestRegister , TRI ) << <STR_LIT> << printReg ( IfSourceRegister , TRI ) << <STR_LIT> << printMBBReference ( * IfBB ) << printReg ( CodeSourceRegister , TRI ) << <STR_LIT> << printMBBReference ( * CodeBB ) << <STR_LIT> ) ; const DebugLoc & DL = MergeBB -> findDebugLoc ( MergeBB -> begin ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * MergeBB , MergeBB -> instr_begin ( ) , DL , TII -> get ( TargetOpcode :: PHI ) , DestRegister ) ; if ( IsUndefIfSource && false ) { MIB . addReg ( IfSourceRegister , RegState :: Undef ) ; } else { MIB . addReg ( IfSourceRegister ) ; } MIB . addMBB ( IfBB )


<s> return ( ( & ( * ( MBB -> getParent ( ) -> begin ( ) ) )


<s> return findDest ( Reg , SourceMBB , DestReg


<s> LinearizedRegion :: LinearizedRegion ( ) { setEntry ( nullptr


<s> setParent ( nullptr ) ; setBBSelectRegOut ( <NUM_LIT> )


<s> for ( auto <ISA_LIT> : phiInfoElementGetSources ( Info ) ) { assert ( ( <ISA_LIT> . second != SourceMBB || SourceReg == <ISA_LIT> . first ) ) ; } phiInfoElementGetSources ( Info ) . insert ( PHISourceT ( SourceReg ,


<s> unsigned PHILinearize :: phiInfoElementGetDest ( PHIInfoElementT *


<s> PHILinearize :: PHISourcesT & PHILinearize ::

phiInfoElementGetSources ( PHIInfoElementT * Info ) {


<s> SmallVector < PHISourceT , <NUM_LIT> > ElimiatedSources ; for ( auto <ISA_LIT> : Sources ) { if ( <ISA_LIT> . first == SourceReg && ( <ISA_LIT> . second == nullptr || <ISA_LIT> .


<s> SmallVector < PHISourceT , <NUM_LIT> > ElimiatedSources ; for ( auto <ISA_LIT> : Sources ) { if ( <ISA_LIT> . first == SourceReg && ( <ISA_LIT> . second == nullptr || <ISA_LIT> . second == SourceMBB ) ) { ElimiatedSources . push_back ( PHISourceT ( <ISA_LIT> . first , <ISA_LIT> . second ) ) ; } } for ( auto & Source : ElimiatedSources ) { Sources . erase (


<s> void PHILinearize :: phiInfoElementSetDef ( PHIInfoElementT * Info , unsigned NewDef ) { Info -> DestReg


<s> if ( IsFirst ) { IsFirst = false ; } else { OS << <STR_LIT> ; } OS << MBB -> getNumber ( ) ; } OS << <STR_LIT> << Entry -> getNumber ( ) << <STR_LIT> << ( Exit == nullptr ? - <NUM_LIT> : Exit -> getNumber ( ) ) << <STR_LIT> << printReg ( getBBSelectRegIn ( ) , TRI ) << <STR_LIT> << printReg ( getBBSelectRegOut ( ) , TRI ) << <STR_LIT> ; for ( auto & LI : LiveOuts ) { OS << printReg ( LI , TRI ) << <STR_LIT> ; } OS <<


<s> auto Children = Region -> getChildren ( ) ; for ( auto CI : * Children ) { if ( ! CI -> isRegion ( ) ) { if ( CI -> getMBBMRT ( ) -> getMBB ( ) -> succ_size ( ) > <NUM_LIT> ) { return false


<s> if ( Entry -> succ_size ( ) != <NUM_LIT> ) { return false ; } for ( MachineBasicBlock :: const_succ_iterator <ISA_LIT> = Entry -> succ_begin ( ) , E = Entry -> succ_end ( ) ; <ISA_LIT> != E ; ++ <ISA_LIT> ) { MachineBasicBlock * Current = * <ISA_LIT> ; if ( Current == Succ )


<s> setParent ( nullptr ) ; setBBSelectRegOut ( <NUM_LIT>


<s> for ( MachineBasicBlock :: succ_iterator PI = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; PI != E ; ++ PI ) { if ( ( * PI ) !=


<s> const TargetRegisterInfo * TRI = MRI -> getTargetRegisterInfo ( ) ; for ( auto MBBI : MBBs ) { MachineBasicBlock * MBB = MBBI ; for ( auto & II : * MBB ) { for ( auto & RI : II . uses ( ) ) { if ( RI . isReg ( ) ) { unsigned Reg = RI . getReg ( ) ; if ( TRI -> isVirtualRegister ( Reg ) ) { if ( hasNoDef ( Reg , MRI ) ) continue ; if ( ! MRI -> hasOneDef ( Reg


<s> MachineBasicBlock * Exit = Region -> getSucc ( ) ; if ( Exit == nullptr ) { return ; } for ( MachineBasicBlock :: pred_iterator PI = Exit -> pred_begin ( ) , E = Exit -> pred_end ( ) ; PI != E ; ++


<s> void PHILinearize :: removeSource ( unsigned DestReg , unsigned SourceReg , MachineBasicBlock *


<s> void PHILinearize :: removeSource ( unsigned DestReg , unsigned SourceReg , MachineBasicBlock * SourceMBB ) { phiInfoElementRemoveSource ( findPHIInfoElement ( DestReg ) , SourceReg , SourceMBB


<s> phiInfoElementSetDef ( findPHIInfoElement ( OldDestReg )


<s> LLVM_DEBUG ( dbgs ( ) << printReg ( CombinedSourceReg , TRI ) << <STR_LIT> << printMBBReference ( * IfMBB ) ) ; unsigned NumInputs = getPHINumInputs ( PHI ) ; for ( unsigned i = <NUM_LIT> ; i < NumInputs ; ++ i ) { if ( isPHIRegionIndex ( PHIRegionIndices , i ) ) { continue ; } unsigned SourceReg = getPHISourceReg ( PHI , i ) ; MachineBasicBlock * SourcePred = getPHIPred ( PHI , i ) ; MIB . addReg ( SourceReg ) ; MIB . addMBB ( SourcePred ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( SourceReg , TRI ) << <STR_LIT> << printMBBReference ( * SourcePred ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PHI . eraseFromParent


<s> replaceRegisterWith ( DestReg , CombinedSourceReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( CombinedSourceReg , TRI ) << <STR_LIT> ) ; PHI . eraseFromParent ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << printReg ( getPHIDestReg ( PHI ) , TRI ) << <STR_LIT> ) ; MachineBasicBlock * MBB = PHI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , PHI , PHI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: PHI ) , getPHIDestReg ( PHI ) ) ; MIB . addReg ( CombinedSourceReg ) ; MIB . addMBB ( IfMBB ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( CombinedSourceReg , TRI ) << <STR_LIT> << printMBBReference ( * IfMBB ) ) ; unsigned NumInputs = getPHINumInputs ( PHI ) ; for ( unsigned i = <NUM_LIT> ;


<s> void LinearizedRegion :: replaceLiveOut ( unsigned OldReg , unsigned NewReg ) { if ( isLiveOut ( OldReg ) ) { removeLiveOut ( OldReg


<s> void LinearizedRegion :: replaceLiveOut ( unsigned OldReg , unsigned NewReg ) { if ( isLiveOut ( OldReg ) ) { removeLiveOut ( OldReg ) ; addLiveOut (


<s> IsDead = false ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> << ( IsDead ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ) ; if ( IsDead ) { LRegion -> removeLiveOut ( Reg ) ; } WasLiveOut = true ; } } if ( WasLiveOut ) LRegion -> addLiveOut (


<s> void LinearizedRegion :: replaceRegister ( unsigned Register , unsigned NewRegister , MachineRegisterInfo * MRI , bool ReplaceInside , bool ReplaceOutside , bool IncludeLoopPHI ) { assert ( Register != NewRegister && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Register , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> << printReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; if ( ReplaceOutside && ( isLiveOut ( Register ) || this -> getParent ( ) -> isLiveOut ( Register ) ) ) { LinearizedRegion * Current = this ; while ( Current != nullptr && Current -> getEntry ( ) != nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current -> replaceLiveOut ( Register , NewRegister ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current = Current -> getParent ( ) ; } } for ( MachineRegisterInfo :: reg_iterator I = MRI -> reg_begin ( Register ) , E = MRI -> reg_end ( ) ; I != E ; ) { MachineOperand & O = * I ; ++ I ; if ( O . isDef ( ) ) continue ; bool IsInside = contains ( O . getParent ( ) -> getParent ( ) ) ; bool IsLoopPHI = IsInside && ( O . getParent ( ) -> isPHI ( ) && O . getParent ( ) -> getParent ( ) == getEntry ( ) ) ; bool ShouldReplace = ( IsInside && ReplaceInside ) || ( ! IsInside && ReplaceOutside ) || ( IncludeLoopPHI && IsLoopPHI ) ; if ( ShouldReplace ) { if ( TargetRegisterInfo :: isPhysicalRegister ( NewRegister ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Register , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT>


<s> if ( ReplaceOutside && ( isLiveOut ( Register ) || this -> getParent ( ) -> isLiveOut ( Register ) ) ) { LinearizedRegion * Current = this ; while ( Current != nullptr && Current -> getEntry ( ) != nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current -> replaceLiveOut ( Register , NewRegister ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current = Current -> getParent ( ) ; } } for ( MachineRegisterInfo :: reg_iterator I = MRI -> reg_begin ( Register ) , E = MRI -> reg_end ( ) ; I != E ; ) { MachineOperand & O = * I ; ++ I ; if ( O . isDef ( ) ) continue ; bool IsInside = contains ( O . getParent ( ) -> getParent ( ) ) ; bool IsLoopPHI = IsInside && ( O . getParent ( ) -> isPHI ( ) && O . getParent ( ) -> getParent ( ) == getEntry ( ) ) ; bool ShouldReplace = ( IsInside && ReplaceInside ) || ( ! IsInside && ReplaceOutside ) || ( IncludeLoopPHI && IsLoopPHI ) ; if ( ShouldReplace ) { if ( TargetRegisterInfo :: isPhysicalRegister ( NewRegister ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; llvm_unreachable (


<s> void LinearizedRegion :: replaceRegisterInsideRegion ( unsigned Register , unsigned NewRegister , bool

IncludeLoopPHIs , MachineRegisterInfo * MRI ) {


<s> void LinearizedRegion :: replaceRegisterInsideRegion ( unsigned Register , unsigned NewRegister , bool IncludeLoopPHIs , MachineRegisterInfo * MRI ) { replaceRegister ( Register , NewRegister , MRI , true , false ,


<s> void LinearizedRegion :: replaceRegisterOutsideRegion ( unsigned Register , unsigned NewRegister , bool IncludeLoopPHIs , MachineRegisterInfo


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; unsigned Reg = LI ; if ( Reg != InnerRegion -> getBBSelectRegOut ( ) ) { const TargetRegisterClass * RegClass = MRI -> getRegClass ( Reg ) ; unsigned PHIDestReg = MRI -> createVirtualRegister ( RegClass ) ; unsigned IfSourceReg = MRI -> createVirtualRegister ( RegClass ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg ) << <STR_LIT> ) ; TII -> materializeImmediate ( * IfBB , IfBB -> getFirstTerminator ( ) , DebugLoc ( ) , IfSourceReg , <NUM_LIT> ) ; InnerRegion -> replaceRegisterOutsideRegion ( Reg , PHIDestReg , true , MRI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; insertMergePHI ( IfBB , InnerRegion -> getExit ( ) , MergeBB , PHIDestReg , IfSourceReg , Reg , true ) ; } } SmallVector < unsigned , <NUM_LIT> > Sources ; if ( PHIInfo . findSourcesFromMBB ( CodeBB , Sources ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * CodeBB ) << <STR_LIT> ) ; for ( auto <ISA_LIT> : Sources ) { unsigned DestReg ; PHIInfo . findDest ( <ISA_LIT> , CodeBB , DestReg ) ; insertChainedPHI ( IfBB , CodeBB , MergeBB , InnerRegion , DestReg , <ISA_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( PHIInfo . dump


<s> void <ISA_LIT>MachineCFGStructurizer :: rewriteRegionEntryPHI ( LinearizedRegion * Region , MachineBasicBlock * IfMBB , MachineInstr & PHI ) { SmallVector < unsigned , <NUM_LIT>


<s> unsigned LinearizedSourceReg = storePHILinearizationInfo ( PHI , & PHINonRegionIndices ) ; replaceEntryPHI ( PHI , LinearizedSourceReg , IfMBB


<s> void <ISA_LIT>MachineCFGStructurizer :: rewriteRegionEntryPHIs ( LinearizedRegion * Region , MachineBasicBlock * IfMBB ) { SmallVector < MachineInstr * ,


<s> void <ISA_LIT>MachineCFGStructurizer :: rewriteRegionExitPHIs ( RegionMRT * Region , MachineBasicBlock * LastMerge , LinearizedRegion * LRegion ) { SmallVector < MachineInstr * ,


<s> bool <ISA_LIT>MachineCFGStructurizer :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MRI = & ( MF . getRegInfo ( ) ) ; initFallthroughMap ( MF ) ; checkRegOnlyPHIInputs ( MF ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MF . dump ( ) ) ; Regions = & ( getAnalysis < MachineRegionInfoPass > ( ) . getRegionInfo ( ) ) ; LLVM_DEBUG ( Regions -> dump ( ) ) ; RegionMRT * RTree = MRT :: buildMRT ( MF , Regions , TII , MRI ) ; setRegionMRT ( RTree ) ; initializeSelectRegisters ( RTree , <NUM_LIT> , MRI , TII ) ; LLVM_DEBUG ( RTree -> dump ( TRI ) ) ; bool result = structurizeRegions (


<s> void LinearizedRegion :: setExit ( MachineBasicBlock *


<s> void LinearizedRegion :: setHasLoop ( bool Value ) { HasLoop =


<s> void setLinearizedRegion ( LinearizedRegion *


<s> PHI . getOperand ( Index * <NUM_LIT> +


<s> void setRegionMRT ( RegionMRT * RegionTree


<s> PHILinearize :: source_iterator PHILinearize :: sources_begin ( unsigned


<s> auto InfoElement = findPHIInfoElement ( Reg ) ; return phiInfoElementGetSources ( InfoElement ) .


<s> static MachineBasicBlock * split ( MachineBasicBlock :: iterator I ) { MachineBasicBlock * MBB = ( * I ) . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * SuccMBB = MF -> CreateMachineBasicBlock ( ) ; auto MBBIter = ++ ( MBB -> getIterator


<s> MachineBasicBlock * EntrySucc = split ( Entry -> getFirstNonPHI ( ) ) ; MachineBasicBlock * Exit = LRegion -> getExit ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * Entry ) << <STR_LIT> << printMBBReference ( * Entry

) << <STR_LIT> << printMBBReference ( * EntrySucc ) << <STR_LIT> ) ;


<s> auto MRTRegion = LRegion -> getRegionMRT ( ) ; auto Exit = LRegion -> getExit ( ) ; auto MF = Exit -> getParent ( ) ; auto Succ = MRTRegion -> getSucc ( ) ; auto NewExit = MF -> CreateMachineBasicBlock ( ) ; auto AfterExitIter = Exit -> getIterator ( ) ; AfterExitIter ++ ; MF -> insert ( AfterExitIter , NewExit ) ; Exit -> removeSuccessor ( Succ ) ; Exit -> addSuccessor ( NewExit ) ; NewExit -> addSuccessor ( Succ ) ; insertUnconditionalBranch ( NewExit , Succ ) ; LRegion -> addMBB ( NewExit ) ; LRegion -> setExit ( NewExit ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NewExit -> getNumber ( ) << <STR_LIT> ) ; for ( auto & II : * Succ ) { MachineInstr & Instr


<s> SmallVector < unsigned , <NUM_LIT> > PHIRegionIndices ; getPHIRegionIndices ( LRegion , PHI , PHIRegionIndices ) ; assert ( PHIRegionIndices . size ( ) == <NUM_LIT> ) ; unsigned RegionIndex = PHIRegionIndices [ <NUM_LIT> ] ; unsigned RegionSourceReg = getPHISourceReg ( PHI , RegionIndex ) ; MachineBasicBlock * RegionSourceMBB = getPHIPred ( PHI , RegionIndex ) ; unsigned PHIDest = getPHIDestReg ( PHI ) ; unsigned PHISource = PHIDest ; unsigned ReplaceReg ; if ( shrinkPHI ( PHI , PHIRegionIndices , & ReplaceReg ) ) { PHISource = ReplaceReg ; } const TargetRegisterClass * RegClass = MRI -> getRegClass ( PHIDest ) ; unsigned NewDestReg = MRI -> createVirtualRegister ( RegClass ) ; LRegion -> replaceRegisterInsideRegion ( PHIDest , NewDestReg , false , MRI ) ; MachineInstrBuilder MIB = BuildMI ( * EntrySucc , EntrySucc -> instr_begin ( ) , PHI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: PHI ) , NewDestReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( NewDestReg , TRI ) << <STR_LIT> ) ; MIB . addReg ( PHISource ) ; MIB . addMBB ( Entry ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( PHISource , TRI ) << <STR_LIT> << printMBBReference ( * Entry ) ) ; MIB . addReg ( RegionSourceReg )


<s> if ( PHIInfo . isSource ( Reg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; addLiveOut ( Reg ) ; } else { for ( auto & UI : MRI -> use_operands ( Reg ) ) { if ( UI . getParent ( ) -> getParent ( ) != MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; addLiveOut ( Reg ) ; } else { MachineInstr * UseInstr = UI . getParent ( ) ; for ( MachineBasicBlock :: instr_iterator MII = UseInstr -> getIterator ( ) , MIE = UseInstr -> getParent ( ) -> instr_end ( ) ; MII != MIE ; ++ MII ) { if ( ( & ( * MII ) ) == DefInstr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; addLiveOut ( Reg )


<s> void LinearizedRegion :: storeLiveOutRegRegion ( RegionMRT * Region , unsigned Reg , MachineInstr * DefInstr , const MachineRegisterInfo * MRI , const TargetRegisterInfo * TRI , PHILinearize & PHIInfo ) { if ( TRI -> isVirtualRegister ( Reg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) <<


<s> void LinearizedRegion :: storeLiveOutRegRegion ( RegionMRT * Region , unsigned Reg , MachineInstr * DefInstr , const MachineRegisterInfo * MRI , const TargetRegisterInfo * TRI , PHILinearize & PHIInfo ) { if ( TRI -> isVirtualRegister ( Reg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; for ( auto & UI : MRI -> use_operands ( Reg ) ) { if ( ! Region -> contains ( UI . getParent ( ) -> getParent ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( void * ) Region


<s> for ( auto CI : * Children ) { if ( CI -> isMBB ( ) ) { auto MBB = CI -> getMBBMRT ( ) -> getMBB ( ) ; storeMBBLiveOuts ( MBB , MRI , TRI , PHIInfo , TopRegion ) ; } else { LinearizedRegion * SubRegion = CI -> getRegionMRT ( ) -> getLinearizedRegion ( ) ; for ( auto MBBI : SubRegion -> MBBs ) { storeMBBLiveOuts ( MBBI , MRI , TRI , PHIInfo , TopRegion ) ; } } } if ( CurrentTopRegion == nullptr ) { auto Succ = Region -> getSucc ( ) ; for ( auto & II : * Succ ) { if ( II . isPHI ( )


<s> } else { LinearizedRegion * SubRegion = CI -> getRegionMRT ( ) -> getLinearizedRegion ( ) ; for ( auto MBBI : SubRegion -> MBBs ) { storeMBBLiveOuts ( MBBI , MRI , TRI , PHIInfo , TopRegion ) ; } } } if ( CurrentTopRegion == nullptr ) { auto Succ = Region -> getSucc ( ) ; for ( auto & II : * Succ ) { if ( II . isPHI ( ) ) { MachineInstr & PHI = II ; int numPreds = getPHINumInputs


<s> void LinearizedRegion :: storeMBBLiveOuts ( MachineBasicBlock * MBB , const MachineRegisterInfo * MRI , const TargetRegisterInfo * TRI , PHILinearize & PHIInfo , RegionMRT * TopRegion ) { for ( auto & II : * MBB ) { for ( auto & RI : II . defs ( ) ) { storeLiveOutRegRegion ( TopRegion , RI . getReg ( ) , RI . getParent ( ) , MRI , TRI , PHIInfo ) ; } for ( auto & IRI : II . implicit_operands ( ) ) { if ( IRI . isDef ( ) ) { storeLiveOutRegRegion ( TopRegion , IRI . getReg ( ) , IRI . getParent ( ) , MRI ,


<s> unsigned <ISA_LIT>MachineCFGStructurizer :: storePHILinearizationInfo ( MachineInstr & PHI , SmallVector < unsigned , <NUM_LIT> > * RegionIndices ) { unsigned DestReg = getPHIDestReg ( PHI ) ; unsigned LinearizeDestReg = MRI -> createVirtualRegister ( MRI -> getRegClass ( DestReg ) ) ; PHIInfo . addDest ( LinearizeDestReg , PHI . getDebugLoc ( ) ) ; storePHILinearizationInfoDest ( LinearizeDestReg , PHI , RegionIndices ) ; return LinearizeDestReg


<s> unsigned LinearizeDestReg = MRI -> createVirtualRegister ( MRI -> getRegClass ( DestReg ) ) ; PHIInfo . addDest ( LinearizeDestReg , PHI . getDebugLoc ( ) ) ; storePHILinearizationInfoDest ( LinearizeDestReg , PHI , RegionIndices


<s> for ( auto i : * RegionIndices ) { PHIInfo . addSource ( LDestReg , getPHISourceReg ( PHI , i ) , getPHIPred ( PHI , i ) ) ; } } else


<s> for ( auto i : * RegionIndices ) { PHIInfo . addSource ( LDestReg , getPHISourceReg ( PHI , i ) , getPHIPred ( PHI , i ) ) ; } }


<s> return true ; } else if ( regionIsSequence ( Region ) ) { fixupRegionExits ( Region ) ; return false ; } else { structurizeComplexRegion ( Region


<s> bool Changed = false ; auto Children = Region -> getChildren ( ) ; for ( auto CI : * Children ) { if ( CI -> isRegion ( )


<s> } for ( auto CI : Children ) { delete & ( * CI


<s> for ( auto CI : Children ) { delete & ( *


<s> MachineFunctionInfo ( ) , ShaderType ( ShaderType :: COMPUTE ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , ScratchSize


<s> unsigned getShaderType ( ) const { return


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , IsModuleEntryFunction (

<STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) {


<s> static bool canElideModuleLDS ( const Function &


<s> Align Alignment = DL . getValueOrABITypeAlignment ( GV . getAlign ( ) , GV . getValueType ( ) ) ; if ( Alignment <= DynLDSAlign ) return ; LDSSize = alignTo ( StaticLDSSize , Alignment ) ; DynLDSAlign = Alignment


<s> uint64_t allocateKernArg ( uint64_t Size , unsigned Align ) { assert ( isPowerOf2_32 ( Align ) ) ; KernArgSize = alignTo ( KernArgSize


<s> assert ( isPowerOf2_32 ( Align ) ) ; KernArgSize = alignTo ( KernArgSize , Align ) ; uint64_t Result = KernArgSize ; KernArgSize += Size ; MaxKernArgAlign = std :: max ( Align , MaxKernArgAlign ) ; return


<s> const GlobalVariable * GV = M -> getNamedGlobal ( <STR_LIT> ) ; if ( GV ) { unsigned Offset = allocateLDSGlobal ( M -> getDataLayout ( ) , * GV ) ; ( void )


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , IsModuleEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF . getFunction ( ) ; Attribute MemBoundAttr = F . getFnAttribute ( <STR_LIT> ) ; MemoryBound = MemBoundAttr . getValueAsBool ( ) ; Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ; WaveLimiter = WaveLimitAttr . getValueAsBool


<s> uint64_t getKernArgSize ( ) const { return


<s> unsigned getLDSSize ( ) const { return


<s> void setABIArgOffset ( unsigned NewOffset ) { ABIArgOffset = NewOffset


<s> unsigned Align = GV . getAlignment ( ) ; if ( Align == <NUM_LIT> ) Align = DL . getABITypeAlignment ( GV . getValueType ( ) ) ; unsigned Offset = LDSSize = alignTo ( LDSSize , Align ) ; Entry . first -> second = Offset ; LDSSize += DL . getTypeAllocSize ( GV . getValueType


<s> const Function & F = MF . getFunction ( ) ; if ( auto * Resolver = MF . getMMI ( ) . getResolver ( ) ) { if ( <ISA_LIT>PerfHintAnalysis * PHA = static_cast < <ISA_LIT>PerfHintAnalysis * > ( Resolver -> getAnalysisIfAvailable ( & <ISA_LIT>PerfHintAnalysisID , true ) ) ) { MemoryBound = PHA -> isMemoryBound ( & F


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , ExplicitKernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) , MemoryBound ( false ) , WaveLimiter ( false ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF . getFunction


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , IsKernel ( MF . getFunction ( ) -> getCallingConv

( ) == CallingConv :: <ISA_LIT>_KERNEL || MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: SPIR_KERNEL ) {


<s> uint64_t getExplicitKernArgSize ( ) const


<s> uint32_t getLDSSize ( ) const { return


<s> bool hasNoSignedZerosFPMath ( ) const { return NoSignedZerosFPMath


<s> bool isMemoryBound ( ) const { return MemoryBound


<s> bool isModuleEntryFunction ( ) const


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , IsModuleEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF


<s> Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ; WaveLimiter = WaveLimitAttr . isStringAttribute ( ) && WaveLimitAttr . getValueAsString ( ) == <STR_LIT> ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) ExplicitKernArgSize =

ST . getExplicitKernArgSize ( F , MaxKernArgAlign ) ;


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , ExplicitKernArgSize ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , Mode ( MF . getFunction ( ) , MF . getSubtarget < GCNSubtarget > ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) , MemoryBound ( false ) , WaveLimiter ( false ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF . getFunction ( ) ; Attribute MemBoundAttr = F . getFnAttribute ( <STR_LIT> ) ; MemoryBound = MemBoundAttr . isStringAttribute ( ) && MemBoundAttr . getValueAsString ( ) == <STR_LIT> ; Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ; WaveLimiter = WaveLimitAttr . isStringAttribute ( ) && WaveLimitAttr . getValueAsString ( ) == <STR_LIT> ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) ExplicitKernArgSize = ST

. getExplicitKernArgSize ( F , MaxKernArgAlign ) ;


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , ExplicitKernArgSize ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , Mode ( MF . getFunction ( ) , MF . getSubtarget < GCNSubtarget > ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) , MemoryBound ( false ) , WaveLimiter ( false ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get (


<s> MemoryBound = MemBoundAttr . getValueAsBool ( ) ; Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ; WaveLimiter = WaveLimitAttr . getValueAsBool ( ) ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) ExplicitKernArgSize

= ST . getExplicitKernArgSize ( F , MaxKernArgAlign ) ;


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , IsEntryFunction ( <STR_LIT> ( MF

. getFunction ( ) -> getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) {


<s> MachineFunctionInfo ( ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT> ) , IsKernel


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF .

getTarget ( ) . Options . NoSignedZerosFPMath ) {


<s> const Function & F = MF . getFunction ( ) ; Attribute MemBoundAttr = F . getFnAttribute ( <STR_LIT> ) ; MemoryBound = MemBoundAttr . isStringAttribute ( ) && MemBoundAttr . getValueAsString ( ) == <STR_LIT> ; Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ; WaveLimiter = WaveLimitAttr . isStringAttribute ( ) && WaveLimitAttr . getValueAsString ( ) == <STR_LIT> ; CallingConv :: ID CC = F .


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , ExplicitKernArgSize ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) , MemoryBound ( false ) , WaveLimiter ( false ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , IsEntryFunction ( isEntryFunctionCC ( MF . getFunction ( ) -> getCallingConv

( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) {


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , IsEntryFunction ( isEntryFunctionCC ( MF . getFunction ( ) -> getCallingConv


<s> auto Entry = LocalMemoryObjects . insert ( std :: make_pair ( & GV , <NUM_LIT> ) ) ; if ( ! Entry . second ) return Entry . first -> second ; Align Alignment = DL . getValueOrABITypeAlignment ( GV . getAlign ( ) , GV . getValueType ( ) ) ; unsigned Offset = LDSSize = alignTo ( LDSSize , Alignment ) ; Entry . first ->


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF . getFunction ( ) ; Attribute MemBoundAttr = F . getFnAttribute ( <STR_LIT> ) ; MemoryBound = MemBoundAttr . isStringAttribute ( ) && MemBoundAttr . getValueAsString ( ) == <STR_LIT> ; Attribute WaveLimitAttr = F . getFnAttribute (


<s> MachineFunctionInfo ( ) , Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF . getFunction ( ) ; Attribute MemBoundAttr = F . getFnAttribute ( <STR_LIT> ) ; MemoryBound = MemBoundAttr . isStringAttribute ( ) && MemBoundAttr . getValueAsString ( ) == <STR_LIT> ; Attribute WaveLimitAttr = F . getFnAttribute


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , ExplicitKernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) , MemoryBound ( false ) , WaveLimiter ( false ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF . getFunction ( ) ; Attribute MemBoundAttr = F . getFnAttribute ( <STR_LIT> ) ; MemoryBound = MemBoundAttr . isStringAttribute ( ) && MemBoundAttr . getValueAsString ( ) == <STR_LIT> ; Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ; WaveLimiter = WaveLimitAttr . isStringAttribute ( ) && WaveLimitAttr . getValueAsString


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT>


<s> bool <ISA_LIT>MachineFunction :: isKernel ( ) const { return IsKernel


<s> AgentS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT> ) ; WorkgroupS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT> ) ; WavefrontS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT> ) ; SystemOneAddressSpaceS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT> ) ; AgentOneAddressSpaceS<ISA_LIT>D = CTX . getOrInsertSyncScopeID (


<s> SyncScope :: ID getAgentOneAddressSpaceS<ISA_LIT>D ( ) const { return


<s> SyncScope :: ID getWorkgroupOneAddressSpaceS<ISA_LIT>D


<s> Optional < bool > isSyncScopeInclusion ( SyncScope :: ID A , SyncScope :: ID B ) const { const auto & AIO = getSyncScopeInclusionOrdering ( A ) ; const auto & BIO = getSyncScopeInclusionOrdering ( B ) ; if ( ! AIO || ! BIO ) return None ; bool IsAOneAddressSpace = isOneAddressSpace ( A )


<s> WorkgroupS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT> ) ; WavefrontS<ISA_LIT>D = CTX . getOrInsertSyncScopeID


<s> AgentS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT> ) ; WorkgroupS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT> ) ; WavefrontS<ISA_LIT>D = CTX . getOrInsertSyncScopeID ( <STR_LIT>


<s> SyncScope :: ID getAgentS<ISA_LIT>D ( ) const { return AgentS<ISA_LIT>D


<s> else if ( S<ISA_LIT>D == getAgentS<ISA_LIT>D ( ) ) return <NUM_LIT> ; else if ( S<ISA_LIT>D == SyncScope ::


<s> SyncScope :: ID getWavefrontS<ISA_LIT>D (


<s> SyncScope :: ID getWorkgroupS<ISA_LIT>D ( ) const


<s> const auto & AIO = getSyncScopeInclusionOrdering ( A ) ; const auto & BIO = getSyncScopeInclusionOrdering ( B ) ; if ( ! AIO || ! BIO


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! FirstMI ) return true ; const MachineOperand * Src2 = TII . getNamedOperand ( SecondMI , <STR_LIT> :: src2 ) ; return FirstMI -> definesRegister ( Src2 ->


<s> if ( ! FirstMI ) return true ; const MachineOperand * Src2 = TII . getNamedOperand ( SecondMI , <STR_LIT> :: src2 ) ; return FirstMI -> definesRegister ( Src2 -> getReg ( ) ) ; } default : return false


<s> return createMacroFusionDAGMutation ( shouldScheduleAdjacent


<s> return SectionName == <STR_LIT> || SectionName == <STR_LIT> || SectionName == <STR_LIT> ||

SectionName == <STR_LIT> || MCAsmInfo :: shouldOmitSectionDirective ( SectionName ) ;


<s> return SectionName == <STR_LIT> || SectionName == <STR_LIT> || SectionName == <STR_LIT> || SectionName == <STR_LIT>

|| MCAsmInfo :: shouldOmitSectionDirective ( SectionName ) ;


<s> StackGrowsUp = true ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false


<s> MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasNoDeadStrip = true ; SupportsDebugInformation = true ; UsesCFIForDebug = true ; DwarfRegNumForCFI = true ; UseIntegratedAssembler =


<s> SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasDotTypeDotSizeDirective = false ; HasNoDeadStrip = true ; WeakRefDirective = <STR_LIT> ; SupportsDebugInformation = true


<s> StackGrowsUp = true ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT>


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) : MCAsmInfoELF ( ) { CodePointerSize = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes =


<s> CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes =


<s> HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasNoDeadStrip = true ; WeakRefDirective = <STR_LIT> ; SupportsDebugInformation =


<s> CodePointerSize = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; StackGrowsUp = true ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax =


<s> StackGrowsUp = true ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true


<s> MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd =


<s> InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasNoDeadStrip = true ; WeakRefDirective = <STR_LIT> ; SupportsDebugInformation =


<s> MaxInstLength = <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes =


<s> CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT , const MCTargetOptions & Options ) : MCAsmInfoELF ( ) { CodePointerSize = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; StackGrowsUp = true ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax =


<s> HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true


<s> unsigned <ISA_LIT>MCAsmInfo :: getMaxInstLength ( const MCSubtargetInfo * STI ) const { if ( ! STI || STI -> getTargetTriple ( ) . getArch ( ) == Triple :: r600 ) return MaxInstLength ; if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI -> getFeatureBits ( )


<s> if ( ! STI || STI -> getTargetTriple ( ) . getArch ( ) == Triple :: r600 ) return MaxInstLength ; if ( STI -> getFeatureBits ( ) [


<s> virtual unsigned getSMEMOffsetEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI


<s> virtual unsigned getSDWA9SrcEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT>


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT>


<s> virtual uint64_t getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const


<s> virtual unsigned getSDWASrcEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ,


<s> virtual unsigned getSDWASrcEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl

< MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


<s> virtual unsigned getSDWAVopcDstEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo


<s> virtual unsigned getSOPPBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , const <ISA_LIT>Subtarget & st ) : Ctx ( ctx ) , ST ( st


<s> } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back ( ) ; raw_string_ostream HexStream ( HexLine ) ; for ( size_t i = <NUM_LIT> ; i < CodeBytes . size ( ) ; i +=


<s> break ; case MachineOperand :: MO_Register : MCOp = MCOperand :: createReg ( <STR_LIT> ( MO . getReg ( ) , ST ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( GV -> getName ( ) ) ) ; MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Sym , Ctx ) ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( MO . getSymbolName ( ) ) ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } } OutMI . addOperand (


<s> EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back ( ) ; raw_string_ostream HexStream ( HexLine ) ; for ( size_t i = <NUM_LIT> ; i < CodeBytes . size ( ) ; i += <NUM_LIT> ) { unsigned int CodeDWord = * ( unsigned int * ) & CodeBytes [ i ] ; HexStream << format ( <STR_LIT> , ( i > <NUM_LIT>

? <STR_LIT> : <STR_LIT> ) , CodeDWord ) ;


<s> case <ISA_LIT>InstrInfo :: MO_GOTPCREL : return MCSymbolRefExpr :: VK_GOTPCREL ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI ; case <ISA_LIT>InstrInfo :: MO_REL32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO


<s> if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; lowerOperand ( MO , MCOp


<s> bool <ISA_LIT>AsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand ( MO


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand ( MO


<s> return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back ( ) ; raw_string_ostream HexStream ( HexLine ) ; for ( size_t i = <NUM_LIT> ; i < CodeBytes . size ( ) ; i += <NUM_LIT> ) { unsigned int CodeDWord = * ( unsigned int * ) & CodeBytes [


<s> if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; StringRef Err ; if ( ! STI . getInstrInfo ( ) -> verifyInstruction ( * MI , Err ) ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( <STR_LIT> + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode (


<s> lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Src ) ; OutMI . addOperand ( Dest ) ; OutMI . addOperand ( Src ) ; return ; } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands


<s> } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter


<s> OutMI . addOperand ( Dest ) ; OutMI . addOperand ( Src ) ; return ; } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; lowerOperand ( MO ,


<s> const auto * TII = ST . getInstrInfo ( ) ; if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) { OutMI . setOpcode ( TII -> pseudoToMCOpcode ( <STR_LIT> ) ) ; MCOperand Dest , Src ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Src ) ; OutMI . addOperand ( Dest ) ; OutMI . addOperand ( Src ) ; return ; } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode


<s> MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back ( ) ; raw_string_ostream HexStream ( HexLine ) ; for ( size_t i = <NUM_LIT> ; i < CodeBytes . size ( ) ; i += <NUM_LIT> ) { unsigned int CodeDWord = * ( unsigned int * )


<s> switch ( MOFlags ) { default : return MCSymbolRefExpr :: VK_None ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL : return MCSymbolRefExpr :: VK_GOTPCREL ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI ; case <ISA_LIT>InstrInfo :: MO_REL32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO ; case <ISA_LIT>InstrInfo :: MO_REL32_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_HI ; case <ISA_LIT>InstrInfo :: MO_ABS32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_ABS32_LO ; case <ISA_LIT>InstrInfo


<s> case <ISA_LIT>InstrInfo :: MO_REL32_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_HI ; case <ISA_LIT>InstrInfo :: MO_ABS32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_ABS32_LO ; case <ISA_LIT>InstrInfo :: MO_ABS32_HI : return MCSymbolRefExpr ::


<s> else if ( Opcode == <STR_LIT> ) { OutMI . setOpcode ( TII -> pseudoToMCOpcode ( <STR_LIT> ) ) ; MCOperand Dest , Src ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Src ) ; OutMI . addOperand ( Dest ) ; OutMI . addOperand ( Src ) ; return ; } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) .


<s> if ( const MCExpr * E = lowerAddrSpaceCast ( TM , CV , OutContext ) ) return E ; return AsmPrinter :: lowerConstant ( CV )


<s> bool <ISA_LIT>AsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { const GCNSubtarget & STI = MF -> getSubtarget < GCNSubtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand ( MO


<s> const GCNSubtarget & STI = MF -> getSubtarget < GCNSubtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; return MCInstLowering . lowerOperand ( MO ,


<s> MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( )


<s> <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back


<s> const MCExpr * <ISA_LIT>AsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const MCExpr * E = lowerAddrSpaceCast ( TM , CV , OutContext ) ) return E ; return AsmPrinter :: lowerConstant (


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & Ctx , const <ISA_LIT>Subtarget & ST , const AsmPrinter


<s> case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; return true ; case MachineOperand :: MO_Register : MCOp = MCOperand :: createReg ( <STR_LIT> ( MO . getReg ( ) , ST ) ) ; return true ; case MachineOperand :: MO_MachineBasicBlock : { if ( MO . getTargetFlags ( ) != <NUM_LIT> ) { MCOp = MCOperand :: createExpr ( getLongBranchBlockExpr ( * MO . getParent ( ) -> getParent ( ) , MO ) ) ; } else { MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; } return true ; } case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; SmallString < <NUM_LIT> > SymbolName ; AP . getNameWithPrefix ( SymbolName , GV ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( SymbolName ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , getVariantKind ( MO . getTargetFlags ( ) ) , Ctx ) ; int64_t Offset = MO . getOffset ( ) ; if ( Offset != <NUM_LIT> ) { Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; } MCOp = MCOperand ::


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( ! MI -> isPseudo ( ) && STI . isCPUStringValid ( STI . getCPU ( ) ) && ( ! STI . hasOffset3fBug ( ) || ! MI -> isBranch ( ) ) ) { SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; std :: unique_ptr < MCCodeEmitter > InstEmitter ( create<ISA_LIT>MCCodeEmitter ( * STI . getInstrInfo ( ) , * OutContext . getRegisterInfo ( ) , OutContext ) ) ; InstEmitter -> encodeInstruction ( TmpInst , CodeStream , Fixups , STI ) ; assert ( CodeBytes . size ( ) == STI . getInstrInfo ( ) -> getInstSizeInBytes ( * MI ) ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , <NUM_LIT> , StringRef ( ) , STI , DisasmStream ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; DumpCodeInstEmitter -> encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back ( ) ; raw_string_ostream HexStream ( HexLine ) ; for ( size_t i = <NUM_LIT> ; i < CodeBytes . size ( ) ; i += <NUM_LIT> ) { unsigned int CodeDWord = * ( unsigned int * ) & CodeBytes [ i ] ; HexStream << format ( <STR_LIT> , ( i > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , CodeDWord ) ; } DisasmStream . flush ( ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen


<s> const GCNSubtarget & STI = MF -> getSubtarget < GCNSubtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; StringRef Err ; if ( ! STI . getInstrInfo ( ) -> verifyInstruction ( * MI , Err ) ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { emitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> isMetaInstruction ( ) ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( ! MI -> isPseudo ( ) && STI . isCPUStringValid ( STI . getCPU ( ) ) && ( ! STI . hasOffset3fBug ( ) || ! MI -> isBranch ( ) ) ) { SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; std :: unique_ptr < MCCodeEmitter > InstEmitter ( create<ISA_LIT>MCCodeEmitter ( * STI . getInstrInfo ( ) , OutContext ) ) ; InstEmitter -> encodeInstruction ( TmpInst , CodeStream , Fixups , STI ) ; assert ( CodeBytes . size ( ) == STI . getInstrInfo ( ) -> getInstSizeInBytes ( * MI ) ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , <NUM_LIT> , StringRef ( ) , STI , DisasmStream ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes )


<s> C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { emitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( ! MI -> isPseudo ( ) && STI . isCPUStringValid ( STI . getCPU ( ) ) ) { SmallVector < MCFixup , <NUM_LIT>


<s> emitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( ! MI -> isPseudo ( ) && STI . isCPUStringValid ( STI . getCPU ( ) ) ) { SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; std :: unique_ptr < MCCodeEmitter > InstEmitter ( create<ISA_LIT>MCCodeEmitter ( * STI . getInstrInfo ( ) , * OutContext . getRegisterInfo ( ) , OutContext ) ) ; InstEmitter -> encodeInstruction ( TmpInst , CodeStream , Fixups , STI ) ; assert ( CodeBytes . size ( ) == STI . getInstrInfo ( ) -> getInstSizeInBytes ( * MI ) ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , <NUM_LIT> , StringRef ( ) , STI , DisasmStream ) ; SmallVector < MCFixup , <NUM_LIT>


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; StringRef Err ; if ( ! STI . getInstrInfo ( ) -> verifyInstruction ( * MI , Err ) ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo >


<s> MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine


<s> unsigned Opcode = MI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; int MCOpcode = ST . getInstrInfo ( ) -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand


<s> if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; int MCOpcode = ST . getInstrInfo ( ) -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; lowerOperand ( MO , MCOp ) ; OutMI . addOperand ( MCOp


<s> MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) .


<s> const MCConstantExpr * One = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; SrcBBSym = MCBinaryExpr :: createAdd ( SrcBBSym , One , Ctx ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) return MCBinaryExpr :: createSub ( DestBBSym , SrcBBSym , Ctx ) ; assert ( MO . getTargetFlags ( ) == <STR_LIT> ) ; return MCBinaryExpr :: createSub ( SrcBBSym


<s> } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode


<s> if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { emitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> isMetaInstruction ( ) ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( ! MI -> isPseudo ( ) && STI . isCPUStringValid ( STI . getCPU ( ) ) && ( ! STI . hasOffset3fBug ( ) || ! MI -> isBranch ( ) ) ) { SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; std :: unique_ptr < MCCodeEmitter > InstEmitter ( create<ISA_LIT>MCCodeEmitter ( * STI . getInstrInfo ( ) , * OutContext . getRegisterInfo ( ) , OutContext ) ) ; InstEmitter -> encodeInstruction ( TmpInst , CodeStream , Fixups , STI ) ; assert ( CodeBytes . size ( ) == STI . getInstrInfo


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) { OutMI . setOpcode ( TII -> pseudoToMCOpcode ( <STR_LIT> ) ) ; MCOperand Dest , Src ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Src ) ; OutMI . addOperand ( Dest ) ; OutMI . addOperand ( Src ) ; return ; } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; lowerOperand ( MO , MCOp ) ; OutMI . addOperand ( MCOp ) ; } int FIIdx = <STR_LIT> ( MCOpcode ,


<s> return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back ( ) ; raw_string_ostream HexStream ( HexLine ) ; for ( size_t i = <NUM_LIT> ; i < CodeBytes . size ( ) ; i += <NUM_LIT> ) { unsigned int CodeDWord = * ( unsigned int * ) & CodeBytes [ i ] ; HexStream << format ( <STR_LIT> , ( i > <NUM_LIT> ? <STR_LIT> : <STR_LIT> )


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( GV -> getName ( ) ) ) ; const MCExpr * SymExpr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; const MCExpr * Expr = MCBinaryExpr :: createAdd ( SymExpr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( MO . getSymbolName ( ) ) ) ; Sym -> setExternal ( true ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } } OutMI . addOperand (


<s> DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine =


<s> while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( <STR_LIT> + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( )


<s> switch ( MOFlags ) { default : return MCSymbolRefExpr :: VK_None ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL : return


<s> void <ISA_LIT>MCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { int MCOpcode = ST . getInstrInfo ( ) -> pseudoToMCOpcode ( MI -> getOpcode ( ) ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_Register : MCOp = MCOperand :: createReg ( <STR_LIT> ( MO . getReg ( ) , ST ) ) ; break ; case MachineOperand


<s> MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer ->


<s> LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer ,


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; const GCNSubtarget & STI = MF -> getSubtarget < GCNSubtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; StringRef Err ; if ( ! STI . getInstrInfo ( ) -> verifyInstruction ( * MI , Err ) ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB


<s> while ( I != MBB -> end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( I ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes


<s> break ; case MachineOperand :: MO_Register : MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( GV -> getName ( ) ) ) ; MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Sym , Ctx ) ) ; break ; } case MachineOperand :: MO_TargetIndex : { assert ( MO . getIndex ( ) == <STR_LIT> ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( END_OF_TEXT_LABEL_NAME ) ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( MO . getSymbolName ( ) ) ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; MCOp = MCOperand :: createExpr


<s> if ( TT . getArch ( ) == Triple :: r600 ) Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; else Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; return


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; if ( TT . getArch ( ) == Triple :: r600 ) Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; else Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT>


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) ,


<s> TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCCodeEmitter ( getTheGCNTarget ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getTheGCNTarget ( ) , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getTheGCNTarget ( )


<s> static MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S


<s> if ( TT . getArch ( ) == Triple :: r600 ) Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; else Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; return X


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU ,


<s> if ( T . getOS ( ) == Triple :: AMDHSA ) return create<ISA_LIT>ELFStreamer ( Context , MAB ,


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { if ( T . getOS ( ) == Triple :: AMDHSA ) return create<ISA_LIT>ELFStreamer (

Context , MAB , OS , Emitter , RelaxAll ) ;


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target


<s> if ( T . getArch ( ) == Triple :: r600 ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; else return new <ISA_LIT>InstPrinter ( MAI , MII ,


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( T . getArch ( ) == Triple :: r600 ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; else return new <ISA_LIT>InstPrinter ( MAI , MII


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; if ( TT . getArch ( ) == Triple :: r600 ) Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ; else Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { if ( TT . getArch ( ) == Triple :: r600 ) return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { return new <ISA_LIT>TargetELFStreamer ( S ,


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { return new <ISA_LIT>TargetELFStreamer ( S , STI


<s> return create<ISA_LIT>ELFStreamer ( T , Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter )


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == <NUM_LIT> || ! Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( <NUM_LIT> )


<s> LLVM_EXTERNAL_VI<ISA_LIT>BILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { TargetRegistry :: RegisterMCInstrInfo ( getTheGCNTarget ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getTheGCNTarget ( ) } ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model


<s> for ( Target * T : { & The<ISA_LIT>Target , & TheGCNTarget } ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCCodeGenInfo ( * T , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return T . getArch ( ) == Triple :: r600 ? new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) : new <ISA_LIT>InstPrinter ( MAI , MII


<s> return create<ISA_LIT>ELFStreamer ( T , Context , std :: move ( MAB ) , OS , std :: move


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend


<s> TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) ,


<s> TargetRegistry :: RegisterMCCodeGenInfo ( * T , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T ,


<s> return false ; default : break ; } } const auto checkNoAlias = [ AA , Ptr ] ( auto I ) -> bool { return I && AA -> isNoAlias ( I -> getPointerOperand ( ) , Ptr ) ; } ; if ( checkNoAlias ( dyn_cast < AtomicCmpXchgInst > ( DefInst ) ) || checkNoAlias ( dyn_cast < AtomicRMWInst > ( DefInst


<s> MemoryAccess * MA = WorkList . pop_back_val ( ) ; if ( ! Visited . insert ( MA ) . second ) continue ; if ( MSSA -> isLiveOnEntryDef ( MA ) ) continue ; if ( MemoryDef * Def = dyn_cast < MemoryDef > ( MA ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Def -> getMemoryInst ( ) << '\n' ) ; if ( isReallyAClobber ( Load -> getPointerOperand ( ) , Def , AA )


<s> default : break ; } } const auto checkNoAlias = [ AA , Ptr ] ( auto I ) -> bool { return I && AA -> isNoAlias ( I -> getPointerOperand ( ) , Ptr ) ; } ; if ( checkNoAlias ( dyn_cast < AtomicCmpXchgInst > ( DefInst ) ) || checkNoAlias ( dyn_cast < AtomicRMWInst > ( DefInst ) ) ) return false ; return true


<s> static void addPipelineEdges ( const llvm :: ArrayRef < InstructionClass * > PipelineOrder , ScheduleDAGInstrs * DAG ) { for ( int i = <NUM_LIT> ; i < ( int ) PipelineOrder . size ( ) - <NUM_LIT> ; i ++ ) { auto StageA = PipelineOrder [ i ] ; for ( int j = i + <NUM_LIT> ; j < ( int ) PipelineOrder . size ( ) ; j ++ ) { auto StageB = PipelineOrder [ j ] ; for ( auto SUnitA : StageA -> Collection ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; DAG -> dumpNode ( * SUnitA ) ; ) ; for ( auto SUnitB : StageB -> Collection ) { if ( DAG -> canAddEdge ( SUnitB , SUnitA ) ) { DAG -> addEdge ( SUnitB , SDep ( SUnitA , SDep :: Artificial ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; DAG -> dumpNode ( * SUnitB ) ; ) ; } else { LLVM_DEBUG ( dbgs (


<s> const GCNSubtarget & ST = DAGInstrs -> MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ! ST . hasMAIInsts ( ) ) return ; DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; const TargetSchedModel * TSchedModel = DAGInstrs -> getSchedModel ( ) ; if ( ! TSchedModel || DAG -> SUnits . empty ( ) ) return ; const IsInstructionType isMFMAFn = [ this ] ( const MachineInstr & MI ) { if ( TII -> isMAI ( MI ) && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass MFMASUnits ( isMFMAFn , MFMAGroupMaxSize ) ; const IsInstructionType isVMEMReadFn = [ this ] ( const MachineInstr & MI ) { if ( ( ( TII -> isFLAT ( MI ) && ! TII -> isDS ( MI ) ) || TII -> isVMEM ( MI ) ) && MI . mayLoad ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass VMEMReadSUnits ( isVMEMReadFn , VMEMGroupMaxSize ) ; const IsInstructionType isDSWriteFn = [ this ] ( const MachineInstr & MI ) { if ( TII -> isDS ( MI ) && MI . mayStore ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass DSWriteSUnits ( isDSWriteFn , LDWGroupMaxSize ) ; const IsInstructionType isDSReadFn = [ this ]


<s> InstructionClass MFMASUnits ( isMFMAFn , MFMAGroupMaxSize ) ; const IsInstructionType isVMEMReadFn = [ this ] ( const MachineInstr & MI ) { if ( ( ( TII -> isFLAT ( MI ) && ! TII -> isDS ( MI ) ) || TII -> isVMEM ( MI ) ) && MI . mayLoad ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass VMEMReadSUnits ( isVMEMReadFn , VMEMGroupMaxSize ) ; const IsInstructionType isDSWriteFn = [ this ] ( const MachineInstr & MI ) { if ( TII -> isDS ( MI ) && MI . mayStore ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass DSWriteSUnits ( isDSWriteFn , LDWGroupMaxSize ) ; const IsInstructionType isDSReadFn = [ this ] ( const MachineInstr & MI ) { if ( TII -> isDS ( MI ) && MI . mayLoad ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ; } return false ; } ; InstructionClass DSReadSUnits ( isDSReadFn , LDRGroupMaxSize ) ; SmallVector < InstructionClass * , <NUM_LIT> > PipelineOrder = { & VMEMReadSUnits , & DSReadSUnits , & MFMASUnits , & DSWriteSUnits } ; collectSUnits ( PipelineOrder , TII , DAG


<s> std :: unique_ptr < ScheduleDAGMutation


<s> return EnableMFMAIGroupLP ? std :: make_unique < MFMAIGroupLPDAGMutation > ( )


<s> InstructionClass ( IsInstructionType IsInstructionClass , int maxSize ) : isInstructionClass ( IsInstructionClass


<s> InstructionClass ( IsInstructionType IsInstructionClass , int maxSize ) : isInstructionClass (

IsInstructionClass ) , MaxSize ( maxSize ) { }


<s> return ! ( MaxSize <= <NUM_LIT> ) && ( int ) Collection .


<s> bool IsFull ( ) { return ! ( MaxSize <= <NUM_LIT> ) && ( int )


<s> static void collectFunctionUsers ( User * U , DenseSet < Function * > & Funcs ) { if ( auto * I = dyn_cast < Instruction > ( U ) ) { auto * F = I -> getParent ( ) -> getParent ( ) ; if ( Funcs . insert ( F ) . second ) collectCallers ( F , Funcs ) ; return ; } if ( ! isa < Constant > ( U )


<s> if ( auto * CI = dyn_cast < CallInst > ( & * U ) ) { auto * Caller = CI -> getParent ( ) -> getParent