<s> Register PCReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto I = MBB . end ( ) ; MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , PCReg ) ; auto & MCCtx = MF -> getContext ( ) ; MCSymbol * PostGetPCLabel = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; GetPC -> setPostInstrSymbol ( * MF , PostGetPCLabel ) ; MCSymbol * OffsetLo = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; MCSymbol * OffsetHi = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addSym ( OffsetLo , MO_FAR_BRANCH_OFFSET ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addSym ( OffsetHi , MO_FAR_BRANCH_OFFSET ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( PCReg ) ; auto ComputeBlockSize = [ ] ( const TargetInstrInfo * TII , const MachineBasicBlock & MBB ) { unsigned Size = <NUM_LIT> ; for ( const MachineInstr & MI : MBB ) Size += TII -> getInstSizeInBytes ( MI ) ; return Size ; } ; RS -> enterBasicBlockEnd ( MBB ) ; Register Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false , <NUM_LIT> ) ; MRI . replaceRegWith ( PCReg , Scav ) ; MRI . clearVirtRegs ( ) ; RS -> setRegUsed ( Scav


<s> assert ( MBB . empty ( ) && <STR_LIT> ) ; assert ( MBB . pred_size ( ) == <NUM_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register PCReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto I = MBB . end ( ) ; MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , PCReg ) ; auto & MCCtx = MF -> getContext ( ) ; MCSymbol * PostGetPCLabel = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; GetPC -> setPostInstrSymbol ( * MF , PostGetPCLabel ) ; MCSymbol * OffsetLo = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; MCSymbol * OffsetHi = MCCtx . createTempSymbol ( <STR_LIT> , true ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addSym ( OffsetLo , MO_FAR_BRANCH_OFFSET ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( PCReg , RegState :: Define , <STR_LIT> ) . addReg ( PCReg , <NUM_LIT> , <STR_LIT> ) . addSym ( OffsetHi , MO_FAR_BRANCH_OFFSET ) ; BuildMI ( & MBB , DL , get ( <STR_LIT>


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ; } case


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ; } case <STR_LIT>


<s> bool <ISA_LIT>InstrInfo :: isIgnorableUse ( const MachineOperand & MO ) const { return MO . getReg ( ) == <STR_LIT> && MO . isImplicit ( ) && isVALU


<s> } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; if ( ! isLegalRegOperand ( MRI , OpInfo , * MO ) ) return false ; bool IsAGPR = RI . isAGPR ( MRI , MO -> getReg ( ) ) ; if ( IsAGPR && ! ST . hasMAIInsts ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; if ( IsAGPR && ( ! ST . hasGFX90AInsts ( ) || ! MRI . reservedRegsFrozen ( ) ) && ( MI . mayLoad ( ) || MI . mayStore ( ) || isDS ( Opc ) || isMIMG ( Opc ) ) ) return false ; const int VDstIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; const int DataIdx = <STR_LIT> ( Opc , isDS ( Opc ) ? <STR_LIT> :: data0 : <STR_LIT> :: vdata ) ; if ( ( int ) OpIdx == VDstIdx && DataIdx != - <NUM_LIT> && MI . getOperand ( DataIdx ) . isReg ( ) && RI . isAGPR ( MRI , MI . getOperand ( DataIdx ) . getReg ( ) ) != IsAGPR ) return false ; if ( ( int ) OpIdx == DataIdx ) { if ( VDstIdx != - <NUM_LIT> && RI . isAGPR ( MRI , MI . getOperand ( VDstIdx ) . getReg ( ) ) != IsAGPR ) return false ; const int Data1Idx = <STR_LIT> ( Opc , <STR_LIT> :: data1 ) ; if ( Data1Idx != - <NUM_LIT> && MI . getOperand ( Data1Idx ) . isReg ( ) && RI . isAGPR ( MRI , MI . getOperand ( Data1Idx ) . getReg ( ) ) != IsAGPR ) return false ; } if ( Opc == <STR_LIT> && ( int ) OpIdx == <STR_LIT> ( Opc , <STR_LIT> :: src0 ) && RI . isSGPRReg ( MRI , MO -> getReg ( ) ) ) return false ; return true ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) || MO -> isGlobal ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO


<s> bool <ISA_LIT>InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isSDWA ( MI ) ) { return ! MI . hasImplicitDef ( ) && MI . getNumImplicitOperands ( ) == MI . getDesc ( ) . getNumImplicitUses ( )


<s> return ! MI . hasImplicitDef ( ) && MI . getNumImplicitOperands ( ) == MI . getDesc ( ) . getNumImplicitUses ( )


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI

-> getStackPtrOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; assert ( DestReg != <STR_LIT> && DestReg != <STR_LIT> && DestReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( DestReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode (

SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ;


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , Begin , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; MachineBasicBlock :: iterator AfterMI = MI ; ++ AfterMI ; for ( auto I = Begin ; I != AfterMI ; I ++ ) { for ( auto & MO : I -> uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , End , MBB . end ( ) ) ; LoopBB -> splice ( LoopBB -> begin ( ) , & MBB , Begin , MBB . end ( ) ) ; MBB . addSuccessor


<s> MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Cond = Inst . getOperand ( <NUM_LIT> ) ; Register SCCSource = Cond . getReg ( ) ; bool IsSCC = ( SCCSource == <STR_LIT> ) ; if ( ! IsSCC && Src0 . isImm ( ) && ( Src0 . getImm ( ) == - <NUM_LIT> ) && Src1 . isImm ( ) && ( Src1 . getImm ( ) == <NUM_LIT> ) ) { MRI . replaceRegWith ( Dest . getReg ( ) , SCCSource ) ; return ; } const TargetRegisterClass * TC = RI . getRegClass ( <STR_LIT> ) ; Register CopySCC = MRI . createVirtualRegister ( TC ) ; if ( IsSCC ) { bool CopyFound = false ; for ( MachineInstr & CandI : make_range ( std :: next ( MachineBasicBlock :: reverse_iterator ( Inst ) ) , Inst . getParent ( ) -> rend ( ) ) ) { if ( CandI . findRegisterDefOperandIdx ( <STR_LIT> , false , false , & RI ) != - <NUM_LIT> ) { if ( CandI . isCopy ( ) && CandI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , CopySCC ) . addReg ( CandI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; CopyFound = true ; } break ; } } if ( ! CopyFound ) { unsigned Opcode = ( ST . getWavefrontSize ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; auto NewSelect = BuildMI ( MBB , MII , DL , get ( Opcode ) , CopySCC ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; NewSelect -> getOperand ( <NUM_LIT> ) . setIsUndef ( Cond .


<s> MachineRegisterInfo & MRI = Inst . getMF ( ) -> getRegInfo ( ) ; MachineOperand & SAddr = Inst . getOperand ( OldSAddrIdx ) ; if ( RI . isSGPRReg ( MRI , SAddr . getReg ( ) ) ) return false ; int NewVAddrIdx = <STR_LIT> ( NewOpc , <STR_LIT> :: vaddr ) ; if ( NewVAddrIdx < <NUM_LIT> ) return false ; int OldVAddrIdx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr ) ; MachineInstr * VAddrDef = nullptr ; if ( OldVAddrIdx >= <NUM_LIT> ) { MachineOperand & VAddr = Inst . getOperand ( OldVAddrIdx ) ; VAddrDef = MRI . getUniqueVRegDef ( VAddr . getReg ( ) ) ; if ( ! VAddrDef || VAddrDef -> getOpcode ( ) != <STR_LIT> || ! VAddrDef -> getOperand ( <NUM_LIT> ) . isImm ( ) || VAddrDef -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; } const MCInstrDesc & NewDesc = get ( NewOpc ) ; Inst . setDesc ( NewDesc ) ; if ( OldVAddrIdx == NewVAddrIdx ) { MachineOperand & NewVAddr = Inst . getOperand ( NewVAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . moveOperands ( & NewVAddr , & SAddr , <NUM_LIT> ) ; Inst . RemoveOperand ( OldSAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . addRegOperandToUseList ( & NewVAddr ) ; }


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; Register OldDstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = Inst . getOpcode ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; unsigned NewOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MRI . replaceRegWith ( OldDstReg ,


<s> Mask &= maxUIntN ( SrcSize ) ; return isPowerOf2_64 ( Mask ) ; } ; MachineOperand * SrcOp = & Def -> getOperand ( <NUM_LIT> ) ; if ( isMask ( SrcOp ) ) SrcOp = & Def -> getOperand ( <NUM_LIT> ) ; else if ( isMask ( & Def -> getOperand ( <NUM_LIT> ) ) ) SrcOp = & Def -> getOperand ( <NUM_LIT> ) ; else return false ; unsigned BitNo = countTrailingZeros ( ( uint64_t ) Mask ) ; if ( IsSigned && BitNo == SrcSize - <NUM_LIT> ) return false ; ExpectedValue <<= BitNo ; bool IsReversedCC = false ; if ( CmpValue != ExpectedValue ) { if ( ! IsReversable ) return false ; IsReversedCC = CmpValue == ( ExpectedValue ^ Mask ) ; if ( ! IsReversedCC ) return false ; } Register DefReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( IsReversedCC && ! MRI -> hasOneNonDBGUse ( DefReg ) ) return false ; for ( auto I = std :: next ( Def -> getIterator ( ) ) , E = CmpInstr . getIterator ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , & RI ) || I -> killsRegister ( <STR_LIT> , & RI ) ) return false ; } MachineOperand * SccDef = Def -> findRegisterDefOperand ( <STR_LIT> ) ; SccDef -> setIsDead ( false ) ; CmpInstr . eraseFromParent ( ) ; if ( ! MRI -> use_nodbg_empty ( DefReg ) ) { assert ( ! IsReversedCC ) ; return true ; } MachineBasicBlock * MBB = Def -> getParent ( ) ; unsigned NewOpc = ( SrcSize == <NUM_LIT> ) ? IsReversedCC ? <STR_LIT> : <STR_LIT> : IsReversedCC ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , Def , Def -> getDebugLoc ( ) , get ( NewOpc ) ) . add ( * SrcOp ) . addImm ( BitNo ) ; Def -> eraseFromParent ( ) ; return true ; } ; switch ( CmpInstr . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , true , false ) ; case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , false , false ) ; case <STR_LIT> : case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , false , true ) ; case <STR_LIT> : return optimizeCmpAnd ( <NUM_LIT> , <NUM_LIT> , true , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> } } int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - <NUM_LIT> ; NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp == ( uint16_t ) - <NUM_LIT> ) NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp != ( uint16_t ) - <NUM_LIT> ) MCOp = NMCOp ; } if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ; if ( isAsmOnlyOpcode ( MCOp ) )


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) ; unsigned Count = <NUM_LIT> ; unsigned RemovedSize = <NUM_LIT> ; while ( I != MBB . end ( ) ) { MachineBasicBlock :: iterator Next = std :: next ( I ) ; RemovedSize += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; ++ Count ; I = Next ; } if ( BytesRemoved ) * BytesRemoved


<s> Register DestSub1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * Src0RC = nullptr ; const TargetRegisterClass * Src0SubRC = nullptr ; if ( Src0 . isReg ( ) ) { Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; } const TargetRegisterClass * Src1RC = nullptr ; const TargetRegisterClass * Src1SubRC = nullptr ; if ( Src1 . isReg ( ) ) { Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; } MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; LoHalf -> getOperand ( <NUM_LIT> ) . setReg ( SCCSource ) ; Worklist . insert ( LoHalf ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; HiHalf -> getOperand ( <NUM_LIT> ) . setReg ( SCCSource ) ; Worklist . insert ( HiHalf ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1


<s> if ( Src0 . isReg ( ) ) { Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; } const TargetRegisterClass * Src1RC = nullptr ; const TargetRegisterClass * Src1SubRC = nullptr ; if ( Src1 . isReg ( ) ) { Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; } MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; LoHalf -> getOperand ( <NUM_LIT> ) . setReg ( SCCSource ) ; Worklist . insert ( LoHalf ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; HiHalf -> getOperand ( <NUM_LIT> ) . setReg ( SCCSource ) ; Worklist . insert ( HiHalf ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; legalizeOperands ( * LoHalf , MDT ) ; legalizeOperands ( * HiHalf , MDT


<s> MFI -> setHasSpilledSGPRs ( ) ; assert ( SrcReg != <STR_LIT> && <STR_LIT> ) ; assert ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( SrcReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID (

FrameIndex , TargetStackID :: SGPRSpill ) ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( Imm ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Trunc = static_cast < uint32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } default : llvm_unreachable ( <STR_LIT> )


<s> llvm :: make_range ( MachineBasicBlock :: iterator ( SCCDefInst ) , SCCDefInst . getParent ( ) -> end ( ) ) ) { if ( MI . findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) return ; if ( MI . findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) Worklist . insert ( &


<s> const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . addImm ( Src0Mods ? Src0Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src0 ) . addImm ( Src1Mods ? Src1Mods -> getImm ( ) : <NUM_LIT> ) . add ( * Src1 ) . addImm ( <NUM_LIT> ) . add ( * Src2 ) .

addImm ( Clamp ? Clamp -> getImm ( ) : <NUM_LIT> ) . addImm ( Omod ? Omod -> getImm ( ) : <NUM_LIT> ) ;


<s> break ; case <STR_LIT> : IsF16 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { int Src0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src0 ) ; const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT>


<s> return false ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset && SOffset -> isReg ( ) ) return false ; const MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; if ( SOffset ) Offset += SOffset -> getImm ( ) ; return true ; } if ( isSMRD ( LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; if ( ! OffsetImm ) return false ; const MachineOperand * SBaseReg = getNamedOperand ( LdSt , <STR_LIT> :: sbase ) ; BaseReg = SBaseReg -> getReg ( ) ; Offset = OffsetImm -> getImm


<s> break ; } case <ISA_LIT>InstrInfo :: EXECNZ : { unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: EXECZ : { unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addReg ( SReg ) ; llvm_unreachable ( <STR_LIT> ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } } else { llvm_unreachable ( <STR_LIT> )


<s> case <STR_LIT> : case <STR_LIT> : { int32_t Trunc = static_cast < int32_t > ( Imm ) ; return Trunc == Imm && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { uint32_t Trunc = static_cast < uint32_t >


<s> } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) )

. addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; DebugLoc DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Src . getReg ( ) ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , ResultReg ) . addReg ( Src . getReg ( ) ) . addReg ( TmpReg ) ; MRI . replaceRegWith ( Dest . getReg ( ) ,


<s> case <STR_LIT> : BuildMI ( * MBB , Inst , Inst . getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { movePackToVALU ( Worklist , MRI , Inst ) ; Inst . eraseFromParent ( ) ; continue ; } } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst . setDesc ( NewDesc ) ; for ( unsigned i = Inst . getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst . getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) { Inst . RemoveOperand ( i ) ; addSCCDefUsersToVALUWorklist ( Inst , Worklist ) ; } } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst . addImplicitDefUseOperands ( * Inst . getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } bool HasDst = Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isDef ( ) ; unsigned NewDstReg = <STR_LIT> ; if ( HasDst ) { unsigned DstReg = Inst . getOperand ( <NUM_LIT> )


<s> SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = <NUM_LIT> ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( FirstDst -> getReg ( ) ) ; return ( NumLoads * ( RI . getRegSizeInBits ( * DstRC ) /


<s> SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return


<s> bool llvm :: isEXECMaskConstantBetweenDefAndUses ( unsigned VReg , MachineRegisterInfo & MRI ) { assert ( MRI . isSSA ( ) && <STR_LIT> ) ; auto * TRI = MRI . getTargetRegisterInfo ( ) ; auto * DefI = MRI . getVRegDef ( VReg ) ; auto * BB = DefI -> getParent ( ) ; DenseSet < MachineInstr * > Uses ; for ( auto & Use : MRI . use_nodbg_operands ( VReg ) ) { auto * I = Use .


<s> bool <ISA_LIT>InstrInfo :: mayReadEXEC ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) const { if ( MI . isMetaInstruction ( ) ) return false ; if ( MI . isCopyLike ( ) ) { if ( ! RI . isSGPRReg ( MRI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) )


<s> if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg

( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> splitScalar64BitBCNT ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : { splitScalar64BitBFE ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; } case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst . getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { movePackToVALU ( Worklist , MRI , Inst ) ; Inst . eraseFromParent ( ) ; continue ; } } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst . setDesc


<s> case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst . eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst . getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { movePackToVALU ( Worklist , MRI , Inst ) ; Inst . eraseFromParent ( ) ; continue ; } } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst . setDesc ( NewDesc ) ; for ( unsigned i = Inst . getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst . getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) { Inst . RemoveOperand ( i ) ; addSCCDefUsersToVALUWorklist ( Inst , Worklist ) ; } } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst . addImplicitDefUseOperands ( * Inst . getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } bool HasDst = Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isDef ( ) ; unsigned NewDstReg = <STR_LIT> ; if ( HasDst


<s> MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 )


<s> DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; } BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm (


<s> bool <ISA_LIT>InstrInfo :: checkInstOffsetsDoNotOverlap ( MachineInstr * MIa , MachineInstr * MIb ) const { unsigned BaseReg0 , BaseReg1 ; int64_t Offset0 , Offset1 ; if ( getMemOpBaseRegImmOfs ( MIa , BaseReg0 , Offset0 , & RI ) && getMemOpBaseRegImmOfs ( MIb , BaseReg1 , Offset1 , & RI ) ) { if ( ! MIa -> hasOneMemOperand ( ) || ! MIb -> hasOneMemOperand ( ) ) { return false ; } unsigned Width0 = ( * MIa -> memoperands_begin (


<s> int Src0Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; if ( ! Src0 . isReg ( ) ) return nullptr ; int Src1Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src1 ) ; if ( ( OpIdx0 != static_cast < unsigned > ( Src0Idx ) || OpIdx1 != static_cast < unsigned > ( Src1Idx ) ) && ( OpIdx0 != static_cast < unsigned > ( Src1Idx ) || OpIdx1 != static_cast < unsigned > ( Src0Idx ) ) ) return nullptr ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( isVOP2 ( * MI ) || isVOPC ( * MI ) ) { const MCInstrDesc & InstrDesc = MI -> getDesc ( ) ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( * MI ) && ! isVOP3 ( * MI ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ; int Src0ModsVal = Src0Mods -> getImm ( ) ; if ( ! Src1Mods && Src0ModsVal != <NUM_LIT> ) return nullptr ; int Src1ModsVal = Src1Mods -> getImm ( ) ; assert ( ( Src1ModsVal == <NUM_LIT> ) && <STR_LIT> ) ; Src1Mods -> setImm ( Src0ModsVal ) ; Src0Mods -> setImm ( Src1ModsVal ) ; } unsigned Reg = Src0 .


<s> const MachineOperand * Src1 = getNamedOperand ( * MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src2 = getNamedOperand ( * MI , <STR_LIT> :: src2 ) ; return BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addOperand ( * Dst ) . addImm ( <NUM_LIT> ) . addOperand ( * Src0 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src1 ) . addImm ( <NUM_LIT> ) . addOperand ( * Src2 ) .

addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; unsigned Src1Reg = Src1 -> getReg ( ) ; unsigned Src1SubReg = Src1 -> getSubReg ( ) ; Src0 -> setReg ( Src1Reg ) ; Src0 -> setSubReg ( Src1SubReg ) ; Src0 -> setIsKill ( Src1 -> isKill ( ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI ) ; UseMI -> setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI -> eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> ) { UseMI -> untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( * UseMI )


<s> if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( * LdSt ) || isMTBUF ( * LdSt ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isSMRD ( * LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; if ( ! OffsetImm ) return false ; const MachineOperand * SBaseReg = getNamedOperand ( * LdSt , <STR_LIT> :: sbase ) ; BaseReg = SBaseReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isFLAT ( * LdSt ) ) { const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg ->


<s> Offset = OffsetImm -> getImm ( ) ; return true ; } const MachineOperand * Offset0Imm = getNamedOperand ( * LdSt , <STR_LIT> :: offset0 ) ; const MachineOperand * Offset1Imm = getNamedOperand ( * LdSt , <STR_LIT> :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; if ( Offset1 > Offset0 && Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt -> mayLoad ( ) ) EltSize = getOpRegClass ( * LdSt , <NUM_LIT> ) -> getSize ( ) / <NUM_LIT> ; else { assert ( LdSt -> mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = getOpRegClass ( * LdSt , Data0Idx ) -> getSize ( ) ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( * LdSt ) || isMTBUF ( * LdSt ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isSMRD ( * LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; if ( ! OffsetImm ) return false ; const MachineOperand * SBaseReg = getNamedOperand ( * LdSt , <STR_LIT> :: sbase ) ; BaseReg = SBaseReg ->


<s> uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ; Rsrc23 |= ( EltSizeValue << <STR_LIT> ) | ( UINT64_C ( <NUM_LIT> ) << <STR_LIT> ) ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS )


<s> bool <ISA_LIT>InstrInfo :: isLowLatencyInstruction ( const MachineInstr * MI ) const { unsigned Opc = MI -> getOpcode ( ) ; return isSMRD (


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MI -> modifiesRegister ( <STR_LIT> ,


<s> } break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst -> getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) { Inst -> RemoveOperand ( i ) ; addSCCDefUsersToVALUWorklist ( Inst , Worklist ) ; } } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst -> addImplicitDefUseOperands ( * Inst -> getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } bool HasDst = Inst -> getOperand ( <NUM_LIT> ) . isReg ( ) && Inst -> getOperand ( <NUM_LIT> ) . isDef ( ) ; unsigned NewDstReg = <STR_LIT> ; if ( HasDst ) { const TargetRegisterClass * NewDstRC = getDestEquivalentVGPRClass ( * Inst ) ; if ( ! NewDstRC ) continue ; unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; } legalizeOperands ( Inst ) ; if ( HasDst ) addUsersToMoveToVALUWorklist ( NewDstReg ,


<s> break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst -> getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) { Inst -> RemoveOperand ( i ) ; addSCCDefUsersToVALUWorklist ( Inst , Worklist ) ; } } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst -> addImplicitDefUseOperands ( * Inst -> getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } bool HasDst = Inst -> getOperand ( <NUM_LIT> ) . isReg ( ) && Inst -> getOperand ( <NUM_LIT> ) . isDef ( ) ; unsigned NewDstReg = <STR_LIT> ; if ( HasDst ) { const TargetRegisterClass * NewDstRC = getDestEquivalentVGPRClass ( * Inst ) ; if ( ! NewDstRC ) continue ; unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg


<s> MachineInstrBuilder MIB = BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getDestEquivalentVGPRClass ( const MachineInstr & Inst ) const { const TargetRegisterClass * NewDstRC = getOpRegClass ( Inst , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . hasAGPRs ( SrcRC ) ) { if ( RI . hasAGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; } else { if ( RI . hasVGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; } return NewDstRC ; } default : return


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . hasAGPRs ( SrcRC ) ) { if ( RI . hasAGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return


<s> case <STR_LIT> : break ; default : OpNo = I . getOperandNo ( ) ; break ; } if ( ! RI . hasVectorRegisters ( getOpRegClass ( UseMI , OpNo ) ) ) { Worklist . insert ( & UseMI ) ; do { ++ I ; } while ( I != E && I -> getParent ( ) == & UseMI ) ; } else


<s> int Op32DstIdx = <STR_LIT> ( Op32 , <STR_LIT> :: vdst ) ; if ( Op32DstIdx != - <NUM_LIT> ) { Inst32 . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { assert ( ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( * Src2 ) ; } else { copyFlagsToImplicitVCC ( * Inst32 , * Src2 ) ; } } return Inst32


<s> unsigned DstReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MachineInstr * <ISA_LIT>IF = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>END = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg ) ; IfEntry -> erase ( TI ) ; IfEntry -> insert ( IfEntry -> end ( ) , <ISA_LIT>IF ) ; IfEnd -> insert ( IfEnd -> getFirstNonPHI ( ) , <ISA_LIT>END


<s> MachineRegisterInfo & MRI = IfEntry -> getParent ( ) -> getRegInfo ( ) ; if ( Branch -> getOpcode ( ) == <STR_LIT> ) { unsigned DstReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MachineInstr * <ISA_LIT>IF = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>END = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg ) ; IfEntry -> erase ( TI


<s> MachineBasicBlock :: iterator I = LoopBB . begin ( ) ; unsigned VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; unsigned SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned CondReg0 = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned CondReg1 = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned AndCond = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned SRsrcSub0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub0 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub1 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub2 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub3 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) . addReg ( SRsrcSub0 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub1 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub2 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub3 ) . addImm ( <STR_LIT> ) ; Rsrc . setReg ( SRsrc ) ; Rsrc . setIsKill ( true ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg0 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT> ) . addReg ( VRsrc , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg1 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT> ) . addReg ( VRsrc ,


<s> static void emitLoadSRsrcFromVGPRLoop ( const <ISA_LIT>InstrInfo & TII , MachineRegisterInfo & MRI , MachineBasicBlock & OrigBB , MachineBasicBlock & LoopBB , const DebugLoc & DL , MachineOperand & Rsrc ) { MachineFunction & MF = * OrigBB . getParent ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned SaveExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned XorTermOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AndOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; MachineBasicBlock :: iterator I = LoopBB . begin ( ) ; unsigned VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; unsigned SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned CondReg0 = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned CondReg1 = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned AndCond = MRI . createVirtualRegister ( BoolXExecRC ) ; unsigned SRsrcSub0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrcSub3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub0 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub1


<s> unsigned UnusedCarry = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MRI . setRegAllocationHint ( UnusedCarry , <NUM_LIT> , RI . getVCC ( ) ) ; return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define |


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned UnusedCarry = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MRI . setRegAllocationHint ( UnusedCarry , <NUM_LIT> , RI . getVCC ( ) ) ; return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg )

. addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . hasAGPRs ( SrcRC ) ) { if ( RI . hasAGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; } else { if ( RI . hasVGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; } return


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ; if ( Opcode == <STR_LIT> || Opcode


<s> MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value


<s> unsigned <ISA_LIT>InstrInfo :: insertNE ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned SrcReg , int Value ) const { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( RI .


<s> unsigned <ISA_LIT>InstrInfo :: insertNE ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned SrcReg , int Value ) const { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( RI


<s> return ; } if ( DstSize == <NUM_LIT> && Pred == SCC_TRUE ) { MachineInstr * Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { if ( NElts % <NUM_LIT> ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; } else { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; NElts /= <NUM_LIT> ; } } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> )


<s> const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpNo ] ; assert ( MO . isImm ( ) || MO . isTargetIndex ( ) || MO . isFI ( ) || MO . isGlobal ( ) ) ; if ( OpInfo . OperandType == MCOI :: OPERAND_IMMEDIATE ) return


<s> bool HasImplicitSGPR = findImplicitSGPRRead ( MI ) != <STR_LIT> ; if ( HasImplicitSGPR && ST . getConstantBusLimit ( Opc ) <= <NUM_LIT> && Src0 . isReg ( ) && ( RI . isSGPRReg ( MRI , Src0 . getReg ( ) ) || isLiteralConstantLike ( Src0 , InstrDesc . OpInfo [ Src0Idx ] ) ) ) legalizeOpWithMove ( MI , Src0Idx ) ; if ( Opc == <STR_LIT> ) { const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Src0 . isReg ( ) && RI . isVGPR ( MRI , Src0 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src0 ) ; Src0 . ChangeToRegister ( Reg , false ) ; } if ( Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg ,


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) ; if ( RI . hasAGPRs (


<s> MachineFunction & MF = * MBB . getParent ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; unsigned SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; for ( auto & MO : MI . uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; MachineBasicBlock :: iterator J = I ++ ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ; LoopBB -> splice ( LoopBB -> begin ( ) , & MBB , J ) ; MBB . addSuccessor ( LoopBB ) ; if ( MDT ) { MDT -> addNewBlock ( LoopBB , & MBB ) ; MDT -> addNewBlock ( RemainderBB , LoopBB ) ; for ( auto & Succ : RemainderBB -> successors ( ) ) { if ( MDT -> dominates ( & MBB , Succ ) ) { MDT -> changeImmediateDominator ( Succ , RemainderBB ) ; } } } emitLoadSRsrcFromVGPRLoop ( TII , MRI , MBB , * LoopBB , DL , Rsrc ) ; MachineBasicBlock :: iterator First = RemainderBB -> begin ( ) ; BuildMI ( * RemainderBB , First , DL , TII . get ( MovExecOpc ) , Exec


<s> void <ISA_LIT>InstrInfo :: lowerScalarXnor ( SetVectorType & Worklist , MachineInstr & Inst ) const { MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; if ( ST . hasDLInsts ( ) ) { unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src0 , MRI , DL ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src1 , MRI , DL ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . add ( Src0 ) . add ( Src1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; addUsersToMoveToVALUWorklist ( NewDest , MRI , Worklist ) ; } else { bool Src0IsSGPR = Src0 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src0 . getReg ( ) ) ) ; bool Src1IsSGPR = Src1 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src1 . getReg ( ) ) ) ; MachineInstr * Xor ; unsigned Temp = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( Src0IsSGPR ) { BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Temp ) .


<s> unsigned NewSrcReg = MRI . createVirtualRegister ( VRC ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) , NewSrcReg ) . addReg ( SrcReg ) ; SrcReg = NewSrcReg ; } if ( SubRegs == <NUM_LIT> ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR ) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc (


<s> MachineBasicBlock :: iterator MII = Inst ; const TargetRegisterClass * Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; const TargetRegisterClass * Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; legalizeOperands ( * LoHalf , MDT ) ; legalizeOperands ( * HiHalf , MDT ) ; addUsersToMoveToVALUWorklist ( FullDestReg , MRI , Worklist


<s> if ( ! memOpsHaveSameBaseOperands ( BaseOps0 , BaseOps1 ) ) return false ; if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) { return false ; } unsigned Width0 = MIa . memoperands ( ) . front ( ) -> getSize ( ) ; unsigned Width1 = MIb . memoperands ( ) . front ( ) -> getSize ( ) ; return offsetsDoNotOverlap ( Width0 , Offset0


<s> int64_t Offset0 , Offset1 ; bool Offset0IsScalable , Offset1IsScalable ; if ( ! getMemOperandsWithOffset ( MIa , BaseOps0 , Offset0 , Offset0IsScalable , & RI ) || ! getMemOperandsWithOffset ( MIb , BaseOps1 , Offset1 , Offset1IsScalable , & RI ) ) return false ; if ( ! memOpsHaveSameBaseOperands ( BaseOps0 , BaseOps1 ) )


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT>


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> )


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> static unsigned getIndirectVGPRWritePseudoOpc ( unsigned VecSize ) { switch ( VecSize ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT>


<s> static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT> ; const TargetRegisterClass * EltRC = & <STR_LIT> ; const int16_t * SubIndices = Sub0_15 ; int NElts = DstSize / <NUM_LIT> ; if ( Pred == SCC_TRUE ) { if ( NElts % <NUM_LIT> ) { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; } else { SelOp = <STR_LIT> ; EltRC = & <STR_LIT> ; SubIndices = Sub0_15_64 ; NElts /= <NUM_LIT> ; } } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) ; I = MIB -> getIterator ( ) ; SmallVector < Register , <NUM_LIT> > Regs ; for ( int Idx = <NUM_LIT> ; Idx != NElts ; ++ Idx ) { Register DstElt = MRI . createVirtualRegister ( EltRC ) ; Regs . push_back ( DstElt ) ; unsigned SubIdx = SubIndices [


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) || MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( )

== <STR_LIT> || changesVGPRIndexingMode ( MI ) ;


<s> const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( DestReg . isVirtual ( ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode (


<s> auto Base1 = MO1 -> getValue ( ) ; auto Base2 = MO2 -> getValue ( ) ; if ( ! Base1 || ! Base2 ) return false ; const MachineFunction & MF = * MI1 . getParent ( ) -> getParent ( ) ; const DataLayout & DL = MF . getFunction ( ) . getParent ( ) -> getDataLayout ( ) ; Base1 = GetUnderlyingObject (


<s> if ( memOpsHaveSameBaseOperands ( BaseOps1 , BaseOps2 ) ) return true ; if ( ! MI1 . hasOneMemOperand ( ) || ! MI2 . hasOneMemOperand ( ) ) return false ; auto MO1 = * MI1 . memoperands_begin ( ) ; auto MO2 = * MI2 . memoperands_begin ( ) ; if ( MO1 -> getAddrSpace ( ) != MO2 -> getAddrSpace


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillSaveOpcode ( SpillSize ) : getVGPRSpillSaveOpcode ( SpillSize ) ; MFI -> setHasSpilledVGPRs ( ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; if ( RI . hasAGPRs


<s> if ( NonRegOp . isImm ( ) ) RegOp . ChangeToImmediate ( NonRegOp . getImm ( ) ) ; else if ( NonRegOp . isFI ( ) ) RegOp . ChangeToFrameIndex ( NonRegOp . getIndex ( ) ) ; else return nullptr ; NonRegOp . ChangeToRegister ( Reg , false , false , IsKill , IsDead ,


<s> unsigned SaveExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned XorTermOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AndOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; MachineBasicBlock :: iterator I = LoopBB . begin ( ) ; Register VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; Register CondReg0 = MRI . createVirtualRegister ( BoolXExecRC ) ; Register CondReg1 = MRI . createVirtualRegister ( BoolXExecRC ) ; Register AndCond = MRI . createVirtualRegister ( BoolXExecRC ) ; Register SRsrcSub0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrcSub1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrcSub2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrcSub3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub0 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub1 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub2 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub3 ) . addReg ( VRsrc , VRsrcUndef


<s> const MCInstrDesc & Desc = MI . getDesc ( ) ; unsigned SGPRReg = findImplicitSGPRRead ( MI ) ; if ( SGPRReg != <STR_LIT> ) return SGPRReg ; unsigned UsedSGPRs [ <NUM_LIT> ] = { <STR_LIT> } ; const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = OpIndices [ i ] ; if ( Idx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; const TargetRegisterClass * OpRC = RI . getRegClass ( Desc . OpInfo [ Idx ] . RegClass ) ; bool IsRequiredSGPR = RI . isSGPRClass ( OpRC ) ; if ( IsRequiredSGPR ) return MO . getReg ( ) ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RegRC = MRI . getRegClass ( Reg ) ; if ( RI . isSGPRClass ( RegRC ) ) UsedSGPRs


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = RS . scavengeRegister ( RI . getBoolRC ( ) , I , <NUM_LIT>


<s> unsigned <ISA_LIT>InstrInfo :: insertEQ ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned SrcReg , int Value ) const { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; Register Reg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Value ) . addReg ( SrcReg ) ; return


<s> unsigned <ISA_LIT>InstrInfo :: insertEQ ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned SrcReg , int Value ) const { MachineRegisterInfo & MRI = MBB -> getParent ( ) ->


<s> BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) , Reg ) .


<s> BranchPredicate Pred = static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; if ( Pred == VCCZ || Pred == SCC_FALSE ) { Pred = static_cast < BranchPredicate > ( - Pred ) ; std :: swap ( TrueReg , FalseReg ) ; } MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * DstRC = MRI . getRegClass ( DstReg ) ; unsigned DstSize = RI . getRegSizeInBits ( * DstRC ) ; if ( DstSize == <NUM_LIT> ) { unsigned SelOp = Pred == SCC_TRUE ? <STR_LIT> : <STR_LIT> ; MachineInstr * Select = BuildMI ( MBB , I , DL , get ( SelOp ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } if ( DstSize == <NUM_LIT> && Pred == SCC_TRUE ) { MachineInstr * Select = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ; preserveCondRegFlags ( Select -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; return ; } static const int16_t Sub0_15 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; unsigned SelOp = <STR_LIT>


<s> } case <ISA_LIT>InstrInfo :: SCC_FALSE : { Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCNZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: EXECNZ : { Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; Register SReg2 = MRI . createVirtualRegister ( RI . getBoolRC


<s> Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCNZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: EXECNZ : { Register SReg = MRI . createVirtualRegister ( BoolXExecRC ) ; Register SReg2 = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( FalseReg ) . addImm ( <NUM_LIT> ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo ::


<s> Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; RC = TRI -> getSubRegClass ( RC , MO . getSubReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) )


<s> Register DstReg = MRI . createVirtualRegister ( DstRC ) ; MachineInstr * Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . add ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ; if ( Def -> isMoveImmediate ( ) ) FoldImmediate ( * Copy , * Def , OpReg , & MRI ) ; bool ImpDef = Def -> isImplicitDef ( ) ; while ( ! ImpDef && Def && Def -> isCopy ( ) ) { Def = MRI . getUniqueVRegDef ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ImpDef = Def && Def -> isImplicitDef (


<s> MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode (


<s> unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , I , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; for ( auto & MO : MI . uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; LoopBB -> addSuccessor ( RemainderBB ) ; MachineBasicBlock :: iterator J = I ++ ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ; LoopBB -> splice ( LoopBB -> begin ( ) , & MBB , J ) ; MBB . addSuccessor ( LoopBB ) ; if ( MDT ) { MDT -> addNewBlock ( LoopBB


<s> void <ISA_LIT>InstrInfo :: lowerScalarXnor ( SetVectorType & Worklist , MachineInstr & Inst ) const { MachineBasicBlock & MBB = * Inst . getParent ( ) ; MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MII = Inst ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; if ( ST . hasDLInsts ( ) ) { Register NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src0 , MRI , DL ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src1 , MRI , DL ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . add ( Src0 ) . add ( Src1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; addUsersToMoveToVALUWorklist ( NewDest , MRI , Worklist ) ; } else { bool Src0IsSGPR = Src0 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src0


<s> if ( ST . hasDLInsts ( ) ) { Register NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src0 , MRI , DL ) ; legalizeGenericOperand ( MBB , MII , & <STR_LIT> , Src1 , MRI , DL ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . add ( Src0 ) . add ( Src1 ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; addUsersToMoveToVALUWorklist ( NewDest , MRI , Worklist ) ; } else { bool Src0IsSGPR = Src0 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src0 . getReg ( ) ) ) ; bool Src1IsSGPR = Src1 . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( Src1 . getReg ( ) ) ) ; MachineInstr * Xor ; Register Temp = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( Src0IsSGPR ) { BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Temp ) . add ( Src0 ) ; Xor = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Temp ) . add ( Src1 ) ; } else if ( Src1IsSGPR ) { BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Temp ) . add ( Src1 ) ; Xor = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . add ( Src0 ) . addReg ( Temp ) ; } else { Xor = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Temp ) . add ( Src0 ) . add ( Src1 ) ; MachineInstr * Not = BuildMI ( MBB , MII , DL ,

get ( <STR_LIT> ) , NewDest ) . addReg ( Temp ) ;


<s> BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) , NewSrcReg ) . addReg ( SrcReg ) ; SrcReg = NewSrcReg ; } if ( SubRegs == <NUM_LIT> ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { Register SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR )

. addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ;


<s> if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: sdst ) ; } else if ( isDS ( FirstLdSt ) && isDS ( SecondLdSt ) ) { FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } if ( ! FirstDst || ! SecondDst ) return false ; unsigned LoadClusterThreshold = <NUM_LIT> ; const MachineRegisterInfo & MRI = FirstLdSt . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const Register Reg = FirstDst -> getReg ( ) ; const TargetRegisterClass * DstRC = Register :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass


<s> MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , Interm ) . add ( Src0 ) . add ( Src1 ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) ; Worklist . insert ( & Op ) ; Worklist . insert ( &


<s> const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src0 = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; Register NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , Interm ) . add ( Src0 ) . add ( Src1 ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , NewDest ) . addReg ( Interm ) ; Worklist . insert ( & Op ) ; Worklist . insert ( & Not ) ; MRI . replaceRegWith ( Dest . getReg ( ) , NewDest ) ; addUsersToMoveToVALUWorklist ( NewDest , MRI ,


<s> case <STR_LIT> : MI . eraseFromParent ( ) ; break ; case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; const MachineOperand & SrcOp = MI . getOperand ( <NUM_LIT> ) ; assert ( ! SrcOp . isFPImm ( ) ) ; if ( SrcOp . isImm ( ) ) { APInt Imm ( <NUM_LIT> , SrcOp . getImm ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addImm ( Imm . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } else { assert ( SrcOp . isReg ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & SrcCond = MI . getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb ) const { assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return


<s> if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( MIa ) ) { if ( isDS ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) || isSegmentSpecificFLAT ( MIb ) ; } if ( isMUBUF ( MIa ) || isMTBUF ( MIa ) ) { if ( isMUBUF ( MIb ) || isMTBUF ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isSMRD ( MIb ) ; } if ( isSMRD ( MIa ) ) { if ( isSMRD ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( MIb ) && ! isMUBUF ( MIa ) && ! isMTBUF ( MIa ) ; } if ( isFLAT ( MIa ) ) { if ( isFLAT ( MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa ,


<s> if ( InsPt != MBB . end ( ) && ( InsPt -> getOpcode ( ) == <STR_LIT> || InsPt -> getOpcode ( ) == <STR_LIT> || InsPt -> getOpcode ( ) == <STR_LIT> ) && InsPt -> definesRegister ( Src ) ) { InsPt ++ ; return BuildMI ( MBB , InsPt , InsPt -> getDebugLoc ( ) , get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , Dst ) . addReg ( Src , <NUM_LIT>

, SrcSubReg ) . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> if ( ST . hasAddNoCarry ( ) ) return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; Register UnusedCarry = RS . scavengeRegister ( RI . getBoolRC ( ) , I , <NUM_LIT> , false ) ; if ( ! UnusedCarry . isValid ( ) ) return MachineInstrBuilder ( ) ; return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( UnusedCarry

, RegState :: Define | RegState :: Dead ) ;


<s> case <STR_LIT> : NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; break ; default : NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; } if ( ! NewDstRC ) return nullptr ; } else { if ( RI . hasVGPRs ( NewDstRC ) ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC )


<s> for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } FrameInfo . setStackID ( FrameIndex , <STR_LIT> ) ; MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores (


<s> } } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst . addImplicitDefUseOperands ( * Inst . getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } bool HasDst = Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isDef ( ) ; unsigned NewDstReg = <STR_LIT> ; if ( HasDst ) { unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) continue ; const TargetRegisterClass * NewDstRC = getDestEquivalentVGPRClass ( Inst ) ; if ( ! NewDstRC ) continue ; if ( Inst . isCopy ( ) && TargetRegisterInfo :: isVirtualRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && NewDstRC == RI . getRegClassForReg ( MRI , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { addUsersToMoveToVALUWorklist ( DstReg , MRI , Worklist ) ; MRI . replaceRegWith ( DstReg , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MRI . clearKillFlags ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Inst . getOperand ( <NUM_LIT> ) . setReg ( DstReg ) ; for ( unsigned I = Inst . getNumOperands ( ) - <NUM_LIT> ; I != <NUM_LIT> ; -- I ) Inst . RemoveOperand ( I ) ; Inst . setDesc ( get ( <STR_LIT> ) ) ; continue ; } NewDstReg = MRI .


<s> MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( NewDestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest .


<s> const TargetRegisterClass * Src0RC = Src0 . isReg ( ) ? MRI . getRegClass ( Src0 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1RC = Src1 . isReg ( ) ? MRI . getRegClass ( Src1 . getReg ( ) ) : & <STR_LIT> ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & LoHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ; MachineInstr & HiHalf = * BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister (