<s> O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O <<


<s> void <ISA_LIT>InstPrinter :: printClamp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printIfSet ( MI , OpNo ,


<s> using namespace llvm :: <STR_LIT> ; unsigned <ISA_LIT>mm16 = MI -> getOperand ( OpNo ) . getImm ( ) ; const unsigned Id = ( <ISA_LIT>mm16 & ID_MASK_ ) >> ID_SHIFT_ ; const unsigned Offset = ( <ISA_LIT>mm16 & OFFSET_MASK_ ) >> OFFSET_SHIFT_ ; const unsigned Width = ( ( <ISA_LIT>mm16 & WIDTH_M1_MASK_ ) >> WIDTH_M1_SHIFT_ ) + <NUM_LIT> ; O << <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printLiteral ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand


<s> void <ISA_LIT>InstPrinter :: printNeg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printIfSet ( MI , OpNo , O , '-'


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v'


<s> switch ( Sel ) { case <NUM_LIT> : O << 'X' ; break ; case <NUM_LIT> : O << 'Y' ; break ; case <NUM_LIT> : O << 'Z' ; break ; case <NUM_LIT> : O << 'W'


<s> void <ISA_LIT>InstPrinter :: printUpdateExecMask ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printIfSet ( MI , OpNo


<s> printIfSet ( MI , OpNo , O , <STR_LIT>


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case MCOI :: OPERAND_IMMEDIATE : printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate64 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate16 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Op . getImm ( ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> void <ISA_LIT>InstPrinter :: printOperandAndIntInputMods ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned InputModifiers = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( InputModifiers & <STR_LIT> ) O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ; if ( InputModifiers & <STR_LIT> ) O << ')' ; switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( int ) OpNo + <NUM_LIT> == <STR_LIT> ( MI -> getOpcode ( ) ,

<STR_LIT> :: src1 ) ) printDefaultVccOperand ( OpNo , STI , O ) ;


<s> return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) .


<s> O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs =


<s> if ( ! ! ( Ops [ I ] & Mod ) != DefaultValue ) return false ; } if ( HasDstSel && ( Ops [ <NUM_LIT> ] & <STR_LIT> ) != <NUM_LIT> )


<s> Ops [ NumOps ++ ] = MI -> getOperand ( Idx ) . getImm ( ) ; } const bool HasDstSel = NumOps > <NUM_LIT> && Mod == <STR_LIT> && MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ; if ( allOpsDefaultValue ( Ops , NumOps , Mod , HasDstSel ) ) return ; O << Name ; for ( int I = <NUM_LIT> ; I


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains


<s> O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O <<


<s> O << formatDec ( static_cast < int16_t > ( MI -> getOperand ( OpNo )


<s> if ( ! ! ( Ops [ I ] & Mod ) != DefaultValue ) return false ; } if ( HasDstSel && ( Ops [ <NUM_LIT> ] & <STR_LIT> ) != <NUM_LIT> ) return false ; return true


<s> void <ISA_LIT>InstPrinter :: printAbs ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo


<s> void <ISA_LIT>InstPrinter :: printAddr64 ( const MCInst * MI , unsigned OpNo


<s> O << <STR_LIT> ; printU4ImmOperand ( MI , OpNo , STI


<s> void <ISA_LIT>InstPrinter :: printBoundCtrl ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if (


<s> void <ISA_LIT>InstPrinter :: printClamp ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo


<s> void <ISA_LIT>InstPrinter :: printClamp ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo ,


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) )


<s> void <ISA_LIT>InstPrinter :: printD16 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printNamedBit ( MI , OpNo , O


<s> void <ISA_LIT>InstPrinter :: printD16 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream


<s> void <ISA_LIT>InstPrinter :: printDA ( const MCInst * MI , unsigned OpNo ,

const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> void <ISA_LIT>InstPrinter :: printDA ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O <<


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm <= DppCtrl :: QUAD_PERM_LAST ) { O << <STR_LIT> ; O << formatDec ( Imm & <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ']' ; } else if ( ( Imm >= DppCtrl :: ROW_SHL_FIRST ) && ( Imm <= DppCtrl :: ROW_SHL_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_SHR_FIRST ) && ( Imm <= DppCtrl :: ROW_SHR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_ROR_FIRST ) && ( Imm <= DppCtrl :: ROW_ROR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == DppCtrl :: WAVE_SHL1 ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROL1 ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_SHR1 ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROR1 ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_MIRROR ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_HALF_MIRROR ) { O <<


<s> void <ISA_LIT>InstPrinter :: printExpCompr ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo


<s> void <ISA_LIT>InstPrinter :: printExpSrc1 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printExpSrcN < <NUM_LIT> > ( MI ,


<s> printExpSrcN < <NUM_LIT> > ( MI , OpNo , STI ,


<s> void <ISA_LIT>InstPrinter :: printExpSrc3 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printExpSrcN < <NUM_LIT> > ( MI , OpNo , STI ,


<s> void <ISA_LIT>InstPrinter :: printExpSrc3 ( const MCInst * MI , unsigned OpNo ,


<s> else if ( Tgt == <NUM_LIT> ) O << <STR_LIT> ; else if ( Tgt >= <NUM_LIT> && Tgt <= <NUM_LIT> ) O << <STR_LIT> << Tgt - <NUM_LIT> ; else if ( Tgt >= <NUM_LIT> && Tgt <= <NUM_LIT> ) O << <STR_LIT> << Tgt - <NUM_LIT> ; else { O << <STR_LIT>


<s> if ( MI -> getOperand ( OpNo ) . getImm (


<s> void <ISA_LIT>InstPrinter :: printFORMAT ( const MCInst * MI , unsigned OpNo ,


<s> void <ISA_LIT>InstPrinter :: printFORMAT ( const MCInst * MI , unsigned OpNo , const

MCSubtargetInfo & STI , raw_ostream & O ) {


<s> void <ISA_LIT>InstPrinter :: printGDS ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printNamedBit ( MI , OpNo , O


<s> printNamedBit ( MI , OpNo , O , <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printGLC ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI


<s> void <ISA_LIT>InstPrinter :: printHigh ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O


<s> void <ISA_LIT>InstPrinter :: printIdxen ( const MCInst * MI , unsigned


<s> void <ISA_LIT>InstPrinter :: printIfSet ( const MCInst * MI , unsigned OpNo , raw_ostream & O , char Asm ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; assert ( Op . isImm (


<s> else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm ==


<s> else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) O << <STR_LIT> ; else O << formatHex ( static_cast <


<s> int64_t <ISA_LIT>mm = static_cast < int64_t > ( Imm ) ; if ( <ISA_LIT>mm >= - <NUM_LIT> && <ISA_LIT>mm <= <NUM_LIT> ) { O << <ISA_LIT>mm ; return ; } if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ,


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { O . flush ( ) ; printInstruction ( MI , O ) ; printAnnotation ( O , Annot


<s> void <ISA_LIT>InstPrinter :: printInterpAttr ( const MCInst * MI , unsigned OpNum ,


<s> unsigned Chan = MI -> getOperand ( OpNum ) . getImm ( ) ; O << '.' << <STR_LIT> [ Chan &


<s> void <ISA_LIT>InstPrinter :: printInterpAttrChan ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Chan = MI -> getOperand ( OpNum ) . getImm (


<s> <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo ,


<s> <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo , O , <STR_LIT> ,


<s> int64_t Imm = Op . getImm ( ) ; O << Imm << '(' << BitsToFloat ( Imm ) << ')' ; } if ( Op .


<s> void <ISA_LIT>InstPrinter :: printLWE ( const MCInst * MI , unsigned OpNo ,


<s> printNamedBit ( MI , OpNo , O , <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printOperand ( MI , OpNo


<s>
void
<ISA_LIT>InstPrinter
::
printNamedBit
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
,
StringRef
BitName
)
{
if
(
MI
->
getOperand
(
OpNo
)
.
getImm
(
)
)
{
O
<<
' '


<s> <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo


<s> void <ISA_LIT>InstPrinter :: printNegHi ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printPackedModifier ( MI , <STR_LIT> ,


<s> void <ISA_LIT>InstPrinter :: printNegLo ( const MCInst * MI , unsigned OpNo ,


<s> void <ISA_LIT>InstPrinter :: printOffset ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { uint16_t Imm = MI -> getOperand ( OpNo ) .


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU8ImmDecOperand ( MI , OpNo


<s> void <ISA_LIT>InstPrinter :: printOffset1 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU8ImmDecOperand ( MI , OpNo


<s> O << ( ( OpNo == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; printS13ImmDecOperand ( MI ,


<s> void <ISA_LIT>InstPrinter :: printOMod<ISA_LIT> ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { int Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm == <STR_LIT> ) O << <STR_LIT> ; else if ( Imm == <STR_LIT>


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case <STR_LIT> : break ; default : O << getRegisterName ( Op . getReg ( ) ) ; break ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op .


<s> NegMnemo = Op . isImm ( ) || Op . isFPImm ( ) ; } if ( NegMnemo ) { O << <STR_LIT> ; } else { O << '-' ; } } if ( InputModifiers & <STR_LIT> ) O << '|' ; printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ; if ( InputModifiers & <STR_LIT> ) O << '|' ; if ( NegMnemo


<s> unsigned InputModifiers = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( InputModifiers & <STR_LIT> ) O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ; if ( InputModifiers & <STR_LIT> )


<s> printPackedModifier ( MI , <STR_LIT> , <STR_LIT>


<s> Ops [ NumOps ++ ] = MI -> getOperand ( Idx ) . getImm ( ) ; } const bool HasDstSel = NumOps > <NUM_LIT> && Mod == <STR_LIT> && MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ; const bool IsPacked = MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ; if ( allOpsDefaultValue ( Ops , NumOps , Mod , IsPacked , HasDstSel ) ) return ; O << Name ; for ( int I = <NUM_LIT> ; I < NumOps ; ++ I ) { if ( I != <NUM_LIT> ) O << ',' ; O << ! ! ( Ops [ I ] & Mod ) ; } if ( HasDstSel ) { O << ',' << ! ! ( Ops [ <NUM_LIT> ] & <STR_LIT> ) ; } O << ']'


<s> void <ISA_LIT>InstPrinter :: printR128A16 ( const MCInst * MI , unsigned OpNo , const


<s> <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo ,


<s> void <ISA_LIT>InstPrinter :: printS13ImmDecOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << formatDec ( SignExtend32 < <NUM_LIT> > ( MI -> getOperand ( OpNo


<s> void <ISA_LIT>InstPrinter :: printSDWADstSel ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { O <<


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( Imm ) { case DstUnused :: UNUSED_PAD : O


<s> using namespace llvm :: <STR_LIT> ; unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( Imm ) { case SdwaSel :: BYTE_0 : O << <STR_LIT> ; break ; case SdwaSel :: BYTE_1 : O << <STR_LIT> ; break ; case SdwaSel :: BYTE_2 : O << <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printSDWASrc0Sel ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream


<s> void <ISA_LIT>InstPrinter :: printSDWASrc1Sel ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printSDWASel ( MI , OpNo , O


<s> do { if ( Id == ID_INTERRUPT ) { if ( ( <ISA_LIT>mm16 & ~ ID_MASK_ ) != <NUM_LIT> ) break ; O << <STR_LIT> << IdSymbolic [ Id ] << ')' ; return ; } if ( Id == ID_GS || Id == ID_GS_DONE ) { if ( ( <ISA_LIT>mm16 & ~ ( ID_MASK_ | OP_GS_MASK_ | STREAM_ID_MASK_ ) ) != <NUM_LIT> ) break ; const unsigned OpGs = ( <ISA_LIT>mm16 & OP_GS_MASK_ ) >> OP_SHIFT_ ; const unsigned StreamId = ( <ISA_LIT>mm16 & STREAM_ID_MASK_ ) >> STREAM_ID_SHIFT_ ; if ( OpGs == OP_GS_NOP && Id != ID_GS_DONE ) break ; if ( OpGs == OP_GS_NOP && StreamId != <NUM_LIT> ) break ; O << <STR_LIT> << IdSymbolic [ Id ] << <STR_LIT> << OpGsSymbolic [ OpGs ] ; if ( OpGs != OP_GS_NOP ) { O << <STR_LIT> << StreamId ; } O << ')' ; return ; } if ( Id == ID_SYSMSG


<s> void <ISA_LIT>InstPrinter :: printSMRDLiteralOffset ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream


<s> void <ISA_LIT>InstPrinter :: printSMRDLiteralOffset ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI ,


<s> printU32ImmOperand ( MI , OpNo , STI ,


<s> void <ISA_LIT>InstPrinter :: printSMRDOffset8 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printU32ImmOperand ( MI , OpNo , STI


<s> uint16_t OrMask = ( Imm >> BITMASK_OR_SHIFT ) & BITMASK_MASK ; uint16_t XorMask = ( Imm >> BITMASK_XOR_SHIFT ) & BITMASK_MASK ; if ( AndMask == BITMASK_MAX && OrMask == <NUM_LIT> && countPopulation ( XorMask ) == <NUM_LIT> ) { O << <STR_LIT> << IdSymbolic [ ID_SWAP ] ; O << <STR_LIT> ; O << formatDec ( XorMask ) ; O << <STR_LIT> ; } else if ( AndMask == BITMASK_MAX && OrMask == <NUM_LIT> && XorMask > <NUM_LIT> && isPowerOf2_64 ( XorMask + <NUM_LIT> ) ) { O << <STR_LIT> << IdSymbolic [ ID_REVERSE ] ; O << <STR_LIT> ; O << formatDec ( XorMask + <NUM_LIT> ) ; O << <STR_LIT> ; } else { uint16_t GroupSize = BITMASK_MAX - AndMask + <NUM_LIT> ; if ( GroupSize > <NUM_LIT> && isPowerOf2_64 ( GroupSize ) && OrMask < GroupSize && XorMask == <NUM_LIT> ) { O << <STR_LIT> << IdSymbolic [ ID_BROADCAST ] ; O << <STR_LIT> ; O << formatDec ( GroupSize ) ; O << <STR_LIT> ; O << formatDec ( OrMask ) ; O << <STR_LIT> ; } else { O << <STR_LIT> << IdSymbolic [ ID_BITMASK_PERM ] ; O << <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printTFE ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printNamedBit ( MI , OpNo


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { int64_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) O << formatHex ( static_cast < uint64_t > ( Imm & <NUM_LIT> ) ) ; else printU32ImmOperand ( MI , OpNo , STI ,


<s> void <ISA_LIT>InstPrinter :: printU4ImmDecOperand ( const MCInst * MI , unsigned OpNo ,


<s> O << formatHex ( MI -> getOperand ( OpNo


<s> void <ISA_LIT>InstPrinter :: printUpdateExecMask ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo , O ,


<s> <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo


<s> void <ISA_LIT>InstPrinter :: printUpdatePred ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { <ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo ,


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Val == <NUM_LIT> ) { O << <STR_LIT> ; return ; } if ( Val & VGPRIndexMode :: DST_ENABLE ) O << <STR_LIT> ; if ( Val & VGPRIndexMode :: SRC0_ENABLE ) O << <STR_LIT> ; if ( Val & VGPRIndexMode ::


<s> void <ISA_LIT>InstPrinter :: printVINTRPDst ( const MCInst * MI , unsigned OpNo

, const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> void <ISA_LIT>InstPrinter :: printVOPDst ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else O <<


<s>
<STR_LIT>
ISA
=
<STR_LIT>
(
STI
.
getCPU
(
)
)
;
unsigned
<ISA_LIT>mm16
=
MI
->
getOperand
(
OpNo
)
.
getImm
(
)
;
unsigned
Vmcnt
,
Expcnt
,
Lgkmcnt
;
decodeWaitcnt
(
ISA
,
<ISA_LIT>mm16
,
Vmcnt
,
Expcnt
,
Lgkmcnt
)
;
bool
NeedSpace
=
false
;
if
(
Vmcnt
!=
getVmcntBitMask
(
ISA
)
)
{
O
<<
<STR_LIT>
<<
Vmcnt
<<
')'
;
NeedSpace
=
true
;
}
if
(
Expcnt
!=
getExpcntBitMask
(
ISA
)
)
{
if
(
NeedSpace
)
O
<<
' '
;
O
<<
<STR_LIT>
<<
Expcnt
<<
')'
;
NeedSpace
=
true
;
}
if
(
Lgkmcnt
!=
getLgkmcntBitMask
(
ISA
)
)
{
if
(
NeedSpace
)
O
<<
' '
;
O
<<
<STR_LIT>
<<
Lgkmcnt


<s>
unsigned
Vmcnt
,
Expcnt
,
Lgkmcnt
;
decodeWaitcnt
(
ISA
,
<ISA_LIT>mm16
,
Vmcnt
,
Expcnt
,
Lgkmcnt
)
;
bool
NeedSpace
=
false
;
if
(
Vmcnt
!=
getVmcntBitMask
(
ISA
)
)
{
O
<<
<STR_LIT>
<<
Vmcnt
<<
')'
;
NeedSpace
=
true
;
}
if
(
Expcnt
!=
getExpcntBitMask
(
ISA
)
)
{
if
(
NeedSpace
)
O
<<
' '
;
O
<<
<STR_LIT>
<<
Expcnt
<<
')'
;
NeedSpace
=


<s> void <ISA_LIT>InstPrinter :: printWrite ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS <<


<s> case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } StringRef RegName ( getRegisterName ( RegNo ) ) ; if ( ! Keep16BitSuffixes ) if ( ! RegName . consume_back ( <STR_LIT> ) ) RegName . consume_back


<s> O << formatHex ( MI -> getOperand ( OpNo ) .


<s> O << formatHex ( MI -> getOperand ( OpNo ) . getImm ( )


<s> O << <STR_LIT> << formatDec ( Imm & <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { O << ',' << formatDec ( ( Imm >> ( <NUM_LIT> * i ) ) & <NUM_LIT> ) ; } O <<


<s> void <ISA_LIT>InstPrinter :: printDPP8 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! <STR_LIT> ( STI ) ) llvm_unreachable ( <STR_LIT> ) ; unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; O << <STR_LIT> << formatDec (


<s> void <ISA_LIT>InstPrinter :: printExpCompr ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printNamedBit ( MI , OpNo , O


<s> void <ISA_LIT>InstPrinter :: printExpSrc0 ( const MCInst * MI , unsigned

OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> void <ISA_LIT>InstPrinter :: printExpSrc1 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printExpSrcN ( MI , OpNo , STI , O ,


<s> void <ISA_LIT>InstPrinter :: printExpSrc1 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printExpSrcN ( MI , OpNo ,


<s> void <ISA_LIT>InstPrinter :: printExpSrc2 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream &


<s> void <ISA_LIT>InstPrinter :: printExpSrc3 ( const MCInst * MI , unsigned OpNo


<s> unsigned Opc = MI -> getOpcode ( ) ; int EnIdx = <STR_LIT> ( Opc , <STR_LIT> :: en ) ; unsigned En = MI -> getOperand ( EnIdx ) . getImm ( ) ; int ComprIdx = <STR_LIT> ( Opc , <STR_LIT> :: compr ) ; if ( MI -> getOperand ( ComprIdx ) . getImm ( ) ) OpNo = OpNo - N + N / <NUM_LIT> ; if ( En & ( <NUM_LIT> << N ) ) printRegOperand ( MI -> getOperand ( OpNo


<s>
unsigned
Id
=
MI
->
getOperand
(
OpNo
)
.
getImm
(
)
&
(
(
<NUM_LIT>
<<
<NUM_LIT>
)
<NUM_LIT>
)
;
int
Index
;
StringRef
TgtName
;
if
(
getTgtName
(
Id
,
TgtName
,
Index
)
&&
isSupportedTgtId
(
Id
,
STI
)
)
{
O
<<
' '
<<
TgtName
;
if
(
Index
>=
<NUM_LIT>
)
O
<<
Index
;
}


<s> void <ISA_LIT>InstPrinter :: printHigh ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo &


<s> void <ISA_LIT>InstPrinter :: printImmediateInt16 ( uint32_t Imm , const MCSubtargetInfo & STI , raw_ostream & O ) { int16_t <ISA_LIT>mm = static_cast < int16_t > ( Imm ) ; if ( isInlinableIntLiteral ( <ISA_LIT>mm ) ) { O << <ISA_LIT>mm ; } else { uint64_t Imm16 = static_cast < uint16_t


<s> void <ISA_LIT>InstPrinter :: printOffset ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { uint16_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm != <NUM_LIT>


<s> if ( InputModifiers & <STR_LIT> ) { if ( OpNo + <NUM_LIT> < MI -> getNumOperands ( ) && ( InputModifiers & <STR_LIT> ) == <NUM_LIT> ) { const MCOperand & Op = MI -> getOperand ( OpNo + <NUM_LIT> ) ; NegMnemo = Op . isImm ( ) || Op . isDFPImm ( ) ; } if ( NegMnemo ) { O << <STR_LIT> ; }


<s> if ( ! MsgName . empty ( ) && isValidMsgOp ( MsgId , OpId , STI ) && isValidMsgStream ( MsgId , OpId , StreamId , STI ) ) { O << <STR_LIT> << MsgName ; if ( msgRequiresOp ( MsgId ) ) { O << <STR_LIT> << getMsgOpName ( MsgId , OpId ) ; if ( msgSupportsStream ( MsgId , OpId ) ) { O << <STR_LIT> << StreamId ; } } O << ')' ; } else if ( encodeMsg ( MsgId , OpId , StreamId ) == Imm16 ) { O << <STR_LIT> << MsgId << <STR_LIT> << OpId


<s> void <ISA_LIT>InstPrinter :: printSymbolicFormat ( const MCInst * MI , const MCSubtargetInfo & STI , raw_ostream & O ) { using namespace llvm :: <STR_LIT> ; int OpNo = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: format ) ; assert ( OpNo != - <NUM_LIT> ) ; unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( <STR_LIT> ( STI ) ) { if ( Val == UFMT_DEFAULT ) return ; if ( isValidUnifiedFormat (


<s> unsigned <ISA_LIT>mm16 = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Vmcnt , Expcnt , Lgkmcnt ; decodeWaitcnt ( ISA , <ISA_LIT>mm16 , Vmcnt , Expcnt , Lgkmcnt ) ; bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask ( ISA ) ; bool IsDefaultExpcnt = Expcnt == getExpcntBitMask ( ISA ) ; bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask ( ISA ) ; bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt ; bool NeedSpace = false ; if ( ! IsDefaultVmcnt || PrintAll ) { O << <STR_LIT> <<


<s> if ( ( Imm & CPol :: DLC ) && <STR_LIT> ( STI ) ) O << <STR_LIT> ; if ( ( Imm & CPol :: SCC ) && <STR_LIT> ( STI ) ) O << <STR_LIT> ; if ( Imm & ~ CPol :: ALL ) O


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case MCOI :: OPERAND_IMMEDIATE : printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate64 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediateInt16 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate16 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Op . getImm ( ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; } if ( OpTy == <STR_LIT> ) { printImmediate16 ( static_cast < uint16_t > ( Op . getImm ( ) ) , STI , O ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : printImmediateInt16 ( static_cast < uint16_t > ( Op . getImm ( ) ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isDFPImm ( ) ) { double Value = bit_cast < double > ( Op . getDFPImm ( ) ) ; if ( Value == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Value ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Value ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case <STR_LIT> : break ; default : O << getRegisterName ( Op . getReg ( ) ) ; break ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op . isDFPImm ( ) ) { if ( Op . getDFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { O << bit_cast < double > ( Op . getDFPImm ( ) ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT>


<s> default : printRegOperand ( Op . getReg ( ) , O , MRI ) ; break ; } } else if ( Op . isImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; switch ( Desc . OpInfo [ OpNo ] . OperandType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case MCOI :: OPERAND_IMMEDIATE : printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate64 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate16 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID )


<s> if ( InputModifiers & <STR_LIT> ) O << '|' ; printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ; if ( InputModifiers & <STR_LIT>


<s> if ( InputModifiers & <STR_LIT> ) O << '-' ; if ( InputModifiers & <STR_LIT> ) O << '|' ; printOperand ( MI , OpNo + <NUM_LIT>


<s> static const std :: array < const char * , <NUM_LIT> > InstSkips = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned <ISA_LIT>mm16 = MI -> getOperand ( OpNo ) . getImm ( ) ; const char * Prefix = <STR_LIT> ; unsigned Value = <ISA_LIT>mm16 & <NUM_LIT> ; if ( Value ) { const char * Name = Value < InstIds . size ( ) ? InstIds [ Value ] : BadInstId ; O << Prefix << <STR_LIT> << Name << ')' ; Prefix = <STR_LIT> ; } Value = ( <ISA_LIT>mm16 >> <NUM_LIT> ) & <NUM_LIT> ; if ( Value ) { const char * Name = Value < InstSkips . size ( ) ? InstSkips [ Value ] : BadInstSkip ; O << Prefix << <STR_LIT> << Name << ')' ; Prefix = <STR_LIT> ; } Value = ( <ISA_LIT>mm16 >> <NUM_LIT> ) & <NUM_LIT> ; if ( Value ) { const char * Name = Value < InstIds . size (


<s> void <ISA_LIT>InstPrinter :: printSMEMOffsetMod ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { O <<


<s> void <ISA_LIT>InstPrinter :: printWaitEXP ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { uint8_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm != <NUM_LIT>


<s> O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs =


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned


<s> void <ISA_LIT>InstPrinter :: printBankMask ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT>


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm ) { O <<


<s> if ( Imm <= <NUM_LIT> ) { O << <STR_LIT> ; O << formatDec ( Imm & <NUM_LIT> ) << <STR_LIT> ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; assert ( Op . isImm ( ) || Op . isExpr ( ) ) ; if ( Op . isImm ( ) ) { int64_t Imm = Op .


<s> void <ISA_LIT>InstPrinter :: printOffset0 ( const MCInst * MI , unsigned OpNo , raw_ostream


<s> void <ISA_LIT>InstPrinter :: printSDWADstUnused ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( Imm ) { case <NUM_LIT> : O


<s> void <ISA_LIT>InstPrinter :: printSDWASrc1Sel ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O <<


<s> void <ISA_LIT>InstPrinter :: printSMRDLiteralOffset ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printU32ImmOperand ( MI , OpNo , O


<s> void <ISA_LIT>InstPrinter :: printSMRDOffset ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printU32ImmOperand ( MI , OpNo , O


<s> void <ISA_LIT>InstPrinter :: printVOPDst ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MII . get ( MI -> getOpcode ( ) ) .


<s> if ( OpNo > <NUM_LIT> ) O << <STR_LIT> ; printRegOperand ( <STR_LIT> , O , MRI ) ; if ( OpNo == <NUM_LIT>


<s> printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( int ) OpNo == <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src1 ) ) printDefaultVccOperand ( OpNo ,


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> if ( <STR_LIT> ( STI ) ) { O << formatDec ( SignExtend32 < <NUM_LIT> > ( MI -> getOperand ( OpNo ) . getImm (


<s> void <ISA_LIT>InstPrinter :: printS13ImmDecOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( <STR_LIT> ( STI ) ) { O << formatDec ( SignExtend32 < <NUM_LIT> > ( MI -> getOperand ( OpNo ) .


<s> const unsigned Id = <ISA_LIT>mm16 & ID_MASK_ ; do { if ( Id == ID_INTERRUPT || ( Id == ID_GS_ALLOC_REQ && ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) ) { if ( ( <ISA_LIT>mm16 & ~ ID_MASK_ ) != <NUM_LIT> ) break ; O << <STR_LIT> << IdSymbolic [ Id ] << ')' ; return ; } if ( Id == ID_GS || Id == ID_GS_DONE ) { if ( ( <ISA_LIT>mm16 & ~ ( ID_MASK_ | OP_GS_MASK_ | STREAM_ID_MASK_ ) ) != <NUM_LIT> ) break ; const unsigned OpGs = ( <ISA_LIT>mm16 & OP_GS_MASK_ ) >> OP_SHIFT_ ; const unsigned StreamId = ( <ISA_LIT>mm16 & STREAM_ID_MASK_ ) >> STREAM_ID_SHIFT_ ; if ( OpGs == OP_GS_NOP && Id != ID_GS_DONE ) break ; if ( OpGs == OP_GS_NOP && StreamId != <NUM_LIT> ) break ; O << <STR_LIT> << IdSymbolic [ Id ] << <STR_LIT> << OpGsSymbolic [ OpGs ] ; if ( OpGs != OP_GS_NOP ) { O << <STR_LIT> << StreamId ; } O << ')' ; return ; } if ( Id == ID_SYSMSG


<s> void <ISA_LIT>InstPrinter :: printVOPDst ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( OpNo == <NUM_LIT> ) { if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; } printOperand ( MI , OpNo , STI , O ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT>


<s> O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ']' ; } else if ( ( Imm >= DppCtrl :: ROW_SHL_FIRST ) && ( Imm <= DppCtrl :: ROW_SHL_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_SHR_FIRST ) && ( Imm <= DppCtrl :: ROW_SHR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_ROR_FIRST ) && ( Imm <= DppCtrl :: ROW_ROR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == DppCtrl :: WAVE_SHL1 ) { if ( <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROL1 ) { if ( <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_SHR1 ) { if ( <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printAbs ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printIfSet ( MI , OpNo , O


<s> if ( Imm <= <NUM_LIT> ) { O << <STR_LIT> ; O << formatDec ( Imm & <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ']' ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O <<


<s> O << <STR_LIT> ; O << formatDec ( Imm & <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ',' ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << ']' ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printNamedBit ( const MCInst * MI , unsigned OpNo , raw_ostream & O


<s> if ( InputModifiers & <STR_LIT> ) O << '|' ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ; if ( InputModifiers & <STR_LIT>


<s> void <ISA_LIT>InstPrinter :: printOperandAndIntInputMods ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned InputModifiers = MI -> getOperand (


<s> unsigned InputModifiers = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( InputModifiers & <STR_LIT> ) O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ; if ( InputModifiers & <STR_LIT> )


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; default : break ; } unsigned RegIdx = MRI . getEncodingValue ( reg ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg


<s> NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT>


<s> void <ISA_LIT>InstPrinter :: printRel ( const MCInst * MI , unsigned OpNo ,


<s> void <ISA_LIT>InstPrinter :: printRel ( const MCInst * MI , unsigned


<s> unsigned En = MI -> getOperand ( EnIdx ) . getImm ( ) ; if ( En & ( <NUM_LIT> << N ) ) printRegOperand ( MI -> getOperand ( OpNo ) . getReg ( ) ,


<s> } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case <STR_LIT> : break ; default : printRegOperand ( Op . getReg ( ) , O , MRI ) ; break ; } } else if ( Op . isImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; if ( RCID != - <NUM_LIT> ) { const MCRegisterClass & ImmRC = MRI . getRegClass ( RCID ) ; if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate32 ( Op . getImm ( ) , O ) ; else if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate64 ( Op . getImm ( ) , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( Desc . OpInfo [ OpNo ] . OperandType == MCOI :: OPERAND_IMMEDIATE ) { printImmediate32 ( Op . getImm ( ) , O ) ; } else { O << formatDec ( Op . getImm ( ) ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; const MCRegisterClass & ImmRC = MRI . getRegClass ( Desc . OpInfo [ OpNo ] . RegClass ) ; if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , O ) ; else if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( )


<s> default : printRegOperand ( Op . getReg ( ) , O , MRI ) ; break ; } } else if ( Op . isImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; if ( RCID != - <NUM_LIT> ) { const MCRegisterClass & ImmRC = MRI . getRegClass ( RCID ) ; if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate32 ( Op . getImm ( ) , O ) ; else if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate64 ( Op . getImm ( ) , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( Desc . OpInfo [ OpNo ]

. OperandType == MCOI :: OPERAND_IMMEDIATE ) {


<s> if ( ! <STR_LIT> ( STI ) ) llvm_unreachable ( <STR_LIT> ) ; unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; O << <STR_LIT> << formatDec ( Imm & <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i <


<s> } else if ( ( Imm >= DppCtrl :: ROW_ROR_FIRST ) && ( Imm <= DppCtrl :: ROW_ROR_LAST ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == DppCtrl :: WAVE_SHL1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROL1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_SHR1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: WAVE_ROR1 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_MIRROR ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: ROW_HALF_MIRROR ) { O << <STR_LIT> ; } else if ( Imm == DppCtrl :: BCAST15 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( Imm == DppCtrl :: BCAST31 ) { if ( ! <STR_LIT> ( STI ) && ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; } else if ( ( Imm >= DppCtrl :: ROW_SHARE_FIRST ) && ( Imm <= DppCtrl :: ROW_SHARE_LAST ) ) { if ( ! <STR_LIT> ( STI ) ) { O << <STR_LIT> ; return ; } O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= DppCtrl :: ROW_XMASK_FIRST ) && ( Imm <= DppCtrl :: ROW_XMASK_LAST ) ) { if ( ! <STR_LIT> ( STI ) ) { O <<


<s> void <ISA_LIT>InstPrinter :: printFlatOffset ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { uint16_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm != <NUM_LIT> ) { O << <STR_LIT> ; const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; bool IsFlatSeg = ! ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) ; if ( IsFlatSeg ) { printU16ImmDecOperand ( MI , OpNo , O ) ; } else { if ( <STR_LIT> ( STI ) ) { O << formatDec ( SignExtend32 < <NUM_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ) ; }


<s> case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Op . getImm ( ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; } if ( OpTy == <STR_LIT> ) { printImmediate16 ( static_cast < uint16_t > ( Op . getImm ( ) ) , STI , O ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : printImmediateInt16 ( static_cast < uint16_t > ( Op . getImm ( ) ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O <<


<s> else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; O << getRegisterName ( RegNo , AltName


<s> else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) AltName = <STR_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) || MRI . getRegClass ( <STR_LIT> ) .


<s> break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case


<s> O << <ISA_LIT>mm ; return ; } if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) O << <STR_LIT> ; else if ( Imm == <NUM_LIT> ) { assert ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ; O <<


<s> if ( isInlinableIntLiteral ( <ISA_LIT>mm ) ) O << <ISA_LIT>mm ; else O << formatHex ( static_cast < uint64_t >


<s> if ( MI -> getOperand ( OpNo ) . getImm ( )


<s> void <ISA_LIT>InstPrinter :: printClamp<ISA_LIT> ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) )


<s> unsigned CT = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( CT


<s> if ( Imm != <NUM_LIT> ) { O << <STR_LIT> ; printU16ImmDecOperand ( MI ,


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU8ImmDecOperand ( MI , OpNo , O


<s> void <ISA_LIT>InstPrinter :: printGDS ( const MCInst * MI , unsigned OpNo


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) )


<s> if ( MI -> getOperand ( OpNo ) . getImm (


<s> void <ISA_LIT>InstPrinter :: printIfSet ( const MCInst * MI , unsigned OpNo ,

raw_ostream & O , StringRef Asm , StringRef Default ) {


<s> int32_t <ISA_LIT>mm = static_cast < int32_t > ( Imm ) ; if ( <ISA_LIT>mm >= - <NUM_LIT> && <ISA_LIT>mm <= <NUM_LIT> ) { O << <ISA_LIT>mm ; return ; } if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) )


<s> return ; } if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == FloatToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else O << formatHex ( static_cast < uint64_t > (


<s> else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) )


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { OS . flush ( ) ; printInstruction ( MI ,


<s> unsigned Imm = MI -> getOperand ( OpNum ) . getImm ( ) ; if ( Imm == <NUM_LIT> ) { O <<


<s> int KCacheMode = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( KCacheMode > <NUM_LIT> ) { int KCacheBank = MI -> getOperand ( OpNo - <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> << KCacheBank


<s> void <ISA_LIT>InstPrinter :: printLast ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printIfSet ( MI , OpNo , O , <STR_LIT> ,


<s> int32_t Imm = MI -> getOperand ( OpNo )


<s> void <ISA_LIT>InstPrinter :: printLiteral ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { int32_t Imm = MI -> getOperand ( OpNo ) .


<s> void <ISA_LIT>InstPrinter :: printNeg ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printIfSet ( MI , OpNo , O


<s> if ( MI -> getOperand ( OpNo ) . getImm


<s> void <ISA_LIT>InstPrinter :: printOMOD ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { switch ( MI -> getOperand ( OpNo ) . getImm ( ) ) { default : break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT>


<s> if ( Imm == <STR_LIT> ) O << <STR_LIT> ; else if ( Imm == <STR_LIT> ) O << <STR_LIT> ; else if ( Imm == <STR_LIT> )


<s> void <ISA_LIT>InstPrinter :: printOMod<ISA_LIT> ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { int Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm == <STR_LIT>


<s> if ( InputModifiers & <STR_LIT> ) O << '-' ; if ( InputModifiers & <STR_LIT> ) O << '|' ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ; if ( InputModifiers & <STR_LIT> ) O


<s> return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; default : break ; } char Type ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type = 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { Type =


<s> void <ISA_LIT>InstPrinter :: printRel ( const MCInst * MI


<s> void <ISA_LIT>InstPrinter :: printSendMsg ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned <ISA_LIT>mm16 = MI -> getOperand ( OpNo ) . getImm ( ) ; unsigned Msg = <ISA_LIT>mm16 & <NUM_LIT> ; if ( Msg == <NUM_LIT> || Msg == <NUM_LIT> ) { unsigned Op = ( <ISA_LIT>mm16 >> <NUM_LIT> ) & <NUM_LIT> ; if ( Msg == <NUM_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Op == <NUM_LIT> ) { O << <STR_LIT> ; } else { unsigned Stream = ( <ISA_LIT>mm16 >> <NUM_LIT> ) & <NUM_LIT> ; if ( Op == <NUM_LIT> ) O


<s> void <ISA_LIT>InstPrinter :: printTFE ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) )


<s> O << formatDec ( MI -> getOperand ( OpNo ) . getImm ( ) &


<s> O << formatHex ( MI -> getOperand ( OpNo ) . getImm (


<s> void <ISA_LIT>InstPrinter :: printU32ImmOperand ( const MCInst * MI ,


<s> void <ISA_LIT>InstPrinter :: printU32ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << formatHex ( MI -> getOperand ( OpNo ) . getImm (


<s> void <ISA_LIT>InstPrinter :: printU8ImmDecOperand ( const MCInst * MI ,


<s> O << formatHex ( MI -> getOperand ( OpNo )


<s> void <ISA_LIT>InstPrinter :: printUpdatePred ( const MCInst * MI , unsigned OpNo , raw_ostream &


<s> void <ISA_LIT>InstPrinter :: printVOPDst ( const MCInst * MI


<s>
bool
NeedSpace
=
false
;
if
(
Vmcnt
!=
<NUM_LIT>
)
{
O
<<
<STR_LIT>
<<
Vmcnt
<<
')'
;
NeedSpace
=
true
;
}
if
(
Expcnt
!=
<NUM_LIT>
)
{
if
(
NeedSpace
)
O
<<
' '
;
O
<<
<STR_LIT>
<<
Expcnt
<<
')'
;
NeedSpace
=


<s> if ( const Argument * Arg = dyn_cast < Argument > ( Ptr ) ) return <STR_LIT> ( Arg ) ; const Instruction * I = dyn_cast < Instruction > ( Ptr ) ; return I && I -> getMetadata (


<s> const Value * Ptr = MMO -> getValue ( ) ; if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ; if ( const Argument * Arg = dyn_cast < Argument > (


<s> <ISA_LIT>EncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & <STR_LIT> ) != <NUM_LIT> && ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ) Gen = <STR_LIT> ; if ( get ( Opcode ) . TSFlags & <STR_LIT> ) Gen = ST . getGeneration ( ) == <ISA_LIT>Subtarget :: GFX9 ? <STR_LIT> : <STR_LIT> ; int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return


<s> if ( ( get ( Opcode ) . TSFlags & <STR_LIT> ) != <NUM_LIT> && ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ) Gen = <STR_LIT> ; if ( get ( Opcode ) . TSFlags & <STR_LIT> ) Gen = ST . getGeneration ( ) == <ISA_LIT>Subtarget :: GFX9 ? <STR_LIT> : <STR_LIT> ; int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( MCOp == ( uint16_t ) - <NUM_LIT> ) return - <NUM_LIT> ; return


<s> <ISA_LIT>EncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( get ( Opcode ) . TSFlags & <STR_LIT> ) Gen = ST . getGeneration ( ) == <ISA_LIT>Subtarget :: GFX9 ? <STR_LIT> : <STR_LIT> ; int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( MCOp == ( uint16_t )


<s> if ( get ( Opcode ) . TSFlags & <STR_LIT> ) Gen = ST . getGeneration ( ) == <ISA_LIT>Subtarget :: GFX9 ? <STR_LIT> : <STR_LIT> ; if ( ( get ( Opcode ) . TSFlags & <STR_LIT> ) != <NUM_LIT> && ST . getGeneration ( ) >= <ISA_LIT>Subtarget ::


<s> if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ; if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS ::


<s> if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ; if ( const Argument * Arg = dyn_cast < Argument > ( Ptr ) ) return <STR_LIT> ( Arg ) ; const Instruction * I = dyn_cast < Instruction > ( Ptr


<s> bool <ISA_LIT>InstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI ,


<s> bool <ISA_LIT>InstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , ArrayRef < unsigned > Ops ) const { return


<s> Offset = MF . getSubtarget ( ) . getFrameLowering ( ) -> getFrameIndexOffset ( MF , - <NUM_LIT> ) ; return getIndirectIndexBegin ( MF ) + Offset


<s> ArrayRef < std :: pair < int , const char * >> <ISA_LIT>InstrInfo :: getSerializableTargetIndices ( ) const { static const std :: pair < int , const char * > TargetIndices [ ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; return makeArrayRef ( TargetIndices


<s> static const std :: pair < int , const char * > TargetIndices [ ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , {

<STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;


<s> switch ( ST . getGeneration ( ) ) { case <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS : case <ISA_LIT>Subtarget :: SEA_ISLANDS : return <STR_LIT> ; case <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS


<s> MachineInstr * <ISA_LIT>InstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MFI , MachineBasicBlock :: iterator & MBBI , LiveVariables * LV ) const { return nullptr


<s> bool <ISA_LIT>InstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const { return


<s> int OffsetOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: addr ) ; int RegOpIdx = OffsetOpIdx + <NUM_LIT> ; int ChanOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: chan ) ; if ( isRegisterLoad ( * MI ) ) { int DstOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: dst ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == <STR_LIT> ) { buildMovInstr ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , getIndirectAddrRegClass ( ) -> getRegister ( Address ) ) ; } else { buildIndirectRead ( MBB , MI , MI -> getOperand ( DstOpIdx ) . getReg ( ) , Address , OffsetReg ) ; } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: val ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress (


<s> if ( MRI . livein_empty ( ) ) { return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( MachineRegisterInfo :: livein_iterator LI = MRI . livein_begin ( ) , LE = MRI . livein_end ( ) ; LI != LE ; ++ LI ) { unsigned Reg = LI -> first ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex )


<s> int <ISA_LIT>InstrInfo :: getIndirectIndexBegin ( const MachineFunction & MF ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int Offset = - <NUM_LIT> ; if ( MFI -> getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } if ( MRI . livein_empty ( ) ) { return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( MachineRegisterInfo :: livein_iterator LI = MRI . livein_begin ( ) , LE = MRI . livein_end ( ) ; LI != LE ; ++ LI ) { unsigned Reg = LI -> first ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex


<s> int <ISA_LIT>InstrInfo :: getIndirectIndexEnd ( const MachineFunction & MF ) const { int Offset = <NUM_LIT> ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; assert ( ! MFI -> hasVarSizedObjects ( ) ) ; if ( MFI -> getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } unsigned IgnoredFrameReg ; Offset = MF . getSubtarget ( ) . getFrameLowering ( ) -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ; return getIndirectIndexBegin ( MF )


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; assert ( ! MFI -> hasVarSizedObjects ( ) ) ; if ( MFI -> getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } unsigned IgnoredFrameReg ; Offset = MF . getSubtarget ( ) . getFrameLowering ( ) -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ; return getIndirectIndexBegin ( MF ) +


<s> case <NUM_LIT> : return <STR_LIT> ( Opcode , <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> ( Opcode , <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT>


<s> int <ISA_LIT>InstrInfo :: getMaskedMIMGOp ( uint16_t Opcode , unsigned Channels ) const { switch ( Channels ) { default : return


<s> static int getMCOpcode ( uint16_t Opcode , unsigned Gen ) { return getMCOpcodeGen ( Opcode , (


<s> unsigned <ISA_LIT>InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad

, bool UnfoldStore , unsigned * LoadRegIndex ) const {


<s> static std :: pair < int , const char * > TargetIndices [ ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; return makeArrayRef ( TargetIndices


<s> bool <ISA_LIT>InstrInfo :: hasLoadFromStackSlot ( const MachineInstr * MI , const MachineMemOperand


<s> bool <ISA_LIT>InstrInfo :: hasStoreFromStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int &


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex )


<s> bool <ISA_LIT>InstrInfo :: isPredicable (


. TSFlags & <ISA_LIT>_FLAG_REGISTER_LOAD ;


. TSFlags & <ISA_LIT>_FLAG_REGISTER_STORE ;


<s> return get ( MI . getOpcode ( ) ) . TSFlags &


<s> unsigned <ISA_LIT>InstrInfo :: isStoreFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return


<s> unsigned <ISA_LIT>InstrInfo :: isStoreFromStackSlot ( const MachineInstr * MI , int


<s> unsigned <ISA_LIT>InstrInfo :: isStoreFromStackSlotPostFE ( const MachineInstr * MI


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { llvm_unreachable ( <STR_LIT>


<s> int <ISA_LIT>InstrInfo :: pseudoToMCOpcode ( int Opcode ) const { int MCOp = <STR_LIT> ( Opcode , AMDGPUSubtargetTo<ISA_LIT>Subtarget ( ST . getGeneration ( ) ) ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( MCOp == ( uint16_t ) -


<s> bool <ISA_LIT>InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load0 , SDNode * Load1 , int64_t Offset0 , int64_t Offset1 , unsigned NumLoads ) const { assert ( Offset1 > Offset0 && <STR_LIT> ) ; return ( NumLoads <= <NUM_LIT> && ( Offset1 -


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { llvm_unreachable ( <STR_LIT> )


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1

, ArrayRef < MachineOperand > Pred2 ) const {


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return


<s> bool <ISA_LIT>InstrInfo :: unfoldMemoryOperand ( SelectionDAG & DAG , SDNode * N , SmallVectorImpl < SDNode * > & NewNodes ) const { return


<s> std :: tie ( IdxBaseReg , Offset ) = <STR_LIT> ( MRI , IdxReg ) ; if ( IdxBaseReg == <STR_LIT> ) { assert ( Offset == <NUM_LIT> ) ; IdxBaseReg = IdxReg ; } ArrayRef < int16_t > SubRegs = TRI . getRegSplitParts ( SuperRC , EltSize ) ; if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ; return std :: make_pair ( IdxBaseReg ,


<s> static std :: pair < Register , unsigned > computeIndirectRegIndex ( MachineRegisterInfo & MRI , const <ISA_LIT>RegisterInfo & TRI , const TargetRegisterClass * SuperRC , Register IdxReg , unsigned EltSize ) { Register IdxBaseReg ; int Offset ; std :: tie ( IdxBaseReg , Offset ) = <STR_LIT> ( MRI , IdxReg ) ; if ( IdxBaseReg == <STR_LIT> ) { assert ( Offset == <NUM_LIT> ) ; IdxBaseReg =


<s> if ( ! OffsetVal || ! isInt < <NUM_LIT> > ( * OffsetVal ) )


<s> Optional < int64_t > OffsetVal = getIConstantVRegSExtVal ( Reg , MRI ) ; if ( ! OffsetVal || ! isInt < <NUM_LIT> > (


<s> MachineOperand & RHS = RootI -> getOperand ( <NUM_LIT> ) ; Optional < ValueAndVReg > MaybeOffset = getIConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ; if ( ! MaybeOffset ) return { Root , <NUM_LIT> } ; return { RootI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MaybeOffset ->


<s> std :: pair < Register , int64_t > <ISA_LIT>InstructionSelector :: getPtrBaseWithConstantOffset ( Register Root , const MachineRegisterInfo & MRI ) const { MachineInstr * RootI = getDefIgnoringCopies ( Root , MRI ) ; if ( RootI -> getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return { Root , <NUM_LIT> } ; MachineOperand & RHS = RootI ->


<s> return RBI . getRegBank ( Reg , * MRI , TRI ) -> getID (


<s> bool <ISA_LIT>InstructionSelector :: isSGPR ( Register Reg ) const { return RBI . getRegBank ( Reg , * MRI , TRI ) -> getID (


<s> if ( ! RHS ) return false ; if ( RHS -> countTrailingOnes ( ) >= ShAmtBits ) return true ; const APInt & LHSKnownZeros = KnownBits -> getKnownZeroes ( MI .

getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> if ( mi_match ( Reg , MRI , m_GZExt ( m_Reg ( ZExtSrc ) ) ) ) return MRI . getType ( ZExtSrc ) == LLT :: scalar ( <NUM_LIT> ) ? ZExtSrc : Register ( ) ; const MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; if ( Def -> getOpcode ( ) != <STR_LIT> )


<s> if ( mi_match ( Reg , MRI , m_GZExt ( m_Reg ( ZExtSrc ) ) ) ) return MRI . getType ( ZExtSrc ) == LLT :: scalar ( <NUM_LIT> ) ? ZExtSrc : Register ( ) ; const MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; if ( Def -> getOpcode ( ) != <STR_LIT> ) return false ; if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ZeroInt ( ) ) ) { return Def -> getOperand ( <NUM_LIT> ) . getReg


<s> MIB . addImm ( MI . getOperand ( OpIdx ) . getImm


<s> assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( MI . getOperand ( OpIdx ) . getImm ( )


<s> void <ISA_LIT>InstructionSelector :: renderSetGLC ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const { assert ( OpIdx >= <NUM_LIT> &&


<s> MachineOperand & SOffset = MI . getOperand ( <NUM_LIT> ) ; int16_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool HasVOffset = ! isOperandImmEqual ( VOffset , <NUM_LIT> , * MRI ) ; bool HasVIndex = ! isOperandImmEqual ( VIndex , <NUM_LIT> , * MRI ) ; unsigned Opcode ; if ( HasVOffset ) { Opcode = HasVIndex ? <STR_LIT> : <STR_LIT> ; } else { Opcode = HasVIndex ? <STR_LIT> : <STR_LIT> ; } if ( MRI -> getType ( VDataIn . getReg ( ) ) . isVector ( ) ) { switch ( Opcode ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } auto I = BuildMI ( * MBB , MI , DL , TII . get ( Opcode ) ) ; I . add ( VDataIn ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { Register IdxReg = MRI -> createVirtualRegister ( TRI . getVGPR64Class ( ) ) ; BuildMI ( * MBB , & * I , DL , TII . get ( <STR_LIT> ) , IdxReg ) . addReg ( VIndex . getReg ( ) ) . addImm ( <STR_LIT> ) . addReg ( VOffset . getReg ( ) ) . addImm ( <STR_LIT> ) ; I . addReg ( IdxReg ) ; } else if ( HasVIndex ) { I . add ( VIndex ) ; } else if ( HasVOffset ) { I . add ( VOffset ) ; } I . add ( MI . getOperand ( <NUM_LIT> ) ) ; I . add ( SOffset ) ; I . addImm ( Offset ) ; I . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; I . cloneMemRefs ( MI ) ; MI . eraseFromParent ( )


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Size = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; const bool Is64 = Size == <NUM_LIT> ; if ( Size != STI . getWavefrontSize ( ) ) return false ; Optional < ValueAndVReg > Arg = getIConstantVRegValWithLookThrough ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( Arg . hasValue ( ) ) { const int64_t Value = Arg . getValue ( ) . Value . getSExtValue ( ) ; if ( Value == <NUM_LIT> ) { unsigned Opcode = Is64 ?


<s> const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; Optional < ValueAndVReg > ConstVal = getIConstantVRegValWithLookThrough ( SrcReg , * MRI , true ) ; if ( ConstVal ) { unsigned MovOpc = STI . isWave64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , DstReg ) . addImm ( ConstVal -> Value . getBoolValue ( ) ? - <NUM_LIT> : <NUM_LIT> ) ; } else { Register MaskedReg = MRI -> createVirtualRegister ( SrcRC ) ; unsigned AndOpc = TRI . isSGPRClass ( SrcRC ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( AndOpc ) , MaskedReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( MaskedReg ) ; } if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , SrcRC ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg


<s> unsigned Opc ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( Ty == LLT :: scalar ( <NUM_LIT> ) ) Opc = <STR_LIT> ; else return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; Register Numer = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Denom = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ChooseDenom = MI . getOperand ( <NUM_LIT>


<s> if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) { Register VSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( STI . needsAlignedVGPRs ( ) ) { Register Undef = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & * MIB , DL , TII . get ( <STR_LIT> ) , Undef ) ; Register NewVR = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & * MIB , DL , TII . get ( <STR_LIT> ) , NewVR ) . addReg ( VSrc , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) . addImm ( <STR_LIT> ) . addReg ( Undef ) . addImm ( <STR_LIT> ) ; MIB . addReg ( NewVR , <NUM_LIT> , <STR_LIT> ) ; MIB . addReg ( NewVR , RegState :: Implicit ) ; } else { MIB . addReg ( VSrc


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB

. addImm ( PtrWithOffset . second ) ; } , } } ;


<s> return false ; } auto Addr = selectFlatOffsetImpl ( AddrOp , <STR_LIT> ) ; Register Data = DataOp . getReg ( ) ; const unsigned Opc = MRI -> getType ( Data ) . isVector ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( Opc ) ) . addReg ( Addr . first ) . addReg ( Data ) . addImm ( Addr . second ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI ,


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( ! MRI -> use_nodbg_empty ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Function & F = MBB -> getParent ( ) -> getFunction ( ) ; DiagnosticInfoUnsupported NoFpRet ( F , <STR_LIT> , MI . getDebugLoc ( ) , DS_Error ) ; F . getContext ( ) . diagnose ( NoFpRet ) ; return false


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectGlobalOffset ( MachineOperand & Root ) const { auto PtrWithOffset = selectFlatOffsetImpl (


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register HighBits = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , HighBits ) . addImm ( RemainderOffset ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrBase ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( HighBits ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( SplitImmOffset ) ; } , } } ; } } unsigned NumLiterals = ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset & <NUM_LIT> ) ) + ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset >> <NUM_LIT> ) ) ; if ( STI . getConstantBusLimit ( <STR_LIT> ) > NumLiterals ) return None ; } } } auto AddrDef = getDefSrcRegIgnoringCopies ( Addr , * MRI ) ; if ( ! AddrDef ) return None ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register SAddr = getSrcRegIgnoringCopies ( AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( SAddr && isSGPR ( SAddr ) ) { Register PtrBaseOffset = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register VOffset = matchZeroExtendFromS32 ( * MRI , PtrBaseOffset ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } } } if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || ! isSGPR ( AddrDef -> Reg ) ) return None ; MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register VOffset = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get

( <STR_LIT> ) , VOffset ) . addImm ( <NUM_LIT> ) ;


<s> } unsigned NumLiterals = ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset & <NUM_LIT> ) ) + ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset >> <NUM_LIT> ) ) ; if ( STI . getConstantBusLimit ( <STR_LIT> ) > NumLiterals ) return None ; } } } auto AddrDef = getDefSrcRegIgnoringCopies ( Addr , * MRI ) ; if ( ! AddrDef ) return None ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register SAddr = getSrcRegIgnoringCopies ( AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( SAddr && isSGPR ( SAddr ) ) { Register PtrBaseOffset = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register VOffset = matchZeroExtendFromS32 ( * MRI , PtrBaseOffset ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } } } if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || ! isSGPR ( AddrDef -> Reg ) ) return None ; MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register VOffset = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , VOffset ) . addImm ( <NUM_LIT> ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( AddrDef -> Reg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } }


<s> MachineBasicBlock * BB = MI . getParent ( ) ; Register VAddr , RSrcReg , SOffset ; int64_t Offset = <NUM_LIT> ; unsigned Opcode ; if ( selectMUBUFOffsetImpl ( MI . getOperand ( <NUM_LIT> ) , RSrcReg , SOffset , Offset ) ) { Opcode = Is64 ? <STR_LIT> : <STR_LIT> ; } else if ( selectMUBUFAddr64Impl ( MI . getOperand ( <NUM_LIT> ) , VAddr , RSrcReg , SOffset , Offset ) ) { Opcode = Is64 ? <STR_LIT> : <STR_LIT> ; } else return selectImpl ( MI , * CoverageInfo ) ; auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( Opcode ) , TmpReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( VAddr ) MIB . addReg ( VAddr ) ; MIB . addReg ( RSrcReg ) ; if ( SOffset ) MIB . addReg ( SOffset ) ; else MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( Offset ) ; MIB . addImm ( <STR_LIT> :: GLC


<s> Register CondPhysReg ; const TargetRegisterClass * ConstrainRC ; if ( ! isVCC ( CondReg , * MRI ) ) { if ( MRI -> getType ( CondReg ) != LLT :: scalar ( <NUM_LIT> ) ) return false ; CondPhysReg = <STR_LIT> ; BrOpcode = <STR_LIT> ; ConstrainRC = & <STR_LIT> ; } else { if ( ! isVCmpResult ( CondReg , * MRI ) ) { const bool Is64 = STI . isWave64 ( ) ; const unsigned Opcode = Is64 ? <STR_LIT> : <STR_LIT> ; const Register Exec = Is64 ? <STR_LIT> : <STR_LIT> ; Register TmpReg = MRI -> createVirtualRegister ( TRI . getBoolRC ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , TmpReg ) . addReg ( CondReg ) . addReg ( Exec ) ; CondReg = TmpReg ; } CondPhysReg = TRI . getVCC ( ) ; BrOpcode = <STR_LIT> ; ConstrainRC = TRI . getBoolRC ( ) ; } if ( ! MRI -> getRegClassOrNull ( CondReg ) ) MRI -> setRegClass ( CondReg , ConstrainRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CondPhysReg ) . addReg ( CondReg ) ; BuildMI ( * BB , & I , DL , TII . get ( BrOpcode ) ) . addMBB ( I . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; I . eraseFromParent ( ) ; return true


<s> const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( SrcTy , * SrcRB , * MRI ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( DstTy , * DstRB , * MRI ) ; if ( ! SrcRC || ! DstRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } const MCInstrDesc & GPRIDXDesc = TII . getIndirectGPRIDXPseudo ( TRI . getRegSizeInBits ( * SrcRC ) , true ) ; BuildMI ( * BB , MI , DL , GPRIDXDesc , DstReg ) . addReg ( SrcReg ) . addReg ( IdxReg ) . addImm ( SubReg ) ; MI . eraseFromParent ( ) ; return


<s> const TargetRegisterClass * ValRC = TRI . getRegClassForTypeOnBank ( ValTy , * ValRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( VecReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( ValReg , * ValRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; if ( VecRB -> getID ( ) == <STR_LIT> && ValSize != <NUM_LIT> ) return false ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , VecRC , IdxReg , ValSize / <NUM_LIT> ) ; const bool IndexMode = VecRB -> getID ( ) == <STR_LIT> && STI . useVGPRIndexMode ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( ! IndexMode ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; const MCInstrDesc & RegWriteOp = TII . getIndirectRegWriteMovRelPseudo ( VecSize , ValSize , VecRB -> getID ( ) == <STR_LIT> ) ; BuildMI ( * BB , MI , DL , RegWriteOp , DstReg ) . addReg ( VecReg ) . addReg ( ValReg ) . addImm ( SubReg ) ; MI . eraseFromParent ( ) ; return true ; } const MCInstrDesc & GPRIDXDesc = TII . getIndirectGPRIDXPseudo ( TRI . getRegSizeInBits ( * VecRC ) , false ) ; BuildMI ( * BB , MI , DL , GPRIDXDesc , DstReg ) . addReg ( VecReg ) . addReg ( ValReg ) . addReg ( IdxReg ) .


<s> if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * VecRC = TRI . getRegClassForTypeOnBank ( VecTy , * VecRB , * MRI ) ; const TargetRegisterClass * ValRC = TRI . getRegClassForTypeOnBank ( ValTy , * ValRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( VecReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( ValReg , * ValRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; if ( VecRB -> getID ( ) == <STR_LIT> && ValSize != <NUM_LIT> ) return false ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , VecRC , IdxReg , ValSize / <NUM_LIT> ) ; const bool IndexMode = VecRB -> getID ( ) == <STR_LIT> && STI .


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return selectWritelane ( I ) ; case <STR_LIT> : return selectDivScale ( I ) ; case <STR_LIT> : return selectIntrinsicIcmp ( I ) ; case <STR_LIT> : return selectBallot ( I ) ; case <STR_LIT> : return selectRelocConstant ( I ) ; case <STR_LIT> : return selectGroupStaticSize ( I ) ; case <STR_LIT>


<s> case <STR_LIT> : { MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return selectWritelane ( I ) ; case <STR_LIT>


<s> unsigned AS = PtrTy . getAddressSpace ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) return selectGlobalAtomicFadd ( I , I . getOperand ( <NUM_LIT> ) , I . getOperand ( <NUM_LIT> ) ) ; } initM0 ( I ) ; return selectImpl ( I , * CoverageInfo


<s> const LLT PtrTy = MRI -> getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned AS = PtrTy . getAddressSpace ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS ) return selectGlobalAtomicFadd ( I , I .

getOperand ( <NUM_LIT> ) , I . getOperand ( <NUM_LIT> ) ) ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; assert ( Size <= <NUM_LIT> || Size == <NUM_LIT> ) ; const MachineOperand & CCOp = I . getOperand ( <NUM_LIT> ) ; Register CCReg = CCOp . getReg ( ) ; if ( ! isVCC ( CCReg , * MRI ) ) { unsigned SelectOpcode = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * CopySCC = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CCReg ) ; if ( ! MRI -> getRegClassOrNull ( CCReg ) ) MRI -> setRegClass ( CCReg , TRI . getConstrainedRegClassForOperand ( CCOp , * MRI ) ) ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( SelectOpcode ) , DstReg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = false ; Ret |= constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) ; Ret |= constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return


<s> if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ; } } else if ( Mask [ <NUM_LIT> ] == - <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { MachineInstr * MovSDWA = BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_1 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_0 ) . addReg ( SrcVec , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT>