<s> Offset = ByteOffsetNode ; Imm = false ; return true ; } if ( ByteOffsetNode . getOpcode ( ) == <STR_LIT> ) { if ( ByteOffsetNode . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { Offset = ByteOffsetNode . getOperand ( <NUM_LIT> ) ; Imm = false ; return true ; } } return false ; } SDLoc SL ( ByteOffsetNode ) ; int64_t ByteOffset = C -> getSExtValue ( ) ; Optional < int64_t > EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset , false ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; Imm = true ; return true ; } if ( ByteOffset < <NUM_LIT> ) return false ; EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; return true ; } if ( ! isUInt < <NUM_LIT> > ( ByteOffset ) && ! isInt < <NUM_LIT> > ( ByteOffset ) ) return false ; SDValue C32Bit = CurDAG -> getTargetConstant ( ByteOffset , SL , <STR_LIT> ) ; Offset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL ,


<s> if ( ByteOffsetNode . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { Offset = ByteOffsetNode . getOperand ( <NUM_LIT> ) ; Imm = false ; return true ; } } return false ; } SDLoc SL ( ByteOffsetNode ) ; int64_t ByteOffset = C -> getSExtValue ( ) ; Optional < int64_t > EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset , false ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; Imm = true ; return true ; } if ( ByteOffset < <NUM_LIT> ) return false ; EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; return true ; } if ( ! isUInt < <NUM_LIT> > ( ByteOffset ) && ! isInt < <NUM_LIT> > ( ByteOffset ) ) return false ; SDValue C32Bit = CurDAG -> getTargetConstant ( ByteOffset , SL , <STR_LIT> ) ; Offset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , C32Bit ) , <NUM_LIT> ) ; return


<s> LoopInfo * LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( auto & L : LI -> getLoopsInPreorder ( ) ) { assert ( L -> isLCSSAForm ( DT ) ) ; } Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF


<s> for ( auto & L : LI -> getLoopsInPreorder ( ) ) { assert ( L -> isLCSSAForm ( DT ) ) ; } Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF


<s> MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( BaseOffset ) ) { glueCopyToM0 ( N , CurDAG -> getTargetConstant ( - <NUM_LIT> , SL , <STR_LIT> ) ) ; ImmOffset = ConstOffset -> getZExtValue ( ) + <NUM_LIT> ; } else { if ( CurDAG -> isBaseWithConstantOffset ( BaseOffset ) ) { ImmOffset = BaseOffset . getConstantOperandVal ( <NUM_LIT> ) ; BaseOffset = BaseOffset . getOperand ( <NUM_LIT> ) ; } SDNode * SGPROffset = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , BaseOffset ) ; SDNode * M0Base = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , SDValue ( SGPROffset , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; glueCopyToM0 ( N , SDValue ( M0Base , <NUM_LIT> ) ) ; } SDValue V0 ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Glue ; if ( HasVSrc ) { SDValue VSrc0 = N -> getOperand ( <NUM_LIT> ) ; V0 = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue CopyToV0 = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , SL , V0 , VSrc0 , N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ) ; Chain = CopyToV0 ; Glue = CopyToV0 . getValue ( <NUM_LIT> ) ; } SDValue OffsetField = CurDAG -> getTargetConstant ( ImmOffset , SL , <STR_LIT> ) ; SDValue GDS = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const unsigned Opc = gwsIntrinToOpcode ( IntrID ) ; SmallVector < SDValue ,


<s> ConstantSDNode * C = cast < ConstantSDNode > ( Addr64 ) ; if ( C -> getSExtValue ( ) ) { SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . wrapAddr64Rsrc ( * CurDAG , DL , Ptr ) , <NUM_LIT> ) ; return true ; } return false


<s> <ISA_LIT>DAGToDAGISel :: <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( * TM , OptLevel ) { EnableLateStructurizeCFG = <ISA_LIT>TargetMachine ::


<s> <ISA_LIT>DAGToDAGISel :: <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel


<s> void <ISA_LIT>DAGToDAGISel :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < <ISA_LIT>ArgumentUsageInfo


<s> SDValue BaseLo = Lo . getOperand ( <NUM_LIT> ) ; SDValue BaseHi = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( BaseLo . getOpcode ( ) == <STR_LIT> && BaseHi . getOpcode ( ) == <STR_LIT> && BaseLo . getOperand ( <NUM_LIT> ) == BaseHi . getOperand ( <NUM_LIT> ) && isa < ConstantSDNode > ( BaseLo . getOperand ( <NUM_LIT> ) ) && BaseLo . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && isa < ConstantSDNode > ( BaseHi . getOperand ( <NUM_LIT> ) ) && BaseHi . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) { N0 = BaseLo . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; N1 = Lo . getOperand ( <NUM_LIT> ) ; return true ; } } } return false


<s> return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [ OpIdx ] . RegClass ; if ( RegClass == - <NUM_LIT> ) return nullptr ; return Subtarget -> getRegisterInfo ( ) -> getRegClass ( RegClass ) ; } case <STR_LIT> : { unsigned RCID = cast < ConstantSDNode > ( N ->

getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> return MRI . getRegClass ( Reg ) ; } const <ISA_LIT>RegisterInfo * TRI = static_cast < const GCNSubtarget * > ( Subtarget ) -> getRegisterInfo ( ) ; return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [ OpIdx ]


<s> RHS = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( getBaseWithOffsetUsingSplitOR ( * CurDAG , Addr


<s> if ( Offset0 % Size != <NUM_LIT> || Offset1 % Size != <NUM_LIT> ) return false ; if ( ! isUInt < <NUM_LIT> > ( Offset0 / Size ) || !

isUInt < <NUM_LIT> > ( Offset1 / Size ) ) return false ;


<s> bool <ISA_LIT>DAGToDAGISel :: isDSOffsetLegal ( SDValue Base , unsigned Offset ) const { if ( ! isUInt < <NUM_LIT> > ( Offset ) ) return false ; if ( ! Base || Subtarget -> hasUsableDSOffset ( ) ||

Subtarget -> unsafeDSOffsetFoldingEnabled ( ) ) return true ;


<s> if ( ! Base || Subtarget -> hasUsableDSOffset ( ) || Subtarget -> unsafeDSOffsetFoldingEnabled ( ) ) return true ; return CurDAG -> SignBitIsZero ( Base


<s> Out = In . getOperand ( <NUM_LIT> ) ; return true ; } } if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftAmt -> getZExtValue ( ) == <NUM_LIT> ) { Out = stripBitcast ( Srl .


<s> bool <ISA_LIT>DAGToDAGISel :: isNoNanSrc ( SDValue N ) const { if ( TM . Options . NoNaNsFPMath ) return true ; if ( N -> getFlags ( ) . hasNoNaNs ( )


<s> SDLoc DL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) ; bool ConsumeCarry = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool ProduceCarry = ConsumeCarry || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool IsAdd = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * Lo0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub0 ) ; SDNode * Hi0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub1 ) ; SDNode * Lo1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub0 ) ; SDNode * Hi1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub1 ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; static const unsigned OpcMap [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; unsigned Opc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; unsigned CarryOpc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [


<s> SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue CPol = CurDAG -> getTargetConstant ( <STR_LIT> :: GLC , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , CPol , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue CPol = CurDAG -> getTargetConstant ( <STR_LIT> :: GLC , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , CPol , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineMemOperand * MMO = Mem -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( CmpSwap , { MMO } ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap


<s> void <ISA_LIT>DAGToDAGISel :: SelectDIV_SCALE ( SDNode * N ) { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3BMods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3BMods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS128Bit8ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0


<s> return SelectDSReadWrite2 ( Addr , Base ,


<s> SmallVector < SDValue , <NUM_LIT> > Opnds ; Opnds . push_back ( Zero ) ; Opnds . push_back ( Addr . getOperand ( <NUM_LIT> ) ) ; unsigned SubOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { SubOp = <STR_LIT> ; Opnds . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) ) ; } MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Opnds ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ByteOffset , DL , <STR_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isDSOffsetLegal ( SDValue ( ) , CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } Base =


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const { return SelectDSReadWrite2 ( Addr , Base ,


<s> void <ISA_LIT>DAGToDAGISel :: SelectDSAppendConsume ( SDNode * N , unsigned IntrID ) { unsigned Opc = IntrID == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; bool IsGDS = M -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; SDValue Offset ; if ( CurDAG -> isBaseWithConstantOffset ( Ptr ) ) { SDValue PtrBase = Ptr . getOperand ( <NUM_LIT> ) ; SDValue PtrOffset = Ptr . getOperand ( <NUM_LIT> ) ; const APInt & OffsetVal = cast < ConstantSDNode > ( PtrOffset ) -> getAPIntValue ( ) ; if ( isDSOffsetLegal ( PtrBase , OffsetVal . getZExtValue ( ) ) ) { N = glueCopyToM0 ( N , PtrBase ) ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; } } if ( ! Offset ) { N = glueCopyToM0 ( N ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDSReadWrite2 ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 , unsigned Size ) const { SDLoc DL ( Addr ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; unsigned OffsetValue0 = C1 -> getZExtValue ( ) ; unsigned OffsetValue1 = OffsetValue0 + Size ; if ( isDSOffset2Legal ( N0 , OffsetValue0 , OffsetValue1 , Size ) ) { Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( OffsetValue0 / Size , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( OffsetValue1 / Size , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned OffsetValue0 = C -> getZExtValue ( ) ; unsigned OffsetValue1 = OffsetValue0 + Size ; if ( isDSOffset2Legal ( SDValue ( ) , OffsetValue0 , OffsetValue1 , Size ) ) { SDLoc DL ( Addr ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL


<s> return ; } const bool HasVSrc = N -> getNumOperands ( ) == <NUM_LIT> ; assert ( HasVSrc || N -> getNumOperands ( ) == <NUM_LIT> ) ; SDLoc SL ( N ) ; SDValue BaseOffset = N -> getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) ; int ImmOffset = <NUM_LIT> ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( BaseOffset ) ) { glueCopyToM0 ( N , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; ImmOffset = ConstOffset -> getZExtValue ( ) ; } else { if ( CurDAG -> isBaseWithConstantOffset ( BaseOffset


<s> BaseOffset = BaseOffset . getOperand ( <NUM_LIT> ) ; } SDNode * SGPROffset = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , BaseOffset ) ; SDNode * M0Base = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , SDValue ( SGPROffset , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; glueCopyToM0 ( N , SDValue ( M0Base , <NUM_LIT> ) ) ; } SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue OffsetField = CurDAG -> getTargetConstant ( ImmOffset , SL , <STR_LIT> ) ; const unsigned Opc = gwsIntrinToOpcode ( IntrID ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HasVSrc ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( OffsetField ) ; Ops . push_back ( Chain ) ; SDNode * Selected = CurDAG -> SelectNodeTo ( N , Opc , N


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatOffset ( SDNode * N , SDValue Addr , SDValue & VAddr , SDValue &


<s> bool UseFMAC = Subtarget -> hasDLInsts ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) ; unsigned Opcode = UseFMAC ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opcode , N -> getVTList


<s> SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; bool UseFMAC = Subtarget -> hasDLInsts ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [

<NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) ;


<s> return SelectFlatOffsetImpl ( N , Addr ,


<s> unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Clamp } ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Clamp } ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( )


<s> SDLoc DL ( Index ) ; if ( CurDAG -> isBaseWithConstantOffset ( Index ) ) { SDValue N0 = Index . getOperand ( <NUM_LIT> ) ; SDValue N1 = Index . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( C1 -> getSExtValue ( ) <= <NUM_LIT> || CurDAG -> SignBitIsZero ( N0 ) || ( Index -> getOpcode ( ) == <STR_LIT> && C1 -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = N0 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } if ( isa < ConstantSDNode > ( Index ) ) return false ; Base =


<s> if ( ! SelectMUBUF ( Addr , Ptr , VAddr , SOffset , Offset , Offen , Idxen , Addr64 ) ) return false ; if ( ! cast < ConstantSDNode > ( Offen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Idxen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Addr64 ) -> getSExtValue ( ) ) { uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnes ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL , Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ; return true ; } return


<s> SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } std :: tie ( VAddr , SOffset ) = foldFrameIndex ( Addr ) ; ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL ,


<s> ConstantSDNode * CAddr ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { CAddr = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( ! CAddr || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) return false ; if ( ! IsCopyFromSGPR ( * TRI , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; SOffset = Addr . getOperand ( <NUM_LIT> ) ; } else if ( ( CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) && <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { return false ; } SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( )


<s> CAddr = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( ! CAddr || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) return false ; if ( ! IsCopyFromSGPR ( * TRI , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; SOffset = Addr . getOperand ( <NUM_LIT> ) ; } else if ( ( CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) && <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { return false ; } SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr ->


<s> bool <ISA_LIT>DAGToDAGISel :: SelectScratchOffset ( SDNode * N , SDValue Addr , SDValue & VAddr , SDValue


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) || Addr . getOpcode ( ) == <STR_LIT> ) { N0 = Addr . getOperand ( <NUM_LIT> ) ; N1 = Addr . getOperand ( <NUM_LIT> ) ; } else if ( getBaseWithOffsetUsingSplitOR ( * CurDAG , Addr , N0 , N1 ) ) { assert ( N0 && N1 && isa < ConstantSDNode > ( N1 ) ) ; } if ( N0 && N1 ) { if ( SelectSMRDOffset ( N1 , Offset , Imm ) ) { SBase = Expand32BitAddress ( N0 ) ; return true ; } } } SBase = Expand32BitAddress (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3BMods ( SDValue In , SDValue & Src , SDValue & SrcMods ) const { unsigned Mods ; if ( SelectVOP3ModsImpl ( In , Src , Mods , false ) ) { SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; } return false


<s> Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Omod = CurDAG -> getTargetConstant ( <NUM_LIT>


<s> if ( AllowAbs && Src . getOpcode ( ) == <STR_LIT> ) { Mods |= <STR_LIT> ; Src = Src . getOperand ( <NUM_LIT> ) ; } return true


<s> Mods = <NUM_LIT> ; Src = In ; if ( Src . getOpcode ( ) == <STR_LIT> ) { Mods |= <STR_LIT> ; Src = Src . getOperand ( <NUM_LIT> ) ; } if ( AllowAbs && Src . getOpcode ( ) == <STR_LIT>


<s> Mods ^= <STR_LIT> ; } if ( isExtractHiElt ( Lo , Lo ) ) Mods |= <STR_LIT> ; if ( isExtractHiElt ( Hi , Hi ) ) Mods |= <STR_LIT> ; unsigned VecSize = Src . getValueSizeInBits ( ) ; Lo = stripExtractLoElt ( Lo ) ; Hi = stripExtractLoElt ( Hi ) ; if ( Lo . getValueSizeInBits ( ) > VecSize ) { Lo = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Lo ) ; } if ( Hi . getValueSizeInBits ( ) > VecSize ) { Hi = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Hi ) ; } assert ( Lo . getValueSizeInBits ( ) <= VecSize && Hi . getValueSizeInBits ( ) <= VecSize ) ; if ( Lo == Hi && ! isInlineImmediate ( Lo . getNode ( ) ) ) { if ( VecSize == <NUM_LIT> || VecSize == Lo . getValueSizeInBits ( ) ) { Src = Lo ; } else { assert ( Lo . getValueSizeInBits ( ) == <NUM_LIT> && VecSize == <NUM_LIT> ) ; SDLoc SL ( In ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , SL , Lo . getValueType ( ) ) , <NUM_LIT> ) ; auto RC = Lo -> isDivergent ( ) ? <STR_LIT> : <STR_LIT> ; const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( RC , SL , <STR_LIT> ) , Lo , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Undef ,

CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) } ;


<s> Lo = stripBitcast ( Lo . getOperand ( <NUM_LIT> ) ) ; Mods ^= <STR_LIT> ; } if ( Hi . getOpcode ( ) == <STR_LIT> ) { Hi = stripBitcast ( Hi . getOperand ( <NUM_LIT> ) ) ; Mods ^= <STR_LIT> ; } if ( isExtractHiElt ( Lo , Lo ) ) Mods |= <STR_LIT> ; if ( isExtractHiElt ( Hi , Hi ) ) Mods |= <STR_LIT> ; unsigned VecSize = Src . getValueSizeInBits ( ) ; Lo = stripExtractLoElt ( Lo ) ; Hi = stripExtractLoElt ( Hi ) ; if ( Lo . getValueSizeInBits ( ) > VecSize ) { Lo = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Lo ) ; } if ( Hi . getValueSizeInBits ( ) > VecSize ) { Hi = CurDAG -> getTargetExtractSubreg ( ( VecSize > <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> , SDLoc ( In ) , <STR_LIT> ( VecSize ) , Hi ) ; } assert ( Lo . getValueSizeInBits ( ) <= VecSize && Hi . getValueSizeInBits ( ) <= VecSize ) ; if ( Lo == Hi && ! isInlineImmediate ( Lo . getNode ( ) ) ) { if ( VecSize == <NUM_LIT> || VecSize == Lo . getValueSizeInBits ( ) ) { Src = Lo ; } else { assert ( Lo . getValueSizeInBits ( ) == <NUM_LIT> && VecSize == <NUM_LIT> ) ; SDLoc SL ( In ) ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , SL , Lo . getValueType ( ) ) , <NUM_LIT> ) ; auto RC = Lo -> isDivergent ( ) ? <STR_LIT> : <STR_LIT> ; const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( RC , SL , <STR_LIT> ) , Lo , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Undef , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) } ; Src = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , SL , Src . getValueType ( ) , Ops ) , <NUM_LIT> ) ; } SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; } if ( VecSize == <NUM_LIT> && Lo == Hi && isa < ConstantFPSDNode > ( Lo ) ) { uint64_t Lit = cast < ConstantFPSDNode > ( Lo ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( <STR_LIT> ( Lit , Subtarget


<s> if ( ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( In . getOperand ( <NUM_LIT> ) ) ) { if ( Idx -> isZero ( ) && In . getValueSizeInBits ( ) <= <NUM_LIT> ) return In .


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return ; } else if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant (


<s> GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr =


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFAddr64 ( SDValue Addr , SDValue & SRsrc , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { SDValue Ptr , Offen , Idxen , Addr64 ; if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS )


<s> SelectMUBUF ( Addr , Ptr , VAddr , SOffset , Offset , Offen , Idxen , Addr64 , GLC , SLC , TFE ) ; if ( ! cast < ConstantSDNode > ( Offen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Idxen )

-> getSExtValue ( ) && ! cast < ConstantSDNode > ( Addr64 ) -> getSExtValue ( ) ) {


<s> uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnesValue ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL ,

Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ;


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Glue ) ; CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , N -> getVTList ( ) , Ops ) ; return N


<s> SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back (


<s> return isLegalMUBUFImmOffset ( Imm -> getZExtValue ( )


<s> CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineSDNode :: mmo_iterator MMOs = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; * MMOs = Mem -> getMemOperand ( ) ; CmpSwap -> setMemRefs ( MMOs , MMOs + <NUM_LIT> ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Extract ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( N


<s> SelectCode ( N ) ; return ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , GLC , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineSDNode :: mmo_iterator MMOs = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; * MMOs = Mem -> getMemOperand ( ) ; CmpSwap -> setMemRefs ( MMOs , MMOs + <NUM_LIT> ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap


<s> unsigned Imm = CAddr -> getZExtValue ( ) ; assert ( ! isLegalMUBUFImmOffset ( Imm ) && <STR_LIT> ) ; SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode


<s> SDLoc DL ( Addr ) ; MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue (


<s> Mods = <NUM_LIT> ; SelectVOP3ModsImpl ( In , Src , Mods ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) { Src = Src .


<s> assert ( Src . getValueType ( ) == <STR_LIT> ) ; Src = stripBitcast ( Src ) ; Mods |= <STR_LIT> ; if ( isExtractHiElt ( Src , Src ) ) Mods |= <STR_LIT> ; return true ; } return


<s> const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; SOffset = CurDAG -> getRegister ( Info ->

getScratchWaveOffsetReg ( ) , <STR_LIT> ) ;


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; SOffset = CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OMods ( SDValue In , SDValue & Src , SDValue & Clamp , SDValue & Omod ) const { Src = In ; SDLoc DL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , DL ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OMods ( SDValue In , SDValue & Src , SDValue & Clamp , SDValue & Omod ) const { Src = In


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ; AU . addRequired < DivergenceAnalysis


<s> unsigned AS = findMemSDNode ( N ) -> getAddressSpace ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , AS , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } else { SDLoc DL ( N ) ; uint64_t ImmField ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( AS , IsSigned ) ; if ( IsSigned ) { ImmField = SignExtend64 ( COffsetVal , NumBits ) ; if ( static_cast < int64_t > ( COffsetVal ) > <NUM_LIT> ) { if ( static_cast < int64_t > ( ImmField ) < <NUM_LIT> ) { const uint64_t OffsetMask = maskTrailingOnes < uint64_t > ( NumBits - <NUM_LIT> ) ; ImmField = COffsetVal & OffsetMask ; } } } else { const uint64_t OffsetMask = maskTrailingOnes < uint64_t > ( NumBits ) ; ImmField = COffsetVal & OffsetMask ; } uint64_t RemainderOffset = COffsetVal - ImmField ; assert ( TII -> isLegalFLATOffset ( ImmField , AS , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; OffsetVal = ImmField ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT>


<s> } if ( IsVALU ) { unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else { unsigned Opc = N -> getOpcode ( ) ==


<s> } case <STR_LIT> : { SelectFMUL_W_CHAIN ( N ) ; return ; } case <STR_LIT> : { SelectFMA_W_CHAIN ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) { if ( Opc == <STR_LIT> && NumVectorElts == <NUM_LIT> ) { if ( SDNode * Packed = packConstantV2I16 ( N , * CurDAG ) ) { ReplaceNode ( N , Packed ) ; return ; } } break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = <ISA_LIT>RegisterInfo :: getSGPRClassForBitWidth ( NumVectorElts * <NUM_LIT> ) -> getID ( ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT>


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) { if ( Opc == <STR_LIT> && NumVectorElts == <NUM_LIT> ) { if ( SDNode * Packed = packConstantV2I16 ( N , * CurDAG ) ) { ReplaceNode ( N , Packed ) ; return ; } } break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = selectSGPRVectorRegClassID ( NumVectorElts ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT>


<s> if ( In . getValueType ( ) == <STR_LIT> ) return SelectVOP3Mods ( In , Src , SrcMods ) ; Src = In


<s> const APInt & LHSKnownZeros = CurDAG -> computeKnownBits ( N -> getOperand ( <NUM_LIT> ) ) . Zero ; return ( LHSKnownZeros | RHS ) . countTrailingOnes (


<s> SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getBFE32 ( Signed , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : return SelectMUL_LOHI ( N ) ; case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : SelectFMAD_FMA ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT>


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Zero , Clamp } ; SDNode * Mad = CurDAG -> getMachineNode ( Opc , SL , N -> getVTList ( ) , Ops ) ; if ( ! SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) ; SDNode * Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SL , <STR_LIT> , SDValue ( Mad , <NUM_LIT> ) , Sub0 ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Lo , <NUM_LIT> ) ) ; } if ( ! SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) ; SDNode * Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , SL , <STR_LIT> , SDValue ( Mad , <NUM_LIT> ) , Sub1 ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Hi


<s> SDValue LHS , RHS ; if ( isBaseWithConstantOffset64 ( Addr , LHS , RHS ) ) { int64_t COffsetVal = cast < ConstantSDNode > ( RHS ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG ->

getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ;


<s> const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ; VAddr = SDValue ( VMov , <NUM_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3PModsDOT ( SDValue In , SDValue & Src , SDValue & SrcMods )


<s> if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap )


<s> bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineMemOperand * MMO = Mem -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( CmpSwap , { MMO } ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT


<s> if ( Addr . getValueType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Opnds ; Opnds . push_back ( N0 ) ; Opnds . push_back ( AddOffsetLo ) ; unsigned AddOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { AddOp = <STR_LIT> ; Opnds . push_back ( Clamp ) ; } Addr = SDValue ( CurDAG -> getMachineNode ( AddOp , DL , <STR_LIT> , Opnds ) , <NUM_LIT> ) ; } else { SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * N0Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub0 ) ; SDNode * N0Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub1 ) ; SDValue AddOffsetHi = getMaterializedScalarImm32 ( Hi_32 ( RemainderOffset ) , DL ) ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; SDNode * Add = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetLo , SDValue ( N0Lo , <NUM_LIT> ) , Clamp } ) ; SDNode * Addc = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetHi , SDValue ( N0Hi , <NUM_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Clamp } ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Sub0 , SDValue ( Addc , <NUM_LIT> ) , Sub1 } ; Addr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , RegSequenceArgs ) , <NUM_LIT> ) ; } } } } VAddr =


<s> void <ISA_LIT>DAGToDAGISel :: SelectFMA_W_CHAIN ( SDNode * N ) { SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; Ops [ <NUM_LIT> ] = N


<s> } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ; VOffset = SDValue ( VMov , <NUM_LIT> ) ; SAddr = LHS ; Offset = CurDAG -> getTargetConstant ( SplitImmOffset , SDLoc ( ) , <STR_LIT> ) ; return true ; } } } if ( Addr . getOpcode ( ) != <STR_LIT> ) { if ( Addr -> isDivergent ( ) || Addr . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Addr ) ) return false ; SAddr = Addr ; SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( Addr ) , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ) ; VOffset = SDValue ( VMov , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ImmOffset , SDLoc ( ) , <STR_LIT> ) ; return true ; } LHS = Addr . getOperand ( <NUM_LIT> ) ; RHS = Addr . getOperand ( <NUM_LIT> ) ; if ( ! LHS -> isDivergent ( ) ) { if ( SDValue ZextRHS = matchZExtFromI32 ( RHS ) ) { SAddr = LHS ; VOffset = ZextRHS ; } } if ( ! SAddr && ! RHS -> isDivergent ( ) ) { if ( SDValue ZextLHS = matchZExtFromI32 ( LHS ) ) { SAddr =


<s> if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ; VOffset = SDValue ( VMov , <NUM_LIT> ) ; SAddr = LHS ; Offset = CurDAG -> getTargetConstant ( SplitImmOffset , SDLoc ( ) , <STR_LIT> ) ; return true


<s> uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnesValue ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL , Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ; return


<s> bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 , Src2Mods ) ; assert ( ( IsFMA || ! Mode . FP32Denormals ) && <STR_LIT> ) ; if ( Sel0 || Sel1 || Sel2 ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( Src0Mods , SDLoc ( ) , <STR_LIT> ) , Src0 , CurDAG -> getTargetConstant ( Src1Mods , SDLoc ( ) , <STR_LIT> ) , Src1 , CurDAG -> getTargetConstant ( Src2Mods , SDLoc ( ) , <STR_LIT> ) , Src2 , CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) , Zero , Zero } ; CurDAG -> SelectNodeTo ( N , IsFMA ? <STR_LIT> : <STR_LIT> , <STR_LIT> , Ops ) ; } else


<s> if ( Subtarget -> hasFlatInstOffsets ( ) && ( ! Subtarget -> hasFlatSegmentOffsetBug ( ) || findMemSDNode ( N ) -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) && CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , findMemSDNode ( N ) -> getAddressSpace ( ) , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr =


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS128Bit8ByteAligned ( SDValue Addr , SDValue & Base

, SDValue & Offset0 , SDValue & Offset1 ) const {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS128Bit8ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const { return SelectDSReadWrite2 ( Addr , Base , Offset0


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue &


<s> case <STR_LIT> : case <STR_LIT> : { SelectUADDO_USUBO ( N ) ; return ; } case <STR_LIT> : { SelectFMUL_W_CHAIN ( N ) ; return ; } case <STR_LIT> : { SelectFMA_W_CHAIN ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) { if ( Opc == <STR_LIT> && NumVectorElts == <NUM_LIT> ) { uint32_t LHSVal , RHSVal ; if ( getConstantValue ( N -> getOperand ( <NUM_LIT> ) , LHSVal ) && getConstantValue ( N -> getOperand ( <NUM_LIT> ) , RHSVal ) ) { uint32_t K = LHSVal | ( RHSVal << <NUM_LIT> ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , CurDAG -> getTargetConstant ( K , SDLoc ( N ) , <STR_LIT> ) ) ; return ; } } break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = selectSGPRVectorRegClassID ( NumVectorElts ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate


<s> void <ISA_LIT>DAGToDAGISel :: SelectBRCOND ( SDNode * N ) { SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . isUndef ( ) ) { CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return ; } bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; unsigned CondReg = UseSCCBr ? <STR_LIT> : <STR_LIT> ; SDLoc SL ( N ) ; SDValue VCC = CurDAG -> getCopyToReg ( N -> getOperand ( <NUM_LIT> )


<s> unsigned Imm = CAddr -> getZExtValue ( ) ; SDValue HighBits = CurDAG -> getTargetConstant ( Imm & ~ <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovHighBits = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , HighBits ) ; VAddr = SDValue ( MovHighBits , <NUM_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( )


<s> return SelectFlatOffset ( Addr , VAddr , Offset , SLC


<s> SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( COffsetVal ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( )


<s> uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( COffsetVal ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ; Offset = CurDAG -> getTargetConstant ( OffsetVal ,


<s> SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isLegalMUBUFImmOffset ( C1 ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFScratchOffset ( SDNode * Root , SDValue Addr , SDValue & SRsrc , SDValue & SOffset , SDValue & Offset ) const { ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ; if ( ! CAddr || ! isLegalMUBUFImmOffset ( CAddr ) ) return false ; SDLoc DL ( Addr ) ; MachineFunction & MF = CurDAG


<s> if ( ! N -> readMem ( ) ) return false ; const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ; if ( CbId == - <NUM_LIT> ) return checkType ( MemVal , <ISA_LIT>AS ::


<s> bool <ISA_LIT>DAGToDAGISel :: isConstantLoad ( const MemSDNode * N , int CbId ) const { if ( ! N -> readMem ( ) ) return false ; const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ; if ( CbId == - <NUM_LIT> ) return checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; return checkType ( MemVal , <ISA_LIT>AS ::


<s> bool <ISA_LIT>DAGToDAGISel :: isFlatStore ( const MemSDNode * N ) { if ( ! N -> writeMem


<s> if ( N -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) { if ( Subtarget -> getGeneration ( ) < <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return ! isa < GlobalValue > ( GetUnderlyingObject ( N -> getMemOperand ( ) -> getValue ( ) , CurDAG ->


<s> if ( ! N -> writeMem ( ) ) return false ; return checkType ( N -> getMemOperand ( ) ->

getValue ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ;


<s> int64_t ByteOffset = C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( ByteOffset ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , ByteOffset , <NUM_LIT> ) ) { MachineSDNode * MachineSub = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode >


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isDSOffsetLegal ( N0 , C1 -> getSExtValue ( ) , <NUM_LIT> ) ) { Base = N0 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { int64_t ByteOffset = C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( ByteOffset ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , ByteOffset , <NUM_LIT> ) ) { MachineSDNode * MachineSub = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } else if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; VAddr = N1 ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUF ( SDValue Addr , SDValue & Ptr , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & Offen , SDValue & Idxen , SDValue & Addr64 , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { if ( Subtarget -> useFlatForGlobal ( ) ) return false ; SDLoc DL ( Addr ) ; if ( ! GLC . getNode ( ) ) GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( ! SLC . getNode ( ) ) SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand (


<s> if ( Imm >= <NUM_LIT> ) { if ( Imm <= <NUM_LIT> + <NUM_LIT> ) { Overflow = Imm - <NUM_LIT> ; Imm = <NUM_LIT> ; } else { uint32_t High = ( Imm + <NUM_LIT> ) & ~ <NUM_LIT> ; uint32_t Low = ( Imm + <NUM_LIT> ) & <NUM_LIT> ; Imm = Low ; Overflow = High - <NUM_LIT> ; } } ImmOffset = CurDAG -> getTargetConstant ( Imm , DL


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFIntrinsicOffset ( SDValue Offset , SDValue & SOffset , SDValue & ImmOffset ) const { SDLoc DL (


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFIntrinsicVOffset ( SDValue Offset , SDValue & SOffset , SDValue & ImmOffset , SDValue & VOffset ) const { SDLoc DL ( Offset ) ; if ( isa < ConstantSDNode > ( Offset ) ) return false ; if ( CurDAG -> isBaseWithConstantOffset ( Offset ) ) { SDValue N0 = Offset . getOperand ( <NUM_LIT>


<s> } } SDLoc DL ( Addr ) ; if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = Addr ; return true ; } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return true


<s> SDLoc DL ( Addr ) ; if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( N -> getOperand ( i ) ) ; Ops . push_back (


<s> SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) Ops


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue CarryIn = N -> getOperand ( <NUM_LIT> ) ; SDValue VCC = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , SL , <STR_LIT> , CarryIn , SDValue ( ) ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue CarryIn = N -> getOperand ( <NUM_LIT> ) ; SDValue VCC = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , SL , <STR_LIT> , CarryIn , SDValue ( ) ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT>


<s> bool IsGDS = M -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; SDValue Offset ; if ( CurDAG -> isBaseWithConstantOffset ( Ptr ) ) { SDValue PtrBase = Ptr . getOperand ( <NUM_LIT> ) ; SDValue PtrOffset = Ptr . getOperand ( <NUM_LIT> ) ; const APInt & OffsetVal = cast < ConstantSDNode > ( PtrOffset ) -> getAPIntValue ( ) ; if ( isDSOffsetLegal ( PtrBase , OffsetVal . getZExtValue ( ) , <NUM_LIT> ) ) { N = glueCopyToM0 ( N , PtrBase ) ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; } } if ( !


<s> SAddr = SelectSAddrFI ( CurDAG , SAddr ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ) { int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ; COffsetVal =


<s> SelectVOP3BMods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3BMods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3BMods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ]


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3BMods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT>


<s> SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( true ) ; int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; assert ( TII -> isLegalFLATOffset ( ImmField , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; COffsetVal = ImmField ; SDLoc DL ( N ) ; SDValue AddOffset = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SAddr , AddOffset )


<s> COffsetVal = cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SAddr = Addr . getOperand ( <NUM_LIT> ) ; } if ( auto FI = dyn_cast < FrameIndexSDNode > ( SAddr ) ) { SAddr = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; } else if ( SAddr . getOpcode ( ) == <STR_LIT> && isa < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ) { auto FI = cast < FrameIndexSDNode > ( SAddr . getOperand ( <NUM_LIT> ) ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( true ) ; int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; assert ( TII -> isLegalFLATOffset ( ImmField , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) ; assert ( RemainderOffset + ImmField == COffsetVal


<s> static bool isNullConstantOrUndef ( SDValue V ) { if ( V . isUndef ( ) ) return true ; ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( V ) ; return Const != nullptr && Const -> isZero


<s> ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( V ) ; return Const != nullptr && Const


<s> RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getBFE32 ( Signed , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : return SelectMUL_LOHI ( N ) ; case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : SelectFMAD_FMA (


<s> void <ISA_LIT>DAGToDAGISel :: SelectINTRIN<ISA_LIT>C_W_CHAIN ( SDNode * N ) { unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrID )


<s> unsigned PtrIdx = M -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( OpIdx == PtrIdx ) continue ; unsigned OpN = M -> getNumOperands ( ) ; SDValue NewOps [ <NUM_LIT> ] ; assert ( OpN < array_lengthof ( NewOps ) ) ; for ( unsigned Op = <NUM_LIT> ; Op != OpN ; ++ Op ) { if ( Op != OpIdx ) { NewOps [ Op ] = M -> getOperand ( Op ) ; continue ; } MachineSDNode * Mov = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( M ) , <STR_LIT> , FI ) ; NewOps [ Op ] = SDValue ( Mov , <NUM_LIT> ) ; } CurDAG -> UpdateNodeOperands ( M , makeArrayRef ( NewOps ,


<s> break ; } assert ( VT . getVectorElementType ( ) . bitsEq ( <STR_LIT> ) ) ; unsigned RegClassID = selectSGPRVectorRegClassID ( NumVectorElts ) ; SelectBuildVector ( N , RegClassID ) ; return ; } case <STR_LIT> : { SDValue RC , SubReg0 , SubReg1 ; SDLoc DL ( N ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ; SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm


<s> uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; unsigned AS = findMemSDNode ( N ) -> getAddressSpace ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , AS , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } else { SDLoc DL ( N ) ; uint64_t RemainderOffset = COffsetVal ; uint64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( IsSigned ) ; if ( IsSigned ) { int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( static_cast < int64_t > ( COffsetVal ) / D ) * D ; ImmField = COffsetVal - RemainderOffset ; } else if ( static_cast < int64_t > ( COffsetVal ) >= <NUM_LIT> ) { ImmField = COffsetVal & maskTrailingOnes < uint64_t > ( NumBits ) ; RemainderOffset = COffsetVal - ImmField ; } assert ( TII -> isLegalFLATOffset ( ImmField , AS , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; OffsetVal = ImmField ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT>


<s> } else if ( getBaseWithOffsetUsingSplitOR ( * CurDAG , Addr , N0 , N1 ) ) { assert ( N0 && N1 && isa < ConstantSDNode > ( N1 ) ) ; } if ( N0 && N1 ) { uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; unsigned AS = findMemSDNode ( N ) -> getAddressSpace ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , AS , IsSigned ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } else { SDLoc DL ( N ) ; uint64_t RemainderOffset = COffsetVal ; uint64_t ImmField = <NUM_LIT> ; const unsigned NumBits = TII -> getNumFlatOffsetBits ( IsSigned ) ; if ( IsSigned ) { int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( static_cast < int64_t > ( COffsetVal ) / D ) * D ; ImmField = COffsetVal - RemainderOffset ; } else if ( static_cast < int64_t > ( COffsetVal ) >= <NUM_LIT> ) { ImmField = COffsetVal & maskTrailingOnes < uint64_t > ( NumBits ) ; RemainderOffset = COffsetVal - ImmField ; } assert ( TII -> isLegalFLATOffset ( ImmField , AS , IsSigned ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; OffsetVal = ImmField ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * N0Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub0 ) ; SDNode * N0Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub1 ) ; SDValue AddOffsetLo = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ; SDValue AddOffsetHi = getMaterializedScalarImm32 ( Hi_32 ( RemainderOffset ) , DL ) ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * Add = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetLo , SDValue ( N0Lo , <NUM_LIT> ) , Clamp } ) ; SDNode * Addc = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetHi , SDValue ( N0Hi , <NUM_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Clamp } ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Add , <NUM_LIT> )

, Sub0 , SDValue ( Addc , <NUM_LIT> ) , Sub1 } ;


<s> if ( Subtarget -> getGeneration ( ) < <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return ! isa < GlobalValue > ( GetUnderlyingObject ( N -> getMemOperand ( ) -> getValue (


<s> MachineSDNode * <ISA_LIT>DAGToDAGISel :: buildSMovImm64 ( SDLoc & DL , uint64_t Imm , EVT VT ) const { SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ; SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm >> <NUM_LIT> , DL , <STR_LIT> ) ) ; const SDValue Ops [


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( TargetMachine *


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( TargetMachine * TM ,


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel )


<s> const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , Addr , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL

, <STR_LIT> , AddrHi ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , SL , <STR_LIT> ) , } ;


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ; AU . addRequired < <ISA_LIT>PerfHintAnalysis >


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ; AU . addRequired < <ISA_LIT>PerfHintAnalysis > ( ) ; AU . addRequired < DivergenceAnalysis > ( ) ; SelectionDAGISel :: getAnalysisUsage


<s> Out = C -> getAPIntValue ( ) . getSExtValue ( ) ; return true ; } if ( const ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode


<s> return MRI . getRegClass ( Reg ) ; } const <ISA_LIT>RegisterInfo * TRI = static_cast < const GCNSubtarget * > ( Subtarget ) -> getRegisterInfo ( ) ; return TRI -> getPhysRegClass ( Reg ) ; } return nullptr ; } switch ( N -> getMachineOpcode ( ) ) { default : { const MCInstrDesc & Desc = Subtarget -> getInstrInfo ( ) -> get ( N -> getMachineOpcode ( ) ) ; unsigned OpIdx = Desc . getNumDefs ( ) + OpNo ; if ( OpIdx >= Desc . getNumOperands ( ) ) return nullptr ; int RegClass = Desc . OpInfo [ OpIdx ] . RegClass ; if ( RegClass == - <NUM_LIT> ) return nullptr ; return Subtarget -> getRegisterInfo ( ) -> getRegClass ( RegClass ) ; } case <STR_LIT> : { unsigned RCID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const TargetRegisterClass * SuperRC = Subtarget -> getRegisterInfo ( ) -> getRegClass


<s> uint32_t PackedVal = Offset | ( Width << <NUM_LIT> ) ; SDValue PackedConst = CurDAG -> getTargetConstant ( PackedVal , DL , <STR_LIT> ) ; return CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Val ,


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Glue ) ; return CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , N


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i )


<s> if ( VT == <STR_LIT> ) { auto ST = static_cast < const GCNSubtarget * > ( Subtarget ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return ( CC == <STR_LIT> || CC == <STR_LIT> ) && ST -> hasScalarCompareEq64 ( ) ; } return false


<s> if ( ! N -> readMem ( ) ) return false ; if ( CbId == - <NUM_LIT> ) return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT>

. CONSTANT_ADDRESS || N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT ;


<s> if ( CbId == - <NUM_LIT> ) return N -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || N -> getAddressSpace ( ) ==


<s> In = stripBitcast ( In ) ; if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftAmt -> getZExtValue ( ) ==


<s> if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftAmt -> getZExtValue ( ) == <NUM_LIT> ) { Out = stripBitcast ( Srl . getOperand ( <NUM_LIT> ) ) ; return true ; } } } return


<s> return <STR_LIT> ( Imm , Subtarget ->


<s> bool isInlineImmediate16 ( int64_t Imm ) const { return <STR_LIT> ( Imm , Subtarget


<s> bool isInlineImmediate32 ( int64_t Imm )


<s> return <STR_LIT> ( Imm , Subtarget -> hasInv2PiInlineImm


<s> bool isNegInlineImmediate ( const SDNode


<s> static inline bool isNullConstantOrUndef ( SDValue V ) { if ( V . isUndef ( ) )


<s> static inline SDNode * packNegConstantV2I16 ( const SDNode * N , SelectionDAG


<s> bool IsModified = false ; do { IsModified = false ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ; while ( Position != CurDAG -> allnodes_end ( ) ) { SDNode * Node = & * Position ++ ; MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( Node ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { if ( ResNode ) ReplaceUses ( Node , ResNode ) ; IsModified = true ; } } CurDAG -> RemoveDeadNodes ( ) ; } while (


<s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool IsModified = false ; do { IsModified = false ; SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction &


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; unsigned RegClassID ; switch ( NumVectorElts ) { case <NUM_LIT> : RegClassID = <STR_LIT> ; break ; case


<s> if ( Addr . getOpcode ( ) == <STR_LIT> && ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset ->


<s> AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ; } SDValue AddHiArgs [ ] = { SDValue ( Hi0 , <NUM_LIT> ) , SDValue ( Hi1 , <NUM_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) } ; SDNode * AddHi = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , AddHiArgs ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( AddLo , <NUM_LIT> ) , Sub0 , SDValue ( AddHi , <NUM_LIT> ) , Sub1 , } ; SDNode * RegSequence = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , RegSequenceArgs ) ; if ( ProduceCarry ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( AddHi , <NUM_LIT> ) ) ; } ReplaceNode ( N , RegSequence )


<s> if ( Cond . isUndef ( ) ) { CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return ; } bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; unsigned CondReg = UseSCCBr ? <STR_LIT> : <STR_LIT> ; SDLoc SL ( N


<s> void <ISA_LIT>DAGToDAGISel :: SelectDIV_SCALE ( SDNode * N ) { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT>


<s> unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc ,


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const { SDLoc DL ( Addr ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; unsigned DWordOffset0 = C1 -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isDSOffsetLegal ( N0 , DWordOffset1 , <NUM_LIT> ) ) { Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned DWordOffset0 = C -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isUInt < <NUM_LIT> > ( DWordOffset0 ) ) { SDLoc DL ( Addr ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , DWordOffset1 , <NUM_LIT> ) ) { unsigned SubOp = Subtarget -> hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFlatAtomic ( SDValue Addr , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { return SelectFlatOffset < false > ( Addr , VAddr , Offset


<s> int64_t OffsetVal = <NUM_LIT> ; if ( Subtarget -> hasFlatInstOffsets ( ) && CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) ,


<s> void <ISA_LIT>DAGToDAGISel :: SelectFMAD_FMA ( SDNode * N ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; bool IsFMA = N -> getOpcode ( ) == <STR_LIT> ; if ( VT != <STR_LIT> || ( ! Subtarget -> hasMadMixInsts ( ) && ! Subtarget -> hasFmaMixInsts ( ) ) || ( ( IsFMA && Subtarget -> hasMadMixInsts ( ) ) || ( ! IsFMA && Subtarget -> hasFmaMixInsts ( ) ) ) ) { SelectCode ( N ) ; return ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; unsigned Src0Mods , Src1Mods , Src2Mods ; bool Sel0 = SelectVOP3PMadMixModsImpl ( Src0 , Src0 , Src0Mods ) ; bool Sel1 = SelectVOP3PMadMixModsImpl ( Src1 , Src1 , Src1Mods ) ; bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 ,


<s> SelectCode ( N ) ; return ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = N -> getOperand ( <NUM_LIT> ) ; unsigned Src0Mods , Src1Mods , Src2Mods ; bool Sel0 = SelectVOP3PMadMixModsImpl ( Src0 , Src0 , Src0Mods ) ; bool Sel1 = SelectVOP3PMadMixModsImpl ( Src1 , Src1 , Src1Mods ) ; bool Sel2 = SelectVOP3PMadMixModsImpl ( Src2 , Src2 , Src2Mods ) ; assert ( ( IsFMA || ! Subtarget -> hasFP32Denormals


<s> Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , N ->


<s> SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [


<s> void <ISA_LIT>DAGToDAGISel :: SelectFMUL_W_CHAIN ( SDNode * N ) { SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; } return


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Clamp } ; CurDAG -> SelectNodeTo ( N , Opc , N


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; unsigned Opc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT>


<s> if ( CurDAG -> isBaseWithConstantOffset ( Index ) ) { SDValue N0 = Index . getOperand ( <NUM_LIT> ) ; SDValue N1 = Index . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > (


<s> } else { uint32_t High = ( Imm + Align ) & ~ <NUM_LIT> ; uint32_t Low = ( Imm + Align ) & <NUM_LIT> ; Imm = Low ; Overflow = High - Align ; } } if ( Overflow > <NUM_LIT> && Subtarget -> getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) return false ; ImmOffset = CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ; if ( Overflow <= <NUM_LIT> ) SOffset = CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) ; else SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) )


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFIntrinsicOffset ( SDValue Offset , SDValue &


<s> if ( cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) >= <NUM_LIT> && SelectMUBUFConstant ( N1 , SOffset , ImmOffset ) ) { VOffset = N0 ; return true ; } } SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; VOffset =


<s> if ( isa < ConstantSDNode > ( Offset ) ) { SDValue Tmp1 , Tmp2 ; if ( Subtarget -> getGeneration ( ) > <ISA_LIT>Subtarget :: SEA_ISLANDS || SelectMUBUFConstant ( Offset , Tmp1 , Tmp2 ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Offset ) ) { SDValue N0 = Offset . getOperand ( <NUM_LIT> ) ; SDValue N1 = Offset . getOperand ( <NUM_LIT>


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFOffset ( SDValue Addr , SDValue & SRsrc , SDValue & Soffset , SDValue & Offset , SDValue


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFOffset ( SDValue Addr , SDValue & SRsrc , SDValue & Soffset , SDValue & Offset , SDValue & SLC ) const { SDValue GLC , TFE ; return SelectMUBUFOffset ( Addr , SRsrc , Soffset , Offset


<s> const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } std :: tie ( VAddr , SOffset ) = foldFrameIndex ( Addr ) ; ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> ,


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info ->


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; unsigned SOffsetReg = isStackPtrRelative ( PtrInfo ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; SOffset = CurDAG -> getRegister ( SOffsetReg , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT>