<s> EVT eltVT = vecVT . getVectorElementType ( ) ; SDNode * bvNode = build_vec . getNode ( ) ; DebugLoc dl = bvNode -> getDebugLoc ( ) ; if ( ( ( vecVT == <STR_LIT> ) && ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG ) . getNode ( ) != <NUM_LIT> ) ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) ) ) return Select ( build_vec ) ; std :: vector < Constant * > CV ; for ( size_t i = <NUM_LIT> ; i < build_vec . getNumOperands ( ) ; ++ i ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( build_vec . getOperand ( i ) ) ; CV . push_back ( const_cast < ConstantInt * > ( V -> getConstantIntValue ( ) ) ) ; } Constant * CP = ConstantVector :: get ( CV ) ; SDValue CPIdx = CurDAG -> getConstantPool ( CP , <ISA_LIT>tli . getPointerTy ( ) ) ;

unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ;


<s> SDNode * emitBuildVector ( SDValue build_vec ) { EVT vecVT = build_vec . getValueType ( ) ; EVT eltVT = vecVT . getVectorElementType ( ) ; SDNode * bvNode = build_vec . getNode ( ) ; DebugLoc dl = bvNode -> getDebugLoc ( ) ; if ( ( ( vecVT == <STR_LIT> ) && ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG ) . getNode ( ) != <NUM_LIT> ) ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) ) ) return Select ( build_vec ) ; std :: vector < Constant * > CV ; for ( size_t i = <NUM_LIT> ; i < build_vec . getNumOperands ( ) ; ++ i ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( build_vec . getOperand ( i ) ) ; CV . push_back ( const_cast < ConstantInt * > ( V -> getConstantIntValue ( ) ) ) ; } Constant * CP = ConstantVector :: get ( CV ) ; SDValue CPIdx = CurDAG -> getConstantPool ( CP , <ISA_LIT>tli . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ;

SDValue CGPoolOffset = <STR_LIT> ( CPIdx , * CurDAG , <ISA_LIT>tli . get<ISA_LIT>TargetMachine ( ) ) ;


<s> raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << VT . getEVTString ( ) ; llvm_report_error ( Msg . str ( ) ) ; } return retval ;


<s> switch ( Op0 . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Base = Op0 ; Index = Zero ; return true ; case <STR_LIT> : { GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op0 ) ; GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( GV -> getAlignment ( ) == <NUM_LIT> ) { Base = Op0 ; Index = Zero ; return true ; } break ; } } }


<s> } else if ( i64vec . getOpcode ( ) == <STR_LIT> ) { SDValue lhs = i64vec . getOperand ( <NUM_LIT> ) ; SDValue rhs = i64vec . getOperand ( <NUM_LIT> ) ; SDValue shufmask = i64vec . getOperand ( <NUM_LIT> ) ; if ( lhs . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( lhs , lhs . getOperand ( <NUM_LIT> ) ) ; lhs = lhs . getOperand ( <NUM_LIT> ) ; } SDNode * lhsNode = ( lhs . getNode ( ) -> isMachineOpcode ( ) ? lhs . getNode ( ) : emitBuildVector ( lhs ) ) ; if ( rhs . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( rhs , rhs . getOperand ( <NUM_LIT> ) ) ;


<s> Op1 = getSmallIPtrImm ( <NUM_LIT> ) ; } break ; case 'v' : llvm_unreachable ( <STR_LIT> ) ; SelectAddrIdxOnly ( Op , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ;


<s> VecOp0 = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ZeroFill , <NUM_LIT> ) , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( SelMask , <NUM_LIT> ) ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : VecOp0 ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * Bytes = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; SDNode * Bits = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( Bytes , <NUM_LIT> ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( Shift , <NUM_LIT> ) , SDValue ( Bits , <NUM_LIT> ) ) ;


<s> SDNode * Shift = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { bytes = <NUM_LIT> - bytes ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { bits = <NUM_LIT> - bits ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : UpperLowerSelect ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * NegShift = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , SDValue ( NegShift , <NUM_LIT> ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( Shift , <NUM_LIT> ) , SDValue ( NegShift , <NUM_LIT> ) ) ;


<s> if ( bytes > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : VecOp0 ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * Bytes = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; SDNode * Bits = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Bytes = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , SDValue ( Bytes , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Bits = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , SDValue ( Bits , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( Bytes , <NUM_LIT> ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( Shift , <NUM_LIT> ) , SDValue ( Bits , <NUM_LIT> ) ) ; } return CurDAG -> getTargetNode ( <STR_LIT> , dl , OpVT , SDValue ( Shift , <NUM_LIT> ) ) ;


<s> SDNode * emitBuildVector ( SDNode * bvNode ) { EVT vecVT = bvNode -> getValueType ( <NUM_LIT> ) ; EVT eltVT = vecVT . getVectorElementType ( ) ; DebugLoc dl = bvNode -> getDebugLoc ( ) ; if ( ( ( vecVT == <STR_LIT> ) && ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG ) . getNode ( ) != <NUM_LIT> ) ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) ) ) { HandleSDNode Dummy ( SDValue ( bvNode , <NUM_LIT> ) ) ; if ( SDNode * N = Select ( bvNode ) ) return N ; return Dummy . getValue ( ) . getNode ( ) ; } std :: vector < Constant * > CV ; for ( size_t i = <NUM_LIT> ; i < bvNode -> getNumOperands ( ) ; ++ i ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( bvNode -> getOperand ( i ) ) ; CV . push_back ( const_cast < ConstantInt * > ( V -> getConstantIntValue ( ) ) ) ; }

Constant * CP = ConstantVector :: get ( CV ) ;


<s> EVT OffsVT = <STR_LIT> ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , OffsVT ) ; switch ( N . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_report_error ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_report_error ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : if ( N . hasOneUse ( ) ) { SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; switch ( Op0 . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Base = Op0 ; Index = Zero ; return true ; case <STR_LIT> : { GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op0 ) ; GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( GV -> getAlignment ( ) == <NUM_LIT> ) { Base = Op0 ; Index = Zero ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_report_error ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : if ( N . hasOneUse ( ) ) { SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; switch ( Op0 . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Base = Op0 ; Index = Zero ; return true ; case <STR_LIT> : {

GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op0 ) ;


<s> SDValue Op0 = i64vec . getOperand ( <NUM_LIT> ) ; ReplaceUses ( i64vec , Op0 ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , OpVT , SDValue ( emitBuildVector ( Op0 . getNode ( ) ) , <NUM_LIT> ) ) ; } else if ( i64vec . getOpcode ( ) == <STR_LIT> ) { SDValue lhs = i64vec . getOperand ( <NUM_LIT> ) ; SDValue rhs = i64vec . getOperand ( <NUM_LIT> ) ; SDValue shufmask = i64vec . getOperand ( <NUM_LIT> ) ; if ( lhs . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( lhs , lhs . getOperand ( <NUM_LIT> ) ) ; lhs = lhs . getOperand ( <NUM_LIT> ) ; } SDNode * lhsNode = ( lhs . getNode ( ) -> isMachineOpcode ( ) ? lhs . getNode ( ) : emitBuildVector ( lhs . getNode ( ) ) ) ; if ( rhs . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( rhs , rhs . getOperand ( <NUM_LIT> ) ) ; rhs = rhs . getOperand ( <NUM_LIT> ) ; } SDNode * rhsNode = ( rhs . getNode ( ) -> isMachineOpcode ( ) ? rhs . getNode ( ) : emitBuildVector ( rhs . getNode ( ) ) ) ; if ( shufmask . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( shufmask , shufmask . getOperand ( <NUM_LIT> ) ) ; shufmask = shufmask . getOperand ( <NUM_LIT> ) ; } SDNode * shufMaskNode = ( shufmask . getNode ( ) -> isMachineOpcode ( ) ? shufmask . getNode ( ) : emitBuildVector ( shufmask . getNode ( ) ) ) ; SDValue shufNode = CurDAG -> getNode ( <STR_LIT> , dl , OpVecVT , SDValue ( lhsNode , <NUM_LIT> ) , SDValue ( rhsNode , <NUM_LIT> ) , SDValue ( shufMaskNode , <NUM_LIT> ) ) ; HandleSDNode Dummy ( shufNode ) ; SDNode * SN = SelectCode ( Dummy . getValue ( ) . getNode ( ) ) ; if ( SN == <NUM_LIT> ) SN = Dummy . getValue ( ) . getNode ( ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , OpVT , SDValue ( SN , <NUM_LIT> ) ) ; } else if ( i64vec . getOpcode ( ) == <STR_LIT> ) { return CurDAG -> getMachineNode ( <STR_LIT> , dl , OpVT , SDValue ( emitBuildVector ( i64vec . getNode ( ) ) , <NUM_LIT> ) ) ; } else { llvm_report_error ( <STR_LIT> <STR_LIT> ) ;


<s> SDNode * shufMaskNode = ( shufmask . getNode ( ) -> isMachineOpcode ( ) ? shufmask . getNode ( ) : emitBuildVector ( shufmask . getNode ( ) ) ) ; SDValue shufNode = CurDAG -> getNode ( <STR_LIT> , dl , OpVecVT , SDValue ( lhsNode , <NUM_LIT> ) , SDValue ( rhsNode , <NUM_LIT> ) , SDValue ( shufMaskNode , <NUM_LIT> ) ) ; HandleSDNode Dummy ( shufNode ) ; SDNode * SN = SelectCode ( Dummy . getValue ( ) . getNode ( ) ) ; if ( SN == <NUM_LIT> ) SN = Dummy . getValue ( ) . getNode ( ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , OpVT , SDValue ( SN , <NUM_LIT> ) ) ; } else if ( i64vec . getOpcode ( ) == <STR_LIT> ) { return CurDAG -> getMachineNode ( <STR_LIT> , dl , OpVT , SDValue ( emitBuildVector ( i64vec . getNode ( ) ) , <NUM_LIT> ) ) ;


<s> static bool isFPS16Immediate ( ConstantFPSDNode * FPN , short & Imm ) { EVT vt = FPN -> getValueType ( <NUM_LIT> ) ;


<s> EVT vt = CN -> getValueType ( <NUM_LIT> ) ; Imm = ( short ) CN -> getZExtValue ( ) ; if ( vt . getSimpleVT ( ) >= <STR_LIT> && vt . getSimpleVT ( ) <= <STR_LIT> ) { return true ; } else if ( vt == <STR_LIT> ) { int32_t i_val = ( int32_t ) CN -> getZExtValue ( ) ; return i_val == SignExtend32 < <NUM_LIT> > ( i_val ) ; } else { int64_t i_val = ( int64_t ) CN -> getZExtValue ( ) ; return i_val == SignExtend64 < <NUM_LIT> > ( i_val ) ; }


<s> return i_val == SignExtend32 < <NUM_LIT> > ( i_val ) ; } else { int64_t i_val = ( int64_t ) CN -> getZExtValue ( ) ; return i_val == SignExtend64 < <NUM_LIT> > ( i_val ) ; }


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) {

return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op1 ; return true ; } } } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ; Index = N ; return true ; } else if ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 ) ) { int32_t offset = <NUM_LIT> ; SDValue idxOp ; if ( isa < ConstantSDNode > ( Op1 ) ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op1 ) ; offset = int32_t ( CN -> getSExtValue ( ) ) ; idxOp = Op0 ; } else if ( isa < ConstantSDNode > ( Op0 ) ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 ) ; offset = int32_t ( CN -> getSExtValue ( ) ) ; idxOp = Op1 ; } if ( offset >= minOffset && offset <= maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = idxOp ; return true ; } } } else if ( Opc == <STR_LIT> ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , N . getValueType ( ) ) ; Index = N ; return true ; } else if ( Opc == <STR_LIT> ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , N . getValueType ( ) ) ; Index = N ; return true ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned OpOpc = Op -> getOpcode ( ) ; if ( OpOpc == <STR_LIT> || OpOpc == <STR_LIT> ) { SDValue Offs ; Offs = ( ( OpOpc == <STR_LIT> ) ? Op -> getOperand ( <NUM_LIT> ) : Op -> getOperand ( <NUM_LIT> ) ) ; if ( Offs . getOpcode ( ) == <STR_LIT> || Offs . getOpcode ( ) == <STR_LIT> ) { if ( Offs . getOpcode ( ) == <STR_LIT> ) Offs = CurDAG -> getTargetConstant ( <NUM_LIT> , Offs . getValueType ( ) ) ; Base = Offs ; Index = N ;


<s> } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; if ( ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) || ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ; Index = N ; return true ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> || Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op1 ) ; int32_t offset = int32_t ( CN -> getSExtValue ( ) ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op0 ) ; int FI = int ( FIN -> getIndex ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << offset << <STR_LIT> << FI << <STR_LIT> ) ; if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op0 ; return true ; } } else if ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 ) ; int32_t offset = int32_t ( CN -> getSExtValue ( ) ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op1 ) ; int FI = int ( FIN -> getIndex ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << offset << <STR_LIT> << FI << <STR_LIT> ) ; if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op1 ; return true ; } } } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ;

if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) {


<s> return Dummy . getValue ( ) . getNode ( ) ; } std :: vector < Constant * > CV ; for ( size_t i = <NUM_LIT> ; i < bvNode -> getNumOperands ( ) ; ++ i ) { ConstantSDNode * V = cast < ConstantSDNode > ( bvNode -> getOperand ( i ) ) ; CV . push_back ( const_cast < ConstantInt * > ( V -> getConstantIntValue ( ) ) ) ; } const Constant * CP = ConstantVector :: get ( CV ) ; SDValue CPIdx = CurDAG -> getConstantPool ( CP , <ISA_LIT>tli . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue CGPoolOffset = <STR_LIT> ( CPIdx , * CurDAG , TM ) ; HandleSDNode Dummy ( CurDAG -> getLoad ( vecVT , dl , CurDAG -> getEntryNode ( ) , CGPoolOffset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ) ; CurDAG -> ReplaceAllUsesWith ( SDValue ( bvNode , <NUM_LIT> ) , Dummy . getValue ( ) ) ;

if ( SDNode * N = SelectCode ( Dummy . getValue ( ) . getNode ( ) ) ) return N ;


<s> SDValue getBorrowGenerateShufMask ( SelectionDAG & DAG , DebugLoc dl ) { SmallVector < SDValue , <NUM_LIT> > ShufBytes ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > ShufBytes ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ShufBytes . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> inline SDValue getI32Imm ( uint32_t Imm ) {

return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> inline SDValue getSmallIPtrImm ( unsigned Imm ) {

return CurDAG -> getTargetConstant ( Imm , <ISA_LIT>tli . getPointerTy ( ) ) ;


<s> int sval = ( int ) ( ( val << <NUM_LIT> ) >> <NUM_LIT> ) ; Imm = ( short ) val ; return val == sval ; }


<s> static bool isFPS16Immediate ( ConstantFPSDNode * FPN , short & Imm ) { EVT vt = FPN -> getValueType ( <NUM_LIT> ) ; if ( vt == <STR_LIT> ) { int val = FloatToBits ( FPN -> getValueAPF ( ) . convertToFloat ( ) ) ; int sval = ( int ) ( ( val << <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> return isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ;


<s> return isUInt < <NUM_LIT> > ( ( short ) CN -> getZExtValue ( ) ) ;


<s> return isUInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ;


<s> bool isIntS16Immediate ( ConstantSDNode * CN , short & Imm ) { EVT vt = CN -> getValueType ( <NUM_LIT> ) ; Imm = ( short ) CN -> getZExtValue ( ) ;

if ( vt . getSimpleVT ( ) >= <STR_LIT> && vt . getSimpleVT ( ) <= <STR_LIT> ) {


<s> GlobalBaseReg = <NUM_LIT> ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ;


SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> const int maxDForm2Offset = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ;

return DFormAddressPredicate ( Op , N , Disp , Base , minDForm2Offset , maxDForm2Offset ) ;


<s> const int maxDForm2Offset = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; return DFormAddressPredicate ( Op , N , Disp , Base , minDForm2Offset , maxDForm2Offset ) ;


<s> return DFormAddressPredicate ( Op , N , Base , Index , <ISA_LIT>FrameLowering :: minFrameOffset ( ) , <ISA_LIT>FrameLowering :: maxFrameOffset ( ) ) ;


<s> if ( rhs . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( rhs , rhs . getOperand ( <NUM_LIT> ) ) ; rhs = rhs . getOperand ( <NUM_LIT> ) ; } SDNode * rhsNode = ( rhs . getNode ( ) -> isMachineOpcode ( ) ? rhs . getNode ( ) : emitBuildVector ( rhs . getNode ( ) ) ) ; if ( shufmask . getOpcode ( ) == <STR_LIT> ) { ReplaceUses ( shufmask , shufmask . getOperand ( <NUM_LIT> ) ) ; shufmask = shufmask . getOperand ( <NUM_LIT> ) ; } SDNode * shufMaskNode = ( shufmask . getNode ( ) -> isMachineOpcode ( ) ? shufmask . getNode ( ) : emitBuildVector ( shufmask . getNode ( ) ) ) ; SDValue shufNode = CurDAG -> getNode ( <STR_LIT> , dl , OpVecVT , SDValue ( lhsNode , <NUM_LIT> ) , SDValue ( rhsNode , <NUM_LIT> ) , SDValue ( shufMaskNode , <NUM_LIT> ) ) ; HandleSDNode Dummy ( shufNode ) ; SDNode * SN = SelectCode ( Dummy . getValue ( ) . getNode ( ) ) ;

if ( SN == <NUM_LIT> ) SN = Dummy . getValue ( ) . getNode ( ) ;


<s> switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectDFormAddr ( Op . getNode ( ) , Op , Op0 , Op1 ) && ! SelectAFormAddr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) SelectXFormAddr ( Op . getNode ( ) , Op , Op0 , Op1 ) ; break ;


<s> if ( bits > <NUM_LIT> ) { Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : VecOp0 ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * Bytes = CurDAG -> getMachineNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; SDNode * Bits = CurDAG -> getMachineNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( Bytes , <NUM_LIT> ) ) ; Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( Shift , <NUM_LIT> ) , SDValue ( Bits , <NUM_LIT> ) ) ; } return CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , OpVT , SDValue ( Shift , <NUM_LIT> ) , getRC ( <STR_LIT> ) ) ;


<s> SDNode * UpperHalfSign = CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , <STR_LIT> , SDValue ( SignRot , <NUM_LIT> ) , getRC ( <STR_LIT> ) ) ; SDNode * UpperHalfSignMask = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSign , <NUM_LIT> ) ) ; SDNode * UpperLowerMask = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDNode * UpperLowerSelect = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSignMask , <NUM_LIT> ) , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( UpperLowerMask , <NUM_LIT> ) ) ; SDNode * Shift = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { bytes = <NUM_LIT> - bytes ;

Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VecVT = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , OpVT , ( <NUM_LIT> / OpVT . getSizeInBits ( ) ) ) ; SDValue ShiftAmt = N -> getOperand ( <NUM_LIT> ) ; EVT ShiftAmtVT = ShiftAmt . getValueType ( ) ; SDNode * VecOp0 , * Shift = <NUM_LIT> ; DebugLoc dl = N -> getDebugLoc ( ) ; VecOp0 = CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , VecVT , Op0 , getRC ( <STR_LIT> ) ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectSRLi64 ( SDNode * N , EVT OpVT ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VecVT = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , OpVT , ( <NUM_LIT> / OpVT . getSizeInBits ( ) ) ) ; SDValue ShiftAmt = N -> getOperand ( <NUM_LIT> ) ; EVT ShiftAmtVT = ShiftAmt . getValueType ( ) ; SDNode * VecOp0 , * Shift = <NUM_LIT> ; DebugLoc dl = N -> getDebugLoc ( ) ; VecOp0 = CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , VecVT , Op0 , getRC ( <STR_LIT> ) ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectXFormAddr ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Index ) { if ( ! SelectAFormAddr ( Op , N , Base , Index ) && ! SelectDFormAddr ( Op , N , Base , Index ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectXFormAddr ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Index ) { if ( ! SelectAFormAddr ( Op , N , Base , Index ) && ! SelectDFormAddr ( Op , N , Base , Index ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , <ISA_LIT>tli ( * tm . getTargetLowering ( ) ) {


<s> if ( valtype_map [ i ] . valtype == VT ) { retval = valtype_map + i ; break ; } } if ( retval == <NUM_LIT> ) { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << VT . getEVTString ( ) ;


<s> if ( retval == <NUM_LIT> ) { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << VT . getEVTString ( ) ; llvm_report_error ( Msg . str ( ) ) ;


<s> SDValue <STR_LIT> ( SDNode * N , SelectionDAG & DAG , EVT ValueType ) { if ( ConstantSDNode * CN = getVecImm ( N ) ) { int64_t Value = CN -> getSExtValue ( ) ;


<s> case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , T , T , T , T ) ; }


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; const TargetMachine & TM = DAG . getTarget ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } }


<s> } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { VarArgsFrameIndex = MFI -> CreateFixedObject ( StackSlotSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; SDValue ArgVal = DAG . getRegister ( ArgRegs [ ArgRegIdx ] , <STR_LIT> ) ;

SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } else {


<s> SDValue lhsHi32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , IntVT , i64lhs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; SDValue lhsHi32abs = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , lhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue lhsLo32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , i64lhs ) ; if ( CC -> get ( ) == <STR_LIT> ) { APInt ccResultAllOnes = APInt :: getAllOnesValue ( ccResultVT . getSizeInBits ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhs , DAG . getConstantFP ( <NUM_LIT> , lhsVT ) , <STR_LIT> ) , DAG . getConstant ( ccResultAllOnes , ccResultVT ) ) ; } else if ( CC -> get ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhsHi32abs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) , DAG . getSetCC ( dl , ccResultVT , lhsLo32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ) ; } SDValue i64rhs = DAG . getNode ( <STR_LIT> , dl , IntVT , rhs ) ; SDValue rhsHi32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , IntVT , i64rhs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; SDValue signMag2TC = DAG . getConstant ( <NUM_LIT> , IntVT ) ; SDValue lhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , lhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue lhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64lhs ) ; SDValue lhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , lhsSelectMask , lhsSignMag2TC , i64lhs ) ; SDValue rhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , rhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue rhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64rhs ) ; SDValue rhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , rhsSelectMask , rhsSignMag2TC , i64rhs ) ; unsigned compareOp ; switch ( CC -> get ( ) ) { case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> :


<s> } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } alignLoadVec = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , SN -> getSrcValue ( ) , SN -> getSrcValueOffset ( ) , SN -> isVolatile ( ) , SN -> isNonTemporal ( ) , <NUM_LIT> ) ; the_chain = alignLoadVec . getValue ( <NUM_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( alignLoadVec ) ; SDValue theValue = SN -> getValue ( ) ; SDValue result ; if ( StVT != VT && ( theValue . getOpcode ( ) == <STR_LIT> || theValue . getOpcode ( ) == <STR_LIT> ) ) { theValue = theValue . getOperand ( <NUM_LIT> ) ; } if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { errs ( ) << <STR_LIT> ; basePtr . getNode ( ) -> dump ( & DAG ) ; errs ( ) << <STR_LIT> ; } SDValue insertEltOp = DAG . getNode ( <STR_LIT> , dl , vecVT , insertEltOffs ) ; SDValue vectorizeOp = DAG . getNode ( <STR_LIT> , dl , vecVT , theValue ) ; result = DAG . getNode ( <STR_LIT> , dl , vecVT , vectorizeOp , alignLoadVec , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , insertEltOp ) ) ; result = DAG . getStore ( the_chain , dl , result , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , LN -> getAlignment ( ) ) ; if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { const SDValue & currentRoot = DAG . getRoot ( ) ; DAG . setRoot ( result ) ; errs ( ) << <STR_LIT> ; DAG . dump ( ) ; errs ( ) << <STR_LIT> ; DAG . setRoot ( currentRoot ) ; } return result ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {


<s> SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } alignLoadVec = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , SN -> getSrcValue ( ) , SN -> getSrcValueOffset ( ) , SN -> isVolatile ( ) , SN -> isNonTemporal ( ) , <NUM_LIT> ) ; the_chain = alignLoadVec . getValue ( <NUM_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( alignLoadVec ) ; SDValue theValue = SN -> getValue ( ) ; SDValue result ; if ( StVT != VT && ( theValue . getOpcode ( ) == <STR_LIT> || theValue . getOpcode ( ) == <STR_LIT> ) ) { theValue = theValue . getOperand ( <NUM_LIT> ) ; } if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { errs ( ) << <STR_LIT> ; basePtr . getNode ( ) -> dump ( & DAG ) ; errs ( ) << <STR_LIT> ; } SDValue insertEltOp = DAG . getNode ( <STR_LIT> , dl , vecVT , insertEltOffs ) ; SDValue vectorizeOp = DAG . getNode ( <STR_LIT> , dl , vecVT , theValue ) ; result = DAG . getNode ( <STR_LIT> , dl , vecVT , vectorizeOp , alignLoadVec , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , insertEltOp ) ) ; result = DAG . getStore ( the_chain , dl , result , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , LN -> getAlignment ( ) ) ; if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { const SDValue & currentRoot = DAG . getRoot ( ) ; DAG . setRoot ( result ) ; errs ( ) << <STR_LIT> ; DAG . dump ( ) ; errs ( ) << <STR_LIT> ; DAG . setRoot ( currentRoot ) ; } return result ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op . getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ;


<s> weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : weight = CW_Register ;


<s> break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : weight = CW_Register ; break ; }


<s> node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ;


<s> if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return true ; if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ) return true ; return false ;


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > ( Imm ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const {


<s> uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , T , T , T , T ) ;


<s> uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : report_fatal_error ( <STR_LIT> + Twine ( VT . getEVTString ( ) ) ) ; case <STR_LIT> : { uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; }


<s> uint64_t dbits = DoubleToBits ( FP -> getValueAPF ( ) . convertToDouble ( ) ) ; SDValue T = DAG . getConstant ( dbits , <STR_LIT> ) ; SDValue Tvec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tvec ) ) ;


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; const TargetMachine & TM = DAG . getTarget ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) {

return DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ;


<s> static SDValue LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { EVT OpVT = Op . getValueType ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; EVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || OpVT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getFPTOSINT ( Op0VT , OpVT ) : RTLIB :: getFPTOUINT ( Op0VT , OpVT ) ;

assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } else { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; }


<s> static SDValue LowerI8Math ( SDValue Op , SelectionDAG & DAG , unsigned Opc , const TargetLowering & TLI ) { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT ShiftVT = TLI . getShiftAmountTy ( N0 . getValueType ( ) ) ; assert ( Op . getValueType ( ) == <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> :


<s> int64_t Offset = <NUM_LIT> ; if ( IdxOp . getOpcode ( ) != <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( IdxOp ) ; assert ( CN != <NUM_LIT> && <STR_LIT> ) ; Offset = ( CN -> getSExtValue ( ) ) * eltVT . getSizeInBits ( ) / <NUM_LIT> ; } EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( Offset , PtrVT ) ) ; EVT maskVT = EVT :: getVectorVT ( * ( DAG . getContext ( ) ) , VT . getVectorElementType ( ) , <NUM_LIT> / VT . getVectorElementType ( ) . getSizeInBits ( ) ) ;

SDValue ShufMask = DAG . getNode ( <STR_LIT> , dl , maskVT , Pointer ) ;


<s> if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || Op0VT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getSINTTOFP ( Op0VT , OpVT ) : RTLIB :: getUINTTOFP ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; }


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; const TargetMachine & TM = DAG . getTarget ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ;

SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ;


<s> SDValue rotate ; if ( ( alignment % <NUM_LIT> ) == <NUM_LIT> ) { ConstantSDNode * CN ; if ( basePtr . getOpcode ( ) == <STR_LIT> && ( CN = dyn_cast < ConstantSDNode > ( basePtr . getOperand ( <NUM_LIT> ) ) ) != <NUM_LIT> ) { int64_t offset = CN -> getSExtValue ( ) ; int64_t rotamt = int64_t ( ( offset & <NUM_LIT> ) - pso ) ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getConstant ( rotamt , <STR_LIT> ) ; basePtr = basePtr . getOperand ( <NUM_LIT> ) ; if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else if ( ( basePtr . getOpcode ( ) == <STR_LIT> ) || ( basePtr . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { int64_t rotamt = - pso ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getConstant ( rotamt , <STR_LIT> ) ; } else { int64_t rotamt = - pso ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( rotamt , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ;


<s> default : { errs ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << Opc << <STR_LIT> ; errs ( ) << <STR_LIT> ; Op . getNode ( ) -> dump ( ) ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerLOAD ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT == <STR_LIT> ) return LowerI8Math ( Op , DAG , Opc , * this ) ; break ; } case <STR_LIT> :


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> static SDValue LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Op0 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 . getNode ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ConstVecValues ; EVT VT ; size_t n_copies ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; }

SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ;


<s> SmallVector < SDValue , <NUM_LIT> > ConstVecValues ; EVT VT ; size_t n_copies ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ; for ( size_t j = <NUM_LIT> ; j < n_copies ; ++ j ) ConstVecValues . push_back ( CValue ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , & ConstVecValues [ <NUM_LIT> ] , ConstVecValues . size ( ) ) ; } else { switch ( Op0 . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> APInt ccResultAllOnes = APInt :: getAllOnesValue ( ccResultVT . getSizeInBits ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhs , DAG . getConstantFP ( <NUM_LIT> , lhsVT ) , <STR_LIT> ) , DAG . getConstant ( ccResultAllOnes , ccResultVT ) ) ; } else if ( CC -> get ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhsHi32abs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) , DAG . getSetCC ( dl , ccResultVT , lhsLo32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ) ; } SDValue i64rhs = DAG . getNode ( <STR_LIT> , dl , IntVT , rhs ) ; SDValue rhsHi32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , IntVT , i64rhs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; SDValue signMag2TC = DAG . getConstant ( <NUM_LIT> , IntVT ) ; SDValue lhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , lhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue lhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64lhs ) ; SDValue lhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , lhsSelectMask , lhsSignMag2TC , i64lhs ) ; SDValue rhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , rhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue rhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64rhs ) ; SDValue rhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , rhsSelectMask , rhsSignMag2TC , i64rhs ) ; unsigned compareOp ; switch ( CC -> get ( ) ) { case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> :


<s> ( void ) OpVT ; unsigned mask1 = <NUM_LIT> ; unsigned mask2 = Op0VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned mask3 = Op0VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( mask1 , <STR_LIT> ) , DAG . getConstant ( mask1 , <STR_LIT> ) , DAG . getConstant ( mask2 , <STR_LIT> ) , DAG . getConstant ( mask3 , <STR_LIT> ) ) ; MVT mvt = Op0VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;

SDValue sraVal = DAG . getNode ( <STR_LIT> , dl , mvt , DAG . getNode ( <STR_LIT> , dl , mvt , Op0 , Op0 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> MVT simpleVT = VT . getSimpleVT ( ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT , ( <NUM_LIT> / VT . getSizeInBits ( ) ) ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; EVT Op0VT = Op0 . getValueType ( ) ; if ( Op0VT == <STR_LIT> && simpleVT == <STR_LIT> ) { unsigned maskHigh = <NUM_LIT> ; unsigned maskLow = <NUM_LIT> ; SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) ) ; SDValue truncShuffle = DAG . getNode ( <STR_LIT> , dl , VecVT , Op0 , Op0 , shufMask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , truncShuffle ) ;


<s> SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) ) ; SDValue truncShuffle = DAG . getNode ( <STR_LIT> , dl , VecVT , Op0 , Op0 , shufMask ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , truncShuffle ) ;


<s> uint32_t upper = uint32_t ( SplatVal >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( SplatVal ) ; if ( upper == lower ) { SDValue Val = DAG . getTargetConstant ( upper , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Val , Val , Val ) ) ; } else { bool upper_special , lower_special ; upper_special = ( upper == <NUM_LIT> || upper == <NUM_LIT> || upper == <NUM_LIT> ) ; lower_special = ( lower == <NUM_LIT> || lower == <NUM_LIT> || lower == <NUM_LIT> ) ; if ( lower_special && upper_special ) { SDValue UpperVal = DAG . getConstant ( upper , <STR_LIT> ) ; SDValue LowerVal = DAG . getConstant ( lower , <STR_LIT> ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , UpperVal , LowerVal , UpperVal , LowerVal ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , BV ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ; val <<= <NUM_LIT> ; process_upper = ( upper_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; process_lower = ( lower_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; if ( process_upper || process_lower ) { if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= ( j == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } else val |= i * <NUM_LIT> + j + ( ( i & <NUM_LIT> ) * <NUM_LIT> ) ; } ShufBytes . push_back ( DAG . getConstant ( val , <STR_LIT> ) ) ;


<s> } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ; val <<= <NUM_LIT> ;

process_upper = ( upper_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> EVT maskVT ; if ( EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; maskVT = <STR_LIT> ; } else if ( EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; maskVT = <STR_LIT> ; } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; maskVT = <STR_LIT> ; } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; maskVT = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != MaxElts ; ++ i ) { if ( SVN -> getMaskElt ( i ) < <NUM_LIT> ) continue ; unsigned SrcElt = SVN -> getMaskElt ( i ) ; if ( monotonic ) { if ( SrcElt >= V2EltIdx0 ) { if ( EltsFromV2 == <NUM_LIT> && CurrElt == ( SrcElt - V2EltIdx0 ) ) V2EltOffset = ( SrcElt - V2EltIdx0 ) * ( EltVT . getSizeInBits ( ) / <NUM_LIT> ) ; else monotonic = false ; ++ EltsFromV2 ; } else if ( CurrElt != SrcElt ) { monotonic = false ; } ++ CurrElt ; } if ( rotate ) { if ( PrevElt > <NUM_LIT> && SrcElt < MaxElts ) {

if ( ( PrevElt == SrcElt - <NUM_LIT> ) || ( PrevElt == MaxElts - <NUM_LIT> && SrcElt == <NUM_LIT> ) ) {


<s> if ( VT == <STR_LIT> ) retval = <NUM_LIT> ; if ( VT == <STR_LIT> ) retval = <NUM_LIT> ;


<s> int retval = <NUM_LIT> ; if ( VT == <STR_LIT> ) retval = <NUM_LIT> ; if ( VT == <STR_LIT> ) retval = <NUM_LIT> ; if ( VT == <STR_LIT> ) retval = <NUM_LIT> ;


<s> errs ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << Opc << <STR_LIT> ; errs ( ) << <STR_LIT> ; N -> dump ( ) ;


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) { VT = <STR_LIT> ; } return VT . getSizeInBits ( ) ; }


<s> Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( TLI . getLibcallName ( LC ) , TLI . getPointerTy ( ) ) ; const Type * RetTy = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getTypeForMVT ( ) ; std :: pair < SDValue , SDValue > CallInfo = TLI . LowerCallTo ( InChain , RetTy , isSigned , ! isSigned , false , false , CallingConv :: C , false , Callee , Args , DAG , Op . getDebugLoc ( ) ) ;


<s> Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( TLI . getLibcallName ( LC ) , TLI . getPointerTy ( ) ) ; const Type * RetTy = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getTypeForMVT ( ) ; std :: pair < SDValue , SDValue > CallInfo = TLI . LowerCallTo ( InChain , RetTy , isSigned , ! isSigned , false , false , CallingConv :: C , false , Callee , Args , DAG , Op . getDebugLoc ( ) ) ; return CallInfo . first ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'b' : case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; break ;


<s> case 'b' : case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ;


<s> return ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ? VT : <STR_LIT> ) ;


<s> MVT <ISA_LIT>TargetLowering :: getSetCCResultType ( MVT VT ) const {

return ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ? VT : <STR_LIT> ) ;


<s> node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ;


<s> if ( node_names . empty ( ) ) { node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ;


<s> if ( valtype_map [ i ] . valtype == VT ) { retval = valtype_map + i ; break ; } } if ( retval == <NUM_LIT> ) { cerr << <STR_LIT> << VT . getMVTString ( ) << <STR_LIT> ; abort ( ) ; }


<s> if ( ( ValueType == <STR_LIT> && ( ( unsigned ) Value & <NUM_LIT> ) == ( unsigned ) Value ) || ( ValueType == <STR_LIT> && ( Value & <NUM_LIT> ) == Value ) ) return DAG . getTargetConstant ( Value >> <NUM_LIT> , ValueType ) ; }


<s> if ( ValueType == <STR_LIT> ) { uint64_t UValue = CN -> getZExtValue ( ) ; uint32_t upper = uint32_t ( UValue >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( UValue ) ; if ( upper != lower ) return SDValue ( ) ;


<s> SDValue <STR_LIT> ( SDNode * N , SelectionDAG & DAG , MVT ValueType ) { if ( ConstantSDNode * CN = getVecImm ( N ) ) { int64_t Value = CN -> getSExtValue ( ) ; if ( ValueType == <STR_LIT> ) {

uint64_t UValue = CN -> getZExtValue ( ) ;


<s> uint64_t UValue = CN -> getZExtValue ( ) ; uint32_t upper = uint32_t ( UValue >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( UValue ) ; if ( upper != lower ) return SDValue ( ) ; Value = Value >> <NUM_LIT> ; }

if ( Value >= - ( <NUM_LIT> << <NUM_LIT> ) && Value <= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) {


<s> SDValue <STR_LIT> ( SDNode * N , SelectionDAG & DAG , MVT ValueType ) { if ( ConstantSDNode * CN = getVecImm ( N ) ) { int Value = ( int ) CN -> getZExtValue ( ) ; if ( ValueType == <STR_LIT> && Value <= <NUM_LIT> && ( ( short ) Value >> <NUM_LIT> ) == ( ( short ) Value & <NUM_LIT> ) ) return DAG . getTargetConstant ( Value & <NUM_LIT> , ValueType ) ; else if ( ValueType == <STR_LIT> && ( Value & <NUM_LIT> ) == Value ) return DAG . getTargetConstant ( Value , ValueType ) ; }


<s> uint32_t upper = uint32_t ( UValue >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( UValue ) ; if ( upper != lower ) return SDValue ( ) ; Value = Value >> <NUM_LIT> ; } if ( Value <= <NUM_LIT> ) return DAG . getTargetConstant ( Value , ValueType ) ; } return SDValue ( ) ;


<s> SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; break ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; break ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , T , T , T , T ) ; } case <STR_LIT> : {


<s> assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned minSplatBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) && minSplatBits <= SplatBitSize ) { uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; SDValue tc = DAG . getTargetConstant ( SplatBits & <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > tcVec ; tcVec . assign ( <NUM_LIT> , tc ) ;

return DAG . getNode ( Op . getNode ( ) -> getOpcode ( ) , dl , VT , Arg , DAG . getNode ( <STR_LIT> , dl , VT , & tcVec [ <NUM_LIT> ] , tcVec . size ( ) ) ) ;


<s> SDValue ConstVec ; SDValue Arg ; MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; ConstVec = Op . getOperand ( <NUM_LIT> ) ; Arg = Op . getOperand ( <NUM_LIT> ) ; if ( ConstVec . getNode ( ) -> getOpcode ( ) != <STR_LIT> ) { if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstVec = ConstVec . getOperand ( <NUM_LIT> ) ; } else { ConstVec = Op . getOperand ( <NUM_LIT> ) ; Arg = Op . getOperand ( <NUM_LIT> ) ; if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstVec = ConstVec . getOperand ( <NUM_LIT> ) ; } } } if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { BuildVectorSDNode * BCN = dyn_cast < BuildVectorSDNode > ( ConstVec . getNode ( ) ) ; assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned minSplatBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) && minSplatBits <= SplatBitSize ) { uint64_t SplatBits = APSplatBits . getZExtValue ( ) ;

SDValue tc = DAG . getTargetConstant ( SplatBits & <NUM_LIT> , <STR_LIT> ) ;


<s> static SDValue LowerConstantFP ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT == <STR_LIT> ) { ConstantFPSDNode * FP = cast < ConstantFPSDNode > ( Op . getNode ( ) ) ; assert ( ( FP != <NUM_LIT> ) && <STR_LIT> ) ; uint64_t dbits = DoubleToBits ( FP -> getValueAPF ( ) . convertToDouble ( ) ) ; SDValue T = DAG . getConstant ( dbits , <STR_LIT> ) ; SDValue Tvec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tvec ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } }


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; }


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned CNTB_reg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned SUM1_reg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue N = Op . getOperand ( <NUM_LIT> ) ; SDValue Elt0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Mask0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Shift1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Shift2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Promote = DAG . getNode ( <STR_LIT> , dl , vecVT , N , N ) ; SDValue CNTB = DAG . getNode ( <STR_LIT> , dl , vecVT , Promote ) ; SDValue CNTB_result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CNTB , Elt0 ) ; SDValue CNTB_rescopy = DAG . getCopyToReg ( CNTB_result , dl , CNTB_reg , CNTB_result ) ; SDValue Comp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getCopyFromReg ( CNTB_rescopy , dl , CNTB_reg , <STR_LIT> ) , Shift1 ) ; SDValue Sum1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Comp1 , DAG . getCopyFromReg ( CNTB_rescopy , dl , CNTB_reg , <STR_LIT> ) ) ; SDValue Sum1_rescopy = DAG . getCopyToReg ( CNTB_result , dl , SUM1_reg , Sum1 ) ; SDValue Comp2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getCopyFromReg ( Sum1_rescopy , dl , SUM1_reg , <STR_LIT> ) , Shift2 ) ;

SDValue Sum2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Comp2 , DAG . getCopyFromReg ( Sum1_rescopy , dl , SUM1_reg , <STR_LIT> ) ) ;


<s> case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Root , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Root , FIN , NULL , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } ArgValues . push_back ( ArgVal ) ; Root = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { VarArgsFrameIndex = MFI -> CreateFixedObject ( StackSlotSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; SDValue ArgVal = DAG . getRegister ( ArgRegs [ ArgRegIdx ] , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Root , dl , ArgVal , FIN , NULL , <NUM_LIT> ) ; Root = Store . getOperand ( <NUM_LIT> ) ; MemOps . push_back ( Store ) ; ArgOffset += StackSlotSize ; } if ( ! MemOps . empty ( ) ) Root = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; } ArgValues . push_back ( Root ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getNode ( ) -> getVTList ( ) , & ArgValues [ <NUM_LIT> ] , ArgValues . size ( ) ) ;


<s> RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getFPTOSINT ( Op0VT , OpVT ) : RTLIB :: getFPTOUINT ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; }


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , PtrVT , GSDN -> getOffset ( ) ) ; const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) {


<s> case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; MVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; MVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = <STR_LIT> ; if ( N1 . getValueType ( ) . bitsGT ( ShiftVT ) ) N1Opc = <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; MVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = <STR_LIT> ; if ( N1VT . bitsGT ( ShiftVT ) ) N1Opc = <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ;


<s> SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( CN -> getSExtValue ( ) , PtrVT ) ) ; SDValue ShufMask = DAG . getNode ( <STR_LIT> , dl , VT , Pointer ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , ValOp ) , VecOp , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShufMask ) ) ; return result ;


<s> MVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || Op0VT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getSINTTOFP ( Op0VT , OpVT ) : RTLIB :: getUINTTOFP ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; }


<s> MVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; const TargetMachine & TM = DAG . getTarget ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; }


<s> if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ;


<s> int64_t rotamt = - vtm -> prefslot_byte ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( rotamt , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( - vtm -> prefslot_byte , PtrVT ) ) ; } result = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , <NUM_LIT> ) ; the_chain = result . getValue ( <NUM_LIT> ) ; result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , result . getValue ( <NUM_LIT> ) , rotate ) ; MVT vecVT = <STR_LIT> ( InVT , ( <NUM_LIT> / InVT . getSizeInBits ( ) ) ) ; result = DAG . getNode ( <STR_LIT> , dl , InVT , DAG . getNode ( <STR_LIT> , dl , vecVT , result ) ) ; if ( ExtType == <STR_LIT> ) { result = DAG . getNode ( <STR_LIT> , dl , OutVT , result ) ; } else if ( ExtType == <STR_LIT> ) { result = DAG . getNode ( <STR_LIT> , dl , OutVT , result ) ; } else if ( ExtType == <STR_LIT> ) { unsigned NewOpc = <STR_LIT> ; if ( OutVT . isFloatingPoint ( ) ) NewOpc = <STR_LIT> ; result = DAG . getNode ( NewOpc , dl , OutVT , result ) ; } SDVTList retvts = DAG . getVTList ( OutVT , <STR_LIT> ) ; SDValue retops [ <NUM_LIT> ] = {


<s> cerr << <STR_LIT> ; Op . getNode ( ) -> dump ( ) ; abort ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerLOAD ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG , VarArgsFrameIndex ) ; case <STR_LIT> : return LowerCALL ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerRET ( Op , DAG , getTargetMachine ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT == <STR_LIT> ) return LowerI8Math ( Op , DAG , Opc , * this ) ; break ; } case <STR_LIT> :


<s> } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Op . getOperand ( i * <NUM_LIT> + <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ; for ( size_t j = <NUM_LIT> ; j < n_copies ; ++ j ) ConstVecValues . push_back ( CValue ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , & ConstVecValues [ <NUM_LIT> ] , ConstVecValues . size ( ) ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ; for ( size_t j = <NUM_LIT> ; j < n_copies ; ++ j ) ConstVecValues . push_back ( CValue ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , & ConstVecValues [ <NUM_LIT> ] , ConstVecValues . size ( ) ) ; } else { switch ( Op0 . getValueType ( ) . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op0 , Op0 ) ; } } return SDValue ( ) ;


<s> MVT VT = Op . getValueType ( ) ; SDValue lhs = Op . getOperand ( <NUM_LIT> ) ; SDValue rhs = Op . getOperand ( <NUM_LIT> ) ; SDValue trueval = Op . getOperand ( <NUM_LIT> ) ;

SDValue falseval = Op . getOperand ( <NUM_LIT> ) ;


<s> APInt ccResultAllOnes = APInt :: getAllOnesValue ( ccResultVT . getSizeInBits ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhs , DAG . getConstantFP ( <NUM_LIT> , lhsVT ) , <STR_LIT> ) , DAG . getConstant ( ccResultAllOnes , ccResultVT ) ) ; } else if ( CC -> get ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhsHi32abs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) , DAG . getSetCC ( dl , ccResultVT , lhsLo32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ) ; } SDValue i64rhs = DAG . getNode ( <STR_LIT> , dl , IntVT , rhs ) ; SDValue rhsHi32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , IntVT , i64rhs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; SDValue signMag2TC = DAG . getConstant ( <NUM_LIT> , IntVT ) ; SDValue lhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , lhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue lhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64lhs ) ; SDValue lhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , lhsSelectMask , lhsSignMag2TC , i64lhs ) ; SDValue rhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , rhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue rhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64rhs ) ; SDValue rhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , rhsSelectMask , rhsSignMag2TC , i64rhs ) ; unsigned compareOp ; switch ( CC -> get ( ) ) { case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> :


<s> static SDValue LowerTRUNCATE ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getValueType ( ) ; <STR_LIT> simpleVT = VT . getSimpleVT ( ) ; MVT VecVT = <STR_LIT> ( VT , ( <NUM_LIT> / VT . getSizeInBits ( ) ) ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = Op0 . getValueType ( ) ; if ( Op0VT . getSimpleVT ( ) == <STR_LIT> && simpleVT == <STR_LIT> ) {


<s> MVT Op0VT = Op0 . getValueType ( ) ; if ( Op0VT . getSimpleVT ( ) == <STR_LIT> && simpleVT == <STR_LIT> ) { unsigned maskHigh = <NUM_LIT> ; unsigned maskLow = <NUM_LIT> ;

SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) ) ;


<s> if ( upper == lower ) { SDValue Val = DAG . getTargetConstant ( upper , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Val , Val , Val ) ) ; } else { bool upper_special , lower_special ; upper_special = ( upper == <NUM_LIT> || upper == <NUM_LIT> || upper == <NUM_LIT> ) ; lower_special = ( lower == <NUM_LIT> || lower == <NUM_LIT> || lower == <NUM_LIT> ) ; if ( lower_special && upper_special ) { SDValue SplatValCN = DAG . getConstant ( SplatVal , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatValCN , SplatValCN ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ;


<s> SDValue SplatValCN = DAG . getConstant ( SplatVal , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatValCN , SplatValCN ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ; val <<= <NUM_LIT> ; process_upper = ( upper_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; process_lower = ( lower_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; if ( process_upper || process_lower ) { if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= ( j == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } else val |= i * <NUM_LIT> + j + ( ( i & <NUM_LIT> ) * <NUM_LIT> ) ; } ShufBytes . push_back ( DAG . getConstant ( val , <STR_LIT> ) ) ;


<s> unsigned V0Elt = <NUM_LIT> ; bool monotonic = true ; bool rotate = true ; if ( EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; } else if ( EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; } else assert ( <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != PermMask . getNumOperands ( ) ; ++ i ) { if ( PermMask . getOperand ( i ) . getOpcode ( ) != <STR_LIT> ) { unsigned SrcElt = cast < ConstantSDNode > ( PermMask . getOperand ( i ) ) -> getZExtValue ( ) ; if ( monotonic ) { if ( SrcElt >= V2EltIdx0 ) { if ( <NUM_LIT> >= ( ++ EltsFromV2 ) ) { V2Elt = ( V2EltIdx0 - SrcElt ) << <NUM_LIT> ; } } else if ( CurrElt != SrcElt ) { monotonic = false ; } ++ CurrElt ; } if ( rotate ) { if ( PrevElt > <NUM_LIT> && SrcElt < MaxElts ) { if ( ( PrevElt == SrcElt - <NUM_LIT> ) || ( PrevElt == MaxElts - <NUM_LIT> && SrcElt == <NUM_LIT> ) ) { PrevElt = SrcElt ;


<s> unsigned Opc = ( unsigned ) N -> getOpcode ( ) ; MVT OpVT = N -> getValueType ( <NUM_LIT> ) ; switch ( Opc ) { default : { cerr << <STR_LIT> ; cerr << <STR_LIT> << Opc << <STR_LIT> ; cerr << <STR_LIT> ;


<s> Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( TLI . getLibcallName ( LC ) , TLI . getPointerTy ( ) ) ; Type * RetTy = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) ;

TargetLowering :: CallLoweringInfo CLI ( InChain , RetTy , isSigned , ! isSigned , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( LC ) , false , false , true , Callee , Args , DAG , Op . getDebugLoc ( ) ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressImmediate ( GlobalValue * GV ) const { return false ;


<s> prefslot_begin = <NUM_LIT> ; prefslot_end = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { prefslot_begin = <NUM_LIT> ; prefslot_end = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { prefslot_begin = <NUM_LIT> ; prefslot_end = <NUM_LIT> ; break ; } } assert ( prefslot_begin != - <NUM_LIT> && prefslot_end != - <NUM_LIT> && <STR_LIT> ) ; unsigned int ShufBytes [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned int mask_val ; if ( i <= prefslot_end ) { mask_val = ( ( i < prefslot_begin ) ? <NUM_LIT> : elt_byte + ( i - prefslot_begin ) ) ; ShufBytes [ i ] = mask_val ; } else ShufBytes [ i ] = ShufBytes [ i % ( prefslot_end + <NUM_LIT> ) ] ; } SDValue ShufMask [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < sizeof ( ShufMask ) / sizeof ( ShufMask [ <NUM_LIT> ] ) ; ++ i ) { unsigned bidx = i * <NUM_LIT> ; unsigned int bits = ( ( ShufBytes [ bidx ] << <NUM_LIT> ) | ( ShufBytes [ bidx + <NUM_LIT> ] << <NUM_LIT> ) | ( ShufBytes [ bidx + <NUM_LIT> ] << <NUM_LIT> ) | ShufBytes [ bidx + <NUM_LIT> ] ) ; ShufMask [ i ] = DAG . getConstant ( bits , <STR_LIT> ) ; } SDValue ShufMaskVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ShufMask [ <NUM_LIT> ] , sizeof ( ShufMask ) / sizeof ( ShufMask [ <NUM_LIT> ] ) ) ; retval = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , N . getValueType ( ) , N , N , ShufMaskVec ) ) ; } else { EVT VecVT = N . getValueType ( ) ; if ( ! VecVT . isSimple ( ) || ! VecVT . isVector ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } if ( Elt . getValueType ( ) != <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ;

APInt scaleFactor = APInt ( <NUM_LIT> , uint64_t ( <NUM_LIT> / N . getValueType ( ) . getVectorNumElements ( ) ) , false ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned ArgOffset = <ISA_LIT>FrameLowering :: minStackSize ( ) ; unsigned ArgRegIdx = <NUM_LIT> ; unsigned StackSlotSize = <ISA_LIT>FrameLowering :: stackSlotSize ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CCC_<ISA_LIT> ) ; for ( unsigned ArgNo = <NUM_LIT> , e = Ins . size ( ) ; ArgNo != e ; ++ ArgNo ) { EVT ObjectVT = Ins [ ArgNo ] . VT ; unsigned ObjSize = ObjectVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ArgVal ; CCValAssign & VA = ArgLocs [ ArgNo ] ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * ArgRegClass ; switch ( ObjectVT . getSimpleVT ( ) . SimpleTy ) { default : report_fatal_error ( <STR_LIT> + Twine ( ObjectVT . getEVTString ( ) ) ) ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ;


<s> static SDValue LowerBUILD_VECTOR ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; BuildVectorSDNode * BCN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; unsigned minSplatBits = EltVT . getSizeInBits ( ) ; if ( minSplatBits < <NUM_LIT> ) minSplatBits = <NUM_LIT> ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) || minSplatBits < SplatBitSize ) return SDValue ( ) ; uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : report_fatal_error ( <STR_LIT> + Twine ( VT . getEVTString ( ) ) ) ; case <STR_LIT> : { uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; break ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; break ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumArgRegs = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( StackSlotSize , ArgOffset , true ) ) ;

SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;


<s> const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } else {


<s> SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = <STR_LIT> ; if ( N1 . getValueType ( ) . bitsGT ( ShiftVT ) ) N1Opc = <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; }