<s> case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = <STR_LIT> ; if ( N1 . getValueType ( ) . bitsGT ( ShiftVT ) ) N1Opc = <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = <STR_LIT> ; if ( N1VT . bitsGT ( ShiftVT ) ) N1Opc = <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ;


<s> lower_special = ( lower == <NUM_LIT> || lower == <NUM_LIT> || lower == <NUM_LIT> ) ; if ( lower_special && upper_special ) { SDValue SplatValCN = DAG . getConstant ( SplatVal , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatValCN , SplatValCN ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) {


<s> if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ; val <<= <NUM_LIT> ; process_upper = ( upper_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; process_lower = ( lower_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; if ( process_upper || process_lower ) { if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= ( j == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } else val |= i * <NUM_LIT> + j + ( ( i & <NUM_LIT> ) * <NUM_LIT> ) ; } ShufBytes . push_back ( DAG . getConstant ( val , <STR_LIT> ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , OpVT , HI32 , LO32 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ShufBytes [ <NUM_LIT> ] , ShufBytes . size ( ) ) ) ;


<s> Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( TLI . getLibcallName ( LC ) , TLI . getPointerTy ( ) ) ;

Type * RetTy = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ArgRegIdx != NumArgRegs ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; ArgOffset += StackSlotSize ; } break ; } } unsigned NumStackBytes = ArgOffset - <ISA_LIT>FrameLowering :: minStackSize ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumStackBytes , true ) ) ; if ( ! MemOpChains . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned CallOpc = <STR_LIT> ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , CalleeVT ) ; if ( ! ST -> usingLargeMem ( ) ) { if ( GV -> isDeclaration ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue ExtSym = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) ) ; if ( ! ST -> usingLargeMem ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , ExtSym , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , ExtSym , Zero ) ; } } else if ( SDNode * Dest = isLSAAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: computeMaskedBitsForTargetNode ( const SDValue Op , const APInt & Mask , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { const uint64_t uint64_sizebits = sizeof ( uint64_t ) * CHAR_BIT ; switch ( Op . getOpcode ( ) ) { default : break ; case CALL : case SHUFB : case SHUFFLE_MASK : case CNTB : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> EVT VT = Op . getValueType ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) { VT = <STR_LIT> ; }


<s> TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op . getOperand ( i ) . getValueType ( ) ; const Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ;


<s> TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op . getOperand ( i ) . getValueType ( ) ; const Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ;


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * ) const { return <NUM_LIT> ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'b' : case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; break ; case 'v' :


<s> <STR_LIT> <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const {

return ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ? VT . getSimpleVT ( ) . SimpleTy :


<s> node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; } std :: map < unsigned , const char * > :: iterator i = node_names . find ( Opcode ) ;

return ( ( i != node_names . end ( ) ) ? i -> second : <NUM_LIT> ) ;


<s> break ; } } if ( retval == <NUM_LIT> ) { report_fatal_error ( <STR_LIT> + Twine ( VT . getEVTString ( ) ) ) ; }


<s> for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ;

if ( OpVal . getNode ( ) == <NUM_LIT> ) OpVal = N -> getOperand ( i ) ;


<s> else if ( OpVal != N -> getOperand ( i ) ) return <NUM_LIT> ; } if ( OpVal . getNode ( ) != <NUM_LIT> ) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) {


<s> if ( ConstantSDNode * CN = getVecImm ( N ) ) { uint64_t Value = CN -> getZExtValue ( ) ; if ( ( ValueType == <STR_LIT> && ( ( unsigned ) Value & <NUM_LIT> ) == ( unsigned ) Value ) || ( ValueType == <STR_LIT> && ( Value & <NUM_LIT> ) == Value ) ) return DAG . getTargetConstant ( Value >> <NUM_LIT> , ValueType ) ; }


<s> return DAG . getTargetConstant ( ( unsigned ) CN -> getZExtValue ( ) , <STR_LIT> ) ;


<s> uint32_t upper = uint32_t ( UValue >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( UValue ) ; if ( upper != lower ) return SDValue ( ) ; Value = Value >> <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( Value ) ) return DAG . getTargetConstant ( Value , ValueType ) ; } return SDValue ( ) ;


<s> int64_t Value = CN -> getSExtValue ( ) ; if ( ValueType == <STR_LIT> ) { uint64_t UValue = CN -> getZExtValue ( ) ; uint32_t upper = uint32_t ( UValue >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( UValue ) ; if ( upper != lower ) return SDValue ( ) ; Value = Value >> <NUM_LIT> ; }

if ( Value >= - ( <NUM_LIT> << <NUM_LIT> ) && Value <= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) {


<s> uint64_t UValue = CN -> getZExtValue ( ) ; uint32_t upper = uint32_t ( UValue >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( UValue ) ; if ( upper != lower ) return SDValue ( ) ; Value = Value >> <NUM_LIT> ; }

if ( Value <= <NUM_LIT> ) return DAG . getTargetConstant ( Value , ValueType ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressImmediate ( llvm :: GlobalValue * GV ) const {


<s> if ( ( Addr & <NUM_LIT> ) != <NUM_LIT> || ( Addr << <NUM_LIT> >> <NUM_LIT> ) != Addr ) return <NUM_LIT> ;

return DAG . getConstant ( ( int ) C -> getZExtValue ( ) >> <NUM_LIT> , <STR_LIT> ) . getNode ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ;


<s> TargetLowering :: LowerAsmOperandForConstraint ( Op , ConstraintLetter , hasMemory , Ops , DAG ) ;


<s> uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; break ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; break ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , T , T , T , T ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , T , T ) ; } case <STR_LIT> : { return <STR_LIT> ( VT , DAG , SplatBits , dl ) ; } } return SDValue ( ) ;


<s> assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned minSplatBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) && minSplatBits <= SplatBitSize ) { uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; SDValue tc = DAG . getTargetConstant ( SplatBits & <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > tcVec ; tcVec . assign ( <NUM_LIT> , tc ) ;

return DAG . getNode ( Op . getNode ( ) -> getOpcode ( ) , dl , VT , Arg , DAG . getNode ( <STR_LIT> , dl , VT , & tcVec [ <NUM_LIT> ] , tcVec . size ( ) ) ) ;


<s> } } if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { BuildVectorSDNode * BCN = dyn_cast < BuildVectorSDNode > ( ConstVec . getNode ( ) ) ; assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned minSplatBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) && minSplatBits <= SplatBitSize ) { uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; SDValue tc = DAG . getTargetConstant ( SplatBits & <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > tcVec ; tcVec . assign ( <NUM_LIT> , tc ) ;


<s> ConstantFPSDNode * FP = cast < ConstantFPSDNode > ( Op . getNode ( ) ) ; assert ( ( FP != <NUM_LIT> ) && <STR_LIT> ) ; uint64_t dbits = DoubleToBits ( FP -> getValueAPF ( ) . convertToDouble ( ) ) ; SDValue T = DAG . getConstant ( dbits , <STR_LIT> ) ; SDValue Tvec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tvec ) ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT == <STR_LIT> ) { ConstantFPSDNode * FP = cast < ConstantFPSDNode > ( Op . getNode ( ) ) ; assert ( ( FP != <NUM_LIT> ) && <STR_LIT> ) ; uint64_t dbits = DoubleToBits ( FP -> getValueAPF ( ) . convertToDouble ( ) ) ; SDValue T = DAG . getConstant ( dbits , <STR_LIT> ) ; SDValue Tvec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ;


<s> return :: LowerConstantPool ( Op , DAG , TM . getSubtargetImpl ( ) ) ;


<s> unsigned SUM1_reg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue N = Op . getOperand ( <NUM_LIT> ) ; SDValue Elt0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Mask0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Shift1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Shift2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Promote = DAG . getNode ( <STR_LIT> , dl , vecVT , N , N ) ; SDValue CNTB = DAG . getNode ( <STR_LIT> , dl , vecVT , Promote ) ; SDValue CNTB_result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CNTB , Elt0 ) ; SDValue CNTB_rescopy = DAG . getCopyToReg ( CNTB_result , dl , CNTB_reg , CNTB_result ) ; SDValue Comp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getCopyFromReg ( CNTB_rescopy , dl , CNTB_reg , <STR_LIT> ) , Shift1 ) ; SDValue Sum1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Comp1 , DAG . getCopyFromReg ( CNTB_rescopy , dl , CNTB_reg , <STR_LIT> ) ) ; SDValue Sum1_rescopy = DAG . getCopyToReg ( CNTB_result , dl , SUM1_reg , Sum1 ) ; SDValue Comp2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getCopyFromReg ( Sum1_rescopy , dl , SUM1_reg , <STR_LIT> ) , Shift2 ) ; SDValue Sum2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Comp2 , DAG . getCopyFromReg ( Sum1_rescopy , dl , SUM1_reg , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sum2 , Mask0 ) ; }


<s> unsigned SUM1_reg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue N = Op . getOperand ( <NUM_LIT> ) ; SDValue Elt0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Mask0 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Shift1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Shift2 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Promote = DAG . getNode ( <STR_LIT> , dl , vecVT , N , N ) ; SDValue CNTB = DAG . getNode ( <STR_LIT> , dl , vecVT , Promote ) ; SDValue CNTB_result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CNTB , Elt0 ) ; SDValue CNTB_rescopy = DAG . getCopyToReg ( CNTB_result , dl , CNTB_reg , CNTB_result ) ; SDValue Comp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getCopyFromReg ( CNTB_rescopy , dl , CNTB_reg , <STR_LIT> ) , Shift1 ) ; SDValue Sum1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Comp1 , DAG . getCopyFromReg ( CNTB_rescopy , dl , CNTB_reg , <STR_LIT> ) ) ; SDValue Sum1_rescopy = DAG . getCopyToReg ( CNTB_result , dl , SUM1_reg , Sum1 ) ; SDValue Comp2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getCopyFromReg ( Sum1_rescopy , dl , SUM1_reg , <STR_LIT> ) , Shift2 ) ; SDValue Sum2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Comp2 , DAG . getCopyFromReg ( Sum1_rescopy , dl , SUM1_reg , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sum2 , Mask0 ) ; } case <STR_LIT> : break ; }


<s> report_fatal_error ( <STR_LIT> + Twine ( ObjectVT . getEVTString ( ) ) ) ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ;

for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { VarArgsFrameIndex = MFI -> CreateFixedObject ( StackSlotSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; unsigned VReg = MF . addLiveIn ( ArgRegs [ ArgRegIdx ] , & <STR_LIT> ) ; SDValue ArgVal = DAG . getRegister ( VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Store . getOperand ( <NUM_LIT> ) ; MemOps . push_back ( Store ) ; ArgOffset += StackSlotSize ; }

if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ;


<s> EVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || OpVT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getFPTOSINT ( Op0VT , OpVT ) : RTLIB :: getFPTOUINT ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; } return Op ;


<s> GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GSDN -> getGlobal ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , PtrVT , GSDN -> getOffset ( ) ) ; const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } else { report_fatal_error ( <STR_LIT> <STR_LIT> ) ;


<s> case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> :


<s> EVT VT = Op . getValueType ( ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( IdxOp ) ; assert ( CN != <NUM_LIT> && <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( CN -> getSExtValue ( ) , PtrVT ) ) ; SDValue ShufMask = DAG . getNode ( <STR_LIT> , dl , VT , Pointer ) ;

SDValue result = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , ValOp ) , VecOp , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShufMask ) ) ;


<s> static SDValue LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) { SDValue VecOp = Op . getOperand ( <NUM_LIT> ) ; SDValue ValOp = Op . getOperand ( <NUM_LIT> ) ; SDValue IdxOp = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( IdxOp ) ; assert ( CN != <NUM_LIT> && <STR_LIT> ) ;

EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; EVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || Op0VT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getSINTTOFP ( Op0VT , OpVT ) : RTLIB :: getUINTTOFP ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; } return Op ;


<s> EVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || Op0VT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getSINTTOFP ( Op0VT , OpVT ) : RTLIB :: getUINTTOFP ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; }


<s> case <STR_LIT> : { SDValue result ; SDValue basePtr = LN -> getBasePtr ( ) ; SDValue rotate ; if ( alignment == <NUM_LIT> ) { ConstantSDNode * CN ; if ( basePtr . getOpcode ( ) == <STR_LIT> && ( CN = dyn_cast < ConstantSDNode > ( basePtr . getOperand ( <NUM_LIT> ) ) ) != <NUM_LIT> ) { int64_t offset = CN -> getSExtValue ( ) ; int64_t rotamt = int64_t ( ( offset & <NUM_LIT> ) - vtm -> prefslot_byte ) ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getConstant ( rotamt , <STR_LIT> ) ; basePtr = basePtr . getOperand ( <NUM_LIT> ) ; if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else if ( ( basePtr . getOpcode ( ) == <STR_LIT> ) || ( basePtr . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { int64_t rotamt = - vtm -> prefslot_byte ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getConstant ( rotamt , <STR_LIT> ) ; } else { int64_t rotamt = - vtm -> prefslot_byte ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( rotamt , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( - vtm -> prefslot_byte , PtrVT ) ) ; }

result = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , <NUM_LIT> ) ;


<s> } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( - vtm -> prefslot_byte , PtrVT ) ) ; } result = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , <NUM_LIT> ) ; the_chain = result . getValue ( <NUM_LIT> ) ; result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , result . getValue ( <NUM_LIT> ) , rotate ) ; EVT vecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT , ( <NUM_LIT> / InVT . getSizeInBits ( ) ) ) ; result = DAG . getNode ( <STR_LIT> , dl , InVT , DAG . getNode ( <STR_LIT> , dl , vecVT , result ) ) ; if ( ExtType == <STR_LIT> ) { result = DAG . getNode ( <STR_LIT> , dl , OutVT , result ) ; } else if ( ExtType == <STR_LIT> ) { result = DAG . getNode ( <STR_LIT> , dl , OutVT , result ) ; } else if ( ExtType == <STR_LIT> ) { unsigned NewOpc = <STR_LIT> ; if ( OutVT . isFloatingPoint ( ) ) NewOpc = <STR_LIT> ; result = DAG . getNode ( NewOpc , dl , OutVT , result ) ; } SDVTList retvts = DAG . getVTList ( OutVT , <STR_LIT> ) ; SDValue retops [ <NUM_LIT> ] = { result , the_chain } ; result = DAG . getNode ( <STR_LIT> , dl , retvts , retops , sizeof ( retops ) / sizeof ( retops [ <NUM_LIT> ] ) ) ; return result ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { report_fatal_error ( <STR_LIT> <STR_LIT> + Twine ( ( unsigned ) LN -> getAddressingMode ( ) ) ) ; } }


<s> case <STR_LIT> : return LowerLOAD ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT == <STR_LIT> ) return LowerI8Math ( Op , DAG , Opc , * this ) ; break ; } case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , * this ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;

Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ;


<s> static SDValue LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Op0 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 . getNode ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ConstVecValues ; EVT VT ; size_t n_copies ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ; for ( size_t j = <NUM_LIT> ; j < n_copies ; ++ j ) ConstVecValues . push_back ( CValue ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , & ConstVecValues [ <NUM_LIT> ] , ConstVecValues . size ( ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > ConstVecValues ; EVT VT ; size_t n_copies ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ; for ( size_t j = <NUM_LIT> ; j < n_copies ; ++ j ) ConstVecValues . push_back ( CValue ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , & ConstVecValues [ <NUM_LIT> ] , ConstVecValues . size ( ) ) ; } else { switch ( Op0 . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static SDValue LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG , const TargetLowering & TLI ) { EVT VT = Op . getValueType ( ) ; SDValue lhs = Op . getOperand ( <NUM_LIT> ) ; SDValue rhs = Op . getOperand ( <NUM_LIT> ) ; SDValue trueval = Op . getOperand ( <NUM_LIT> ) ; SDValue falseval = Op . getOperand ( <NUM_LIT> ) ; SDValue condition = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue compare = DAG . getNode ( <STR_LIT> , dl , TLI . getSetCCResultType ( Op . getValueType ( ) ) , lhs , rhs , condition ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , falseval , trueval , compare ) ;


<s> SDValue lhsLo32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , i64lhs ) ; if ( CC -> get ( ) == <STR_LIT> ) { APInt ccResultAllOnes = APInt :: getAllOnesValue ( ccResultVT . getSizeInBits ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhs , DAG . getConstantFP ( <NUM_LIT> , lhsVT ) , <STR_LIT> ) , DAG . getConstant ( ccResultAllOnes , ccResultVT ) ) ; } else if ( CC -> get ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhsHi32abs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) , DAG . getSetCC ( dl , ccResultVT , lhsLo32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ) ; } SDValue i64rhs = DAG . getNode ( <STR_LIT> , dl , IntVT , rhs ) ; SDValue rhsHi32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , IntVT , i64rhs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; SDValue signMag2TC = DAG . getConstant ( <NUM_LIT> , IntVT ) ; SDValue lhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , lhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue lhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64lhs ) ; SDValue lhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , lhsSelectMask , lhsSignMag2TC , i64lhs ) ; SDValue rhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , rhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue rhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64rhs ) ; SDValue rhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , rhsSelectMask , rhsSignMag2TC , i64rhs ) ; unsigned compareOp ; switch ( CC -> get ( ) ) { case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> ) ; } SDValue result = DAG . getSetCC ( dl , ccResultVT , lhsSelect , rhsSelect , ( <STR_LIT> ) compareOp ) ; if ( ( CC -> get ( ) & <NUM_LIT> ) == <NUM_LIT> ) {

SDValue lhsNaN = DAG . getSetCC ( dl , ccResultVT , lhs , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ;


<s> MVT mvt = Op0VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue sraVal = DAG . getNode ( <STR_LIT> , dl , mvt , DAG . getNode ( <STR_LIT> , dl , mvt , Op0 , Op0 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue extShuffle = DAG . getNode ( <STR_LIT> , dl , mvt , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , sraVal , shufMask ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , extShuffle ) ;


<s> EVT VT = Op . getValueType ( ) ; MVT simpleVT = VT . getSimpleVT ( ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT , ( <NUM_LIT> / VT . getSizeInBits ( ) ) ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; EVT Op0VT = Op0 . getValueType ( ) ; if ( Op0VT . getSimpleVT ( ) == <STR_LIT> && simpleVT == <STR_LIT> ) { unsigned maskHigh = <NUM_LIT> ;


<s> uint32_t upper = uint32_t ( SplatVal >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( SplatVal ) ; if ( upper == lower ) { SDValue Val = DAG . getTargetConstant ( upper , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Val , Val , Val ) ) ; } else { bool upper_special , lower_special ; upper_special = ( upper == <NUM_LIT> || upper == <NUM_LIT> || upper == <NUM_LIT> ) ; lower_special = ( lower == <NUM_LIT> || lower == <NUM_LIT> || lower == <NUM_LIT> ) ; if ( lower_special && upper_special ) { SDValue SplatValCN = DAG . getConstant ( SplatVal , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatValCN , SplatValCN ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ;

for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) {


<s> } else if ( CurrElt != SrcElt ) { monotonic = false ; } ++ CurrElt ; } if ( rotate ) { if ( PrevElt > <NUM_LIT> && SrcElt < MaxElts ) { if ( ( PrevElt == SrcElt - <NUM_LIT> ) || ( PrevElt == MaxElts - <NUM_LIT> && SrcElt == <NUM_LIT> ) ) { PrevElt = SrcElt ; if ( SrcElt == <NUM_LIT> ) V0Elt = i ; } else { rotate = false ; } } else if ( PrevElt == <NUM_LIT> ) { PrevElt = SrcElt ; } else { rotate = false ; } } } if ( EltsFromV2 == <NUM_LIT> && monotonic ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue InitTempReg = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , VReg , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue ShufMaskOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getTargetConstant ( V2Elt , <STR_LIT> ) , DAG . getCopyFromReg ( InitTempReg , dl , VReg , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V2 , V1 , ShufMaskOp ) ; } else if ( rotate ) { int rotamt = ( MaxElts - V0Elt ) * EltVT . getSizeInBits ( ) / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , DAG . getConstant ( rotamt , <STR_LIT> ) ) ; } else { unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask ; for ( unsigned i = <NUM_LIT> , e = MaxElts ; i != e ; ++ i ) { unsigned SrcElt = SVN -> getMaskElt ( i ) < <NUM_LIT> ? <NUM_LIT> : SVN -> getMaskElt ( i ) ; for ( unsigned j = <NUM_LIT> ; j < BytesPerElement ; ++ j ) ResultMask . push_back ( DAG . getConstant ( SrcElt * BytesPerElement + j , <STR_LIT> ) ) ; } SDValue VPermMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ResultMask [ <NUM_LIT> ] , ResultMask . size ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 , VPermMask ) ; }


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && NodeVT == Op0VT ) { if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { errs ( ) << <STR_LIT> ; N -> dump ( & DAG ) ; errs ( ) << <STR_LIT> ; Op0 . getNode ( ) -> dump ( & DAG ) ; errs ( ) << <STR_LIT> ; } return Op0 ; } break ; } case <STR_LIT> : { if ( ! ST -> usingLargeMem ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( CN != <NUM_LIT> && CN -> getZExtValue ( ) == <NUM_LIT> ) { DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( & DAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( Op0 . getNode ( ) -> dump ( & DAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; return Op0 ; } } else if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( Op1 ) ) { if ( CN1 -> isNullValue ( ) ) { if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { errs ( ) << <STR_LIT> << <STR_LIT> << <STR_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , Op0VT , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } }


<s> default : { errs ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << Opc << <STR_LIT> ; errs ( ) << <STR_LIT> ; N -> dump ( ) ; abort ( ) ; } }


<s> Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( TLI . getLibcallName ( LC ) , TLI . getPointerTy ( ) ) ;

const Type * RetTy = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) ;


<s> SDValue ExpandLibCall ( RTLIB :: Libcall LC , SDValue Op , SelectionDAG & DAG , bool isSigned , SDValue & Hi , const <ISA_LIT>TargetLowering & TLI ) { SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op . getOperand ( i ) . getValueType ( ) ; const Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ;


<s> TargetLowering :: LowerAsmOperandForConstraint ( Op , ConstraintLetter , Ops , DAG ) ;


<s> unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) || minSplatBits < SplatBitSize ) return SDValue ( ) ; uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : report_fatal_error ( <STR_LIT> + Twine ( VT . getEVTString ( ) ) ) ; case <STR_LIT> : { uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; break ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; break ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , T , T , T , T ) ;


<s> break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumArgRegs = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( StackSlotSize , ArgOffset , true ) ) ; SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; unsigned VReg = MF . addLiveIn ( ArgRegs [ ArgRegIdx ] , & <STR_LIT> ) ; SDValue ArgVal = DAG . getRegister ( VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Store . getOperand ( <NUM_LIT> ) ; MemOps . push_back ( Store ) ; ArgOffset += StackSlotSize ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; }


<s> } EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( Offset , PtrVT ) ) ; EVT maskVT = EVT :: getVectorVT ( * ( DAG . getContext ( ) ) , VT . getVectorElementType ( ) , <NUM_LIT> / VT . getVectorElementType ( ) . getSizeInBits ( ) ) ;

SDValue ShufMask = DAG . getNode ( <STR_LIT> , dl , maskVT , Pointer ) ;


<s> } EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( Offset , PtrVT ) ) ; EVT maskVT = EVT :: getVectorVT ( * ( DAG . getContext ( ) ) , VT . getVectorElementType ( ) , <NUM_LIT> / VT . getVectorElementType ( ) . getSizeInBits ( ) ) ; SDValue ShufMask = DAG . getNode ( <STR_LIT> , dl , maskVT , Pointer ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; }

if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ;


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> EVT VT = Value . getValueType ( ) ; EVT StVT = ( ! SN -> isTruncatingStore ( ) ? VT : SN -> getMemoryVT ( ) ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned alignment = SN -> getAlignment ( ) ; switch ( SN -> getAddressingMode ( ) ) { case <STR_LIT> : { EVT vecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT , ( <NUM_LIT> / VT . getSizeInBits ( ) ) ) ; SDValue alignLoadVec ; SDValue basePtr = SN -> getBasePtr ( ) ; SDValue the_chain = SN -> getChain ( ) ; SDValue insertEltOffs ; if ( alignment == <NUM_LIT> ) { ConstantSDNode * CN ; if ( basePtr . getOpcode ( ) == <STR_LIT> && ( CN = dyn_cast < ConstantSDNode > ( basePtr . getOperand ( <NUM_LIT> ) ) ) != <NUM_LIT> ) { int64_t offset = CN -> getSExtValue ( ) ; basePtr = basePtr . getOperand ( <NUM_LIT> ) ; insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & <NUM_LIT> ) , PtrVT ) ) ; if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else { insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ;


<s> basePtr = basePtr . getOperand ( <NUM_LIT> ) ; insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & <NUM_LIT> ) , PtrVT ) ) ; if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else { insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; }

alignLoadVec = DAG . getLoad ( vecVT , dl , the_chain , basePtr , SN -> getSrcValue ( ) , SN -> getSrcValueOffset ( ) , SN -> isVolatile ( ) , SN -> isNonTemporal ( ) , <NUM_LIT> ) ;


<s> } else if ( EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; maskVT = <STR_LIT> ; } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; maskVT = <STR_LIT> ; } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; maskVT = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != MaxElts ; ++ i ) { if ( SVN -> getMaskElt ( i ) < <NUM_LIT> ) continue ; unsigned SrcElt = SVN -> getMaskElt ( i ) ; if ( monotonic ) { if ( SrcElt >= V2EltIdx0 ) { if ( EltsFromV2 == <NUM_LIT> && CurrElt == ( SrcElt - V2EltIdx0 ) ) V2EltOffset = ( SrcElt - V2EltIdx0 ) * ( EltVT . getSizeInBits ( ) / <NUM_LIT> ) ; else monotonic = false ; ++ EltsFromV2 ; } else if ( CurrElt != SrcElt ) { monotonic = false ; } ++ CurrElt ; } if ( rotate ) { if ( PrevElt > <NUM_LIT> && SrcElt < MaxElts ) { if ( ( PrevElt == SrcElt - <NUM_LIT> ) || ( PrevElt == MaxElts - <NUM_LIT> && SrcElt == <NUM_LIT> ) ) { PrevElt = SrcElt ; if ( SrcElt == <NUM_LIT> ) V0Elt = i ; } else { rotate = false ; } } else if ( i == <NUM_LIT> ) { PrevElt = SrcElt ; } else { rotate = false ; } } } if ( EltsFromV2 == <NUM_LIT> && monotonic ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( V2EltOffset , <STR_LIT> ) ) ; SDValue ShufMaskOp = DAG . getNode ( <STR_LIT> , dl , maskVT , Pointer ) ;

return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V2 , V1 , ShufMaskOp ) ;


<s> virtual unsigned getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { return <NUM_LIT> ;


<s> virtual unsigned getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const {


<s> assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; unsigned minSplatBits = EltVT . getSizeInBits ( ) ; if ( minSplatBits < <NUM_LIT> ) minSplatBits = <NUM_LIT> ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) || minSplatBits < SplatBitSize ) return SDValue ( ) ; uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; switch ( VT . getSimpleVT ( ) ) { default : cerr << <STR_LIT> << VT . getMVTString ( ) << <STR_LIT> ; abort ( ) ; case <STR_LIT> : { uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; break ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; break ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : {

SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ;


<s> MVT OpVT = Op . getValueType ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || OpVT == <STR_LIT> ) {

RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getFPTOSINT ( Op0VT , OpVT ) : RTLIB :: getFPTOUINT ( Op0VT , OpVT ) ;


<s> } if ( EltsFromV2 == <NUM_LIT> && monotonic ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue InitTempReg = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , VReg , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue ShufMaskOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getTargetConstant ( V2Elt , <STR_LIT> ) , DAG . getCopyFromReg ( InitTempReg , dl , VReg , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V2 , V1 , ShufMaskOp ) ; } else if ( rotate ) { int rotamt = ( MaxElts - V0Elt ) * EltVT . getSizeInBits ( ) / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , DAG . getConstant ( rotamt , <STR_LIT> ) ) ; } else { unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask ; for ( unsigned i = <NUM_LIT> , e = MaxElts ; i != e ; ++ i ) { unsigned SrcElt = SVN -> getMaskElt ( i ) < <NUM_LIT> ? <NUM_LIT> : SVN -> getMaskElt ( i ) ; for ( unsigned j = <NUM_LIT> ; j < BytesPerElement ; ++ j ) ResultMask . push_back ( DAG . getConstant ( SrcElt * BytesPerElement + j , <STR_LIT> ) ) ;


<s> } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; } else assert ( <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != MaxElts ; ++ i ) { if ( SVN -> getMaskElt ( i ) < <NUM_LIT> ) continue ; unsigned SrcElt = SVN -> getMaskElt ( i ) ; if ( monotonic ) { if ( SrcElt >= V2EltIdx0 ) { if ( <NUM_LIT> >= ( ++ EltsFromV2 ) ) { V2Elt = ( V2EltIdx0 - SrcElt ) << <NUM_LIT> ; } } else if ( CurrElt != SrcElt ) { monotonic = false ; } ++ CurrElt ; } if ( rotate ) { if ( PrevElt > <NUM_LIT> && SrcElt < MaxElts ) { if ( ( PrevElt == SrcElt - <NUM_LIT> ) || ( PrevElt == MaxElts - <NUM_LIT> && SrcElt == <NUM_LIT> ) ) { PrevElt = SrcElt ; if ( SrcElt == <NUM_LIT> ) V0Elt = i ; } else { rotate = false ; } } else if ( PrevElt == <NUM_LIT> ) { PrevElt = SrcElt ; } else { rotate = false ; } } } if ( EltsFromV2 == <NUM_LIT> && monotonic ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue InitTempReg = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , VReg , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue ShufMaskOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getTargetConstant ( V2Elt , <STR_LIT> ) , DAG . getCopyFromReg ( InitTempReg , dl , VReg , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V2 , V1 , ShufMaskOp ) ; } else if ( rotate ) { int rotamt = ( MaxElts - V0Elt ) * EltVT . getSizeInBits ( ) / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , DAG . getConstant ( rotamt , <STR_LIT> ) ) ;


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : retval = <STR_LIT> ; break ; case <STR_LIT> :


<s> if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ) return true ;

if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return true ;


<s> if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ) return true ; if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return true ;

if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ) return true ;


<s> unsigned ArgOffset = <ISA_LIT>FrameInfo :: minStackSize ( ) ; unsigned ArgRegIdx = <NUM_LIT> ; std :: vector < std :: pair < unsigned , SDValue > > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; ArgRegIdx != NumOps ; ++ ArgRegIdx ) { SDValue Arg = OutVals [ ArgRegIdx ] ; CCValAssign & VA = ArgLocs [ ArgRegIdx ] ; SDValue PtrOff = DAG . getConstant ( ArgOffset , StackPtr . getValueType ( ) ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , PtrOff ) ; switch ( Arg . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ArgRegIdx != NumArgRegs ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; ArgOffset += StackSlotSize ; } break ; } } unsigned NumStackBytes = ArgOffset - <ISA_LIT>FrameInfo :: minStackSize ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumStackBytes , true ) ) ; if ( ! MemOpChains . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned CallOpc = <STR_LIT> ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , CalleeVT ) ; if ( ! ST -> usingLargeMem ( ) ) { if ( GV -> isDeclaration ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; }

} else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


<s> for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned CallOpc = <STR_LIT> ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , CalleeVT ) ; if ( ! ST -> usingLargeMem ( ) ) { if ( GV -> isDeclaration ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue ExtSym = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) ) ; if ( ! ST -> usingLargeMem ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , ExtSym , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , ExtSym , Zero ) ; } } else if ( SDNode * Dest = isLSAAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ; } Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( CallOpc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;


<s> } if ( isVarArg ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumArgRegs = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( StackSlotSize , ArgOffset , true ) ) ; SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; unsigned VReg = MF . addLiveIn ( ArgRegs [ ArgRegIdx ] , & <STR_LIT> ) ; SDValue ArgVal = DAG . getRegister ( VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = Store . getOperand ( <NUM_LIT> ) ; MemOps . push_back ( Store ) ; ArgOffset += StackSlotSize ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ;


<s> basePtr = basePtr . getOperand ( <NUM_LIT> ) ; if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else if ( ( basePtr . getOpcode ( ) == <STR_LIT> ) || ( basePtr . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { int64_t rotamt = - pso ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getConstant ( rotamt , <STR_LIT> ) ; } else { int64_t rotamt = - pso ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( rotamt , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( - pso , PtrVT ) ) ; } SDValue low = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , lowMemPtr , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , <NUM_LIT> ) ; if ( alignment >= InVT . getSizeInBits ( ) / <NUM_LIT> ) { the_chain = low . getValue ( <NUM_LIT> ) ; result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , low . getValue ( <NUM_LIT> ) , rotate ) ; EVT vecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT , ( <NUM_LIT> / InVT . getSizeInBits ( ) ) ) ; result = DAG . getNode ( <STR_LIT> , dl , InVT , DAG . getNode ( <STR_LIT> , dl , vecVT , result ) ) ;


<s> SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( mask1 , <STR_LIT> ) , DAG . getConstant ( mask1 , <STR_LIT> ) , DAG . getConstant ( mask2 , <STR_LIT> ) , DAG . getConstant ( mask3 , <STR_LIT> ) ) ; MVT mvt = Op0VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue sraVal = DAG . getNode ( <STR_LIT> , dl , mvt , DAG . getNode ( <STR_LIT> , dl , mvt , Op0 , Op0 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue extended = SDValue ( DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op0VT , Op0 , DAG . getTargetConstant ( <STR_LIT> . getID ( ) , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue extShuffle = DAG . getNode ( <STR_LIT> , dl , mvt , extended , sraVal , shufMask ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , extShuffle ) ;


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = Op0 . getValueType ( ) . getSimpleVT ( ) ; assert ( ( OpVT == <STR_LIT> && ( Op0VT == <STR_LIT> || Op0VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned mask1 = <NUM_LIT> ; unsigned mask2 = Op0VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned mask3 = Op0VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( mask1 , <STR_LIT> ) , DAG . getConstant ( mask1 , <STR_LIT> ) , DAG . getConstant ( mask2 , <STR_LIT> ) , DAG . getConstant ( mask3 , <STR_LIT> ) ) ;


<s> prefslot_begin = <NUM_LIT> ; prefslot_end = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { prefslot_begin = <NUM_LIT> ; prefslot_end = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { prefslot_begin = <NUM_LIT> ; prefslot_end = <NUM_LIT> ; break ; } } assert ( prefslot_begin != - <NUM_LIT> && prefslot_end != - <NUM_LIT> && <STR_LIT> ) ; unsigned int ShufBytes [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned int mask_val ; if ( i <= prefslot_end ) { mask_val = ( ( i < prefslot_begin ) ? <NUM_LIT> : elt_byte + ( i - prefslot_begin ) ) ; ShufBytes [ i ] = mask_val ; } else ShufBytes [ i ] = ShufBytes [ i % ( prefslot_end + <NUM_LIT> ) ] ; } SDValue ShufMask [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < sizeof ( ShufMask ) / sizeof ( ShufMask [ <NUM_LIT> ] ) ; ++ i ) { unsigned bidx = i * <NUM_LIT> ; unsigned int bits = ( ( ShufBytes [ bidx ] << <NUM_LIT> ) | ( ShufBytes [ bidx + <NUM_LIT> ] << <NUM_LIT> ) | ( ShufBytes [ bidx + <NUM_LIT> ] << <NUM_LIT> ) | ShufBytes [ bidx + <NUM_LIT> ] ) ; ShufMask [ i ] = DAG . getConstant ( bits , <STR_LIT> ) ; } SDValue ShufMaskVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ShufMask [ <NUM_LIT> ] , sizeof ( ShufMask ) / sizeof ( ShufMask [ <NUM_LIT> ] ) ) ; retval = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , N . getValueType ( ) , N , N , ShufMaskVec ) ) ; } else { EVT VecVT = N . getValueType ( ) ; if ( ! VecVT . isSimple ( ) || ! VecVT . isVector ( ) || ! VecVT . is128BitVector ( ) ) { llvm_report_error ( <STR_LIT> <STR_LIT> ) ; } if ( Elt . getValueType ( ) != <STR_LIT> ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt ) ; APInt scaleFactor = APInt ( <NUM_LIT> , uint64_t ( <NUM_LIT> / N . getValueType ( ) . getVectorNumElements ( ) ) , false ) ; unsigned scaleShift = scaleFactor . logBase2 ( ) ; SDValue vecShift ; if ( scaleShift > <NUM_LIT> ) { Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt , DAG . getConstant ( scaleShift , <STR_LIT> ) ) ; } vecShift = DAG . getNode ( <STR_LIT> , dl , VecVT , N , Elt ) ; SDValue replicate ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_report_error ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : { SDValue factor = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;

replicate = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , factor , factor , factor , factor ) ;


<s> default : { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << ObjectVT . getEVTString ( ) ; llvm_report_error ( Msg . str ( ) ) ; } case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { VarArgsFrameIndex = MFI -> CreateFixedObject ( StackSlotSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; SDValue ArgVal = DAG . getRegister ( ArgRegs [ ArgRegIdx ] , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , NULL , <NUM_LIT> ) ; Chain = Store . getOperand ( <NUM_LIT> ) ;


<s> break ; } case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , * this ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerByteImmed ( Op , DAG ) ; case <STR_LIT> : if ( VT == <STR_LIT> ) return LowerI8Math ( Op , DAG , Opc , * this ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> :

return LowerSELECT_CC ( Op , DAG , * this ) ;


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;


<s> if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else { insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } alignLoadVec = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , SN -> getSrcValue ( ) , SN -> getSrcValueOffset ( ) , SN -> isVolatile ( ) , <NUM_LIT> ) ; the_chain = alignLoadVec . getValue ( <NUM_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( alignLoadVec ) ; SDValue theValue = SN -> getValue ( ) ; SDValue result ; if ( StVT != VT && ( theValue . getOpcode ( ) == <STR_LIT> || theValue . getOpcode ( ) == <STR_LIT> ) ) { theValue = theValue . getOperand ( <NUM_LIT> ) ; } if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { cerr << <STR_LIT> ; basePtr . getNode ( ) -> dump ( & DAG ) ; cerr << <STR_LIT> ; } SDValue insertEltOp = DAG . getNode ( <STR_LIT> , dl , vecVT , insertEltOffs ) ; SDValue vectorizeOp = DAG . getNode ( <STR_LIT> , dl , vecVT , theValue ) ; result = DAG . getNode ( <STR_LIT> , dl , vecVT , vectorizeOp , alignLoadVec , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , insertEltOp ) ) ;

result = DAG . getStore ( the_chain , dl , result , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , LN -> getAlignment ( ) ) ;


<s> } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } alignLoadVec = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , SN -> getSrcValue ( ) , SN -> getSrcValueOffset ( ) , SN -> isVolatile ( ) , <NUM_LIT> ) ; the_chain = alignLoadVec . getValue ( <NUM_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( alignLoadVec ) ; SDValue theValue = SN -> getValue ( ) ; SDValue result ; if ( StVT != VT && ( theValue . getOpcode ( ) == <STR_LIT> || theValue . getOpcode ( ) == <STR_LIT> ) ) { theValue = theValue . getOperand ( <NUM_LIT> ) ; } if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { cerr << <STR_LIT> ; basePtr . getNode ( ) -> dump ( & DAG ) ; cerr << <STR_LIT> ; } SDValue insertEltOp = DAG . getNode ( <STR_LIT> , dl , vecVT , insertEltOffs ) ; SDValue vectorizeOp = DAG . getNode ( <STR_LIT> , dl , vecVT , theValue ) ; result = DAG . getNode ( <STR_LIT> , dl , vecVT , vectorizeOp , alignLoadVec , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , insertEltOp ) ) ; result = DAG . getStore ( the_chain , dl , result , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , LN -> getAlignment ( ) ) ; if ( DebugFlag && isCurrentDebugType ( DEBUG_TYPE ) ) { const SDValue & currentRoot = DAG . getRoot ( ) ; DAG . setRoot ( result ) ; cerr << <STR_LIT> ; DAG . dump ( ) ; cerr << <STR_LIT> ; DAG . setRoot ( currentRoot ) ; } return result ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> cerr << <STR_LIT> ; cerr << <STR_LIT> << Opc << <STR_LIT> ; cerr << <STR_LIT> ; N -> dump ( ) ; abort ( ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : UsesLR ( false ) {


<s> void <ISA_LIT>FunctionInfo :: anchor ( ) {


<s> int getVarArgsFrameIndex ( ) const {


<s> void setUsesLR ( bool U ) { UsesLR = U ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : UsesLR ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) {


<s> Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; HasDotLocAndDotFile = true ;


<s> GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; HasDotLocAndDotFile = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: None ;


<s> PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; HasDotLocAndDotFile = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: None ; UsesELFSectionDirectiveForBSS = true ;


<s> void <ISA_LIT>LinuxMCAsmInfo :: anchor ( ) {


<s> Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ;


<s> CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; HasDotLocAndDotFile = true ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( Reloc :: Static , CM ) ; return X ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( <NUM_LIT> , Dst , Src ) ; return MAI ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>LinuxMCAsmInfo ( T , TT ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ;

MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( Reloc :: Static , CM , OL ) ; return X ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) {

MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ;


<s> Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X ;


<s> void LLVMInitializeCell<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( TheCell<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ;

TargetRegistry :: RegisterMCCodeGenInfo ( TheCell<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( TheCell<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ;

TargetRegistry :: RegisterMCRegInfo ( TheCell<ISA_LIT>Target , createCell<ISA_LIT>MCRegisterInfo ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>NopFillerPass ( <ISA_LIT>TargetMachine & tm ) { return new <ISA_LIT>NopFiller ( tm ) ;


<s> case <NUM_LIT> : retval = pseudo ; break ; case <NUM_LIT> : retval = odd ; break ; case <NUM_LIT> : retval = even ; break ; default : retval = pseudo ; assert ( false && <STR_LIT> ) ;


<s> <ISA_LIT>NopFiller :: <ISA_LIT>OpPlace <ISA_LIT>NopFiller :: getOpPlacement ( MachineInstr & instr ) { int sc = instr . getDesc ( ) . getSchedClass ( ) ; const InstrStage * stage = IID -> beginStage ( sc ) ; unsigned FUs = stage -> getUnits ( ) ; <ISA_LIT>OpPlace retval ; switch ( FUs ) { case <NUM_LIT> : retval = pseudo ; break ; case <NUM_LIT> : retval = odd ; break ;

case <NUM_LIT> : retval = even ; break ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> else if ( ! isEvenPlace && this_optype == even && next_optype == odd ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; DEBUG ( I -> dump ( ) ; ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; isEvenPlace = true ; } if ( this_optype != pseudo ) isEvenPlace = ! isEvenPlace ; } if ( ! isEvenPlace ) { MachineBasicBlock :: iterator J = MBB . end ( ) ; J -- ; if ( getOpPlacement ( * J ) == odd ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; BuildMI ( MBB , J , J -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; } else { J ++ ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ;

BuildMI ( MBB , J , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ;


<s> isEvenPlace = true ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) runOnMachineBasicBlock ( * FI ) ; return true ;


<s> for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) runOnMachineBasicBlock ( * FI ) ;


<s> Offset += MO . getImm ( ) + MFI -> getStackSize ( ) + <ISA_LIT>FrameInfo :: minStackSize ( ) ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; SPOp . ChangeToRegister ( <STR_LIT> , false ) ; if ( Offset > <ISA_LIT>FrameInfo :: maxFrameOffset ( ) || Offset < <ISA_LIT>FrameInfo :: minFrameOffset ( ) ) { errs ( ) << <STR_LIT> << Offset << <STR_LIT> ; } else { MO . ChangeToImmediate ( Offset ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize + LinkSlotOffset ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( FrameSize <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && FrameSize >= - ( <NUM_LIT> << <NUM_LIT> ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { std :: string msg ;


<s> } else if ( FrameSize <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && FrameSize >= - ( <NUM_LIT> << <NUM_LIT> ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << FrameSize ; llvm_report_error ( Msg . str ( ) ) ;


<s> void <ISA_LIT>RegisterInfo :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MF . getRegInfo ( ) . setPhysRegUnused ( <STR_LIT> ) ; MF . getRegInfo ( ) . setPhysRegUnused ( <STR_LIT> ) ;


<s> void <ISA_LIT>RegisterInfo :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MF . getRegInfo ( ) . setPhysRegUnused ( <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : assert ( false && <STR_LIT> ) ; }


<s> DebugLoc dl = II -> getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } MachineOperand & SPOp = MI . getOperand ( i ) ; int FrameIndex = SPOp . getIndex ( ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; unsigned OpNo = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) OpNo = <NUM_LIT> ; MachineOperand & MO = MI . getOperand ( OpNo ) ; Offset += MO . getImm ( ) + MFI -> getStackSize ( ) + <ISA_LIT>FrameLowering :: minStackSize ( ) ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ;

SPOp . ChangeToRegister ( <STR_LIT> , false ) ;


<s> DebugLoc dl = II -> getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } MachineOperand & SPOp = MI . getOperand ( i ) ; int FrameIndex = SPOp . getIndex ( ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; unsigned OpNo = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) OpNo = <NUM_LIT> ; MachineOperand & MO = MI . getOperand ( OpNo ) ; Offset += MO . getImm ( ) + MFI -> getStackSize ( ) + <ISA_LIT>FrameLowering :: minStackSize ( ) ;

assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & subtarget , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( subtarget ) , TII ( tii ) {


<s> unsigned AlignMask = Align - <NUM_LIT> ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ;

MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = II -> getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } MachineOperand & SPOp = MI . getOperand ( i ) ; int FrameIndex = SPOp . getIndex ( ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; unsigned OpNo = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) OpNo = <NUM_LIT> ; MachineOperand & MO = MI . getOperand ( OpNo ) ; Offset += MO . getImm ( ) + MFI -> getStackSize ( ) + <ISA_LIT>FrameInfo :: minStackSize ( ) ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; SPOp . ChangeToRegister ( <STR_LIT> , false ) ; if ( ( MI . getOpcode ( ) == <STR_LIT> && ! isInt < <NUM_LIT> > ( Offset ) ) || ! isInt < <NUM_LIT> > ( Offset ) ) { int newOpcode = convertDFormToXForm ( MI . getOpcode ( ) ) ; unsigned tmpReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , tmpReg ) . addImm ( Offset ) ; BuildMI ( MBB , II , dl , TII . get ( newOpcode ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( tmpReg , RegState :: Kill ) . addReg ( <STR_LIT> ) ; MBB . erase ( II ) ; } else { MO . ChangeToImmediate ( Offset ) ;


<s> if ( FrameSize > <NUM_LIT> || MFI -> hasCalls ( ) ) { FrameSize = FrameSize + <ISA_LIT>FrameInfo :: minStackSize ( ) ; if ( isInt < <NUM_LIT> > ( FrameSize + LinkSlotOffset ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize + LinkSlotOffset ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( FrameSize <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && FrameSize >= - ( <NUM_LIT> << <NUM_LIT> ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; }


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( FrameSize ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( isInt < <NUM_LIT> > ( FrameSize ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; } if ( hasDebugInfo ) { std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ;

MachineLocation SPDst ( MachineLocation :: VirtualFP ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; } if ( hasDebugInfo ) { std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , - FrameSize ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { int Offset = MFI -> getObjectOffset ( CSI [ I ] . getFrameIdx ( ) ) ; unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg == <STR_LIT> ) continue ;

MachineLocation CSDst ( MachineLocation :: VirtualFP , Offset ) ;


<s> assert ( RS && <STR_LIT> ) ; unsigned Reg = RS -> FindUnusedReg ( RC ) ; if ( Reg == <NUM_LIT> ) Reg = RS -> scavengeRegister ( RC , II , SPAdj ) ;


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ;


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull ( RegNum , <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <STR_LIT> ;


<s> MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ;

Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ;


<s> MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ; Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getNumArgRegs ( ) { return sizeof ( <ISA_LIT>_ArgRegs ) / sizeof ( <ISA_LIT>_ArgRegs [ <NUM_LIT> ] ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( unsigned Kind ) const {


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const {