<s> return ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ;


<s> Value = adjustFixupValue ( Fixup , Value , Ctx ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , <NUM_LIT> ) / <NUM_LIT> ;

assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ;


<s> <ISA_LIT>AsmBackend ( uint8_t OSABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( OSABI ) {


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const {

return create<ISA_LIT>ELFObjectWriter ( OSABI ) ;


<s> if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; switch ( ( unsigned ) Kind ) { case <STR_LIT> : { const static MCFixupKindInfo info { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return info ; } case <STR_LIT> : { const static MCFixupKindInfo info { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return info ; } case <STR_LIT> : { const static MCFixupKindInfo info { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } ; return info ; } case <STR_LIT> : { const static MCFixupKindInfo info { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } ; return info ; } default : llvm_unreachable ( <STR_LIT> ) ; }


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS . write ( <STR_LIT> , <NUM_LIT> ) ;


<s> ~ <ISA_LIT>AsmBackend ( ) override {


<s> IsConstant = true ; Imm = CE -> getValue ( ) ; } if ( IsConstant ) Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;

else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> IsConstant = RE -> evaluateAsConstant ( Imm ) ; } else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { IsConstant = true ; Imm = CE -> getValue ( ) ; } if ( IsConstant ) Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ; case Token : Tok = o . Tok ; break ; }


<s> } if ( isa < MCConstantExpr > ( Expr ) || isa < MCSymbolRefExpr > ( Expr ) ) return true ; const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ; if ( ! BE ) return false ; if ( ! isa < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ) return false ; if ( BE -> getOpcode ( ) != MCBinaryExpr :: Add && BE -> getOpcode ( ) != MCBinaryExpr :: Sub ) return false ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub && isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) ) return true ;

auto AddendExpr = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ;


<s> bool <ISA_LIT>AsmParser :: classifySymbolRef ( const MCExpr * Expr , <ISA_LIT>MCExpr :: VariantKind & Kind , int64_t & Addend ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; Addend = <NUM_LIT> ; if ( const <ISA_LIT>MCExpr * RE = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { Kind = RE -> getKind ( ) ; Expr = RE -> getSubExpr ( ) ; } if ( isa < MCConstantExpr > ( Expr ) || isa < MCSymbolRefExpr > ( Expr ) ) return true ; const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc S ) { auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ;


<s> bool evaluateConstantImm ( int64_t & Imm , <ISA_LIT>MCExpr :: VariantKind & VK ) const { const MCExpr * Val = getImm ( ) ; bool Ret = false ;

if ( auto * RE = dyn_cast < <ISA_LIT>MCExpr > ( Val ) ) {


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t Upper , Twine Msg = <STR_LIT> ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , Msg + <STR_LIT> + Twine ( Lower ) + <STR_LIT> + Twine ( Upper ) + <STR_LIT> ) ;


<s> int64_t getConstantImm ( ) const { const MCExpr * Val = getImm ( ) ; return static_cast < const MCConstantExpr * > ( Val ) -> getValue ( ) ;


return static_cast < const MCConstantExpr * > ( Val ) -> getValue ( ) ;


assert ( Kind == Immediate && <STR_LIT> ) ;


return getParser ( ) . getTok ( ) . getLoc ( ) ;


<s> unsigned getReg ( ) const override {

assert ( Kind == Register && <STR_LIT> ) ;


<s> SMLoc getStartLoc ( ) const override { return StartLoc ;


<s> StringRef getToken ( ) const { assert ( Kind == Token && <STR_LIT> ) ;


<s> if ( IsConstantImm ) IsValid = pred ( Imm ) ;

else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( IsConstantImm ) IsValid = pred ( Imm ) ; else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


return isBareImm ( isInt < <NUM_LIT> > ) ;


<s> if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ;


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ; else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;

return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;


<s> return isBareImm ( isInt < <NUM_LIT> > ) ;


<s> bool isSImm11Lsb0 ( ) const { return isBareImm ( isShiftedInt < <NUM_LIT> , <NUM_LIT> > ) ;


<s> bool isSImm6 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ;


<s> bool isUImm4 ( ) const { return isBareImm ( isUInt < <NUM_LIT> > ) ;


<s> return isBareImm ( isUInt < <NUM_LIT> > ) ;


<s> return isBareImm ( isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ) ;


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> unsigned Res = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( Res ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } <ISA_LIT>Operand & Operand = ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ; if ( ! Operand . isImm ( ) ) return Error ( Operand . getStartLoc ( ) , <STR_LIT> ) ; switch ( Res ) { case Match_InvalidSImm ## nbits : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , - ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) , ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) - <NUM_LIT> ) ; case Match_InvalidUImm ## nbits : \ return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> ) ; case Match_InvalidSImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , - ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) , ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) - <NUM_LIT> , \ <STR_LIT> ) ; case Match_InvalidUImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> , \ <STR_LIT> ) ; CASE_MATCH_INVALID_UIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_SIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_UIMM_LSB0 ( <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ;


<s> case Match_InvalidUImm ## nbits : \ return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> ) ; case Match_InvalidSImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , - ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) , ( <NUM_LIT> << ( nbits - <NUM_LIT> ) ) - <NUM_LIT> , \ <STR_LIT> ) ; case Match_InvalidUImm ## nbits ## Lsb0 : \ return generateImmOutOfRangeError ( \ Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << nbits ) - <NUM_LIT> , \ <STR_LIT> ) ; CASE_MATCH_INVALID_UIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_SIMM ( <NUM_LIT> ) ; CASE_MATCH_INVALID_UIMM_LSB0 ( <NUM_LIT> ) ; case Match_InvalidSImm6 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm10 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; }


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ;


<s> StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; break ; } case AsmToken :: Percent : {

return parseOperandWithModifier ( Operands ) ;


<s> } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ;


<s> return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLoc ( ) ) ) ; return MatchOperand_Success ;


<s> if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ;


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) return MatchOperand_NoMatch ; } getLexer ( ) . Lex ( ) ; Operands . push_back ( <STR_LIT> ( RegNo , S , E ) ) ;


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; unsigned RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <NUM_LIT> ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == <NUM_LIT> ) return MatchOperand_NoMatch ; } getLexer ( ) . Lex ( ) ; Operands . push_back ( <STR_LIT> ( RegNo , S , E ) ) ; } return MatchOperand_Success ;


<s> break ; case Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> bool Res = compressInst ( CInst , TmpInst , * TM . getMCSubtargetInfo ( ) , OutStreamer -> getContext ( ) ) ;

EmitToStreamer ( * OutStreamer , Res ? CInst : TmpInst ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( ! MO . isReg ( ) ) return true ; OS << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ; return false ; }

return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ;


<s> if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ;


<s> if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> if ( RegNo > sizeof ( GPRDecoderTable ) ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ;


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; addImplySP ( Inst , Address , Decoder ) ;

Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> return MCDisassembler :: Fail ; } uint32_t Inst ; DecodeStatus Result ; uint8_t is24bitInst = Bytes [ <NUM_LIT> ] & <NUM_LIT> ; if ( is24bitInst ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Inst = Bytes [ <NUM_LIT> ] | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable24 , MI , Inst , Address , this , STI ) ; Size = <NUM_LIT> ; } else { if ( Bytes . size ( ) < <NUM_LIT> ) {


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , true ) {


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> case FK_Data_2 : return ELF :: R_<ISA_LIT>_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_11 ;


<s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_2 : return ELF :: R_<ISA_LIT>_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO10 ; case <STR_LIT> :


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> } else if ( isInt < <NUM_LIT> > ( Val ) ) { unsigned Opc = <STR_LIT> ; bool isSub = Val < <NUM_LIT> ; if ( isSub ) { Val = - Val ; Opc = <STR_LIT> ; } unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm16 ( MBB , MBBI , DL , ScratchReg , Val , Flag ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg ) . setMIFlag ( Flag ) ; } else { report_fatal_error ( <STR_LIT> ) ; }


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( STI ) {


<s> if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; }


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ;

FrameSize = alignTo ( FrameSize , StackAlign ) ;


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override {


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ; MachineBasicBlock :: iterator LastFrameDestroy = MBBI ; std :: advance ( LastFrameDestroy , - MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) {


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; unsigned FPReg = getFPReg ( ) ; unsigned SPReg = getSPReg ( ) ; DebugLoc DL ;


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) {


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ;

if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) {


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ;

const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ;

RS -> addScavengingFrameIndex ( RegScavFI ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ;

const MCOperand & MO = MI -> getOperand ( OpNo ) ;


<s> } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == <NUM_LIT> && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) {

parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const {

assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ;


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ;

int NumOp = MI . getNumExplicitOperands ( ) ;


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ; int NumOp = MI . getNumExplicitOperands ( ) ; return MI . getOperand ( NumOp - <NUM_LIT> ) . getMBB ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : return get ( Opcode ) . getSize ( ) ; case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } }


<s> return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ;


<s> if ( ! <STR_LIT> . hasSubClassEq ( RC ) ) llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: movImm16 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi6 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo10 = SignExtend64 < <NUM_LIT> > ( Val ) ;

BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi6 ) . setMIFlag ( Flag ) ;


<s> void <ISA_LIT>InstrInfo :: movImm16 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ;

uint64_t Hi6 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ;


<s> assert ( LastInst . getDesc ( ) . isConditionalBranch ( ) && <STR_LIT> ) ;

Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; bool ShouldSwap = false ; switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; ShouldSwap = true ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; ShouldSwap = true ; break ; case <STR_LIT> : Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ) ; ShouldSwap = true ; break ; case <STR_LIT> :


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;

if ( ! <STR_LIT> . hasSubClassEq ( RC ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


<s> return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> StringRef getPassName ( ) const override {


<s> SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ;


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } if ( Node -> getOpcode ( ) == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } SelectCode ( Node ) ;


<s> if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; return true ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i :


<s> const TargetInstrInfo & TII = * BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end ( ) ) ;

TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; TailMBB -> splice ( TailMBB -> begin ( ) , HeadMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto CC = static_cast < <STR_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ;

BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond ) -> get ( ) ; normalizeSetCC ( LHS , RHS , CC ) ;

return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC , DL , <STR_LIT> ) , Dest ) ;


<s> EVT RegVT = VA . getLocVT ( ) ; if ( RegVT != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } const unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) == <STR_LIT> ) ; assert ( VA . getLocVT ( ) == <STR_LIT> ) ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgVal = DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } InVals . push_back ( ArgVal ) ; } return Chain ;


<s> SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; } return FrameAddr ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - <NUM_LIT> ;

SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;


<s> const GlobalValue * GV = N -> getGlobal ( ) ; int64_t Offset = N -> getOffset ( ) ; if ( isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , Offset , <STR_LIT> ) ;

SDValue GALo = DAG . getTargetGlobalAddress ( GV , DL , Ty , Offset , <STR_LIT> ) ;


<s> return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ;


<s> report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> :


<s> report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ;


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ;


<s> return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( RI . getRARegister ( ) , & <STR_LIT> ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , <STR_LIT> ) ;


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { int Off = - <NUM_LIT> ; SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( Off , DL , VT ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( RI . getRARegister ( ) , & <STR_LIT> ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , <STR_LIT> ) ;


<s> SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , VTs , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SetNE = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { CondV , Zero , SetNE , TrueV , FalseV } ;


<s> case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ( CC ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ;


<s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx , const MCInstrInfo & MCII ) : Ctx ( ctx ) , MCII ( MCII ) {


<s> return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII ) ;


<s> } unsigned Size = Desc . getSize ( ) ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits & <NUM_LIT> , <STR_LIT> ) ; OS . write ( ( Bits >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { expandHlt ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } unsigned Size = Desc . getSize ( ) ;


<s> MCInst TmpInst = MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;

uint16_t Bits = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> :


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; <STR_LIT> FixupKind = <STR_LIT> ; unsigned Offset = <NUM_LIT> ; if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ; case <STR_LIT> :


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> explicit <ISA_LIT>MCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) {


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Expr , Kind ) ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) {

return new ( Ctx ) <ISA_LIT>MCExpr ( Expr , Kind ) ;


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> if ( ! Value . isAbsolute ( ) ) return false ;

Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> case VK_<ISA_LIT>_LO : return SignExtend64 < <NUM_LIT> > ( Value ) ; case VK_<ISA_LIT>_HI :

return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ;


<s> return SignExtend64 < <NUM_LIT> > ( Value ) ; case VK_<ISA_LIT>_HI : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; }


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const {

return getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ; }


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { bool HasVariant = getKind ( ) != VK_<ISA_LIT>_None ; if ( HasVariant ) OS << '%' << getVariantKindName ( getKind ( ) ) << '(' ; Expr -> print ( OS , MAI ) ; if ( HasVariant ) OS << ')' ;


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ;

Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ;


<s> bool llvm :: Lower<ISA_LIT>MachineOperandToMCOperand ( const MachineOperand & MO , MCOperand & MCOp , const AsmPrinter & AP ) { switch ( MO . getType ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ;


<s> if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;

if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ME = <ISA_LIT>MCExpr :: create ( ME , Kind , Ctx ) ;


<s> break ; } const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( Kind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ME = <ISA_LIT>MCExpr :: create ( ME , Kind , Ctx ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) {


<s> return new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ;

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , FS ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { Target & T = getThe<ISA_LIT>Target ( ) ; TargetRegistry :: RegisterMCAsmInfo ( T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ;

TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( unsigned HwMode ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , HwMode ) {


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override {


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override {


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override {


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {


<s> bool enableMachineScheduler ( ) const override { return true ;


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override {


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ;

ParseSubtargetFeatures ( CPUName , FS ) ;


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> RegisterTarget < Triple :: cahp > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) {


<s> Target & getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: cahp > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> static StringRef computeDataLayout ( const Triple & TT ) {


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this , PM ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> static std :: string computeDataLayout ( const Triple & TT ) {


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;